1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 167 /* required last entry */ 168 PVID_END 169 }; 170 171 static pci_vendor_info_t igb_vendor_info_array[] = 172 { 173 /* Intel(R) PRO/1000 Network Connection - igb */ 174 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 /********************************************************************* 218 * Function prototypes 219 *********************************************************************/ 220 static void *em_register(device_t dev); 221 static void *igb_register(device_t dev); 222 static int em_if_attach_pre(if_ctx_t ctx); 223 static int em_if_attach_post(if_ctx_t ctx); 224 static int em_if_detach(if_ctx_t ctx); 225 static int em_if_shutdown(if_ctx_t ctx); 226 static int em_if_suspend(if_ctx_t ctx); 227 static int em_if_resume(if_ctx_t ctx); 228 229 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 230 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 231 static void em_if_queues_free(if_ctx_t ctx); 232 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 234 static void em_if_init(if_ctx_t ctx); 235 static void em_if_stop(if_ctx_t ctx); 236 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 237 static int em_if_media_change(if_ctx_t ctx); 238 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 239 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 240 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 241 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 242 243 static void em_identify_hardware(if_ctx_t ctx); 244 static int em_allocate_pci_resources(if_ctx_t ctx); 245 static void em_free_pci_resources(if_ctx_t ctx); 246 static void em_reset(if_ctx_t ctx); 247 static int em_setup_interface(if_ctx_t ctx); 248 static int em_setup_msix(if_ctx_t ctx); 249 250 static void em_initialize_transmit_unit(if_ctx_t ctx); 251 static void em_initialize_receive_unit(if_ctx_t ctx); 252 253 static void em_if_enable_intr(if_ctx_t ctx); 254 static void em_if_disable_intr(if_ctx_t ctx); 255 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 256 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 257 static void em_if_multi_set(if_ctx_t ctx); 258 static void em_if_update_admin_status(if_ctx_t ctx); 259 static void em_if_debug(if_ctx_t ctx); 260 static void em_update_stats_counters(struct adapter *); 261 static void em_add_hw_stats(struct adapter *adapter); 262 static int em_if_set_promisc(if_ctx_t ctx, int flags); 263 static void em_setup_vlan_hw_support(struct adapter *); 264 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 265 static void em_print_nvm_info(struct adapter *); 266 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 267 static int em_get_rs(SYSCTL_HANDLER_ARGS); 268 static void em_print_debug_info(struct adapter *); 269 static int em_is_valid_ether_addr(u8 *); 270 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 271 static void em_add_int_delay_sysctl(struct adapter *, const char *, 272 const char *, struct em_int_delay_info *, int, int); 273 /* Management and WOL Support */ 274 static void em_init_manageability(struct adapter *); 275 static void em_release_manageability(struct adapter *); 276 static void em_get_hw_control(struct adapter *); 277 static void em_release_hw_control(struct adapter *); 278 static void em_get_wakeup(if_ctx_t ctx); 279 static void em_enable_wakeup(if_ctx_t ctx); 280 static int em_enable_phy_wakeup(struct adapter *); 281 static void em_disable_aspm(struct adapter *); 282 283 int em_intr(void *arg); 284 static void em_disable_promisc(if_ctx_t ctx); 285 286 /* MSIX handlers */ 287 static int em_if_msix_intr_assign(if_ctx_t, int); 288 static int em_msix_link(void *); 289 static void em_handle_link(void *context); 290 291 static void em_enable_vectors_82574(if_ctx_t); 292 293 static void em_set_sysctl_value(struct adapter *, const char *, 294 const char *, int *, int); 295 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 296 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 297 static void em_if_led_func(if_ctx_t ctx, int onoff); 298 299 static int em_get_regs(SYSCTL_HANDLER_ARGS); 300 301 static void lem_smartspeed(struct adapter *adapter); 302 static void igb_configure_queues(struct adapter *adapter); 303 304 305 /********************************************************************* 306 * FreeBSD Device Interface Entry Points 307 *********************************************************************/ 308 static device_method_t em_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_register, em_register), 311 DEVMETHOD(device_probe, iflib_device_probe), 312 DEVMETHOD(device_attach, iflib_device_attach), 313 DEVMETHOD(device_detach, iflib_device_detach), 314 DEVMETHOD(device_shutdown, iflib_device_shutdown), 315 DEVMETHOD(device_suspend, iflib_device_suspend), 316 DEVMETHOD(device_resume, iflib_device_resume), 317 DEVMETHOD_END 318 }; 319 320 static device_method_t igb_methods[] = { 321 /* Device interface */ 322 DEVMETHOD(device_register, igb_register), 323 DEVMETHOD(device_probe, iflib_device_probe), 324 DEVMETHOD(device_attach, iflib_device_attach), 325 DEVMETHOD(device_detach, iflib_device_detach), 326 DEVMETHOD(device_shutdown, iflib_device_shutdown), 327 DEVMETHOD(device_suspend, iflib_device_suspend), 328 DEVMETHOD(device_resume, iflib_device_resume), 329 DEVMETHOD_END 330 }; 331 332 333 static driver_t em_driver = { 334 "em", em_methods, sizeof(struct adapter), 335 }; 336 337 static devclass_t em_devclass; 338 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 339 340 MODULE_DEPEND(em, pci, 1, 1, 1); 341 MODULE_DEPEND(em, ether, 1, 1, 1); 342 MODULE_DEPEND(em, iflib, 1, 1, 1); 343 344 static driver_t igb_driver = { 345 "igb", igb_methods, sizeof(struct adapter), 346 }; 347 348 static devclass_t igb_devclass; 349 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 350 351 MODULE_DEPEND(igb, pci, 1, 1, 1); 352 MODULE_DEPEND(igb, ether, 1, 1, 1); 353 MODULE_DEPEND(igb, iflib, 1, 1, 1); 354 355 356 static device_method_t em_if_methods[] = { 357 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 358 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 359 DEVMETHOD(ifdi_detach, em_if_detach), 360 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 361 DEVMETHOD(ifdi_suspend, em_if_suspend), 362 DEVMETHOD(ifdi_resume, em_if_resume), 363 DEVMETHOD(ifdi_init, em_if_init), 364 DEVMETHOD(ifdi_stop, em_if_stop), 365 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 366 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 367 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 368 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 369 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 370 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 371 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 372 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 373 DEVMETHOD(ifdi_media_status, em_if_media_status), 374 DEVMETHOD(ifdi_media_change, em_if_media_change), 375 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 376 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 377 DEVMETHOD(ifdi_timer, em_if_timer), 378 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 379 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 380 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 381 DEVMETHOD(ifdi_led_func, em_if_led_func), 382 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 383 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 384 DEVMETHOD(ifdi_debug, em_if_debug), 385 DEVMETHOD_END 386 }; 387 388 /* 389 * note that if (adapter->msix_mem) is replaced by: 390 * if (adapter->intr_type == IFLIB_INTR_MSIX) 391 */ 392 static driver_t em_if_driver = { 393 "em_if", em_if_methods, sizeof(struct adapter) 394 }; 395 396 /********************************************************************* 397 * Tunable default values. 398 *********************************************************************/ 399 400 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 401 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 402 #define M_TSO_LEN 66 403 404 #define MAX_INTS_PER_SEC 8000 405 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 406 407 /* Allow common code without TSO */ 408 #ifndef CSUM_TSO 409 #define CSUM_TSO 0 410 #endif 411 412 #define TSO_WORKAROUND 4 413 414 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 415 416 static int em_disable_crc_stripping = 0; 417 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 418 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 419 420 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 421 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 422 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 423 0, "Default transmit interrupt delay in usecs"); 424 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 425 0, "Default receive interrupt delay in usecs"); 426 427 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 428 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 429 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 430 &em_tx_abs_int_delay_dflt, 0, 431 "Default transmit interrupt delay limit in usecs"); 432 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 433 &em_rx_abs_int_delay_dflt, 0, 434 "Default receive interrupt delay limit in usecs"); 435 436 static int em_smart_pwr_down = FALSE; 437 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 438 0, "Set to true to leave smart power down enabled on newer adapters"); 439 440 /* Controls whether promiscuous also shows bad packets */ 441 static int em_debug_sbp = TRUE; 442 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 443 "Show bad packets in promiscuous mode"); 444 445 /* How many packets rxeof tries to clean at a time */ 446 static int em_rx_process_limit = 100; 447 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 448 &em_rx_process_limit, 0, 449 "Maximum number of received packets to process " 450 "at a time, -1 means unlimited"); 451 452 /* Energy efficient ethernet - default to OFF */ 453 static int eee_setting = 1; 454 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 455 "Enable Energy Efficient Ethernet"); 456 457 /* 458 ** Tuneable Interrupt rate 459 */ 460 static int em_max_interrupt_rate = 8000; 461 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 462 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 463 464 465 466 /* Global used in WOL setup with multiport cards */ 467 static int global_quad_port_a = 0; 468 469 extern struct if_txrx igb_txrx; 470 extern struct if_txrx em_txrx; 471 extern struct if_txrx lem_txrx; 472 473 static struct if_shared_ctx em_sctx_init = { 474 .isc_magic = IFLIB_MAGIC, 475 .isc_q_align = PAGE_SIZE, 476 .isc_tx_maxsize = EM_TSO_SIZE, 477 .isc_tx_maxsegsize = PAGE_SIZE, 478 .isc_rx_maxsize = MJUM9BYTES, 479 .isc_rx_nsegments = 1, 480 .isc_rx_maxsegsize = MJUM9BYTES, 481 .isc_nfl = 1, 482 .isc_nrxqs = 1, 483 .isc_ntxqs = 1, 484 .isc_admin_intrcnt = 1, 485 .isc_vendor_info = em_vendor_info_array, 486 .isc_driver_version = em_driver_version, 487 .isc_driver = &em_if_driver, 488 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 489 490 .isc_nrxd_min = {EM_MIN_RXD}, 491 .isc_ntxd_min = {EM_MIN_TXD}, 492 .isc_nrxd_max = {EM_MAX_RXD}, 493 .isc_ntxd_max = {EM_MAX_TXD}, 494 .isc_nrxd_default = {EM_DEFAULT_RXD}, 495 .isc_ntxd_default = {EM_DEFAULT_TXD}, 496 }; 497 498 if_shared_ctx_t em_sctx = &em_sctx_init; 499 500 501 static struct if_shared_ctx igb_sctx_init = { 502 .isc_magic = IFLIB_MAGIC, 503 .isc_q_align = PAGE_SIZE, 504 .isc_tx_maxsize = EM_TSO_SIZE, 505 .isc_tx_maxsegsize = PAGE_SIZE, 506 .isc_rx_maxsize = MJUM9BYTES, 507 .isc_rx_nsegments = 1, 508 .isc_rx_maxsegsize = MJUM9BYTES, 509 .isc_nfl = 1, 510 .isc_nrxqs = 1, 511 .isc_ntxqs = 1, 512 .isc_admin_intrcnt = 1, 513 .isc_vendor_info = igb_vendor_info_array, 514 .isc_driver_version = em_driver_version, 515 .isc_driver = &em_if_driver, 516 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 517 518 .isc_nrxd_min = {EM_MIN_RXD}, 519 .isc_ntxd_min = {EM_MIN_TXD}, 520 .isc_nrxd_max = {EM_MAX_RXD}, 521 .isc_ntxd_max = {EM_MAX_TXD}, 522 .isc_nrxd_default = {EM_DEFAULT_RXD}, 523 .isc_ntxd_default = {EM_DEFAULT_TXD}, 524 }; 525 526 if_shared_ctx_t igb_sctx = &igb_sctx_init; 527 528 /***************************************************************** 529 * 530 * Dump Registers 531 * 532 ****************************************************************/ 533 #define IGB_REGS_LEN 739 534 535 static int em_get_regs(SYSCTL_HANDLER_ARGS) 536 { 537 struct adapter *adapter = (struct adapter *)arg1; 538 struct e1000_hw *hw = &adapter->hw; 539 540 struct sbuf *sb; 541 u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT); 542 int rc; 543 544 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 545 546 rc = sysctl_wire_old_buffer(req, 0); 547 MPASS(rc == 0); 548 if (rc != 0) 549 return (rc); 550 551 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 552 MPASS(sb != NULL); 553 if (sb == NULL) 554 return (ENOMEM); 555 556 /* General Registers */ 557 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 558 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 559 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 560 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 561 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 562 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 563 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 564 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 565 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 566 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 567 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 568 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 569 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 570 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 571 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 572 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 573 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 574 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 575 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 576 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 577 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 578 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 579 580 sbuf_printf(sb, "General Registers\n"); 581 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 582 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 583 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 584 585 sbuf_printf(sb, "Interrupt Registers\n"); 586 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 587 588 sbuf_printf(sb, "RX Registers\n"); 589 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 590 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 591 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 592 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 593 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 594 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 595 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 596 597 sbuf_printf(sb, "TX Registers\n"); 598 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 599 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 600 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 601 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 602 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 603 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 604 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 605 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 606 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 607 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 608 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 609 610 #ifdef DUMP_DESCS 611 { 612 if_softc_ctx_t scctx = adapter->shared; 613 struct rx_ring *rxr = &rx_que->rxr; 614 struct tx_ring *txr = &tx_que->txr; 615 int ntxd = scctx->isc_ntxd[0]; 616 int nrxd = scctx->isc_nrxd[0]; 617 int j; 618 619 for (j = 0; j < nrxd; j++) { 620 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 621 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 622 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 623 } 624 625 for (j = 0; j < min(ntxd, 256); j++) { 626 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 627 628 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 629 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 630 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 631 632 } 633 } 634 #endif 635 636 rc = sbuf_finish(sb); 637 sbuf_delete(sb); 638 return(rc); 639 } 640 641 static void * 642 em_register(device_t dev) 643 { 644 return (em_sctx); 645 } 646 647 static void * 648 igb_register(device_t dev) 649 { 650 return (igb_sctx); 651 } 652 653 static int 654 em_set_num_queues(if_ctx_t ctx) 655 { 656 struct adapter *adapter = iflib_get_softc(ctx); 657 int maxqueues; 658 659 /* Sanity check based on HW */ 660 switch (adapter->hw.mac.type) { 661 case e1000_82576: 662 case e1000_82580: 663 case e1000_i350: 664 case e1000_i354: 665 maxqueues = 8; 666 break; 667 case e1000_i210: 668 case e1000_82575: 669 maxqueues = 4; 670 break; 671 case e1000_i211: 672 case e1000_82574: 673 maxqueues = 2; 674 break; 675 default: 676 maxqueues = 1; 677 break; 678 } 679 680 return (maxqueues); 681 } 682 683 684 #define EM_CAPS \ 685 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 686 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 687 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 688 689 #define IGB_CAPS \ 690 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 691 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 692 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 693 694 /********************************************************************* 695 * Device initialization routine 696 * 697 * The attach entry point is called when the driver is being loaded. 698 * This routine identifies the type of hardware, allocates all resources 699 * and initializes the hardware. 700 * 701 * return 0 on success, positive on failure 702 *********************************************************************/ 703 704 static int 705 em_if_attach_pre(if_ctx_t ctx) 706 { 707 struct adapter *adapter; 708 if_softc_ctx_t scctx; 709 device_t dev; 710 struct e1000_hw *hw; 711 int error = 0; 712 713 INIT_DEBUGOUT("em_if_attach_pre begin"); 714 dev = iflib_get_dev(ctx); 715 adapter = iflib_get_softc(ctx); 716 717 if (resource_disabled("em", device_get_unit(dev))) { 718 device_printf(dev, "Disabled by device hint\n"); 719 return (ENXIO); 720 } 721 722 adapter->ctx = ctx; 723 adapter->dev = adapter->osdep.dev = dev; 724 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 725 adapter->media = iflib_get_media(ctx); 726 hw = &adapter->hw; 727 728 adapter->tx_process_limit = scctx->isc_ntxd[0]; 729 730 /* SYSCTL stuff */ 731 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 732 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 733 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 734 em_sysctl_nvm_info, "I", "NVM Information"); 735 736 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 737 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 738 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 739 em_sysctl_debug_info, "I", "Debug Information"); 740 741 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 742 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 743 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 744 em_set_flowcntl, "I", "Flow Control"); 745 746 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 747 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 748 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 749 em_get_regs, "A", "Dump Registers"); 750 751 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 752 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 753 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 754 em_get_rs, "I", "Dump RS indexes"); 755 756 /* Determine hardware and mac info */ 757 em_identify_hardware(ctx); 758 759 /* Set isc_msix_bar */ 760 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 761 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 762 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 763 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 764 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 765 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 766 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 767 768 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 769 770 771 if (adapter->hw.mac.type >= igb_mac_min) { 772 int try_second_bar; 773 774 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 775 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 776 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 777 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 778 scctx->isc_txrx = &igb_txrx; 779 scctx->isc_capenable = IGB_CAPS; 780 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 781 | CSUM_IP6_UDP | CSUM_IP6_TCP; 782 if (adapter->hw.mac.type != e1000_82575) 783 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 784 785 /* 786 ** Some new devices, as with ixgbe, now may 787 ** use a different BAR, so we need to keep 788 ** track of which is used. 789 */ 790 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 791 if (try_second_bar == 0) 792 scctx->isc_msix_bar += 4; 793 794 } else if (adapter->hw.mac.type >= em_mac_min) { 795 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 796 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 797 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 798 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 799 scctx->isc_txrx = &em_txrx; 800 scctx->isc_capenable = EM_CAPS; 801 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 802 } else { 803 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 804 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 805 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 806 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 807 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 808 scctx->isc_txrx = &lem_txrx; 809 scctx->isc_capenable = EM_CAPS; 810 if (adapter->hw.mac.type < e1000_82543) 811 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 812 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 813 scctx->isc_msix_bar = 0; 814 } 815 816 /* Setup PCI resources */ 817 if (em_allocate_pci_resources(ctx)) { 818 device_printf(dev, "Allocation of PCI resources failed\n"); 819 error = ENXIO; 820 goto err_pci; 821 } 822 823 /* 824 ** For ICH8 and family we need to 825 ** map the flash memory, and this 826 ** must happen after the MAC is 827 ** identified 828 */ 829 if ((hw->mac.type == e1000_ich8lan) || 830 (hw->mac.type == e1000_ich9lan) || 831 (hw->mac.type == e1000_ich10lan) || 832 (hw->mac.type == e1000_pchlan) || 833 (hw->mac.type == e1000_pch2lan) || 834 (hw->mac.type == e1000_pch_lpt)) { 835 int rid = EM_BAR_TYPE_FLASH; 836 adapter->flash = bus_alloc_resource_any(dev, 837 SYS_RES_MEMORY, &rid, RF_ACTIVE); 838 if (adapter->flash == NULL) { 839 device_printf(dev, "Mapping of Flash failed\n"); 840 error = ENXIO; 841 goto err_pci; 842 } 843 /* This is used in the shared code */ 844 hw->flash_address = (u8 *)adapter->flash; 845 adapter->osdep.flash_bus_space_tag = 846 rman_get_bustag(adapter->flash); 847 adapter->osdep.flash_bus_space_handle = 848 rman_get_bushandle(adapter->flash); 849 } 850 /* 851 ** In the new SPT device flash is not a 852 ** separate BAR, rather it is also in BAR0, 853 ** so use the same tag and an offset handle for the 854 ** FLASH read/write macros in the shared code. 855 */ 856 else if (hw->mac.type == e1000_pch_spt) { 857 adapter->osdep.flash_bus_space_tag = 858 adapter->osdep.mem_bus_space_tag; 859 adapter->osdep.flash_bus_space_handle = 860 adapter->osdep.mem_bus_space_handle 861 + E1000_FLASH_BASE_ADDR; 862 } 863 864 /* Do Shared Code initialization */ 865 error = e1000_setup_init_funcs(hw, TRUE); 866 if (error) { 867 device_printf(dev, "Setup of Shared code failed, error %d\n", 868 error); 869 error = ENXIO; 870 goto err_pci; 871 } 872 873 em_setup_msix(ctx); 874 e1000_get_bus_info(hw); 875 876 /* Set up some sysctls for the tunable interrupt delays */ 877 em_add_int_delay_sysctl(adapter, "rx_int_delay", 878 "receive interrupt delay in usecs", &adapter->rx_int_delay, 879 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 880 em_add_int_delay_sysctl(adapter, "tx_int_delay", 881 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 882 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 883 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 884 "receive interrupt delay limit in usecs", 885 &adapter->rx_abs_int_delay, 886 E1000_REGISTER(hw, E1000_RADV), 887 em_rx_abs_int_delay_dflt); 888 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 889 "transmit interrupt delay limit in usecs", 890 &adapter->tx_abs_int_delay, 891 E1000_REGISTER(hw, E1000_TADV), 892 em_tx_abs_int_delay_dflt); 893 em_add_int_delay_sysctl(adapter, "itr", 894 "interrupt delay limit in usecs/4", 895 &adapter->tx_itr, 896 E1000_REGISTER(hw, E1000_ITR), 897 DEFAULT_ITR); 898 899 /* Sysctl for limiting the amount of work done in the taskqueue */ 900 em_set_sysctl_value(adapter, "rx_processing_limit", 901 "max number of rx packets to process", &adapter->rx_process_limit, 902 em_rx_process_limit); 903 904 hw->mac.autoneg = DO_AUTO_NEG; 905 hw->phy.autoneg_wait_to_complete = FALSE; 906 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 907 908 if (adapter->hw.mac.type < em_mac_min) { 909 e1000_init_script_state_82541(&adapter->hw, TRUE); 910 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 911 } 912 /* Copper options */ 913 if (hw->phy.media_type == e1000_media_type_copper) { 914 hw->phy.mdix = AUTO_ALL_MODES; 915 hw->phy.disable_polarity_correction = FALSE; 916 hw->phy.ms_type = EM_MASTER_SLAVE; 917 } 918 919 /* 920 * Set the frame limits assuming 921 * standard ethernet sized frames. 922 */ 923 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 924 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 925 926 /* 927 * This controls when hardware reports transmit completion 928 * status. 929 */ 930 hw->mac.report_tx_early = 1; 931 932 /* Allocate multicast array memory. */ 933 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 934 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 935 if (adapter->mta == NULL) { 936 device_printf(dev, "Can not allocate multicast setup array\n"); 937 error = ENOMEM; 938 goto err_late; 939 } 940 941 /* Check SOL/IDER usage */ 942 if (e1000_check_reset_block(hw)) 943 device_printf(dev, "PHY reset is blocked" 944 " due to SOL/IDER session.\n"); 945 946 /* Sysctl for setting Energy Efficient Ethernet */ 947 hw->dev_spec.ich8lan.eee_disable = eee_setting; 948 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 949 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 950 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 951 adapter, 0, em_sysctl_eee, "I", 952 "Disable Energy Efficient Ethernet"); 953 954 /* 955 ** Start from a known state, this is 956 ** important in reading the nvm and 957 ** mac from that. 958 */ 959 e1000_reset_hw(hw); 960 961 /* Make sure we have a good EEPROM before we read from it */ 962 if (e1000_validate_nvm_checksum(hw) < 0) { 963 /* 964 ** Some PCI-E parts fail the first check due to 965 ** the link being in sleep state, call it again, 966 ** if it fails a second time its a real issue. 967 */ 968 if (e1000_validate_nvm_checksum(hw) < 0) { 969 device_printf(dev, 970 "The EEPROM Checksum Is Not Valid\n"); 971 error = EIO; 972 goto err_late; 973 } 974 } 975 976 /* Copy the permanent MAC address out of the EEPROM */ 977 if (e1000_read_mac_addr(hw) < 0) { 978 device_printf(dev, "EEPROM read error while reading MAC" 979 " address\n"); 980 error = EIO; 981 goto err_late; 982 } 983 984 if (!em_is_valid_ether_addr(hw->mac.addr)) { 985 device_printf(dev, "Invalid MAC address\n"); 986 error = EIO; 987 goto err_late; 988 } 989 990 /* Disable ULP support */ 991 e1000_disable_ulp_lpt_lp(hw, TRUE); 992 993 /* 994 * Get Wake-on-Lan and Management info for later use 995 */ 996 em_get_wakeup(ctx); 997 998 iflib_set_mac(ctx, hw->mac.addr); 999 1000 return (0); 1001 1002 err_late: 1003 em_release_hw_control(adapter); 1004 err_pci: 1005 em_free_pci_resources(ctx); 1006 free(adapter->mta, M_DEVBUF); 1007 1008 return (error); 1009 } 1010 1011 static int 1012 em_if_attach_post(if_ctx_t ctx) 1013 { 1014 struct adapter *adapter = iflib_get_softc(ctx); 1015 struct e1000_hw *hw = &adapter->hw; 1016 int error = 0; 1017 1018 /* Setup OS specific network interface */ 1019 error = em_setup_interface(ctx); 1020 if (error != 0) { 1021 goto err_late; 1022 } 1023 1024 em_reset(ctx); 1025 1026 /* Initialize statistics */ 1027 em_update_stats_counters(adapter); 1028 hw->mac.get_link_status = 1; 1029 em_if_update_admin_status(ctx); 1030 em_add_hw_stats(adapter); 1031 1032 /* Non-AMT based hardware can now take control from firmware */ 1033 if (adapter->has_manage && !adapter->has_amt) 1034 em_get_hw_control(adapter); 1035 1036 INIT_DEBUGOUT("em_if_attach_post: end"); 1037 1038 return (error); 1039 1040 err_late: 1041 em_release_hw_control(adapter); 1042 em_free_pci_resources(ctx); 1043 em_if_queues_free(ctx); 1044 free(adapter->mta, M_DEVBUF); 1045 1046 return (error); 1047 } 1048 1049 /********************************************************************* 1050 * Device removal routine 1051 * 1052 * The detach entry point is called when the driver is being removed. 1053 * This routine stops the adapter and deallocates all the resources 1054 * that were allocated for driver operation. 1055 * 1056 * return 0 on success, positive on failure 1057 *********************************************************************/ 1058 1059 static int 1060 em_if_detach(if_ctx_t ctx) 1061 { 1062 struct adapter *adapter = iflib_get_softc(ctx); 1063 1064 INIT_DEBUGOUT("em_detach: begin"); 1065 1066 e1000_phy_hw_reset(&adapter->hw); 1067 1068 em_release_manageability(adapter); 1069 em_release_hw_control(adapter); 1070 em_free_pci_resources(ctx); 1071 1072 return (0); 1073 } 1074 1075 /********************************************************************* 1076 * 1077 * Shutdown entry point 1078 * 1079 **********************************************************************/ 1080 1081 static int 1082 em_if_shutdown(if_ctx_t ctx) 1083 { 1084 return em_if_suspend(ctx); 1085 } 1086 1087 /* 1088 * Suspend/resume device methods. 1089 */ 1090 static int 1091 em_if_suspend(if_ctx_t ctx) 1092 { 1093 struct adapter *adapter = iflib_get_softc(ctx); 1094 1095 em_release_manageability(adapter); 1096 em_release_hw_control(adapter); 1097 em_enable_wakeup(ctx); 1098 return (0); 1099 } 1100 1101 static int 1102 em_if_resume(if_ctx_t ctx) 1103 { 1104 struct adapter *adapter = iflib_get_softc(ctx); 1105 1106 if (adapter->hw.mac.type == e1000_pch2lan) 1107 e1000_resume_workarounds_pchlan(&adapter->hw); 1108 em_if_init(ctx); 1109 em_init_manageability(adapter); 1110 1111 return(0); 1112 } 1113 1114 static int 1115 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1116 { 1117 int max_frame_size; 1118 struct adapter *adapter = iflib_get_softc(ctx); 1119 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1120 1121 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1122 1123 switch (adapter->hw.mac.type) { 1124 case e1000_82571: 1125 case e1000_82572: 1126 case e1000_ich9lan: 1127 case e1000_ich10lan: 1128 case e1000_pch2lan: 1129 case e1000_pch_lpt: 1130 case e1000_pch_spt: 1131 case e1000_82574: 1132 case e1000_82583: 1133 case e1000_80003es2lan: 1134 /* 9K Jumbo Frame size */ 1135 max_frame_size = 9234; 1136 break; 1137 case e1000_pchlan: 1138 max_frame_size = 4096; 1139 break; 1140 case e1000_82542: 1141 case e1000_ich8lan: 1142 /* Adapters that do not support jumbo frames */ 1143 max_frame_size = ETHER_MAX_LEN; 1144 break; 1145 default: 1146 if (adapter->hw.mac.type >= igb_mac_min) 1147 max_frame_size = 9234; 1148 else /* lem */ 1149 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1150 } 1151 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1152 return (EINVAL); 1153 } 1154 1155 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1156 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1157 return (0); 1158 } 1159 1160 /********************************************************************* 1161 * Init entry point 1162 * 1163 * This routine is used in two ways. It is used by the stack as 1164 * init entry point in network interface structure. It is also used 1165 * by the driver as a hw/sw initialization routine to get to a 1166 * consistent state. 1167 * 1168 * return 0 on success, positive on failure 1169 **********************************************************************/ 1170 1171 static void 1172 em_if_init(if_ctx_t ctx) 1173 { 1174 struct adapter *adapter = iflib_get_softc(ctx); 1175 struct ifnet *ifp = iflib_get_ifp(ctx); 1176 struct em_tx_queue *tx_que; 1177 int i; 1178 INIT_DEBUGOUT("em_if_init: begin"); 1179 1180 /* Get the latest mac address, User can use a LAA */ 1181 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1182 ETHER_ADDR_LEN); 1183 1184 /* Put the address into the Receive Address Array */ 1185 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1186 1187 /* 1188 * With the 82571 adapter, RAR[0] may be overwritten 1189 * when the other port is reset, we make a duplicate 1190 * in RAR[14] for that eventuality, this assures 1191 * the interface continues to function. 1192 */ 1193 if (adapter->hw.mac.type == e1000_82571) { 1194 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1195 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1196 E1000_RAR_ENTRIES - 1); 1197 } 1198 1199 1200 /* Initialize the hardware */ 1201 em_reset(ctx); 1202 em_if_update_admin_status(ctx); 1203 1204 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1205 struct tx_ring *txr = &tx_que->txr; 1206 1207 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1208 } 1209 1210 /* Setup VLAN support, basic and offload if available */ 1211 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1212 1213 /* Clear bad data from Rx FIFOs */ 1214 if (adapter->hw.mac.type >= igb_mac_min) 1215 e1000_rx_fifo_flush_82575(&adapter->hw); 1216 1217 /* Configure for OS presence */ 1218 em_init_manageability(adapter); 1219 1220 /* Prepare transmit descriptors and buffers */ 1221 em_initialize_transmit_unit(ctx); 1222 1223 /* Setup Multicast table */ 1224 em_if_multi_set(ctx); 1225 1226 /* 1227 * Figure out the desired mbuf 1228 * pool for doing jumbos 1229 */ 1230 if (adapter->hw.mac.max_frame_size <= 2048) 1231 adapter->rx_mbuf_sz = MCLBYTES; 1232 #ifndef CONTIGMALLOC_WORKS 1233 else 1234 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1235 #else 1236 else if (adapter->hw.mac.max_frame_size <= 4096) 1237 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1238 else 1239 adapter->rx_mbuf_sz = MJUM9BYTES; 1240 #endif 1241 em_initialize_receive_unit(ctx); 1242 1243 /* Use real VLAN Filter support? */ 1244 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1245 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1246 /* Use real VLAN Filter support */ 1247 em_setup_vlan_hw_support(adapter); 1248 else { 1249 u32 ctrl; 1250 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1251 ctrl |= E1000_CTRL_VME; 1252 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1253 } 1254 } 1255 1256 /* Don't lose promiscuous settings */ 1257 em_if_set_promisc(ctx, IFF_PROMISC); 1258 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1259 1260 /* MSI/X configuration for 82574 */ 1261 if (adapter->hw.mac.type == e1000_82574) { 1262 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1263 1264 tmp |= E1000_CTRL_EXT_PBA_CLR; 1265 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1266 /* Set the IVAR - interrupt vector routing. */ 1267 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1268 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1269 igb_configure_queues(adapter); 1270 1271 /* this clears any pending interrupts */ 1272 E1000_READ_REG(&adapter->hw, E1000_ICR); 1273 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1274 1275 /* AMT based hardware can now take control from firmware */ 1276 if (adapter->has_manage && adapter->has_amt) 1277 em_get_hw_control(adapter); 1278 1279 /* Set Energy Efficient Ethernet */ 1280 if (adapter->hw.mac.type >= igb_mac_min && 1281 adapter->hw.phy.media_type == e1000_media_type_copper) { 1282 if (adapter->hw.mac.type == e1000_i354) 1283 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1284 else 1285 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1286 } 1287 } 1288 1289 /********************************************************************* 1290 * 1291 * Fast Legacy/MSI Combined Interrupt Service routine 1292 * 1293 *********************************************************************/ 1294 int 1295 em_intr(void *arg) 1296 { 1297 struct adapter *adapter = arg; 1298 if_ctx_t ctx = adapter->ctx; 1299 u32 reg_icr; 1300 1301 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1302 1303 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1304 goto skip_stray; 1305 /* Hot eject? */ 1306 if (reg_icr == 0xffffffff) 1307 return FILTER_STRAY; 1308 1309 /* Definitely not our interrupt. */ 1310 if (reg_icr == 0x0) 1311 return FILTER_STRAY; 1312 1313 /* 1314 * Starting with the 82571 chip, bit 31 should be used to 1315 * determine whether the interrupt belongs to us. 1316 */ 1317 if (adapter->hw.mac.type >= e1000_82571 && 1318 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1319 return FILTER_STRAY; 1320 1321 skip_stray: 1322 /* Link status change */ 1323 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1324 adapter->hw.mac.get_link_status = 1; 1325 iflib_admin_intr_deferred(ctx); 1326 } 1327 1328 if (reg_icr & E1000_ICR_RXO) 1329 adapter->rx_overruns++; 1330 1331 return (FILTER_SCHEDULE_THREAD); 1332 } 1333 1334 static void 1335 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1336 { 1337 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1338 } 1339 1340 static void 1341 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1342 { 1343 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1344 } 1345 1346 static void 1347 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1348 { 1349 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1350 } 1351 1352 static void 1353 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1354 { 1355 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1356 } 1357 1358 static int 1359 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1360 { 1361 struct adapter *adapter = iflib_get_softc(ctx); 1362 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1363 1364 if (adapter->hw.mac.type >= igb_mac_min) 1365 igb_rx_enable_queue(adapter, rxq); 1366 else 1367 em_rx_enable_queue(adapter, rxq); 1368 return (0); 1369 } 1370 1371 static int 1372 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1373 { 1374 struct adapter *adapter = iflib_get_softc(ctx); 1375 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1376 1377 if (adapter->hw.mac.type >= igb_mac_min) 1378 igb_tx_enable_queue(adapter, txq); 1379 else 1380 em_tx_enable_queue(adapter, txq); 1381 return (0); 1382 } 1383 1384 /********************************************************************* 1385 * 1386 * MSIX RX Interrupt Service routine 1387 * 1388 **********************************************************************/ 1389 static int 1390 em_msix_que(void *arg) 1391 { 1392 struct em_rx_queue *que = arg; 1393 1394 ++que->irqs; 1395 1396 return (FILTER_SCHEDULE_THREAD); 1397 } 1398 1399 /********************************************************************* 1400 * 1401 * MSIX Link Fast Interrupt Service routine 1402 * 1403 **********************************************************************/ 1404 static int 1405 em_msix_link(void *arg) 1406 { 1407 struct adapter *adapter = arg; 1408 u32 reg_icr; 1409 1410 ++adapter->link_irq; 1411 MPASS(adapter->hw.back != NULL); 1412 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1413 1414 if (reg_icr & E1000_ICR_RXO) 1415 adapter->rx_overruns++; 1416 1417 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1418 em_handle_link(adapter->ctx); 1419 } else { 1420 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1421 EM_MSIX_LINK | E1000_IMS_LSC); 1422 if (adapter->hw.mac.type >= igb_mac_min) 1423 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1424 } 1425 1426 /* 1427 * Because we must read the ICR for this interrupt 1428 * it may clear other causes using autoclear, for 1429 * this reason we simply create a soft interrupt 1430 * for all these vectors. 1431 */ 1432 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1433 E1000_WRITE_REG(&adapter->hw, 1434 E1000_ICS, adapter->ims); 1435 } 1436 1437 return (FILTER_HANDLED); 1438 } 1439 1440 static void 1441 em_handle_link(void *context) 1442 { 1443 if_ctx_t ctx = context; 1444 struct adapter *adapter = iflib_get_softc(ctx); 1445 1446 adapter->hw.mac.get_link_status = 1; 1447 iflib_admin_intr_deferred(ctx); 1448 } 1449 1450 1451 /********************************************************************* 1452 * 1453 * Media Ioctl callback 1454 * 1455 * This routine is called whenever the user queries the status of 1456 * the interface using ifconfig. 1457 * 1458 **********************************************************************/ 1459 static void 1460 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1461 { 1462 struct adapter *adapter = iflib_get_softc(ctx); 1463 u_char fiber_type = IFM_1000_SX; 1464 1465 INIT_DEBUGOUT("em_if_media_status: begin"); 1466 1467 iflib_admin_intr_deferred(ctx); 1468 1469 ifmr->ifm_status = IFM_AVALID; 1470 ifmr->ifm_active = IFM_ETHER; 1471 1472 if (!adapter->link_active) { 1473 return; 1474 } 1475 1476 ifmr->ifm_status |= IFM_ACTIVE; 1477 1478 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1479 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1480 if (adapter->hw.mac.type == e1000_82545) 1481 fiber_type = IFM_1000_LX; 1482 ifmr->ifm_active |= fiber_type | IFM_FDX; 1483 } else { 1484 switch (adapter->link_speed) { 1485 case 10: 1486 ifmr->ifm_active |= IFM_10_T; 1487 break; 1488 case 100: 1489 ifmr->ifm_active |= IFM_100_TX; 1490 break; 1491 case 1000: 1492 ifmr->ifm_active |= IFM_1000_T; 1493 break; 1494 } 1495 if (adapter->link_duplex == FULL_DUPLEX) 1496 ifmr->ifm_active |= IFM_FDX; 1497 else 1498 ifmr->ifm_active |= IFM_HDX; 1499 } 1500 } 1501 1502 /********************************************************************* 1503 * 1504 * Media Ioctl callback 1505 * 1506 * This routine is called when the user changes speed/duplex using 1507 * media/mediopt option with ifconfig. 1508 * 1509 **********************************************************************/ 1510 static int 1511 em_if_media_change(if_ctx_t ctx) 1512 { 1513 struct adapter *adapter = iflib_get_softc(ctx); 1514 struct ifmedia *ifm = iflib_get_media(ctx); 1515 1516 INIT_DEBUGOUT("em_if_media_change: begin"); 1517 1518 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1519 return (EINVAL); 1520 1521 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1522 case IFM_AUTO: 1523 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1524 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1525 break; 1526 case IFM_1000_LX: 1527 case IFM_1000_SX: 1528 case IFM_1000_T: 1529 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1530 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1531 break; 1532 case IFM_100_TX: 1533 adapter->hw.mac.autoneg = FALSE; 1534 adapter->hw.phy.autoneg_advertised = 0; 1535 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1536 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1537 else 1538 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1539 break; 1540 case IFM_10_T: 1541 adapter->hw.mac.autoneg = FALSE; 1542 adapter->hw.phy.autoneg_advertised = 0; 1543 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1544 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1545 else 1546 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1547 break; 1548 default: 1549 device_printf(adapter->dev, "Unsupported media type\n"); 1550 } 1551 1552 em_if_init(ctx); 1553 1554 return (0); 1555 } 1556 1557 static int 1558 em_if_set_promisc(if_ctx_t ctx, int flags) 1559 { 1560 struct adapter *adapter = iflib_get_softc(ctx); 1561 u32 reg_rctl; 1562 1563 em_disable_promisc(ctx); 1564 1565 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1566 1567 if (flags & IFF_PROMISC) { 1568 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1569 /* Turn this on if you want to see bad packets */ 1570 if (em_debug_sbp) 1571 reg_rctl |= E1000_RCTL_SBP; 1572 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1573 } else if (flags & IFF_ALLMULTI) { 1574 reg_rctl |= E1000_RCTL_MPE; 1575 reg_rctl &= ~E1000_RCTL_UPE; 1576 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1577 } 1578 return (0); 1579 } 1580 1581 static void 1582 em_disable_promisc(if_ctx_t ctx) 1583 { 1584 struct adapter *adapter = iflib_get_softc(ctx); 1585 struct ifnet *ifp = iflib_get_ifp(ctx); 1586 u32 reg_rctl; 1587 int mcnt = 0; 1588 1589 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1590 reg_rctl &= (~E1000_RCTL_UPE); 1591 if (if_getflags(ifp) & IFF_ALLMULTI) 1592 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1593 else 1594 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1595 /* Don't disable if in MAX groups */ 1596 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1597 reg_rctl &= (~E1000_RCTL_MPE); 1598 reg_rctl &= (~E1000_RCTL_SBP); 1599 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1600 } 1601 1602 1603 /********************************************************************* 1604 * Multicast Update 1605 * 1606 * This routine is called whenever multicast address list is updated. 1607 * 1608 **********************************************************************/ 1609 1610 static void 1611 em_if_multi_set(if_ctx_t ctx) 1612 { 1613 struct adapter *adapter = iflib_get_softc(ctx); 1614 struct ifnet *ifp = iflib_get_ifp(ctx); 1615 u32 reg_rctl = 0; 1616 u8 *mta; /* Multicast array memory */ 1617 int mcnt = 0; 1618 1619 IOCTL_DEBUGOUT("em_set_multi: begin"); 1620 1621 mta = adapter->mta; 1622 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1623 1624 if (adapter->hw.mac.type == e1000_82542 && 1625 adapter->hw.revision_id == E1000_REVISION_2) { 1626 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1627 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1628 e1000_pci_clear_mwi(&adapter->hw); 1629 reg_rctl |= E1000_RCTL_RST; 1630 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1631 msec_delay(5); 1632 } 1633 1634 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1635 1636 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1637 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1638 reg_rctl |= E1000_RCTL_MPE; 1639 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1640 } else 1641 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1642 1643 if (adapter->hw.mac.type == e1000_82542 && 1644 adapter->hw.revision_id == E1000_REVISION_2) { 1645 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1646 reg_rctl &= ~E1000_RCTL_RST; 1647 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1648 msec_delay(5); 1649 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1650 e1000_pci_set_mwi(&adapter->hw); 1651 } 1652 } 1653 1654 1655 /********************************************************************* 1656 * Timer routine 1657 * 1658 * This routine checks for link status and updates statistics. 1659 * 1660 **********************************************************************/ 1661 1662 static void 1663 em_if_timer(if_ctx_t ctx, uint16_t qid) 1664 { 1665 struct adapter *adapter = iflib_get_softc(ctx); 1666 struct em_rx_queue *que; 1667 int i; 1668 int trigger = 0; 1669 1670 if (qid != 0) 1671 return; 1672 1673 em_if_update_admin_status(ctx); 1674 em_update_stats_counters(adapter); 1675 1676 /* Reset LAA into RAR[0] on 82571 */ 1677 if ((adapter->hw.mac.type == e1000_82571) && 1678 e1000_get_laa_state_82571(&adapter->hw)) 1679 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1680 1681 if (adapter->hw.mac.type < em_mac_min) 1682 lem_smartspeed(adapter); 1683 1684 /* Mask to use in the irq trigger */ 1685 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1686 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1687 trigger |= que->eims; 1688 } else { 1689 trigger = E1000_ICS_RXDMT0; 1690 } 1691 } 1692 1693 1694 static void 1695 em_if_update_admin_status(if_ctx_t ctx) 1696 { 1697 struct adapter *adapter = iflib_get_softc(ctx); 1698 struct e1000_hw *hw = &adapter->hw; 1699 struct ifnet *ifp = iflib_get_ifp(ctx); 1700 device_t dev = iflib_get_dev(ctx); 1701 u32 link_check = 0; 1702 1703 /* Get the cached link value or read phy for real */ 1704 switch (hw->phy.media_type) { 1705 case e1000_media_type_copper: 1706 if (hw->mac.get_link_status) { 1707 if (hw->mac.type == e1000_pch_spt) 1708 msec_delay(50); 1709 /* Do the work to read phy */ 1710 e1000_check_for_link(hw); 1711 link_check = !hw->mac.get_link_status; 1712 if (link_check) /* ESB2 fix */ 1713 e1000_cfg_on_link_up(hw); 1714 } else { 1715 link_check = TRUE; 1716 } 1717 break; 1718 case e1000_media_type_fiber: 1719 e1000_check_for_link(hw); 1720 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1721 E1000_STATUS_LU); 1722 break; 1723 case e1000_media_type_internal_serdes: 1724 e1000_check_for_link(hw); 1725 link_check = adapter->hw.mac.serdes_has_link; 1726 break; 1727 default: 1728 case e1000_media_type_unknown: 1729 break; 1730 } 1731 1732 /* Now check for a transition */ 1733 if (link_check && (adapter->link_active == 0)) { 1734 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1735 &adapter->link_duplex); 1736 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1737 if ((adapter->link_speed != SPEED_1000) && 1738 ((hw->mac.type == e1000_82571) || 1739 (hw->mac.type == e1000_82572))) { 1740 int tarc0; 1741 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1742 tarc0 &= ~TARC_SPEED_MODE_BIT; 1743 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1744 } 1745 if (bootverbose) 1746 device_printf(dev, "Link is up %d Mbps %s\n", 1747 adapter->link_speed, 1748 ((adapter->link_duplex == FULL_DUPLEX) ? 1749 "Full Duplex" : "Half Duplex")); 1750 adapter->link_active = 1; 1751 adapter->smartspeed = 0; 1752 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1753 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1754 printf("Link state changed to up\n"); 1755 } else if (!link_check && (adapter->link_active == 1)) { 1756 if_setbaudrate(ifp, 0); 1757 adapter->link_speed = 0; 1758 adapter->link_duplex = 0; 1759 if (bootverbose) 1760 device_printf(dev, "Link is Down\n"); 1761 adapter->link_active = 0; 1762 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1763 printf("link state changed to down\n"); 1764 } 1765 1766 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1767 } 1768 1769 /********************************************************************* 1770 * 1771 * This routine disables all traffic on the adapter by issuing a 1772 * global reset on the MAC and deallocates TX/RX buffers. 1773 * 1774 * This routine should always be called with BOTH the CORE 1775 * and TX locks. 1776 **********************************************************************/ 1777 1778 static void 1779 em_if_stop(if_ctx_t ctx) 1780 { 1781 struct adapter *adapter = iflib_get_softc(ctx); 1782 1783 INIT_DEBUGOUT("em_stop: begin"); 1784 1785 e1000_reset_hw(&adapter->hw); 1786 if (adapter->hw.mac.type >= e1000_82544) 1787 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1788 1789 e1000_led_off(&adapter->hw); 1790 e1000_cleanup_led(&adapter->hw); 1791 } 1792 1793 1794 /********************************************************************* 1795 * 1796 * Determine hardware revision. 1797 * 1798 **********************************************************************/ 1799 static void 1800 em_identify_hardware(if_ctx_t ctx) 1801 { 1802 device_t dev = iflib_get_dev(ctx); 1803 struct adapter *adapter = iflib_get_softc(ctx); 1804 1805 /* Make sure our PCI config space has the necessary stuff set */ 1806 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1807 1808 /* Save off the information about this board */ 1809 adapter->hw.vendor_id = pci_get_vendor(dev); 1810 adapter->hw.device_id = pci_get_device(dev); 1811 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1812 adapter->hw.subsystem_vendor_id = 1813 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1814 adapter->hw.subsystem_device_id = 1815 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1816 1817 /* Do Shared Code Init and Setup */ 1818 if (e1000_set_mac_type(&adapter->hw)) { 1819 device_printf(dev, "Setup init failure\n"); 1820 return; 1821 } 1822 } 1823 1824 static int 1825 em_allocate_pci_resources(if_ctx_t ctx) 1826 { 1827 struct adapter *adapter = iflib_get_softc(ctx); 1828 device_t dev = iflib_get_dev(ctx); 1829 int rid, val; 1830 1831 rid = PCIR_BAR(0); 1832 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1833 &rid, RF_ACTIVE); 1834 if (adapter->memory == NULL) { 1835 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1836 return (ENXIO); 1837 } 1838 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1839 adapter->osdep.mem_bus_space_handle = 1840 rman_get_bushandle(adapter->memory); 1841 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1842 1843 /* Only older adapters use IO mapping */ 1844 if (adapter->hw.mac.type < em_mac_min && 1845 adapter->hw.mac.type > e1000_82543) { 1846 /* Figure our where our IO BAR is ? */ 1847 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1848 val = pci_read_config(dev, rid, 4); 1849 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1850 adapter->io_rid = rid; 1851 break; 1852 } 1853 rid += 4; 1854 /* check for 64bit BAR */ 1855 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1856 rid += 4; 1857 } 1858 if (rid >= PCIR_CIS) { 1859 device_printf(dev, "Unable to locate IO BAR\n"); 1860 return (ENXIO); 1861 } 1862 adapter->ioport = bus_alloc_resource_any(dev, 1863 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1864 if (adapter->ioport == NULL) { 1865 device_printf(dev, "Unable to allocate bus resource: " 1866 "ioport\n"); 1867 return (ENXIO); 1868 } 1869 adapter->hw.io_base = 0; 1870 adapter->osdep.io_bus_space_tag = 1871 rman_get_bustag(adapter->ioport); 1872 adapter->osdep.io_bus_space_handle = 1873 rman_get_bushandle(adapter->ioport); 1874 } 1875 1876 adapter->hw.back = &adapter->osdep; 1877 1878 return (0); 1879 } 1880 1881 /********************************************************************* 1882 * 1883 * Setup the MSIX Interrupt handlers 1884 * 1885 **********************************************************************/ 1886 static int 1887 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1888 { 1889 struct adapter *adapter = iflib_get_softc(ctx); 1890 struct em_rx_queue *rx_que = adapter->rx_queues; 1891 struct em_tx_queue *tx_que = adapter->tx_queues; 1892 int error, rid, i, vector = 0, rx_vectors; 1893 char buf[16]; 1894 1895 /* First set up ring resources */ 1896 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1897 rid = vector + 1; 1898 snprintf(buf, sizeof(buf), "rxq%d", i); 1899 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1900 if (error) { 1901 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1902 adapter->rx_num_queues = i + 1; 1903 goto fail; 1904 } 1905 1906 rx_que->msix = vector; 1907 1908 /* 1909 * Set the bit to enable interrupt 1910 * in E1000_IMS -- bits 20 and 21 1911 * are for RX0 and RX1, note this has 1912 * NOTHING to do with the MSIX vector 1913 */ 1914 if (adapter->hw.mac.type == e1000_82574) { 1915 rx_que->eims = 1 << (20 + i); 1916 adapter->ims |= rx_que->eims; 1917 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1918 } else if (adapter->hw.mac.type == e1000_82575) 1919 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1920 else 1921 rx_que->eims = 1 << vector; 1922 } 1923 rx_vectors = vector; 1924 1925 vector = 0; 1926 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1927 rid = vector + 1; 1928 snprintf(buf, sizeof(buf), "txq%d", i); 1929 tx_que = &adapter->tx_queues[i]; 1930 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1931 1932 tx_que->msix = (vector % adapter->tx_num_queues); 1933 1934 /* 1935 * Set the bit to enable interrupt 1936 * in E1000_IMS -- bits 22 and 23 1937 * are for TX0 and TX1, note this has 1938 * NOTHING to do with the MSIX vector 1939 */ 1940 if (adapter->hw.mac.type == e1000_82574) { 1941 tx_que->eims = 1 << (22 + i); 1942 adapter->ims |= tx_que->eims; 1943 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1944 } if (adapter->hw.mac.type == e1000_82575) 1945 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1946 else 1947 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1948 } 1949 1950 /* Link interrupt */ 1951 rid = rx_vectors + 1; 1952 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1953 1954 if (error) { 1955 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1956 goto fail; 1957 } 1958 adapter->linkvec = rx_vectors; 1959 if (adapter->hw.mac.type < igb_mac_min) { 1960 adapter->ivars |= (8 | rx_vectors) << 16; 1961 adapter->ivars |= 0x80000000; 1962 } 1963 return (0); 1964 fail: 1965 iflib_irq_free(ctx, &adapter->irq); 1966 rx_que = adapter->rx_queues; 1967 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1968 iflib_irq_free(ctx, &rx_que->que_irq); 1969 return (error); 1970 } 1971 1972 static void 1973 igb_configure_queues(struct adapter *adapter) 1974 { 1975 struct e1000_hw *hw = &adapter->hw; 1976 struct em_rx_queue *rx_que; 1977 struct em_tx_queue *tx_que; 1978 u32 tmp, ivar = 0, newitr = 0; 1979 1980 /* First turn on RSS capability */ 1981 if (adapter->hw.mac.type != e1000_82575) 1982 E1000_WRITE_REG(hw, E1000_GPIE, 1983 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 1984 E1000_GPIE_PBA | E1000_GPIE_NSICR); 1985 1986 /* Turn on MSIX */ 1987 switch (adapter->hw.mac.type) { 1988 case e1000_82580: 1989 case e1000_i350: 1990 case e1000_i354: 1991 case e1000_i210: 1992 case e1000_i211: 1993 case e1000_vfadapt: 1994 case e1000_vfadapt_i350: 1995 /* RX entries */ 1996 for (int i = 0; i < adapter->rx_num_queues; i++) { 1997 u32 index = i >> 1; 1998 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1999 rx_que = &adapter->rx_queues[i]; 2000 if (i & 1) { 2001 ivar &= 0xFF00FFFF; 2002 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2003 } else { 2004 ivar &= 0xFFFFFF00; 2005 ivar |= rx_que->msix | E1000_IVAR_VALID; 2006 } 2007 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2008 } 2009 /* TX entries */ 2010 for (int i = 0; i < adapter->tx_num_queues; i++) { 2011 u32 index = i >> 1; 2012 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2013 tx_que = &adapter->tx_queues[i]; 2014 if (i & 1) { 2015 ivar &= 0x00FFFFFF; 2016 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2017 } else { 2018 ivar &= 0xFFFF00FF; 2019 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2020 } 2021 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2022 adapter->que_mask |= tx_que->eims; 2023 } 2024 2025 /* And for the link interrupt */ 2026 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2027 adapter->link_mask = 1 << adapter->linkvec; 2028 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2029 break; 2030 case e1000_82576: 2031 /* RX entries */ 2032 for (int i = 0; i < adapter->rx_num_queues; i++) { 2033 u32 index = i & 0x7; /* Each IVAR has two entries */ 2034 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2035 rx_que = &adapter->rx_queues[i]; 2036 if (i < 8) { 2037 ivar &= 0xFFFFFF00; 2038 ivar |= rx_que->msix | E1000_IVAR_VALID; 2039 } else { 2040 ivar &= 0xFF00FFFF; 2041 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2042 } 2043 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2044 adapter->que_mask |= rx_que->eims; 2045 } 2046 /* TX entries */ 2047 for (int i = 0; i < adapter->tx_num_queues; i++) { 2048 u32 index = i & 0x7; /* Each IVAR has two entries */ 2049 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2050 tx_que = &adapter->tx_queues[i]; 2051 if (i < 8) { 2052 ivar &= 0xFFFF00FF; 2053 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2054 } else { 2055 ivar &= 0x00FFFFFF; 2056 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2057 } 2058 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2059 adapter->que_mask |= tx_que->eims; 2060 } 2061 2062 /* And for the link interrupt */ 2063 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2064 adapter->link_mask = 1 << adapter->linkvec; 2065 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2066 break; 2067 2068 case e1000_82575: 2069 /* enable MSI-X support*/ 2070 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2071 tmp |= E1000_CTRL_EXT_PBA_CLR; 2072 /* Auto-Mask interrupts upon ICR read. */ 2073 tmp |= E1000_CTRL_EXT_EIAME; 2074 tmp |= E1000_CTRL_EXT_IRCA; 2075 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2076 2077 /* Queues */ 2078 for (int i = 0; i < adapter->rx_num_queues; i++) { 2079 rx_que = &adapter->rx_queues[i]; 2080 tmp = E1000_EICR_RX_QUEUE0 << i; 2081 tmp |= E1000_EICR_TX_QUEUE0 << i; 2082 rx_que->eims = tmp; 2083 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2084 i, rx_que->eims); 2085 adapter->que_mask |= rx_que->eims; 2086 } 2087 2088 /* Link */ 2089 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2090 E1000_EIMS_OTHER); 2091 adapter->link_mask |= E1000_EIMS_OTHER; 2092 default: 2093 break; 2094 } 2095 2096 /* Set the starting interrupt rate */ 2097 if (em_max_interrupt_rate > 0) 2098 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2099 2100 if (hw->mac.type == e1000_82575) 2101 newitr |= newitr << 16; 2102 else 2103 newitr |= E1000_EITR_CNT_IGNR; 2104 2105 for (int i = 0; i < adapter->rx_num_queues; i++) { 2106 rx_que = &adapter->rx_queues[i]; 2107 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2108 } 2109 2110 return; 2111 } 2112 2113 static void 2114 em_free_pci_resources(if_ctx_t ctx) 2115 { 2116 struct adapter *adapter = iflib_get_softc(ctx); 2117 struct em_rx_queue *que = adapter->rx_queues; 2118 device_t dev = iflib_get_dev(ctx); 2119 2120 /* Release all msix queue resources */ 2121 if (adapter->intr_type == IFLIB_INTR_MSIX) 2122 iflib_irq_free(ctx, &adapter->irq); 2123 2124 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2125 iflib_irq_free(ctx, &que->que_irq); 2126 } 2127 2128 /* First release all the interrupt resources */ 2129 if (adapter->memory != NULL) { 2130 bus_release_resource(dev, SYS_RES_MEMORY, 2131 PCIR_BAR(0), adapter->memory); 2132 adapter->memory = NULL; 2133 } 2134 2135 if (adapter->flash != NULL) { 2136 bus_release_resource(dev, SYS_RES_MEMORY, 2137 EM_FLASH, adapter->flash); 2138 adapter->flash = NULL; 2139 } 2140 if (adapter->ioport != NULL) 2141 bus_release_resource(dev, SYS_RES_IOPORT, 2142 adapter->io_rid, adapter->ioport); 2143 } 2144 2145 /* Setup MSI or MSI/X */ 2146 static int 2147 em_setup_msix(if_ctx_t ctx) 2148 { 2149 struct adapter *adapter = iflib_get_softc(ctx); 2150 2151 if (adapter->hw.mac.type == e1000_82574) { 2152 em_enable_vectors_82574(ctx); 2153 } 2154 return (0); 2155 } 2156 2157 /********************************************************************* 2158 * 2159 * Initialize the hardware to a configuration 2160 * as specified by the adapter structure. 2161 * 2162 **********************************************************************/ 2163 2164 static void 2165 lem_smartspeed(struct adapter *adapter) 2166 { 2167 u16 phy_tmp; 2168 2169 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2170 adapter->hw.mac.autoneg == 0 || 2171 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2172 return; 2173 2174 if (adapter->smartspeed == 0) { 2175 /* If Master/Slave config fault is asserted twice, 2176 * we assume back-to-back */ 2177 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2178 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2179 return; 2180 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2181 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2182 e1000_read_phy_reg(&adapter->hw, 2183 PHY_1000T_CTRL, &phy_tmp); 2184 if(phy_tmp & CR_1000T_MS_ENABLE) { 2185 phy_tmp &= ~CR_1000T_MS_ENABLE; 2186 e1000_write_phy_reg(&adapter->hw, 2187 PHY_1000T_CTRL, phy_tmp); 2188 adapter->smartspeed++; 2189 if(adapter->hw.mac.autoneg && 2190 !e1000_copper_link_autoneg(&adapter->hw) && 2191 !e1000_read_phy_reg(&adapter->hw, 2192 PHY_CONTROL, &phy_tmp)) { 2193 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2194 MII_CR_RESTART_AUTO_NEG); 2195 e1000_write_phy_reg(&adapter->hw, 2196 PHY_CONTROL, phy_tmp); 2197 } 2198 } 2199 } 2200 return; 2201 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2202 /* If still no link, perhaps using 2/3 pair cable */ 2203 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2204 phy_tmp |= CR_1000T_MS_ENABLE; 2205 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2206 if(adapter->hw.mac.autoneg && 2207 !e1000_copper_link_autoneg(&adapter->hw) && 2208 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2209 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2210 MII_CR_RESTART_AUTO_NEG); 2211 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2212 } 2213 } 2214 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2215 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2216 adapter->smartspeed = 0; 2217 } 2218 2219 2220 static void 2221 em_reset(if_ctx_t ctx) 2222 { 2223 device_t dev = iflib_get_dev(ctx); 2224 struct adapter *adapter = iflib_get_softc(ctx); 2225 struct ifnet *ifp = iflib_get_ifp(ctx); 2226 struct e1000_hw *hw = &adapter->hw; 2227 u16 rx_buffer_size; 2228 u32 pba; 2229 2230 INIT_DEBUGOUT("em_reset: begin"); 2231 2232 /* Set up smart power down as default off on newer adapters. */ 2233 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2234 hw->mac.type == e1000_82572)) { 2235 u16 phy_tmp = 0; 2236 2237 /* Speed up time to link by disabling smart power down. */ 2238 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2239 phy_tmp &= ~IGP02E1000_PM_SPD; 2240 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2241 } 2242 2243 /* 2244 * Packet Buffer Allocation (PBA) 2245 * Writing PBA sets the receive portion of the buffer 2246 * the remainder is used for the transmit buffer. 2247 */ 2248 switch (hw->mac.type) { 2249 /* Total Packet Buffer on these is 48K */ 2250 case e1000_82571: 2251 case e1000_82572: 2252 case e1000_80003es2lan: 2253 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2254 break; 2255 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2256 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2257 break; 2258 case e1000_82574: 2259 case e1000_82583: 2260 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2261 break; 2262 case e1000_ich8lan: 2263 pba = E1000_PBA_8K; 2264 break; 2265 case e1000_ich9lan: 2266 case e1000_ich10lan: 2267 /* Boost Receive side for jumbo frames */ 2268 if (adapter->hw.mac.max_frame_size > 4096) 2269 pba = E1000_PBA_14K; 2270 else 2271 pba = E1000_PBA_10K; 2272 break; 2273 case e1000_pchlan: 2274 case e1000_pch2lan: 2275 case e1000_pch_lpt: 2276 case e1000_pch_spt: 2277 pba = E1000_PBA_26K; 2278 break; 2279 case e1000_82575: 2280 pba = E1000_PBA_32K; 2281 break; 2282 case e1000_82576: 2283 case e1000_vfadapt: 2284 pba = E1000_READ_REG(hw, E1000_RXPBS); 2285 pba &= E1000_RXPBS_SIZE_MASK_82576; 2286 break; 2287 case e1000_82580: 2288 case e1000_i350: 2289 case e1000_i354: 2290 case e1000_vfadapt_i350: 2291 pba = E1000_READ_REG(hw, E1000_RXPBS); 2292 pba = e1000_rxpbs_adjust_82580(pba); 2293 break; 2294 case e1000_i210: 2295 case e1000_i211: 2296 pba = E1000_PBA_34K; 2297 break; 2298 default: 2299 if (adapter->hw.mac.max_frame_size > 8192) 2300 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2301 else 2302 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2303 } 2304 2305 /* Special needs in case of Jumbo frames */ 2306 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2307 u32 tx_space, min_tx, min_rx; 2308 pba = E1000_READ_REG(hw, E1000_PBA); 2309 tx_space = pba >> 16; 2310 pba &= 0xffff; 2311 min_tx = (adapter->hw.mac.max_frame_size + 2312 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2313 min_tx = roundup2(min_tx, 1024); 2314 min_tx >>= 10; 2315 min_rx = adapter->hw.mac.max_frame_size; 2316 min_rx = roundup2(min_rx, 1024); 2317 min_rx >>= 10; 2318 if (tx_space < min_tx && 2319 ((min_tx - tx_space) < pba)) { 2320 pba = pba - (min_tx - tx_space); 2321 /* 2322 * if short on rx space, rx wins 2323 * and must trump tx adjustment 2324 */ 2325 if (pba < min_rx) 2326 pba = min_rx; 2327 } 2328 E1000_WRITE_REG(hw, E1000_PBA, pba); 2329 } 2330 2331 if (hw->mac.type < igb_mac_min) 2332 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2333 2334 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2335 2336 /* 2337 * These parameters control the automatic generation (Tx) and 2338 * response (Rx) to Ethernet PAUSE frames. 2339 * - High water mark should allow for at least two frames to be 2340 * received after sending an XOFF. 2341 * - Low water mark works best when it is very near the high water mark. 2342 * This allows the receiver to restart by sending XON when it has 2343 * drained a bit. Here we use an arbitrary value of 1500 which will 2344 * restart after one full frame is pulled from the buffer. There 2345 * could be several smaller frames in the buffer and if so they will 2346 * not trigger the XON until their total number reduces the buffer 2347 * by 1500. 2348 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2349 */ 2350 rx_buffer_size = (pba & 0xffff) << 10; 2351 hw->fc.high_water = rx_buffer_size - 2352 roundup2(adapter->hw.mac.max_frame_size, 1024); 2353 hw->fc.low_water = hw->fc.high_water - 1500; 2354 2355 if (adapter->fc) /* locally set flow control value? */ 2356 hw->fc.requested_mode = adapter->fc; 2357 else 2358 hw->fc.requested_mode = e1000_fc_full; 2359 2360 if (hw->mac.type == e1000_80003es2lan) 2361 hw->fc.pause_time = 0xFFFF; 2362 else 2363 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2364 2365 hw->fc.send_xon = TRUE; 2366 2367 /* Device specific overrides/settings */ 2368 switch (hw->mac.type) { 2369 case e1000_pchlan: 2370 /* Workaround: no TX flow ctrl for PCH */ 2371 hw->fc.requested_mode = e1000_fc_rx_pause; 2372 hw->fc.pause_time = 0xFFFF; /* override */ 2373 if (if_getmtu(ifp) > ETHERMTU) { 2374 hw->fc.high_water = 0x3500; 2375 hw->fc.low_water = 0x1500; 2376 } else { 2377 hw->fc.high_water = 0x5000; 2378 hw->fc.low_water = 0x3000; 2379 } 2380 hw->fc.refresh_time = 0x1000; 2381 break; 2382 case e1000_pch2lan: 2383 case e1000_pch_lpt: 2384 case e1000_pch_spt: 2385 hw->fc.high_water = 0x5C20; 2386 hw->fc.low_water = 0x5048; 2387 hw->fc.pause_time = 0x0650; 2388 hw->fc.refresh_time = 0x0400; 2389 /* Jumbos need adjusted PBA */ 2390 if (if_getmtu(ifp) > ETHERMTU) 2391 E1000_WRITE_REG(hw, E1000_PBA, 12); 2392 else 2393 E1000_WRITE_REG(hw, E1000_PBA, 26); 2394 break; 2395 case e1000_82575: 2396 case e1000_82576: 2397 /* 8-byte granularity */ 2398 hw->fc.low_water = hw->fc.high_water - 8; 2399 break; 2400 case e1000_82580: 2401 case e1000_i350: 2402 case e1000_i354: 2403 case e1000_i210: 2404 case e1000_i211: 2405 case e1000_vfadapt: 2406 case e1000_vfadapt_i350: 2407 /* 16-byte granularity */ 2408 hw->fc.low_water = hw->fc.high_water - 16; 2409 break; 2410 case e1000_ich9lan: 2411 case e1000_ich10lan: 2412 if (if_getmtu(ifp) > ETHERMTU) { 2413 hw->fc.high_water = 0x2800; 2414 hw->fc.low_water = hw->fc.high_water - 8; 2415 break; 2416 } 2417 /* else fall thru */ 2418 default: 2419 if (hw->mac.type == e1000_80003es2lan) 2420 hw->fc.pause_time = 0xFFFF; 2421 break; 2422 } 2423 2424 /* Issue a global reset */ 2425 e1000_reset_hw(hw); 2426 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2427 em_disable_aspm(adapter); 2428 /* and a re-init */ 2429 if (e1000_init_hw(hw) < 0) { 2430 device_printf(dev, "Hardware Initialization Failed\n"); 2431 return; 2432 } 2433 2434 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2435 e1000_get_phy_info(hw); 2436 e1000_check_for_link(hw); 2437 } 2438 2439 #define RSSKEYLEN 10 2440 static void 2441 em_initialize_rss_mapping(struct adapter *adapter) 2442 { 2443 uint8_t rss_key[4 * RSSKEYLEN]; 2444 uint32_t reta = 0; 2445 struct e1000_hw *hw = &adapter->hw; 2446 int i; 2447 2448 /* 2449 * Configure RSS key 2450 */ 2451 arc4rand(rss_key, sizeof(rss_key), 0); 2452 for (i = 0; i < RSSKEYLEN; ++i) { 2453 uint32_t rssrk = 0; 2454 2455 rssrk = EM_RSSRK_VAL(rss_key, i); 2456 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2457 } 2458 2459 /* 2460 * Configure RSS redirect table in following fashion: 2461 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2462 */ 2463 for (i = 0; i < sizeof(reta); ++i) { 2464 uint32_t q; 2465 2466 q = (i % adapter->rx_num_queues) << 7; 2467 reta |= q << (8 * i); 2468 } 2469 2470 for (i = 0; i < 32; ++i) 2471 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2472 2473 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2474 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2475 E1000_MRQC_RSS_FIELD_IPV4 | 2476 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2477 E1000_MRQC_RSS_FIELD_IPV6_EX | 2478 E1000_MRQC_RSS_FIELD_IPV6); 2479 2480 } 2481 2482 static void 2483 igb_initialize_rss_mapping(struct adapter *adapter) 2484 { 2485 struct e1000_hw *hw = &adapter->hw; 2486 int i; 2487 int queue_id; 2488 u32 reta; 2489 u32 rss_key[10], mrqc, shift = 0; 2490 2491 /* XXX? */ 2492 if (adapter->hw.mac.type == e1000_82575) 2493 shift = 6; 2494 2495 /* 2496 * The redirection table controls which destination 2497 * queue each bucket redirects traffic to. 2498 * Each DWORD represents four queues, with the LSB 2499 * being the first queue in the DWORD. 2500 * 2501 * This just allocates buckets to queues using round-robin 2502 * allocation. 2503 * 2504 * NOTE: It Just Happens to line up with the default 2505 * RSS allocation method. 2506 */ 2507 2508 /* Warning FM follows */ 2509 reta = 0; 2510 for (i = 0; i < 128; i++) { 2511 #ifdef RSS 2512 queue_id = rss_get_indirection_to_bucket(i); 2513 /* 2514 * If we have more queues than buckets, we'll 2515 * end up mapping buckets to a subset of the 2516 * queues. 2517 * 2518 * If we have more buckets than queues, we'll 2519 * end up instead assigning multiple buckets 2520 * to queues. 2521 * 2522 * Both are suboptimal, but we need to handle 2523 * the case so we don't go out of bounds 2524 * indexing arrays and such. 2525 */ 2526 queue_id = queue_id % adapter->rx_num_queues; 2527 #else 2528 queue_id = (i % adapter->rx_num_queues); 2529 #endif 2530 /* Adjust if required */ 2531 queue_id = queue_id << shift; 2532 2533 /* 2534 * The low 8 bits are for hash value (n+0); 2535 * The next 8 bits are for hash value (n+1), etc. 2536 */ 2537 reta = reta >> 8; 2538 reta = reta | ( ((uint32_t) queue_id) << 24); 2539 if ((i & 3) == 3) { 2540 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2541 reta = 0; 2542 } 2543 } 2544 2545 /* Now fill in hash table */ 2546 2547 /* 2548 * MRQC: Multiple Receive Queues Command 2549 * Set queuing to RSS control, number depends on the device. 2550 */ 2551 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2552 2553 #ifdef RSS 2554 /* XXX ew typecasting */ 2555 rss_getkey((uint8_t *) &rss_key); 2556 #else 2557 arc4rand(&rss_key, sizeof(rss_key), 0); 2558 #endif 2559 for (i = 0; i < 10; i++) 2560 E1000_WRITE_REG_ARRAY(hw, 2561 E1000_RSSRK(0), i, rss_key[i]); 2562 2563 /* 2564 * Configure the RSS fields to hash upon. 2565 */ 2566 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2567 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2568 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2569 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2570 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2571 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2572 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2573 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2574 2575 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2576 } 2577 2578 /********************************************************************* 2579 * 2580 * Setup networking device structure and register an interface. 2581 * 2582 **********************************************************************/ 2583 static int 2584 em_setup_interface(if_ctx_t ctx) 2585 { 2586 struct ifnet *ifp = iflib_get_ifp(ctx); 2587 struct adapter *adapter = iflib_get_softc(ctx); 2588 if_softc_ctx_t scctx = adapter->shared; 2589 uint64_t cap = 0; 2590 2591 INIT_DEBUGOUT("em_setup_interface: begin"); 2592 2593 /* TSO parameters */ 2594 if_sethwtsomax(ifp, IP_MAXPACKET); 2595 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2596 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2597 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2598 2599 /* Single Queue */ 2600 if (adapter->tx_num_queues == 1) { 2601 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2602 if_setsendqready(ifp); 2603 } 2604 2605 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2606 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2607 2608 /* 2609 * Tell the upper layer(s) we 2610 * support full VLAN capability 2611 */ 2612 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2613 if_setcapabilitiesbit(ifp, cap, 0); 2614 2615 /* 2616 * Don't turn this on by default, if vlans are 2617 * created on another pseudo device (eg. lagg) 2618 * then vlan events are not passed thru, breaking 2619 * operation, but with HW FILTER off it works. If 2620 * using vlans directly on the em driver you can 2621 * enable this and get full hardware tag filtering. 2622 */ 2623 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2624 2625 /* Enable only WOL MAGIC by default */ 2626 if (adapter->wol) { 2627 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2628 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2629 } else { 2630 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2631 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2632 } 2633 2634 /* 2635 * Specify the media types supported by this adapter and register 2636 * callbacks to update media and link information 2637 */ 2638 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2639 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2640 u_char fiber_type = IFM_1000_SX; /* default type */ 2641 2642 if (adapter->hw.mac.type == e1000_82545) 2643 fiber_type = IFM_1000_LX; 2644 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2645 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2646 } else { 2647 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2648 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2649 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2650 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2651 if (adapter->hw.phy.type != e1000_phy_ife) { 2652 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2653 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2654 } 2655 } 2656 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2657 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2658 return (0); 2659 } 2660 2661 static int 2662 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2663 { 2664 struct adapter *adapter = iflib_get_softc(ctx); 2665 if_softc_ctx_t scctx = adapter->shared; 2666 int error = E1000_SUCCESS; 2667 struct em_tx_queue *que; 2668 int i, j; 2669 2670 MPASS(adapter->tx_num_queues > 0); 2671 MPASS(adapter->tx_num_queues == ntxqsets); 2672 2673 /* First allocate the top level queue structs */ 2674 if (!(adapter->tx_queues = 2675 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2676 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2677 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2678 return(ENOMEM); 2679 } 2680 2681 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2682 /* Set up some basics */ 2683 2684 struct tx_ring *txr = &que->txr; 2685 txr->adapter = que->adapter = adapter; 2686 que->me = txr->me = i; 2687 2688 /* Allocate report status array */ 2689 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2690 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2691 error = ENOMEM; 2692 goto fail; 2693 } 2694 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2695 txr->tx_rsq[j] = QIDX_INVALID; 2696 /* get the virtual and physical address of the hardware queues */ 2697 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2698 txr->tx_paddr = paddrs[i*ntxqs]; 2699 } 2700 2701 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2702 return (0); 2703 fail: 2704 em_if_queues_free(ctx); 2705 return (error); 2706 } 2707 2708 static int 2709 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2710 { 2711 struct adapter *adapter = iflib_get_softc(ctx); 2712 int error = E1000_SUCCESS; 2713 struct em_rx_queue *que; 2714 int i; 2715 2716 MPASS(adapter->rx_num_queues > 0); 2717 MPASS(adapter->rx_num_queues == nrxqsets); 2718 2719 /* First allocate the top level queue structs */ 2720 if (!(adapter->rx_queues = 2721 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2722 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2723 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2724 error = ENOMEM; 2725 goto fail; 2726 } 2727 2728 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2729 /* Set up some basics */ 2730 struct rx_ring *rxr = &que->rxr; 2731 rxr->adapter = que->adapter = adapter; 2732 rxr->que = que; 2733 que->me = rxr->me = i; 2734 2735 /* get the virtual and physical address of the hardware queues */ 2736 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2737 rxr->rx_paddr = paddrs[i*nrxqs]; 2738 } 2739 2740 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2741 2742 return (0); 2743 fail: 2744 em_if_queues_free(ctx); 2745 return (error); 2746 } 2747 2748 static void 2749 em_if_queues_free(if_ctx_t ctx) 2750 { 2751 struct adapter *adapter = iflib_get_softc(ctx); 2752 struct em_tx_queue *tx_que = adapter->tx_queues; 2753 struct em_rx_queue *rx_que = adapter->rx_queues; 2754 2755 if (tx_que != NULL) { 2756 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2757 struct tx_ring *txr = &tx_que->txr; 2758 if (txr->tx_rsq == NULL) 2759 break; 2760 2761 free(txr->tx_rsq, M_DEVBUF); 2762 txr->tx_rsq = NULL; 2763 } 2764 free(adapter->tx_queues, M_DEVBUF); 2765 adapter->tx_queues = NULL; 2766 } 2767 2768 if (rx_que != NULL) { 2769 free(adapter->rx_queues, M_DEVBUF); 2770 adapter->rx_queues = NULL; 2771 } 2772 2773 em_release_hw_control(adapter); 2774 2775 if (adapter->mta != NULL) { 2776 free(adapter->mta, M_DEVBUF); 2777 } 2778 } 2779 2780 /********************************************************************* 2781 * 2782 * Enable transmit unit. 2783 * 2784 **********************************************************************/ 2785 static void 2786 em_initialize_transmit_unit(if_ctx_t ctx) 2787 { 2788 struct adapter *adapter = iflib_get_softc(ctx); 2789 if_softc_ctx_t scctx = adapter->shared; 2790 struct em_tx_queue *que; 2791 struct tx_ring *txr; 2792 struct e1000_hw *hw = &adapter->hw; 2793 u32 tctl, txdctl = 0, tarc, tipg = 0; 2794 2795 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2796 2797 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2798 u64 bus_addr; 2799 caddr_t offp, endp; 2800 2801 que = &adapter->tx_queues[i]; 2802 txr = &que->txr; 2803 bus_addr = txr->tx_paddr; 2804 2805 /* Clear checksum offload context. */ 2806 offp = (caddr_t)&txr->csum_flags; 2807 endp = (caddr_t)(txr + 1); 2808 bzero(offp, endp - offp); 2809 2810 /* Base and Len of TX Ring */ 2811 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2812 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2813 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2814 (u32)(bus_addr >> 32)); 2815 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2816 (u32)bus_addr); 2817 /* Init the HEAD/TAIL indices */ 2818 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2819 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2820 2821 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2822 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2823 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2824 2825 txdctl = 0; /* clear txdctl */ 2826 txdctl |= 0x1f; /* PTHRESH */ 2827 txdctl |= 1 << 8; /* HTHRESH */ 2828 txdctl |= 1 << 16;/* WTHRESH */ 2829 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2830 txdctl |= E1000_TXDCTL_GRAN; 2831 txdctl |= 1 << 25; /* LWTHRESH */ 2832 2833 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2834 } 2835 2836 /* Set the default values for the Tx Inter Packet Gap timer */ 2837 switch (adapter->hw.mac.type) { 2838 case e1000_80003es2lan: 2839 tipg = DEFAULT_82543_TIPG_IPGR1; 2840 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2841 E1000_TIPG_IPGR2_SHIFT; 2842 break; 2843 case e1000_82542: 2844 tipg = DEFAULT_82542_TIPG_IPGT; 2845 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2846 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2847 break; 2848 default: 2849 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2850 (adapter->hw.phy.media_type == 2851 e1000_media_type_internal_serdes)) 2852 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2853 else 2854 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2855 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2856 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2857 } 2858 2859 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2860 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 2861 2862 if(adapter->hw.mac.type >= e1000_82540) 2863 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 2864 adapter->tx_abs_int_delay.value); 2865 2866 if ((adapter->hw.mac.type == e1000_82571) || 2867 (adapter->hw.mac.type == e1000_82572)) { 2868 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2869 tarc |= TARC_SPEED_MODE_BIT; 2870 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2871 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2872 /* errata: program both queues to unweighted RR */ 2873 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2874 tarc |= 1; 2875 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2876 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2877 tarc |= 1; 2878 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2879 } else if (adapter->hw.mac.type == e1000_82574) { 2880 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2881 tarc |= TARC_ERRATA_BIT; 2882 if ( adapter->tx_num_queues > 1) { 2883 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 2884 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2885 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2886 } else 2887 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2888 } 2889 2890 if (adapter->tx_int_delay.value > 0) 2891 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2892 2893 /* Program the Transmit Control Register */ 2894 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2895 tctl &= ~E1000_TCTL_CT; 2896 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2897 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 2898 2899 if (adapter->hw.mac.type >= e1000_82571) 2900 tctl |= E1000_TCTL_MULR; 2901 2902 /* This write will effectively turn on the transmit unit. */ 2903 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2904 2905 if (hw->mac.type == e1000_pch_spt) { 2906 u32 reg; 2907 reg = E1000_READ_REG(hw, E1000_IOSFPC); 2908 reg |= E1000_RCTL_RDMTS_HEX; 2909 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 2910 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2911 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 2912 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2913 } 2914 } 2915 2916 /********************************************************************* 2917 * 2918 * Enable receive unit. 2919 * 2920 **********************************************************************/ 2921 2922 static void 2923 em_initialize_receive_unit(if_ctx_t ctx) 2924 { 2925 struct adapter *adapter = iflib_get_softc(ctx); 2926 if_softc_ctx_t scctx = adapter->shared; 2927 struct ifnet *ifp = iflib_get_ifp(ctx); 2928 struct e1000_hw *hw = &adapter->hw; 2929 struct em_rx_queue *que; 2930 int i; 2931 u32 rctl, rxcsum, rfctl; 2932 2933 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 2934 2935 /* 2936 * Make sure receives are disabled while setting 2937 * up the descriptor ring 2938 */ 2939 rctl = E1000_READ_REG(hw, E1000_RCTL); 2940 /* Do not disable if ever enabled on this hardware */ 2941 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 2942 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2943 2944 /* Setup the Receive Control Register */ 2945 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2946 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 2947 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 2948 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2949 2950 /* Do not store bad packets */ 2951 rctl &= ~E1000_RCTL_SBP; 2952 2953 /* Enable Long Packet receive */ 2954 if (if_getmtu(ifp) > ETHERMTU) 2955 rctl |= E1000_RCTL_LPE; 2956 else 2957 rctl &= ~E1000_RCTL_LPE; 2958 2959 /* Strip the CRC */ 2960 if (!em_disable_crc_stripping) 2961 rctl |= E1000_RCTL_SECRC; 2962 2963 if (adapter->hw.mac.type >= e1000_82540) { 2964 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 2965 adapter->rx_abs_int_delay.value); 2966 2967 /* 2968 * Set the interrupt throttling rate. Value is calculated 2969 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2970 */ 2971 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 2972 } 2973 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 2974 adapter->rx_int_delay.value); 2975 2976 /* Use extended rx descriptor formats */ 2977 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2978 rfctl |= E1000_RFCTL_EXTEN; 2979 /* 2980 * When using MSIX interrupts we need to throttle 2981 * using the EITR register (82574 only) 2982 */ 2983 if (hw->mac.type == e1000_82574) { 2984 for (int i = 0; i < 4; i++) 2985 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 2986 DEFAULT_ITR); 2987 /* Disable accelerated acknowledge */ 2988 rfctl |= E1000_RFCTL_ACK_DIS; 2989 } 2990 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2991 2992 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2993 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 2994 adapter->hw.mac.type >= e1000_82543) { 2995 if (adapter->tx_num_queues > 1) { 2996 if (adapter->hw.mac.type >= igb_mac_min) { 2997 rxcsum |= E1000_RXCSUM_PCSD; 2998 if (hw->mac.type != e1000_82575) 2999 rxcsum |= E1000_RXCSUM_CRCOFL; 3000 } else 3001 rxcsum |= E1000_RXCSUM_TUOFL | 3002 E1000_RXCSUM_IPOFL | 3003 E1000_RXCSUM_PCSD; 3004 } else { 3005 if (adapter->hw.mac.type >= igb_mac_min) 3006 rxcsum |= E1000_RXCSUM_IPPCSE; 3007 else 3008 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3009 if (adapter->hw.mac.type > e1000_82575) 3010 rxcsum |= E1000_RXCSUM_CRCOFL; 3011 } 3012 } else 3013 rxcsum &= ~E1000_RXCSUM_TUOFL; 3014 3015 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3016 3017 if (adapter->rx_num_queues > 1) { 3018 if (adapter->hw.mac.type >= igb_mac_min) 3019 igb_initialize_rss_mapping(adapter); 3020 else 3021 em_initialize_rss_mapping(adapter); 3022 } 3023 3024 /* 3025 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3026 * long latencies are observed, like Lenovo X60. This 3027 * change eliminates the problem, but since having positive 3028 * values in RDTR is a known source of problems on other 3029 * platforms another solution is being sought. 3030 */ 3031 if (hw->mac.type == e1000_82573) 3032 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3033 3034 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3035 struct rx_ring *rxr = &que->rxr; 3036 /* Setup the Base and Length of the Rx Descriptor Ring */ 3037 u64 bus_addr = rxr->rx_paddr; 3038 #if 0 3039 u32 rdt = adapter->rx_num_queues -1; /* default */ 3040 #endif 3041 3042 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3043 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3044 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3045 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3046 /* Setup the Head and Tail Descriptor Pointers */ 3047 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3048 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3049 } 3050 3051 /* 3052 * Set PTHRESH for improved jumbo performance 3053 * According to 10.2.5.11 of Intel 82574 Datasheet, 3054 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3055 * Only write to RXDCTL(1) if there is a need for different 3056 * settings. 3057 */ 3058 3059 if (((adapter->hw.mac.type == e1000_ich9lan) || 3060 (adapter->hw.mac.type == e1000_pch2lan) || 3061 (adapter->hw.mac.type == e1000_ich10lan)) && 3062 (if_getmtu(ifp) > ETHERMTU)) { 3063 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3064 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3065 } else if (adapter->hw.mac.type == e1000_82574) { 3066 for (int i = 0; i < adapter->rx_num_queues; i++) { 3067 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3068 rxdctl |= 0x20; /* PTHRESH */ 3069 rxdctl |= 4 << 8; /* HTHRESH */ 3070 rxdctl |= 4 << 16;/* WTHRESH */ 3071 rxdctl |= 1 << 24; /* Switch to granularity */ 3072 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3073 } 3074 } else if (adapter->hw.mac.type >= igb_mac_min) { 3075 u32 psize, srrctl = 0; 3076 3077 if (if_getmtu(ifp) > ETHERMTU) { 3078 /* Set maximum packet len */ 3079 if (adapter->rx_mbuf_sz <= 4096) { 3080 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3081 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3082 } else if (adapter->rx_mbuf_sz > 4096) { 3083 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3084 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3085 } 3086 psize = scctx->isc_max_frame_size; 3087 /* are we on a vlan? */ 3088 if (ifp->if_vlantrunk != NULL) 3089 psize += VLAN_TAG_SIZE; 3090 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3091 } else { 3092 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3093 rctl |= E1000_RCTL_SZ_2048; 3094 } 3095 3096 /* 3097 * If TX flow control is disabled and there's >1 queue defined, 3098 * enable DROP. 3099 * 3100 * This drops frames rather than hanging the RX MAC for all queues. 3101 */ 3102 if ((adapter->rx_num_queues > 1) && 3103 (adapter->fc == e1000_fc_none || 3104 adapter->fc == e1000_fc_rx_pause)) { 3105 srrctl |= E1000_SRRCTL_DROP_EN; 3106 } 3107 /* Setup the Base and Length of the Rx Descriptor Rings */ 3108 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3109 struct rx_ring *rxr = &que->rxr; 3110 u64 bus_addr = rxr->rx_paddr; 3111 u32 rxdctl; 3112 3113 #ifdef notyet 3114 /* Configure for header split? -- ignore for now */ 3115 rxr->hdr_split = igb_header_split; 3116 #else 3117 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3118 #endif 3119 3120 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3121 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3122 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3123 (uint32_t)(bus_addr >> 32)); 3124 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3125 (uint32_t)bus_addr); 3126 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3127 /* Enable this Queue */ 3128 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3129 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3130 rxdctl &= 0xFFF00000; 3131 rxdctl |= IGB_RX_PTHRESH; 3132 rxdctl |= IGB_RX_HTHRESH << 8; 3133 rxdctl |= IGB_RX_WTHRESH << 16; 3134 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3135 } 3136 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3137 if (if_getmtu(ifp) > ETHERMTU) 3138 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3139 else 3140 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3141 } 3142 3143 /* Make sure VLAN Filters are off */ 3144 rctl &= ~E1000_RCTL_VFE; 3145 3146 if (adapter->hw.mac.type < igb_mac_min) { 3147 if (adapter->rx_mbuf_sz == MCLBYTES) 3148 rctl |= E1000_RCTL_SZ_2048; 3149 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3150 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3151 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3152 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3153 3154 /* ensure we clear use DTYPE of 00 here */ 3155 rctl &= ~0x00000C00; 3156 } 3157 3158 /* Write out the settings */ 3159 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3160 3161 return; 3162 } 3163 3164 static void 3165 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3166 { 3167 struct adapter *adapter = iflib_get_softc(ctx); 3168 u32 index, bit; 3169 3170 index = (vtag >> 5) & 0x7F; 3171 bit = vtag & 0x1F; 3172 adapter->shadow_vfta[index] |= (1 << bit); 3173 ++adapter->num_vlans; 3174 } 3175 3176 static void 3177 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3178 { 3179 struct adapter *adapter = iflib_get_softc(ctx); 3180 u32 index, bit; 3181 3182 index = (vtag >> 5) & 0x7F; 3183 bit = vtag & 0x1F; 3184 adapter->shadow_vfta[index] &= ~(1 << bit); 3185 --adapter->num_vlans; 3186 } 3187 3188 static void 3189 em_setup_vlan_hw_support(struct adapter *adapter) 3190 { 3191 struct e1000_hw *hw = &adapter->hw; 3192 u32 reg; 3193 3194 /* 3195 * We get here thru init_locked, meaning 3196 * a soft reset, this has already cleared 3197 * the VFTA and other state, so if there 3198 * have been no vlan's registered do nothing. 3199 */ 3200 if (adapter->num_vlans == 0) 3201 return; 3202 3203 /* 3204 * A soft reset zero's out the VFTA, so 3205 * we need to repopulate it now. 3206 */ 3207 for (int i = 0; i < EM_VFTA_SIZE; i++) 3208 if (adapter->shadow_vfta[i] != 0) 3209 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3210 i, adapter->shadow_vfta[i]); 3211 3212 reg = E1000_READ_REG(hw, E1000_CTRL); 3213 reg |= E1000_CTRL_VME; 3214 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3215 3216 /* Enable the Filter Table */ 3217 reg = E1000_READ_REG(hw, E1000_RCTL); 3218 reg &= ~E1000_RCTL_CFIEN; 3219 reg |= E1000_RCTL_VFE; 3220 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3221 } 3222 3223 static void 3224 em_if_enable_intr(if_ctx_t ctx) 3225 { 3226 struct adapter *adapter = iflib_get_softc(ctx); 3227 struct e1000_hw *hw = &adapter->hw; 3228 u32 ims_mask = IMS_ENABLE_MASK; 3229 3230 if (hw->mac.type == e1000_82574) { 3231 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3232 ims_mask |= adapter->ims; 3233 } if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3234 u32 mask = (adapter->que_mask | adapter->link_mask); 3235 3236 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3237 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3238 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3239 ims_mask = E1000_IMS_LSC; 3240 } 3241 3242 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3243 } 3244 3245 static void 3246 em_if_disable_intr(if_ctx_t ctx) 3247 { 3248 struct adapter *adapter = iflib_get_softc(ctx); 3249 struct e1000_hw *hw = &adapter->hw; 3250 3251 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3252 if (hw->mac.type >= igb_mac_min) 3253 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3254 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3255 } 3256 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3257 } 3258 3259 /* 3260 * Bit of a misnomer, what this really means is 3261 * to enable OS management of the system... aka 3262 * to disable special hardware management features 3263 */ 3264 static void 3265 em_init_manageability(struct adapter *adapter) 3266 { 3267 /* A shared code workaround */ 3268 #define E1000_82542_MANC2H E1000_MANC2H 3269 if (adapter->has_manage) { 3270 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3271 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3272 3273 /* disable hardware interception of ARP */ 3274 manc &= ~(E1000_MANC_ARP_EN); 3275 3276 /* enable receiving management packets to the host */ 3277 manc |= E1000_MANC_EN_MNG2HOST; 3278 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3279 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3280 manc2h |= E1000_MNG2HOST_PORT_623; 3281 manc2h |= E1000_MNG2HOST_PORT_664; 3282 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3283 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3284 } 3285 } 3286 3287 /* 3288 * Give control back to hardware management 3289 * controller if there is one. 3290 */ 3291 static void 3292 em_release_manageability(struct adapter *adapter) 3293 { 3294 if (adapter->has_manage) { 3295 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3296 3297 /* re-enable hardware interception of ARP */ 3298 manc |= E1000_MANC_ARP_EN; 3299 manc &= ~E1000_MANC_EN_MNG2HOST; 3300 3301 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3302 } 3303 } 3304 3305 /* 3306 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3307 * For ASF and Pass Through versions of f/w this means 3308 * that the driver is loaded. For AMT version type f/w 3309 * this means that the network i/f is open. 3310 */ 3311 static void 3312 em_get_hw_control(struct adapter *adapter) 3313 { 3314 u32 ctrl_ext, swsm; 3315 3316 if (adapter->hw.mac.type == e1000_82573) { 3317 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3318 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3319 swsm | E1000_SWSM_DRV_LOAD); 3320 return; 3321 } 3322 /* else */ 3323 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3324 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3325 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3326 return; 3327 } 3328 3329 /* 3330 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3331 * For ASF and Pass Through versions of f/w this means that 3332 * the driver is no longer loaded. For AMT versions of the 3333 * f/w this means that the network i/f is closed. 3334 */ 3335 static void 3336 em_release_hw_control(struct adapter *adapter) 3337 { 3338 u32 ctrl_ext, swsm; 3339 3340 if (!adapter->has_manage) 3341 return; 3342 3343 if (adapter->hw.mac.type == e1000_82573) { 3344 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3345 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3346 swsm & ~E1000_SWSM_DRV_LOAD); 3347 return; 3348 } 3349 /* else */ 3350 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3351 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3352 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3353 return; 3354 } 3355 3356 static int 3357 em_is_valid_ether_addr(u8 *addr) 3358 { 3359 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3360 3361 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3362 return (FALSE); 3363 } 3364 3365 return (TRUE); 3366 } 3367 3368 /* 3369 ** Parse the interface capabilities with regard 3370 ** to both system management and wake-on-lan for 3371 ** later use. 3372 */ 3373 static void 3374 em_get_wakeup(if_ctx_t ctx) 3375 { 3376 struct adapter *adapter = iflib_get_softc(ctx); 3377 device_t dev = iflib_get_dev(ctx); 3378 u16 eeprom_data = 0, device_id, apme_mask; 3379 3380 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3381 apme_mask = EM_EEPROM_APME; 3382 3383 switch (adapter->hw.mac.type) { 3384 case e1000_82542: 3385 case e1000_82543: 3386 break; 3387 case e1000_82544: 3388 e1000_read_nvm(&adapter->hw, 3389 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3390 apme_mask = EM_82544_APME; 3391 break; 3392 case e1000_82546: 3393 case e1000_82546_rev_3: 3394 if (adapter->hw.bus.func == 1) { 3395 e1000_read_nvm(&adapter->hw, 3396 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3397 break; 3398 } else 3399 e1000_read_nvm(&adapter->hw, 3400 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3401 break; 3402 case e1000_82573: 3403 case e1000_82583: 3404 adapter->has_amt = TRUE; 3405 /* FALLTHROUGH */ 3406 case e1000_82571: 3407 case e1000_82572: 3408 case e1000_80003es2lan: 3409 if (adapter->hw.bus.func == 1) { 3410 e1000_read_nvm(&adapter->hw, 3411 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3412 break; 3413 } else 3414 e1000_read_nvm(&adapter->hw, 3415 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3416 break; 3417 case e1000_ich8lan: 3418 case e1000_ich9lan: 3419 case e1000_ich10lan: 3420 case e1000_pchlan: 3421 case e1000_pch2lan: 3422 case e1000_pch_lpt: 3423 case e1000_pch_spt: 3424 case e1000_82575: /* listing all igb devices */ 3425 case e1000_82576: 3426 case e1000_82580: 3427 case e1000_i350: 3428 case e1000_i354: 3429 case e1000_i210: 3430 case e1000_i211: 3431 case e1000_vfadapt: 3432 case e1000_vfadapt_i350: 3433 apme_mask = E1000_WUC_APME; 3434 adapter->has_amt = TRUE; 3435 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3436 break; 3437 default: 3438 e1000_read_nvm(&adapter->hw, 3439 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3440 break; 3441 } 3442 if (eeprom_data & apme_mask) 3443 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3444 /* 3445 * We have the eeprom settings, now apply the special cases 3446 * where the eeprom may be wrong or the board won't support 3447 * wake on lan on a particular port 3448 */ 3449 device_id = pci_get_device(dev); 3450 switch (device_id) { 3451 case E1000_DEV_ID_82546GB_PCIE: 3452 adapter->wol = 0; 3453 break; 3454 case E1000_DEV_ID_82546EB_FIBER: 3455 case E1000_DEV_ID_82546GB_FIBER: 3456 /* Wake events only supported on port A for dual fiber 3457 * regardless of eeprom setting */ 3458 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3459 E1000_STATUS_FUNC_1) 3460 adapter->wol = 0; 3461 break; 3462 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3463 /* if quad port adapter, disable WoL on all but port A */ 3464 if (global_quad_port_a != 0) 3465 adapter->wol = 0; 3466 /* Reset for multiple quad port adapters */ 3467 if (++global_quad_port_a == 4) 3468 global_quad_port_a = 0; 3469 break; 3470 case E1000_DEV_ID_82571EB_FIBER: 3471 /* Wake events only supported on port A for dual fiber 3472 * regardless of eeprom setting */ 3473 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3474 E1000_STATUS_FUNC_1) 3475 adapter->wol = 0; 3476 break; 3477 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3478 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3479 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3480 /* if quad port adapter, disable WoL on all but port A */ 3481 if (global_quad_port_a != 0) 3482 adapter->wol = 0; 3483 /* Reset for multiple quad port adapters */ 3484 if (++global_quad_port_a == 4) 3485 global_quad_port_a = 0; 3486 break; 3487 } 3488 return; 3489 } 3490 3491 3492 /* 3493 * Enable PCI Wake On Lan capability 3494 */ 3495 static void 3496 em_enable_wakeup(if_ctx_t ctx) 3497 { 3498 struct adapter *adapter = iflib_get_softc(ctx); 3499 device_t dev = iflib_get_dev(ctx); 3500 if_t ifp = iflib_get_ifp(ctx); 3501 u32 pmc, ctrl, ctrl_ext, rctl, wuc; 3502 u16 status; 3503 3504 if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) 3505 return; 3506 3507 /* Advertise the wakeup capability */ 3508 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3509 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3510 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3511 wuc = E1000_READ_REG(&adapter->hw, E1000_WUC); 3512 wuc |= (E1000_WUC_PME_EN | E1000_WUC_APME); 3513 E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc); 3514 3515 if ((adapter->hw.mac.type == e1000_ich8lan) || 3516 (adapter->hw.mac.type == e1000_pchlan) || 3517 (adapter->hw.mac.type == e1000_ich9lan) || 3518 (adapter->hw.mac.type == e1000_ich10lan)) 3519 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3520 3521 /* Keep the laser running on Fiber adapters */ 3522 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3523 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3524 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3525 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3526 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3527 } 3528 3529 /* 3530 * Determine type of Wakeup: note that wol 3531 * is set with all bits on by default. 3532 */ 3533 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3534 adapter->wol &= ~E1000_WUFC_MAG; 3535 3536 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3537 adapter->wol &= ~E1000_WUFC_EX; 3538 3539 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3540 adapter->wol &= ~E1000_WUFC_MC; 3541 else { 3542 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3543 rctl |= E1000_RCTL_MPE; 3544 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3545 } 3546 3547 if ( adapter->hw.mac.type >= e1000_pchlan) { 3548 if (em_enable_phy_wakeup(adapter)) 3549 return; 3550 } else { 3551 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3552 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3553 } 3554 3555 if (adapter->hw.phy.type == e1000_phy_igp_3) 3556 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3557 3558 /* Request PME */ 3559 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3560 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3561 if (if_getcapenable(ifp) & IFCAP_WOL) 3562 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3563 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3564 3565 return; 3566 } 3567 3568 /* 3569 * WOL in the newer chipset interfaces (pchlan) 3570 * require thing to be copied into the phy 3571 */ 3572 static int 3573 em_enable_phy_wakeup(struct adapter *adapter) 3574 { 3575 struct e1000_hw *hw = &adapter->hw; 3576 u32 mreg, ret = 0; 3577 u16 preg; 3578 3579 /* copy MAC RARs to PHY RARs */ 3580 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3581 3582 /* copy MAC MTA to PHY MTA */ 3583 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3584 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3585 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3586 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3587 (u16)((mreg >> 16) & 0xFFFF)); 3588 } 3589 3590 /* configure PHY Rx Control register */ 3591 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3592 mreg = E1000_READ_REG(hw, E1000_RCTL); 3593 if (mreg & E1000_RCTL_UPE) 3594 preg |= BM_RCTL_UPE; 3595 if (mreg & E1000_RCTL_MPE) 3596 preg |= BM_RCTL_MPE; 3597 preg &= ~(BM_RCTL_MO_MASK); 3598 if (mreg & E1000_RCTL_MO_3) 3599 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3600 << BM_RCTL_MO_SHIFT); 3601 if (mreg & E1000_RCTL_BAM) 3602 preg |= BM_RCTL_BAM; 3603 if (mreg & E1000_RCTL_PMCF) 3604 preg |= BM_RCTL_PMCF; 3605 mreg = E1000_READ_REG(hw, E1000_CTRL); 3606 if (mreg & E1000_CTRL_RFCE) 3607 preg |= BM_RCTL_RFCE; 3608 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3609 3610 /* enable PHY wakeup in MAC register */ 3611 E1000_WRITE_REG(hw, E1000_WUC, 3612 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3613 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3614 3615 /* configure and enable PHY wakeup in PHY registers */ 3616 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3617 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3618 3619 /* activate PHY wakeup */ 3620 ret = hw->phy.ops.acquire(hw); 3621 if (ret) { 3622 printf("Could not acquire PHY\n"); 3623 return ret; 3624 } 3625 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3626 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3627 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3628 if (ret) { 3629 printf("Could not read PHY page 769\n"); 3630 goto out; 3631 } 3632 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3633 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3634 if (ret) 3635 printf("Could not set PHY Host Wakeup bit\n"); 3636 out: 3637 hw->phy.ops.release(hw); 3638 3639 return ret; 3640 } 3641 3642 static void 3643 em_if_led_func(if_ctx_t ctx, int onoff) 3644 { 3645 struct adapter *adapter = iflib_get_softc(ctx); 3646 3647 if (onoff) { 3648 e1000_setup_led(&adapter->hw); 3649 e1000_led_on(&adapter->hw); 3650 } else { 3651 e1000_led_off(&adapter->hw); 3652 e1000_cleanup_led(&adapter->hw); 3653 } 3654 } 3655 3656 /* 3657 * Disable the L0S and L1 LINK states 3658 */ 3659 static void 3660 em_disable_aspm(struct adapter *adapter) 3661 { 3662 int base, reg; 3663 u16 link_cap,link_ctrl; 3664 device_t dev = adapter->dev; 3665 3666 switch (adapter->hw.mac.type) { 3667 case e1000_82573: 3668 case e1000_82574: 3669 case e1000_82583: 3670 break; 3671 default: 3672 return; 3673 } 3674 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3675 return; 3676 reg = base + PCIER_LINK_CAP; 3677 link_cap = pci_read_config(dev, reg, 2); 3678 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3679 return; 3680 reg = base + PCIER_LINK_CTL; 3681 link_ctrl = pci_read_config(dev, reg, 2); 3682 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3683 pci_write_config(dev, reg, link_ctrl, 2); 3684 return; 3685 } 3686 3687 /********************************************************************** 3688 * 3689 * Update the board statistics counters. 3690 * 3691 **********************************************************************/ 3692 static void 3693 em_update_stats_counters(struct adapter *adapter) 3694 { 3695 3696 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3697 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3698 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3699 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3700 } 3701 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3702 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3703 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3704 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3705 3706 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3707 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3708 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3709 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3710 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3711 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3712 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3713 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3714 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3715 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3716 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3717 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3718 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3719 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3720 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3721 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3722 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3723 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3724 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3725 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3726 3727 /* For the 64-bit byte counters the low dword must be read first. */ 3728 /* Both registers clear on the read of the high dword */ 3729 3730 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3731 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3732 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3733 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3734 3735 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3736 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3737 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3738 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3739 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3740 3741 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3742 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3743 3744 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3745 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3746 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3747 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3748 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3749 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3750 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3751 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3752 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3753 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3754 3755 /* Interrupt Counts */ 3756 3757 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3758 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3759 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3760 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3761 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3762 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3763 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3764 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3765 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3766 3767 if (adapter->hw.mac.type >= e1000_82543) { 3768 adapter->stats.algnerrc += 3769 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3770 adapter->stats.rxerrc += 3771 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3772 adapter->stats.tncrs += 3773 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3774 adapter->stats.cexterr += 3775 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3776 adapter->stats.tsctc += 3777 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3778 adapter->stats.tsctfc += 3779 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3780 } 3781 } 3782 3783 static uint64_t 3784 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3785 { 3786 struct adapter *adapter = iflib_get_softc(ctx); 3787 struct ifnet *ifp = iflib_get_ifp(ctx); 3788 3789 switch (cnt) { 3790 case IFCOUNTER_COLLISIONS: 3791 return (adapter->stats.colc); 3792 case IFCOUNTER_IERRORS: 3793 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3794 adapter->stats.crcerrs + adapter->stats.algnerrc + 3795 adapter->stats.ruc + adapter->stats.roc + 3796 adapter->stats.mpc + adapter->stats.cexterr); 3797 case IFCOUNTER_OERRORS: 3798 return (adapter->stats.ecol + adapter->stats.latecol + 3799 adapter->watchdog_events); 3800 default: 3801 return (if_get_counter_default(ifp, cnt)); 3802 } 3803 } 3804 3805 /* Export a single 32-bit register via a read-only sysctl. */ 3806 static int 3807 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3808 { 3809 struct adapter *adapter; 3810 u_int val; 3811 3812 adapter = oidp->oid_arg1; 3813 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3814 return (sysctl_handle_int(oidp, &val, 0, req)); 3815 } 3816 3817 /* 3818 * Add sysctl variables, one per statistic, to the system. 3819 */ 3820 static void 3821 em_add_hw_stats(struct adapter *adapter) 3822 { 3823 device_t dev = iflib_get_dev(adapter->ctx); 3824 struct em_tx_queue *tx_que = adapter->tx_queues; 3825 struct em_rx_queue *rx_que = adapter->rx_queues; 3826 3827 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3828 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3829 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3830 struct e1000_hw_stats *stats = &adapter->stats; 3831 3832 struct sysctl_oid *stat_node, *queue_node, *int_node; 3833 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3834 3835 #define QUEUE_NAME_LEN 32 3836 char namebuf[QUEUE_NAME_LEN]; 3837 3838 /* Driver Statistics */ 3839 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3840 CTLFLAG_RD, &adapter->dropped_pkts, 3841 "Driver dropped packets"); 3842 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3843 CTLFLAG_RD, &adapter->link_irq, 3844 "Link MSIX IRQ Handled"); 3845 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 3846 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 3847 "Defragmenting mbuf chain failed"); 3848 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 3849 CTLFLAG_RD, &adapter->no_tx_dma_setup, 3850 "Driver tx dma failure in xmit"); 3851 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3852 CTLFLAG_RD, &adapter->rx_overruns, 3853 "RX overruns"); 3854 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 3855 CTLFLAG_RD, &adapter->watchdog_events, 3856 "Watchdog timeouts"); 3857 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 3858 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 3859 em_sysctl_reg_handler, "IU", 3860 "Device Control Register"); 3861 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 3862 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 3863 em_sysctl_reg_handler, "IU", 3864 "Receiver Control Register"); 3865 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 3866 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 3867 "Flow Control High Watermark"); 3868 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 3869 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 3870 "Flow Control Low Watermark"); 3871 3872 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3873 struct tx_ring *txr = &tx_que->txr; 3874 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 3875 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3876 CTLFLAG_RD, NULL, "TX Queue Name"); 3877 queue_list = SYSCTL_CHILDREN(queue_node); 3878 3879 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 3880 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3881 E1000_TDH(txr->me), 3882 em_sysctl_reg_handler, "IU", 3883 "Transmit Descriptor Head"); 3884 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 3885 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3886 E1000_TDT(txr->me), 3887 em_sysctl_reg_handler, "IU", 3888 "Transmit Descriptor Tail"); 3889 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 3890 CTLFLAG_RD, &txr->tx_irq, 3891 "Queue MSI-X Transmit Interrupts"); 3892 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "no_desc_avail", 3893 CTLFLAG_RD, &txr->no_desc_avail, 3894 "Queue No Descriptor Available"); 3895 } 3896 3897 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 3898 struct rx_ring *rxr = &rx_que->rxr; 3899 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 3900 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3901 CTLFLAG_RD, NULL, "RX Queue Name"); 3902 queue_list = SYSCTL_CHILDREN(queue_node); 3903 3904 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 3905 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3906 E1000_RDH(rxr->me), 3907 em_sysctl_reg_handler, "IU", 3908 "Receive Descriptor Head"); 3909 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 3910 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3911 E1000_RDT(rxr->me), 3912 em_sysctl_reg_handler, "IU", 3913 "Receive Descriptor Tail"); 3914 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 3915 CTLFLAG_RD, &rxr->rx_irq, 3916 "Queue MSI-X Receive Interrupts"); 3917 } 3918 3919 /* MAC stats get their own sub node */ 3920 3921 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 3922 CTLFLAG_RD, NULL, "Statistics"); 3923 stat_list = SYSCTL_CHILDREN(stat_node); 3924 3925 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 3926 CTLFLAG_RD, &stats->ecol, 3927 "Excessive collisions"); 3928 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 3929 CTLFLAG_RD, &stats->scc, 3930 "Single collisions"); 3931 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 3932 CTLFLAG_RD, &stats->mcc, 3933 "Multiple collisions"); 3934 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 3935 CTLFLAG_RD, &stats->latecol, 3936 "Late collisions"); 3937 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 3938 CTLFLAG_RD, &stats->colc, 3939 "Collision Count"); 3940 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 3941 CTLFLAG_RD, &adapter->stats.symerrs, 3942 "Symbol Errors"); 3943 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 3944 CTLFLAG_RD, &adapter->stats.sec, 3945 "Sequence Errors"); 3946 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 3947 CTLFLAG_RD, &adapter->stats.dc, 3948 "Defer Count"); 3949 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 3950 CTLFLAG_RD, &adapter->stats.mpc, 3951 "Missed Packets"); 3952 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 3953 CTLFLAG_RD, &adapter->stats.rnbc, 3954 "Receive No Buffers"); 3955 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 3956 CTLFLAG_RD, &adapter->stats.ruc, 3957 "Receive Undersize"); 3958 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 3959 CTLFLAG_RD, &adapter->stats.rfc, 3960 "Fragmented Packets Received "); 3961 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 3962 CTLFLAG_RD, &adapter->stats.roc, 3963 "Oversized Packets Received"); 3964 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 3965 CTLFLAG_RD, &adapter->stats.rjc, 3966 "Recevied Jabber"); 3967 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 3968 CTLFLAG_RD, &adapter->stats.rxerrc, 3969 "Receive Errors"); 3970 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 3971 CTLFLAG_RD, &adapter->stats.crcerrs, 3972 "CRC errors"); 3973 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 3974 CTLFLAG_RD, &adapter->stats.algnerrc, 3975 "Alignment Errors"); 3976 /* On 82575 these are collision counts */ 3977 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 3978 CTLFLAG_RD, &adapter->stats.cexterr, 3979 "Collision/Carrier extension errors"); 3980 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 3981 CTLFLAG_RD, &adapter->stats.xonrxc, 3982 "XON Received"); 3983 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 3984 CTLFLAG_RD, &adapter->stats.xontxc, 3985 "XON Transmitted"); 3986 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 3987 CTLFLAG_RD, &adapter->stats.xoffrxc, 3988 "XOFF Received"); 3989 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 3990 CTLFLAG_RD, &adapter->stats.xofftxc, 3991 "XOFF Transmitted"); 3992 3993 /* Packet Reception Stats */ 3994 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 3995 CTLFLAG_RD, &adapter->stats.tpr, 3996 "Total Packets Received "); 3997 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 3998 CTLFLAG_RD, &adapter->stats.gprc, 3999 "Good Packets Received"); 4000 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4001 CTLFLAG_RD, &adapter->stats.bprc, 4002 "Broadcast Packets Received"); 4003 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4004 CTLFLAG_RD, &adapter->stats.mprc, 4005 "Multicast Packets Received"); 4006 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4007 CTLFLAG_RD, &adapter->stats.prc64, 4008 "64 byte frames received "); 4009 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4010 CTLFLAG_RD, &adapter->stats.prc127, 4011 "65-127 byte frames received"); 4012 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4013 CTLFLAG_RD, &adapter->stats.prc255, 4014 "128-255 byte frames received"); 4015 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4016 CTLFLAG_RD, &adapter->stats.prc511, 4017 "256-511 byte frames received"); 4018 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4019 CTLFLAG_RD, &adapter->stats.prc1023, 4020 "512-1023 byte frames received"); 4021 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4022 CTLFLAG_RD, &adapter->stats.prc1522, 4023 "1023-1522 byte frames received"); 4024 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4025 CTLFLAG_RD, &adapter->stats.gorc, 4026 "Good Octets Received"); 4027 4028 /* Packet Transmission Stats */ 4029 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4030 CTLFLAG_RD, &adapter->stats.gotc, 4031 "Good Octets Transmitted"); 4032 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4033 CTLFLAG_RD, &adapter->stats.tpt, 4034 "Total Packets Transmitted"); 4035 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4036 CTLFLAG_RD, &adapter->stats.gptc, 4037 "Good Packets Transmitted"); 4038 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4039 CTLFLAG_RD, &adapter->stats.bptc, 4040 "Broadcast Packets Transmitted"); 4041 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4042 CTLFLAG_RD, &adapter->stats.mptc, 4043 "Multicast Packets Transmitted"); 4044 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4045 CTLFLAG_RD, &adapter->stats.ptc64, 4046 "64 byte frames transmitted "); 4047 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4048 CTLFLAG_RD, &adapter->stats.ptc127, 4049 "65-127 byte frames transmitted"); 4050 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4051 CTLFLAG_RD, &adapter->stats.ptc255, 4052 "128-255 byte frames transmitted"); 4053 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4054 CTLFLAG_RD, &adapter->stats.ptc511, 4055 "256-511 byte frames transmitted"); 4056 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4057 CTLFLAG_RD, &adapter->stats.ptc1023, 4058 "512-1023 byte frames transmitted"); 4059 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4060 CTLFLAG_RD, &adapter->stats.ptc1522, 4061 "1024-1522 byte frames transmitted"); 4062 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4063 CTLFLAG_RD, &adapter->stats.tsctc, 4064 "TSO Contexts Transmitted"); 4065 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4066 CTLFLAG_RD, &adapter->stats.tsctfc, 4067 "TSO Contexts Failed"); 4068 4069 4070 /* Interrupt Stats */ 4071 4072 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4073 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4074 int_list = SYSCTL_CHILDREN(int_node); 4075 4076 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4077 CTLFLAG_RD, &adapter->stats.iac, 4078 "Interrupt Assertion Count"); 4079 4080 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4081 CTLFLAG_RD, &adapter->stats.icrxptc, 4082 "Interrupt Cause Rx Pkt Timer Expire Count"); 4083 4084 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4085 CTLFLAG_RD, &adapter->stats.icrxatc, 4086 "Interrupt Cause Rx Abs Timer Expire Count"); 4087 4088 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4089 CTLFLAG_RD, &adapter->stats.ictxptc, 4090 "Interrupt Cause Tx Pkt Timer Expire Count"); 4091 4092 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4093 CTLFLAG_RD, &adapter->stats.ictxatc, 4094 "Interrupt Cause Tx Abs Timer Expire Count"); 4095 4096 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4097 CTLFLAG_RD, &adapter->stats.ictxqec, 4098 "Interrupt Cause Tx Queue Empty Count"); 4099 4100 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4101 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4102 "Interrupt Cause Tx Queue Min Thresh Count"); 4103 4104 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4105 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4106 "Interrupt Cause Rx Desc Min Thresh Count"); 4107 4108 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4109 CTLFLAG_RD, &adapter->stats.icrxoc, 4110 "Interrupt Cause Receiver Overrun Count"); 4111 } 4112 4113 /********************************************************************** 4114 * 4115 * This routine provides a way to dump out the adapter eeprom, 4116 * often a useful debug/service tool. This only dumps the first 4117 * 32 words, stuff that matters is in that extent. 4118 * 4119 **********************************************************************/ 4120 static int 4121 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4122 { 4123 struct adapter *adapter = (struct adapter *)arg1; 4124 int error; 4125 int result; 4126 4127 result = -1; 4128 error = sysctl_handle_int(oidp, &result, 0, req); 4129 4130 if (error || !req->newptr) 4131 return (error); 4132 4133 /* 4134 * This value will cause a hex dump of the 4135 * first 32 16-bit words of the EEPROM to 4136 * the screen. 4137 */ 4138 if (result == 1) 4139 em_print_nvm_info(adapter); 4140 4141 return (error); 4142 } 4143 4144 static void 4145 em_print_nvm_info(struct adapter *adapter) 4146 { 4147 u16 eeprom_data; 4148 int i, j, row = 0; 4149 4150 /* Its a bit crude, but it gets the job done */ 4151 printf("\nInterface EEPROM Dump:\n"); 4152 printf("Offset\n0x0000 "); 4153 for (i = 0, j = 0; i < 32; i++, j++) { 4154 if (j == 8) { /* Make the offset block */ 4155 j = 0; ++row; 4156 printf("\n0x00%x0 ",row); 4157 } 4158 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4159 printf("%04x ", eeprom_data); 4160 } 4161 printf("\n"); 4162 } 4163 4164 static int 4165 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4166 { 4167 struct em_int_delay_info *info; 4168 struct adapter *adapter; 4169 u32 regval; 4170 int error, usecs, ticks; 4171 4172 info = (struct em_int_delay_info *) arg1; 4173 usecs = info->value; 4174 error = sysctl_handle_int(oidp, &usecs, 0, req); 4175 if (error != 0 || req->newptr == NULL) 4176 return (error); 4177 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4178 return (EINVAL); 4179 info->value = usecs; 4180 ticks = EM_USECS_TO_TICKS(usecs); 4181 if (info->offset == E1000_ITR) /* units are 256ns here */ 4182 ticks *= 4; 4183 4184 adapter = info->adapter; 4185 4186 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4187 regval = (regval & ~0xffff) | (ticks & 0xffff); 4188 /* Handle a few special cases. */ 4189 switch (info->offset) { 4190 case E1000_RDTR: 4191 break; 4192 case E1000_TIDV: 4193 if (ticks == 0) { 4194 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4195 /* Don't write 0 into the TIDV register. */ 4196 regval++; 4197 } else 4198 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4199 break; 4200 } 4201 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4202 return (0); 4203 } 4204 4205 static void 4206 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4207 const char *description, struct em_int_delay_info *info, 4208 int offset, int value) 4209 { 4210 info->adapter = adapter; 4211 info->offset = offset; 4212 info->value = value; 4213 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4214 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4215 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4216 info, 0, em_sysctl_int_delay, "I", description); 4217 } 4218 4219 static void 4220 em_set_sysctl_value(struct adapter *adapter, const char *name, 4221 const char *description, int *limit, int value) 4222 { 4223 *limit = value; 4224 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 4225 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4226 OID_AUTO, name, CTLFLAG_RW, limit, value, description); 4227 } 4228 4229 4230 /* 4231 * Set flow control using sysctl: 4232 * Flow control values: 4233 * 0 - off 4234 * 1 - rx pause 4235 * 2 - tx pause 4236 * 3 - full 4237 */ 4238 static int 4239 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4240 { 4241 int error; 4242 static int input = 3; /* default is full */ 4243 struct adapter *adapter = (struct adapter *) arg1; 4244 4245 error = sysctl_handle_int(oidp, &input, 0, req); 4246 4247 if ((error) || (req->newptr == NULL)) 4248 return (error); 4249 4250 if (input == adapter->fc) /* no change? */ 4251 return (error); 4252 4253 switch (input) { 4254 case e1000_fc_rx_pause: 4255 case e1000_fc_tx_pause: 4256 case e1000_fc_full: 4257 case e1000_fc_none: 4258 adapter->hw.fc.requested_mode = input; 4259 adapter->fc = input; 4260 break; 4261 default: 4262 /* Do nothing */ 4263 return (error); 4264 } 4265 4266 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4267 e1000_force_mac_fc(&adapter->hw); 4268 return (error); 4269 } 4270 4271 /* 4272 * Manage Energy Efficient Ethernet: 4273 * Control values: 4274 * 0/1 - enabled/disabled 4275 */ 4276 static int 4277 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4278 { 4279 struct adapter *adapter = (struct adapter *) arg1; 4280 int error, value; 4281 4282 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4283 error = sysctl_handle_int(oidp, &value, 0, req); 4284 if (error || req->newptr == NULL) 4285 return (error); 4286 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4287 em_if_init(adapter->ctx); 4288 4289 return (0); 4290 } 4291 4292 static int 4293 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4294 { 4295 struct adapter *adapter; 4296 int error; 4297 int result; 4298 4299 result = -1; 4300 error = sysctl_handle_int(oidp, &result, 0, req); 4301 4302 if (error || !req->newptr) 4303 return (error); 4304 4305 if (result == 1) { 4306 adapter = (struct adapter *) arg1; 4307 em_print_debug_info(adapter); 4308 } 4309 4310 return (error); 4311 } 4312 4313 static int 4314 em_get_rs(SYSCTL_HANDLER_ARGS) 4315 { 4316 struct adapter *adapter = (struct adapter *) arg1; 4317 int error; 4318 int result; 4319 4320 result = 0; 4321 error = sysctl_handle_int(oidp, &result, 0, req); 4322 4323 if (error || !req->newptr || result != 1) 4324 return (error); 4325 em_dump_rs(adapter); 4326 4327 return (error); 4328 } 4329 4330 static void 4331 em_if_debug(if_ctx_t ctx) 4332 { 4333 em_dump_rs(iflib_get_softc(ctx)); 4334 } 4335 4336 /* 4337 * This routine is meant to be fluid, add whatever is 4338 * needed for debugging a problem. -jfv 4339 */ 4340 static void 4341 em_print_debug_info(struct adapter *adapter) 4342 { 4343 device_t dev = adapter->dev; 4344 struct tx_ring *txr = &adapter->tx_queues->txr; 4345 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4346 4347 if (if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) 4348 printf("Interface is RUNNING "); 4349 else 4350 printf("Interface is NOT RUNNING\n"); 4351 4352 if (if_getdrvflags(adapter->ifp) & IFF_DRV_OACTIVE) 4353 printf("and INACTIVE\n"); 4354 else 4355 printf("and ACTIVE\n"); 4356 4357 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4358 device_printf(dev, "TX Queue %d ------\n", i); 4359 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4360 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4361 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4362 4363 } 4364 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4365 device_printf(dev, "RX Queue %d ------\n", j); 4366 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4367 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4368 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4369 } 4370 } 4371 4372 /* 4373 * 82574 only: 4374 * Write a new value to the EEPROM increasing the number of MSIX 4375 * vectors from 3 to 5, for proper multiqueue support. 4376 */ 4377 static void 4378 em_enable_vectors_82574(if_ctx_t ctx) 4379 { 4380 struct adapter *adapter = iflib_get_softc(ctx); 4381 struct e1000_hw *hw = &adapter->hw; 4382 device_t dev = iflib_get_dev(ctx); 4383 u16 edata; 4384 4385 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4386 printf("Current cap: %#06x\n", edata); 4387 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4388 device_printf(dev, "Writing to eeprom: increasing " 4389 "reported MSIX vectors from 3 to 5...\n"); 4390 edata &= ~(EM_NVM_MSIX_N_MASK); 4391 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4392 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4393 e1000_update_nvm_checksum(hw); 4394 device_printf(dev, "Writing to eeprom: done\n"); 4395 } 4396 } 4397 4398 4399 #ifdef DDB 4400 DB_COMMAND(em_reset_dev, em_ddb_reset_dev) 4401 { 4402 devclass_t dc; 4403 int max_em; 4404 4405 dc = devclass_find("em"); 4406 max_em = devclass_get_maxunit(dc); 4407 4408 for (int index = 0; index < (max_em - 1); index++) { 4409 device_t dev; 4410 dev = devclass_get_device(dc, index); 4411 if (device_get_driver(dev) == &em_driver) { 4412 struct adapter *adapter = device_get_softc(dev); 4413 em_if_init(adapter->ctx); 4414 } 4415 } 4416 } 4417 DB_COMMAND(em_dump_queue, em_ddb_dump_queue) 4418 { 4419 devclass_t dc; 4420 int max_em; 4421 4422 dc = devclass_find("em"); 4423 max_em = devclass_get_maxunit(dc); 4424 4425 for (int index = 0; index < (max_em - 1); index++) { 4426 device_t dev; 4427 dev = devclass_get_device(dc, index); 4428 if (device_get_driver(dev) == &em_driver) 4429 em_print_debug_info(device_get_softc(dev)); 4430 } 4431 4432 } 4433 #endif 4434