1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static bool em_automask_tso(if_ctx_t); 334 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 335 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 336 const char *, struct em_int_delay_info *, int, int); 337 /* Management and WOL Support */ 338 static void em_init_manageability(struct e1000_softc *); 339 static void em_release_manageability(struct e1000_softc *); 340 static void em_get_hw_control(struct e1000_softc *); 341 static void em_release_hw_control(struct e1000_softc *); 342 static void em_get_wakeup(if_ctx_t); 343 static void em_enable_wakeup(if_ctx_t); 344 static int em_enable_phy_wakeup(struct e1000_softc *); 345 static void em_disable_aspm(struct e1000_softc *); 346 347 int em_intr(void *); 348 349 /* MSI-X handlers */ 350 static int em_if_msix_intr_assign(if_ctx_t, int); 351 static int em_msix_link(void *); 352 static void em_handle_link(void *); 353 354 static void em_enable_vectors_82574(if_ctx_t); 355 356 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 357 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 358 static void em_if_led_func(if_ctx_t, int); 359 360 static int em_get_regs(SYSCTL_HANDLER_ARGS); 361 362 static void lem_smartspeed(struct e1000_softc *); 363 static void igb_configure_queues(struct e1000_softc *); 364 static void em_flush_desc_rings(struct e1000_softc *); 365 366 367 /********************************************************************* 368 * FreeBSD Device Interface Entry Points 369 *********************************************************************/ 370 static device_method_t em_methods[] = { 371 /* Device interface */ 372 DEVMETHOD(device_register, em_register), 373 DEVMETHOD(device_probe, iflib_device_probe), 374 DEVMETHOD(device_attach, iflib_device_attach), 375 DEVMETHOD(device_detach, iflib_device_detach), 376 DEVMETHOD(device_shutdown, iflib_device_shutdown), 377 DEVMETHOD(device_suspend, iflib_device_suspend), 378 DEVMETHOD(device_resume, iflib_device_resume), 379 DEVMETHOD_END 380 }; 381 382 static device_method_t igb_methods[] = { 383 /* Device interface */ 384 DEVMETHOD(device_register, igb_register), 385 DEVMETHOD(device_probe, iflib_device_probe), 386 DEVMETHOD(device_attach, iflib_device_attach), 387 DEVMETHOD(device_detach, iflib_device_detach), 388 DEVMETHOD(device_shutdown, iflib_device_shutdown), 389 DEVMETHOD(device_suspend, iflib_device_suspend), 390 DEVMETHOD(device_resume, iflib_device_resume), 391 DEVMETHOD_END 392 }; 393 394 395 static driver_t em_driver = { 396 "em", em_methods, sizeof(struct e1000_softc), 397 }; 398 399 DRIVER_MODULE(em, pci, em_driver, 0, 0); 400 401 MODULE_DEPEND(em, pci, 1, 1, 1); 402 MODULE_DEPEND(em, ether, 1, 1, 1); 403 MODULE_DEPEND(em, iflib, 1, 1, 1); 404 405 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 406 407 static driver_t igb_driver = { 408 "igb", igb_methods, sizeof(struct e1000_softc), 409 }; 410 411 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 412 413 MODULE_DEPEND(igb, pci, 1, 1, 1); 414 MODULE_DEPEND(igb, ether, 1, 1, 1); 415 MODULE_DEPEND(igb, iflib, 1, 1, 1); 416 417 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 418 419 static device_method_t em_if_methods[] = { 420 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 421 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 422 DEVMETHOD(ifdi_detach, em_if_detach), 423 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 424 DEVMETHOD(ifdi_suspend, em_if_suspend), 425 DEVMETHOD(ifdi_resume, em_if_resume), 426 DEVMETHOD(ifdi_init, em_if_init), 427 DEVMETHOD(ifdi_stop, em_if_stop), 428 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 429 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 430 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 431 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 432 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 433 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 434 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 435 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 436 DEVMETHOD(ifdi_media_status, em_if_media_status), 437 DEVMETHOD(ifdi_media_change, em_if_media_change), 438 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 439 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 440 DEVMETHOD(ifdi_timer, em_if_timer), 441 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 442 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 443 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 444 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 445 DEVMETHOD(ifdi_led_func, em_if_led_func), 446 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 447 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 448 DEVMETHOD(ifdi_debug, em_if_debug), 449 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 450 DEVMETHOD_END 451 }; 452 453 static driver_t em_if_driver = { 454 "em_if", em_if_methods, sizeof(struct e1000_softc) 455 }; 456 457 static device_method_t igb_if_methods[] = { 458 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 459 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 460 DEVMETHOD(ifdi_detach, em_if_detach), 461 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 462 DEVMETHOD(ifdi_suspend, em_if_suspend), 463 DEVMETHOD(ifdi_resume, em_if_resume), 464 DEVMETHOD(ifdi_init, em_if_init), 465 DEVMETHOD(ifdi_stop, em_if_stop), 466 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 467 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 468 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 469 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 470 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 471 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 472 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 473 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 474 DEVMETHOD(ifdi_media_status, em_if_media_status), 475 DEVMETHOD(ifdi_media_change, em_if_media_change), 476 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 477 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 478 DEVMETHOD(ifdi_timer, em_if_timer), 479 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 480 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 481 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 482 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 483 DEVMETHOD(ifdi_led_func, em_if_led_func), 484 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 485 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 486 DEVMETHOD(ifdi_debug, em_if_debug), 487 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 488 DEVMETHOD_END 489 }; 490 491 static driver_t igb_if_driver = { 492 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 493 }; 494 495 /********************************************************************* 496 * Tunable default values. 497 *********************************************************************/ 498 499 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 500 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 501 502 #define MAX_INTS_PER_SEC 8000 503 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 504 505 /* Allow common code without TSO */ 506 #ifndef CSUM_TSO 507 #define CSUM_TSO 0 508 #endif 509 510 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 511 "EM driver parameters"); 512 513 static int em_disable_crc_stripping = 0; 514 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 515 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 516 517 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 518 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 519 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 520 0, "Default transmit interrupt delay in usecs"); 521 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 522 0, "Default receive interrupt delay in usecs"); 523 524 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 525 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 526 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 527 &em_tx_abs_int_delay_dflt, 0, 528 "Default transmit interrupt delay limit in usecs"); 529 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 530 &em_rx_abs_int_delay_dflt, 0, 531 "Default receive interrupt delay limit in usecs"); 532 533 static int em_smart_pwr_down = false; 534 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 535 0, "Set to true to leave smart power down enabled on newer adapters"); 536 537 static bool em_unsupported_tso = false; 538 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 539 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 540 541 /* Controls whether promiscuous also shows bad packets */ 542 static int em_debug_sbp = false; 543 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 544 "Show bad packets in promiscuous mode"); 545 546 /* How many packets rxeof tries to clean at a time */ 547 static int em_rx_process_limit = 100; 548 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 549 &em_rx_process_limit, 0, 550 "Maximum number of received packets to process " 551 "at a time, -1 means unlimited"); 552 553 /* Energy efficient ethernet - default to OFF */ 554 static int eee_setting = 1; 555 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 556 "Enable Energy Efficient Ethernet"); 557 558 /* 559 ** Tuneable Interrupt rate 560 */ 561 static int em_max_interrupt_rate = 8000; 562 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 563 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 564 565 566 567 /* Global used in WOL setup with multiport cards */ 568 static int global_quad_port_a = 0; 569 570 extern struct if_txrx igb_txrx; 571 extern struct if_txrx em_txrx; 572 extern struct if_txrx lem_txrx; 573 574 static struct if_shared_ctx em_sctx_init = { 575 .isc_magic = IFLIB_MAGIC, 576 .isc_q_align = PAGE_SIZE, 577 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 578 .isc_tx_maxsegsize = PAGE_SIZE, 579 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 580 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 581 .isc_rx_maxsize = MJUM9BYTES, 582 .isc_rx_nsegments = 1, 583 .isc_rx_maxsegsize = MJUM9BYTES, 584 .isc_nfl = 1, 585 .isc_nrxqs = 1, 586 .isc_ntxqs = 1, 587 .isc_admin_intrcnt = 1, 588 .isc_vendor_info = em_vendor_info_array, 589 .isc_driver_version = em_driver_version, 590 .isc_driver = &em_if_driver, 591 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 592 593 .isc_nrxd_min = {EM_MIN_RXD}, 594 .isc_ntxd_min = {EM_MIN_TXD}, 595 .isc_nrxd_max = {EM_MAX_RXD}, 596 .isc_ntxd_max = {EM_MAX_TXD}, 597 .isc_nrxd_default = {EM_DEFAULT_RXD}, 598 .isc_ntxd_default = {EM_DEFAULT_TXD}, 599 }; 600 601 static struct if_shared_ctx igb_sctx_init = { 602 .isc_magic = IFLIB_MAGIC, 603 .isc_q_align = PAGE_SIZE, 604 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 605 .isc_tx_maxsegsize = PAGE_SIZE, 606 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 607 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 608 .isc_rx_maxsize = MJUM9BYTES, 609 .isc_rx_nsegments = 1, 610 .isc_rx_maxsegsize = MJUM9BYTES, 611 .isc_nfl = 1, 612 .isc_nrxqs = 1, 613 .isc_ntxqs = 1, 614 .isc_admin_intrcnt = 1, 615 .isc_vendor_info = igb_vendor_info_array, 616 .isc_driver_version = igb_driver_version, 617 .isc_driver = &igb_if_driver, 618 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 619 620 .isc_nrxd_min = {EM_MIN_RXD}, 621 .isc_ntxd_min = {EM_MIN_TXD}, 622 .isc_nrxd_max = {IGB_MAX_RXD}, 623 .isc_ntxd_max = {IGB_MAX_TXD}, 624 .isc_nrxd_default = {EM_DEFAULT_RXD}, 625 .isc_ntxd_default = {EM_DEFAULT_TXD}, 626 }; 627 628 /***************************************************************** 629 * 630 * Dump Registers 631 * 632 ****************************************************************/ 633 #define IGB_REGS_LEN 739 634 635 static int em_get_regs(SYSCTL_HANDLER_ARGS) 636 { 637 struct e1000_softc *sc = (struct e1000_softc *)arg1; 638 struct e1000_hw *hw = &sc->hw; 639 struct sbuf *sb; 640 u32 *regs_buff; 641 int rc; 642 643 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 644 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 645 646 rc = sysctl_wire_old_buffer(req, 0); 647 MPASS(rc == 0); 648 if (rc != 0) { 649 free(regs_buff, M_DEVBUF); 650 return (rc); 651 } 652 653 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 654 MPASS(sb != NULL); 655 if (sb == NULL) { 656 free(regs_buff, M_DEVBUF); 657 return (ENOMEM); 658 } 659 660 /* General Registers */ 661 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 662 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 663 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 664 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 665 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 666 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 667 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 668 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 669 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 670 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 671 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 672 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 673 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 674 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 675 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 676 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 677 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 678 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 679 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 680 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 681 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 682 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 683 684 sbuf_printf(sb, "General Registers\n"); 685 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 686 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 687 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 688 689 sbuf_printf(sb, "Interrupt Registers\n"); 690 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 691 692 sbuf_printf(sb, "RX Registers\n"); 693 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 694 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 695 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 696 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 697 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 698 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 699 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 700 701 sbuf_printf(sb, "TX Registers\n"); 702 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 703 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 704 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 705 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 706 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 707 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 708 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 709 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 710 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 711 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 712 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 713 714 free(regs_buff, M_DEVBUF); 715 716 #ifdef DUMP_DESCS 717 { 718 if_softc_ctx_t scctx = sc->shared; 719 struct rx_ring *rxr = &rx_que->rxr; 720 struct tx_ring *txr = &tx_que->txr; 721 int ntxd = scctx->isc_ntxd[0]; 722 int nrxd = scctx->isc_nrxd[0]; 723 int j; 724 725 for (j = 0; j < nrxd; j++) { 726 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 727 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 728 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 729 } 730 731 for (j = 0; j < min(ntxd, 256); j++) { 732 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 733 734 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 735 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 736 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 737 738 } 739 } 740 #endif 741 742 rc = sbuf_finish(sb); 743 sbuf_delete(sb); 744 return(rc); 745 } 746 747 static void * 748 em_register(device_t dev) 749 { 750 return (&em_sctx_init); 751 } 752 753 static void * 754 igb_register(device_t dev) 755 { 756 return (&igb_sctx_init); 757 } 758 759 static int 760 em_set_num_queues(if_ctx_t ctx) 761 { 762 struct e1000_softc *sc = iflib_get_softc(ctx); 763 int maxqueues; 764 765 /* Sanity check based on HW */ 766 switch (sc->hw.mac.type) { 767 case e1000_82576: 768 case e1000_82580: 769 case e1000_i350: 770 case e1000_i354: 771 maxqueues = 8; 772 break; 773 case e1000_i210: 774 case e1000_82575: 775 maxqueues = 4; 776 break; 777 case e1000_i211: 778 case e1000_82574: 779 maxqueues = 2; 780 break; 781 default: 782 maxqueues = 1; 783 break; 784 } 785 786 return (maxqueues); 787 } 788 789 #define LEM_CAPS \ 790 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 791 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 792 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 793 794 #define EM_CAPS \ 795 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 796 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 797 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 798 IFCAP_TSO6 799 800 #define IGB_CAPS \ 801 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 802 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 803 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 804 IFCAP_TSO6 805 806 /********************************************************************* 807 * Device initialization routine 808 * 809 * The attach entry point is called when the driver is being loaded. 810 * This routine identifies the type of hardware, allocates all resources 811 * and initializes the hardware. 812 * 813 * return 0 on success, positive on failure 814 *********************************************************************/ 815 static int 816 em_if_attach_pre(if_ctx_t ctx) 817 { 818 struct e1000_softc *sc; 819 if_softc_ctx_t scctx; 820 device_t dev; 821 struct e1000_hw *hw; 822 struct sysctl_oid_list *child; 823 struct sysctl_ctx_list *ctx_list; 824 int error = 0; 825 826 INIT_DEBUGOUT("em_if_attach_pre: begin"); 827 dev = iflib_get_dev(ctx); 828 sc = iflib_get_softc(ctx); 829 830 sc->ctx = sc->osdep.ctx = ctx; 831 sc->dev = sc->osdep.dev = dev; 832 scctx = sc->shared = iflib_get_softc_ctx(ctx); 833 sc->media = iflib_get_media(ctx); 834 hw = &sc->hw; 835 836 sc->tx_process_limit = scctx->isc_ntxd[0]; 837 838 /* Determine hardware and mac info */ 839 em_identify_hardware(ctx); 840 841 /* SYSCTL stuff */ 842 ctx_list = device_get_sysctl_ctx(dev); 843 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 844 845 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 846 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 847 em_sysctl_nvm_info, "I", "NVM Information"); 848 849 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 850 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 851 em_sysctl_print_fw_version, "A", 852 "Prints FW/NVM Versions"); 853 854 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 855 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 856 em_sysctl_debug_info, "I", "Debug Information"); 857 858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 859 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 860 em_set_flowcntl, "I", "Flow Control"); 861 862 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 863 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 864 em_get_regs, "A", "Dump Registers"); 865 866 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 867 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 868 em_get_rs, "I", "Dump RS indexes"); 869 870 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 871 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 872 if (bootverbose) 873 device_printf(dev, "attach_pre capping queues at %d\n", 874 scctx->isc_ntxqsets_max); 875 876 if (hw->mac.type >= igb_mac_min) { 877 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 878 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 879 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 880 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 881 scctx->isc_txrx = &igb_txrx; 882 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 883 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 884 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 885 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 886 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 887 CSUM_IP6_TCP | CSUM_IP6_UDP; 888 if (hw->mac.type != e1000_82575) 889 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 890 /* 891 ** Some new devices, as with ixgbe, now may 892 ** use a different BAR, so we need to keep 893 ** track of which is used. 894 */ 895 scctx->isc_msix_bar = pci_msix_table_bar(dev); 896 } else if (hw->mac.type >= em_mac_min) { 897 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 898 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 899 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 900 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 901 scctx->isc_txrx = &em_txrx; 902 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 903 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 904 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 905 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 906 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 907 CSUM_IP6_TCP | CSUM_IP6_UDP; 908 909 /* Disable TSO on 82574L due to performance loss being investigated */ 910 if (hw->mac.type == e1000_82574) 911 scctx->isc_capenable &= ~IFCAP_TSO; 912 /* 913 * Disable TSO on SPT due to errata that downclocks DMA performance 914 * i218-i219 Specification Update 1.5.4.5 915 */ 916 if (hw->mac.type == e1000_pch_spt) 917 scctx->isc_capenable &= ~IFCAP_TSO; 918 919 /* 920 * We support MSI-X with 82574 only, but indicate to iflib(4) 921 * that it shall give MSI at least a try with other devices. 922 */ 923 if (hw->mac.type == e1000_82574) { 924 scctx->isc_msix_bar = pci_msix_table_bar(dev); 925 } else { 926 scctx->isc_msix_bar = -1; 927 scctx->isc_disable_msix = 1; 928 } 929 } else { 930 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 931 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 932 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 933 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 934 scctx->isc_txrx = &lem_txrx; 935 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 936 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 937 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 938 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 939 if (em_unsupported_tso) 940 scctx->isc_capabilities |= IFCAP_TSO6; 941 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 942 CSUM_IP6_TCP | CSUM_IP6_UDP; 943 944 /* 82541ER doesn't do HW tagging */ 945 if (hw->device_id == E1000_DEV_ID_82541ER || 946 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 947 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 948 scctx->isc_capenable = scctx->isc_capabilities; 949 } 950 /* This is the first e1000 chip and it does not do offloads */ 951 if (hw->mac.type == e1000_82542) { 952 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 953 IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING | 954 IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO); 955 scctx->isc_capenable = scctx->isc_capabilities; 956 } 957 /* These can't do TSO for various reasons */ 958 if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 || 959 hw->mac.type == e1000_82547_rev_2) { 960 scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 961 scctx->isc_capenable = scctx->isc_capabilities; 962 } 963 /* XXXKB: No IPv6 before this? */ 964 if (hw->mac.type < e1000_82545){ 965 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 966 scctx->isc_capenable = scctx->isc_capabilities; 967 } 968 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 969 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 970 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 971 IFCAP_HWCSUM_IPV6); 972 973 /* INTx only */ 974 scctx->isc_msix_bar = 0; 975 } 976 977 /* Setup PCI resources */ 978 if (em_allocate_pci_resources(ctx)) { 979 device_printf(dev, "Allocation of PCI resources failed\n"); 980 error = ENXIO; 981 goto err_pci; 982 } 983 984 /* 985 ** For ICH8 and family we need to 986 ** map the flash memory, and this 987 ** must happen after the MAC is 988 ** identified 989 */ 990 if ((hw->mac.type == e1000_ich8lan) || 991 (hw->mac.type == e1000_ich9lan) || 992 (hw->mac.type == e1000_ich10lan) || 993 (hw->mac.type == e1000_pchlan) || 994 (hw->mac.type == e1000_pch2lan) || 995 (hw->mac.type == e1000_pch_lpt)) { 996 int rid = EM_BAR_TYPE_FLASH; 997 sc->flash = bus_alloc_resource_any(dev, 998 SYS_RES_MEMORY, &rid, RF_ACTIVE); 999 if (sc->flash == NULL) { 1000 device_printf(dev, "Mapping of Flash failed\n"); 1001 error = ENXIO; 1002 goto err_pci; 1003 } 1004 /* This is used in the shared code */ 1005 hw->flash_address = (u8 *)sc->flash; 1006 sc->osdep.flash_bus_space_tag = 1007 rman_get_bustag(sc->flash); 1008 sc->osdep.flash_bus_space_handle = 1009 rman_get_bushandle(sc->flash); 1010 } 1011 /* 1012 ** In the new SPT device flash is not a 1013 ** separate BAR, rather it is also in BAR0, 1014 ** so use the same tag and an offset handle for the 1015 ** FLASH read/write macros in the shared code. 1016 */ 1017 else if (hw->mac.type >= e1000_pch_spt) { 1018 sc->osdep.flash_bus_space_tag = 1019 sc->osdep.mem_bus_space_tag; 1020 sc->osdep.flash_bus_space_handle = 1021 sc->osdep.mem_bus_space_handle 1022 + E1000_FLASH_BASE_ADDR; 1023 } 1024 1025 /* Do Shared Code initialization */ 1026 error = e1000_setup_init_funcs(hw, true); 1027 if (error) { 1028 device_printf(dev, "Setup of Shared code failed, error %d\n", 1029 error); 1030 error = ENXIO; 1031 goto err_pci; 1032 } 1033 1034 em_setup_msix(ctx); 1035 e1000_get_bus_info(hw); 1036 1037 /* Set up some sysctls for the tunable interrupt delays */ 1038 em_add_int_delay_sysctl(sc, "rx_int_delay", 1039 "receive interrupt delay in usecs", &sc->rx_int_delay, 1040 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1041 em_add_int_delay_sysctl(sc, "tx_int_delay", 1042 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1043 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1044 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1045 "receive interrupt delay limit in usecs", 1046 &sc->rx_abs_int_delay, 1047 E1000_REGISTER(hw, E1000_RADV), 1048 em_rx_abs_int_delay_dflt); 1049 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1050 "transmit interrupt delay limit in usecs", 1051 &sc->tx_abs_int_delay, 1052 E1000_REGISTER(hw, E1000_TADV), 1053 em_tx_abs_int_delay_dflt); 1054 em_add_int_delay_sysctl(sc, "itr", 1055 "interrupt delay limit in usecs/4", 1056 &sc->tx_itr, 1057 E1000_REGISTER(hw, E1000_ITR), 1058 DEFAULT_ITR); 1059 1060 hw->mac.autoneg = DO_AUTO_NEG; 1061 hw->phy.autoneg_wait_to_complete = false; 1062 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1063 1064 if (hw->mac.type < em_mac_min) { 1065 e1000_init_script_state_82541(hw, true); 1066 e1000_set_tbi_compatibility_82543(hw, true); 1067 } 1068 /* Copper options */ 1069 if (hw->phy.media_type == e1000_media_type_copper) { 1070 hw->phy.mdix = AUTO_ALL_MODES; 1071 hw->phy.disable_polarity_correction = false; 1072 hw->phy.ms_type = EM_MASTER_SLAVE; 1073 } 1074 1075 /* 1076 * Set the frame limits assuming 1077 * standard ethernet sized frames. 1078 */ 1079 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1080 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1081 1082 /* 1083 * This controls when hardware reports transmit completion 1084 * status. 1085 */ 1086 hw->mac.report_tx_early = 1; 1087 1088 /* Allocate multicast array memory. */ 1089 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1090 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1091 if (sc->mta == NULL) { 1092 device_printf(dev, "Can not allocate multicast setup array\n"); 1093 error = ENOMEM; 1094 goto err_late; 1095 } 1096 1097 /* Clear the IFCAP_TSO auto mask */ 1098 sc->tso_automasked = 0; 1099 1100 /* Check SOL/IDER usage */ 1101 if (e1000_check_reset_block(hw)) 1102 device_printf(dev, "PHY reset is blocked" 1103 " due to SOL/IDER session.\n"); 1104 1105 /* Sysctl for setting Energy Efficient Ethernet */ 1106 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1107 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1108 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1109 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1110 1111 /* 1112 ** Start from a known state, this is 1113 ** important in reading the nvm and 1114 ** mac from that. 1115 */ 1116 e1000_reset_hw(hw); 1117 1118 /* Make sure we have a good EEPROM before we read from it */ 1119 if (e1000_validate_nvm_checksum(hw) < 0) { 1120 /* 1121 ** Some PCI-E parts fail the first check due to 1122 ** the link being in sleep state, call it again, 1123 ** if it fails a second time its a real issue. 1124 */ 1125 if (e1000_validate_nvm_checksum(hw) < 0) { 1126 device_printf(dev, 1127 "The EEPROM Checksum Is Not Valid\n"); 1128 error = EIO; 1129 goto err_late; 1130 } 1131 } 1132 1133 /* Copy the permanent MAC address out of the EEPROM */ 1134 if (e1000_read_mac_addr(hw) < 0) { 1135 device_printf(dev, "EEPROM read error while reading MAC" 1136 " address\n"); 1137 error = EIO; 1138 goto err_late; 1139 } 1140 1141 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1142 if (sc->vf_ifp) { 1143 ether_gen_addr(iflib_get_ifp(ctx), 1144 (struct ether_addr *)hw->mac.addr); 1145 } else { 1146 device_printf(dev, "Invalid MAC address\n"); 1147 error = EIO; 1148 goto err_late; 1149 } 1150 } 1151 1152 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1153 em_fw_version_locked(ctx); 1154 1155 em_print_fw_version(sc); 1156 1157 /* 1158 * Get Wake-on-Lan and Management info for later use 1159 */ 1160 em_get_wakeup(ctx); 1161 1162 /* Enable only WOL MAGIC by default */ 1163 scctx->isc_capenable &= ~IFCAP_WOL; 1164 if (sc->wol != 0) 1165 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1166 1167 iflib_set_mac(ctx, hw->mac.addr); 1168 1169 return (0); 1170 1171 err_late: 1172 em_release_hw_control(sc); 1173 err_pci: 1174 em_free_pci_resources(ctx); 1175 free(sc->mta, M_DEVBUF); 1176 1177 return (error); 1178 } 1179 1180 static int 1181 em_if_attach_post(if_ctx_t ctx) 1182 { 1183 struct e1000_softc *sc = iflib_get_softc(ctx); 1184 struct e1000_hw *hw = &sc->hw; 1185 int error = 0; 1186 1187 /* Setup OS specific network interface */ 1188 error = em_setup_interface(ctx); 1189 if (error != 0) { 1190 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1191 goto err_late; 1192 } 1193 1194 em_reset(ctx); 1195 1196 /* Initialize statistics */ 1197 em_update_stats_counters(sc); 1198 hw->mac.get_link_status = 1; 1199 em_if_update_admin_status(ctx); 1200 em_add_hw_stats(sc); 1201 1202 /* Non-AMT based hardware can now take control from firmware */ 1203 if (sc->has_manage && !sc->has_amt) 1204 em_get_hw_control(sc); 1205 1206 INIT_DEBUGOUT("em_if_attach_post: end"); 1207 1208 return (0); 1209 1210 err_late: 1211 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1212 return (error); 1213 } 1214 1215 /********************************************************************* 1216 * Device removal routine 1217 * 1218 * The detach entry point is called when the driver is being removed. 1219 * This routine stops the adapter and deallocates all the resources 1220 * that were allocated for driver operation. 1221 * 1222 * return 0 on success, positive on failure 1223 *********************************************************************/ 1224 static int 1225 em_if_detach(if_ctx_t ctx) 1226 { 1227 struct e1000_softc *sc = iflib_get_softc(ctx); 1228 1229 INIT_DEBUGOUT("em_if_detach: begin"); 1230 1231 e1000_phy_hw_reset(&sc->hw); 1232 1233 em_release_manageability(sc); 1234 em_release_hw_control(sc); 1235 em_free_pci_resources(ctx); 1236 free(sc->mta, M_DEVBUF); 1237 sc->mta = NULL; 1238 1239 return (0); 1240 } 1241 1242 /********************************************************************* 1243 * 1244 * Shutdown entry point 1245 * 1246 **********************************************************************/ 1247 1248 static int 1249 em_if_shutdown(if_ctx_t ctx) 1250 { 1251 return em_if_suspend(ctx); 1252 } 1253 1254 /* 1255 * Suspend/resume device methods. 1256 */ 1257 static int 1258 em_if_suspend(if_ctx_t ctx) 1259 { 1260 struct e1000_softc *sc = iflib_get_softc(ctx); 1261 1262 em_release_manageability(sc); 1263 em_release_hw_control(sc); 1264 em_enable_wakeup(ctx); 1265 return (0); 1266 } 1267 1268 static int 1269 em_if_resume(if_ctx_t ctx) 1270 { 1271 struct e1000_softc *sc = iflib_get_softc(ctx); 1272 1273 if (sc->hw.mac.type == e1000_pch2lan) 1274 e1000_resume_workarounds_pchlan(&sc->hw); 1275 em_if_init(ctx); 1276 em_init_manageability(sc); 1277 1278 return(0); 1279 } 1280 1281 static int 1282 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1283 { 1284 int max_frame_size; 1285 struct e1000_softc *sc = iflib_get_softc(ctx); 1286 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1287 1288 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1289 1290 switch (sc->hw.mac.type) { 1291 case e1000_82571: 1292 case e1000_82572: 1293 case e1000_ich9lan: 1294 case e1000_ich10lan: 1295 case e1000_pch2lan: 1296 case e1000_pch_lpt: 1297 case e1000_pch_spt: 1298 case e1000_pch_cnp: 1299 case e1000_pch_tgp: 1300 case e1000_pch_adp: 1301 case e1000_pch_mtp: 1302 case e1000_pch_ptp: 1303 case e1000_82574: 1304 case e1000_82583: 1305 case e1000_80003es2lan: 1306 /* 9K Jumbo Frame size */ 1307 max_frame_size = 9234; 1308 break; 1309 case e1000_pchlan: 1310 max_frame_size = 4096; 1311 break; 1312 case e1000_82542: 1313 case e1000_ich8lan: 1314 /* Adapters that do not support jumbo frames */ 1315 max_frame_size = ETHER_MAX_LEN; 1316 break; 1317 default: 1318 if (sc->hw.mac.type >= igb_mac_min) 1319 max_frame_size = 9234; 1320 else /* lem */ 1321 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1322 } 1323 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1324 return (EINVAL); 1325 } 1326 1327 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1328 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1329 return (0); 1330 } 1331 1332 /********************************************************************* 1333 * Init entry point 1334 * 1335 * This routine is used in two ways. It is used by the stack as 1336 * init entry point in network interface structure. It is also used 1337 * by the driver as a hw/sw initialization routine to get to a 1338 * consistent state. 1339 * 1340 **********************************************************************/ 1341 static void 1342 em_if_init(if_ctx_t ctx) 1343 { 1344 struct e1000_softc *sc = iflib_get_softc(ctx); 1345 if_softc_ctx_t scctx = sc->shared; 1346 if_t ifp = iflib_get_ifp(ctx); 1347 struct em_tx_queue *tx_que; 1348 int i; 1349 1350 INIT_DEBUGOUT("em_if_init: begin"); 1351 1352 /* Get the latest mac address, User can use a LAA */ 1353 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1354 ETHER_ADDR_LEN); 1355 1356 /* Put the address into the Receive Address Array */ 1357 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1358 1359 /* 1360 * With the 82571 adapter, RAR[0] may be overwritten 1361 * when the other port is reset, we make a duplicate 1362 * in RAR[14] for that eventuality, this assures 1363 * the interface continues to function. 1364 */ 1365 if (sc->hw.mac.type == e1000_82571) { 1366 e1000_set_laa_state_82571(&sc->hw, true); 1367 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1368 E1000_RAR_ENTRIES - 1); 1369 } 1370 1371 /* Initialize the hardware */ 1372 em_reset(ctx); 1373 em_if_update_admin_status(ctx); 1374 1375 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1376 struct tx_ring *txr = &tx_que->txr; 1377 1378 txr->tx_rs_cidx = txr->tx_rs_pidx; 1379 1380 /* Initialize the last processed descriptor to be the end of 1381 * the ring, rather than the start, so that we avoid an 1382 * off-by-one error when calculating how many descriptors are 1383 * done in the credits_update function. 1384 */ 1385 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1386 } 1387 1388 /* Setup VLAN support, basic and offload if available */ 1389 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1390 1391 /* Clear bad data from Rx FIFOs */ 1392 if (sc->hw.mac.type >= igb_mac_min) 1393 e1000_rx_fifo_flush_base(&sc->hw); 1394 1395 /* Configure for OS presence */ 1396 em_init_manageability(sc); 1397 1398 /* Prepare transmit descriptors and buffers */ 1399 em_initialize_transmit_unit(ctx); 1400 1401 /* Setup Multicast table */ 1402 em_if_multi_set(ctx); 1403 1404 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1405 em_initialize_receive_unit(ctx); 1406 1407 /* Set up VLAN support and filter */ 1408 em_setup_vlan_hw_support(ctx); 1409 1410 /* Don't lose promiscuous settings */ 1411 em_if_set_promisc(ctx, if_getflags(ifp)); 1412 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1413 1414 /* MSI-X configuration for 82574 */ 1415 if (sc->hw.mac.type == e1000_82574) { 1416 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1417 1418 tmp |= E1000_CTRL_EXT_PBA_CLR; 1419 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1420 /* Set the IVAR - interrupt vector routing. */ 1421 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1422 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1423 igb_configure_queues(sc); 1424 1425 /* this clears any pending interrupts */ 1426 E1000_READ_REG(&sc->hw, E1000_ICR); 1427 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1428 1429 /* AMT based hardware can now take control from firmware */ 1430 if (sc->has_manage && sc->has_amt) 1431 em_get_hw_control(sc); 1432 1433 /* Set Energy Efficient Ethernet */ 1434 if (sc->hw.mac.type >= igb_mac_min && 1435 sc->hw.phy.media_type == e1000_media_type_copper) { 1436 if (sc->hw.mac.type == e1000_i354) 1437 e1000_set_eee_i354(&sc->hw, true, true); 1438 else 1439 e1000_set_eee_i350(&sc->hw, true, true); 1440 } 1441 } 1442 1443 /********************************************************************* 1444 * 1445 * Fast Legacy/MSI Combined Interrupt Service routine 1446 * 1447 *********************************************************************/ 1448 int 1449 em_intr(void *arg) 1450 { 1451 struct e1000_softc *sc = arg; 1452 if_ctx_t ctx = sc->ctx; 1453 u32 reg_icr; 1454 1455 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1456 1457 /* Hot eject? */ 1458 if (reg_icr == 0xffffffff) 1459 return FILTER_STRAY; 1460 1461 /* Definitely not our interrupt. */ 1462 if (reg_icr == 0x0) 1463 return FILTER_STRAY; 1464 1465 /* 1466 * Starting with the 82571 chip, bit 31 should be used to 1467 * determine whether the interrupt belongs to us. 1468 */ 1469 if (sc->hw.mac.type >= e1000_82571 && 1470 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1471 return FILTER_STRAY; 1472 1473 /* 1474 * Only MSI-X interrupts have one-shot behavior by taking advantage 1475 * of the EIAC register. Thus, explicitly disable interrupts. This 1476 * also works around the MSI message reordering errata on certain 1477 * systems. 1478 */ 1479 IFDI_INTR_DISABLE(ctx); 1480 1481 /* Link status change */ 1482 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1483 em_handle_link(ctx); 1484 1485 if (reg_icr & E1000_ICR_RXO) 1486 sc->rx_overruns++; 1487 1488 return (FILTER_SCHEDULE_THREAD); 1489 } 1490 1491 static int 1492 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1493 { 1494 struct e1000_softc *sc = iflib_get_softc(ctx); 1495 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1496 1497 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1498 return (0); 1499 } 1500 1501 static int 1502 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1503 { 1504 struct e1000_softc *sc = iflib_get_softc(ctx); 1505 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1506 1507 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1508 return (0); 1509 } 1510 1511 static int 1512 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1513 { 1514 struct e1000_softc *sc = iflib_get_softc(ctx); 1515 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1516 1517 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1518 return (0); 1519 } 1520 1521 static int 1522 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1523 { 1524 struct e1000_softc *sc = iflib_get_softc(ctx); 1525 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1526 1527 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1528 return (0); 1529 } 1530 1531 /********************************************************************* 1532 * 1533 * MSI-X RX Interrupt Service routine 1534 * 1535 **********************************************************************/ 1536 static int 1537 em_msix_que(void *arg) 1538 { 1539 struct em_rx_queue *que = arg; 1540 1541 ++que->irqs; 1542 1543 return (FILTER_SCHEDULE_THREAD); 1544 } 1545 1546 /********************************************************************* 1547 * 1548 * MSI-X Link Fast Interrupt Service routine 1549 * 1550 **********************************************************************/ 1551 static int 1552 em_msix_link(void *arg) 1553 { 1554 struct e1000_softc *sc = arg; 1555 u32 reg_icr; 1556 1557 ++sc->link_irq; 1558 MPASS(sc->hw.back != NULL); 1559 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1560 1561 if (reg_icr & E1000_ICR_RXO) 1562 sc->rx_overruns++; 1563 1564 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1565 em_handle_link(sc->ctx); 1566 1567 /* Re-arm unconditionally */ 1568 if (sc->hw.mac.type >= igb_mac_min) { 1569 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1570 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1571 } else if (sc->hw.mac.type == e1000_82574) { 1572 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1573 E1000_IMS_OTHER); 1574 /* 1575 * Because we must read the ICR for this interrupt it may 1576 * clear other causes using autoclear, for this reason we 1577 * simply create a soft interrupt for all these vectors. 1578 */ 1579 if (reg_icr) 1580 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1581 } else 1582 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1583 1584 return (FILTER_HANDLED); 1585 } 1586 1587 static void 1588 em_handle_link(void *context) 1589 { 1590 if_ctx_t ctx = context; 1591 struct e1000_softc *sc = iflib_get_softc(ctx); 1592 1593 sc->hw.mac.get_link_status = 1; 1594 iflib_admin_intr_deferred(ctx); 1595 } 1596 1597 /********************************************************************* 1598 * 1599 * Media Ioctl callback 1600 * 1601 * This routine is called whenever the user queries the status of 1602 * the interface using ifconfig. 1603 * 1604 **********************************************************************/ 1605 static void 1606 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1607 { 1608 struct e1000_softc *sc = iflib_get_softc(ctx); 1609 u_char fiber_type = IFM_1000_SX; 1610 1611 INIT_DEBUGOUT("em_if_media_status: begin"); 1612 1613 iflib_admin_intr_deferred(ctx); 1614 1615 ifmr->ifm_status = IFM_AVALID; 1616 ifmr->ifm_active = IFM_ETHER; 1617 1618 if (!sc->link_active) { 1619 return; 1620 } 1621 1622 ifmr->ifm_status |= IFM_ACTIVE; 1623 1624 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1625 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1626 if (sc->hw.mac.type == e1000_82545) 1627 fiber_type = IFM_1000_LX; 1628 ifmr->ifm_active |= fiber_type | IFM_FDX; 1629 } else { 1630 switch (sc->link_speed) { 1631 case 10: 1632 ifmr->ifm_active |= IFM_10_T; 1633 break; 1634 case 100: 1635 ifmr->ifm_active |= IFM_100_TX; 1636 break; 1637 case 1000: 1638 ifmr->ifm_active |= IFM_1000_T; 1639 break; 1640 } 1641 if (sc->link_duplex == FULL_DUPLEX) 1642 ifmr->ifm_active |= IFM_FDX; 1643 else 1644 ifmr->ifm_active |= IFM_HDX; 1645 } 1646 } 1647 1648 /********************************************************************* 1649 * 1650 * Media Ioctl callback 1651 * 1652 * This routine is called when the user changes speed/duplex using 1653 * media/mediopt option with ifconfig. 1654 * 1655 **********************************************************************/ 1656 static int 1657 em_if_media_change(if_ctx_t ctx) 1658 { 1659 struct e1000_softc *sc = iflib_get_softc(ctx); 1660 struct ifmedia *ifm = iflib_get_media(ctx); 1661 1662 INIT_DEBUGOUT("em_if_media_change: begin"); 1663 1664 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1665 return (EINVAL); 1666 1667 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1668 case IFM_AUTO: 1669 sc->hw.mac.autoneg = DO_AUTO_NEG; 1670 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1671 break; 1672 case IFM_1000_LX: 1673 case IFM_1000_SX: 1674 case IFM_1000_T: 1675 sc->hw.mac.autoneg = DO_AUTO_NEG; 1676 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1677 break; 1678 case IFM_100_TX: 1679 sc->hw.mac.autoneg = false; 1680 sc->hw.phy.autoneg_advertised = 0; 1681 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1682 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1683 else 1684 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1685 break; 1686 case IFM_10_T: 1687 sc->hw.mac.autoneg = false; 1688 sc->hw.phy.autoneg_advertised = 0; 1689 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1690 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1691 else 1692 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1693 break; 1694 default: 1695 device_printf(sc->dev, "Unsupported media type\n"); 1696 } 1697 1698 em_if_init(ctx); 1699 1700 return (0); 1701 } 1702 1703 static int 1704 em_if_set_promisc(if_ctx_t ctx, int flags) 1705 { 1706 struct e1000_softc *sc = iflib_get_softc(ctx); 1707 if_t ifp = iflib_get_ifp(ctx); 1708 u32 reg_rctl; 1709 int mcnt = 0; 1710 1711 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1712 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1713 if (flags & IFF_ALLMULTI) 1714 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1715 else 1716 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1717 1718 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1719 reg_rctl &= (~E1000_RCTL_MPE); 1720 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1721 1722 if (flags & IFF_PROMISC) { 1723 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1724 em_if_vlan_filter_disable(sc); 1725 /* Turn this on if you want to see bad packets */ 1726 if (em_debug_sbp) 1727 reg_rctl |= E1000_RCTL_SBP; 1728 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1729 } else { 1730 if (flags & IFF_ALLMULTI) { 1731 reg_rctl |= E1000_RCTL_MPE; 1732 reg_rctl &= ~E1000_RCTL_UPE; 1733 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1734 } 1735 if (em_if_vlan_filter_used(ctx)) 1736 em_if_vlan_filter_enable(sc); 1737 } 1738 return (0); 1739 } 1740 1741 static u_int 1742 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1743 { 1744 u8 *mta = arg; 1745 1746 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1747 return (0); 1748 1749 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1750 1751 return (1); 1752 } 1753 1754 /********************************************************************* 1755 * Multicast Update 1756 * 1757 * This routine is called whenever multicast address list is updated. 1758 * 1759 **********************************************************************/ 1760 static void 1761 em_if_multi_set(if_ctx_t ctx) 1762 { 1763 struct e1000_softc *sc = iflib_get_softc(ctx); 1764 if_t ifp = iflib_get_ifp(ctx); 1765 u8 *mta; /* Multicast array memory */ 1766 u32 reg_rctl = 0; 1767 int mcnt = 0; 1768 1769 IOCTL_DEBUGOUT("em_set_multi: begin"); 1770 1771 mta = sc->mta; 1772 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1773 1774 if (sc->hw.mac.type == e1000_82542 && 1775 sc->hw.revision_id == E1000_REVISION_2) { 1776 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1777 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1778 e1000_pci_clear_mwi(&sc->hw); 1779 reg_rctl |= E1000_RCTL_RST; 1780 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1781 msec_delay(5); 1782 } 1783 1784 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1785 1786 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1787 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1788 1789 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1790 1791 if (if_getflags(ifp) & IFF_PROMISC) 1792 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1793 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1794 if_getflags(ifp) & IFF_ALLMULTI) { 1795 reg_rctl |= E1000_RCTL_MPE; 1796 reg_rctl &= ~E1000_RCTL_UPE; 1797 } else 1798 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1799 1800 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1801 1802 if (sc->hw.mac.type == e1000_82542 && 1803 sc->hw.revision_id == E1000_REVISION_2) { 1804 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1805 reg_rctl &= ~E1000_RCTL_RST; 1806 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1807 msec_delay(5); 1808 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1809 e1000_pci_set_mwi(&sc->hw); 1810 } 1811 } 1812 1813 /********************************************************************* 1814 * Timer routine 1815 * 1816 * This routine schedules em_if_update_admin_status() to check for 1817 * link status and to gather statistics as well as to perform some 1818 * controller-specific hardware patting. 1819 * 1820 **********************************************************************/ 1821 static void 1822 em_if_timer(if_ctx_t ctx, uint16_t qid) 1823 { 1824 1825 if (qid != 0) 1826 return; 1827 1828 iflib_admin_intr_deferred(ctx); 1829 } 1830 1831 static void 1832 em_if_update_admin_status(if_ctx_t ctx) 1833 { 1834 struct e1000_softc *sc = iflib_get_softc(ctx); 1835 struct e1000_hw *hw = &sc->hw; 1836 device_t dev = iflib_get_dev(ctx); 1837 u32 link_check, thstat, ctrl; 1838 bool automasked = false; 1839 1840 link_check = thstat = ctrl = 0; 1841 /* Get the cached link value or read phy for real */ 1842 switch (hw->phy.media_type) { 1843 case e1000_media_type_copper: 1844 if (hw->mac.get_link_status) { 1845 if (hw->mac.type == e1000_pch_spt) 1846 msec_delay(50); 1847 /* Do the work to read phy */ 1848 e1000_check_for_link(hw); 1849 link_check = !hw->mac.get_link_status; 1850 if (link_check) /* ESB2 fix */ 1851 e1000_cfg_on_link_up(hw); 1852 } else { 1853 link_check = true; 1854 } 1855 break; 1856 case e1000_media_type_fiber: 1857 e1000_check_for_link(hw); 1858 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1859 E1000_STATUS_LU); 1860 break; 1861 case e1000_media_type_internal_serdes: 1862 e1000_check_for_link(hw); 1863 link_check = hw->mac.serdes_has_link; 1864 break; 1865 /* VF device is type_unknown */ 1866 case e1000_media_type_unknown: 1867 e1000_check_for_link(hw); 1868 link_check = !hw->mac.get_link_status; 1869 /* FALLTHROUGH */ 1870 default: 1871 break; 1872 } 1873 1874 /* Check for thermal downshift or shutdown */ 1875 if (hw->mac.type == e1000_i350) { 1876 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1877 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1878 } 1879 1880 /* Now check for a transition */ 1881 if (link_check && (sc->link_active == 0)) { 1882 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1883 &sc->link_duplex); 1884 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1885 if ((sc->link_speed != SPEED_1000) && 1886 ((hw->mac.type == e1000_82571) || 1887 (hw->mac.type == e1000_82572))) { 1888 int tarc0; 1889 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1890 tarc0 &= ~TARC_SPEED_MODE_BIT; 1891 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1892 } 1893 if (bootverbose) 1894 device_printf(dev, "Link is up %d Mbps %s\n", 1895 sc->link_speed, 1896 ((sc->link_duplex == FULL_DUPLEX) ? 1897 "Full Duplex" : "Half Duplex")); 1898 sc->link_active = 1; 1899 sc->smartspeed = 0; 1900 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1901 E1000_CTRL_EXT_LINK_MODE_GMII && 1902 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1903 device_printf(dev, "Link: thermal downshift\n"); 1904 /* Delay Link Up for Phy update */ 1905 if (((hw->mac.type == e1000_i210) || 1906 (hw->mac.type == e1000_i211)) && 1907 (hw->phy.id == I210_I_PHY_ID)) 1908 msec_delay(I210_LINK_DELAY); 1909 /* Reset if the media type changed. */ 1910 if (hw->dev_spec._82575.media_changed && 1911 hw->mac.type >= igb_mac_min) { 1912 hw->dev_spec._82575.media_changed = false; 1913 sc->flags |= IGB_MEDIA_RESET; 1914 em_reset(ctx); 1915 } 1916 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 1917 if (hw->mac.type < igb_mac_min) 1918 automasked = em_automask_tso(ctx); 1919 1920 /* Automasking resets the interface, so don't mark it up yet */ 1921 if (!automasked) 1922 iflib_link_state_change(ctx, LINK_STATE_UP, 1923 IF_Mbps(sc->link_speed)); 1924 } else if (!link_check && (sc->link_active == 1)) { 1925 sc->link_speed = 0; 1926 sc->link_duplex = 0; 1927 sc->link_active = 0; 1928 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1929 } 1930 em_update_stats_counters(sc); 1931 1932 /* Reset LAA into RAR[0] on 82571 */ 1933 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1934 e1000_rar_set(hw, hw->mac.addr, 0); 1935 1936 if (hw->mac.type < em_mac_min) 1937 lem_smartspeed(sc); 1938 } 1939 1940 static void 1941 em_if_watchdog_reset(if_ctx_t ctx) 1942 { 1943 struct e1000_softc *sc = iflib_get_softc(ctx); 1944 1945 /* 1946 * Just count the event; iflib(4) will already trigger a 1947 * sufficient reset of the controller. 1948 */ 1949 sc->watchdog_events++; 1950 } 1951 1952 /********************************************************************* 1953 * 1954 * This routine disables all traffic on the adapter by issuing a 1955 * global reset on the MAC. 1956 * 1957 **********************************************************************/ 1958 static void 1959 em_if_stop(if_ctx_t ctx) 1960 { 1961 struct e1000_softc *sc = iflib_get_softc(ctx); 1962 1963 INIT_DEBUGOUT("em_if_stop: begin"); 1964 1965 /* I219 needs special flushing to avoid hangs */ 1966 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1967 em_flush_desc_rings(sc); 1968 1969 e1000_reset_hw(&sc->hw); 1970 if (sc->hw.mac.type >= e1000_82544) 1971 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1972 1973 e1000_led_off(&sc->hw); 1974 e1000_cleanup_led(&sc->hw); 1975 } 1976 1977 /********************************************************************* 1978 * 1979 * Determine hardware revision. 1980 * 1981 **********************************************************************/ 1982 static void 1983 em_identify_hardware(if_ctx_t ctx) 1984 { 1985 device_t dev = iflib_get_dev(ctx); 1986 struct e1000_softc *sc = iflib_get_softc(ctx); 1987 1988 /* Make sure our PCI config space has the necessary stuff set */ 1989 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1990 1991 /* Save off the information about this board */ 1992 sc->hw.vendor_id = pci_get_vendor(dev); 1993 sc->hw.device_id = pci_get_device(dev); 1994 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1995 sc->hw.subsystem_vendor_id = 1996 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1997 sc->hw.subsystem_device_id = 1998 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1999 2000 /* Do Shared Code Init and Setup */ 2001 if (e1000_set_mac_type(&sc->hw)) { 2002 device_printf(dev, "Setup init failure\n"); 2003 return; 2004 } 2005 2006 /* Are we a VF device? */ 2007 if ((sc->hw.mac.type == e1000_vfadapt) || 2008 (sc->hw.mac.type == e1000_vfadapt_i350)) 2009 sc->vf_ifp = 1; 2010 else 2011 sc->vf_ifp = 0; 2012 } 2013 2014 static int 2015 em_allocate_pci_resources(if_ctx_t ctx) 2016 { 2017 struct e1000_softc *sc = iflib_get_softc(ctx); 2018 device_t dev = iflib_get_dev(ctx); 2019 int rid, val; 2020 2021 rid = PCIR_BAR(0); 2022 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2023 &rid, RF_ACTIVE); 2024 if (sc->memory == NULL) { 2025 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2026 return (ENXIO); 2027 } 2028 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2029 sc->osdep.mem_bus_space_handle = 2030 rman_get_bushandle(sc->memory); 2031 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2032 2033 /* Only older adapters use IO mapping */ 2034 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2035 /* Figure our where our IO BAR is ? */ 2036 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2037 val = pci_read_config(dev, rid, 4); 2038 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2039 break; 2040 } 2041 rid += 4; 2042 /* check for 64bit BAR */ 2043 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2044 rid += 4; 2045 } 2046 if (rid >= PCIR_CIS) { 2047 device_printf(dev, "Unable to locate IO BAR\n"); 2048 return (ENXIO); 2049 } 2050 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2051 &rid, RF_ACTIVE); 2052 if (sc->ioport == NULL) { 2053 device_printf(dev, "Unable to allocate bus resource: " 2054 "ioport\n"); 2055 return (ENXIO); 2056 } 2057 sc->hw.io_base = 0; 2058 sc->osdep.io_bus_space_tag = 2059 rman_get_bustag(sc->ioport); 2060 sc->osdep.io_bus_space_handle = 2061 rman_get_bushandle(sc->ioport); 2062 } 2063 2064 sc->hw.back = &sc->osdep; 2065 2066 return (0); 2067 } 2068 2069 /********************************************************************* 2070 * 2071 * Set up the MSI-X Interrupt handlers 2072 * 2073 **********************************************************************/ 2074 static int 2075 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2076 { 2077 struct e1000_softc *sc = iflib_get_softc(ctx); 2078 struct em_rx_queue *rx_que = sc->rx_queues; 2079 struct em_tx_queue *tx_que = sc->tx_queues; 2080 int error, rid, i, vector = 0, rx_vectors; 2081 char buf[16]; 2082 2083 /* First set up ring resources */ 2084 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2085 rid = vector + 1; 2086 snprintf(buf, sizeof(buf), "rxq%d", i); 2087 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2088 if (error) { 2089 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2090 sc->rx_num_queues = i + 1; 2091 goto fail; 2092 } 2093 2094 rx_que->msix = vector; 2095 2096 /* 2097 * Set the bit to enable interrupt 2098 * in E1000_IMS -- bits 20 and 21 2099 * are for RX0 and RX1, note this has 2100 * NOTHING to do with the MSI-X vector 2101 */ 2102 if (sc->hw.mac.type == e1000_82574) { 2103 rx_que->eims = 1 << (20 + i); 2104 sc->ims |= rx_que->eims; 2105 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2106 } else if (sc->hw.mac.type == e1000_82575) 2107 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2108 else 2109 rx_que->eims = 1 << vector; 2110 } 2111 rx_vectors = vector; 2112 2113 vector = 0; 2114 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2115 snprintf(buf, sizeof(buf), "txq%d", i); 2116 tx_que = &sc->tx_queues[i]; 2117 iflib_softirq_alloc_generic(ctx, 2118 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2119 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2120 2121 tx_que->msix = (vector % sc->rx_num_queues); 2122 2123 /* 2124 * Set the bit to enable interrupt 2125 * in E1000_IMS -- bits 22 and 23 2126 * are for TX0 and TX1, note this has 2127 * NOTHING to do with the MSI-X vector 2128 */ 2129 if (sc->hw.mac.type == e1000_82574) { 2130 tx_que->eims = 1 << (22 + i); 2131 sc->ims |= tx_que->eims; 2132 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2133 } else if (sc->hw.mac.type == e1000_82575) { 2134 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2135 } else { 2136 tx_que->eims = 1 << i; 2137 } 2138 } 2139 2140 /* Link interrupt */ 2141 rid = rx_vectors + 1; 2142 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2143 2144 if (error) { 2145 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2146 goto fail; 2147 } 2148 sc->linkvec = rx_vectors; 2149 if (sc->hw.mac.type < igb_mac_min) { 2150 sc->ivars |= (8 | rx_vectors) << 16; 2151 sc->ivars |= 0x80000000; 2152 /* Enable the "Other" interrupt type for link status change */ 2153 sc->ims |= E1000_IMS_OTHER; 2154 } 2155 2156 return (0); 2157 fail: 2158 iflib_irq_free(ctx, &sc->irq); 2159 rx_que = sc->rx_queues; 2160 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2161 iflib_irq_free(ctx, &rx_que->que_irq); 2162 return (error); 2163 } 2164 2165 static void 2166 igb_configure_queues(struct e1000_softc *sc) 2167 { 2168 struct e1000_hw *hw = &sc->hw; 2169 struct em_rx_queue *rx_que; 2170 struct em_tx_queue *tx_que; 2171 u32 tmp, ivar = 0, newitr = 0; 2172 2173 /* First turn on RSS capability */ 2174 if (hw->mac.type != e1000_82575) 2175 E1000_WRITE_REG(hw, E1000_GPIE, 2176 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2177 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2178 2179 /* Turn on MSI-X */ 2180 switch (hw->mac.type) { 2181 case e1000_82580: 2182 case e1000_i350: 2183 case e1000_i354: 2184 case e1000_i210: 2185 case e1000_i211: 2186 case e1000_vfadapt: 2187 case e1000_vfadapt_i350: 2188 /* RX entries */ 2189 for (int i = 0; i < sc->rx_num_queues; i++) { 2190 u32 index = i >> 1; 2191 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2192 rx_que = &sc->rx_queues[i]; 2193 if (i & 1) { 2194 ivar &= 0xFF00FFFF; 2195 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2196 } else { 2197 ivar &= 0xFFFFFF00; 2198 ivar |= rx_que->msix | E1000_IVAR_VALID; 2199 } 2200 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2201 } 2202 /* TX entries */ 2203 for (int i = 0; i < sc->tx_num_queues; i++) { 2204 u32 index = i >> 1; 2205 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2206 tx_que = &sc->tx_queues[i]; 2207 if (i & 1) { 2208 ivar &= 0x00FFFFFF; 2209 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2210 } else { 2211 ivar &= 0xFFFF00FF; 2212 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2213 } 2214 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2215 sc->que_mask |= tx_que->eims; 2216 } 2217 2218 /* And for the link interrupt */ 2219 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2220 sc->link_mask = 1 << sc->linkvec; 2221 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2222 break; 2223 case e1000_82576: 2224 /* RX entries */ 2225 for (int i = 0; i < sc->rx_num_queues; i++) { 2226 u32 index = i & 0x7; /* Each IVAR has two entries */ 2227 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2228 rx_que = &sc->rx_queues[i]; 2229 if (i < 8) { 2230 ivar &= 0xFFFFFF00; 2231 ivar |= rx_que->msix | E1000_IVAR_VALID; 2232 } else { 2233 ivar &= 0xFF00FFFF; 2234 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2235 } 2236 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2237 sc->que_mask |= rx_que->eims; 2238 } 2239 /* TX entries */ 2240 for (int i = 0; i < sc->tx_num_queues; i++) { 2241 u32 index = i & 0x7; /* Each IVAR has two entries */ 2242 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2243 tx_que = &sc->tx_queues[i]; 2244 if (i < 8) { 2245 ivar &= 0xFFFF00FF; 2246 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2247 } else { 2248 ivar &= 0x00FFFFFF; 2249 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2250 } 2251 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2252 sc->que_mask |= tx_que->eims; 2253 } 2254 2255 /* And for the link interrupt */ 2256 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2257 sc->link_mask = 1 << sc->linkvec; 2258 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2259 break; 2260 2261 case e1000_82575: 2262 /* enable MSI-X support*/ 2263 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2264 tmp |= E1000_CTRL_EXT_PBA_CLR; 2265 /* Auto-Mask interrupts upon ICR read. */ 2266 tmp |= E1000_CTRL_EXT_EIAME; 2267 tmp |= E1000_CTRL_EXT_IRCA; 2268 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2269 2270 /* Queues */ 2271 for (int i = 0; i < sc->rx_num_queues; i++) { 2272 rx_que = &sc->rx_queues[i]; 2273 tmp = E1000_EICR_RX_QUEUE0 << i; 2274 tmp |= E1000_EICR_TX_QUEUE0 << i; 2275 rx_que->eims = tmp; 2276 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2277 i, rx_que->eims); 2278 sc->que_mask |= rx_que->eims; 2279 } 2280 2281 /* Link */ 2282 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2283 E1000_EIMS_OTHER); 2284 sc->link_mask |= E1000_EIMS_OTHER; 2285 default: 2286 break; 2287 } 2288 2289 /* Set the starting interrupt rate */ 2290 if (em_max_interrupt_rate > 0) 2291 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2292 2293 if (hw->mac.type == e1000_82575) 2294 newitr |= newitr << 16; 2295 else 2296 newitr |= E1000_EITR_CNT_IGNR; 2297 2298 for (int i = 0; i < sc->rx_num_queues; i++) { 2299 rx_que = &sc->rx_queues[i]; 2300 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2301 } 2302 2303 return; 2304 } 2305 2306 static void 2307 em_free_pci_resources(if_ctx_t ctx) 2308 { 2309 struct e1000_softc *sc = iflib_get_softc(ctx); 2310 struct em_rx_queue *que = sc->rx_queues; 2311 device_t dev = iflib_get_dev(ctx); 2312 2313 /* Release all MSI-X queue resources */ 2314 if (sc->intr_type == IFLIB_INTR_MSIX) 2315 iflib_irq_free(ctx, &sc->irq); 2316 2317 if (que != NULL) { 2318 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2319 iflib_irq_free(ctx, &que->que_irq); 2320 } 2321 } 2322 2323 if (sc->memory != NULL) { 2324 bus_release_resource(dev, SYS_RES_MEMORY, 2325 rman_get_rid(sc->memory), sc->memory); 2326 sc->memory = NULL; 2327 } 2328 2329 if (sc->flash != NULL) { 2330 bus_release_resource(dev, SYS_RES_MEMORY, 2331 rman_get_rid(sc->flash), sc->flash); 2332 sc->flash = NULL; 2333 } 2334 2335 if (sc->ioport != NULL) { 2336 bus_release_resource(dev, SYS_RES_IOPORT, 2337 rman_get_rid(sc->ioport), sc->ioport); 2338 sc->ioport = NULL; 2339 } 2340 } 2341 2342 /* Set up MSI or MSI-X */ 2343 static int 2344 em_setup_msix(if_ctx_t ctx) 2345 { 2346 struct e1000_softc *sc = iflib_get_softc(ctx); 2347 2348 if (sc->hw.mac.type == e1000_82574) { 2349 em_enable_vectors_82574(ctx); 2350 } 2351 return (0); 2352 } 2353 2354 /********************************************************************* 2355 * 2356 * Workaround for SmartSpeed on 82541 and 82547 controllers 2357 * 2358 **********************************************************************/ 2359 static void 2360 lem_smartspeed(struct e1000_softc *sc) 2361 { 2362 u16 phy_tmp; 2363 2364 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2365 sc->hw.mac.autoneg == 0 || 2366 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2367 return; 2368 2369 if (sc->smartspeed == 0) { 2370 /* If Master/Slave config fault is asserted twice, 2371 * we assume back-to-back */ 2372 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2373 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2374 return; 2375 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2376 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2377 e1000_read_phy_reg(&sc->hw, 2378 PHY_1000T_CTRL, &phy_tmp); 2379 if(phy_tmp & CR_1000T_MS_ENABLE) { 2380 phy_tmp &= ~CR_1000T_MS_ENABLE; 2381 e1000_write_phy_reg(&sc->hw, 2382 PHY_1000T_CTRL, phy_tmp); 2383 sc->smartspeed++; 2384 if(sc->hw.mac.autoneg && 2385 !e1000_copper_link_autoneg(&sc->hw) && 2386 !e1000_read_phy_reg(&sc->hw, 2387 PHY_CONTROL, &phy_tmp)) { 2388 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2389 MII_CR_RESTART_AUTO_NEG); 2390 e1000_write_phy_reg(&sc->hw, 2391 PHY_CONTROL, phy_tmp); 2392 } 2393 } 2394 } 2395 return; 2396 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2397 /* If still no link, perhaps using 2/3 pair cable */ 2398 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2399 phy_tmp |= CR_1000T_MS_ENABLE; 2400 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2401 if(sc->hw.mac.autoneg && 2402 !e1000_copper_link_autoneg(&sc->hw) && 2403 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2404 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2405 MII_CR_RESTART_AUTO_NEG); 2406 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2407 } 2408 } 2409 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2410 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2411 sc->smartspeed = 0; 2412 } 2413 2414 /********************************************************************* 2415 * 2416 * Initialize the DMA Coalescing feature 2417 * 2418 **********************************************************************/ 2419 static void 2420 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2421 { 2422 device_t dev = sc->dev; 2423 struct e1000_hw *hw = &sc->hw; 2424 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2425 u16 hwm; 2426 u16 max_frame_size; 2427 2428 if (hw->mac.type == e1000_i211) 2429 return; 2430 2431 max_frame_size = sc->shared->isc_max_frame_size; 2432 if (hw->mac.type > e1000_82580) { 2433 2434 if (sc->dmac == 0) { /* Disabling it */ 2435 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2436 return; 2437 } else 2438 device_printf(dev, "DMA Coalescing enabled\n"); 2439 2440 /* Set starting threshold */ 2441 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2442 2443 hwm = 64 * pba - max_frame_size / 16; 2444 if (hwm < 64 * (pba - 6)) 2445 hwm = 64 * (pba - 6); 2446 reg = E1000_READ_REG(hw, E1000_FCRTC); 2447 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2448 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2449 & E1000_FCRTC_RTH_COAL_MASK); 2450 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2451 2452 2453 dmac = pba - max_frame_size / 512; 2454 if (dmac < pba - 10) 2455 dmac = pba - 10; 2456 reg = E1000_READ_REG(hw, E1000_DMACR); 2457 reg &= ~E1000_DMACR_DMACTHR_MASK; 2458 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2459 & E1000_DMACR_DMACTHR_MASK); 2460 2461 /* transition to L0x or L1 if available..*/ 2462 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2463 2464 /* Check if status is 2.5Gb backplane connection 2465 * before configuration of watchdog timer, which is 2466 * in msec values in 12.8usec intervals 2467 * watchdog timer= msec values in 32usec intervals 2468 * for non 2.5Gb connection 2469 */ 2470 if (hw->mac.type == e1000_i354) { 2471 int status = E1000_READ_REG(hw, E1000_STATUS); 2472 if ((status & E1000_STATUS_2P5_SKU) && 2473 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2474 reg |= ((sc->dmac * 5) >> 6); 2475 else 2476 reg |= (sc->dmac >> 5); 2477 } else { 2478 reg |= (sc->dmac >> 5); 2479 } 2480 2481 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2482 2483 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2484 2485 /* Set the interval before transition */ 2486 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2487 if (hw->mac.type == e1000_i350) 2488 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2489 /* 2490 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2491 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2492 */ 2493 if (hw->mac.type == e1000_i354) { 2494 int status = E1000_READ_REG(hw, E1000_STATUS); 2495 if ((status & E1000_STATUS_2P5_SKU) && 2496 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2497 reg |= 0xA; 2498 else 2499 reg |= 0x4; 2500 } else { 2501 reg |= 0x4; 2502 } 2503 2504 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2505 2506 /* free space in tx packet buffer to wake from DMA coal */ 2507 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2508 (2 * max_frame_size)) >> 6); 2509 2510 /* make low power state decision controlled by DMA coal */ 2511 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2512 reg &= ~E1000_PCIEMISC_LX_DECISION; 2513 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2514 2515 } else if (hw->mac.type == e1000_82580) { 2516 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2517 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2518 reg & ~E1000_PCIEMISC_LX_DECISION); 2519 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2520 } 2521 } 2522 /********************************************************************* 2523 * The 3 following flush routines are used as a workaround in the 2524 * I219 client parts and only for them. 2525 * 2526 * em_flush_tx_ring - remove all descriptors from the tx_ring 2527 * 2528 * We want to clear all pending descriptors from the TX ring. 2529 * zeroing happens when the HW reads the regs. We assign the ring itself as 2530 * the data of the next descriptor. We don't care about the data we are about 2531 * to reset the HW. 2532 **********************************************************************/ 2533 static void 2534 em_flush_tx_ring(struct e1000_softc *sc) 2535 { 2536 struct e1000_hw *hw = &sc->hw; 2537 struct tx_ring *txr = &sc->tx_queues->txr; 2538 struct e1000_tx_desc *txd; 2539 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2540 u16 size = 512; 2541 2542 tctl = E1000_READ_REG(hw, E1000_TCTL); 2543 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2544 2545 txd = &txr->tx_base[txr->tx_cidx_processed]; 2546 2547 /* Just use the ring as a dummy buffer addr */ 2548 txd->buffer_addr = txr->tx_paddr; 2549 txd->lower.data = htole32(txd_lower | size); 2550 txd->upper.data = 0; 2551 2552 /* flush descriptors to memory before notifying the HW */ 2553 wmb(); 2554 2555 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2556 mb(); 2557 usec_delay(250); 2558 } 2559 2560 /********************************************************************* 2561 * em_flush_rx_ring - remove all descriptors from the rx_ring 2562 * 2563 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2564 **********************************************************************/ 2565 static void 2566 em_flush_rx_ring(struct e1000_softc *sc) 2567 { 2568 struct e1000_hw *hw = &sc->hw; 2569 u32 rctl, rxdctl; 2570 2571 rctl = E1000_READ_REG(hw, E1000_RCTL); 2572 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2573 E1000_WRITE_FLUSH(hw); 2574 usec_delay(150); 2575 2576 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2577 /* zero the lower 14 bits (prefetch and host thresholds) */ 2578 rxdctl &= 0xffffc000; 2579 /* 2580 * update thresholds: prefetch threshold to 31, host threshold to 1 2581 * and make sure the granularity is "descriptors" and not "cache lines" 2582 */ 2583 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2584 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2585 2586 /* momentarily enable the RX ring for the changes to take effect */ 2587 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2588 E1000_WRITE_FLUSH(hw); 2589 usec_delay(150); 2590 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2591 } 2592 2593 /********************************************************************* 2594 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2595 * 2596 * In I219, the descriptor rings must be emptied before resetting the HW 2597 * or before changing the device state to D3 during runtime (runtime PM). 2598 * 2599 * Failure to do this will cause the HW to enter a unit hang state which can 2600 * only be released by PCI reset on the device 2601 * 2602 **********************************************************************/ 2603 static void 2604 em_flush_desc_rings(struct e1000_softc *sc) 2605 { 2606 struct e1000_hw *hw = &sc->hw; 2607 device_t dev = sc->dev; 2608 u16 hang_state; 2609 u32 fext_nvm11, tdlen; 2610 2611 /* First, disable MULR fix in FEXTNVM11 */ 2612 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2613 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2614 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2615 2616 /* do nothing if we're not in faulty state, or if the queue is empty */ 2617 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2618 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2619 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2620 return; 2621 em_flush_tx_ring(sc); 2622 2623 /* recheck, maybe the fault is caused by the rx ring */ 2624 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2625 if (hang_state & FLUSH_DESC_REQUIRED) 2626 em_flush_rx_ring(sc); 2627 } 2628 2629 2630 /********************************************************************* 2631 * 2632 * Initialize the hardware to a configuration as specified by the 2633 * sc structure. 2634 * 2635 **********************************************************************/ 2636 static void 2637 em_reset(if_ctx_t ctx) 2638 { 2639 device_t dev = iflib_get_dev(ctx); 2640 struct e1000_softc *sc = iflib_get_softc(ctx); 2641 if_t ifp = iflib_get_ifp(ctx); 2642 struct e1000_hw *hw = &sc->hw; 2643 u32 rx_buffer_size; 2644 u32 pba; 2645 2646 INIT_DEBUGOUT("em_reset: begin"); 2647 /* Let the firmware know the OS is in control */ 2648 em_get_hw_control(sc); 2649 2650 /* Set up smart power down as default off on newer adapters. */ 2651 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2652 hw->mac.type == e1000_82572)) { 2653 u16 phy_tmp = 0; 2654 2655 /* Speed up time to link by disabling smart power down. */ 2656 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2657 phy_tmp &= ~IGP02E1000_PM_SPD; 2658 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2659 } 2660 2661 /* 2662 * Packet Buffer Allocation (PBA) 2663 * Writing PBA sets the receive portion of the buffer 2664 * the remainder is used for the transmit buffer. 2665 */ 2666 switch (hw->mac.type) { 2667 /* 82547: Total Packet Buffer is 40K */ 2668 case e1000_82547: 2669 case e1000_82547_rev_2: 2670 if (hw->mac.max_frame_size > 8192) 2671 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2672 else 2673 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2674 break; 2675 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2676 case e1000_82571: 2677 case e1000_82572: 2678 case e1000_80003es2lan: 2679 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2680 break; 2681 /* 82573: Total Packet Buffer is 32K */ 2682 case e1000_82573: 2683 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2684 break; 2685 case e1000_82574: 2686 case e1000_82583: 2687 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2688 break; 2689 case e1000_ich8lan: 2690 pba = E1000_PBA_8K; 2691 break; 2692 case e1000_ich9lan: 2693 case e1000_ich10lan: 2694 /* Boost Receive side for jumbo frames */ 2695 if (hw->mac.max_frame_size > 4096) 2696 pba = E1000_PBA_14K; 2697 else 2698 pba = E1000_PBA_10K; 2699 break; 2700 case e1000_pchlan: 2701 case e1000_pch2lan: 2702 case e1000_pch_lpt: 2703 case e1000_pch_spt: 2704 case e1000_pch_cnp: 2705 case e1000_pch_tgp: 2706 case e1000_pch_adp: 2707 case e1000_pch_mtp: 2708 case e1000_pch_ptp: 2709 pba = E1000_PBA_26K; 2710 break; 2711 case e1000_82575: 2712 pba = E1000_PBA_32K; 2713 break; 2714 case e1000_82576: 2715 case e1000_vfadapt: 2716 pba = E1000_READ_REG(hw, E1000_RXPBS); 2717 pba &= E1000_RXPBS_SIZE_MASK_82576; 2718 break; 2719 case e1000_82580: 2720 case e1000_i350: 2721 case e1000_i354: 2722 case e1000_vfadapt_i350: 2723 pba = E1000_READ_REG(hw, E1000_RXPBS); 2724 pba = e1000_rxpbs_adjust_82580(pba); 2725 break; 2726 case e1000_i210: 2727 case e1000_i211: 2728 pba = E1000_PBA_34K; 2729 break; 2730 default: 2731 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2732 if (hw->mac.max_frame_size > 8192) 2733 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2734 else 2735 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2736 } 2737 2738 /* Special needs in case of Jumbo frames */ 2739 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2740 u32 tx_space, min_tx, min_rx; 2741 pba = E1000_READ_REG(hw, E1000_PBA); 2742 tx_space = pba >> 16; 2743 pba &= 0xffff; 2744 min_tx = (hw->mac.max_frame_size + 2745 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2746 min_tx = roundup2(min_tx, 1024); 2747 min_tx >>= 10; 2748 min_rx = hw->mac.max_frame_size; 2749 min_rx = roundup2(min_rx, 1024); 2750 min_rx >>= 10; 2751 if (tx_space < min_tx && 2752 ((min_tx - tx_space) < pba)) { 2753 pba = pba - (min_tx - tx_space); 2754 /* 2755 * if short on rx space, rx wins 2756 * and must trump tx adjustment 2757 */ 2758 if (pba < min_rx) 2759 pba = min_rx; 2760 } 2761 E1000_WRITE_REG(hw, E1000_PBA, pba); 2762 } 2763 2764 if (hw->mac.type < igb_mac_min) 2765 E1000_WRITE_REG(hw, E1000_PBA, pba); 2766 2767 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2768 2769 /* 2770 * These parameters control the automatic generation (Tx) and 2771 * response (Rx) to Ethernet PAUSE frames. 2772 * - High water mark should allow for at least two frames to be 2773 * received after sending an XOFF. 2774 * - Low water mark works best when it is very near the high water mark. 2775 * This allows the receiver to restart by sending XON when it has 2776 * drained a bit. Here we use an arbitrary value of 1500 which will 2777 * restart after one full frame is pulled from the buffer. There 2778 * could be several smaller frames in the buffer and if so they will 2779 * not trigger the XON until their total number reduces the buffer 2780 * by 1500. 2781 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2782 */ 2783 rx_buffer_size = (pba & 0xffff) << 10; 2784 hw->fc.high_water = rx_buffer_size - 2785 roundup2(hw->mac.max_frame_size, 1024); 2786 hw->fc.low_water = hw->fc.high_water - 1500; 2787 2788 if (sc->fc) /* locally set flow control value? */ 2789 hw->fc.requested_mode = sc->fc; 2790 else 2791 hw->fc.requested_mode = e1000_fc_full; 2792 2793 if (hw->mac.type == e1000_80003es2lan) 2794 hw->fc.pause_time = 0xFFFF; 2795 else 2796 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2797 2798 hw->fc.send_xon = true; 2799 2800 /* Device specific overrides/settings */ 2801 switch (hw->mac.type) { 2802 case e1000_pchlan: 2803 /* Workaround: no TX flow ctrl for PCH */ 2804 hw->fc.requested_mode = e1000_fc_rx_pause; 2805 hw->fc.pause_time = 0xFFFF; /* override */ 2806 if (if_getmtu(ifp) > ETHERMTU) { 2807 hw->fc.high_water = 0x3500; 2808 hw->fc.low_water = 0x1500; 2809 } else { 2810 hw->fc.high_water = 0x5000; 2811 hw->fc.low_water = 0x3000; 2812 } 2813 hw->fc.refresh_time = 0x1000; 2814 break; 2815 case e1000_pch2lan: 2816 case e1000_pch_lpt: 2817 case e1000_pch_spt: 2818 case e1000_pch_cnp: 2819 case e1000_pch_tgp: 2820 case e1000_pch_adp: 2821 case e1000_pch_mtp: 2822 case e1000_pch_ptp: 2823 hw->fc.high_water = 0x5C20; 2824 hw->fc.low_water = 0x5048; 2825 hw->fc.pause_time = 0x0650; 2826 hw->fc.refresh_time = 0x0400; 2827 /* Jumbos need adjusted PBA */ 2828 if (if_getmtu(ifp) > ETHERMTU) 2829 E1000_WRITE_REG(hw, E1000_PBA, 12); 2830 else 2831 E1000_WRITE_REG(hw, E1000_PBA, 26); 2832 break; 2833 case e1000_82575: 2834 case e1000_82576: 2835 /* 8-byte granularity */ 2836 hw->fc.low_water = hw->fc.high_water - 8; 2837 break; 2838 case e1000_82580: 2839 case e1000_i350: 2840 case e1000_i354: 2841 case e1000_i210: 2842 case e1000_i211: 2843 case e1000_vfadapt: 2844 case e1000_vfadapt_i350: 2845 /* 16-byte granularity */ 2846 hw->fc.low_water = hw->fc.high_water - 16; 2847 break; 2848 case e1000_ich9lan: 2849 case e1000_ich10lan: 2850 if (if_getmtu(ifp) > ETHERMTU) { 2851 hw->fc.high_water = 0x2800; 2852 hw->fc.low_water = hw->fc.high_water - 8; 2853 break; 2854 } 2855 /* FALLTHROUGH */ 2856 default: 2857 if (hw->mac.type == e1000_80003es2lan) 2858 hw->fc.pause_time = 0xFFFF; 2859 break; 2860 } 2861 2862 /* I219 needs some special flushing to avoid hangs */ 2863 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2864 em_flush_desc_rings(sc); 2865 2866 /* Issue a global reset */ 2867 e1000_reset_hw(hw); 2868 if (hw->mac.type >= igb_mac_min) { 2869 E1000_WRITE_REG(hw, E1000_WUC, 0); 2870 } else { 2871 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2872 em_disable_aspm(sc); 2873 } 2874 if (sc->flags & IGB_MEDIA_RESET) { 2875 e1000_setup_init_funcs(hw, true); 2876 e1000_get_bus_info(hw); 2877 sc->flags &= ~IGB_MEDIA_RESET; 2878 } 2879 /* and a re-init */ 2880 if (e1000_init_hw(hw) < 0) { 2881 device_printf(dev, "Hardware Initialization Failed\n"); 2882 return; 2883 } 2884 if (hw->mac.type >= igb_mac_min) 2885 igb_init_dmac(sc, pba); 2886 2887 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2888 e1000_get_phy_info(hw); 2889 e1000_check_for_link(hw); 2890 } 2891 2892 /* 2893 * Initialise the RSS mapping for NICs that support multiple transmit/ 2894 * receive rings. 2895 */ 2896 2897 #define RSSKEYLEN 10 2898 static void 2899 em_initialize_rss_mapping(struct e1000_softc *sc) 2900 { 2901 uint8_t rss_key[4 * RSSKEYLEN]; 2902 uint32_t reta = 0; 2903 struct e1000_hw *hw = &sc->hw; 2904 int i; 2905 2906 /* 2907 * Configure RSS key 2908 */ 2909 arc4rand(rss_key, sizeof(rss_key), 0); 2910 for (i = 0; i < RSSKEYLEN; ++i) { 2911 uint32_t rssrk = 0; 2912 2913 rssrk = EM_RSSRK_VAL(rss_key, i); 2914 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2915 } 2916 2917 /* 2918 * Configure RSS redirect table in following fashion: 2919 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2920 */ 2921 for (i = 0; i < sizeof(reta); ++i) { 2922 uint32_t q; 2923 2924 q = (i % sc->rx_num_queues) << 7; 2925 reta |= q << (8 * i); 2926 } 2927 2928 for (i = 0; i < 32; ++i) 2929 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2930 2931 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2932 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2933 E1000_MRQC_RSS_FIELD_IPV4 | 2934 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2935 E1000_MRQC_RSS_FIELD_IPV6_EX | 2936 E1000_MRQC_RSS_FIELD_IPV6); 2937 } 2938 2939 static void 2940 igb_initialize_rss_mapping(struct e1000_softc *sc) 2941 { 2942 struct e1000_hw *hw = &sc->hw; 2943 int i; 2944 int queue_id; 2945 u32 reta; 2946 u32 rss_key[10], mrqc, shift = 0; 2947 2948 /* XXX? */ 2949 if (hw->mac.type == e1000_82575) 2950 shift = 6; 2951 2952 /* 2953 * The redirection table controls which destination 2954 * queue each bucket redirects traffic to. 2955 * Each DWORD represents four queues, with the LSB 2956 * being the first queue in the DWORD. 2957 * 2958 * This just allocates buckets to queues using round-robin 2959 * allocation. 2960 * 2961 * NOTE: It Just Happens to line up with the default 2962 * RSS allocation method. 2963 */ 2964 2965 /* Warning FM follows */ 2966 reta = 0; 2967 for (i = 0; i < 128; i++) { 2968 #ifdef RSS 2969 queue_id = rss_get_indirection_to_bucket(i); 2970 /* 2971 * If we have more queues than buckets, we'll 2972 * end up mapping buckets to a subset of the 2973 * queues. 2974 * 2975 * If we have more buckets than queues, we'll 2976 * end up instead assigning multiple buckets 2977 * to queues. 2978 * 2979 * Both are suboptimal, but we need to handle 2980 * the case so we don't go out of bounds 2981 * indexing arrays and such. 2982 */ 2983 queue_id = queue_id % sc->rx_num_queues; 2984 #else 2985 queue_id = (i % sc->rx_num_queues); 2986 #endif 2987 /* Adjust if required */ 2988 queue_id = queue_id << shift; 2989 2990 /* 2991 * The low 8 bits are for hash value (n+0); 2992 * The next 8 bits are for hash value (n+1), etc. 2993 */ 2994 reta = reta >> 8; 2995 reta = reta | ( ((uint32_t) queue_id) << 24); 2996 if ((i & 3) == 3) { 2997 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2998 reta = 0; 2999 } 3000 } 3001 3002 /* Now fill in hash table */ 3003 3004 /* 3005 * MRQC: Multiple Receive Queues Command 3006 * Set queuing to RSS control, number depends on the device. 3007 */ 3008 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3009 3010 #ifdef RSS 3011 /* XXX ew typecasting */ 3012 rss_getkey((uint8_t *) &rss_key); 3013 #else 3014 arc4rand(&rss_key, sizeof(rss_key), 0); 3015 #endif 3016 for (i = 0; i < 10; i++) 3017 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3018 3019 /* 3020 * Configure the RSS fields to hash upon. 3021 */ 3022 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3023 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3024 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3025 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3026 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3027 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3028 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3029 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3030 3031 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3032 } 3033 3034 /********************************************************************* 3035 * 3036 * Setup networking device structure and register interface media. 3037 * 3038 **********************************************************************/ 3039 static int 3040 em_setup_interface(if_ctx_t ctx) 3041 { 3042 if_t ifp = iflib_get_ifp(ctx); 3043 struct e1000_softc *sc = iflib_get_softc(ctx); 3044 if_softc_ctx_t scctx = sc->shared; 3045 3046 INIT_DEBUGOUT("em_setup_interface: begin"); 3047 3048 /* Single Queue */ 3049 if (sc->tx_num_queues == 1) { 3050 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3051 if_setsendqready(ifp); 3052 } 3053 3054 /* 3055 * Specify the media types supported by this adapter and register 3056 * callbacks to update media and link information 3057 */ 3058 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3059 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3060 u_char fiber_type = IFM_1000_SX; /* default type */ 3061 3062 if (sc->hw.mac.type == e1000_82545) 3063 fiber_type = IFM_1000_LX; 3064 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3065 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3066 } else { 3067 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3068 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3069 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3070 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3071 if (sc->hw.phy.type != e1000_phy_ife) { 3072 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3073 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3074 } 3075 } 3076 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3077 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3078 return (0); 3079 } 3080 3081 static int 3082 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3083 { 3084 struct e1000_softc *sc = iflib_get_softc(ctx); 3085 if_softc_ctx_t scctx = sc->shared; 3086 int error = E1000_SUCCESS; 3087 struct em_tx_queue *que; 3088 int i, j; 3089 3090 MPASS(sc->tx_num_queues > 0); 3091 MPASS(sc->tx_num_queues == ntxqsets); 3092 3093 /* First allocate the top level queue structs */ 3094 if (!(sc->tx_queues = 3095 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3096 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3097 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3098 return(ENOMEM); 3099 } 3100 3101 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3102 /* Set up some basics */ 3103 3104 struct tx_ring *txr = &que->txr; 3105 txr->sc = que->sc = sc; 3106 que->me = txr->me = i; 3107 3108 /* Allocate report status array */ 3109 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3110 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3111 error = ENOMEM; 3112 goto fail; 3113 } 3114 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3115 txr->tx_rsq[j] = QIDX_INVALID; 3116 /* get the virtual and physical address of the hardware queues */ 3117 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3118 txr->tx_paddr = paddrs[i*ntxqs]; 3119 } 3120 3121 if (bootverbose) 3122 device_printf(iflib_get_dev(ctx), 3123 "allocated for %d tx_queues\n", sc->tx_num_queues); 3124 return (0); 3125 fail: 3126 em_if_queues_free(ctx); 3127 return (error); 3128 } 3129 3130 static int 3131 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3132 { 3133 struct e1000_softc *sc = iflib_get_softc(ctx); 3134 int error = E1000_SUCCESS; 3135 struct em_rx_queue *que; 3136 int i; 3137 3138 MPASS(sc->rx_num_queues > 0); 3139 MPASS(sc->rx_num_queues == nrxqsets); 3140 3141 /* First allocate the top level queue structs */ 3142 if (!(sc->rx_queues = 3143 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3144 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3145 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3146 error = ENOMEM; 3147 goto fail; 3148 } 3149 3150 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3151 /* Set up some basics */ 3152 struct rx_ring *rxr = &que->rxr; 3153 rxr->sc = que->sc = sc; 3154 rxr->que = que; 3155 que->me = rxr->me = i; 3156 3157 /* get the virtual and physical address of the hardware queues */ 3158 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3159 rxr->rx_paddr = paddrs[i*nrxqs]; 3160 } 3161 3162 if (bootverbose) 3163 device_printf(iflib_get_dev(ctx), 3164 "allocated for %d rx_queues\n", sc->rx_num_queues); 3165 3166 return (0); 3167 fail: 3168 em_if_queues_free(ctx); 3169 return (error); 3170 } 3171 3172 static void 3173 em_if_queues_free(if_ctx_t ctx) 3174 { 3175 struct e1000_softc *sc = iflib_get_softc(ctx); 3176 struct em_tx_queue *tx_que = sc->tx_queues; 3177 struct em_rx_queue *rx_que = sc->rx_queues; 3178 3179 if (tx_que != NULL) { 3180 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3181 struct tx_ring *txr = &tx_que->txr; 3182 if (txr->tx_rsq == NULL) 3183 break; 3184 3185 free(txr->tx_rsq, M_DEVBUF); 3186 txr->tx_rsq = NULL; 3187 } 3188 free(sc->tx_queues, M_DEVBUF); 3189 sc->tx_queues = NULL; 3190 } 3191 3192 if (rx_que != NULL) { 3193 free(sc->rx_queues, M_DEVBUF); 3194 sc->rx_queues = NULL; 3195 } 3196 } 3197 3198 /********************************************************************* 3199 * 3200 * Enable transmit unit. 3201 * 3202 **********************************************************************/ 3203 static void 3204 em_initialize_transmit_unit(if_ctx_t ctx) 3205 { 3206 struct e1000_softc *sc = iflib_get_softc(ctx); 3207 if_softc_ctx_t scctx = sc->shared; 3208 struct em_tx_queue *que; 3209 struct tx_ring *txr; 3210 struct e1000_hw *hw = &sc->hw; 3211 u32 tctl, txdctl = 0, tarc, tipg = 0; 3212 3213 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3214 3215 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3216 u64 bus_addr; 3217 caddr_t offp, endp; 3218 3219 que = &sc->tx_queues[i]; 3220 txr = &que->txr; 3221 bus_addr = txr->tx_paddr; 3222 3223 /* Clear checksum offload context. */ 3224 offp = (caddr_t)&txr->csum_flags; 3225 endp = (caddr_t)(txr + 1); 3226 bzero(offp, endp - offp); 3227 3228 /* Base and Len of TX Ring */ 3229 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3230 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3231 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3232 (u32)(bus_addr >> 32)); 3233 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3234 (u32)bus_addr); 3235 /* Init the HEAD/TAIL indices */ 3236 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3237 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3238 3239 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3240 E1000_READ_REG(hw, E1000_TDBAL(i)), 3241 E1000_READ_REG(hw, E1000_TDLEN(i))); 3242 3243 txdctl = 0; /* clear txdctl */ 3244 txdctl |= 0x1f; /* PTHRESH */ 3245 txdctl |= 1 << 8; /* HTHRESH */ 3246 txdctl |= 1 << 16;/* WTHRESH */ 3247 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3248 txdctl |= E1000_TXDCTL_GRAN; 3249 txdctl |= 1 << 25; /* LWTHRESH */ 3250 3251 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3252 } 3253 3254 /* Set the default values for the Tx Inter Packet Gap timer */ 3255 switch (hw->mac.type) { 3256 case e1000_80003es2lan: 3257 tipg = DEFAULT_82543_TIPG_IPGR1; 3258 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3259 E1000_TIPG_IPGR2_SHIFT; 3260 break; 3261 case e1000_82542: 3262 tipg = DEFAULT_82542_TIPG_IPGT; 3263 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3264 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3265 break; 3266 default: 3267 if (hw->phy.media_type == e1000_media_type_fiber || 3268 hw->phy.media_type == e1000_media_type_internal_serdes) 3269 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3270 else 3271 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3272 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3273 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3274 } 3275 3276 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3277 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3278 3279 if(hw->mac.type >= e1000_82540) 3280 E1000_WRITE_REG(hw, E1000_TADV, 3281 sc->tx_abs_int_delay.value); 3282 3283 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3284 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3285 tarc |= TARC_SPEED_MODE_BIT; 3286 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3287 } else if (hw->mac.type == e1000_80003es2lan) { 3288 /* errata: program both queues to unweighted RR */ 3289 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3290 tarc |= 1; 3291 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3292 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3293 tarc |= 1; 3294 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3295 } else if (hw->mac.type == e1000_82574) { 3296 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3297 tarc |= TARC_ERRATA_BIT; 3298 if ( sc->tx_num_queues > 1) { 3299 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3300 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3301 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3302 } else 3303 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3304 } 3305 3306 if (sc->tx_int_delay.value > 0) 3307 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3308 3309 /* Program the Transmit Control Register */ 3310 tctl = E1000_READ_REG(hw, E1000_TCTL); 3311 tctl &= ~E1000_TCTL_CT; 3312 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3313 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3314 3315 if (hw->mac.type >= e1000_82571) 3316 tctl |= E1000_TCTL_MULR; 3317 3318 /* This write will effectively turn on the transmit unit. */ 3319 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3320 3321 /* SPT and KBL errata workarounds */ 3322 if (hw->mac.type == e1000_pch_spt) { 3323 u32 reg; 3324 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3325 reg |= E1000_RCTL_RDMTS_HEX; 3326 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3327 /* i218-i219 Specification Update 1.5.4.5 */ 3328 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3329 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3330 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3331 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3332 } 3333 } 3334 3335 /********************************************************************* 3336 * 3337 * Enable receive unit. 3338 * 3339 **********************************************************************/ 3340 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3341 3342 static void 3343 em_initialize_receive_unit(if_ctx_t ctx) 3344 { 3345 struct e1000_softc *sc = iflib_get_softc(ctx); 3346 if_softc_ctx_t scctx = sc->shared; 3347 if_t ifp = iflib_get_ifp(ctx); 3348 struct e1000_hw *hw = &sc->hw; 3349 struct em_rx_queue *que; 3350 int i; 3351 uint32_t rctl, rxcsum; 3352 3353 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3354 3355 /* 3356 * Make sure receives are disabled while setting 3357 * up the descriptor ring 3358 */ 3359 rctl = E1000_READ_REG(hw, E1000_RCTL); 3360 /* Do not disable if ever enabled on this hardware */ 3361 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3362 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3363 3364 /* Setup the Receive Control Register */ 3365 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3366 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3367 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3368 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3369 3370 /* Do not store bad packets */ 3371 rctl &= ~E1000_RCTL_SBP; 3372 3373 /* Enable Long Packet receive */ 3374 if (if_getmtu(ifp) > ETHERMTU) 3375 rctl |= E1000_RCTL_LPE; 3376 else 3377 rctl &= ~E1000_RCTL_LPE; 3378 3379 /* Strip the CRC */ 3380 if (!em_disable_crc_stripping) 3381 rctl |= E1000_RCTL_SECRC; 3382 3383 if (hw->mac.type >= e1000_82540) { 3384 E1000_WRITE_REG(hw, E1000_RADV, 3385 sc->rx_abs_int_delay.value); 3386 3387 /* 3388 * Set the interrupt throttling rate. Value is calculated 3389 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3390 */ 3391 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3392 } 3393 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3394 3395 if (hw->mac.type >= em_mac_min) { 3396 uint32_t rfctl; 3397 /* Use extended rx descriptor formats */ 3398 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3399 rfctl |= E1000_RFCTL_EXTEN; 3400 3401 /* 3402 * When using MSI-X interrupts we need to throttle 3403 * using the EITR register (82574 only) 3404 */ 3405 if (hw->mac.type == e1000_82574) { 3406 for (int i = 0; i < 4; i++) 3407 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3408 DEFAULT_ITR); 3409 /* Disable accelerated acknowledge */ 3410 rfctl |= E1000_RFCTL_ACK_DIS; 3411 } 3412 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3413 } 3414 3415 /* Set up L3 and L4 csum Rx descriptor offloads */ 3416 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3417 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3418 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3419 if (hw->mac.type > e1000_82575) 3420 rxcsum |= E1000_RXCSUM_CRCOFL; 3421 else if (hw->mac.type < em_mac_min && 3422 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3423 rxcsum |= E1000_RXCSUM_IPV6OFL; 3424 } else { 3425 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3426 if (hw->mac.type > e1000_82575) 3427 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3428 else if (hw->mac.type < em_mac_min) 3429 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3430 } 3431 3432 if (sc->rx_num_queues > 1) { 3433 /* RSS hash needed in the Rx descriptor */ 3434 rxcsum |= E1000_RXCSUM_PCSD; 3435 3436 if (hw->mac.type >= igb_mac_min) 3437 igb_initialize_rss_mapping(sc); 3438 else 3439 em_initialize_rss_mapping(sc); 3440 } 3441 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3442 3443 /* 3444 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3445 * long latencies are observed, like Lenovo X60. This 3446 * change eliminates the problem, but since having positive 3447 * values in RDTR is a known source of problems on other 3448 * platforms another solution is being sought. 3449 */ 3450 if (hw->mac.type == e1000_82573) 3451 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3452 3453 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3454 struct rx_ring *rxr = &que->rxr; 3455 /* Setup the Base and Length of the Rx Descriptor Ring */ 3456 u64 bus_addr = rxr->rx_paddr; 3457 #if 0 3458 u32 rdt = sc->rx_num_queues -1; /* default */ 3459 #endif 3460 3461 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3462 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3463 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3464 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3465 /* Setup the Head and Tail Descriptor Pointers */ 3466 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3467 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3468 } 3469 3470 /* 3471 * Set PTHRESH for improved jumbo performance 3472 * According to 10.2.5.11 of Intel 82574 Datasheet, 3473 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3474 * Only write to RXDCTL(1) if there is a need for different 3475 * settings. 3476 */ 3477 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3478 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3479 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3480 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3481 } else if (hw->mac.type == e1000_82574) { 3482 for (int i = 0; i < sc->rx_num_queues; i++) { 3483 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3484 rxdctl |= 0x20; /* PTHRESH */ 3485 rxdctl |= 4 << 8; /* HTHRESH */ 3486 rxdctl |= 4 << 16;/* WTHRESH */ 3487 rxdctl |= 1 << 24; /* Switch to granularity */ 3488 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3489 } 3490 } else if (hw->mac.type >= igb_mac_min) { 3491 u32 psize, srrctl = 0; 3492 3493 if (if_getmtu(ifp) > ETHERMTU) { 3494 psize = scctx->isc_max_frame_size; 3495 /* are we on a vlan? */ 3496 if (if_vlantrunkinuse(ifp)) 3497 psize += VLAN_TAG_SIZE; 3498 3499 if (sc->vf_ifp) 3500 e1000_rlpml_set_vf(hw, psize); 3501 else 3502 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3503 } 3504 3505 /* Set maximum packet buffer len */ 3506 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3507 E1000_SRRCTL_BSIZEPKT_SHIFT; 3508 3509 /* 3510 * If TX flow control is disabled and there's >1 queue defined, 3511 * enable DROP. 3512 * 3513 * This drops frames rather than hanging the RX MAC for all queues. 3514 */ 3515 if ((sc->rx_num_queues > 1) && 3516 (sc->fc == e1000_fc_none || 3517 sc->fc == e1000_fc_rx_pause)) { 3518 srrctl |= E1000_SRRCTL_DROP_EN; 3519 } 3520 /* Setup the Base and Length of the Rx Descriptor Rings */ 3521 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3522 struct rx_ring *rxr = &que->rxr; 3523 u64 bus_addr = rxr->rx_paddr; 3524 u32 rxdctl; 3525 3526 #ifdef notyet 3527 /* Configure for header split? -- ignore for now */ 3528 rxr->hdr_split = igb_header_split; 3529 #else 3530 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3531 #endif 3532 3533 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3534 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3535 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3536 (uint32_t)(bus_addr >> 32)); 3537 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3538 (uint32_t)bus_addr); 3539 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3540 /* Enable this Queue */ 3541 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3542 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3543 rxdctl &= 0xFFF00000; 3544 rxdctl |= IGB_RX_PTHRESH; 3545 rxdctl |= IGB_RX_HTHRESH << 8; 3546 rxdctl |= IGB_RX_WTHRESH << 16; 3547 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3548 } 3549 } else if (hw->mac.type >= e1000_pch2lan) { 3550 if (if_getmtu(ifp) > ETHERMTU) 3551 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3552 else 3553 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3554 } 3555 3556 /* Make sure VLAN Filters are off */ 3557 rctl &= ~E1000_RCTL_VFE; 3558 3559 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3560 if (hw->mac.type < igb_mac_min) { 3561 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3562 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3563 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3564 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3565 else if (sc->rx_mbuf_sz > 8192) 3566 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3567 else { 3568 rctl |= E1000_RCTL_SZ_2048; 3569 rctl &= ~E1000_RCTL_BSEX; 3570 } 3571 } else 3572 rctl |= E1000_RCTL_SZ_2048; 3573 3574 /* 3575 * rctl bits 11:10 are as follows 3576 * lem: reserved 3577 * em: DTYPE 3578 * igb: reserved 3579 * and should be 00 on all of the above 3580 */ 3581 rctl &= ~0x00000C00; 3582 3583 /* Write out the settings */ 3584 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3585 3586 return; 3587 } 3588 3589 static void 3590 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3591 { 3592 struct e1000_softc *sc = iflib_get_softc(ctx); 3593 u32 index, bit; 3594 3595 index = (vtag >> 5) & 0x7F; 3596 bit = vtag & 0x1F; 3597 sc->shadow_vfta[index] |= (1 << bit); 3598 ++sc->num_vlans; 3599 em_if_vlan_filter_write(sc); 3600 } 3601 3602 static void 3603 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3604 { 3605 struct e1000_softc *sc = iflib_get_softc(ctx); 3606 u32 index, bit; 3607 3608 index = (vtag >> 5) & 0x7F; 3609 bit = vtag & 0x1F; 3610 sc->shadow_vfta[index] &= ~(1 << bit); 3611 --sc->num_vlans; 3612 em_if_vlan_filter_write(sc); 3613 } 3614 3615 static bool 3616 em_if_vlan_filter_capable(if_ctx_t ctx) 3617 { 3618 if_t ifp = iflib_get_ifp(ctx); 3619 3620 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3621 !em_disable_crc_stripping) 3622 return (true); 3623 3624 return (false); 3625 } 3626 3627 static bool 3628 em_if_vlan_filter_used(if_ctx_t ctx) 3629 { 3630 struct e1000_softc *sc = iflib_get_softc(ctx); 3631 3632 if (!em_if_vlan_filter_capable(ctx)) 3633 return (false); 3634 3635 for (int i = 0; i < EM_VFTA_SIZE; i++) 3636 if (sc->shadow_vfta[i] != 0) 3637 return (true); 3638 3639 return (false); 3640 } 3641 3642 static void 3643 em_if_vlan_filter_enable(struct e1000_softc *sc) 3644 { 3645 struct e1000_hw *hw = &sc->hw; 3646 u32 reg; 3647 3648 reg = E1000_READ_REG(hw, E1000_RCTL); 3649 reg &= ~E1000_RCTL_CFIEN; 3650 reg |= E1000_RCTL_VFE; 3651 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3652 } 3653 3654 static void 3655 em_if_vlan_filter_disable(struct e1000_softc *sc) 3656 { 3657 struct e1000_hw *hw = &sc->hw; 3658 u32 reg; 3659 3660 reg = E1000_READ_REG(hw, E1000_RCTL); 3661 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3662 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3663 } 3664 3665 static void 3666 em_if_vlan_filter_write(struct e1000_softc *sc) 3667 { 3668 struct e1000_hw *hw = &sc->hw; 3669 3670 if (sc->vf_ifp) 3671 return; 3672 3673 /* Disable interrupts for lem-class devices during the filter change */ 3674 if (hw->mac.type < em_mac_min) 3675 em_if_intr_disable(sc->ctx); 3676 3677 for (int i = 0; i < EM_VFTA_SIZE; i++) 3678 if (sc->shadow_vfta[i] != 0) { 3679 /* XXXKB: incomplete VF support, we return early above */ 3680 if (sc->vf_ifp) 3681 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3682 else 3683 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3684 } 3685 3686 /* Re-enable interrupts for lem-class devices */ 3687 if (hw->mac.type < em_mac_min) 3688 em_if_intr_enable(sc->ctx); 3689 } 3690 3691 static void 3692 em_setup_vlan_hw_support(if_ctx_t ctx) 3693 { 3694 struct e1000_softc *sc = iflib_get_softc(ctx); 3695 struct e1000_hw *hw = &sc->hw; 3696 if_t ifp = iflib_get_ifp(ctx); 3697 u32 reg; 3698 3699 /* XXXKB: Return early if we are a VF until VF decap and filter management 3700 * is ready and tested. 3701 */ 3702 if (sc->vf_ifp) 3703 return; 3704 3705 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3706 !em_disable_crc_stripping) { 3707 reg = E1000_READ_REG(hw, E1000_CTRL); 3708 reg |= E1000_CTRL_VME; 3709 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3710 } else { 3711 reg = E1000_READ_REG(hw, E1000_CTRL); 3712 reg &= ~E1000_CTRL_VME; 3713 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3714 } 3715 3716 /* If we aren't doing HW filtering, we're done */ 3717 if (!em_if_vlan_filter_capable(ctx)) { 3718 em_if_vlan_filter_disable(sc); 3719 return; 3720 } 3721 3722 /* 3723 * A soft reset zero's out the VFTA, so 3724 * we need to repopulate it now. 3725 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3726 * traffic through. This will write the entire table. 3727 */ 3728 em_if_vlan_register(ctx, 0); 3729 3730 /* Enable the Filter Table */ 3731 em_if_vlan_filter_enable(sc); 3732 } 3733 3734 static void 3735 em_if_intr_enable(if_ctx_t ctx) 3736 { 3737 struct e1000_softc *sc = iflib_get_softc(ctx); 3738 struct e1000_hw *hw = &sc->hw; 3739 u32 ims_mask = IMS_ENABLE_MASK; 3740 3741 if (sc->intr_type == IFLIB_INTR_MSIX) { 3742 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3743 ims_mask |= sc->ims; 3744 } 3745 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3746 E1000_WRITE_FLUSH(hw); 3747 } 3748 3749 static void 3750 em_if_intr_disable(if_ctx_t ctx) 3751 { 3752 struct e1000_softc *sc = iflib_get_softc(ctx); 3753 struct e1000_hw *hw = &sc->hw; 3754 3755 if (sc->intr_type == IFLIB_INTR_MSIX) 3756 E1000_WRITE_REG(hw, EM_EIAC, 0); 3757 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3758 E1000_WRITE_FLUSH(hw); 3759 } 3760 3761 static void 3762 igb_if_intr_enable(if_ctx_t ctx) 3763 { 3764 struct e1000_softc *sc = iflib_get_softc(ctx); 3765 struct e1000_hw *hw = &sc->hw; 3766 u32 mask; 3767 3768 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3769 mask = (sc->que_mask | sc->link_mask); 3770 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3771 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3772 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3773 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3774 } else 3775 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3776 E1000_WRITE_FLUSH(hw); 3777 } 3778 3779 static void 3780 igb_if_intr_disable(if_ctx_t ctx) 3781 { 3782 struct e1000_softc *sc = iflib_get_softc(ctx); 3783 struct e1000_hw *hw = &sc->hw; 3784 3785 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3786 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3787 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3788 } 3789 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3790 E1000_WRITE_FLUSH(hw); 3791 } 3792 3793 /* 3794 * Bit of a misnomer, what this really means is 3795 * to enable OS management of the system... aka 3796 * to disable special hardware management features 3797 */ 3798 static void 3799 em_init_manageability(struct e1000_softc *sc) 3800 { 3801 /* A shared code workaround */ 3802 #define E1000_82542_MANC2H E1000_MANC2H 3803 if (sc->has_manage) { 3804 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3805 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3806 3807 /* disable hardware interception of ARP */ 3808 manc &= ~(E1000_MANC_ARP_EN); 3809 3810 /* enable receiving management packets to the host */ 3811 manc |= E1000_MANC_EN_MNG2HOST; 3812 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3813 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3814 manc2h |= E1000_MNG2HOST_PORT_623; 3815 manc2h |= E1000_MNG2HOST_PORT_664; 3816 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3817 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3818 } 3819 } 3820 3821 /* 3822 * Give control back to hardware management 3823 * controller if there is one. 3824 */ 3825 static void 3826 em_release_manageability(struct e1000_softc *sc) 3827 { 3828 if (sc->has_manage) { 3829 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3830 3831 /* re-enable hardware interception of ARP */ 3832 manc |= E1000_MANC_ARP_EN; 3833 manc &= ~E1000_MANC_EN_MNG2HOST; 3834 3835 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3836 } 3837 } 3838 3839 /* 3840 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3841 * For ASF and Pass Through versions of f/w this means 3842 * that the driver is loaded. For AMT version type f/w 3843 * this means that the network i/f is open. 3844 */ 3845 static void 3846 em_get_hw_control(struct e1000_softc *sc) 3847 { 3848 u32 ctrl_ext, swsm; 3849 3850 if (sc->vf_ifp) 3851 return; 3852 3853 if (sc->hw.mac.type == e1000_82573) { 3854 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3855 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3856 swsm | E1000_SWSM_DRV_LOAD); 3857 return; 3858 } 3859 /* else */ 3860 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3861 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3862 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3863 } 3864 3865 /* 3866 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3867 * For ASF and Pass Through versions of f/w this means that 3868 * the driver is no longer loaded. For AMT versions of the 3869 * f/w this means that the network i/f is closed. 3870 */ 3871 static void 3872 em_release_hw_control(struct e1000_softc *sc) 3873 { 3874 u32 ctrl_ext, swsm; 3875 3876 if (!sc->has_manage) 3877 return; 3878 3879 if (sc->hw.mac.type == e1000_82573) { 3880 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3881 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3882 swsm & ~E1000_SWSM_DRV_LOAD); 3883 return; 3884 } 3885 /* else */ 3886 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3887 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3888 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3889 return; 3890 } 3891 3892 static int 3893 em_is_valid_ether_addr(u8 *addr) 3894 { 3895 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3896 3897 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3898 return (false); 3899 } 3900 3901 return (true); 3902 } 3903 3904 static bool 3905 em_automask_tso(if_ctx_t ctx) 3906 { 3907 struct e1000_softc *sc = iflib_get_softc(ctx); 3908 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 3909 if_t ifp = iflib_get_ifp(ctx); 3910 3911 if (!em_unsupported_tso && sc->link_speed && 3912 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 3913 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 3914 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 3915 scctx->isc_capenable &= ~IFCAP_TSO; 3916 if_setcapenablebit(ifp, 0, IFCAP_TSO); 3917 /* iflib_init_locked handles ifnet hwassistbits */ 3918 iflib_request_reset(ctx); 3919 return true; 3920 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 3921 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 3922 scctx->isc_capenable |= sc->tso_automasked; 3923 if_setcapenablebit(ifp, sc->tso_automasked, 0); 3924 sc->tso_automasked = 0; 3925 /* iflib_init_locked handles ifnet hwassistbits */ 3926 iflib_request_reset(ctx); 3927 return true; 3928 } 3929 3930 return false; 3931 } 3932 3933 /* 3934 ** Parse the interface capabilities with regard 3935 ** to both system management and wake-on-lan for 3936 ** later use. 3937 */ 3938 static void 3939 em_get_wakeup(if_ctx_t ctx) 3940 { 3941 struct e1000_softc *sc = iflib_get_softc(ctx); 3942 device_t dev = iflib_get_dev(ctx); 3943 u16 eeprom_data = 0, device_id, apme_mask; 3944 3945 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3946 apme_mask = EM_EEPROM_APME; 3947 3948 switch (sc->hw.mac.type) { 3949 case e1000_82542: 3950 case e1000_82543: 3951 break; 3952 case e1000_82544: 3953 e1000_read_nvm(&sc->hw, 3954 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3955 apme_mask = EM_82544_APME; 3956 break; 3957 case e1000_82546: 3958 case e1000_82546_rev_3: 3959 if (sc->hw.bus.func == 1) { 3960 e1000_read_nvm(&sc->hw, 3961 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3962 break; 3963 } else 3964 e1000_read_nvm(&sc->hw, 3965 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3966 break; 3967 case e1000_82573: 3968 case e1000_82583: 3969 sc->has_amt = true; 3970 /* FALLTHROUGH */ 3971 case e1000_82571: 3972 case e1000_82572: 3973 case e1000_80003es2lan: 3974 if (sc->hw.bus.func == 1) { 3975 e1000_read_nvm(&sc->hw, 3976 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3977 break; 3978 } else 3979 e1000_read_nvm(&sc->hw, 3980 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3981 break; 3982 case e1000_ich8lan: 3983 case e1000_ich9lan: 3984 case e1000_ich10lan: 3985 case e1000_pchlan: 3986 case e1000_pch2lan: 3987 case e1000_pch_lpt: 3988 case e1000_pch_spt: 3989 case e1000_82575: /* listing all igb devices */ 3990 case e1000_82576: 3991 case e1000_82580: 3992 case e1000_i350: 3993 case e1000_i354: 3994 case e1000_i210: 3995 case e1000_i211: 3996 case e1000_vfadapt: 3997 case e1000_vfadapt_i350: 3998 apme_mask = E1000_WUC_APME; 3999 sc->has_amt = true; 4000 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4001 break; 4002 default: 4003 e1000_read_nvm(&sc->hw, 4004 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4005 break; 4006 } 4007 if (eeprom_data & apme_mask) 4008 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4009 /* 4010 * We have the eeprom settings, now apply the special cases 4011 * where the eeprom may be wrong or the board won't support 4012 * wake on lan on a particular port 4013 */ 4014 device_id = pci_get_device(dev); 4015 switch (device_id) { 4016 case E1000_DEV_ID_82546GB_PCIE: 4017 sc->wol = 0; 4018 break; 4019 case E1000_DEV_ID_82546EB_FIBER: 4020 case E1000_DEV_ID_82546GB_FIBER: 4021 /* Wake events only supported on port A for dual fiber 4022 * regardless of eeprom setting */ 4023 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4024 E1000_STATUS_FUNC_1) 4025 sc->wol = 0; 4026 break; 4027 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4028 /* if quad port adapter, disable WoL on all but port A */ 4029 if (global_quad_port_a != 0) 4030 sc->wol = 0; 4031 /* Reset for multiple quad port adapters */ 4032 if (++global_quad_port_a == 4) 4033 global_quad_port_a = 0; 4034 break; 4035 case E1000_DEV_ID_82571EB_FIBER: 4036 /* Wake events only supported on port A for dual fiber 4037 * regardless of eeprom setting */ 4038 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4039 E1000_STATUS_FUNC_1) 4040 sc->wol = 0; 4041 break; 4042 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4043 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4044 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4045 /* if quad port adapter, disable WoL on all but port A */ 4046 if (global_quad_port_a != 0) 4047 sc->wol = 0; 4048 /* Reset for multiple quad port adapters */ 4049 if (++global_quad_port_a == 4) 4050 global_quad_port_a = 0; 4051 break; 4052 } 4053 return; 4054 } 4055 4056 4057 /* 4058 * Enable PCI Wake On Lan capability 4059 */ 4060 static void 4061 em_enable_wakeup(if_ctx_t ctx) 4062 { 4063 struct e1000_softc *sc = iflib_get_softc(ctx); 4064 device_t dev = iflib_get_dev(ctx); 4065 if_t ifp = iflib_get_ifp(ctx); 4066 int error = 0; 4067 u32 pmc, ctrl, ctrl_ext, rctl; 4068 u16 status; 4069 4070 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4071 return; 4072 4073 /* 4074 * Determine type of Wakeup: note that wol 4075 * is set with all bits on by default. 4076 */ 4077 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4078 sc->wol &= ~E1000_WUFC_MAG; 4079 4080 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4081 sc->wol &= ~E1000_WUFC_EX; 4082 4083 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4084 sc->wol &= ~E1000_WUFC_MC; 4085 else { 4086 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4087 rctl |= E1000_RCTL_MPE; 4088 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4089 } 4090 4091 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4092 goto pme; 4093 4094 /* Advertise the wakeup capability */ 4095 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4096 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4097 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4098 4099 /* Keep the laser running on Fiber adapters */ 4100 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4101 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4102 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4103 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4104 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4105 } 4106 4107 if ((sc->hw.mac.type == e1000_ich8lan) || 4108 (sc->hw.mac.type == e1000_pchlan) || 4109 (sc->hw.mac.type == e1000_ich9lan) || 4110 (sc->hw.mac.type == e1000_ich10lan)) 4111 e1000_suspend_workarounds_ich8lan(&sc->hw); 4112 4113 if ( sc->hw.mac.type >= e1000_pchlan) { 4114 error = em_enable_phy_wakeup(sc); 4115 if (error) 4116 goto pme; 4117 } else { 4118 /* Enable wakeup by the MAC */ 4119 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4120 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4121 } 4122 4123 if (sc->hw.phy.type == e1000_phy_igp_3) 4124 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4125 4126 pme: 4127 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4128 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4129 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4130 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4131 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4132 4133 return; 4134 } 4135 4136 /* 4137 * WOL in the newer chipset interfaces (pchlan) 4138 * require thing to be copied into the phy 4139 */ 4140 static int 4141 em_enable_phy_wakeup(struct e1000_softc *sc) 4142 { 4143 struct e1000_hw *hw = &sc->hw; 4144 u32 mreg, ret = 0; 4145 u16 preg; 4146 4147 /* copy MAC RARs to PHY RARs */ 4148 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4149 4150 /* copy MAC MTA to PHY MTA */ 4151 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4152 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4153 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4154 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4155 (u16)((mreg >> 16) & 0xFFFF)); 4156 } 4157 4158 /* configure PHY Rx Control register */ 4159 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4160 mreg = E1000_READ_REG(hw, E1000_RCTL); 4161 if (mreg & E1000_RCTL_UPE) 4162 preg |= BM_RCTL_UPE; 4163 if (mreg & E1000_RCTL_MPE) 4164 preg |= BM_RCTL_MPE; 4165 preg &= ~(BM_RCTL_MO_MASK); 4166 if (mreg & E1000_RCTL_MO_3) 4167 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4168 << BM_RCTL_MO_SHIFT); 4169 if (mreg & E1000_RCTL_BAM) 4170 preg |= BM_RCTL_BAM; 4171 if (mreg & E1000_RCTL_PMCF) 4172 preg |= BM_RCTL_PMCF; 4173 mreg = E1000_READ_REG(hw, E1000_CTRL); 4174 if (mreg & E1000_CTRL_RFCE) 4175 preg |= BM_RCTL_RFCE; 4176 e1000_write_phy_reg(hw, BM_RCTL, preg); 4177 4178 /* enable PHY wakeup in MAC register */ 4179 E1000_WRITE_REG(hw, E1000_WUC, 4180 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4181 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4182 4183 /* configure and enable PHY wakeup in PHY registers */ 4184 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4185 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4186 4187 /* activate PHY wakeup */ 4188 ret = hw->phy.ops.acquire(hw); 4189 if (ret) { 4190 printf("Could not acquire PHY\n"); 4191 return ret; 4192 } 4193 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4194 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4195 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4196 if (ret) { 4197 printf("Could not read PHY page 769\n"); 4198 goto out; 4199 } 4200 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4201 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4202 if (ret) 4203 printf("Could not set PHY Host Wakeup bit\n"); 4204 out: 4205 hw->phy.ops.release(hw); 4206 4207 return ret; 4208 } 4209 4210 static void 4211 em_if_led_func(if_ctx_t ctx, int onoff) 4212 { 4213 struct e1000_softc *sc = iflib_get_softc(ctx); 4214 4215 if (onoff) { 4216 e1000_setup_led(&sc->hw); 4217 e1000_led_on(&sc->hw); 4218 } else { 4219 e1000_led_off(&sc->hw); 4220 e1000_cleanup_led(&sc->hw); 4221 } 4222 } 4223 4224 /* 4225 * Disable the L0S and L1 LINK states 4226 */ 4227 static void 4228 em_disable_aspm(struct e1000_softc *sc) 4229 { 4230 int base, reg; 4231 u16 link_cap,link_ctrl; 4232 device_t dev = sc->dev; 4233 4234 switch (sc->hw.mac.type) { 4235 case e1000_82573: 4236 case e1000_82574: 4237 case e1000_82583: 4238 break; 4239 default: 4240 return; 4241 } 4242 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4243 return; 4244 reg = base + PCIER_LINK_CAP; 4245 link_cap = pci_read_config(dev, reg, 2); 4246 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4247 return; 4248 reg = base + PCIER_LINK_CTL; 4249 link_ctrl = pci_read_config(dev, reg, 2); 4250 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4251 pci_write_config(dev, reg, link_ctrl, 2); 4252 return; 4253 } 4254 4255 /********************************************************************** 4256 * 4257 * Update the board statistics counters. 4258 * 4259 **********************************************************************/ 4260 static void 4261 em_update_stats_counters(struct e1000_softc *sc) 4262 { 4263 u64 prev_xoffrxc = sc->stats.xoffrxc; 4264 4265 if(sc->hw.phy.media_type == e1000_media_type_copper || 4266 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4267 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4268 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4269 } 4270 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4271 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4272 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4273 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4274 4275 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4276 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4277 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4278 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4279 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4280 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4281 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4282 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4283 /* 4284 ** For watchdog management we need to know if we have been 4285 ** paused during the last interval, so capture that here. 4286 */ 4287 if (sc->stats.xoffrxc != prev_xoffrxc) 4288 sc->shared->isc_pause_frames = 1; 4289 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4290 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4291 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4292 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4293 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4294 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4295 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4296 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4297 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4298 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4299 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4300 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4301 4302 /* For the 64-bit byte counters the low dword must be read first. */ 4303 /* Both registers clear on the read of the high dword */ 4304 4305 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4306 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4307 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4308 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4309 4310 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4311 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4312 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4313 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4314 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4315 4316 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4317 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4318 4319 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4320 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4321 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4322 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4323 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4324 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4325 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4326 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4327 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4328 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4329 4330 /* Interrupt Counts */ 4331 4332 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4333 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4334 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4335 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4336 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4337 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4338 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4339 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4340 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4341 4342 if (sc->hw.mac.type >= e1000_82543) { 4343 sc->stats.algnerrc += 4344 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4345 sc->stats.rxerrc += 4346 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4347 sc->stats.tncrs += 4348 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4349 sc->stats.cexterr += 4350 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4351 sc->stats.tsctc += 4352 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4353 sc->stats.tsctfc += 4354 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4355 } 4356 } 4357 4358 static uint64_t 4359 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4360 { 4361 struct e1000_softc *sc = iflib_get_softc(ctx); 4362 if_t ifp = iflib_get_ifp(ctx); 4363 4364 switch (cnt) { 4365 case IFCOUNTER_COLLISIONS: 4366 return (sc->stats.colc); 4367 case IFCOUNTER_IERRORS: 4368 return (sc->dropped_pkts + sc->stats.rxerrc + 4369 sc->stats.crcerrs + sc->stats.algnerrc + 4370 sc->stats.ruc + sc->stats.roc + 4371 sc->stats.mpc + sc->stats.cexterr); 4372 case IFCOUNTER_OERRORS: 4373 return (sc->stats.ecol + sc->stats.latecol + 4374 sc->watchdog_events); 4375 default: 4376 return (if_get_counter_default(ifp, cnt)); 4377 } 4378 } 4379 4380 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4381 * @ctx: iflib context 4382 * @event: event code to check 4383 * 4384 * Defaults to returning true for unknown events. 4385 * 4386 * @returns true if iflib needs to reinit the interface 4387 */ 4388 static bool 4389 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4390 { 4391 switch (event) { 4392 case IFLIB_RESTART_VLAN_CONFIG: 4393 return (false); 4394 default: 4395 return (true); 4396 } 4397 } 4398 4399 /* Export a single 32-bit register via a read-only sysctl. */ 4400 static int 4401 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4402 { 4403 struct e1000_softc *sc; 4404 u_int val; 4405 4406 sc = oidp->oid_arg1; 4407 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4408 return (sysctl_handle_int(oidp, &val, 0, req)); 4409 } 4410 4411 /* 4412 * Add sysctl variables, one per statistic, to the system. 4413 */ 4414 static void 4415 em_add_hw_stats(struct e1000_softc *sc) 4416 { 4417 device_t dev = iflib_get_dev(sc->ctx); 4418 struct em_tx_queue *tx_que = sc->tx_queues; 4419 struct em_rx_queue *rx_que = sc->rx_queues; 4420 4421 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4422 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4423 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4424 struct e1000_hw_stats *stats = &sc->stats; 4425 4426 struct sysctl_oid *stat_node, *queue_node, *int_node; 4427 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4428 4429 #define QUEUE_NAME_LEN 32 4430 char namebuf[QUEUE_NAME_LEN]; 4431 4432 /* Driver Statistics */ 4433 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4434 CTLFLAG_RD, &sc->dropped_pkts, 4435 "Driver dropped packets"); 4436 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4437 CTLFLAG_RD, &sc->link_irq, 4438 "Link MSI-X IRQ Handled"); 4439 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4440 CTLFLAG_RD, &sc->rx_overruns, 4441 "RX overruns"); 4442 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4443 CTLFLAG_RD, &sc->watchdog_events, 4444 "Watchdog timeouts"); 4445 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4446 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4447 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4448 "Device Control Register"); 4449 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4450 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4451 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4452 "Receiver Control Register"); 4453 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4454 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4455 "Flow Control High Watermark"); 4456 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4457 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4458 "Flow Control Low Watermark"); 4459 4460 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4461 struct tx_ring *txr = &tx_que->txr; 4462 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4463 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4464 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4465 queue_list = SYSCTL_CHILDREN(queue_node); 4466 4467 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4468 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4469 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4470 "Transmit Descriptor Head"); 4471 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4472 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4473 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4474 "Transmit Descriptor Tail"); 4475 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4476 CTLFLAG_RD, &txr->tx_irq, 4477 "Queue MSI-X Transmit Interrupts"); 4478 } 4479 4480 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4481 struct rx_ring *rxr = &rx_que->rxr; 4482 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4483 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4484 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4485 queue_list = SYSCTL_CHILDREN(queue_node); 4486 4487 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4488 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4489 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4490 "Receive Descriptor Head"); 4491 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4492 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4493 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4494 "Receive Descriptor Tail"); 4495 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4496 CTLFLAG_RD, &rxr->rx_irq, 4497 "Queue MSI-X Receive Interrupts"); 4498 } 4499 4500 /* MAC stats get their own sub node */ 4501 4502 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4503 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4504 stat_list = SYSCTL_CHILDREN(stat_node); 4505 4506 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4507 CTLFLAG_RD, &stats->ecol, 4508 "Excessive collisions"); 4509 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4510 CTLFLAG_RD, &stats->scc, 4511 "Single collisions"); 4512 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4513 CTLFLAG_RD, &stats->mcc, 4514 "Multiple collisions"); 4515 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4516 CTLFLAG_RD, &stats->latecol, 4517 "Late collisions"); 4518 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4519 CTLFLAG_RD, &stats->colc, 4520 "Collision Count"); 4521 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4522 CTLFLAG_RD, &sc->stats.symerrs, 4523 "Symbol Errors"); 4524 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4525 CTLFLAG_RD, &sc->stats.sec, 4526 "Sequence Errors"); 4527 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4528 CTLFLAG_RD, &sc->stats.dc, 4529 "Defer Count"); 4530 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4531 CTLFLAG_RD, &sc->stats.mpc, 4532 "Missed Packets"); 4533 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4534 CTLFLAG_RD, &sc->stats.rnbc, 4535 "Receive No Buffers"); 4536 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4537 CTLFLAG_RD, &sc->stats.ruc, 4538 "Receive Undersize"); 4539 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4540 CTLFLAG_RD, &sc->stats.rfc, 4541 "Fragmented Packets Received "); 4542 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4543 CTLFLAG_RD, &sc->stats.roc, 4544 "Oversized Packets Received"); 4545 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4546 CTLFLAG_RD, &sc->stats.rjc, 4547 "Recevied Jabber"); 4548 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4549 CTLFLAG_RD, &sc->stats.rxerrc, 4550 "Receive Errors"); 4551 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4552 CTLFLAG_RD, &sc->stats.crcerrs, 4553 "CRC errors"); 4554 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4555 CTLFLAG_RD, &sc->stats.algnerrc, 4556 "Alignment Errors"); 4557 /* On 82575 these are collision counts */ 4558 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4559 CTLFLAG_RD, &sc->stats.cexterr, 4560 "Collision/Carrier extension errors"); 4561 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4562 CTLFLAG_RD, &sc->stats.xonrxc, 4563 "XON Received"); 4564 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4565 CTLFLAG_RD, &sc->stats.xontxc, 4566 "XON Transmitted"); 4567 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4568 CTLFLAG_RD, &sc->stats.xoffrxc, 4569 "XOFF Received"); 4570 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4571 CTLFLAG_RD, &sc->stats.xofftxc, 4572 "XOFF Transmitted"); 4573 4574 /* Packet Reception Stats */ 4575 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4576 CTLFLAG_RD, &sc->stats.tpr, 4577 "Total Packets Received "); 4578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4579 CTLFLAG_RD, &sc->stats.gprc, 4580 "Good Packets Received"); 4581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4582 CTLFLAG_RD, &sc->stats.bprc, 4583 "Broadcast Packets Received"); 4584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4585 CTLFLAG_RD, &sc->stats.mprc, 4586 "Multicast Packets Received"); 4587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4588 CTLFLAG_RD, &sc->stats.prc64, 4589 "64 byte frames received "); 4590 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4591 CTLFLAG_RD, &sc->stats.prc127, 4592 "65-127 byte frames received"); 4593 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4594 CTLFLAG_RD, &sc->stats.prc255, 4595 "128-255 byte frames received"); 4596 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4597 CTLFLAG_RD, &sc->stats.prc511, 4598 "256-511 byte frames received"); 4599 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4600 CTLFLAG_RD, &sc->stats.prc1023, 4601 "512-1023 byte frames received"); 4602 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4603 CTLFLAG_RD, &sc->stats.prc1522, 4604 "1023-1522 byte frames received"); 4605 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4606 CTLFLAG_RD, &sc->stats.gorc, 4607 "Good Octets Received"); 4608 4609 /* Packet Transmission Stats */ 4610 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4611 CTLFLAG_RD, &sc->stats.gotc, 4612 "Good Octets Transmitted"); 4613 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4614 CTLFLAG_RD, &sc->stats.tpt, 4615 "Total Packets Transmitted"); 4616 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4617 CTLFLAG_RD, &sc->stats.gptc, 4618 "Good Packets Transmitted"); 4619 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4620 CTLFLAG_RD, &sc->stats.bptc, 4621 "Broadcast Packets Transmitted"); 4622 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4623 CTLFLAG_RD, &sc->stats.mptc, 4624 "Multicast Packets Transmitted"); 4625 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4626 CTLFLAG_RD, &sc->stats.ptc64, 4627 "64 byte frames transmitted "); 4628 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4629 CTLFLAG_RD, &sc->stats.ptc127, 4630 "65-127 byte frames transmitted"); 4631 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4632 CTLFLAG_RD, &sc->stats.ptc255, 4633 "128-255 byte frames transmitted"); 4634 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4635 CTLFLAG_RD, &sc->stats.ptc511, 4636 "256-511 byte frames transmitted"); 4637 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4638 CTLFLAG_RD, &sc->stats.ptc1023, 4639 "512-1023 byte frames transmitted"); 4640 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4641 CTLFLAG_RD, &sc->stats.ptc1522, 4642 "1024-1522 byte frames transmitted"); 4643 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4644 CTLFLAG_RD, &sc->stats.tsctc, 4645 "TSO Contexts Transmitted"); 4646 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4647 CTLFLAG_RD, &sc->stats.tsctfc, 4648 "TSO Contexts Failed"); 4649 4650 4651 /* Interrupt Stats */ 4652 4653 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4654 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4655 int_list = SYSCTL_CHILDREN(int_node); 4656 4657 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4658 CTLFLAG_RD, &sc->stats.iac, 4659 "Interrupt Assertion Count"); 4660 4661 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4662 CTLFLAG_RD, &sc->stats.icrxptc, 4663 "Interrupt Cause Rx Pkt Timer Expire Count"); 4664 4665 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4666 CTLFLAG_RD, &sc->stats.icrxatc, 4667 "Interrupt Cause Rx Abs Timer Expire Count"); 4668 4669 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4670 CTLFLAG_RD, &sc->stats.ictxptc, 4671 "Interrupt Cause Tx Pkt Timer Expire Count"); 4672 4673 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4674 CTLFLAG_RD, &sc->stats.ictxatc, 4675 "Interrupt Cause Tx Abs Timer Expire Count"); 4676 4677 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4678 CTLFLAG_RD, &sc->stats.ictxqec, 4679 "Interrupt Cause Tx Queue Empty Count"); 4680 4681 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4682 CTLFLAG_RD, &sc->stats.ictxqmtc, 4683 "Interrupt Cause Tx Queue Min Thresh Count"); 4684 4685 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4686 CTLFLAG_RD, &sc->stats.icrxdmtc, 4687 "Interrupt Cause Rx Desc Min Thresh Count"); 4688 4689 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4690 CTLFLAG_RD, &sc->stats.icrxoc, 4691 "Interrupt Cause Receiver Overrun Count"); 4692 } 4693 4694 static void 4695 em_fw_version_locked(if_ctx_t ctx) 4696 { 4697 struct e1000_softc *sc = iflib_get_softc(ctx); 4698 struct e1000_hw *hw = &sc->hw; 4699 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4700 uint16_t eep = 0; 4701 4702 /* 4703 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4704 * NVM locking model, so we do it in em_if_attach_pre() and store the 4705 * info in the softc 4706 */ 4707 ASSERT_CTX_LOCK_HELD(hw); 4708 4709 *fw_ver = (struct e1000_fw_version){0}; 4710 4711 if (hw->mac.type >= igb_mac_min) { 4712 /* 4713 * Use the Shared Code for igb(4) 4714 */ 4715 e1000_get_fw_version(hw, fw_ver); 4716 } else { 4717 /* 4718 * Otherwise, EEPROM version should be present on (almost?) all 4719 * devices here 4720 */ 4721 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4722 INIT_DEBUGOUT("can't get EEPROM version"); 4723 return; 4724 } 4725 4726 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4727 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4728 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4729 } 4730 } 4731 4732 static void 4733 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4734 { 4735 const char *space = ""; 4736 4737 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4738 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4739 fw_ver->eep_minor, fw_ver->eep_build); 4740 space = " "; 4741 } 4742 4743 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4744 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4745 space, fw_ver->invm_major, fw_ver->invm_minor, 4746 fw_ver->invm_img_type); 4747 space = " "; 4748 } 4749 4750 if (fw_ver->or_valid) { 4751 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4752 space, fw_ver->or_major, fw_ver->or_build, 4753 fw_ver->or_patch); 4754 space = " "; 4755 } 4756 4757 if (fw_ver->etrack_id) 4758 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4759 } 4760 4761 static void 4762 em_print_fw_version(struct e1000_softc *sc ) 4763 { 4764 device_t dev = sc->dev; 4765 struct sbuf *buf; 4766 int error = 0; 4767 4768 buf = sbuf_new_auto(); 4769 if (!buf) { 4770 device_printf(dev, "Could not allocate sbuf for output.\n"); 4771 return; 4772 } 4773 4774 em_sbuf_fw_version(&sc->fw_ver, buf); 4775 4776 error = sbuf_finish(buf); 4777 if (error) 4778 device_printf(dev, "Error finishing sbuf: %d\n", error); 4779 else if (sbuf_len(buf)) 4780 device_printf(dev, "%s\n", sbuf_data(buf)); 4781 4782 sbuf_delete(buf); 4783 } 4784 4785 static int 4786 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4787 { 4788 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4789 device_t dev = sc->dev; 4790 struct sbuf *buf; 4791 int error = 0; 4792 4793 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4794 if (!buf) { 4795 device_printf(dev, "Could not allocate sbuf for output.\n"); 4796 return (ENOMEM); 4797 } 4798 4799 em_sbuf_fw_version(&sc->fw_ver, buf); 4800 4801 error = sbuf_finish(buf); 4802 if (error) 4803 device_printf(dev, "Error finishing sbuf: %d\n", error); 4804 4805 sbuf_delete(buf); 4806 4807 return (0); 4808 } 4809 4810 /********************************************************************** 4811 * 4812 * This routine provides a way to dump out the adapter eeprom, 4813 * often a useful debug/service tool. This only dumps the first 4814 * 32 words, stuff that matters is in that extent. 4815 * 4816 **********************************************************************/ 4817 static int 4818 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4819 { 4820 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4821 int error; 4822 int result; 4823 4824 result = -1; 4825 error = sysctl_handle_int(oidp, &result, 0, req); 4826 4827 if (error || !req->newptr) 4828 return (error); 4829 4830 /* 4831 * This value will cause a hex dump of the 4832 * first 32 16-bit words of the EEPROM to 4833 * the screen. 4834 */ 4835 if (result == 1) 4836 em_print_nvm_info(sc); 4837 4838 return (error); 4839 } 4840 4841 static void 4842 em_print_nvm_info(struct e1000_softc *sc) 4843 { 4844 struct e1000_hw *hw = &sc->hw; 4845 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4846 u16 eeprom_data; 4847 int i, j, row = 0; 4848 4849 /* Its a bit crude, but it gets the job done */ 4850 printf("\nInterface EEPROM Dump:\n"); 4851 printf("Offset\n0x0000 "); 4852 4853 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4854 sx_xlock(iflib_ctx_lock); 4855 ASSERT_CTX_LOCK_HELD(hw); 4856 for (i = 0, j = 0; i < 32; i++, j++) { 4857 if (j == 8) { /* Make the offset block */ 4858 j = 0; ++row; 4859 printf("\n0x00%x0 ",row); 4860 } 4861 e1000_read_nvm(hw, i, 1, &eeprom_data); 4862 printf("%04x ", eeprom_data); 4863 } 4864 sx_xunlock(iflib_ctx_lock); 4865 printf("\n"); 4866 } 4867 4868 static int 4869 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4870 { 4871 struct em_int_delay_info *info; 4872 struct e1000_softc *sc; 4873 u32 regval; 4874 int error, usecs, ticks; 4875 4876 info = (struct em_int_delay_info *) arg1; 4877 usecs = info->value; 4878 error = sysctl_handle_int(oidp, &usecs, 0, req); 4879 if (error != 0 || req->newptr == NULL) 4880 return (error); 4881 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4882 return (EINVAL); 4883 info->value = usecs; 4884 ticks = EM_USECS_TO_TICKS(usecs); 4885 if (info->offset == E1000_ITR) /* units are 256ns here */ 4886 ticks *= 4; 4887 4888 sc = info->sc; 4889 4890 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4891 regval = (regval & ~0xffff) | (ticks & 0xffff); 4892 /* Handle a few special cases. */ 4893 switch (info->offset) { 4894 case E1000_RDTR: 4895 break; 4896 case E1000_TIDV: 4897 if (ticks == 0) { 4898 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4899 /* Don't write 0 into the TIDV register. */ 4900 regval++; 4901 } else 4902 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4903 break; 4904 } 4905 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4906 return (0); 4907 } 4908 4909 static void 4910 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4911 const char *description, struct em_int_delay_info *info, 4912 int offset, int value) 4913 { 4914 info->sc = sc; 4915 info->offset = offset; 4916 info->value = value; 4917 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4918 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4919 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4920 info, 0, em_sysctl_int_delay, "I", description); 4921 } 4922 4923 /* 4924 * Set flow control using sysctl: 4925 * Flow control values: 4926 * 0 - off 4927 * 1 - rx pause 4928 * 2 - tx pause 4929 * 3 - full 4930 */ 4931 static int 4932 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4933 { 4934 int error; 4935 static int input = 3; /* default is full */ 4936 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4937 4938 error = sysctl_handle_int(oidp, &input, 0, req); 4939 4940 if ((error) || (req->newptr == NULL)) 4941 return (error); 4942 4943 if (input == sc->fc) /* no change? */ 4944 return (error); 4945 4946 switch (input) { 4947 case e1000_fc_rx_pause: 4948 case e1000_fc_tx_pause: 4949 case e1000_fc_full: 4950 case e1000_fc_none: 4951 sc->hw.fc.requested_mode = input; 4952 sc->fc = input; 4953 break; 4954 default: 4955 /* Do nothing */ 4956 return (error); 4957 } 4958 4959 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4960 e1000_force_mac_fc(&sc->hw); 4961 return (error); 4962 } 4963 4964 /* 4965 * Manage Energy Efficient Ethernet: 4966 * Control values: 4967 * 0/1 - enabled/disabled 4968 */ 4969 static int 4970 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4971 { 4972 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4973 int error, value; 4974 4975 value = sc->hw.dev_spec.ich8lan.eee_disable; 4976 error = sysctl_handle_int(oidp, &value, 0, req); 4977 if (error || req->newptr == NULL) 4978 return (error); 4979 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4980 em_if_init(sc->ctx); 4981 4982 return (0); 4983 } 4984 4985 static int 4986 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4987 { 4988 struct e1000_softc *sc; 4989 int error; 4990 int result; 4991 4992 result = -1; 4993 error = sysctl_handle_int(oidp, &result, 0, req); 4994 4995 if (error || !req->newptr) 4996 return (error); 4997 4998 if (result == 1) { 4999 sc = (struct e1000_softc *) arg1; 5000 em_print_debug_info(sc); 5001 } 5002 5003 return (error); 5004 } 5005 5006 static int 5007 em_get_rs(SYSCTL_HANDLER_ARGS) 5008 { 5009 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5010 int error; 5011 int result; 5012 5013 result = 0; 5014 error = sysctl_handle_int(oidp, &result, 0, req); 5015 5016 if (error || !req->newptr || result != 1) 5017 return (error); 5018 em_dump_rs(sc); 5019 5020 return (error); 5021 } 5022 5023 static void 5024 em_if_debug(if_ctx_t ctx) 5025 { 5026 em_dump_rs(iflib_get_softc(ctx)); 5027 } 5028 5029 /* 5030 * This routine is meant to be fluid, add whatever is 5031 * needed for debugging a problem. -jfv 5032 */ 5033 static void 5034 em_print_debug_info(struct e1000_softc *sc) 5035 { 5036 device_t dev = iflib_get_dev(sc->ctx); 5037 if_t ifp = iflib_get_ifp(sc->ctx); 5038 struct tx_ring *txr = &sc->tx_queues->txr; 5039 struct rx_ring *rxr = &sc->rx_queues->rxr; 5040 5041 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5042 printf("Interface is RUNNING "); 5043 else 5044 printf("Interface is NOT RUNNING\n"); 5045 5046 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5047 printf("and INACTIVE\n"); 5048 else 5049 printf("and ACTIVE\n"); 5050 5051 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5052 device_printf(dev, "TX Queue %d ------\n", i); 5053 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5054 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5055 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5056 5057 } 5058 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5059 device_printf(dev, "RX Queue %d ------\n", j); 5060 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5061 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5062 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5063 } 5064 } 5065 5066 /* 5067 * 82574 only: 5068 * Write a new value to the EEPROM increasing the number of MSI-X 5069 * vectors from 3 to 5, for proper multiqueue support. 5070 */ 5071 static void 5072 em_enable_vectors_82574(if_ctx_t ctx) 5073 { 5074 struct e1000_softc *sc = iflib_get_softc(ctx); 5075 struct e1000_hw *hw = &sc->hw; 5076 device_t dev = iflib_get_dev(ctx); 5077 u16 edata; 5078 5079 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5080 if (bootverbose) 5081 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5082 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5083 device_printf(dev, "Writing to eeprom: increasing " 5084 "reported MSI-X vectors from 3 to 5...\n"); 5085 edata &= ~(EM_NVM_MSIX_N_MASK); 5086 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5087 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5088 e1000_update_nvm_checksum(hw); 5089 device_printf(dev, "Writing to eeprom: done\n"); 5090 } 5091 } 5092