1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 /* required last entry */ 178 PVID_END 179 }; 180 181 static pci_vendor_info_t igb_vendor_info_array[] = 182 { 183 /* Intel(R) PRO/1000 Network Connection - igb */ 184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 /* required last entry */ 224 PVID_END 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 static void *em_register(device_t dev); 231 static void *igb_register(device_t dev); 232 static int em_if_attach_pre(if_ctx_t ctx); 233 static int em_if_attach_post(if_ctx_t ctx); 234 static int em_if_detach(if_ctx_t ctx); 235 static int em_if_shutdown(if_ctx_t ctx); 236 static int em_if_suspend(if_ctx_t ctx); 237 static int em_if_resume(if_ctx_t ctx); 238 239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 241 static void em_if_queues_free(if_ctx_t ctx); 242 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 244 static void em_if_init(if_ctx_t ctx); 245 static void em_if_stop(if_ctx_t ctx); 246 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 247 static int em_if_media_change(if_ctx_t ctx); 248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 249 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 252 253 static void em_identify_hardware(if_ctx_t ctx); 254 static int em_allocate_pci_resources(if_ctx_t ctx); 255 static void em_free_pci_resources(if_ctx_t ctx); 256 static void em_reset(if_ctx_t ctx); 257 static int em_setup_interface(if_ctx_t ctx); 258 static int em_setup_msix(if_ctx_t ctx); 259 260 static void em_initialize_transmit_unit(if_ctx_t ctx); 261 static void em_initialize_receive_unit(if_ctx_t ctx); 262 263 static void em_if_enable_intr(if_ctx_t ctx); 264 static void em_if_disable_intr(if_ctx_t ctx); 265 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 266 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 267 static void em_if_multi_set(if_ctx_t ctx); 268 static void em_if_update_admin_status(if_ctx_t ctx); 269 static void em_if_debug(if_ctx_t ctx); 270 static void em_update_stats_counters(struct adapter *); 271 static void em_add_hw_stats(struct adapter *adapter); 272 static int em_if_set_promisc(if_ctx_t ctx, int flags); 273 static void em_setup_vlan_hw_support(struct adapter *); 274 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 275 static void em_print_nvm_info(struct adapter *); 276 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 277 static int em_get_rs(SYSCTL_HANDLER_ARGS); 278 static void em_print_debug_info(struct adapter *); 279 static int em_is_valid_ether_addr(u8 *); 280 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 281 static void em_add_int_delay_sysctl(struct adapter *, const char *, 282 const char *, struct em_int_delay_info *, int, int); 283 /* Management and WOL Support */ 284 static void em_init_manageability(struct adapter *); 285 static void em_release_manageability(struct adapter *); 286 static void em_get_hw_control(struct adapter *); 287 static void em_release_hw_control(struct adapter *); 288 static void em_get_wakeup(if_ctx_t ctx); 289 static void em_enable_wakeup(if_ctx_t ctx); 290 static int em_enable_phy_wakeup(struct adapter *); 291 static void em_disable_aspm(struct adapter *); 292 293 int em_intr(void *arg); 294 static void em_disable_promisc(if_ctx_t ctx); 295 296 /* MSIX handlers */ 297 static int em_if_msix_intr_assign(if_ctx_t, int); 298 static int em_msix_link(void *); 299 static void em_handle_link(void *context); 300 301 static void em_enable_vectors_82574(if_ctx_t); 302 303 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 304 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 305 static void em_if_led_func(if_ctx_t ctx, int onoff); 306 307 static int em_get_regs(SYSCTL_HANDLER_ARGS); 308 309 static void lem_smartspeed(struct adapter *adapter); 310 static void igb_configure_queues(struct adapter *adapter); 311 312 313 /********************************************************************* 314 * FreeBSD Device Interface Entry Points 315 *********************************************************************/ 316 static device_method_t em_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_register, em_register), 319 DEVMETHOD(device_probe, iflib_device_probe), 320 DEVMETHOD(device_attach, iflib_device_attach), 321 DEVMETHOD(device_detach, iflib_device_detach), 322 DEVMETHOD(device_shutdown, iflib_device_shutdown), 323 DEVMETHOD(device_suspend, iflib_device_suspend), 324 DEVMETHOD(device_resume, iflib_device_resume), 325 DEVMETHOD_END 326 }; 327 328 static device_method_t igb_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, igb_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 341 static driver_t em_driver = { 342 "em", em_methods, sizeof(struct adapter), 343 }; 344 345 static devclass_t em_devclass; 346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 347 348 MODULE_DEPEND(em, pci, 1, 1, 1); 349 MODULE_DEPEND(em, ether, 1, 1, 1); 350 MODULE_DEPEND(em, iflib, 1, 1, 1); 351 352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 353 354 static driver_t igb_driver = { 355 "igb", igb_methods, sizeof(struct adapter), 356 }; 357 358 static devclass_t igb_devclass; 359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 360 361 MODULE_DEPEND(igb, pci, 1, 1, 1); 362 MODULE_DEPEND(igb, ether, 1, 1, 1); 363 MODULE_DEPEND(igb, iflib, 1, 1, 1); 364 365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 366 367 static device_method_t em_if_methods[] = { 368 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 369 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 370 DEVMETHOD(ifdi_detach, em_if_detach), 371 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 372 DEVMETHOD(ifdi_suspend, em_if_suspend), 373 DEVMETHOD(ifdi_resume, em_if_resume), 374 DEVMETHOD(ifdi_init, em_if_init), 375 DEVMETHOD(ifdi_stop, em_if_stop), 376 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 377 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 378 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 379 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 380 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 381 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 382 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 383 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 384 DEVMETHOD(ifdi_media_status, em_if_media_status), 385 DEVMETHOD(ifdi_media_change, em_if_media_change), 386 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 387 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 388 DEVMETHOD(ifdi_timer, em_if_timer), 389 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 390 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 391 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 392 DEVMETHOD(ifdi_led_func, em_if_led_func), 393 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 394 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 395 DEVMETHOD(ifdi_debug, em_if_debug), 396 DEVMETHOD_END 397 }; 398 399 /* 400 * note that if (adapter->msix_mem) is replaced by: 401 * if (adapter->intr_type == IFLIB_INTR_MSIX) 402 */ 403 static driver_t em_if_driver = { 404 "em_if", em_if_methods, sizeof(struct adapter) 405 }; 406 407 /********************************************************************* 408 * Tunable default values. 409 *********************************************************************/ 410 411 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 412 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 413 414 #define MAX_INTS_PER_SEC 8000 415 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 416 417 /* Allow common code without TSO */ 418 #ifndef CSUM_TSO 419 #define CSUM_TSO 0 420 #endif 421 422 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 423 424 static int em_disable_crc_stripping = 0; 425 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 426 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 427 428 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 429 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 430 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 431 0, "Default transmit interrupt delay in usecs"); 432 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 433 0, "Default receive interrupt delay in usecs"); 434 435 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 436 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 437 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 438 &em_tx_abs_int_delay_dflt, 0, 439 "Default transmit interrupt delay limit in usecs"); 440 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 441 &em_rx_abs_int_delay_dflt, 0, 442 "Default receive interrupt delay limit in usecs"); 443 444 static int em_smart_pwr_down = FALSE; 445 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 446 0, "Set to true to leave smart power down enabled on newer adapters"); 447 448 /* Controls whether promiscuous also shows bad packets */ 449 static int em_debug_sbp = TRUE; 450 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 451 "Show bad packets in promiscuous mode"); 452 453 /* How many packets rxeof tries to clean at a time */ 454 static int em_rx_process_limit = 100; 455 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 456 &em_rx_process_limit, 0, 457 "Maximum number of received packets to process " 458 "at a time, -1 means unlimited"); 459 460 /* Energy efficient ethernet - default to OFF */ 461 static int eee_setting = 1; 462 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 463 "Enable Energy Efficient Ethernet"); 464 465 /* 466 ** Tuneable Interrupt rate 467 */ 468 static int em_max_interrupt_rate = 8000; 469 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 470 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 471 472 473 474 /* Global used in WOL setup with multiport cards */ 475 static int global_quad_port_a = 0; 476 477 extern struct if_txrx igb_txrx; 478 extern struct if_txrx em_txrx; 479 extern struct if_txrx lem_txrx; 480 481 static struct if_shared_ctx em_sctx_init = { 482 .isc_magic = IFLIB_MAGIC, 483 .isc_q_align = PAGE_SIZE, 484 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 485 .isc_tx_maxsegsize = PAGE_SIZE, 486 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 487 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 488 .isc_rx_maxsize = MJUM9BYTES, 489 .isc_rx_nsegments = 1, 490 .isc_rx_maxsegsize = MJUM9BYTES, 491 .isc_nfl = 1, 492 .isc_nrxqs = 1, 493 .isc_ntxqs = 1, 494 .isc_admin_intrcnt = 1, 495 .isc_vendor_info = em_vendor_info_array, 496 .isc_driver_version = em_driver_version, 497 .isc_driver = &em_if_driver, 498 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 499 500 .isc_nrxd_min = {EM_MIN_RXD}, 501 .isc_ntxd_min = {EM_MIN_TXD}, 502 .isc_nrxd_max = {EM_MAX_RXD}, 503 .isc_ntxd_max = {EM_MAX_TXD}, 504 .isc_nrxd_default = {EM_DEFAULT_RXD}, 505 .isc_ntxd_default = {EM_DEFAULT_TXD}, 506 }; 507 508 if_shared_ctx_t em_sctx = &em_sctx_init; 509 510 static struct if_shared_ctx igb_sctx_init = { 511 .isc_magic = IFLIB_MAGIC, 512 .isc_q_align = PAGE_SIZE, 513 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 514 .isc_tx_maxsegsize = PAGE_SIZE, 515 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 516 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 517 .isc_rx_maxsize = MJUM9BYTES, 518 .isc_rx_nsegments = 1, 519 .isc_rx_maxsegsize = MJUM9BYTES, 520 .isc_nfl = 1, 521 .isc_nrxqs = 1, 522 .isc_ntxqs = 1, 523 .isc_admin_intrcnt = 1, 524 .isc_vendor_info = igb_vendor_info_array, 525 .isc_driver_version = em_driver_version, 526 .isc_driver = &em_if_driver, 527 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 528 529 .isc_nrxd_min = {EM_MIN_RXD}, 530 .isc_ntxd_min = {EM_MIN_TXD}, 531 .isc_nrxd_max = {IGB_MAX_RXD}, 532 .isc_ntxd_max = {IGB_MAX_TXD}, 533 .isc_nrxd_default = {EM_DEFAULT_RXD}, 534 .isc_ntxd_default = {EM_DEFAULT_TXD}, 535 }; 536 537 if_shared_ctx_t igb_sctx = &igb_sctx_init; 538 539 /***************************************************************** 540 * 541 * Dump Registers 542 * 543 ****************************************************************/ 544 #define IGB_REGS_LEN 739 545 546 static int em_get_regs(SYSCTL_HANDLER_ARGS) 547 { 548 struct adapter *adapter = (struct adapter *)arg1; 549 struct e1000_hw *hw = &adapter->hw; 550 struct sbuf *sb; 551 u32 *regs_buff; 552 int rc; 553 554 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 555 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 556 557 rc = sysctl_wire_old_buffer(req, 0); 558 MPASS(rc == 0); 559 if (rc != 0) { 560 free(regs_buff, M_DEVBUF); 561 return (rc); 562 } 563 564 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 565 MPASS(sb != NULL); 566 if (sb == NULL) { 567 free(regs_buff, M_DEVBUF); 568 return (ENOMEM); 569 } 570 571 /* General Registers */ 572 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 573 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 574 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 575 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 576 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 577 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 578 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 579 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 580 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 581 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 582 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 583 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 584 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 585 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 586 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 587 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 588 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 589 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 590 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 591 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 592 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 593 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 594 595 sbuf_printf(sb, "General Registers\n"); 596 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 597 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 598 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 599 600 sbuf_printf(sb, "Interrupt Registers\n"); 601 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 602 603 sbuf_printf(sb, "RX Registers\n"); 604 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 605 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 606 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 607 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 608 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 609 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 610 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 611 612 sbuf_printf(sb, "TX Registers\n"); 613 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 614 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 615 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 616 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 617 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 618 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 619 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 620 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 621 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 622 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 623 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 624 625 free(regs_buff, M_DEVBUF); 626 627 #ifdef DUMP_DESCS 628 { 629 if_softc_ctx_t scctx = adapter->shared; 630 struct rx_ring *rxr = &rx_que->rxr; 631 struct tx_ring *txr = &tx_que->txr; 632 int ntxd = scctx->isc_ntxd[0]; 633 int nrxd = scctx->isc_nrxd[0]; 634 int j; 635 636 for (j = 0; j < nrxd; j++) { 637 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 638 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 639 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 640 } 641 642 for (j = 0; j < min(ntxd, 256); j++) { 643 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 644 645 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 646 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 647 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 648 649 } 650 } 651 #endif 652 653 rc = sbuf_finish(sb); 654 sbuf_delete(sb); 655 return(rc); 656 } 657 658 static void * 659 em_register(device_t dev) 660 { 661 return (em_sctx); 662 } 663 664 static void * 665 igb_register(device_t dev) 666 { 667 return (igb_sctx); 668 } 669 670 static int 671 em_set_num_queues(if_ctx_t ctx) 672 { 673 struct adapter *adapter = iflib_get_softc(ctx); 674 int maxqueues; 675 676 /* Sanity check based on HW */ 677 switch (adapter->hw.mac.type) { 678 case e1000_82576: 679 case e1000_82580: 680 case e1000_i350: 681 case e1000_i354: 682 maxqueues = 8; 683 break; 684 case e1000_i210: 685 case e1000_82575: 686 maxqueues = 4; 687 break; 688 case e1000_i211: 689 case e1000_82574: 690 maxqueues = 2; 691 break; 692 default: 693 maxqueues = 1; 694 break; 695 } 696 697 return (maxqueues); 698 } 699 700 #define LEM_CAPS \ 701 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 702 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 703 704 #define EM_CAPS \ 705 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 706 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 707 IFCAP_LRO | IFCAP_VLAN_HWTSO 708 709 #define IGB_CAPS \ 710 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 711 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 712 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 713 IFCAP_TSO6 714 715 /********************************************************************* 716 * Device initialization routine 717 * 718 * The attach entry point is called when the driver is being loaded. 719 * This routine identifies the type of hardware, allocates all resources 720 * and initializes the hardware. 721 * 722 * return 0 on success, positive on failure 723 *********************************************************************/ 724 725 static int 726 em_if_attach_pre(if_ctx_t ctx) 727 { 728 struct adapter *adapter; 729 if_softc_ctx_t scctx; 730 device_t dev; 731 struct e1000_hw *hw; 732 int error = 0; 733 734 INIT_DEBUGOUT("em_if_attach_pre begin"); 735 dev = iflib_get_dev(ctx); 736 adapter = iflib_get_softc(ctx); 737 738 if (resource_disabled("em", device_get_unit(dev))) { 739 device_printf(dev, "Disabled by device hint\n"); 740 return (ENXIO); 741 } 742 743 adapter->ctx = adapter->osdep.ctx = ctx; 744 adapter->dev = adapter->osdep.dev = dev; 745 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 746 adapter->media = iflib_get_media(ctx); 747 hw = &adapter->hw; 748 749 adapter->tx_process_limit = scctx->isc_ntxd[0]; 750 751 /* SYSCTL stuff */ 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 754 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 755 em_sysctl_nvm_info, "I", "NVM Information"); 756 757 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 759 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 760 em_sysctl_debug_info, "I", "Debug Information"); 761 762 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 763 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 764 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 765 em_set_flowcntl, "I", "Flow Control"); 766 767 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 768 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 769 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 770 em_get_regs, "A", "Dump Registers"); 771 772 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 773 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 774 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 775 em_get_rs, "I", "Dump RS indexes"); 776 777 /* Determine hardware and mac info */ 778 em_identify_hardware(ctx); 779 780 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 781 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 782 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 783 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 784 785 if (adapter->hw.mac.type >= igb_mac_min) { 786 int try_second_bar; 787 788 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 789 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 790 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 791 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 792 scctx->isc_txrx = &igb_txrx; 793 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 794 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 795 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 796 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 797 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 798 CSUM_IP6_TCP | CSUM_IP6_UDP; 799 if (adapter->hw.mac.type != e1000_82575) 800 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 801 802 /* 803 ** Some new devices, as with ixgbe, now may 804 ** use a different BAR, so we need to keep 805 ** track of which is used. 806 */ 807 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 808 if (try_second_bar == 0) 809 scctx->isc_msix_bar += 4; 810 } else if (adapter->hw.mac.type >= em_mac_min) { 811 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 812 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 813 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 814 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 815 scctx->isc_txrx = &em_txrx; 816 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 817 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 818 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 819 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 820 /* 821 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 822 * by default as we don't have workarounds for all associated 823 * silicon errata. E. g., with several MACs such as 82573E, 824 * TSO only works at Gigabit speed and otherwise can cause the 825 * hardware to hang (which also would be next to impossible to 826 * work around given that already queued TSO-using descriptors 827 * would need to be flushed and vlan(4) reconfigured at runtime 828 * in case of a link speed change). Moreover, MACs like 82579 829 * still can hang at Gigabit even with all publicly documented 830 * TSO workarounds implemented. Generally, the penality of 831 * these workarounds is rather high and may involve copying 832 * mbuf data around so advantages of TSO lapse. Still, TSO may 833 * work for a few MACs of this class - at least when sticking 834 * with Gigabit - in which case users may enable TSO manually. 835 */ 836 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 837 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 838 } else { 839 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 840 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 841 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 842 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 843 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 844 scctx->isc_txrx = &lem_txrx; 845 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 846 if (adapter->hw.mac.type < e1000_82543) 847 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 848 scctx->isc_msix_bar = 0; 849 } 850 851 /* Setup PCI resources */ 852 if (em_allocate_pci_resources(ctx)) { 853 device_printf(dev, "Allocation of PCI resources failed\n"); 854 error = ENXIO; 855 goto err_pci; 856 } 857 858 /* 859 ** For ICH8 and family we need to 860 ** map the flash memory, and this 861 ** must happen after the MAC is 862 ** identified 863 */ 864 if ((hw->mac.type == e1000_ich8lan) || 865 (hw->mac.type == e1000_ich9lan) || 866 (hw->mac.type == e1000_ich10lan) || 867 (hw->mac.type == e1000_pchlan) || 868 (hw->mac.type == e1000_pch2lan) || 869 (hw->mac.type == e1000_pch_lpt)) { 870 int rid = EM_BAR_TYPE_FLASH; 871 adapter->flash = bus_alloc_resource_any(dev, 872 SYS_RES_MEMORY, &rid, RF_ACTIVE); 873 if (adapter->flash == NULL) { 874 device_printf(dev, "Mapping of Flash failed\n"); 875 error = ENXIO; 876 goto err_pci; 877 } 878 /* This is used in the shared code */ 879 hw->flash_address = (u8 *)adapter->flash; 880 adapter->osdep.flash_bus_space_tag = 881 rman_get_bustag(adapter->flash); 882 adapter->osdep.flash_bus_space_handle = 883 rman_get_bushandle(adapter->flash); 884 } 885 /* 886 ** In the new SPT device flash is not a 887 ** separate BAR, rather it is also in BAR0, 888 ** so use the same tag and an offset handle for the 889 ** FLASH read/write macros in the shared code. 890 */ 891 else if (hw->mac.type >= e1000_pch_spt) { 892 adapter->osdep.flash_bus_space_tag = 893 adapter->osdep.mem_bus_space_tag; 894 adapter->osdep.flash_bus_space_handle = 895 adapter->osdep.mem_bus_space_handle 896 + E1000_FLASH_BASE_ADDR; 897 } 898 899 /* Do Shared Code initialization */ 900 error = e1000_setup_init_funcs(hw, TRUE); 901 if (error) { 902 device_printf(dev, "Setup of Shared code failed, error %d\n", 903 error); 904 error = ENXIO; 905 goto err_pci; 906 } 907 908 em_setup_msix(ctx); 909 e1000_get_bus_info(hw); 910 911 /* Set up some sysctls for the tunable interrupt delays */ 912 em_add_int_delay_sysctl(adapter, "rx_int_delay", 913 "receive interrupt delay in usecs", &adapter->rx_int_delay, 914 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 915 em_add_int_delay_sysctl(adapter, "tx_int_delay", 916 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 917 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 918 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 919 "receive interrupt delay limit in usecs", 920 &adapter->rx_abs_int_delay, 921 E1000_REGISTER(hw, E1000_RADV), 922 em_rx_abs_int_delay_dflt); 923 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 924 "transmit interrupt delay limit in usecs", 925 &adapter->tx_abs_int_delay, 926 E1000_REGISTER(hw, E1000_TADV), 927 em_tx_abs_int_delay_dflt); 928 em_add_int_delay_sysctl(adapter, "itr", 929 "interrupt delay limit in usecs/4", 930 &adapter->tx_itr, 931 E1000_REGISTER(hw, E1000_ITR), 932 DEFAULT_ITR); 933 934 hw->mac.autoneg = DO_AUTO_NEG; 935 hw->phy.autoneg_wait_to_complete = FALSE; 936 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 937 938 if (adapter->hw.mac.type < em_mac_min) { 939 e1000_init_script_state_82541(&adapter->hw, TRUE); 940 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 941 } 942 /* Copper options */ 943 if (hw->phy.media_type == e1000_media_type_copper) { 944 hw->phy.mdix = AUTO_ALL_MODES; 945 hw->phy.disable_polarity_correction = FALSE; 946 hw->phy.ms_type = EM_MASTER_SLAVE; 947 } 948 949 /* 950 * Set the frame limits assuming 951 * standard ethernet sized frames. 952 */ 953 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 954 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 955 956 /* 957 * This controls when hardware reports transmit completion 958 * status. 959 */ 960 hw->mac.report_tx_early = 1; 961 962 /* Allocate multicast array memory. */ 963 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 964 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 965 if (adapter->mta == NULL) { 966 device_printf(dev, "Can not allocate multicast setup array\n"); 967 error = ENOMEM; 968 goto err_late; 969 } 970 971 /* Check SOL/IDER usage */ 972 if (e1000_check_reset_block(hw)) 973 device_printf(dev, "PHY reset is blocked" 974 " due to SOL/IDER session.\n"); 975 976 /* Sysctl for setting Energy Efficient Ethernet */ 977 hw->dev_spec.ich8lan.eee_disable = eee_setting; 978 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 979 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 980 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 981 adapter, 0, em_sysctl_eee, "I", 982 "Disable Energy Efficient Ethernet"); 983 984 /* 985 ** Start from a known state, this is 986 ** important in reading the nvm and 987 ** mac from that. 988 */ 989 e1000_reset_hw(hw); 990 991 /* Make sure we have a good EEPROM before we read from it */ 992 if (e1000_validate_nvm_checksum(hw) < 0) { 993 /* 994 ** Some PCI-E parts fail the first check due to 995 ** the link being in sleep state, call it again, 996 ** if it fails a second time its a real issue. 997 */ 998 if (e1000_validate_nvm_checksum(hw) < 0) { 999 device_printf(dev, 1000 "The EEPROM Checksum Is Not Valid\n"); 1001 error = EIO; 1002 goto err_late; 1003 } 1004 } 1005 1006 /* Copy the permanent MAC address out of the EEPROM */ 1007 if (e1000_read_mac_addr(hw) < 0) { 1008 device_printf(dev, "EEPROM read error while reading MAC" 1009 " address\n"); 1010 error = EIO; 1011 goto err_late; 1012 } 1013 1014 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1015 device_printf(dev, "Invalid MAC address\n"); 1016 error = EIO; 1017 goto err_late; 1018 } 1019 1020 /* Disable ULP support */ 1021 e1000_disable_ulp_lpt_lp(hw, TRUE); 1022 1023 /* 1024 * Get Wake-on-Lan and Management info for later use 1025 */ 1026 em_get_wakeup(ctx); 1027 1028 /* Enable only WOL MAGIC by default */ 1029 scctx->isc_capenable &= ~IFCAP_WOL; 1030 if (adapter->wol != 0) 1031 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1032 1033 iflib_set_mac(ctx, hw->mac.addr); 1034 1035 return (0); 1036 1037 err_late: 1038 em_release_hw_control(adapter); 1039 err_pci: 1040 em_free_pci_resources(ctx); 1041 free(adapter->mta, M_DEVBUF); 1042 1043 return (error); 1044 } 1045 1046 static int 1047 em_if_attach_post(if_ctx_t ctx) 1048 { 1049 struct adapter *adapter = iflib_get_softc(ctx); 1050 struct e1000_hw *hw = &adapter->hw; 1051 int error = 0; 1052 1053 /* Setup OS specific network interface */ 1054 error = em_setup_interface(ctx); 1055 if (error != 0) { 1056 goto err_late; 1057 } 1058 1059 em_reset(ctx); 1060 1061 /* Initialize statistics */ 1062 em_update_stats_counters(adapter); 1063 hw->mac.get_link_status = 1; 1064 em_if_update_admin_status(ctx); 1065 em_add_hw_stats(adapter); 1066 1067 /* Non-AMT based hardware can now take control from firmware */ 1068 if (adapter->has_manage && !adapter->has_amt) 1069 em_get_hw_control(adapter); 1070 1071 INIT_DEBUGOUT("em_if_attach_post: end"); 1072 1073 return (error); 1074 1075 err_late: 1076 em_release_hw_control(adapter); 1077 em_free_pci_resources(ctx); 1078 em_if_queues_free(ctx); 1079 free(adapter->mta, M_DEVBUF); 1080 1081 return (error); 1082 } 1083 1084 /********************************************************************* 1085 * Device removal routine 1086 * 1087 * The detach entry point is called when the driver is being removed. 1088 * This routine stops the adapter and deallocates all the resources 1089 * that were allocated for driver operation. 1090 * 1091 * return 0 on success, positive on failure 1092 *********************************************************************/ 1093 1094 static int 1095 em_if_detach(if_ctx_t ctx) 1096 { 1097 struct adapter *adapter = iflib_get_softc(ctx); 1098 1099 INIT_DEBUGOUT("em_detach: begin"); 1100 1101 e1000_phy_hw_reset(&adapter->hw); 1102 1103 em_release_manageability(adapter); 1104 em_release_hw_control(adapter); 1105 em_free_pci_resources(ctx); 1106 1107 return (0); 1108 } 1109 1110 /********************************************************************* 1111 * 1112 * Shutdown entry point 1113 * 1114 **********************************************************************/ 1115 1116 static int 1117 em_if_shutdown(if_ctx_t ctx) 1118 { 1119 return em_if_suspend(ctx); 1120 } 1121 1122 /* 1123 * Suspend/resume device methods. 1124 */ 1125 static int 1126 em_if_suspend(if_ctx_t ctx) 1127 { 1128 struct adapter *adapter = iflib_get_softc(ctx); 1129 1130 em_release_manageability(adapter); 1131 em_release_hw_control(adapter); 1132 em_enable_wakeup(ctx); 1133 return (0); 1134 } 1135 1136 static int 1137 em_if_resume(if_ctx_t ctx) 1138 { 1139 struct adapter *adapter = iflib_get_softc(ctx); 1140 1141 if (adapter->hw.mac.type == e1000_pch2lan) 1142 e1000_resume_workarounds_pchlan(&adapter->hw); 1143 em_if_init(ctx); 1144 em_init_manageability(adapter); 1145 1146 return(0); 1147 } 1148 1149 static int 1150 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1151 { 1152 int max_frame_size; 1153 struct adapter *adapter = iflib_get_softc(ctx); 1154 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1155 1156 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1157 1158 switch (adapter->hw.mac.type) { 1159 case e1000_82571: 1160 case e1000_82572: 1161 case e1000_ich9lan: 1162 case e1000_ich10lan: 1163 case e1000_pch2lan: 1164 case e1000_pch_lpt: 1165 case e1000_pch_spt: 1166 case e1000_pch_cnp: 1167 case e1000_82574: 1168 case e1000_82583: 1169 case e1000_80003es2lan: 1170 /* 9K Jumbo Frame size */ 1171 max_frame_size = 9234; 1172 break; 1173 case e1000_pchlan: 1174 max_frame_size = 4096; 1175 break; 1176 case e1000_82542: 1177 case e1000_ich8lan: 1178 /* Adapters that do not support jumbo frames */ 1179 max_frame_size = ETHER_MAX_LEN; 1180 break; 1181 default: 1182 if (adapter->hw.mac.type >= igb_mac_min) 1183 max_frame_size = 9234; 1184 else /* lem */ 1185 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1186 } 1187 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1188 return (EINVAL); 1189 } 1190 1191 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1192 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1193 return (0); 1194 } 1195 1196 /********************************************************************* 1197 * Init entry point 1198 * 1199 * This routine is used in two ways. It is used by the stack as 1200 * init entry point in network interface structure. It is also used 1201 * by the driver as a hw/sw initialization routine to get to a 1202 * consistent state. 1203 * 1204 * return 0 on success, positive on failure 1205 **********************************************************************/ 1206 1207 static void 1208 em_if_init(if_ctx_t ctx) 1209 { 1210 struct adapter *adapter = iflib_get_softc(ctx); 1211 struct ifnet *ifp = iflib_get_ifp(ctx); 1212 struct em_tx_queue *tx_que; 1213 int i; 1214 INIT_DEBUGOUT("em_if_init: begin"); 1215 1216 /* Get the latest mac address, User can use a LAA */ 1217 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1218 ETHER_ADDR_LEN); 1219 1220 /* Put the address into the Receive Address Array */ 1221 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1222 1223 /* 1224 * With the 82571 adapter, RAR[0] may be overwritten 1225 * when the other port is reset, we make a duplicate 1226 * in RAR[14] for that eventuality, this assures 1227 * the interface continues to function. 1228 */ 1229 if (adapter->hw.mac.type == e1000_82571) { 1230 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1231 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1232 E1000_RAR_ENTRIES - 1); 1233 } 1234 1235 1236 /* Initialize the hardware */ 1237 em_reset(ctx); 1238 em_if_update_admin_status(ctx); 1239 1240 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1241 struct tx_ring *txr = &tx_que->txr; 1242 1243 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1244 } 1245 1246 /* Setup VLAN support, basic and offload if available */ 1247 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1248 1249 /* Clear bad data from Rx FIFOs */ 1250 if (adapter->hw.mac.type >= igb_mac_min) 1251 e1000_rx_fifo_flush_82575(&adapter->hw); 1252 1253 /* Configure for OS presence */ 1254 em_init_manageability(adapter); 1255 1256 /* Prepare transmit descriptors and buffers */ 1257 em_initialize_transmit_unit(ctx); 1258 1259 /* Setup Multicast table */ 1260 em_if_multi_set(ctx); 1261 1262 /* 1263 * Figure out the desired mbuf 1264 * pool for doing jumbos 1265 */ 1266 if (adapter->hw.mac.max_frame_size <= 2048) 1267 adapter->rx_mbuf_sz = MCLBYTES; 1268 #ifndef CONTIGMALLOC_WORKS 1269 else 1270 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1271 #else 1272 else if (adapter->hw.mac.max_frame_size <= 4096) 1273 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1274 else 1275 adapter->rx_mbuf_sz = MJUM9BYTES; 1276 #endif 1277 em_initialize_receive_unit(ctx); 1278 1279 /* Use real VLAN Filter support? */ 1280 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1281 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1282 /* Use real VLAN Filter support */ 1283 em_setup_vlan_hw_support(adapter); 1284 else { 1285 u32 ctrl; 1286 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1287 ctrl |= E1000_CTRL_VME; 1288 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1289 } 1290 } 1291 1292 /* Don't lose promiscuous settings */ 1293 em_if_set_promisc(ctx, IFF_PROMISC); 1294 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1295 1296 /* MSI/X configuration for 82574 */ 1297 if (adapter->hw.mac.type == e1000_82574) { 1298 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1299 1300 tmp |= E1000_CTRL_EXT_PBA_CLR; 1301 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1302 /* Set the IVAR - interrupt vector routing. */ 1303 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1304 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1305 igb_configure_queues(adapter); 1306 1307 /* this clears any pending interrupts */ 1308 E1000_READ_REG(&adapter->hw, E1000_ICR); 1309 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1310 1311 /* AMT based hardware can now take control from firmware */ 1312 if (adapter->has_manage && adapter->has_amt) 1313 em_get_hw_control(adapter); 1314 1315 /* Set Energy Efficient Ethernet */ 1316 if (adapter->hw.mac.type >= igb_mac_min && 1317 adapter->hw.phy.media_type == e1000_media_type_copper) { 1318 if (adapter->hw.mac.type == e1000_i354) 1319 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1320 else 1321 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1322 } 1323 } 1324 1325 /********************************************************************* 1326 * 1327 * Fast Legacy/MSI Combined Interrupt Service routine 1328 * 1329 *********************************************************************/ 1330 int 1331 em_intr(void *arg) 1332 { 1333 struct adapter *adapter = arg; 1334 if_ctx_t ctx = adapter->ctx; 1335 u32 reg_icr; 1336 1337 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1338 1339 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1340 goto skip_stray; 1341 /* Hot eject? */ 1342 if (reg_icr == 0xffffffff) 1343 return FILTER_STRAY; 1344 1345 /* Definitely not our interrupt. */ 1346 if (reg_icr == 0x0) 1347 return FILTER_STRAY; 1348 1349 /* 1350 * Starting with the 82571 chip, bit 31 should be used to 1351 * determine whether the interrupt belongs to us. 1352 */ 1353 if (adapter->hw.mac.type >= e1000_82571 && 1354 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1355 return FILTER_STRAY; 1356 1357 skip_stray: 1358 /* Link status change */ 1359 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1360 adapter->hw.mac.get_link_status = 1; 1361 iflib_admin_intr_deferred(ctx); 1362 } 1363 1364 if (reg_icr & E1000_ICR_RXO) 1365 adapter->rx_overruns++; 1366 1367 return (FILTER_SCHEDULE_THREAD); 1368 } 1369 1370 static void 1371 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1372 { 1373 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1374 } 1375 1376 static void 1377 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1378 { 1379 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1380 } 1381 1382 static void 1383 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1384 { 1385 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1386 } 1387 1388 static void 1389 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1390 { 1391 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1392 } 1393 1394 static int 1395 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1396 { 1397 struct adapter *adapter = iflib_get_softc(ctx); 1398 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1399 1400 if (adapter->hw.mac.type >= igb_mac_min) 1401 igb_rx_enable_queue(adapter, rxq); 1402 else 1403 em_rx_enable_queue(adapter, rxq); 1404 return (0); 1405 } 1406 1407 static int 1408 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1409 { 1410 struct adapter *adapter = iflib_get_softc(ctx); 1411 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1412 1413 if (adapter->hw.mac.type >= igb_mac_min) 1414 igb_tx_enable_queue(adapter, txq); 1415 else 1416 em_tx_enable_queue(adapter, txq); 1417 return (0); 1418 } 1419 1420 /********************************************************************* 1421 * 1422 * MSIX RX Interrupt Service routine 1423 * 1424 **********************************************************************/ 1425 static int 1426 em_msix_que(void *arg) 1427 { 1428 struct em_rx_queue *que = arg; 1429 1430 ++que->irqs; 1431 1432 return (FILTER_SCHEDULE_THREAD); 1433 } 1434 1435 /********************************************************************* 1436 * 1437 * MSIX Link Fast Interrupt Service routine 1438 * 1439 **********************************************************************/ 1440 static int 1441 em_msix_link(void *arg) 1442 { 1443 struct adapter *adapter = arg; 1444 u32 reg_icr; 1445 1446 ++adapter->link_irq; 1447 MPASS(adapter->hw.back != NULL); 1448 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1449 1450 if (reg_icr & E1000_ICR_RXO) 1451 adapter->rx_overruns++; 1452 1453 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1454 em_handle_link(adapter->ctx); 1455 } else { 1456 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1457 EM_MSIX_LINK | E1000_IMS_LSC); 1458 if (adapter->hw.mac.type >= igb_mac_min) 1459 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1460 } 1461 1462 /* 1463 * Because we must read the ICR for this interrupt 1464 * it may clear other causes using autoclear, for 1465 * this reason we simply create a soft interrupt 1466 * for all these vectors. 1467 */ 1468 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1469 E1000_WRITE_REG(&adapter->hw, 1470 E1000_ICS, adapter->ims); 1471 } 1472 1473 return (FILTER_HANDLED); 1474 } 1475 1476 static void 1477 em_handle_link(void *context) 1478 { 1479 if_ctx_t ctx = context; 1480 struct adapter *adapter = iflib_get_softc(ctx); 1481 1482 adapter->hw.mac.get_link_status = 1; 1483 iflib_admin_intr_deferred(ctx); 1484 } 1485 1486 1487 /********************************************************************* 1488 * 1489 * Media Ioctl callback 1490 * 1491 * This routine is called whenever the user queries the status of 1492 * the interface using ifconfig. 1493 * 1494 **********************************************************************/ 1495 static void 1496 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1497 { 1498 struct adapter *adapter = iflib_get_softc(ctx); 1499 u_char fiber_type = IFM_1000_SX; 1500 1501 INIT_DEBUGOUT("em_if_media_status: begin"); 1502 1503 iflib_admin_intr_deferred(ctx); 1504 1505 ifmr->ifm_status = IFM_AVALID; 1506 ifmr->ifm_active = IFM_ETHER; 1507 1508 if (!adapter->link_active) { 1509 return; 1510 } 1511 1512 ifmr->ifm_status |= IFM_ACTIVE; 1513 1514 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1515 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1516 if (adapter->hw.mac.type == e1000_82545) 1517 fiber_type = IFM_1000_LX; 1518 ifmr->ifm_active |= fiber_type | IFM_FDX; 1519 } else { 1520 switch (adapter->link_speed) { 1521 case 10: 1522 ifmr->ifm_active |= IFM_10_T; 1523 break; 1524 case 100: 1525 ifmr->ifm_active |= IFM_100_TX; 1526 break; 1527 case 1000: 1528 ifmr->ifm_active |= IFM_1000_T; 1529 break; 1530 } 1531 if (adapter->link_duplex == FULL_DUPLEX) 1532 ifmr->ifm_active |= IFM_FDX; 1533 else 1534 ifmr->ifm_active |= IFM_HDX; 1535 } 1536 } 1537 1538 /********************************************************************* 1539 * 1540 * Media Ioctl callback 1541 * 1542 * This routine is called when the user changes speed/duplex using 1543 * media/mediopt option with ifconfig. 1544 * 1545 **********************************************************************/ 1546 static int 1547 em_if_media_change(if_ctx_t ctx) 1548 { 1549 struct adapter *adapter = iflib_get_softc(ctx); 1550 struct ifmedia *ifm = iflib_get_media(ctx); 1551 1552 INIT_DEBUGOUT("em_if_media_change: begin"); 1553 1554 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1555 return (EINVAL); 1556 1557 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1558 case IFM_AUTO: 1559 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1560 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1561 break; 1562 case IFM_1000_LX: 1563 case IFM_1000_SX: 1564 case IFM_1000_T: 1565 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1566 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1567 break; 1568 case IFM_100_TX: 1569 adapter->hw.mac.autoneg = FALSE; 1570 adapter->hw.phy.autoneg_advertised = 0; 1571 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1572 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1573 else 1574 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1575 break; 1576 case IFM_10_T: 1577 adapter->hw.mac.autoneg = FALSE; 1578 adapter->hw.phy.autoneg_advertised = 0; 1579 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1580 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1581 else 1582 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1583 break; 1584 default: 1585 device_printf(adapter->dev, "Unsupported media type\n"); 1586 } 1587 1588 em_if_init(ctx); 1589 1590 return (0); 1591 } 1592 1593 static int 1594 em_if_set_promisc(if_ctx_t ctx, int flags) 1595 { 1596 struct adapter *adapter = iflib_get_softc(ctx); 1597 u32 reg_rctl; 1598 1599 em_disable_promisc(ctx); 1600 1601 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1602 1603 if (flags & IFF_PROMISC) { 1604 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1605 /* Turn this on if you want to see bad packets */ 1606 if (em_debug_sbp) 1607 reg_rctl |= E1000_RCTL_SBP; 1608 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1609 } else if (flags & IFF_ALLMULTI) { 1610 reg_rctl |= E1000_RCTL_MPE; 1611 reg_rctl &= ~E1000_RCTL_UPE; 1612 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1613 } 1614 return (0); 1615 } 1616 1617 static void 1618 em_disable_promisc(if_ctx_t ctx) 1619 { 1620 struct adapter *adapter = iflib_get_softc(ctx); 1621 struct ifnet *ifp = iflib_get_ifp(ctx); 1622 u32 reg_rctl; 1623 int mcnt = 0; 1624 1625 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1626 reg_rctl &= (~E1000_RCTL_UPE); 1627 if (if_getflags(ifp) & IFF_ALLMULTI) 1628 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1629 else 1630 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1631 /* Don't disable if in MAX groups */ 1632 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1633 reg_rctl &= (~E1000_RCTL_MPE); 1634 reg_rctl &= (~E1000_RCTL_SBP); 1635 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1636 } 1637 1638 1639 /********************************************************************* 1640 * Multicast Update 1641 * 1642 * This routine is called whenever multicast address list is updated. 1643 * 1644 **********************************************************************/ 1645 1646 static void 1647 em_if_multi_set(if_ctx_t ctx) 1648 { 1649 struct adapter *adapter = iflib_get_softc(ctx); 1650 struct ifnet *ifp = iflib_get_ifp(ctx); 1651 u32 reg_rctl = 0; 1652 u8 *mta; /* Multicast array memory */ 1653 int mcnt = 0; 1654 1655 IOCTL_DEBUGOUT("em_set_multi: begin"); 1656 1657 mta = adapter->mta; 1658 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1659 1660 if (adapter->hw.mac.type == e1000_82542 && 1661 adapter->hw.revision_id == E1000_REVISION_2) { 1662 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1663 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1664 e1000_pci_clear_mwi(&adapter->hw); 1665 reg_rctl |= E1000_RCTL_RST; 1666 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1667 msec_delay(5); 1668 } 1669 1670 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1671 1672 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1673 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1674 reg_rctl |= E1000_RCTL_MPE; 1675 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1676 } else 1677 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1678 1679 if (adapter->hw.mac.type == e1000_82542 && 1680 adapter->hw.revision_id == E1000_REVISION_2) { 1681 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1682 reg_rctl &= ~E1000_RCTL_RST; 1683 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1684 msec_delay(5); 1685 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1686 e1000_pci_set_mwi(&adapter->hw); 1687 } 1688 } 1689 1690 1691 /********************************************************************* 1692 * Timer routine 1693 * 1694 * This routine checks for link status and updates statistics. 1695 * 1696 **********************************************************************/ 1697 1698 static void 1699 em_if_timer(if_ctx_t ctx, uint16_t qid) 1700 { 1701 struct adapter *adapter = iflib_get_softc(ctx); 1702 struct em_rx_queue *que; 1703 int i; 1704 int trigger = 0; 1705 1706 if (qid != 0) 1707 return; 1708 1709 iflib_admin_intr_deferred(ctx); 1710 1711 /* Mask to use in the irq trigger */ 1712 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1713 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1714 trigger |= que->eims; 1715 } else { 1716 trigger = E1000_ICS_RXDMT0; 1717 } 1718 } 1719 1720 1721 static void 1722 em_if_update_admin_status(if_ctx_t ctx) 1723 { 1724 struct adapter *adapter = iflib_get_softc(ctx); 1725 struct e1000_hw *hw = &adapter->hw; 1726 device_t dev = iflib_get_dev(ctx); 1727 u32 link_check, thstat, ctrl; 1728 1729 link_check = thstat = ctrl = 0; 1730 /* Get the cached link value or read phy for real */ 1731 switch (hw->phy.media_type) { 1732 case e1000_media_type_copper: 1733 if (hw->mac.get_link_status) { 1734 if (hw->mac.type == e1000_pch_spt) 1735 msec_delay(50); 1736 /* Do the work to read phy */ 1737 e1000_check_for_link(hw); 1738 link_check = !hw->mac.get_link_status; 1739 if (link_check) /* ESB2 fix */ 1740 e1000_cfg_on_link_up(hw); 1741 } else { 1742 link_check = TRUE; 1743 } 1744 break; 1745 case e1000_media_type_fiber: 1746 e1000_check_for_link(hw); 1747 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1748 E1000_STATUS_LU); 1749 break; 1750 case e1000_media_type_internal_serdes: 1751 e1000_check_for_link(hw); 1752 link_check = adapter->hw.mac.serdes_has_link; 1753 break; 1754 /* VF device is type_unknown */ 1755 case e1000_media_type_unknown: 1756 e1000_check_for_link(hw); 1757 link_check = !hw->mac.get_link_status; 1758 /* FALLTHROUGH */ 1759 default: 1760 break; 1761 } 1762 1763 /* Check for thermal downshift or shutdown */ 1764 if (hw->mac.type == e1000_i350) { 1765 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1766 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1767 } 1768 1769 /* Now check for a transition */ 1770 if (link_check && (adapter->link_active == 0)) { 1771 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1772 &adapter->link_duplex); 1773 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1774 if ((adapter->link_speed != SPEED_1000) && 1775 ((hw->mac.type == e1000_82571) || 1776 (hw->mac.type == e1000_82572))) { 1777 int tarc0; 1778 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1779 tarc0 &= ~TARC_SPEED_MODE_BIT; 1780 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1781 } 1782 if (bootverbose) 1783 device_printf(dev, "Link is up %d Mbps %s\n", 1784 adapter->link_speed, 1785 ((adapter->link_duplex == FULL_DUPLEX) ? 1786 "Full Duplex" : "Half Duplex")); 1787 adapter->link_active = 1; 1788 adapter->smartspeed = 0; 1789 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1790 E1000_CTRL_EXT_LINK_MODE_GMII && 1791 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1792 device_printf(dev, "Link: thermal downshift\n"); 1793 /* Delay Link Up for Phy update */ 1794 if (((hw->mac.type == e1000_i210) || 1795 (hw->mac.type == e1000_i211)) && 1796 (hw->phy.id == I210_I_PHY_ID)) 1797 msec_delay(I210_LINK_DELAY); 1798 /* Reset if the media type changed. */ 1799 if ((hw->dev_spec._82575.media_changed) && 1800 (adapter->hw.mac.type >= igb_mac_min)) { 1801 hw->dev_spec._82575.media_changed = false; 1802 adapter->flags |= IGB_MEDIA_RESET; 1803 em_reset(ctx); 1804 } 1805 iflib_link_state_change(ctx, LINK_STATE_UP, 1806 IF_Mbps(adapter->link_speed)); 1807 } else if (!link_check && (adapter->link_active == 1)) { 1808 adapter->link_speed = 0; 1809 adapter->link_duplex = 0; 1810 adapter->link_active = 0; 1811 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1812 } 1813 em_update_stats_counters(adapter); 1814 1815 /* Reset LAA into RAR[0] on 82571 */ 1816 if ((adapter->hw.mac.type == e1000_82571) && 1817 e1000_get_laa_state_82571(&adapter->hw)) 1818 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1819 1820 if (adapter->hw.mac.type < em_mac_min) 1821 lem_smartspeed(adapter); 1822 1823 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1824 } 1825 1826 /********************************************************************* 1827 * 1828 * This routine disables all traffic on the adapter by issuing a 1829 * global reset on the MAC and deallocates TX/RX buffers. 1830 * 1831 * This routine should always be called with BOTH the CORE 1832 * and TX locks. 1833 **********************************************************************/ 1834 1835 static void 1836 em_if_stop(if_ctx_t ctx) 1837 { 1838 struct adapter *adapter = iflib_get_softc(ctx); 1839 1840 INIT_DEBUGOUT("em_stop: begin"); 1841 1842 e1000_reset_hw(&adapter->hw); 1843 if (adapter->hw.mac.type >= e1000_82544) 1844 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1845 1846 e1000_led_off(&adapter->hw); 1847 e1000_cleanup_led(&adapter->hw); 1848 } 1849 1850 1851 /********************************************************************* 1852 * 1853 * Determine hardware revision. 1854 * 1855 **********************************************************************/ 1856 static void 1857 em_identify_hardware(if_ctx_t ctx) 1858 { 1859 device_t dev = iflib_get_dev(ctx); 1860 struct adapter *adapter = iflib_get_softc(ctx); 1861 1862 /* Make sure our PCI config space has the necessary stuff set */ 1863 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1864 1865 /* Save off the information about this board */ 1866 adapter->hw.vendor_id = pci_get_vendor(dev); 1867 adapter->hw.device_id = pci_get_device(dev); 1868 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1869 adapter->hw.subsystem_vendor_id = 1870 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1871 adapter->hw.subsystem_device_id = 1872 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1873 1874 /* Do Shared Code Init and Setup */ 1875 if (e1000_set_mac_type(&adapter->hw)) { 1876 device_printf(dev, "Setup init failure\n"); 1877 return; 1878 } 1879 } 1880 1881 static int 1882 em_allocate_pci_resources(if_ctx_t ctx) 1883 { 1884 struct adapter *adapter = iflib_get_softc(ctx); 1885 device_t dev = iflib_get_dev(ctx); 1886 int rid, val; 1887 1888 rid = PCIR_BAR(0); 1889 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1890 &rid, RF_ACTIVE); 1891 if (adapter->memory == NULL) { 1892 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1893 return (ENXIO); 1894 } 1895 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1896 adapter->osdep.mem_bus_space_handle = 1897 rman_get_bushandle(adapter->memory); 1898 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1899 1900 /* Only older adapters use IO mapping */ 1901 if (adapter->hw.mac.type < em_mac_min && 1902 adapter->hw.mac.type > e1000_82543) { 1903 /* Figure our where our IO BAR is ? */ 1904 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1905 val = pci_read_config(dev, rid, 4); 1906 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1907 adapter->io_rid = rid; 1908 break; 1909 } 1910 rid += 4; 1911 /* check for 64bit BAR */ 1912 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1913 rid += 4; 1914 } 1915 if (rid >= PCIR_CIS) { 1916 device_printf(dev, "Unable to locate IO BAR\n"); 1917 return (ENXIO); 1918 } 1919 adapter->ioport = bus_alloc_resource_any(dev, 1920 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1921 if (adapter->ioport == NULL) { 1922 device_printf(dev, "Unable to allocate bus resource: " 1923 "ioport\n"); 1924 return (ENXIO); 1925 } 1926 adapter->hw.io_base = 0; 1927 adapter->osdep.io_bus_space_tag = 1928 rman_get_bustag(adapter->ioport); 1929 adapter->osdep.io_bus_space_handle = 1930 rman_get_bushandle(adapter->ioport); 1931 } 1932 1933 adapter->hw.back = &adapter->osdep; 1934 1935 return (0); 1936 } 1937 1938 /********************************************************************* 1939 * 1940 * Setup the MSIX Interrupt handlers 1941 * 1942 **********************************************************************/ 1943 static int 1944 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1945 { 1946 struct adapter *adapter = iflib_get_softc(ctx); 1947 struct em_rx_queue *rx_que = adapter->rx_queues; 1948 struct em_tx_queue *tx_que = adapter->tx_queues; 1949 int error, rid, i, vector = 0, rx_vectors; 1950 char buf[16]; 1951 1952 /* First set up ring resources */ 1953 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1954 rid = vector + 1; 1955 snprintf(buf, sizeof(buf), "rxq%d", i); 1956 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1957 if (error) { 1958 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1959 adapter->rx_num_queues = i + 1; 1960 goto fail; 1961 } 1962 1963 rx_que->msix = vector; 1964 1965 /* 1966 * Set the bit to enable interrupt 1967 * in E1000_IMS -- bits 20 and 21 1968 * are for RX0 and RX1, note this has 1969 * NOTHING to do with the MSIX vector 1970 */ 1971 if (adapter->hw.mac.type == e1000_82574) { 1972 rx_que->eims = 1 << (20 + i); 1973 adapter->ims |= rx_que->eims; 1974 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1975 } else if (adapter->hw.mac.type == e1000_82575) 1976 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1977 else 1978 rx_que->eims = 1 << vector; 1979 } 1980 rx_vectors = vector; 1981 1982 vector = 0; 1983 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1984 snprintf(buf, sizeof(buf), "txq%d", i); 1985 tx_que = &adapter->tx_queues[i]; 1986 iflib_softirq_alloc_generic(ctx, 1987 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1988 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1989 1990 tx_que->msix = (vector % adapter->tx_num_queues); 1991 1992 /* 1993 * Set the bit to enable interrupt 1994 * in E1000_IMS -- bits 22 and 23 1995 * are for TX0 and TX1, note this has 1996 * NOTHING to do with the MSIX vector 1997 */ 1998 if (adapter->hw.mac.type == e1000_82574) { 1999 tx_que->eims = 1 << (22 + i); 2000 adapter->ims |= tx_que->eims; 2001 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2002 } else if (adapter->hw.mac.type == e1000_82575) { 2003 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 2004 } else { 2005 tx_que->eims = 1 << (i % adapter->tx_num_queues); 2006 } 2007 } 2008 2009 /* Link interrupt */ 2010 rid = rx_vectors + 1; 2011 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2012 2013 if (error) { 2014 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2015 goto fail; 2016 } 2017 adapter->linkvec = rx_vectors; 2018 if (adapter->hw.mac.type < igb_mac_min) { 2019 adapter->ivars |= (8 | rx_vectors) << 16; 2020 adapter->ivars |= 0x80000000; 2021 } 2022 return (0); 2023 fail: 2024 iflib_irq_free(ctx, &adapter->irq); 2025 rx_que = adapter->rx_queues; 2026 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2027 iflib_irq_free(ctx, &rx_que->que_irq); 2028 return (error); 2029 } 2030 2031 static void 2032 igb_configure_queues(struct adapter *adapter) 2033 { 2034 struct e1000_hw *hw = &adapter->hw; 2035 struct em_rx_queue *rx_que; 2036 struct em_tx_queue *tx_que; 2037 u32 tmp, ivar = 0, newitr = 0; 2038 2039 /* First turn on RSS capability */ 2040 if (adapter->hw.mac.type != e1000_82575) 2041 E1000_WRITE_REG(hw, E1000_GPIE, 2042 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2043 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2044 2045 /* Turn on MSIX */ 2046 switch (adapter->hw.mac.type) { 2047 case e1000_82580: 2048 case e1000_i350: 2049 case e1000_i354: 2050 case e1000_i210: 2051 case e1000_i211: 2052 case e1000_vfadapt: 2053 case e1000_vfadapt_i350: 2054 /* RX entries */ 2055 for (int i = 0; i < adapter->rx_num_queues; i++) { 2056 u32 index = i >> 1; 2057 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2058 rx_que = &adapter->rx_queues[i]; 2059 if (i & 1) { 2060 ivar &= 0xFF00FFFF; 2061 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2062 } else { 2063 ivar &= 0xFFFFFF00; 2064 ivar |= rx_que->msix | E1000_IVAR_VALID; 2065 } 2066 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2067 } 2068 /* TX entries */ 2069 for (int i = 0; i < adapter->tx_num_queues; i++) { 2070 u32 index = i >> 1; 2071 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2072 tx_que = &adapter->tx_queues[i]; 2073 if (i & 1) { 2074 ivar &= 0x00FFFFFF; 2075 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2076 } else { 2077 ivar &= 0xFFFF00FF; 2078 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2079 } 2080 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2081 adapter->que_mask |= tx_que->eims; 2082 } 2083 2084 /* And for the link interrupt */ 2085 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2086 adapter->link_mask = 1 << adapter->linkvec; 2087 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2088 break; 2089 case e1000_82576: 2090 /* RX entries */ 2091 for (int i = 0; i < adapter->rx_num_queues; i++) { 2092 u32 index = i & 0x7; /* Each IVAR has two entries */ 2093 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2094 rx_que = &adapter->rx_queues[i]; 2095 if (i < 8) { 2096 ivar &= 0xFFFFFF00; 2097 ivar |= rx_que->msix | E1000_IVAR_VALID; 2098 } else { 2099 ivar &= 0xFF00FFFF; 2100 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2101 } 2102 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2103 adapter->que_mask |= rx_que->eims; 2104 } 2105 /* TX entries */ 2106 for (int i = 0; i < adapter->tx_num_queues; i++) { 2107 u32 index = i & 0x7; /* Each IVAR has two entries */ 2108 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2109 tx_que = &adapter->tx_queues[i]; 2110 if (i < 8) { 2111 ivar &= 0xFFFF00FF; 2112 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2113 } else { 2114 ivar &= 0x00FFFFFF; 2115 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2116 } 2117 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2118 adapter->que_mask |= tx_que->eims; 2119 } 2120 2121 /* And for the link interrupt */ 2122 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2123 adapter->link_mask = 1 << adapter->linkvec; 2124 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2125 break; 2126 2127 case e1000_82575: 2128 /* enable MSI-X support*/ 2129 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2130 tmp |= E1000_CTRL_EXT_PBA_CLR; 2131 /* Auto-Mask interrupts upon ICR read. */ 2132 tmp |= E1000_CTRL_EXT_EIAME; 2133 tmp |= E1000_CTRL_EXT_IRCA; 2134 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2135 2136 /* Queues */ 2137 for (int i = 0; i < adapter->rx_num_queues; i++) { 2138 rx_que = &adapter->rx_queues[i]; 2139 tmp = E1000_EICR_RX_QUEUE0 << i; 2140 tmp |= E1000_EICR_TX_QUEUE0 << i; 2141 rx_que->eims = tmp; 2142 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2143 i, rx_que->eims); 2144 adapter->que_mask |= rx_que->eims; 2145 } 2146 2147 /* Link */ 2148 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2149 E1000_EIMS_OTHER); 2150 adapter->link_mask |= E1000_EIMS_OTHER; 2151 default: 2152 break; 2153 } 2154 2155 /* Set the starting interrupt rate */ 2156 if (em_max_interrupt_rate > 0) 2157 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2158 2159 if (hw->mac.type == e1000_82575) 2160 newitr |= newitr << 16; 2161 else 2162 newitr |= E1000_EITR_CNT_IGNR; 2163 2164 for (int i = 0; i < adapter->rx_num_queues; i++) { 2165 rx_que = &adapter->rx_queues[i]; 2166 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2167 } 2168 2169 return; 2170 } 2171 2172 static void 2173 em_free_pci_resources(if_ctx_t ctx) 2174 { 2175 struct adapter *adapter = iflib_get_softc(ctx); 2176 struct em_rx_queue *que = adapter->rx_queues; 2177 device_t dev = iflib_get_dev(ctx); 2178 2179 /* Release all msix queue resources */ 2180 if (adapter->intr_type == IFLIB_INTR_MSIX) 2181 iflib_irq_free(ctx, &adapter->irq); 2182 2183 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2184 iflib_irq_free(ctx, &que->que_irq); 2185 } 2186 2187 /* First release all the interrupt resources */ 2188 if (adapter->memory != NULL) { 2189 bus_release_resource(dev, SYS_RES_MEMORY, 2190 PCIR_BAR(0), adapter->memory); 2191 adapter->memory = NULL; 2192 } 2193 2194 if (adapter->flash != NULL) { 2195 bus_release_resource(dev, SYS_RES_MEMORY, 2196 EM_FLASH, adapter->flash); 2197 adapter->flash = NULL; 2198 } 2199 if (adapter->ioport != NULL) 2200 bus_release_resource(dev, SYS_RES_IOPORT, 2201 adapter->io_rid, adapter->ioport); 2202 } 2203 2204 /* Setup MSI or MSI/X */ 2205 static int 2206 em_setup_msix(if_ctx_t ctx) 2207 { 2208 struct adapter *adapter = iflib_get_softc(ctx); 2209 2210 if (adapter->hw.mac.type == e1000_82574) { 2211 em_enable_vectors_82574(ctx); 2212 } 2213 return (0); 2214 } 2215 2216 /********************************************************************* 2217 * 2218 * Initialize the hardware to a configuration 2219 * as specified by the adapter structure. 2220 * 2221 **********************************************************************/ 2222 2223 static void 2224 lem_smartspeed(struct adapter *adapter) 2225 { 2226 u16 phy_tmp; 2227 2228 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2229 adapter->hw.mac.autoneg == 0 || 2230 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2231 return; 2232 2233 if (adapter->smartspeed == 0) { 2234 /* If Master/Slave config fault is asserted twice, 2235 * we assume back-to-back */ 2236 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2237 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2238 return; 2239 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2240 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2241 e1000_read_phy_reg(&adapter->hw, 2242 PHY_1000T_CTRL, &phy_tmp); 2243 if(phy_tmp & CR_1000T_MS_ENABLE) { 2244 phy_tmp &= ~CR_1000T_MS_ENABLE; 2245 e1000_write_phy_reg(&adapter->hw, 2246 PHY_1000T_CTRL, phy_tmp); 2247 adapter->smartspeed++; 2248 if(adapter->hw.mac.autoneg && 2249 !e1000_copper_link_autoneg(&adapter->hw) && 2250 !e1000_read_phy_reg(&adapter->hw, 2251 PHY_CONTROL, &phy_tmp)) { 2252 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2253 MII_CR_RESTART_AUTO_NEG); 2254 e1000_write_phy_reg(&adapter->hw, 2255 PHY_CONTROL, phy_tmp); 2256 } 2257 } 2258 } 2259 return; 2260 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2261 /* If still no link, perhaps using 2/3 pair cable */ 2262 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2263 phy_tmp |= CR_1000T_MS_ENABLE; 2264 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2265 if(adapter->hw.mac.autoneg && 2266 !e1000_copper_link_autoneg(&adapter->hw) && 2267 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2268 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2269 MII_CR_RESTART_AUTO_NEG); 2270 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2271 } 2272 } 2273 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2274 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2275 adapter->smartspeed = 0; 2276 } 2277 2278 /********************************************************************* 2279 * 2280 * Initialize the DMA Coalescing feature 2281 * 2282 **********************************************************************/ 2283 static void 2284 igb_init_dmac(struct adapter *adapter, u32 pba) 2285 { 2286 device_t dev = adapter->dev; 2287 struct e1000_hw *hw = &adapter->hw; 2288 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2289 u16 hwm; 2290 u16 max_frame_size; 2291 2292 if (hw->mac.type == e1000_i211) 2293 return; 2294 2295 max_frame_size = adapter->shared->isc_max_frame_size; 2296 if (hw->mac.type > e1000_82580) { 2297 2298 if (adapter->dmac == 0) { /* Disabling it */ 2299 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2300 return; 2301 } else 2302 device_printf(dev, "DMA Coalescing enabled\n"); 2303 2304 /* Set starting threshold */ 2305 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2306 2307 hwm = 64 * pba - max_frame_size / 16; 2308 if (hwm < 64 * (pba - 6)) 2309 hwm = 64 * (pba - 6); 2310 reg = E1000_READ_REG(hw, E1000_FCRTC); 2311 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2312 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2313 & E1000_FCRTC_RTH_COAL_MASK); 2314 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2315 2316 2317 dmac = pba - max_frame_size / 512; 2318 if (dmac < pba - 10) 2319 dmac = pba - 10; 2320 reg = E1000_READ_REG(hw, E1000_DMACR); 2321 reg &= ~E1000_DMACR_DMACTHR_MASK; 2322 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2323 & E1000_DMACR_DMACTHR_MASK); 2324 2325 /* transition to L0x or L1 if available..*/ 2326 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2327 2328 /* Check if status is 2.5Gb backplane connection 2329 * before configuration of watchdog timer, which is 2330 * in msec values in 12.8usec intervals 2331 * watchdog timer= msec values in 32usec intervals 2332 * for non 2.5Gb connection 2333 */ 2334 if (hw->mac.type == e1000_i354) { 2335 int status = E1000_READ_REG(hw, E1000_STATUS); 2336 if ((status & E1000_STATUS_2P5_SKU) && 2337 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2338 reg |= ((adapter->dmac * 5) >> 6); 2339 else 2340 reg |= (adapter->dmac >> 5); 2341 } else { 2342 reg |= (adapter->dmac >> 5); 2343 } 2344 2345 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2346 2347 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2348 2349 /* Set the interval before transition */ 2350 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2351 if (hw->mac.type == e1000_i350) 2352 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2353 /* 2354 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2355 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2356 */ 2357 if (hw->mac.type == e1000_i354) { 2358 int status = E1000_READ_REG(hw, E1000_STATUS); 2359 if ((status & E1000_STATUS_2P5_SKU) && 2360 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2361 reg |= 0xA; 2362 else 2363 reg |= 0x4; 2364 } else { 2365 reg |= 0x4; 2366 } 2367 2368 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2369 2370 /* free space in tx packet buffer to wake from DMA coal */ 2371 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2372 (2 * max_frame_size)) >> 6); 2373 2374 /* make low power state decision controlled by DMA coal */ 2375 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2376 reg &= ~E1000_PCIEMISC_LX_DECISION; 2377 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2378 2379 } else if (hw->mac.type == e1000_82580) { 2380 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2381 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2382 reg & ~E1000_PCIEMISC_LX_DECISION); 2383 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2384 } 2385 } 2386 2387 static void 2388 em_reset(if_ctx_t ctx) 2389 { 2390 device_t dev = iflib_get_dev(ctx); 2391 struct adapter *adapter = iflib_get_softc(ctx); 2392 struct ifnet *ifp = iflib_get_ifp(ctx); 2393 struct e1000_hw *hw = &adapter->hw; 2394 u16 rx_buffer_size; 2395 u32 pba; 2396 2397 INIT_DEBUGOUT("em_reset: begin"); 2398 /* Let the firmware know the OS is in control */ 2399 em_get_hw_control(adapter); 2400 2401 /* Set up smart power down as default off on newer adapters. */ 2402 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2403 hw->mac.type == e1000_82572)) { 2404 u16 phy_tmp = 0; 2405 2406 /* Speed up time to link by disabling smart power down. */ 2407 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2408 phy_tmp &= ~IGP02E1000_PM_SPD; 2409 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2410 } 2411 2412 /* 2413 * Packet Buffer Allocation (PBA) 2414 * Writing PBA sets the receive portion of the buffer 2415 * the remainder is used for the transmit buffer. 2416 */ 2417 switch (hw->mac.type) { 2418 /* Total Packet Buffer on these is 48K */ 2419 case e1000_82571: 2420 case e1000_82572: 2421 case e1000_80003es2lan: 2422 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2423 break; 2424 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2425 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2426 break; 2427 case e1000_82574: 2428 case e1000_82583: 2429 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2430 break; 2431 case e1000_ich8lan: 2432 pba = E1000_PBA_8K; 2433 break; 2434 case e1000_ich9lan: 2435 case e1000_ich10lan: 2436 /* Boost Receive side for jumbo frames */ 2437 if (adapter->hw.mac.max_frame_size > 4096) 2438 pba = E1000_PBA_14K; 2439 else 2440 pba = E1000_PBA_10K; 2441 break; 2442 case e1000_pchlan: 2443 case e1000_pch2lan: 2444 case e1000_pch_lpt: 2445 case e1000_pch_spt: 2446 case e1000_pch_cnp: 2447 pba = E1000_PBA_26K; 2448 break; 2449 case e1000_82575: 2450 pba = E1000_PBA_32K; 2451 break; 2452 case e1000_82576: 2453 case e1000_vfadapt: 2454 pba = E1000_READ_REG(hw, E1000_RXPBS); 2455 pba &= E1000_RXPBS_SIZE_MASK_82576; 2456 break; 2457 case e1000_82580: 2458 case e1000_i350: 2459 case e1000_i354: 2460 case e1000_vfadapt_i350: 2461 pba = E1000_READ_REG(hw, E1000_RXPBS); 2462 pba = e1000_rxpbs_adjust_82580(pba); 2463 break; 2464 case e1000_i210: 2465 case e1000_i211: 2466 pba = E1000_PBA_34K; 2467 break; 2468 default: 2469 if (adapter->hw.mac.max_frame_size > 8192) 2470 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2471 else 2472 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2473 } 2474 2475 /* Special needs in case of Jumbo frames */ 2476 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2477 u32 tx_space, min_tx, min_rx; 2478 pba = E1000_READ_REG(hw, E1000_PBA); 2479 tx_space = pba >> 16; 2480 pba &= 0xffff; 2481 min_tx = (adapter->hw.mac.max_frame_size + 2482 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2483 min_tx = roundup2(min_tx, 1024); 2484 min_tx >>= 10; 2485 min_rx = adapter->hw.mac.max_frame_size; 2486 min_rx = roundup2(min_rx, 1024); 2487 min_rx >>= 10; 2488 if (tx_space < min_tx && 2489 ((min_tx - tx_space) < pba)) { 2490 pba = pba - (min_tx - tx_space); 2491 /* 2492 * if short on rx space, rx wins 2493 * and must trump tx adjustment 2494 */ 2495 if (pba < min_rx) 2496 pba = min_rx; 2497 } 2498 E1000_WRITE_REG(hw, E1000_PBA, pba); 2499 } 2500 2501 if (hw->mac.type < igb_mac_min) 2502 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2503 2504 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2505 2506 /* 2507 * These parameters control the automatic generation (Tx) and 2508 * response (Rx) to Ethernet PAUSE frames. 2509 * - High water mark should allow for at least two frames to be 2510 * received after sending an XOFF. 2511 * - Low water mark works best when it is very near the high water mark. 2512 * This allows the receiver to restart by sending XON when it has 2513 * drained a bit. Here we use an arbitrary value of 1500 which will 2514 * restart after one full frame is pulled from the buffer. There 2515 * could be several smaller frames in the buffer and if so they will 2516 * not trigger the XON until their total number reduces the buffer 2517 * by 1500. 2518 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2519 */ 2520 rx_buffer_size = (pba & 0xffff) << 10; 2521 hw->fc.high_water = rx_buffer_size - 2522 roundup2(adapter->hw.mac.max_frame_size, 1024); 2523 hw->fc.low_water = hw->fc.high_water - 1500; 2524 2525 if (adapter->fc) /* locally set flow control value? */ 2526 hw->fc.requested_mode = adapter->fc; 2527 else 2528 hw->fc.requested_mode = e1000_fc_full; 2529 2530 if (hw->mac.type == e1000_80003es2lan) 2531 hw->fc.pause_time = 0xFFFF; 2532 else 2533 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2534 2535 hw->fc.send_xon = TRUE; 2536 2537 /* Device specific overrides/settings */ 2538 switch (hw->mac.type) { 2539 case e1000_pchlan: 2540 /* Workaround: no TX flow ctrl for PCH */ 2541 hw->fc.requested_mode = e1000_fc_rx_pause; 2542 hw->fc.pause_time = 0xFFFF; /* override */ 2543 if (if_getmtu(ifp) > ETHERMTU) { 2544 hw->fc.high_water = 0x3500; 2545 hw->fc.low_water = 0x1500; 2546 } else { 2547 hw->fc.high_water = 0x5000; 2548 hw->fc.low_water = 0x3000; 2549 } 2550 hw->fc.refresh_time = 0x1000; 2551 break; 2552 case e1000_pch2lan: 2553 case e1000_pch_lpt: 2554 case e1000_pch_spt: 2555 case e1000_pch_cnp: 2556 hw->fc.high_water = 0x5C20; 2557 hw->fc.low_water = 0x5048; 2558 hw->fc.pause_time = 0x0650; 2559 hw->fc.refresh_time = 0x0400; 2560 /* Jumbos need adjusted PBA */ 2561 if (if_getmtu(ifp) > ETHERMTU) 2562 E1000_WRITE_REG(hw, E1000_PBA, 12); 2563 else 2564 E1000_WRITE_REG(hw, E1000_PBA, 26); 2565 break; 2566 case e1000_82575: 2567 case e1000_82576: 2568 /* 8-byte granularity */ 2569 hw->fc.low_water = hw->fc.high_water - 8; 2570 break; 2571 case e1000_82580: 2572 case e1000_i350: 2573 case e1000_i354: 2574 case e1000_i210: 2575 case e1000_i211: 2576 case e1000_vfadapt: 2577 case e1000_vfadapt_i350: 2578 /* 16-byte granularity */ 2579 hw->fc.low_water = hw->fc.high_water - 16; 2580 break; 2581 case e1000_ich9lan: 2582 case e1000_ich10lan: 2583 if (if_getmtu(ifp) > ETHERMTU) { 2584 hw->fc.high_water = 0x2800; 2585 hw->fc.low_water = hw->fc.high_water - 8; 2586 break; 2587 } 2588 /* FALLTHROUGH */ 2589 default: 2590 if (hw->mac.type == e1000_80003es2lan) 2591 hw->fc.pause_time = 0xFFFF; 2592 break; 2593 } 2594 2595 /* Issue a global reset */ 2596 e1000_reset_hw(hw); 2597 if (adapter->hw.mac.type >= igb_mac_min) { 2598 E1000_WRITE_REG(hw, E1000_WUC, 0); 2599 } else { 2600 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2601 em_disable_aspm(adapter); 2602 } 2603 if (adapter->flags & IGB_MEDIA_RESET) { 2604 e1000_setup_init_funcs(hw, TRUE); 2605 e1000_get_bus_info(hw); 2606 adapter->flags &= ~IGB_MEDIA_RESET; 2607 } 2608 /* and a re-init */ 2609 if (e1000_init_hw(hw) < 0) { 2610 device_printf(dev, "Hardware Initialization Failed\n"); 2611 return; 2612 } 2613 if (adapter->hw.mac.type >= igb_mac_min) 2614 igb_init_dmac(adapter, pba); 2615 2616 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2617 e1000_get_phy_info(hw); 2618 e1000_check_for_link(hw); 2619 } 2620 2621 #define RSSKEYLEN 10 2622 static void 2623 em_initialize_rss_mapping(struct adapter *adapter) 2624 { 2625 uint8_t rss_key[4 * RSSKEYLEN]; 2626 uint32_t reta = 0; 2627 struct e1000_hw *hw = &adapter->hw; 2628 int i; 2629 2630 /* 2631 * Configure RSS key 2632 */ 2633 arc4rand(rss_key, sizeof(rss_key), 0); 2634 for (i = 0; i < RSSKEYLEN; ++i) { 2635 uint32_t rssrk = 0; 2636 2637 rssrk = EM_RSSRK_VAL(rss_key, i); 2638 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2639 } 2640 2641 /* 2642 * Configure RSS redirect table in following fashion: 2643 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2644 */ 2645 for (i = 0; i < sizeof(reta); ++i) { 2646 uint32_t q; 2647 2648 q = (i % adapter->rx_num_queues) << 7; 2649 reta |= q << (8 * i); 2650 } 2651 2652 for (i = 0; i < 32; ++i) 2653 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2654 2655 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2656 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2657 E1000_MRQC_RSS_FIELD_IPV4 | 2658 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2659 E1000_MRQC_RSS_FIELD_IPV6_EX | 2660 E1000_MRQC_RSS_FIELD_IPV6); 2661 2662 } 2663 2664 static void 2665 igb_initialize_rss_mapping(struct adapter *adapter) 2666 { 2667 struct e1000_hw *hw = &adapter->hw; 2668 int i; 2669 int queue_id; 2670 u32 reta; 2671 u32 rss_key[10], mrqc, shift = 0; 2672 2673 /* XXX? */ 2674 if (adapter->hw.mac.type == e1000_82575) 2675 shift = 6; 2676 2677 /* 2678 * The redirection table controls which destination 2679 * queue each bucket redirects traffic to. 2680 * Each DWORD represents four queues, with the LSB 2681 * being the first queue in the DWORD. 2682 * 2683 * This just allocates buckets to queues using round-robin 2684 * allocation. 2685 * 2686 * NOTE: It Just Happens to line up with the default 2687 * RSS allocation method. 2688 */ 2689 2690 /* Warning FM follows */ 2691 reta = 0; 2692 for (i = 0; i < 128; i++) { 2693 #ifdef RSS 2694 queue_id = rss_get_indirection_to_bucket(i); 2695 /* 2696 * If we have more queues than buckets, we'll 2697 * end up mapping buckets to a subset of the 2698 * queues. 2699 * 2700 * If we have more buckets than queues, we'll 2701 * end up instead assigning multiple buckets 2702 * to queues. 2703 * 2704 * Both are suboptimal, but we need to handle 2705 * the case so we don't go out of bounds 2706 * indexing arrays and such. 2707 */ 2708 queue_id = queue_id % adapter->rx_num_queues; 2709 #else 2710 queue_id = (i % adapter->rx_num_queues); 2711 #endif 2712 /* Adjust if required */ 2713 queue_id = queue_id << shift; 2714 2715 /* 2716 * The low 8 bits are for hash value (n+0); 2717 * The next 8 bits are for hash value (n+1), etc. 2718 */ 2719 reta = reta >> 8; 2720 reta = reta | ( ((uint32_t) queue_id) << 24); 2721 if ((i & 3) == 3) { 2722 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2723 reta = 0; 2724 } 2725 } 2726 2727 /* Now fill in hash table */ 2728 2729 /* 2730 * MRQC: Multiple Receive Queues Command 2731 * Set queuing to RSS control, number depends on the device. 2732 */ 2733 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2734 2735 #ifdef RSS 2736 /* XXX ew typecasting */ 2737 rss_getkey((uint8_t *) &rss_key); 2738 #else 2739 arc4rand(&rss_key, sizeof(rss_key), 0); 2740 #endif 2741 for (i = 0; i < 10; i++) 2742 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2743 2744 /* 2745 * Configure the RSS fields to hash upon. 2746 */ 2747 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2748 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2749 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2750 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2751 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2752 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2753 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2754 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2755 2756 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2757 } 2758 2759 /********************************************************************* 2760 * 2761 * Setup networking device structure and register an interface. 2762 * 2763 **********************************************************************/ 2764 static int 2765 em_setup_interface(if_ctx_t ctx) 2766 { 2767 struct ifnet *ifp = iflib_get_ifp(ctx); 2768 struct adapter *adapter = iflib_get_softc(ctx); 2769 if_softc_ctx_t scctx = adapter->shared; 2770 2771 INIT_DEBUGOUT("em_setup_interface: begin"); 2772 2773 /* Single Queue */ 2774 if (adapter->tx_num_queues == 1) { 2775 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2776 if_setsendqready(ifp); 2777 } 2778 2779 /* 2780 * Specify the media types supported by this adapter and register 2781 * callbacks to update media and link information 2782 */ 2783 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2784 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2785 u_char fiber_type = IFM_1000_SX; /* default type */ 2786 2787 if (adapter->hw.mac.type == e1000_82545) 2788 fiber_type = IFM_1000_LX; 2789 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2790 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2791 } else { 2792 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2793 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2794 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2796 if (adapter->hw.phy.type != e1000_phy_ife) { 2797 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2798 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2799 } 2800 } 2801 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2802 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2803 return (0); 2804 } 2805 2806 static int 2807 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2808 { 2809 struct adapter *adapter = iflib_get_softc(ctx); 2810 if_softc_ctx_t scctx = adapter->shared; 2811 int error = E1000_SUCCESS; 2812 struct em_tx_queue *que; 2813 int i, j; 2814 2815 MPASS(adapter->tx_num_queues > 0); 2816 MPASS(adapter->tx_num_queues == ntxqsets); 2817 2818 /* First allocate the top level queue structs */ 2819 if (!(adapter->tx_queues = 2820 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2821 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2822 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2823 return(ENOMEM); 2824 } 2825 2826 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2827 /* Set up some basics */ 2828 2829 struct tx_ring *txr = &que->txr; 2830 txr->adapter = que->adapter = adapter; 2831 que->me = txr->me = i; 2832 2833 /* Allocate report status array */ 2834 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2835 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2836 error = ENOMEM; 2837 goto fail; 2838 } 2839 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2840 txr->tx_rsq[j] = QIDX_INVALID; 2841 /* get the virtual and physical address of the hardware queues */ 2842 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2843 txr->tx_paddr = paddrs[i*ntxqs]; 2844 } 2845 2846 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2847 return (0); 2848 fail: 2849 em_if_queues_free(ctx); 2850 return (error); 2851 } 2852 2853 static int 2854 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2855 { 2856 struct adapter *adapter = iflib_get_softc(ctx); 2857 int error = E1000_SUCCESS; 2858 struct em_rx_queue *que; 2859 int i; 2860 2861 MPASS(adapter->rx_num_queues > 0); 2862 MPASS(adapter->rx_num_queues == nrxqsets); 2863 2864 /* First allocate the top level queue structs */ 2865 if (!(adapter->rx_queues = 2866 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2867 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2868 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2869 error = ENOMEM; 2870 goto fail; 2871 } 2872 2873 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2874 /* Set up some basics */ 2875 struct rx_ring *rxr = &que->rxr; 2876 rxr->adapter = que->adapter = adapter; 2877 rxr->que = que; 2878 que->me = rxr->me = i; 2879 2880 /* get the virtual and physical address of the hardware queues */ 2881 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2882 rxr->rx_paddr = paddrs[i*nrxqs]; 2883 } 2884 2885 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2886 2887 return (0); 2888 fail: 2889 em_if_queues_free(ctx); 2890 return (error); 2891 } 2892 2893 static void 2894 em_if_queues_free(if_ctx_t ctx) 2895 { 2896 struct adapter *adapter = iflib_get_softc(ctx); 2897 struct em_tx_queue *tx_que = adapter->tx_queues; 2898 struct em_rx_queue *rx_que = adapter->rx_queues; 2899 2900 if (tx_que != NULL) { 2901 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2902 struct tx_ring *txr = &tx_que->txr; 2903 if (txr->tx_rsq == NULL) 2904 break; 2905 2906 free(txr->tx_rsq, M_DEVBUF); 2907 txr->tx_rsq = NULL; 2908 } 2909 free(adapter->tx_queues, M_DEVBUF); 2910 adapter->tx_queues = NULL; 2911 } 2912 2913 if (rx_que != NULL) { 2914 free(adapter->rx_queues, M_DEVBUF); 2915 adapter->rx_queues = NULL; 2916 } 2917 2918 em_release_hw_control(adapter); 2919 2920 if (adapter->mta != NULL) { 2921 free(adapter->mta, M_DEVBUF); 2922 } 2923 } 2924 2925 /********************************************************************* 2926 * 2927 * Enable transmit unit. 2928 * 2929 **********************************************************************/ 2930 static void 2931 em_initialize_transmit_unit(if_ctx_t ctx) 2932 { 2933 struct adapter *adapter = iflib_get_softc(ctx); 2934 if_softc_ctx_t scctx = adapter->shared; 2935 struct em_tx_queue *que; 2936 struct tx_ring *txr; 2937 struct e1000_hw *hw = &adapter->hw; 2938 u32 tctl, txdctl = 0, tarc, tipg = 0; 2939 2940 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2941 2942 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2943 u64 bus_addr; 2944 caddr_t offp, endp; 2945 2946 que = &adapter->tx_queues[i]; 2947 txr = &que->txr; 2948 bus_addr = txr->tx_paddr; 2949 2950 /* Clear checksum offload context. */ 2951 offp = (caddr_t)&txr->csum_flags; 2952 endp = (caddr_t)(txr + 1); 2953 bzero(offp, endp - offp); 2954 2955 /* Base and Len of TX Ring */ 2956 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2957 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2958 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2959 (u32)(bus_addr >> 32)); 2960 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2961 (u32)bus_addr); 2962 /* Init the HEAD/TAIL indices */ 2963 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2964 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2965 2966 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2967 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2968 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2969 2970 txdctl = 0; /* clear txdctl */ 2971 txdctl |= 0x1f; /* PTHRESH */ 2972 txdctl |= 1 << 8; /* HTHRESH */ 2973 txdctl |= 1 << 16;/* WTHRESH */ 2974 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2975 txdctl |= E1000_TXDCTL_GRAN; 2976 txdctl |= 1 << 25; /* LWTHRESH */ 2977 2978 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2979 } 2980 2981 /* Set the default values for the Tx Inter Packet Gap timer */ 2982 switch (adapter->hw.mac.type) { 2983 case e1000_80003es2lan: 2984 tipg = DEFAULT_82543_TIPG_IPGR1; 2985 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2986 E1000_TIPG_IPGR2_SHIFT; 2987 break; 2988 case e1000_82542: 2989 tipg = DEFAULT_82542_TIPG_IPGT; 2990 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2991 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2992 break; 2993 default: 2994 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2995 (adapter->hw.phy.media_type == 2996 e1000_media_type_internal_serdes)) 2997 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2998 else 2999 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3000 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3001 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3002 } 3003 3004 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3005 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3006 3007 if(adapter->hw.mac.type >= e1000_82540) 3008 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3009 adapter->tx_abs_int_delay.value); 3010 3011 if ((adapter->hw.mac.type == e1000_82571) || 3012 (adapter->hw.mac.type == e1000_82572)) { 3013 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3014 tarc |= TARC_SPEED_MODE_BIT; 3015 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3016 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3017 /* errata: program both queues to unweighted RR */ 3018 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3019 tarc |= 1; 3020 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3021 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3022 tarc |= 1; 3023 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3024 } else if (adapter->hw.mac.type == e1000_82574) { 3025 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3026 tarc |= TARC_ERRATA_BIT; 3027 if ( adapter->tx_num_queues > 1) { 3028 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3029 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3030 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3031 } else 3032 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3033 } 3034 3035 if (adapter->tx_int_delay.value > 0) 3036 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3037 3038 /* Program the Transmit Control Register */ 3039 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3040 tctl &= ~E1000_TCTL_CT; 3041 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3042 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3043 3044 if (adapter->hw.mac.type >= e1000_82571) 3045 tctl |= E1000_TCTL_MULR; 3046 3047 /* This write will effectively turn on the transmit unit. */ 3048 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3049 3050 /* SPT and KBL errata workarounds */ 3051 if (hw->mac.type == e1000_pch_spt) { 3052 u32 reg; 3053 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3054 reg |= E1000_RCTL_RDMTS_HEX; 3055 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3056 /* i218-i219 Specification Update 1.5.4.5 */ 3057 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3058 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3059 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3060 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3061 } 3062 } 3063 3064 /********************************************************************* 3065 * 3066 * Enable receive unit. 3067 * 3068 **********************************************************************/ 3069 3070 static void 3071 em_initialize_receive_unit(if_ctx_t ctx) 3072 { 3073 struct adapter *adapter = iflib_get_softc(ctx); 3074 if_softc_ctx_t scctx = adapter->shared; 3075 struct ifnet *ifp = iflib_get_ifp(ctx); 3076 struct e1000_hw *hw = &adapter->hw; 3077 struct em_rx_queue *que; 3078 int i; 3079 u32 rctl, rxcsum, rfctl; 3080 3081 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3082 3083 /* 3084 * Make sure receives are disabled while setting 3085 * up the descriptor ring 3086 */ 3087 rctl = E1000_READ_REG(hw, E1000_RCTL); 3088 /* Do not disable if ever enabled on this hardware */ 3089 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3090 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3091 3092 /* Setup the Receive Control Register */ 3093 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3094 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3095 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3096 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3097 3098 /* Do not store bad packets */ 3099 rctl &= ~E1000_RCTL_SBP; 3100 3101 /* Enable Long Packet receive */ 3102 if (if_getmtu(ifp) > ETHERMTU) 3103 rctl |= E1000_RCTL_LPE; 3104 else 3105 rctl &= ~E1000_RCTL_LPE; 3106 3107 /* Strip the CRC */ 3108 if (!em_disable_crc_stripping) 3109 rctl |= E1000_RCTL_SECRC; 3110 3111 if (adapter->hw.mac.type >= e1000_82540) { 3112 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3113 adapter->rx_abs_int_delay.value); 3114 3115 /* 3116 * Set the interrupt throttling rate. Value is calculated 3117 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3118 */ 3119 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3120 } 3121 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3122 adapter->rx_int_delay.value); 3123 3124 /* Use extended rx descriptor formats */ 3125 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3126 rfctl |= E1000_RFCTL_EXTEN; 3127 /* 3128 * When using MSIX interrupts we need to throttle 3129 * using the EITR register (82574 only) 3130 */ 3131 if (hw->mac.type == e1000_82574) { 3132 for (int i = 0; i < 4; i++) 3133 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3134 DEFAULT_ITR); 3135 /* Disable accelerated acknowledge */ 3136 rfctl |= E1000_RFCTL_ACK_DIS; 3137 } 3138 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3139 3140 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3141 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3142 adapter->hw.mac.type >= e1000_82543) { 3143 if (adapter->tx_num_queues > 1) { 3144 if (adapter->hw.mac.type >= igb_mac_min) { 3145 rxcsum |= E1000_RXCSUM_PCSD; 3146 if (hw->mac.type != e1000_82575) 3147 rxcsum |= E1000_RXCSUM_CRCOFL; 3148 } else 3149 rxcsum |= E1000_RXCSUM_TUOFL | 3150 E1000_RXCSUM_IPOFL | 3151 E1000_RXCSUM_PCSD; 3152 } else { 3153 if (adapter->hw.mac.type >= igb_mac_min) 3154 rxcsum |= E1000_RXCSUM_IPPCSE; 3155 else 3156 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3157 if (adapter->hw.mac.type > e1000_82575) 3158 rxcsum |= E1000_RXCSUM_CRCOFL; 3159 } 3160 } else 3161 rxcsum &= ~E1000_RXCSUM_TUOFL; 3162 3163 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3164 3165 if (adapter->rx_num_queues > 1) { 3166 if (adapter->hw.mac.type >= igb_mac_min) 3167 igb_initialize_rss_mapping(adapter); 3168 else 3169 em_initialize_rss_mapping(adapter); 3170 } 3171 3172 /* 3173 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3174 * long latencies are observed, like Lenovo X60. This 3175 * change eliminates the problem, but since having positive 3176 * values in RDTR is a known source of problems on other 3177 * platforms another solution is being sought. 3178 */ 3179 if (hw->mac.type == e1000_82573) 3180 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3181 3182 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3183 struct rx_ring *rxr = &que->rxr; 3184 /* Setup the Base and Length of the Rx Descriptor Ring */ 3185 u64 bus_addr = rxr->rx_paddr; 3186 #if 0 3187 u32 rdt = adapter->rx_num_queues -1; /* default */ 3188 #endif 3189 3190 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3191 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3192 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3193 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3194 /* Setup the Head and Tail Descriptor Pointers */ 3195 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3196 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3197 } 3198 3199 /* 3200 * Set PTHRESH for improved jumbo performance 3201 * According to 10.2.5.11 of Intel 82574 Datasheet, 3202 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3203 * Only write to RXDCTL(1) if there is a need for different 3204 * settings. 3205 */ 3206 3207 if (((adapter->hw.mac.type == e1000_ich9lan) || 3208 (adapter->hw.mac.type == e1000_pch2lan) || 3209 (adapter->hw.mac.type == e1000_ich10lan)) && 3210 (if_getmtu(ifp) > ETHERMTU)) { 3211 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3212 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3213 } else if (adapter->hw.mac.type == e1000_82574) { 3214 for (int i = 0; i < adapter->rx_num_queues; i++) { 3215 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3216 rxdctl |= 0x20; /* PTHRESH */ 3217 rxdctl |= 4 << 8; /* HTHRESH */ 3218 rxdctl |= 4 << 16;/* WTHRESH */ 3219 rxdctl |= 1 << 24; /* Switch to granularity */ 3220 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3221 } 3222 } else if (adapter->hw.mac.type >= igb_mac_min) { 3223 u32 psize, srrctl = 0; 3224 3225 if (if_getmtu(ifp) > ETHERMTU) { 3226 /* Set maximum packet len */ 3227 if (adapter->rx_mbuf_sz <= 4096) { 3228 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3229 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3230 } else if (adapter->rx_mbuf_sz > 4096) { 3231 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3232 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3233 } 3234 psize = scctx->isc_max_frame_size; 3235 /* are we on a vlan? */ 3236 if (ifp->if_vlantrunk != NULL) 3237 psize += VLAN_TAG_SIZE; 3238 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3239 } else { 3240 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3241 rctl |= E1000_RCTL_SZ_2048; 3242 } 3243 3244 /* 3245 * If TX flow control is disabled and there's >1 queue defined, 3246 * enable DROP. 3247 * 3248 * This drops frames rather than hanging the RX MAC for all queues. 3249 */ 3250 if ((adapter->rx_num_queues > 1) && 3251 (adapter->fc == e1000_fc_none || 3252 adapter->fc == e1000_fc_rx_pause)) { 3253 srrctl |= E1000_SRRCTL_DROP_EN; 3254 } 3255 /* Setup the Base and Length of the Rx Descriptor Rings */ 3256 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3257 struct rx_ring *rxr = &que->rxr; 3258 u64 bus_addr = rxr->rx_paddr; 3259 u32 rxdctl; 3260 3261 #ifdef notyet 3262 /* Configure for header split? -- ignore for now */ 3263 rxr->hdr_split = igb_header_split; 3264 #else 3265 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3266 #endif 3267 3268 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3269 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3270 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3271 (uint32_t)(bus_addr >> 32)); 3272 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3273 (uint32_t)bus_addr); 3274 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3275 /* Enable this Queue */ 3276 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3277 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3278 rxdctl &= 0xFFF00000; 3279 rxdctl |= IGB_RX_PTHRESH; 3280 rxdctl |= IGB_RX_HTHRESH << 8; 3281 rxdctl |= IGB_RX_WTHRESH << 16; 3282 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3283 } 3284 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3285 if (if_getmtu(ifp) > ETHERMTU) 3286 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3287 else 3288 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3289 } 3290 3291 /* Make sure VLAN Filters are off */ 3292 rctl &= ~E1000_RCTL_VFE; 3293 3294 if (adapter->hw.mac.type < igb_mac_min) { 3295 if (adapter->rx_mbuf_sz == MCLBYTES) 3296 rctl |= E1000_RCTL_SZ_2048; 3297 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3298 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3299 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3300 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3301 3302 /* ensure we clear use DTYPE of 00 here */ 3303 rctl &= ~0x00000C00; 3304 } 3305 3306 /* Write out the settings */ 3307 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3308 3309 return; 3310 } 3311 3312 static void 3313 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3314 { 3315 struct adapter *adapter = iflib_get_softc(ctx); 3316 u32 index, bit; 3317 3318 index = (vtag >> 5) & 0x7F; 3319 bit = vtag & 0x1F; 3320 adapter->shadow_vfta[index] |= (1 << bit); 3321 ++adapter->num_vlans; 3322 } 3323 3324 static void 3325 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3326 { 3327 struct adapter *adapter = iflib_get_softc(ctx); 3328 u32 index, bit; 3329 3330 index = (vtag >> 5) & 0x7F; 3331 bit = vtag & 0x1F; 3332 adapter->shadow_vfta[index] &= ~(1 << bit); 3333 --adapter->num_vlans; 3334 } 3335 3336 static void 3337 em_setup_vlan_hw_support(struct adapter *adapter) 3338 { 3339 struct e1000_hw *hw = &adapter->hw; 3340 u32 reg; 3341 3342 /* 3343 * We get here thru init_locked, meaning 3344 * a soft reset, this has already cleared 3345 * the VFTA and other state, so if there 3346 * have been no vlan's registered do nothing. 3347 */ 3348 if (adapter->num_vlans == 0) 3349 return; 3350 3351 /* 3352 * A soft reset zero's out the VFTA, so 3353 * we need to repopulate it now. 3354 */ 3355 for (int i = 0; i < EM_VFTA_SIZE; i++) 3356 if (adapter->shadow_vfta[i] != 0) 3357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3358 i, adapter->shadow_vfta[i]); 3359 3360 reg = E1000_READ_REG(hw, E1000_CTRL); 3361 reg |= E1000_CTRL_VME; 3362 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3363 3364 /* Enable the Filter Table */ 3365 reg = E1000_READ_REG(hw, E1000_RCTL); 3366 reg &= ~E1000_RCTL_CFIEN; 3367 reg |= E1000_RCTL_VFE; 3368 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3369 } 3370 3371 static void 3372 em_if_enable_intr(if_ctx_t ctx) 3373 { 3374 struct adapter *adapter = iflib_get_softc(ctx); 3375 struct e1000_hw *hw = &adapter->hw; 3376 u32 ims_mask = IMS_ENABLE_MASK; 3377 3378 if (hw->mac.type == e1000_82574) { 3379 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3380 ims_mask |= adapter->ims; 3381 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3382 u32 mask = (adapter->que_mask | adapter->link_mask); 3383 3384 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3385 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3386 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3387 ims_mask = E1000_IMS_LSC; 3388 } 3389 3390 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3391 } 3392 3393 static void 3394 em_if_disable_intr(if_ctx_t ctx) 3395 { 3396 struct adapter *adapter = iflib_get_softc(ctx); 3397 struct e1000_hw *hw = &adapter->hw; 3398 3399 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3400 if (hw->mac.type >= igb_mac_min) 3401 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3402 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3403 } 3404 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3405 } 3406 3407 /* 3408 * Bit of a misnomer, what this really means is 3409 * to enable OS management of the system... aka 3410 * to disable special hardware management features 3411 */ 3412 static void 3413 em_init_manageability(struct adapter *adapter) 3414 { 3415 /* A shared code workaround */ 3416 #define E1000_82542_MANC2H E1000_MANC2H 3417 if (adapter->has_manage) { 3418 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3419 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3420 3421 /* disable hardware interception of ARP */ 3422 manc &= ~(E1000_MANC_ARP_EN); 3423 3424 /* enable receiving management packets to the host */ 3425 manc |= E1000_MANC_EN_MNG2HOST; 3426 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3427 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3428 manc2h |= E1000_MNG2HOST_PORT_623; 3429 manc2h |= E1000_MNG2HOST_PORT_664; 3430 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3431 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3432 } 3433 } 3434 3435 /* 3436 * Give control back to hardware management 3437 * controller if there is one. 3438 */ 3439 static void 3440 em_release_manageability(struct adapter *adapter) 3441 { 3442 if (adapter->has_manage) { 3443 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3444 3445 /* re-enable hardware interception of ARP */ 3446 manc |= E1000_MANC_ARP_EN; 3447 manc &= ~E1000_MANC_EN_MNG2HOST; 3448 3449 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3450 } 3451 } 3452 3453 /* 3454 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3455 * For ASF and Pass Through versions of f/w this means 3456 * that the driver is loaded. For AMT version type f/w 3457 * this means that the network i/f is open. 3458 */ 3459 static void 3460 em_get_hw_control(struct adapter *adapter) 3461 { 3462 u32 ctrl_ext, swsm; 3463 3464 if (adapter->vf_ifp) 3465 return; 3466 3467 if (adapter->hw.mac.type == e1000_82573) { 3468 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3469 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3470 swsm | E1000_SWSM_DRV_LOAD); 3471 return; 3472 } 3473 /* else */ 3474 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3475 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3476 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3477 } 3478 3479 /* 3480 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3481 * For ASF and Pass Through versions of f/w this means that 3482 * the driver is no longer loaded. For AMT versions of the 3483 * f/w this means that the network i/f is closed. 3484 */ 3485 static void 3486 em_release_hw_control(struct adapter *adapter) 3487 { 3488 u32 ctrl_ext, swsm; 3489 3490 if (!adapter->has_manage) 3491 return; 3492 3493 if (adapter->hw.mac.type == e1000_82573) { 3494 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3495 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3496 swsm & ~E1000_SWSM_DRV_LOAD); 3497 return; 3498 } 3499 /* else */ 3500 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3501 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3502 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3503 return; 3504 } 3505 3506 static int 3507 em_is_valid_ether_addr(u8 *addr) 3508 { 3509 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3510 3511 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3512 return (FALSE); 3513 } 3514 3515 return (TRUE); 3516 } 3517 3518 /* 3519 ** Parse the interface capabilities with regard 3520 ** to both system management and wake-on-lan for 3521 ** later use. 3522 */ 3523 static void 3524 em_get_wakeup(if_ctx_t ctx) 3525 { 3526 struct adapter *adapter = iflib_get_softc(ctx); 3527 device_t dev = iflib_get_dev(ctx); 3528 u16 eeprom_data = 0, device_id, apme_mask; 3529 3530 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3531 apme_mask = EM_EEPROM_APME; 3532 3533 switch (adapter->hw.mac.type) { 3534 case e1000_82542: 3535 case e1000_82543: 3536 break; 3537 case e1000_82544: 3538 e1000_read_nvm(&adapter->hw, 3539 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3540 apme_mask = EM_82544_APME; 3541 break; 3542 case e1000_82546: 3543 case e1000_82546_rev_3: 3544 if (adapter->hw.bus.func == 1) { 3545 e1000_read_nvm(&adapter->hw, 3546 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3547 break; 3548 } else 3549 e1000_read_nvm(&adapter->hw, 3550 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3551 break; 3552 case e1000_82573: 3553 case e1000_82583: 3554 adapter->has_amt = TRUE; 3555 /* FALLTHROUGH */ 3556 case e1000_82571: 3557 case e1000_82572: 3558 case e1000_80003es2lan: 3559 if (adapter->hw.bus.func == 1) { 3560 e1000_read_nvm(&adapter->hw, 3561 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3562 break; 3563 } else 3564 e1000_read_nvm(&adapter->hw, 3565 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3566 break; 3567 case e1000_ich8lan: 3568 case e1000_ich9lan: 3569 case e1000_ich10lan: 3570 case e1000_pchlan: 3571 case e1000_pch2lan: 3572 case e1000_pch_lpt: 3573 case e1000_pch_spt: 3574 case e1000_82575: /* listing all igb devices */ 3575 case e1000_82576: 3576 case e1000_82580: 3577 case e1000_i350: 3578 case e1000_i354: 3579 case e1000_i210: 3580 case e1000_i211: 3581 case e1000_vfadapt: 3582 case e1000_vfadapt_i350: 3583 apme_mask = E1000_WUC_APME; 3584 adapter->has_amt = TRUE; 3585 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3586 break; 3587 default: 3588 e1000_read_nvm(&adapter->hw, 3589 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3590 break; 3591 } 3592 if (eeprom_data & apme_mask) 3593 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3594 /* 3595 * We have the eeprom settings, now apply the special cases 3596 * where the eeprom may be wrong or the board won't support 3597 * wake on lan on a particular port 3598 */ 3599 device_id = pci_get_device(dev); 3600 switch (device_id) { 3601 case E1000_DEV_ID_82546GB_PCIE: 3602 adapter->wol = 0; 3603 break; 3604 case E1000_DEV_ID_82546EB_FIBER: 3605 case E1000_DEV_ID_82546GB_FIBER: 3606 /* Wake events only supported on port A for dual fiber 3607 * regardless of eeprom setting */ 3608 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3609 E1000_STATUS_FUNC_1) 3610 adapter->wol = 0; 3611 break; 3612 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3613 /* if quad port adapter, disable WoL on all but port A */ 3614 if (global_quad_port_a != 0) 3615 adapter->wol = 0; 3616 /* Reset for multiple quad port adapters */ 3617 if (++global_quad_port_a == 4) 3618 global_quad_port_a = 0; 3619 break; 3620 case E1000_DEV_ID_82571EB_FIBER: 3621 /* Wake events only supported on port A for dual fiber 3622 * regardless of eeprom setting */ 3623 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3624 E1000_STATUS_FUNC_1) 3625 adapter->wol = 0; 3626 break; 3627 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3628 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3629 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3630 /* if quad port adapter, disable WoL on all but port A */ 3631 if (global_quad_port_a != 0) 3632 adapter->wol = 0; 3633 /* Reset for multiple quad port adapters */ 3634 if (++global_quad_port_a == 4) 3635 global_quad_port_a = 0; 3636 break; 3637 } 3638 return; 3639 } 3640 3641 3642 /* 3643 * Enable PCI Wake On Lan capability 3644 */ 3645 static void 3646 em_enable_wakeup(if_ctx_t ctx) 3647 { 3648 struct adapter *adapter = iflib_get_softc(ctx); 3649 device_t dev = iflib_get_dev(ctx); 3650 if_t ifp = iflib_get_ifp(ctx); 3651 int error = 0; 3652 u32 pmc, ctrl, ctrl_ext, rctl; 3653 u16 status; 3654 3655 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3656 return; 3657 3658 /* 3659 * Determine type of Wakeup: note that wol 3660 * is set with all bits on by default. 3661 */ 3662 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3663 adapter->wol &= ~E1000_WUFC_MAG; 3664 3665 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3666 adapter->wol &= ~E1000_WUFC_EX; 3667 3668 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3669 adapter->wol &= ~E1000_WUFC_MC; 3670 else { 3671 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3672 rctl |= E1000_RCTL_MPE; 3673 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3674 } 3675 3676 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3677 goto pme; 3678 3679 /* Advertise the wakeup capability */ 3680 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3681 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3682 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3683 3684 /* Keep the laser running on Fiber adapters */ 3685 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3686 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3687 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3688 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3689 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3690 } 3691 3692 if ((adapter->hw.mac.type == e1000_ich8lan) || 3693 (adapter->hw.mac.type == e1000_pchlan) || 3694 (adapter->hw.mac.type == e1000_ich9lan) || 3695 (adapter->hw.mac.type == e1000_ich10lan)) 3696 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3697 3698 if ( adapter->hw.mac.type >= e1000_pchlan) { 3699 error = em_enable_phy_wakeup(adapter); 3700 if (error) 3701 goto pme; 3702 } else { 3703 /* Enable wakeup by the MAC */ 3704 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3705 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3706 } 3707 3708 if (adapter->hw.phy.type == e1000_phy_igp_3) 3709 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3710 3711 pme: 3712 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3713 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3714 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3715 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3716 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3717 3718 return; 3719 } 3720 3721 /* 3722 * WOL in the newer chipset interfaces (pchlan) 3723 * require thing to be copied into the phy 3724 */ 3725 static int 3726 em_enable_phy_wakeup(struct adapter *adapter) 3727 { 3728 struct e1000_hw *hw = &adapter->hw; 3729 u32 mreg, ret = 0; 3730 u16 preg; 3731 3732 /* copy MAC RARs to PHY RARs */ 3733 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3734 3735 /* copy MAC MTA to PHY MTA */ 3736 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3737 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3738 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3739 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3740 (u16)((mreg >> 16) & 0xFFFF)); 3741 } 3742 3743 /* configure PHY Rx Control register */ 3744 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3745 mreg = E1000_READ_REG(hw, E1000_RCTL); 3746 if (mreg & E1000_RCTL_UPE) 3747 preg |= BM_RCTL_UPE; 3748 if (mreg & E1000_RCTL_MPE) 3749 preg |= BM_RCTL_MPE; 3750 preg &= ~(BM_RCTL_MO_MASK); 3751 if (mreg & E1000_RCTL_MO_3) 3752 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3753 << BM_RCTL_MO_SHIFT); 3754 if (mreg & E1000_RCTL_BAM) 3755 preg |= BM_RCTL_BAM; 3756 if (mreg & E1000_RCTL_PMCF) 3757 preg |= BM_RCTL_PMCF; 3758 mreg = E1000_READ_REG(hw, E1000_CTRL); 3759 if (mreg & E1000_CTRL_RFCE) 3760 preg |= BM_RCTL_RFCE; 3761 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3762 3763 /* enable PHY wakeup in MAC register */ 3764 E1000_WRITE_REG(hw, E1000_WUC, 3765 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3766 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3767 3768 /* configure and enable PHY wakeup in PHY registers */ 3769 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3770 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3771 3772 /* activate PHY wakeup */ 3773 ret = hw->phy.ops.acquire(hw); 3774 if (ret) { 3775 printf("Could not acquire PHY\n"); 3776 return ret; 3777 } 3778 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3779 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3780 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3781 if (ret) { 3782 printf("Could not read PHY page 769\n"); 3783 goto out; 3784 } 3785 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3786 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3787 if (ret) 3788 printf("Could not set PHY Host Wakeup bit\n"); 3789 out: 3790 hw->phy.ops.release(hw); 3791 3792 return ret; 3793 } 3794 3795 static void 3796 em_if_led_func(if_ctx_t ctx, int onoff) 3797 { 3798 struct adapter *adapter = iflib_get_softc(ctx); 3799 3800 if (onoff) { 3801 e1000_setup_led(&adapter->hw); 3802 e1000_led_on(&adapter->hw); 3803 } else { 3804 e1000_led_off(&adapter->hw); 3805 e1000_cleanup_led(&adapter->hw); 3806 } 3807 } 3808 3809 /* 3810 * Disable the L0S and L1 LINK states 3811 */ 3812 static void 3813 em_disable_aspm(struct adapter *adapter) 3814 { 3815 int base, reg; 3816 u16 link_cap,link_ctrl; 3817 device_t dev = adapter->dev; 3818 3819 switch (adapter->hw.mac.type) { 3820 case e1000_82573: 3821 case e1000_82574: 3822 case e1000_82583: 3823 break; 3824 default: 3825 return; 3826 } 3827 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3828 return; 3829 reg = base + PCIER_LINK_CAP; 3830 link_cap = pci_read_config(dev, reg, 2); 3831 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3832 return; 3833 reg = base + PCIER_LINK_CTL; 3834 link_ctrl = pci_read_config(dev, reg, 2); 3835 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3836 pci_write_config(dev, reg, link_ctrl, 2); 3837 return; 3838 } 3839 3840 /********************************************************************** 3841 * 3842 * Update the board statistics counters. 3843 * 3844 **********************************************************************/ 3845 static void 3846 em_update_stats_counters(struct adapter *adapter) 3847 { 3848 3849 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3850 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3851 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3852 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3853 } 3854 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3855 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3856 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3857 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3858 3859 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3860 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3861 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3862 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3863 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3864 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3865 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3866 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3867 /* 3868 ** For watchdog management we need to know if we have been 3869 ** paused during the last interval, so capture that here. 3870 */ 3871 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3872 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3873 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3874 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3875 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3876 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3877 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3878 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3879 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3880 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3881 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3882 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3883 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3884 3885 /* For the 64-bit byte counters the low dword must be read first. */ 3886 /* Both registers clear on the read of the high dword */ 3887 3888 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3889 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3890 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3891 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3892 3893 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3894 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3895 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3896 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3897 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3898 3899 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3900 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3901 3902 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3903 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3904 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3905 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3906 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3907 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3908 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3909 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3910 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3911 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3912 3913 /* Interrupt Counts */ 3914 3915 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3916 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3917 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3918 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3919 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3920 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3921 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3922 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3923 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3924 3925 if (adapter->hw.mac.type >= e1000_82543) { 3926 adapter->stats.algnerrc += 3927 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3928 adapter->stats.rxerrc += 3929 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3930 adapter->stats.tncrs += 3931 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3932 adapter->stats.cexterr += 3933 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3934 adapter->stats.tsctc += 3935 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3936 adapter->stats.tsctfc += 3937 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3938 } 3939 } 3940 3941 static uint64_t 3942 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3943 { 3944 struct adapter *adapter = iflib_get_softc(ctx); 3945 struct ifnet *ifp = iflib_get_ifp(ctx); 3946 3947 switch (cnt) { 3948 case IFCOUNTER_COLLISIONS: 3949 return (adapter->stats.colc); 3950 case IFCOUNTER_IERRORS: 3951 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3952 adapter->stats.crcerrs + adapter->stats.algnerrc + 3953 adapter->stats.ruc + adapter->stats.roc + 3954 adapter->stats.mpc + adapter->stats.cexterr); 3955 case IFCOUNTER_OERRORS: 3956 return (adapter->stats.ecol + adapter->stats.latecol + 3957 adapter->watchdog_events); 3958 default: 3959 return (if_get_counter_default(ifp, cnt)); 3960 } 3961 } 3962 3963 /* Export a single 32-bit register via a read-only sysctl. */ 3964 static int 3965 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3966 { 3967 struct adapter *adapter; 3968 u_int val; 3969 3970 adapter = oidp->oid_arg1; 3971 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3972 return (sysctl_handle_int(oidp, &val, 0, req)); 3973 } 3974 3975 /* 3976 * Add sysctl variables, one per statistic, to the system. 3977 */ 3978 static void 3979 em_add_hw_stats(struct adapter *adapter) 3980 { 3981 device_t dev = iflib_get_dev(adapter->ctx); 3982 struct em_tx_queue *tx_que = adapter->tx_queues; 3983 struct em_rx_queue *rx_que = adapter->rx_queues; 3984 3985 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3986 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3987 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3988 struct e1000_hw_stats *stats = &adapter->stats; 3989 3990 struct sysctl_oid *stat_node, *queue_node, *int_node; 3991 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3992 3993 #define QUEUE_NAME_LEN 32 3994 char namebuf[QUEUE_NAME_LEN]; 3995 3996 /* Driver Statistics */ 3997 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3998 CTLFLAG_RD, &adapter->dropped_pkts, 3999 "Driver dropped packets"); 4000 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4001 CTLFLAG_RD, &adapter->link_irq, 4002 "Link MSIX IRQ Handled"); 4003 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4004 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4005 "Defragmenting mbuf chain failed"); 4006 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4007 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4008 "Driver tx dma failure in xmit"); 4009 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4010 CTLFLAG_RD, &adapter->rx_overruns, 4011 "RX overruns"); 4012 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4013 CTLFLAG_RD, &adapter->watchdog_events, 4014 "Watchdog timeouts"); 4015 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4016 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4017 em_sysctl_reg_handler, "IU", 4018 "Device Control Register"); 4019 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4020 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4021 em_sysctl_reg_handler, "IU", 4022 "Receiver Control Register"); 4023 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4024 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4025 "Flow Control High Watermark"); 4026 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4027 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4028 "Flow Control Low Watermark"); 4029 4030 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4031 struct tx_ring *txr = &tx_que->txr; 4032 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4033 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4034 CTLFLAG_RD, NULL, "TX Queue Name"); 4035 queue_list = SYSCTL_CHILDREN(queue_node); 4036 4037 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4038 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4039 E1000_TDH(txr->me), 4040 em_sysctl_reg_handler, "IU", 4041 "Transmit Descriptor Head"); 4042 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4043 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4044 E1000_TDT(txr->me), 4045 em_sysctl_reg_handler, "IU", 4046 "Transmit Descriptor Tail"); 4047 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4048 CTLFLAG_RD, &txr->tx_irq, 4049 "Queue MSI-X Transmit Interrupts"); 4050 } 4051 4052 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4053 struct rx_ring *rxr = &rx_que->rxr; 4054 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4055 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4056 CTLFLAG_RD, NULL, "RX Queue Name"); 4057 queue_list = SYSCTL_CHILDREN(queue_node); 4058 4059 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4060 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4061 E1000_RDH(rxr->me), 4062 em_sysctl_reg_handler, "IU", 4063 "Receive Descriptor Head"); 4064 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4065 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4066 E1000_RDT(rxr->me), 4067 em_sysctl_reg_handler, "IU", 4068 "Receive Descriptor Tail"); 4069 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4070 CTLFLAG_RD, &rxr->rx_irq, 4071 "Queue MSI-X Receive Interrupts"); 4072 } 4073 4074 /* MAC stats get their own sub node */ 4075 4076 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4077 CTLFLAG_RD, NULL, "Statistics"); 4078 stat_list = SYSCTL_CHILDREN(stat_node); 4079 4080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4081 CTLFLAG_RD, &stats->ecol, 4082 "Excessive collisions"); 4083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4084 CTLFLAG_RD, &stats->scc, 4085 "Single collisions"); 4086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4087 CTLFLAG_RD, &stats->mcc, 4088 "Multiple collisions"); 4089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4090 CTLFLAG_RD, &stats->latecol, 4091 "Late collisions"); 4092 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4093 CTLFLAG_RD, &stats->colc, 4094 "Collision Count"); 4095 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4096 CTLFLAG_RD, &adapter->stats.symerrs, 4097 "Symbol Errors"); 4098 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4099 CTLFLAG_RD, &adapter->stats.sec, 4100 "Sequence Errors"); 4101 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4102 CTLFLAG_RD, &adapter->stats.dc, 4103 "Defer Count"); 4104 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4105 CTLFLAG_RD, &adapter->stats.mpc, 4106 "Missed Packets"); 4107 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4108 CTLFLAG_RD, &adapter->stats.rnbc, 4109 "Receive No Buffers"); 4110 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4111 CTLFLAG_RD, &adapter->stats.ruc, 4112 "Receive Undersize"); 4113 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4114 CTLFLAG_RD, &adapter->stats.rfc, 4115 "Fragmented Packets Received "); 4116 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4117 CTLFLAG_RD, &adapter->stats.roc, 4118 "Oversized Packets Received"); 4119 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4120 CTLFLAG_RD, &adapter->stats.rjc, 4121 "Recevied Jabber"); 4122 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4123 CTLFLAG_RD, &adapter->stats.rxerrc, 4124 "Receive Errors"); 4125 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4126 CTLFLAG_RD, &adapter->stats.crcerrs, 4127 "CRC errors"); 4128 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4129 CTLFLAG_RD, &adapter->stats.algnerrc, 4130 "Alignment Errors"); 4131 /* On 82575 these are collision counts */ 4132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4133 CTLFLAG_RD, &adapter->stats.cexterr, 4134 "Collision/Carrier extension errors"); 4135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4136 CTLFLAG_RD, &adapter->stats.xonrxc, 4137 "XON Received"); 4138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4139 CTLFLAG_RD, &adapter->stats.xontxc, 4140 "XON Transmitted"); 4141 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4142 CTLFLAG_RD, &adapter->stats.xoffrxc, 4143 "XOFF Received"); 4144 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4145 CTLFLAG_RD, &adapter->stats.xofftxc, 4146 "XOFF Transmitted"); 4147 4148 /* Packet Reception Stats */ 4149 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4150 CTLFLAG_RD, &adapter->stats.tpr, 4151 "Total Packets Received "); 4152 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4153 CTLFLAG_RD, &adapter->stats.gprc, 4154 "Good Packets Received"); 4155 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4156 CTLFLAG_RD, &adapter->stats.bprc, 4157 "Broadcast Packets Received"); 4158 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4159 CTLFLAG_RD, &adapter->stats.mprc, 4160 "Multicast Packets Received"); 4161 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4162 CTLFLAG_RD, &adapter->stats.prc64, 4163 "64 byte frames received "); 4164 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4165 CTLFLAG_RD, &adapter->stats.prc127, 4166 "65-127 byte frames received"); 4167 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4168 CTLFLAG_RD, &adapter->stats.prc255, 4169 "128-255 byte frames received"); 4170 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4171 CTLFLAG_RD, &adapter->stats.prc511, 4172 "256-511 byte frames received"); 4173 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4174 CTLFLAG_RD, &adapter->stats.prc1023, 4175 "512-1023 byte frames received"); 4176 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4177 CTLFLAG_RD, &adapter->stats.prc1522, 4178 "1023-1522 byte frames received"); 4179 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4180 CTLFLAG_RD, &adapter->stats.gorc, 4181 "Good Octets Received"); 4182 4183 /* Packet Transmission Stats */ 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4185 CTLFLAG_RD, &adapter->stats.gotc, 4186 "Good Octets Transmitted"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4188 CTLFLAG_RD, &adapter->stats.tpt, 4189 "Total Packets Transmitted"); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4191 CTLFLAG_RD, &adapter->stats.gptc, 4192 "Good Packets Transmitted"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4194 CTLFLAG_RD, &adapter->stats.bptc, 4195 "Broadcast Packets Transmitted"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4197 CTLFLAG_RD, &adapter->stats.mptc, 4198 "Multicast Packets Transmitted"); 4199 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4200 CTLFLAG_RD, &adapter->stats.ptc64, 4201 "64 byte frames transmitted "); 4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4203 CTLFLAG_RD, &adapter->stats.ptc127, 4204 "65-127 byte frames transmitted"); 4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4206 CTLFLAG_RD, &adapter->stats.ptc255, 4207 "128-255 byte frames transmitted"); 4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4209 CTLFLAG_RD, &adapter->stats.ptc511, 4210 "256-511 byte frames transmitted"); 4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4212 CTLFLAG_RD, &adapter->stats.ptc1023, 4213 "512-1023 byte frames transmitted"); 4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4215 CTLFLAG_RD, &adapter->stats.ptc1522, 4216 "1024-1522 byte frames transmitted"); 4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4218 CTLFLAG_RD, &adapter->stats.tsctc, 4219 "TSO Contexts Transmitted"); 4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4221 CTLFLAG_RD, &adapter->stats.tsctfc, 4222 "TSO Contexts Failed"); 4223 4224 4225 /* Interrupt Stats */ 4226 4227 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4228 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4229 int_list = SYSCTL_CHILDREN(int_node); 4230 4231 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4232 CTLFLAG_RD, &adapter->stats.iac, 4233 "Interrupt Assertion Count"); 4234 4235 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4236 CTLFLAG_RD, &adapter->stats.icrxptc, 4237 "Interrupt Cause Rx Pkt Timer Expire Count"); 4238 4239 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4240 CTLFLAG_RD, &adapter->stats.icrxatc, 4241 "Interrupt Cause Rx Abs Timer Expire Count"); 4242 4243 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4244 CTLFLAG_RD, &adapter->stats.ictxptc, 4245 "Interrupt Cause Tx Pkt Timer Expire Count"); 4246 4247 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4248 CTLFLAG_RD, &adapter->stats.ictxatc, 4249 "Interrupt Cause Tx Abs Timer Expire Count"); 4250 4251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4252 CTLFLAG_RD, &adapter->stats.ictxqec, 4253 "Interrupt Cause Tx Queue Empty Count"); 4254 4255 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4256 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4257 "Interrupt Cause Tx Queue Min Thresh Count"); 4258 4259 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4260 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4261 "Interrupt Cause Rx Desc Min Thresh Count"); 4262 4263 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4264 CTLFLAG_RD, &adapter->stats.icrxoc, 4265 "Interrupt Cause Receiver Overrun Count"); 4266 } 4267 4268 /********************************************************************** 4269 * 4270 * This routine provides a way to dump out the adapter eeprom, 4271 * often a useful debug/service tool. This only dumps the first 4272 * 32 words, stuff that matters is in that extent. 4273 * 4274 **********************************************************************/ 4275 static int 4276 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4277 { 4278 struct adapter *adapter = (struct adapter *)arg1; 4279 int error; 4280 int result; 4281 4282 result = -1; 4283 error = sysctl_handle_int(oidp, &result, 0, req); 4284 4285 if (error || !req->newptr) 4286 return (error); 4287 4288 /* 4289 * This value will cause a hex dump of the 4290 * first 32 16-bit words of the EEPROM to 4291 * the screen. 4292 */ 4293 if (result == 1) 4294 em_print_nvm_info(adapter); 4295 4296 return (error); 4297 } 4298 4299 static void 4300 em_print_nvm_info(struct adapter *adapter) 4301 { 4302 u16 eeprom_data; 4303 int i, j, row = 0; 4304 4305 /* Its a bit crude, but it gets the job done */ 4306 printf("\nInterface EEPROM Dump:\n"); 4307 printf("Offset\n0x0000 "); 4308 for (i = 0, j = 0; i < 32; i++, j++) { 4309 if (j == 8) { /* Make the offset block */ 4310 j = 0; ++row; 4311 printf("\n0x00%x0 ",row); 4312 } 4313 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4314 printf("%04x ", eeprom_data); 4315 } 4316 printf("\n"); 4317 } 4318 4319 static int 4320 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4321 { 4322 struct em_int_delay_info *info; 4323 struct adapter *adapter; 4324 u32 regval; 4325 int error, usecs, ticks; 4326 4327 info = (struct em_int_delay_info *) arg1; 4328 usecs = info->value; 4329 error = sysctl_handle_int(oidp, &usecs, 0, req); 4330 if (error != 0 || req->newptr == NULL) 4331 return (error); 4332 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4333 return (EINVAL); 4334 info->value = usecs; 4335 ticks = EM_USECS_TO_TICKS(usecs); 4336 if (info->offset == E1000_ITR) /* units are 256ns here */ 4337 ticks *= 4; 4338 4339 adapter = info->adapter; 4340 4341 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4342 regval = (regval & ~0xffff) | (ticks & 0xffff); 4343 /* Handle a few special cases. */ 4344 switch (info->offset) { 4345 case E1000_RDTR: 4346 break; 4347 case E1000_TIDV: 4348 if (ticks == 0) { 4349 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4350 /* Don't write 0 into the TIDV register. */ 4351 regval++; 4352 } else 4353 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4354 break; 4355 } 4356 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4357 return (0); 4358 } 4359 4360 static void 4361 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4362 const char *description, struct em_int_delay_info *info, 4363 int offset, int value) 4364 { 4365 info->adapter = adapter; 4366 info->offset = offset; 4367 info->value = value; 4368 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4369 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4370 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4371 info, 0, em_sysctl_int_delay, "I", description); 4372 } 4373 4374 /* 4375 * Set flow control using sysctl: 4376 * Flow control values: 4377 * 0 - off 4378 * 1 - rx pause 4379 * 2 - tx pause 4380 * 3 - full 4381 */ 4382 static int 4383 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4384 { 4385 int error; 4386 static int input = 3; /* default is full */ 4387 struct adapter *adapter = (struct adapter *) arg1; 4388 4389 error = sysctl_handle_int(oidp, &input, 0, req); 4390 4391 if ((error) || (req->newptr == NULL)) 4392 return (error); 4393 4394 if (input == adapter->fc) /* no change? */ 4395 return (error); 4396 4397 switch (input) { 4398 case e1000_fc_rx_pause: 4399 case e1000_fc_tx_pause: 4400 case e1000_fc_full: 4401 case e1000_fc_none: 4402 adapter->hw.fc.requested_mode = input; 4403 adapter->fc = input; 4404 break; 4405 default: 4406 /* Do nothing */ 4407 return (error); 4408 } 4409 4410 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4411 e1000_force_mac_fc(&adapter->hw); 4412 return (error); 4413 } 4414 4415 /* 4416 * Manage Energy Efficient Ethernet: 4417 * Control values: 4418 * 0/1 - enabled/disabled 4419 */ 4420 static int 4421 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4422 { 4423 struct adapter *adapter = (struct adapter *) arg1; 4424 int error, value; 4425 4426 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4427 error = sysctl_handle_int(oidp, &value, 0, req); 4428 if (error || req->newptr == NULL) 4429 return (error); 4430 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4431 em_if_init(adapter->ctx); 4432 4433 return (0); 4434 } 4435 4436 static int 4437 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4438 { 4439 struct adapter *adapter; 4440 int error; 4441 int result; 4442 4443 result = -1; 4444 error = sysctl_handle_int(oidp, &result, 0, req); 4445 4446 if (error || !req->newptr) 4447 return (error); 4448 4449 if (result == 1) { 4450 adapter = (struct adapter *) arg1; 4451 em_print_debug_info(adapter); 4452 } 4453 4454 return (error); 4455 } 4456 4457 static int 4458 em_get_rs(SYSCTL_HANDLER_ARGS) 4459 { 4460 struct adapter *adapter = (struct adapter *) arg1; 4461 int error; 4462 int result; 4463 4464 result = 0; 4465 error = sysctl_handle_int(oidp, &result, 0, req); 4466 4467 if (error || !req->newptr || result != 1) 4468 return (error); 4469 em_dump_rs(adapter); 4470 4471 return (error); 4472 } 4473 4474 static void 4475 em_if_debug(if_ctx_t ctx) 4476 { 4477 em_dump_rs(iflib_get_softc(ctx)); 4478 } 4479 4480 /* 4481 * This routine is meant to be fluid, add whatever is 4482 * needed for debugging a problem. -jfv 4483 */ 4484 static void 4485 em_print_debug_info(struct adapter *adapter) 4486 { 4487 device_t dev = iflib_get_dev(adapter->ctx); 4488 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4489 struct tx_ring *txr = &adapter->tx_queues->txr; 4490 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4491 4492 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4493 printf("Interface is RUNNING "); 4494 else 4495 printf("Interface is NOT RUNNING\n"); 4496 4497 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4498 printf("and INACTIVE\n"); 4499 else 4500 printf("and ACTIVE\n"); 4501 4502 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4503 device_printf(dev, "TX Queue %d ------\n", i); 4504 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4505 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4506 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4507 4508 } 4509 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4510 device_printf(dev, "RX Queue %d ------\n", j); 4511 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4512 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4513 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4514 } 4515 } 4516 4517 /* 4518 * 82574 only: 4519 * Write a new value to the EEPROM increasing the number of MSIX 4520 * vectors from 3 to 5, for proper multiqueue support. 4521 */ 4522 static void 4523 em_enable_vectors_82574(if_ctx_t ctx) 4524 { 4525 struct adapter *adapter = iflib_get_softc(ctx); 4526 struct e1000_hw *hw = &adapter->hw; 4527 device_t dev = iflib_get_dev(ctx); 4528 u16 edata; 4529 4530 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4531 printf("Current cap: %#06x\n", edata); 4532 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4533 device_printf(dev, "Writing to eeprom: increasing " 4534 "reported MSIX vectors from 3 to 5...\n"); 4535 edata &= ~(EM_NVM_MSIX_N_MASK); 4536 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4537 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4538 e1000_update_nvm_checksum(hw); 4539 device_printf(dev, "Writing to eeprom: done\n"); 4540 } 4541 } 4542