1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 411 static void em_if_init(if_ctx_t); 412 static void em_if_stop(if_ctx_t); 413 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 414 static int em_if_media_change(if_ctx_t); 415 static int em_if_mtu_set(if_ctx_t, uint32_t); 416 static void em_if_timer(if_ctx_t, uint16_t); 417 static void em_if_vlan_register(if_ctx_t, u16); 418 static void em_if_vlan_unregister(if_ctx_t, u16); 419 static void em_if_watchdog_reset(if_ctx_t); 420 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 421 422 static void em_identify_hardware(if_ctx_t); 423 static int em_allocate_pci_resources(if_ctx_t); 424 static void em_free_pci_resources(if_ctx_t); 425 static void em_reset(if_ctx_t); 426 static int em_setup_interface(if_ctx_t); 427 static int em_setup_msix(if_ctx_t); 428 429 static void em_initialize_transmit_unit(if_ctx_t); 430 static void em_initialize_receive_unit(if_ctx_t); 431 432 static void em_if_intr_enable(if_ctx_t); 433 static void em_if_intr_disable(if_ctx_t); 434 static void igb_if_intr_enable(if_ctx_t); 435 static void igb_if_intr_disable(if_ctx_t); 436 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 437 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 440 static void em_if_multi_set(if_ctx_t); 441 static void em_if_update_admin_status(if_ctx_t); 442 static void em_if_debug(if_ctx_t); 443 static void em_update_stats_counters(struct e1000_softc *); 444 static void em_add_hw_stats(struct e1000_softc *); 445 static int em_if_set_promisc(if_ctx_t, int); 446 static bool em_if_vlan_filter_capable(if_ctx_t); 447 static bool em_if_vlan_filter_used(if_ctx_t); 448 static void em_if_vlan_filter_enable(struct e1000_softc *); 449 static void em_if_vlan_filter_disable(struct e1000_softc *); 450 static void em_if_vlan_filter_write(struct e1000_softc *); 451 static void em_setup_vlan_hw_support(if_ctx_t ctx); 452 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 453 static void em_print_nvm_info(struct e1000_softc *); 454 static void em_fw_version_locked(if_ctx_t); 455 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 456 static void em_print_fw_version(struct e1000_softc *); 457 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 458 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 459 static int em_get_rs(SYSCTL_HANDLER_ARGS); 460 static void em_print_debug_info(struct e1000_softc *); 461 static int em_is_valid_ether_addr(u8 *); 462 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 463 struct tx_ring *, struct rx_ring *); 464 static bool em_automask_tso(if_ctx_t); 465 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 466 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 467 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 468 const char *, struct em_int_delay_info *, int, int); 469 /* Management and WOL Support */ 470 static void em_init_manageability(struct e1000_softc *); 471 static void em_release_manageability(struct e1000_softc *); 472 static void em_get_hw_control(struct e1000_softc *); 473 static void em_release_hw_control(struct e1000_softc *); 474 static void em_get_wakeup(if_ctx_t); 475 static void em_enable_wakeup(if_ctx_t); 476 static int em_enable_phy_wakeup(struct e1000_softc *); 477 static void em_disable_aspm(struct e1000_softc *); 478 479 int em_intr(void *); 480 481 /* MSI-X handlers */ 482 static int em_if_msix_intr_assign(if_ctx_t, int); 483 static int em_msix_link(void *); 484 static void em_handle_link(void *); 485 486 static void em_enable_vectors_82574(if_ctx_t); 487 488 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 489 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 490 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 491 static void em_if_led_func(if_ctx_t, int); 492 493 static int em_get_regs(SYSCTL_HANDLER_ARGS); 494 495 static void lem_smartspeed(struct e1000_softc *); 496 static void igb_configure_queues(struct e1000_softc *); 497 static void em_flush_desc_rings(struct e1000_softc *); 498 499 500 /********************************************************************* 501 * FreeBSD Device Interface Entry Points 502 *********************************************************************/ 503 static device_method_t em_methods[] = { 504 /* Device interface */ 505 DEVMETHOD(device_register, em_register), 506 DEVMETHOD(device_probe, iflib_device_probe), 507 DEVMETHOD(device_attach, iflib_device_attach), 508 DEVMETHOD(device_detach, iflib_device_detach), 509 DEVMETHOD(device_shutdown, iflib_device_shutdown), 510 DEVMETHOD(device_suspend, iflib_device_suspend), 511 DEVMETHOD(device_resume, iflib_device_resume), 512 DEVMETHOD_END 513 }; 514 515 static device_method_t igb_methods[] = { 516 /* Device interface */ 517 DEVMETHOD(device_register, igb_register), 518 DEVMETHOD(device_probe, iflib_device_probe), 519 DEVMETHOD(device_attach, iflib_device_attach), 520 DEVMETHOD(device_detach, iflib_device_detach), 521 DEVMETHOD(device_shutdown, iflib_device_shutdown), 522 DEVMETHOD(device_suspend, iflib_device_suspend), 523 DEVMETHOD(device_resume, iflib_device_resume), 524 DEVMETHOD_END 525 }; 526 527 528 static driver_t em_driver = { 529 "em", em_methods, sizeof(struct e1000_softc), 530 }; 531 532 DRIVER_MODULE(em, pci, em_driver, 0, 0); 533 534 MODULE_DEPEND(em, pci, 1, 1, 1); 535 MODULE_DEPEND(em, ether, 1, 1, 1); 536 MODULE_DEPEND(em, iflib, 1, 1, 1); 537 538 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 539 540 static driver_t igb_driver = { 541 "igb", igb_methods, sizeof(struct e1000_softc), 542 }; 543 544 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 545 546 MODULE_DEPEND(igb, pci, 1, 1, 1); 547 MODULE_DEPEND(igb, ether, 1, 1, 1); 548 MODULE_DEPEND(igb, iflib, 1, 1, 1); 549 550 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 551 552 static device_method_t em_if_methods[] = { 553 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 554 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 555 DEVMETHOD(ifdi_detach, em_if_detach), 556 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 557 DEVMETHOD(ifdi_suspend, em_if_suspend), 558 DEVMETHOD(ifdi_resume, em_if_resume), 559 DEVMETHOD(ifdi_init, em_if_init), 560 DEVMETHOD(ifdi_stop, em_if_stop), 561 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 562 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 563 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 564 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 565 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 566 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 567 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 568 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 569 DEVMETHOD(ifdi_media_status, em_if_media_status), 570 DEVMETHOD(ifdi_media_change, em_if_media_change), 571 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 572 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 573 DEVMETHOD(ifdi_timer, em_if_timer), 574 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 575 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 576 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 577 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 578 DEVMETHOD(ifdi_led_func, em_if_led_func), 579 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 580 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 581 DEVMETHOD(ifdi_debug, em_if_debug), 582 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 583 DEVMETHOD_END 584 }; 585 586 static driver_t em_if_driver = { 587 "em_if", em_if_methods, sizeof(struct e1000_softc) 588 }; 589 590 static device_method_t igb_if_methods[] = { 591 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 592 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 593 DEVMETHOD(ifdi_detach, em_if_detach), 594 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 595 DEVMETHOD(ifdi_suspend, em_if_suspend), 596 DEVMETHOD(ifdi_resume, em_if_resume), 597 DEVMETHOD(ifdi_init, em_if_init), 598 DEVMETHOD(ifdi_stop, em_if_stop), 599 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 600 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 601 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 602 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 603 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 604 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 605 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 606 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 607 DEVMETHOD(ifdi_media_status, em_if_media_status), 608 DEVMETHOD(ifdi_media_change, em_if_media_change), 609 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 610 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 611 DEVMETHOD(ifdi_timer, em_if_timer), 612 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 613 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 614 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 615 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 616 DEVMETHOD(ifdi_led_func, em_if_led_func), 617 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 618 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 619 DEVMETHOD(ifdi_debug, em_if_debug), 620 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 621 DEVMETHOD_END 622 }; 623 624 static driver_t igb_if_driver = { 625 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 626 }; 627 628 /********************************************************************* 629 * Tunable default values. 630 *********************************************************************/ 631 632 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 633 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 634 635 /* Allow common code without TSO */ 636 #ifndef CSUM_TSO 637 #define CSUM_TSO 0 638 #endif 639 640 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 641 "EM driver parameters"); 642 643 static int em_disable_crc_stripping = 0; 644 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 645 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 646 647 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 648 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 649 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 650 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 651 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 652 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 653 654 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 655 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 656 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 657 &em_tx_abs_int_delay_dflt, 0, 658 "Default transmit interrupt delay limit in usecs"); 659 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 660 &em_rx_abs_int_delay_dflt, 0, 661 "Default receive interrupt delay limit in usecs"); 662 663 static int em_smart_pwr_down = false; 664 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 665 &em_smart_pwr_down, 666 0, "Set to true to leave smart power down enabled on newer adapters"); 667 668 static bool em_unsupported_tso = false; 669 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 670 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 671 672 /* Controls whether promiscuous also shows bad packets */ 673 static int em_debug_sbp = false; 674 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 675 "Show bad packets in promiscuous mode"); 676 677 /* Energy efficient ethernet - default to OFF */ 678 static int eee_setting = 1; 679 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 680 "Enable Energy Efficient Ethernet"); 681 682 /* 683 * AIM: Adaptive Interrupt Moderation 684 * which means that the interrupt rate is varied over time based on the 685 * traffic for that interrupt vector 686 */ 687 static int em_enable_aim = 1; 688 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 689 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 690 691 /* 692 ** Tuneable Interrupt rate 693 */ 694 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 695 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 696 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 697 698 /* Global used in WOL setup with multiport cards */ 699 static int global_quad_port_a = 0; 700 701 extern struct if_txrx igb_txrx; 702 extern struct if_txrx em_txrx; 703 extern struct if_txrx lem_txrx; 704 705 static struct if_shared_ctx em_sctx_init = { 706 .isc_magic = IFLIB_MAGIC, 707 .isc_q_align = PAGE_SIZE, 708 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 709 .isc_tx_maxsegsize = PAGE_SIZE, 710 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 711 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 712 .isc_rx_maxsize = MJUM9BYTES, 713 .isc_rx_nsegments = 1, 714 .isc_rx_maxsegsize = MJUM9BYTES, 715 .isc_nfl = 1, 716 .isc_nrxqs = 1, 717 .isc_ntxqs = 1, 718 .isc_admin_intrcnt = 1, 719 .isc_vendor_info = em_vendor_info_array, 720 .isc_driver_version = em_driver_version, 721 .isc_driver = &em_if_driver, 722 .isc_flags = 723 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 724 725 .isc_nrxd_min = {EM_MIN_RXD}, 726 .isc_ntxd_min = {EM_MIN_TXD}, 727 .isc_nrxd_max = {EM_MAX_RXD}, 728 .isc_ntxd_max = {EM_MAX_TXD}, 729 .isc_nrxd_default = {EM_DEFAULT_RXD}, 730 .isc_ntxd_default = {EM_DEFAULT_TXD}, 731 }; 732 733 static struct if_shared_ctx igb_sctx_init = { 734 .isc_magic = IFLIB_MAGIC, 735 .isc_q_align = PAGE_SIZE, 736 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 737 .isc_tx_maxsegsize = PAGE_SIZE, 738 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 739 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 740 .isc_rx_maxsize = MJUM9BYTES, 741 .isc_rx_nsegments = 1, 742 .isc_rx_maxsegsize = MJUM9BYTES, 743 .isc_nfl = 1, 744 .isc_nrxqs = 1, 745 .isc_ntxqs = 1, 746 .isc_admin_intrcnt = 1, 747 .isc_vendor_info = igb_vendor_info_array, 748 .isc_driver_version = igb_driver_version, 749 .isc_driver = &igb_if_driver, 750 .isc_flags = 751 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 752 753 .isc_nrxd_min = {EM_MIN_RXD}, 754 .isc_ntxd_min = {EM_MIN_TXD}, 755 .isc_nrxd_max = {IGB_MAX_RXD}, 756 .isc_ntxd_max = {IGB_MAX_TXD}, 757 .isc_nrxd_default = {EM_DEFAULT_RXD}, 758 .isc_ntxd_default = {EM_DEFAULT_TXD}, 759 }; 760 761 /***************************************************************** 762 * 763 * Dump Registers 764 * 765 ****************************************************************/ 766 #define IGB_REGS_LEN 739 767 768 static int em_get_regs(SYSCTL_HANDLER_ARGS) 769 { 770 struct e1000_softc *sc = (struct e1000_softc *)arg1; 771 struct e1000_hw *hw = &sc->hw; 772 struct sbuf *sb; 773 u32 *regs_buff; 774 int rc; 775 776 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 777 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 778 779 rc = sysctl_wire_old_buffer(req, 0); 780 MPASS(rc == 0); 781 if (rc != 0) { 782 free(regs_buff, M_DEVBUF); 783 return (rc); 784 } 785 786 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 787 MPASS(sb != NULL); 788 if (sb == NULL) { 789 free(regs_buff, M_DEVBUF); 790 return (ENOMEM); 791 } 792 793 /* General Registers */ 794 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 795 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 796 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 797 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 798 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 799 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 800 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 801 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 802 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 803 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 804 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 805 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 806 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 807 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 808 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 809 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 810 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 811 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 812 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 813 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 814 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 815 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 816 817 sbuf_printf(sb, "General Registers\n"); 818 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 819 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 820 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 821 822 sbuf_printf(sb, "Interrupt Registers\n"); 823 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 824 825 sbuf_printf(sb, "RX Registers\n"); 826 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 827 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 828 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 829 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 830 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 831 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 832 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 833 834 sbuf_printf(sb, "TX Registers\n"); 835 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 836 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 837 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 838 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 839 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 840 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 841 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 842 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 843 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 844 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 845 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 846 847 free(regs_buff, M_DEVBUF); 848 849 #ifdef DUMP_DESCS 850 { 851 if_softc_ctx_t scctx = sc->shared; 852 struct rx_ring *rxr = &rx_que->rxr; 853 struct tx_ring *txr = &tx_que->txr; 854 int ntxd = scctx->isc_ntxd[0]; 855 int nrxd = scctx->isc_nrxd[0]; 856 int j; 857 858 for (j = 0; j < nrxd; j++) { 859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 861 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 862 PRIx64 " Error:%d Length:%d\n", 863 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 864 } 865 866 for (j = 0; j < min(ntxd, 256); j++) { 867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 868 869 sbuf_printf(sb, 870 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 871 " eop: %d DD=%d\n", 872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 873 buf->eop != -1 ? 874 txr->tx_base[buf->eop].upper.fields.status & 875 E1000_TXD_STAT_DD : 0); 876 877 } 878 } 879 #endif 880 881 rc = sbuf_finish(sb); 882 sbuf_delete(sb); 883 return(rc); 884 } 885 886 static void * 887 em_register(device_t dev) 888 { 889 return (&em_sctx_init); 890 } 891 892 static void * 893 igb_register(device_t dev) 894 { 895 return (&igb_sctx_init); 896 } 897 898 static int 899 em_set_num_queues(if_ctx_t ctx) 900 { 901 struct e1000_softc *sc = iflib_get_softc(ctx); 902 int maxqueues; 903 904 /* Sanity check based on HW */ 905 switch (sc->hw.mac.type) { 906 case e1000_82576: 907 case e1000_82580: 908 case e1000_i350: 909 case e1000_i354: 910 maxqueues = 8; 911 break; 912 case e1000_i210: 913 case e1000_82575: 914 maxqueues = 4; 915 break; 916 case e1000_i211: 917 case e1000_82574: 918 maxqueues = 2; 919 break; 920 default: 921 maxqueues = 1; 922 break; 923 } 924 925 return (maxqueues); 926 } 927 928 #define LEM_CAPS \ 929 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 930 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 931 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 932 933 #define EM_CAPS \ 934 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 935 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 936 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 937 IFCAP_TSO6 938 939 #define IGB_CAPS \ 940 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 941 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 942 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 943 IFCAP_TSO6 944 945 /********************************************************************* 946 * Device initialization routine 947 * 948 * The attach entry point is called when the driver is being loaded. 949 * This routine identifies the type of hardware, allocates all resources 950 * and initializes the hardware. 951 * 952 * return 0 on success, positive on failure 953 *********************************************************************/ 954 static int 955 em_if_attach_pre(if_ctx_t ctx) 956 { 957 struct e1000_softc *sc; 958 if_softc_ctx_t scctx; 959 device_t dev; 960 struct e1000_hw *hw; 961 struct sysctl_oid_list *child; 962 struct sysctl_ctx_list *ctx_list; 963 int error = 0; 964 965 INIT_DEBUGOUT("em_if_attach_pre: begin"); 966 dev = iflib_get_dev(ctx); 967 sc = iflib_get_softc(ctx); 968 969 sc->ctx = sc->osdep.ctx = ctx; 970 sc->dev = sc->osdep.dev = dev; 971 scctx = sc->shared = iflib_get_softc_ctx(ctx); 972 sc->media = iflib_get_media(ctx); 973 hw = &sc->hw; 974 975 /* Determine hardware and mac info */ 976 em_identify_hardware(ctx); 977 978 /* SYSCTL stuff */ 979 ctx_list = device_get_sysctl_ctx(dev); 980 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 981 982 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 983 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 984 em_sysctl_nvm_info, "I", "NVM Information"); 985 986 sc->enable_aim = em_enable_aim; 987 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 988 CTLFLAG_RW, &sc->enable_aim, 0, 989 "Interrupt Moderation (1=normal, 2=lowlatency)"); 990 991 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 992 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 993 em_sysctl_print_fw_version, "A", 994 "Prints FW/NVM Versions"); 995 996 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 997 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 998 em_sysctl_debug_info, "I", "Debug Information"); 999 1000 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1002 em_set_flowcntl, "I", "Flow Control"); 1003 1004 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1006 em_get_regs, "A", "Dump Registers"); 1007 1008 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1009 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1010 em_get_rs, "I", "Dump RS indexes"); 1011 1012 if (hw->mac.type >= e1000_i350) { 1013 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1014 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1015 igb_sysctl_dmac, "I", "DMA Coalesce"); 1016 } 1017 1018 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1019 "tso_tcp_flags_mask_first_segment", 1020 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1021 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1022 "TSO TCP flags mask for first segment"); 1023 1024 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1025 "tso_tcp_flags_mask_middle_segment", 1026 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1027 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1028 "TSO TCP flags mask for middle segment"); 1029 1030 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1031 "tso_tcp_flags_mask_last_segment", 1032 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1033 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1034 "TSO TCP flags mask for last segment"); 1035 1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1037 scctx->isc_nrxqsets_max = 1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1039 if (bootverbose) 1040 device_printf(dev, "attach_pre capping queues at %d\n", 1041 scctx->isc_ntxqsets_max); 1042 1043 if (hw->mac.type >= igb_mac_min) { 1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1045 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1047 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1050 scctx->isc_txrx = &igb_txrx; 1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1056 CSUM_IP6_TCP | CSUM_IP6_UDP; 1057 if (hw->mac.type != e1000_82575) 1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1059 /* 1060 ** Some new devices, as with ixgbe, now may 1061 ** use a different BAR, so we need to keep 1062 ** track of which is used. 1063 */ 1064 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1065 } else if (hw->mac.type >= em_mac_min) { 1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1067 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1069 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1072 scctx->isc_txrx = &em_txrx; 1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1078 CSUM_IP6_TCP | CSUM_IP6_UDP; 1079 1080 /* Disable TSO on all em(4) until ring stalls are debugged */ 1081 scctx->isc_capenable &= ~IFCAP_TSO; 1082 1083 /* 1084 * Disable TSO on SPT due to errata that downclocks DMA 1085 * performance 1086 * i218-i219 Specification Update 1.5.4.5 1087 */ 1088 if (hw->mac.type == e1000_pch_spt) 1089 scctx->isc_capenable &= ~IFCAP_TSO; 1090 1091 /* 1092 * We support MSI-X with 82574 only, but indicate to iflib(4) 1093 * that it shall give MSI at least a try with other devices. 1094 */ 1095 if (hw->mac.type == e1000_82574) { 1096 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1097 } else { 1098 scctx->isc_msix_bar = -1; 1099 scctx->isc_disable_msix = 1; 1100 } 1101 } else { 1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1103 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1105 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1108 scctx->isc_txrx = &lem_txrx; 1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1113 if (em_unsupported_tso) 1114 scctx->isc_capabilities |= IFCAP_TSO6; 1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1116 CSUM_IP6_TCP | CSUM_IP6_UDP; 1117 1118 /* Disable TSO on all lem(4) until ring stalls debugged */ 1119 scctx->isc_capenable &= ~IFCAP_TSO; 1120 1121 /* 82541ER doesn't do HW tagging */ 1122 if (hw->device_id == E1000_DEV_ID_82541ER || 1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1125 scctx->isc_capenable = scctx->isc_capabilities; 1126 } 1127 /* This is the first e1000 chip and it does not do offloads */ 1128 if (hw->mac.type == e1000_82542) { 1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1130 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1131 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1132 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1133 scctx->isc_capenable = scctx->isc_capabilities; 1134 } 1135 /* These can't do TSO for various reasons */ 1136 if (hw->mac.type < e1000_82544 || 1137 hw->mac.type == e1000_82547 || 1138 hw->mac.type == e1000_82547_rev_2) { 1139 scctx->isc_capabilities &= 1140 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1141 scctx->isc_capenable = scctx->isc_capabilities; 1142 } 1143 /* XXXKB: No IPv6 before this? */ 1144 if (hw->mac.type < e1000_82545){ 1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1146 scctx->isc_capenable = scctx->isc_capabilities; 1147 } 1148 /* 1149 * "PCI/PCI-X SDM 4.0" page 33 (b): 1150 * FDX requirement on these chips 1151 */ 1152 if (hw->mac.type == e1000_82547 || 1153 hw->mac.type == e1000_82547_rev_2) 1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1155 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1156 1157 /* INTx only */ 1158 scctx->isc_msix_bar = 0; 1159 } 1160 1161 /* Setup PCI resources */ 1162 if (em_allocate_pci_resources(ctx)) { 1163 device_printf(dev, "Allocation of PCI resources failed\n"); 1164 error = ENXIO; 1165 goto err_pci; 1166 } 1167 1168 /* 1169 ** For ICH8 and family we need to 1170 ** map the flash memory, and this 1171 ** must happen after the MAC is 1172 ** identified 1173 */ 1174 if ((hw->mac.type == e1000_ich8lan) || 1175 (hw->mac.type == e1000_ich9lan) || 1176 (hw->mac.type == e1000_ich10lan) || 1177 (hw->mac.type == e1000_pchlan) || 1178 (hw->mac.type == e1000_pch2lan) || 1179 (hw->mac.type == e1000_pch_lpt)) { 1180 int rid = EM_BAR_TYPE_FLASH; 1181 sc->flash = bus_alloc_resource_any(dev, 1182 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1183 if (sc->flash == NULL) { 1184 device_printf(dev, "Mapping of Flash failed\n"); 1185 error = ENXIO; 1186 goto err_pci; 1187 } 1188 /* This is used in the shared code */ 1189 hw->flash_address = (u8 *)sc->flash; 1190 sc->osdep.flash_bus_space_tag = 1191 rman_get_bustag(sc->flash); 1192 sc->osdep.flash_bus_space_handle = 1193 rman_get_bushandle(sc->flash); 1194 } 1195 /* 1196 ** In the new SPT device flash is not a 1197 ** separate BAR, rather it is also in BAR0, 1198 ** so use the same tag and an offset handle for the 1199 ** FLASH read/write macros in the shared code. 1200 */ 1201 else if (hw->mac.type >= e1000_pch_spt) { 1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1203 sc->osdep.flash_bus_space_handle = 1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1205 } 1206 1207 /* Do Shared Code initialization */ 1208 error = e1000_setup_init_funcs(hw, true); 1209 if (error) { 1210 device_printf(dev, "Setup of Shared code failed, error %d\n", 1211 error); 1212 error = ENXIO; 1213 goto err_pci; 1214 } 1215 1216 em_setup_msix(ctx); 1217 e1000_get_bus_info(hw); 1218 1219 /* Set up some sysctls for the tunable interrupt delays */ 1220 if (hw->mac.type < igb_mac_min) { 1221 em_add_int_delay_sysctl(sc, "rx_int_delay", 1222 "receive interrupt delay in usecs", &sc->rx_int_delay, 1223 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1224 em_add_int_delay_sysctl(sc, "tx_int_delay", 1225 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1226 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1227 } 1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1229 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1230 "receive interrupt delay limit in usecs", 1231 &sc->rx_abs_int_delay, 1232 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1233 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1234 "transmit interrupt delay limit in usecs", 1235 &sc->tx_abs_int_delay, 1236 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1237 em_add_int_delay_sysctl(sc, "itr", 1238 "interrupt delay limit in usecs/4", &sc->tx_itr, 1239 E1000_REGISTER(hw, E1000_ITR), 1240 EM_INTS_TO_ITR(em_max_interrupt_rate)); 1241 } 1242 1243 hw->mac.autoneg = DO_AUTO_NEG; 1244 hw->phy.autoneg_wait_to_complete = false; 1245 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1246 1247 if (hw->mac.type < em_mac_min) { 1248 e1000_init_script_state_82541(hw, true); 1249 e1000_set_tbi_compatibility_82543(hw, true); 1250 } 1251 /* Copper options */ 1252 if (hw->phy.media_type == e1000_media_type_copper) { 1253 hw->phy.mdix = AUTO_ALL_MODES; 1254 hw->phy.disable_polarity_correction = false; 1255 hw->phy.ms_type = EM_MASTER_SLAVE; 1256 } 1257 1258 /* 1259 * Set the frame limits assuming 1260 * standard ethernet sized frames. 1261 */ 1262 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1263 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1264 1265 /* 1266 * This controls when hardware reports transmit completion 1267 * status. 1268 */ 1269 hw->mac.report_tx_early = 1; 1270 1271 /* Allocate multicast array memory. */ 1272 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1273 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1274 if (sc->mta == NULL) { 1275 device_printf(dev, 1276 "Can not allocate multicast setup array\n"); 1277 error = ENOMEM; 1278 goto err_late; 1279 } 1280 1281 /* Clear the IFCAP_TSO auto mask */ 1282 sc->tso_automasked = 0; 1283 1284 /* Check SOL/IDER usage */ 1285 if (e1000_check_reset_block(hw)) 1286 device_printf(dev, 1287 "PHY reset is blocked due to SOL/IDER session.\n"); 1288 1289 /* Sysctl for setting Energy Efficient Ethernet */ 1290 if (hw->mac.type < igb_mac_min) 1291 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1292 else 1293 hw->dev_spec._82575.eee_disable = eee_setting; 1294 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1295 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1296 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1297 1298 /* 1299 ** Start from a known state, this is 1300 ** important in reading the nvm and 1301 ** mac from that. 1302 */ 1303 e1000_reset_hw(hw); 1304 1305 /* Make sure we have a good EEPROM before we read from it */ 1306 if (e1000_validate_nvm_checksum(hw) < 0) { 1307 /* 1308 ** Some PCI-E parts fail the first check due to 1309 ** the link being in sleep state, call it again, 1310 ** if it fails a second time its a real issue. 1311 */ 1312 if (e1000_validate_nvm_checksum(hw) < 0) { 1313 device_printf(dev, 1314 "The EEPROM Checksum Is Not Valid\n"); 1315 error = EIO; 1316 goto err_late; 1317 } 1318 } 1319 1320 /* Copy the permanent MAC address out of the EEPROM */ 1321 if (e1000_read_mac_addr(hw) < 0) { 1322 device_printf(dev, 1323 "EEPROM read error while reading MAC address\n"); 1324 error = EIO; 1325 goto err_late; 1326 } 1327 1328 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1329 if (sc->vf_ifp) { 1330 ether_gen_addr(iflib_get_ifp(ctx), 1331 (struct ether_addr *)hw->mac.addr); 1332 } else { 1333 device_printf(dev, "Invalid MAC address\n"); 1334 error = EIO; 1335 goto err_late; 1336 } 1337 } 1338 1339 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1340 em_fw_version_locked(ctx); 1341 1342 em_print_fw_version(sc); 1343 1344 /* 1345 * Get Wake-on-Lan and Management info for later use 1346 */ 1347 em_get_wakeup(ctx); 1348 1349 /* Enable only WOL MAGIC by default */ 1350 scctx->isc_capenable &= ~IFCAP_WOL; 1351 if (sc->wol != 0) 1352 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1353 1354 iflib_set_mac(ctx, hw->mac.addr); 1355 1356 return (0); 1357 1358 err_late: 1359 em_release_hw_control(sc); 1360 err_pci: 1361 em_free_pci_resources(ctx); 1362 free(sc->mta, M_DEVBUF); 1363 1364 return (error); 1365 } 1366 1367 static int 1368 em_if_attach_post(if_ctx_t ctx) 1369 { 1370 struct e1000_softc *sc = iflib_get_softc(ctx); 1371 struct e1000_hw *hw = &sc->hw; 1372 int error = 0; 1373 1374 /* Setup OS specific network interface */ 1375 error = em_setup_interface(ctx); 1376 if (error != 0) { 1377 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1378 goto err_late; 1379 } 1380 1381 em_reset(ctx); 1382 1383 /* Initialize statistics */ 1384 em_update_stats_counters(sc); 1385 hw->mac.get_link_status = 1; 1386 em_if_update_admin_status(ctx); 1387 em_add_hw_stats(sc); 1388 1389 /* Non-AMT based hardware can now take control from firmware */ 1390 if (sc->has_manage && !sc->has_amt) 1391 em_get_hw_control(sc); 1392 1393 INIT_DEBUGOUT("em_if_attach_post: end"); 1394 1395 return (0); 1396 1397 err_late: 1398 /* 1399 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1400 * free resources 1401 */ 1402 return (error); 1403 } 1404 1405 /********************************************************************* 1406 * Device removal routine 1407 * 1408 * The detach entry point is called when the driver is being removed. 1409 * This routine stops the adapter and deallocates all the resources 1410 * that were allocated for driver operation. 1411 * 1412 * return 0 on success, positive on failure 1413 *********************************************************************/ 1414 static int 1415 em_if_detach(if_ctx_t ctx) 1416 { 1417 struct e1000_softc *sc = iflib_get_softc(ctx); 1418 1419 INIT_DEBUGOUT("em_if_detach: begin"); 1420 1421 e1000_phy_hw_reset(&sc->hw); 1422 1423 em_release_manageability(sc); 1424 em_release_hw_control(sc); 1425 em_free_pci_resources(ctx); 1426 free(sc->mta, M_DEVBUF); 1427 sc->mta = NULL; 1428 1429 return (0); 1430 } 1431 1432 /********************************************************************* 1433 * 1434 * Shutdown entry point 1435 * 1436 **********************************************************************/ 1437 1438 static int 1439 em_if_shutdown(if_ctx_t ctx) 1440 { 1441 return em_if_suspend(ctx); 1442 } 1443 1444 /* 1445 * Suspend/resume device methods. 1446 */ 1447 static int 1448 em_if_suspend(if_ctx_t ctx) 1449 { 1450 struct e1000_softc *sc = iflib_get_softc(ctx); 1451 1452 em_release_manageability(sc); 1453 em_release_hw_control(sc); 1454 em_enable_wakeup(ctx); 1455 return (0); 1456 } 1457 1458 static int 1459 em_if_resume(if_ctx_t ctx) 1460 { 1461 struct e1000_softc *sc = iflib_get_softc(ctx); 1462 1463 if (sc->hw.mac.type == e1000_pch2lan) 1464 e1000_resume_workarounds_pchlan(&sc->hw); 1465 em_if_init(ctx); 1466 em_init_manageability(sc); 1467 1468 return(0); 1469 } 1470 1471 static int 1472 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1473 { 1474 int max_frame_size; 1475 struct e1000_softc *sc = iflib_get_softc(ctx); 1476 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1477 1478 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1479 1480 switch (sc->hw.mac.type) { 1481 case e1000_82571: 1482 case e1000_82572: 1483 case e1000_ich9lan: 1484 case e1000_ich10lan: 1485 case e1000_pch2lan: 1486 case e1000_pch_lpt: 1487 case e1000_pch_spt: 1488 case e1000_pch_cnp: 1489 case e1000_pch_tgp: 1490 case e1000_pch_adp: 1491 case e1000_pch_mtp: 1492 case e1000_pch_ptp: 1493 case e1000_82574: 1494 case e1000_82583: 1495 case e1000_80003es2lan: 1496 /* 9K Jumbo Frame size */ 1497 max_frame_size = 9234; 1498 break; 1499 case e1000_pchlan: 1500 max_frame_size = 4096; 1501 break; 1502 case e1000_82542: 1503 case e1000_ich8lan: 1504 /* Adapters that do not support jumbo frames */ 1505 max_frame_size = ETHER_MAX_LEN; 1506 break; 1507 default: 1508 if (sc->hw.mac.type >= igb_mac_min) 1509 max_frame_size = 9234; 1510 else /* lem */ 1511 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1512 } 1513 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1514 return (EINVAL); 1515 } 1516 1517 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1518 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1519 return (0); 1520 } 1521 1522 /********************************************************************* 1523 * Init entry point 1524 * 1525 * This routine is used in two ways. It is used by the stack as 1526 * init entry point in network interface structure. It is also used 1527 * by the driver as a hw/sw initialization routine to get to a 1528 * consistent state. 1529 * 1530 **********************************************************************/ 1531 static void 1532 em_if_init(if_ctx_t ctx) 1533 { 1534 struct e1000_softc *sc = iflib_get_softc(ctx); 1535 if_softc_ctx_t scctx = sc->shared; 1536 if_t ifp = iflib_get_ifp(ctx); 1537 struct em_tx_queue *tx_que; 1538 int i; 1539 1540 INIT_DEBUGOUT("em_if_init: begin"); 1541 1542 /* Get the latest mac address, User can use a LAA */ 1543 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1544 1545 /* Put the address into the Receive Address Array */ 1546 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1547 1548 /* 1549 * With the 82571 adapter, RAR[0] may be overwritten 1550 * when the other port is reset, we make a duplicate 1551 * in RAR[14] for that eventuality, this assures 1552 * the interface continues to function. 1553 */ 1554 if (sc->hw.mac.type == e1000_82571) { 1555 e1000_set_laa_state_82571(&sc->hw, true); 1556 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1557 E1000_RAR_ENTRIES - 1); 1558 } 1559 1560 /* Initialize the hardware */ 1561 em_reset(ctx); 1562 em_if_update_admin_status(ctx); 1563 1564 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1565 i++, tx_que++) { 1566 struct tx_ring *txr = &tx_que->txr; 1567 1568 txr->tx_rs_cidx = txr->tx_rs_pidx; 1569 1570 /* Initialize the last processed descriptor to be the end of 1571 * the ring, rather than the start, so that we avoid an 1572 * off-by-one error when calculating how many descriptors are 1573 * done in the credits_update function. 1574 */ 1575 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1576 } 1577 1578 /* Setup VLAN support, basic and offload if available */ 1579 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1580 1581 /* Clear bad data from Rx FIFOs */ 1582 if (sc->hw.mac.type >= igb_mac_min) 1583 e1000_rx_fifo_flush_base(&sc->hw); 1584 1585 /* Configure for OS presence */ 1586 em_init_manageability(sc); 1587 1588 /* Prepare transmit descriptors and buffers */ 1589 em_initialize_transmit_unit(ctx); 1590 1591 /* Setup Multicast table */ 1592 em_if_multi_set(ctx); 1593 1594 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1595 em_initialize_receive_unit(ctx); 1596 1597 /* Set up VLAN support and filter */ 1598 em_setup_vlan_hw_support(ctx); 1599 1600 /* Don't lose promiscuous settings */ 1601 em_if_set_promisc(ctx, if_getflags(ifp)); 1602 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1603 1604 /* MSI-X configuration for 82574 */ 1605 if (sc->hw.mac.type == e1000_82574) { 1606 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1607 1608 tmp |= E1000_CTRL_EXT_PBA_CLR; 1609 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1610 /* Set the IVAR - interrupt vector routing. */ 1611 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1612 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1613 /* Set up queue routing */ 1614 igb_configure_queues(sc); 1615 } 1616 1617 /* this clears any pending interrupts */ 1618 E1000_READ_REG(&sc->hw, E1000_ICR); 1619 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1620 1621 /* AMT based hardware can now take control from firmware */ 1622 if (sc->has_manage && sc->has_amt) 1623 em_get_hw_control(sc); 1624 1625 /* Set Energy Efficient Ethernet */ 1626 if (sc->hw.mac.type >= igb_mac_min && 1627 sc->hw.phy.media_type == e1000_media_type_copper) { 1628 if (sc->hw.mac.type == e1000_i354) 1629 e1000_set_eee_i354(&sc->hw, true, true); 1630 else 1631 e1000_set_eee_i350(&sc->hw, true, true); 1632 } 1633 } 1634 1635 enum itr_latency_target { 1636 itr_latency_disabled = 0, 1637 itr_latency_lowest = 1, 1638 itr_latency_low = 2, 1639 itr_latency_bulk = 3 1640 }; 1641 /********************************************************************* 1642 * 1643 * Helper to calculate next (E)ITR value for AIM 1644 * 1645 *********************************************************************/ 1646 static void 1647 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1648 struct tx_ring *txr, struct rx_ring *rxr) 1649 { 1650 struct e1000_hw *hw = &sc->hw; 1651 u32 newitr; 1652 u32 bytes; 1653 u32 bytes_packets; 1654 u32 packets; 1655 u8 nextlatency; 1656 1657 /* Idle, do nothing */ 1658 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0)) 1659 return; 1660 1661 newitr = 0; 1662 1663 if (sc->enable_aim) { 1664 nextlatency = rxr->rx_nextlatency; 1665 1666 /* Use half default (4K) ITR if sub-gig */ 1667 if (sc->link_speed != 1000) { 1668 newitr = EM_INTS_4K; 1669 goto em_set_next_itr; 1670 } 1671 /* Want at least enough packet buffer for two frames to AIM */ 1672 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1673 newitr = em_max_interrupt_rate; 1674 sc->enable_aim = 0; 1675 goto em_set_next_itr; 1676 } 1677 1678 /* Get largest values from the associated tx and rx ring */ 1679 if (txr->tx_bytes && txr->tx_packets) { 1680 bytes = txr->tx_bytes; 1681 bytes_packets = txr->tx_bytes/txr->tx_packets; 1682 packets = txr->tx_packets; 1683 } 1684 if (rxr->rx_bytes && rxr->rx_packets) { 1685 bytes = max(bytes, rxr->rx_bytes); 1686 bytes_packets = 1687 max(bytes_packets, rxr->rx_bytes/rxr->rx_packets); 1688 packets = max(packets, rxr->rx_packets); 1689 } 1690 1691 /* Latency state machine */ 1692 switch (nextlatency) { 1693 case itr_latency_disabled: /* Bootstrapping */ 1694 nextlatency = itr_latency_low; 1695 break; 1696 case itr_latency_lowest: /* 70k ints/s */ 1697 /* TSO and jumbo frames */ 1698 if (bytes_packets > 8000) 1699 nextlatency = itr_latency_bulk; 1700 else if ((packets < 5) && (bytes > 512)) 1701 nextlatency = itr_latency_low; 1702 break; 1703 case itr_latency_low: /* 20k ints/s */ 1704 if (bytes > 10000) { 1705 /* Handle TSO */ 1706 if (bytes_packets > 8000) 1707 nextlatency = itr_latency_bulk; 1708 else if ((packets < 10) || 1709 (bytes_packets > 1200)) 1710 nextlatency = itr_latency_bulk; 1711 else if (packets > 35) 1712 nextlatency = itr_latency_lowest; 1713 } else if (bytes_packets > 2000) { 1714 nextlatency = itr_latency_bulk; 1715 } else if (packets < 3 && bytes < 512) { 1716 nextlatency = itr_latency_lowest; 1717 } 1718 break; 1719 case itr_latency_bulk: /* 4k ints/s */ 1720 if (bytes > 25000) { 1721 if (packets > 35) 1722 nextlatency = itr_latency_low; 1723 } else if (bytes < 1500) 1724 nextlatency = itr_latency_low; 1725 break; 1726 default: 1727 nextlatency = itr_latency_low; 1728 device_printf(sc->dev, 1729 "Unexpected newitr transition %d\n", nextlatency); 1730 break; 1731 } 1732 1733 /* Trim itr_latency_lowest for default AIM setting */ 1734 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1735 nextlatency = itr_latency_low; 1736 1737 /* Request new latency */ 1738 rxr->rx_nextlatency = nextlatency; 1739 } else { 1740 /* We may have toggled to AIM disabled */ 1741 nextlatency = itr_latency_disabled; 1742 rxr->rx_nextlatency = nextlatency; 1743 } 1744 1745 /* ITR state machine */ 1746 switch(nextlatency) { 1747 case itr_latency_lowest: 1748 newitr = EM_INTS_70K; 1749 break; 1750 case itr_latency_low: 1751 newitr = EM_INTS_20K; 1752 break; 1753 case itr_latency_bulk: 1754 newitr = EM_INTS_4K; 1755 break; 1756 case itr_latency_disabled: 1757 default: 1758 newitr = em_max_interrupt_rate; 1759 break; 1760 } 1761 1762 em_set_next_itr: 1763 if (hw->mac.type >= igb_mac_min) { 1764 newitr = IGB_INTS_TO_EITR(newitr); 1765 1766 if (hw->mac.type == e1000_82575) 1767 newitr |= newitr << 16; 1768 else 1769 newitr |= E1000_EITR_CNT_IGNR; 1770 1771 if (newitr != que->itr_setting) { 1772 que->itr_setting = newitr; 1773 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1774 que->itr_setting); 1775 } 1776 } else { 1777 newitr = EM_INTS_TO_ITR(newitr); 1778 1779 if (newitr != que->itr_setting) { 1780 que->itr_setting = newitr; 1781 if (hw->mac.type == e1000_82574 && que->msix) { 1782 E1000_WRITE_REG(hw, 1783 E1000_EITR_82574(que->msix), 1784 que->itr_setting); 1785 } else { 1786 E1000_WRITE_REG(hw, E1000_ITR, 1787 que->itr_setting); 1788 } 1789 } 1790 } 1791 } 1792 1793 /********************************************************************* 1794 * 1795 * Fast Legacy/MSI Combined Interrupt Service routine 1796 * 1797 *********************************************************************/ 1798 int 1799 em_intr(void *arg) 1800 { 1801 struct e1000_softc *sc = arg; 1802 struct e1000_hw *hw = &sc->hw; 1803 struct em_rx_queue *que = &sc->rx_queues[0]; 1804 struct tx_ring *txr = &sc->tx_queues[0].txr; 1805 struct rx_ring *rxr = &que->rxr; 1806 if_ctx_t ctx = sc->ctx; 1807 u32 reg_icr; 1808 1809 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1810 1811 /* Hot eject? */ 1812 if (reg_icr == 0xffffffff) 1813 return FILTER_STRAY; 1814 1815 /* Definitely not our interrupt. */ 1816 if (reg_icr == 0x0) 1817 return FILTER_STRAY; 1818 1819 /* 1820 * Starting with the 82571 chip, bit 31 should be used to 1821 * determine whether the interrupt belongs to us. 1822 */ 1823 if (hw->mac.type >= e1000_82571 && 1824 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1825 return FILTER_STRAY; 1826 1827 /* 1828 * Only MSI-X interrupts have one-shot behavior by taking advantage 1829 * of the EIAC register. Thus, explicitly disable interrupts. This 1830 * also works around the MSI message reordering errata on certain 1831 * systems. 1832 */ 1833 IFDI_INTR_DISABLE(ctx); 1834 1835 /* Link status change */ 1836 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1837 em_handle_link(ctx); 1838 1839 if (reg_icr & E1000_ICR_RXO) 1840 sc->rx_overruns++; 1841 1842 if (hw->mac.type >= e1000_82540) 1843 em_newitr(sc, que, txr, rxr); 1844 1845 /* Reset state */ 1846 txr->tx_bytes = 0; 1847 txr->tx_packets = 0; 1848 rxr->rx_bytes = 0; 1849 rxr->rx_packets = 0; 1850 1851 return (FILTER_SCHEDULE_THREAD); 1852 } 1853 1854 static int 1855 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1856 { 1857 struct e1000_softc *sc = iflib_get_softc(ctx); 1858 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1859 1860 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1861 return (0); 1862 } 1863 1864 static int 1865 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1866 { 1867 struct e1000_softc *sc = iflib_get_softc(ctx); 1868 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1869 1870 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1871 return (0); 1872 } 1873 1874 static int 1875 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1876 { 1877 struct e1000_softc *sc = iflib_get_softc(ctx); 1878 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1879 1880 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1881 return (0); 1882 } 1883 1884 static int 1885 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1886 { 1887 struct e1000_softc *sc = iflib_get_softc(ctx); 1888 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1889 1890 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1891 return (0); 1892 } 1893 1894 /********************************************************************* 1895 * 1896 * MSI-X RX Interrupt Service routine 1897 * 1898 **********************************************************************/ 1899 static int 1900 em_msix_que(void *arg) 1901 { 1902 struct em_rx_queue *que = arg; 1903 struct e1000_softc *sc = que->sc; 1904 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1905 struct rx_ring *rxr = &que->rxr; 1906 1907 ++que->irqs; 1908 1909 em_newitr(sc, que, txr, rxr); 1910 1911 /* Reset state */ 1912 txr->tx_bytes = 0; 1913 txr->tx_packets = 0; 1914 rxr->rx_bytes = 0; 1915 rxr->rx_packets = 0; 1916 1917 return (FILTER_SCHEDULE_THREAD); 1918 } 1919 1920 /********************************************************************* 1921 * 1922 * MSI-X Link Fast Interrupt Service routine 1923 * 1924 **********************************************************************/ 1925 static int 1926 em_msix_link(void *arg) 1927 { 1928 struct e1000_softc *sc = arg; 1929 u32 reg_icr; 1930 1931 ++sc->link_irq; 1932 MPASS(sc->hw.back != NULL); 1933 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1934 1935 if (reg_icr & E1000_ICR_RXO) 1936 sc->rx_overruns++; 1937 1938 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1939 em_handle_link(sc->ctx); 1940 1941 /* Re-arm unconditionally */ 1942 if (sc->hw.mac.type >= igb_mac_min) { 1943 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1944 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1945 } else if (sc->hw.mac.type == e1000_82574) { 1946 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1947 E1000_IMS_LSC | E1000_IMS_OTHER); 1948 /* 1949 * Because we must read the ICR for this interrupt it may 1950 * clear other causes using autoclear, for this reason we 1951 * simply create a soft interrupt for all these vectors. 1952 */ 1953 if (reg_icr) 1954 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1955 } else 1956 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1957 1958 return (FILTER_HANDLED); 1959 } 1960 1961 static void 1962 em_handle_link(void *context) 1963 { 1964 if_ctx_t ctx = context; 1965 struct e1000_softc *sc = iflib_get_softc(ctx); 1966 1967 sc->hw.mac.get_link_status = 1; 1968 iflib_admin_intr_deferred(ctx); 1969 } 1970 1971 /********************************************************************* 1972 * 1973 * Media Ioctl callback 1974 * 1975 * This routine is called whenever the user queries the status of 1976 * the interface using ifconfig. 1977 * 1978 **********************************************************************/ 1979 static void 1980 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1981 { 1982 struct e1000_softc *sc = iflib_get_softc(ctx); 1983 u_char fiber_type = IFM_1000_SX; 1984 1985 INIT_DEBUGOUT("em_if_media_status: begin"); 1986 1987 iflib_admin_intr_deferred(ctx); 1988 1989 ifmr->ifm_status = IFM_AVALID; 1990 ifmr->ifm_active = IFM_ETHER; 1991 1992 if (!sc->link_active) { 1993 return; 1994 } 1995 1996 ifmr->ifm_status |= IFM_ACTIVE; 1997 1998 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1999 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2000 if (sc->hw.mac.type == e1000_82545) 2001 fiber_type = IFM_1000_LX; 2002 switch (sc->link_speed) { 2003 case 10: 2004 ifmr->ifm_active |= IFM_10_FL; 2005 break; 2006 case 100: 2007 ifmr->ifm_active |= IFM_100_FX; 2008 break; 2009 case 1000: 2010 default: 2011 ifmr->ifm_active |= fiber_type | IFM_FDX; 2012 break; 2013 } 2014 } else { 2015 switch (sc->link_speed) { 2016 case 10: 2017 ifmr->ifm_active |= IFM_10_T; 2018 break; 2019 case 100: 2020 ifmr->ifm_active |= IFM_100_TX; 2021 break; 2022 case 1000: 2023 ifmr->ifm_active |= IFM_1000_T; 2024 break; 2025 } 2026 } 2027 2028 if (sc->link_duplex == FULL_DUPLEX) 2029 ifmr->ifm_active |= IFM_FDX; 2030 else 2031 ifmr->ifm_active |= IFM_HDX; 2032 } 2033 2034 /********************************************************************* 2035 * 2036 * Media Ioctl callback 2037 * 2038 * This routine is called when the user changes speed/duplex using 2039 * media/mediopt option with ifconfig. 2040 * 2041 **********************************************************************/ 2042 static int 2043 em_if_media_change(if_ctx_t ctx) 2044 { 2045 struct e1000_softc *sc = iflib_get_softc(ctx); 2046 struct ifmedia *ifm = iflib_get_media(ctx); 2047 2048 INIT_DEBUGOUT("em_if_media_change: begin"); 2049 2050 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2051 return (EINVAL); 2052 2053 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2054 case IFM_AUTO: 2055 sc->hw.mac.autoneg = DO_AUTO_NEG; 2056 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2057 break; 2058 case IFM_1000_LX: 2059 case IFM_1000_SX: 2060 case IFM_1000_T: 2061 sc->hw.mac.autoneg = DO_AUTO_NEG; 2062 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2063 break; 2064 case IFM_100_TX: 2065 sc->hw.mac.autoneg = DO_AUTO_NEG; 2066 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2067 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 2068 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2069 } else { 2070 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 2071 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2072 } 2073 break; 2074 case IFM_10_T: 2075 sc->hw.mac.autoneg = DO_AUTO_NEG; 2076 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2077 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 2078 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2079 } else { 2080 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 2081 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2082 } 2083 break; 2084 case IFM_100_FX: 2085 sc->hw.mac.autoneg = false; 2086 sc->hw.phy.autoneg_advertised = 0; 2087 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2088 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2089 else 2090 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2091 break; 2092 case IFM_10_FL: 2093 sc->hw.mac.autoneg = false; 2094 sc->hw.phy.autoneg_advertised = 0; 2095 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2096 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2097 else 2098 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2099 break; 2100 default: 2101 device_printf(sc->dev, "Unsupported media type\n"); 2102 } 2103 2104 em_if_init(ctx); 2105 2106 return (0); 2107 } 2108 2109 static int 2110 em_if_set_promisc(if_ctx_t ctx, int flags) 2111 { 2112 struct e1000_softc *sc = iflib_get_softc(ctx); 2113 if_t ifp = iflib_get_ifp(ctx); 2114 u32 reg_rctl; 2115 int mcnt = 0; 2116 2117 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2118 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2119 if (flags & IFF_ALLMULTI) 2120 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2121 else 2122 mcnt = min(if_llmaddr_count(ifp), 2123 MAX_NUM_MULTICAST_ADDRESSES); 2124 2125 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2126 reg_rctl &= (~E1000_RCTL_MPE); 2127 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2128 2129 if (flags & IFF_PROMISC) { 2130 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2131 em_if_vlan_filter_disable(sc); 2132 /* Turn this on if you want to see bad packets */ 2133 if (em_debug_sbp) 2134 reg_rctl |= E1000_RCTL_SBP; 2135 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2136 } else { 2137 if (flags & IFF_ALLMULTI) { 2138 reg_rctl |= E1000_RCTL_MPE; 2139 reg_rctl &= ~E1000_RCTL_UPE; 2140 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2141 } 2142 if (em_if_vlan_filter_used(ctx)) 2143 em_if_vlan_filter_enable(sc); 2144 } 2145 return (0); 2146 } 2147 2148 static u_int 2149 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2150 { 2151 u8 *mta = arg; 2152 2153 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2154 return (0); 2155 2156 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2157 2158 return (1); 2159 } 2160 2161 /********************************************************************* 2162 * Multicast Update 2163 * 2164 * This routine is called whenever multicast address list is updated. 2165 * 2166 **********************************************************************/ 2167 static void 2168 em_if_multi_set(if_ctx_t ctx) 2169 { 2170 struct e1000_softc *sc = iflib_get_softc(ctx); 2171 if_t ifp = iflib_get_ifp(ctx); 2172 u8 *mta; /* Multicast array memory */ 2173 u32 reg_rctl = 0; 2174 int mcnt = 0; 2175 2176 IOCTL_DEBUGOUT("em_set_multi: begin"); 2177 2178 mta = sc->mta; 2179 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2180 2181 if (sc->hw.mac.type == e1000_82542 && 2182 sc->hw.revision_id == E1000_REVISION_2) { 2183 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2184 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2185 e1000_pci_clear_mwi(&sc->hw); 2186 reg_rctl |= E1000_RCTL_RST; 2187 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2188 msec_delay(5); 2189 } 2190 2191 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2192 2193 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2194 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2195 2196 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2197 2198 if (if_getflags(ifp) & IFF_PROMISC) 2199 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2200 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2201 if_getflags(ifp) & IFF_ALLMULTI) { 2202 reg_rctl |= E1000_RCTL_MPE; 2203 reg_rctl &= ~E1000_RCTL_UPE; 2204 } else 2205 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2206 2207 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2208 2209 if (sc->hw.mac.type == e1000_82542 && 2210 sc->hw.revision_id == E1000_REVISION_2) { 2211 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2212 reg_rctl &= ~E1000_RCTL_RST; 2213 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2214 msec_delay(5); 2215 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2216 e1000_pci_set_mwi(&sc->hw); 2217 } 2218 } 2219 2220 /********************************************************************* 2221 * Timer routine 2222 * 2223 * This routine schedules em_if_update_admin_status() to check for 2224 * link status and to gather statistics as well as to perform some 2225 * controller-specific hardware patting. 2226 * 2227 **********************************************************************/ 2228 static void 2229 em_if_timer(if_ctx_t ctx, uint16_t qid) 2230 { 2231 if (qid != 0) 2232 return; 2233 2234 iflib_admin_intr_deferred(ctx); 2235 } 2236 2237 static void 2238 em_if_update_admin_status(if_ctx_t ctx) 2239 { 2240 struct e1000_softc *sc = iflib_get_softc(ctx); 2241 struct e1000_hw *hw = &sc->hw; 2242 device_t dev = iflib_get_dev(ctx); 2243 u32 link_check, thstat, ctrl; 2244 bool automasked = false; 2245 2246 link_check = thstat = ctrl = 0; 2247 /* Get the cached link value or read phy for real */ 2248 switch (hw->phy.media_type) { 2249 case e1000_media_type_copper: 2250 if (hw->mac.get_link_status) { 2251 if (hw->mac.type == e1000_pch_spt) 2252 msec_delay(50); 2253 /* Do the work to read phy */ 2254 e1000_check_for_link(hw); 2255 link_check = !hw->mac.get_link_status; 2256 if (link_check) /* ESB2 fix */ 2257 e1000_cfg_on_link_up(hw); 2258 } else { 2259 link_check = true; 2260 } 2261 break; 2262 case e1000_media_type_fiber: 2263 e1000_check_for_link(hw); 2264 link_check = 2265 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2266 break; 2267 case e1000_media_type_internal_serdes: 2268 e1000_check_for_link(hw); 2269 link_check = hw->mac.serdes_has_link; 2270 break; 2271 /* VF device is type_unknown */ 2272 case e1000_media_type_unknown: 2273 e1000_check_for_link(hw); 2274 link_check = !hw->mac.get_link_status; 2275 /* FALLTHROUGH */ 2276 default: 2277 break; 2278 } 2279 2280 /* Check for thermal downshift or shutdown */ 2281 if (hw->mac.type == e1000_i350) { 2282 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2283 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2284 } 2285 2286 /* Now check for a transition */ 2287 if (link_check && (sc->link_active == 0)) { 2288 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2289 &sc->link_duplex); 2290 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2291 if ((sc->link_speed != SPEED_1000) && 2292 ((hw->mac.type == e1000_82571) || 2293 (hw->mac.type == e1000_82572))) { 2294 int tarc0; 2295 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2296 tarc0 &= ~TARC_SPEED_MODE_BIT; 2297 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2298 } 2299 if (bootverbose) 2300 device_printf(dev, "Link is up %d Mbps %s\n", 2301 sc->link_speed, 2302 ((sc->link_duplex == FULL_DUPLEX) ? 2303 "Full Duplex" : "Half Duplex")); 2304 sc->link_active = 1; 2305 sc->smartspeed = 0; 2306 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2307 E1000_CTRL_EXT_LINK_MODE_GMII && 2308 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2309 device_printf(dev, "Link: thermal downshift\n"); 2310 /* Delay Link Up for Phy update */ 2311 if (((hw->mac.type == e1000_i210) || 2312 (hw->mac.type == e1000_i211)) && 2313 (hw->phy.id == I210_I_PHY_ID)) 2314 msec_delay(I210_LINK_DELAY); 2315 /* Reset if the media type changed. */ 2316 if (hw->dev_spec._82575.media_changed && 2317 hw->mac.type >= igb_mac_min) { 2318 hw->dev_spec._82575.media_changed = false; 2319 sc->flags |= IGB_MEDIA_RESET; 2320 em_reset(ctx); 2321 } 2322 /* Only do TSO on gigabit for older chips due to errata */ 2323 if (hw->mac.type < igb_mac_min) 2324 automasked = em_automask_tso(ctx); 2325 2326 /* Automasking resets the interface so don't mark it up yet */ 2327 if (!automasked) 2328 iflib_link_state_change(ctx, LINK_STATE_UP, 2329 IF_Mbps(sc->link_speed)); 2330 } else if (!link_check && (sc->link_active == 1)) { 2331 sc->link_speed = 0; 2332 sc->link_duplex = 0; 2333 sc->link_active = 0; 2334 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2335 } 2336 em_update_stats_counters(sc); 2337 2338 /* Reset LAA into RAR[0] on 82571 */ 2339 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2340 e1000_rar_set(hw, hw->mac.addr, 0); 2341 2342 if (hw->mac.type < em_mac_min) 2343 lem_smartspeed(sc); 2344 } 2345 2346 static void 2347 em_if_watchdog_reset(if_ctx_t ctx) 2348 { 2349 struct e1000_softc *sc = iflib_get_softc(ctx); 2350 2351 /* 2352 * Just count the event; iflib(4) will already trigger a 2353 * sufficient reset of the controller. 2354 */ 2355 sc->watchdog_events++; 2356 } 2357 2358 /********************************************************************* 2359 * 2360 * This routine disables all traffic on the adapter by issuing a 2361 * global reset on the MAC. 2362 * 2363 **********************************************************************/ 2364 static void 2365 em_if_stop(if_ctx_t ctx) 2366 { 2367 struct e1000_softc *sc = iflib_get_softc(ctx); 2368 2369 INIT_DEBUGOUT("em_if_stop: begin"); 2370 2371 /* I219 needs special flushing to avoid hangs */ 2372 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2373 em_flush_desc_rings(sc); 2374 2375 e1000_reset_hw(&sc->hw); 2376 if (sc->hw.mac.type >= e1000_82544) 2377 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2378 2379 e1000_led_off(&sc->hw); 2380 e1000_cleanup_led(&sc->hw); 2381 } 2382 2383 /********************************************************************* 2384 * 2385 * Determine hardware revision. 2386 * 2387 **********************************************************************/ 2388 static void 2389 em_identify_hardware(if_ctx_t ctx) 2390 { 2391 device_t dev = iflib_get_dev(ctx); 2392 struct e1000_softc *sc = iflib_get_softc(ctx); 2393 2394 /* Make sure our PCI config space has the necessary stuff set */ 2395 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2396 2397 /* Save off the information about this board */ 2398 sc->hw.vendor_id = pci_get_vendor(dev); 2399 sc->hw.device_id = pci_get_device(dev); 2400 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2401 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2402 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2403 2404 /* Do Shared Code Init and Setup */ 2405 if (e1000_set_mac_type(&sc->hw)) { 2406 device_printf(dev, "Setup init failure\n"); 2407 return; 2408 } 2409 2410 /* Are we a VF device? */ 2411 if ((sc->hw.mac.type == e1000_vfadapt) || 2412 (sc->hw.mac.type == e1000_vfadapt_i350)) 2413 sc->vf_ifp = 1; 2414 else 2415 sc->vf_ifp = 0; 2416 } 2417 2418 static int 2419 em_allocate_pci_resources(if_ctx_t ctx) 2420 { 2421 struct e1000_softc *sc = iflib_get_softc(ctx); 2422 device_t dev = iflib_get_dev(ctx); 2423 int rid, val; 2424 2425 rid = PCIR_BAR(0); 2426 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2427 RF_ACTIVE); 2428 if (sc->memory == NULL) { 2429 device_printf(dev, 2430 "Unable to allocate bus resource: memory\n"); 2431 return (ENXIO); 2432 } 2433 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2434 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2435 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2436 2437 /* Only older adapters use IO mapping */ 2438 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2439 /* Figure our where our IO BAR is ? */ 2440 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2441 val = pci_read_config(dev, rid, 4); 2442 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2443 break; 2444 } 2445 rid += 4; 2446 /* check for 64bit BAR */ 2447 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2448 rid += 4; 2449 } 2450 if (rid >= PCIR_CIS) { 2451 device_printf(dev, "Unable to locate IO BAR\n"); 2452 return (ENXIO); 2453 } 2454 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2455 &rid, RF_ACTIVE); 2456 if (sc->ioport == NULL) { 2457 device_printf(dev, 2458 "Unable to allocate bus resource: ioport\n"); 2459 return (ENXIO); 2460 } 2461 sc->hw.io_base = 0; 2462 sc->osdep.io_bus_space_tag = 2463 rman_get_bustag(sc->ioport); 2464 sc->osdep.io_bus_space_handle = 2465 rman_get_bushandle(sc->ioport); 2466 } 2467 2468 sc->hw.back = &sc->osdep; 2469 2470 return (0); 2471 } 2472 2473 /********************************************************************* 2474 * 2475 * Set up the MSI-X Interrupt handlers 2476 * 2477 **********************************************************************/ 2478 static int 2479 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2480 { 2481 struct e1000_softc *sc = iflib_get_softc(ctx); 2482 struct em_rx_queue *rx_que = sc->rx_queues; 2483 struct em_tx_queue *tx_que = sc->tx_queues; 2484 int error, rid, i, vector = 0, rx_vectors; 2485 char buf[16]; 2486 2487 /* First set up ring resources */ 2488 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2489 rid = vector + 1; 2490 snprintf(buf, sizeof(buf), "rxq%d", i); 2491 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2492 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2493 if (error) { 2494 device_printf(iflib_get_dev(ctx), 2495 "Failed to allocate que int %d err: %d", 2496 i, error); 2497 sc->rx_num_queues = i + 1; 2498 goto fail; 2499 } 2500 2501 rx_que->msix = vector; 2502 2503 /* 2504 * Set the bit to enable interrupt 2505 * in E1000_IMS -- bits 20 and 21 2506 * are for RX0 and RX1, note this has 2507 * NOTHING to do with the MSI-X vector 2508 */ 2509 if (sc->hw.mac.type == e1000_82574) { 2510 rx_que->eims = 1 << (20 + i); 2511 sc->ims |= rx_que->eims; 2512 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2513 } else if (sc->hw.mac.type == e1000_82575) 2514 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2515 else 2516 rx_que->eims = 1 << vector; 2517 } 2518 rx_vectors = vector; 2519 2520 vector = 0; 2521 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2522 snprintf(buf, sizeof(buf), "txq%d", i); 2523 tx_que = &sc->tx_queues[i]; 2524 iflib_softirq_alloc_generic(ctx, 2525 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2526 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2527 2528 tx_que->msix = (vector % sc->rx_num_queues); 2529 2530 /* 2531 * Set the bit to enable interrupt 2532 * in E1000_IMS -- bits 22 and 23 2533 * are for TX0 and TX1, note this has 2534 * NOTHING to do with the MSI-X vector 2535 */ 2536 if (sc->hw.mac.type == e1000_82574) { 2537 tx_que->eims = 1 << (22 + i); 2538 sc->ims |= tx_que->eims; 2539 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2540 } else if (sc->hw.mac.type == e1000_82575) { 2541 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2542 } else { 2543 tx_que->eims = 1 << i; 2544 } 2545 } 2546 2547 /* Link interrupt */ 2548 rid = rx_vectors + 1; 2549 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2550 em_msix_link, sc, 0, "aq"); 2551 2552 if (error) { 2553 device_printf(iflib_get_dev(ctx), 2554 "Failed to register admin handler"); 2555 goto fail; 2556 } 2557 sc->linkvec = rx_vectors; 2558 if (sc->hw.mac.type < igb_mac_min) { 2559 sc->ivars |= (8 | rx_vectors) << 16; 2560 sc->ivars |= 0x80000000; 2561 /* Enable the "Other" interrupt type for link status change */ 2562 sc->ims |= E1000_IMS_OTHER; 2563 } 2564 2565 return (0); 2566 fail: 2567 iflib_irq_free(ctx, &sc->irq); 2568 rx_que = sc->rx_queues; 2569 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2570 iflib_irq_free(ctx, &rx_que->que_irq); 2571 return (error); 2572 } 2573 2574 static void 2575 igb_configure_queues(struct e1000_softc *sc) 2576 { 2577 struct e1000_hw *hw = &sc->hw; 2578 struct em_rx_queue *rx_que; 2579 struct em_tx_queue *tx_que; 2580 u32 tmp, ivar = 0, newitr = 0; 2581 2582 /* First turn on RSS capability */ 2583 if (hw->mac.type != e1000_82575) 2584 E1000_WRITE_REG(hw, E1000_GPIE, 2585 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2586 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2587 2588 /* Turn on MSI-X */ 2589 switch (hw->mac.type) { 2590 case e1000_82580: 2591 case e1000_i350: 2592 case e1000_i354: 2593 case e1000_i210: 2594 case e1000_i211: 2595 case e1000_vfadapt: 2596 case e1000_vfadapt_i350: 2597 /* RX entries */ 2598 for (int i = 0; i < sc->rx_num_queues; i++) { 2599 u32 index = i >> 1; 2600 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2601 rx_que = &sc->rx_queues[i]; 2602 if (i & 1) { 2603 ivar &= 0xFF00FFFF; 2604 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2605 16; 2606 } else { 2607 ivar &= 0xFFFFFF00; 2608 ivar |= rx_que->msix | E1000_IVAR_VALID; 2609 } 2610 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2611 } 2612 /* TX entries */ 2613 for (int i = 0; i < sc->tx_num_queues; i++) { 2614 u32 index = i >> 1; 2615 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2616 tx_que = &sc->tx_queues[i]; 2617 if (i & 1) { 2618 ivar &= 0x00FFFFFF; 2619 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2620 24; 2621 } else { 2622 ivar &= 0xFFFF00FF; 2623 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2624 8; 2625 } 2626 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2627 sc->que_mask |= tx_que->eims; 2628 } 2629 2630 /* And for the link interrupt */ 2631 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2632 sc->link_mask = 1 << sc->linkvec; 2633 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2634 break; 2635 case e1000_82576: 2636 /* RX entries */ 2637 for (int i = 0; i < sc->rx_num_queues; i++) { 2638 u32 index = i & 0x7; /* Each IVAR has two entries */ 2639 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2640 rx_que = &sc->rx_queues[i]; 2641 if (i < 8) { 2642 ivar &= 0xFFFFFF00; 2643 ivar |= rx_que->msix | E1000_IVAR_VALID; 2644 } else { 2645 ivar &= 0xFF00FFFF; 2646 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2647 16; 2648 } 2649 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2650 sc->que_mask |= rx_que->eims; 2651 } 2652 /* TX entries */ 2653 for (int i = 0; i < sc->tx_num_queues; i++) { 2654 u32 index = i & 0x7; /* Each IVAR has two entries */ 2655 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2656 tx_que = &sc->tx_queues[i]; 2657 if (i < 8) { 2658 ivar &= 0xFFFF00FF; 2659 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2660 8; 2661 } else { 2662 ivar &= 0x00FFFFFF; 2663 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2664 24; 2665 } 2666 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2667 sc->que_mask |= tx_que->eims; 2668 } 2669 2670 /* And for the link interrupt */ 2671 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2672 sc->link_mask = 1 << sc->linkvec; 2673 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2674 break; 2675 2676 case e1000_82575: 2677 /* enable MSI-X support*/ 2678 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2679 tmp |= E1000_CTRL_EXT_PBA_CLR; 2680 /* Auto-Mask interrupts upon ICR read. */ 2681 tmp |= E1000_CTRL_EXT_EIAME; 2682 tmp |= E1000_CTRL_EXT_IRCA; 2683 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2684 2685 /* Queues */ 2686 for (int i = 0; i < sc->rx_num_queues; i++) { 2687 rx_que = &sc->rx_queues[i]; 2688 tmp = E1000_EICR_RX_QUEUE0 << i; 2689 tmp |= E1000_EICR_TX_QUEUE0 << i; 2690 rx_que->eims = tmp; 2691 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2692 rx_que->eims); 2693 sc->que_mask |= rx_que->eims; 2694 } 2695 2696 /* Link */ 2697 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2698 E1000_EIMS_OTHER); 2699 sc->link_mask |= E1000_EIMS_OTHER; 2700 default: 2701 break; 2702 } 2703 2704 /* Set the igb starting interrupt rate */ 2705 if (em_max_interrupt_rate > 0) { 2706 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2707 2708 if (hw->mac.type == e1000_82575) 2709 newitr |= newitr << 16; 2710 else 2711 newitr |= E1000_EITR_CNT_IGNR; 2712 2713 for (int i = 0; i < sc->rx_num_queues; i++) { 2714 rx_que = &sc->rx_queues[i]; 2715 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2716 } 2717 } 2718 2719 return; 2720 } 2721 2722 static void 2723 em_free_pci_resources(if_ctx_t ctx) 2724 { 2725 struct e1000_softc *sc = iflib_get_softc(ctx); 2726 struct em_rx_queue *que = sc->rx_queues; 2727 device_t dev = iflib_get_dev(ctx); 2728 2729 /* Release all MSI-X queue resources */ 2730 if (sc->intr_type == IFLIB_INTR_MSIX) 2731 iflib_irq_free(ctx, &sc->irq); 2732 2733 if (que != NULL) { 2734 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2735 iflib_irq_free(ctx, &que->que_irq); 2736 } 2737 } 2738 2739 if (sc->memory != NULL) { 2740 bus_release_resource(dev, SYS_RES_MEMORY, 2741 rman_get_rid(sc->memory), sc->memory); 2742 sc->memory = NULL; 2743 } 2744 2745 if (sc->flash != NULL) { 2746 bus_release_resource(dev, SYS_RES_MEMORY, 2747 rman_get_rid(sc->flash), sc->flash); 2748 sc->flash = NULL; 2749 } 2750 2751 if (sc->ioport != NULL) { 2752 bus_release_resource(dev, SYS_RES_IOPORT, 2753 rman_get_rid(sc->ioport), sc->ioport); 2754 sc->ioport = NULL; 2755 } 2756 } 2757 2758 /* Set up MSI or MSI-X */ 2759 static int 2760 em_setup_msix(if_ctx_t ctx) 2761 { 2762 struct e1000_softc *sc = iflib_get_softc(ctx); 2763 2764 if (sc->hw.mac.type == e1000_82574) { 2765 em_enable_vectors_82574(ctx); 2766 } 2767 return (0); 2768 } 2769 2770 /********************************************************************* 2771 * 2772 * Workaround for SmartSpeed on 82541 and 82547 controllers 2773 * 2774 **********************************************************************/ 2775 static void 2776 lem_smartspeed(struct e1000_softc *sc) 2777 { 2778 u16 phy_tmp; 2779 2780 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2781 sc->hw.mac.autoneg == 0 || 2782 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2783 return; 2784 2785 if (sc->smartspeed == 0) { 2786 /* If Master/Slave config fault is asserted twice, 2787 * we assume back-to-back */ 2788 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2789 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2790 return; 2791 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2792 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2793 e1000_read_phy_reg(&sc->hw, 2794 PHY_1000T_CTRL, &phy_tmp); 2795 if(phy_tmp & CR_1000T_MS_ENABLE) { 2796 phy_tmp &= ~CR_1000T_MS_ENABLE; 2797 e1000_write_phy_reg(&sc->hw, 2798 PHY_1000T_CTRL, phy_tmp); 2799 sc->smartspeed++; 2800 if(sc->hw.mac.autoneg && 2801 !e1000_copper_link_autoneg(&sc->hw) && 2802 !e1000_read_phy_reg(&sc->hw, 2803 PHY_CONTROL, &phy_tmp)) { 2804 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2805 MII_CR_RESTART_AUTO_NEG); 2806 e1000_write_phy_reg(&sc->hw, 2807 PHY_CONTROL, phy_tmp); 2808 } 2809 } 2810 } 2811 return; 2812 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2813 /* If still no link, perhaps using 2/3 pair cable */ 2814 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2815 phy_tmp |= CR_1000T_MS_ENABLE; 2816 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2817 if(sc->hw.mac.autoneg && 2818 !e1000_copper_link_autoneg(&sc->hw) && 2819 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2820 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2821 MII_CR_RESTART_AUTO_NEG); 2822 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2823 } 2824 } 2825 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2826 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2827 sc->smartspeed = 0; 2828 } 2829 2830 /********************************************************************* 2831 * 2832 * Initialize the DMA Coalescing feature 2833 * 2834 **********************************************************************/ 2835 static void 2836 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2837 { 2838 device_t dev = sc->dev; 2839 struct e1000_hw *hw = &sc->hw; 2840 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2841 u16 hwm; 2842 u16 max_frame_size; 2843 2844 if (hw->mac.type == e1000_i211) 2845 return; 2846 2847 max_frame_size = sc->shared->isc_max_frame_size; 2848 if (hw->mac.type > e1000_82580) { 2849 2850 if (sc->dmac == 0) { /* Disabling it */ 2851 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2852 return; 2853 } else 2854 device_printf(dev, "DMA Coalescing enabled\n"); 2855 2856 /* Set starting threshold */ 2857 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2858 2859 hwm = 64 * pba - max_frame_size / 16; 2860 if (hwm < 64 * (pba - 6)) 2861 hwm = 64 * (pba - 6); 2862 reg = E1000_READ_REG(hw, E1000_FCRTC); 2863 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2864 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2865 & E1000_FCRTC_RTH_COAL_MASK); 2866 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2867 2868 2869 dmac = pba - max_frame_size / 512; 2870 if (dmac < pba - 10) 2871 dmac = pba - 10; 2872 reg = E1000_READ_REG(hw, E1000_DMACR); 2873 reg &= ~E1000_DMACR_DMACTHR_MASK; 2874 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2875 & E1000_DMACR_DMACTHR_MASK); 2876 2877 /* transition to L0x or L1 if available..*/ 2878 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2879 2880 /* Check if status is 2.5Gb backplane connection 2881 * before configuration of watchdog timer, which is 2882 * in msec values in 12.8usec intervals 2883 * watchdog timer= msec values in 32usec intervals 2884 * for non 2.5Gb connection 2885 */ 2886 if (hw->mac.type == e1000_i354) { 2887 int status = E1000_READ_REG(hw, E1000_STATUS); 2888 if ((status & E1000_STATUS_2P5_SKU) && 2889 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2890 reg |= ((sc->dmac * 5) >> 6); 2891 else 2892 reg |= (sc->dmac >> 5); 2893 } else { 2894 reg |= (sc->dmac >> 5); 2895 } 2896 2897 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2898 2899 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2900 2901 /* Set the interval before transition */ 2902 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2903 if (hw->mac.type == e1000_i350) 2904 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2905 /* 2906 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2907 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2908 */ 2909 if (hw->mac.type == e1000_i354) { 2910 int status = E1000_READ_REG(hw, E1000_STATUS); 2911 if ((status & E1000_STATUS_2P5_SKU) && 2912 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2913 reg |= 0xA; 2914 else 2915 reg |= 0x4; 2916 } else { 2917 reg |= 0x4; 2918 } 2919 2920 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2921 2922 /* free space in tx packet buffer to wake from DMA coal */ 2923 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2924 (2 * max_frame_size)) >> 6); 2925 2926 /* make low power state decision controlled by DMA coal */ 2927 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2928 reg &= ~E1000_PCIEMISC_LX_DECISION; 2929 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2930 2931 } else if (hw->mac.type == e1000_82580) { 2932 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2933 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2934 reg & ~E1000_PCIEMISC_LX_DECISION); 2935 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2936 } 2937 } 2938 /********************************************************************* 2939 * The 3 following flush routines are used as a workaround in the 2940 * I219 client parts and only for them. 2941 * 2942 * em_flush_tx_ring - remove all descriptors from the tx_ring 2943 * 2944 * We want to clear all pending descriptors from the TX ring. 2945 * zeroing happens when the HW reads the regs. We assign the ring itself as 2946 * the data of the next descriptor. We don't care about the data we are about 2947 * to reset the HW. 2948 **********************************************************************/ 2949 static void 2950 em_flush_tx_ring(struct e1000_softc *sc) 2951 { 2952 struct e1000_hw *hw = &sc->hw; 2953 struct tx_ring *txr = &sc->tx_queues->txr; 2954 struct e1000_tx_desc *txd; 2955 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2956 u16 size = 512; 2957 2958 tctl = E1000_READ_REG(hw, E1000_TCTL); 2959 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2960 2961 txd = &txr->tx_base[txr->tx_cidx_processed]; 2962 2963 /* Just use the ring as a dummy buffer addr */ 2964 txd->buffer_addr = txr->tx_paddr; 2965 txd->lower.data = htole32(txd_lower | size); 2966 txd->upper.data = 0; 2967 2968 /* flush descriptors to memory before notifying the HW */ 2969 wmb(); 2970 2971 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2972 mb(); 2973 usec_delay(250); 2974 } 2975 2976 /********************************************************************* 2977 * em_flush_rx_ring - remove all descriptors from the rx_ring 2978 * 2979 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2980 **********************************************************************/ 2981 static void 2982 em_flush_rx_ring(struct e1000_softc *sc) 2983 { 2984 struct e1000_hw *hw = &sc->hw; 2985 u32 rctl, rxdctl; 2986 2987 rctl = E1000_READ_REG(hw, E1000_RCTL); 2988 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2989 E1000_WRITE_FLUSH(hw); 2990 usec_delay(150); 2991 2992 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2993 /* zero the lower 14 bits (prefetch and host thresholds) */ 2994 rxdctl &= 0xffffc000; 2995 /* 2996 * update thresholds: prefetch threshold to 31, host threshold to 1 2997 * and make sure the granularity is "descriptors" and not 2998 * "cache lines" 2999 */ 3000 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3001 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 3002 3003 /* momentarily enable the RX ring for the changes to take effect */ 3004 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3005 E1000_WRITE_FLUSH(hw); 3006 usec_delay(150); 3007 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3008 } 3009 3010 /********************************************************************* 3011 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3012 * 3013 * In I219, the descriptor rings must be emptied before resetting the HW 3014 * or before changing the device state to D3 during runtime (runtime PM). 3015 * 3016 * Failure to do this will cause the HW to enter a unit hang state which can 3017 * only be released by PCI reset on the device 3018 * 3019 **********************************************************************/ 3020 static void 3021 em_flush_desc_rings(struct e1000_softc *sc) 3022 { 3023 struct e1000_hw *hw = &sc->hw; 3024 device_t dev = sc->dev; 3025 u16 hang_state; 3026 u32 fext_nvm11, tdlen; 3027 3028 /* First, disable MULR fix in FEXTNVM11 */ 3029 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 3030 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3031 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3032 3033 /* do nothing if we're not in faulty state, or the queue is empty */ 3034 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3035 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3036 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3037 return; 3038 em_flush_tx_ring(sc); 3039 3040 /* recheck, maybe the fault is caused by the rx ring */ 3041 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3042 if (hang_state & FLUSH_DESC_REQUIRED) 3043 em_flush_rx_ring(sc); 3044 } 3045 3046 3047 /********************************************************************* 3048 * 3049 * Initialize the hardware to a configuration as specified by the 3050 * sc structure. 3051 * 3052 **********************************************************************/ 3053 static void 3054 em_reset(if_ctx_t ctx) 3055 { 3056 device_t dev = iflib_get_dev(ctx); 3057 struct e1000_softc *sc = iflib_get_softc(ctx); 3058 if_t ifp = iflib_get_ifp(ctx); 3059 struct e1000_hw *hw = &sc->hw; 3060 u32 rx_buffer_size; 3061 u32 pba; 3062 3063 INIT_DEBUGOUT("em_reset: begin"); 3064 /* Let the firmware know the OS is in control */ 3065 em_get_hw_control(sc); 3066 3067 /* Set up smart power down as default off on newer adapters. */ 3068 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3069 hw->mac.type == e1000_82572)) { 3070 u16 phy_tmp = 0; 3071 3072 /* Speed up time to link by disabling smart power down. */ 3073 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3074 phy_tmp &= ~IGP02E1000_PM_SPD; 3075 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3076 } 3077 3078 /* 3079 * Packet Buffer Allocation (PBA) 3080 * Writing PBA sets the receive portion of the buffer 3081 * the remainder is used for the transmit buffer. 3082 */ 3083 switch (hw->mac.type) { 3084 /* 82547: Total Packet Buffer is 40K */ 3085 case e1000_82547: 3086 case e1000_82547_rev_2: 3087 if (hw->mac.max_frame_size > 8192) 3088 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3089 else 3090 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3091 break; 3092 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3093 case e1000_82571: 3094 case e1000_82572: 3095 case e1000_80003es2lan: 3096 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3097 break; 3098 /* 82573: Total Packet Buffer is 32K */ 3099 case e1000_82573: 3100 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3101 break; 3102 case e1000_82574: 3103 case e1000_82583: 3104 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 3105 break; 3106 case e1000_ich8lan: 3107 pba = E1000_PBA_8K; 3108 break; 3109 case e1000_ich9lan: 3110 case e1000_ich10lan: 3111 /* Boost Receive side for jumbo frames */ 3112 if (hw->mac.max_frame_size > 4096) 3113 pba = E1000_PBA_14K; 3114 else 3115 pba = E1000_PBA_10K; 3116 break; 3117 case e1000_pchlan: 3118 case e1000_pch2lan: 3119 case e1000_pch_lpt: 3120 case e1000_pch_spt: 3121 case e1000_pch_cnp: 3122 case e1000_pch_tgp: 3123 case e1000_pch_adp: 3124 case e1000_pch_mtp: 3125 case e1000_pch_ptp: 3126 pba = E1000_PBA_26K; 3127 break; 3128 case e1000_82575: 3129 pba = E1000_PBA_32K; 3130 break; 3131 case e1000_82576: 3132 case e1000_vfadapt: 3133 pba = E1000_READ_REG(hw, E1000_RXPBS); 3134 pba &= E1000_RXPBS_SIZE_MASK_82576; 3135 break; 3136 case e1000_82580: 3137 case e1000_i350: 3138 case e1000_i354: 3139 case e1000_vfadapt_i350: 3140 pba = E1000_READ_REG(hw, E1000_RXPBS); 3141 pba = e1000_rxpbs_adjust_82580(pba); 3142 break; 3143 case e1000_i210: 3144 case e1000_i211: 3145 pba = E1000_PBA_34K; 3146 break; 3147 default: 3148 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3149 if (hw->mac.max_frame_size > 8192) 3150 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3151 else 3152 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3153 } 3154 3155 /* Special needs in case of Jumbo frames */ 3156 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3157 u32 tx_space, min_tx, min_rx; 3158 pba = E1000_READ_REG(hw, E1000_PBA); 3159 tx_space = pba >> 16; 3160 pba &= 0xffff; 3161 min_tx = (hw->mac.max_frame_size + 3162 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3163 min_tx = roundup2(min_tx, 1024); 3164 min_tx >>= 10; 3165 min_rx = hw->mac.max_frame_size; 3166 min_rx = roundup2(min_rx, 1024); 3167 min_rx >>= 10; 3168 if (tx_space < min_tx && 3169 ((min_tx - tx_space) < pba)) { 3170 pba = pba - (min_tx - tx_space); 3171 /* 3172 * if short on rx space, rx wins 3173 * and must trump tx adjustment 3174 */ 3175 if (pba < min_rx) 3176 pba = min_rx; 3177 } 3178 E1000_WRITE_REG(hw, E1000_PBA, pba); 3179 } 3180 3181 if (hw->mac.type < igb_mac_min) 3182 E1000_WRITE_REG(hw, E1000_PBA, pba); 3183 3184 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3185 3186 /* 3187 * These parameters control the automatic generation (Tx) and 3188 * response (Rx) to Ethernet PAUSE frames. 3189 * - High water mark should allow for at least two frames to be 3190 * received after sending an XOFF. 3191 * - Low water mark works best when it is very near the high water 3192 mark. 3193 * This allows the receiver to restart by sending XON when it has 3194 * drained a bit. Here we use an arbitrary value of 1500 which will 3195 * restart after one full frame is pulled from the buffer. There 3196 * could be several smaller frames in the buffer and if so they will 3197 * not trigger the XON until their total number reduces the buffer 3198 * by 1500. 3199 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3200 */ 3201 rx_buffer_size = (pba & 0xffff) << 10; 3202 hw->fc.high_water = rx_buffer_size - 3203 roundup2(hw->mac.max_frame_size, 1024); 3204 hw->fc.low_water = hw->fc.high_water - 1500; 3205 3206 if (sc->fc) /* locally set flow control value? */ 3207 hw->fc.requested_mode = sc->fc; 3208 else 3209 hw->fc.requested_mode = e1000_fc_full; 3210 3211 if (hw->mac.type == e1000_80003es2lan) 3212 hw->fc.pause_time = 0xFFFF; 3213 else 3214 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3215 3216 hw->fc.send_xon = true; 3217 3218 /* Device specific overrides/settings */ 3219 switch (hw->mac.type) { 3220 case e1000_pchlan: 3221 /* Workaround: no TX flow ctrl for PCH */ 3222 hw->fc.requested_mode = e1000_fc_rx_pause; 3223 hw->fc.pause_time = 0xFFFF; /* override */ 3224 if (if_getmtu(ifp) > ETHERMTU) { 3225 hw->fc.high_water = 0x3500; 3226 hw->fc.low_water = 0x1500; 3227 } else { 3228 hw->fc.high_water = 0x5000; 3229 hw->fc.low_water = 0x3000; 3230 } 3231 hw->fc.refresh_time = 0x1000; 3232 break; 3233 case e1000_pch2lan: 3234 case e1000_pch_lpt: 3235 case e1000_pch_spt: 3236 case e1000_pch_cnp: 3237 case e1000_pch_tgp: 3238 case e1000_pch_adp: 3239 case e1000_pch_mtp: 3240 case e1000_pch_ptp: 3241 hw->fc.high_water = 0x5C20; 3242 hw->fc.low_water = 0x5048; 3243 hw->fc.pause_time = 0x0650; 3244 hw->fc.refresh_time = 0x0400; 3245 /* Jumbos need adjusted PBA */ 3246 if (if_getmtu(ifp) > ETHERMTU) 3247 E1000_WRITE_REG(hw, E1000_PBA, 12); 3248 else 3249 E1000_WRITE_REG(hw, E1000_PBA, 26); 3250 break; 3251 case e1000_82575: 3252 case e1000_82576: 3253 /* 8-byte granularity */ 3254 hw->fc.low_water = hw->fc.high_water - 8; 3255 break; 3256 case e1000_82580: 3257 case e1000_i350: 3258 case e1000_i354: 3259 case e1000_i210: 3260 case e1000_i211: 3261 case e1000_vfadapt: 3262 case e1000_vfadapt_i350: 3263 /* 16-byte granularity */ 3264 hw->fc.low_water = hw->fc.high_water - 16; 3265 break; 3266 case e1000_ich9lan: 3267 case e1000_ich10lan: 3268 if (if_getmtu(ifp) > ETHERMTU) { 3269 hw->fc.high_water = 0x2800; 3270 hw->fc.low_water = hw->fc.high_water - 8; 3271 break; 3272 } 3273 /* FALLTHROUGH */ 3274 default: 3275 if (hw->mac.type == e1000_80003es2lan) 3276 hw->fc.pause_time = 0xFFFF; 3277 break; 3278 } 3279 3280 /* I219 needs some special flushing to avoid hangs */ 3281 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3282 em_flush_desc_rings(sc); 3283 3284 /* Issue a global reset */ 3285 e1000_reset_hw(hw); 3286 if (hw->mac.type >= igb_mac_min) { 3287 E1000_WRITE_REG(hw, E1000_WUC, 0); 3288 } else { 3289 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3290 em_disable_aspm(sc); 3291 } 3292 if (sc->flags & IGB_MEDIA_RESET) { 3293 e1000_setup_init_funcs(hw, true); 3294 e1000_get_bus_info(hw); 3295 sc->flags &= ~IGB_MEDIA_RESET; 3296 } 3297 /* and a re-init */ 3298 if (e1000_init_hw(hw) < 0) { 3299 device_printf(dev, "Hardware Initialization Failed\n"); 3300 return; 3301 } 3302 if (hw->mac.type >= igb_mac_min) 3303 igb_init_dmac(sc, pba); 3304 3305 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3306 sc->pba = pba; 3307 3308 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3309 e1000_get_phy_info(hw); 3310 e1000_check_for_link(hw); 3311 } 3312 3313 /* 3314 * Initialise the RSS mapping for NICs that support multiple transmit/ 3315 * receive rings. 3316 */ 3317 3318 #define RSSKEYLEN 10 3319 static void 3320 em_initialize_rss_mapping(struct e1000_softc *sc) 3321 { 3322 uint8_t rss_key[4 * RSSKEYLEN]; 3323 uint32_t reta = 0; 3324 struct e1000_hw *hw = &sc->hw; 3325 int i; 3326 3327 /* 3328 * Configure RSS key 3329 */ 3330 arc4rand(rss_key, sizeof(rss_key), 0); 3331 for (i = 0; i < RSSKEYLEN; ++i) { 3332 uint32_t rssrk = 0; 3333 3334 rssrk = EM_RSSRK_VAL(rss_key, i); 3335 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3336 } 3337 3338 /* 3339 * Configure RSS redirect table in following fashion: 3340 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3341 */ 3342 for (i = 0; i < sizeof(reta); ++i) { 3343 uint32_t q; 3344 3345 q = (i % sc->rx_num_queues) << 7; 3346 reta |= q << (8 * i); 3347 } 3348 3349 for (i = 0; i < 32; ++i) 3350 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3351 3352 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3353 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3354 E1000_MRQC_RSS_FIELD_IPV4 | 3355 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3356 E1000_MRQC_RSS_FIELD_IPV6_EX | 3357 E1000_MRQC_RSS_FIELD_IPV6); 3358 } 3359 3360 static void 3361 igb_initialize_rss_mapping(struct e1000_softc *sc) 3362 { 3363 struct e1000_hw *hw = &sc->hw; 3364 int i; 3365 int queue_id; 3366 u32 reta; 3367 u32 rss_key[10], mrqc, shift = 0; 3368 3369 /* XXX? */ 3370 if (hw->mac.type == e1000_82575) 3371 shift = 6; 3372 3373 /* 3374 * The redirection table controls which destination 3375 * queue each bucket redirects traffic to. 3376 * Each DWORD represents four queues, with the LSB 3377 * being the first queue in the DWORD. 3378 * 3379 * This just allocates buckets to queues using round-robin 3380 * allocation. 3381 * 3382 * NOTE: It Just Happens to line up with the default 3383 * RSS allocation method. 3384 */ 3385 3386 /* Warning FM follows */ 3387 reta = 0; 3388 for (i = 0; i < 128; i++) { 3389 #ifdef RSS 3390 queue_id = rss_get_indirection_to_bucket(i); 3391 /* 3392 * If we have more queues than buckets, we'll 3393 * end up mapping buckets to a subset of the 3394 * queues. 3395 * 3396 * If we have more buckets than queues, we'll 3397 * end up instead assigning multiple buckets 3398 * to queues. 3399 * 3400 * Both are suboptimal, but we need to handle 3401 * the case so we don't go out of bounds 3402 * indexing arrays and such. 3403 */ 3404 queue_id = queue_id % sc->rx_num_queues; 3405 #else 3406 queue_id = (i % sc->rx_num_queues); 3407 #endif 3408 /* Adjust if required */ 3409 queue_id = queue_id << shift; 3410 3411 /* 3412 * The low 8 bits are for hash value (n+0); 3413 * The next 8 bits are for hash value (n+1), etc. 3414 */ 3415 reta = reta >> 8; 3416 reta = reta | ( ((uint32_t) queue_id) << 24); 3417 if ((i & 3) == 3) { 3418 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3419 reta = 0; 3420 } 3421 } 3422 3423 /* Now fill in hash table */ 3424 3425 /* 3426 * MRQC: Multiple Receive Queues Command 3427 * Set queuing to RSS control, number depends on the device. 3428 */ 3429 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3430 3431 #ifdef RSS 3432 /* XXX ew typecasting */ 3433 rss_getkey((uint8_t *) &rss_key); 3434 #else 3435 arc4rand(&rss_key, sizeof(rss_key), 0); 3436 #endif 3437 for (i = 0; i < 10; i++) 3438 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3439 3440 /* 3441 * Configure the RSS fields to hash upon. 3442 */ 3443 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3444 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3445 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3446 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3447 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3448 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3449 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3450 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3451 3452 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3453 } 3454 3455 /********************************************************************* 3456 * 3457 * Setup networking device structure and register interface media. 3458 * 3459 **********************************************************************/ 3460 static int 3461 em_setup_interface(if_ctx_t ctx) 3462 { 3463 if_t ifp = iflib_get_ifp(ctx); 3464 struct e1000_softc *sc = iflib_get_softc(ctx); 3465 if_softc_ctx_t scctx = sc->shared; 3466 3467 INIT_DEBUGOUT("em_setup_interface: begin"); 3468 3469 /* Single Queue */ 3470 if (sc->tx_num_queues == 1) { 3471 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3472 if_setsendqready(ifp); 3473 } 3474 3475 /* 3476 * Specify the media types supported by this adapter and register 3477 * callbacks to update media and link information 3478 */ 3479 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3480 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3481 u_char fiber_type = IFM_1000_SX; /* default type */ 3482 3483 if (sc->hw.mac.type == e1000_82545) 3484 fiber_type = IFM_1000_LX; 3485 ifmedia_add(sc->media, 3486 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3487 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3488 } else { 3489 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3490 ifmedia_add(sc->media, 3491 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3492 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3493 ifmedia_add(sc->media, 3494 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3495 if (sc->hw.phy.type != e1000_phy_ife) { 3496 ifmedia_add(sc->media, 3497 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3498 ifmedia_add(sc->media, 3499 IFM_ETHER | IFM_1000_T, 0, NULL); 3500 } 3501 } 3502 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3503 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3504 return (0); 3505 } 3506 3507 static int 3508 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3509 int ntxqs, int ntxqsets) 3510 { 3511 struct e1000_softc *sc = iflib_get_softc(ctx); 3512 if_softc_ctx_t scctx = sc->shared; 3513 int error = E1000_SUCCESS; 3514 struct em_tx_queue *que; 3515 int i, j; 3516 3517 MPASS(sc->tx_num_queues > 0); 3518 MPASS(sc->tx_num_queues == ntxqsets); 3519 3520 /* First allocate the top level queue structs */ 3521 if (!(sc->tx_queues = 3522 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3523 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3524 device_printf(iflib_get_dev(ctx), 3525 "Unable to allocate queue memory\n"); 3526 return(ENOMEM); 3527 } 3528 3529 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3530 /* Set up some basics */ 3531 3532 struct tx_ring *txr = &que->txr; 3533 txr->sc = que->sc = sc; 3534 que->me = txr->me = i; 3535 3536 /* Allocate report status array */ 3537 if (!(txr->tx_rsq = 3538 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3539 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3540 device_printf(iflib_get_dev(ctx), 3541 "failed to allocate rs_idxs memory\n"); 3542 error = ENOMEM; 3543 goto fail; 3544 } 3545 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3546 txr->tx_rsq[j] = QIDX_INVALID; 3547 /* get the virtual and physical address of hardware queues */ 3548 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3549 txr->tx_paddr = paddrs[i*ntxqs]; 3550 } 3551 3552 if (bootverbose) 3553 device_printf(iflib_get_dev(ctx), 3554 "allocated for %d tx_queues\n", sc->tx_num_queues); 3555 return (0); 3556 fail: 3557 em_if_queues_free(ctx); 3558 return (error); 3559 } 3560 3561 static int 3562 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3563 int nrxqs, int nrxqsets) 3564 { 3565 struct e1000_softc *sc = iflib_get_softc(ctx); 3566 int error = E1000_SUCCESS; 3567 struct em_rx_queue *que; 3568 int i; 3569 3570 MPASS(sc->rx_num_queues > 0); 3571 MPASS(sc->rx_num_queues == nrxqsets); 3572 3573 /* First allocate the top level queue structs */ 3574 if (!(sc->rx_queues = 3575 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3576 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3577 device_printf(iflib_get_dev(ctx), 3578 "Unable to allocate queue memory\n"); 3579 error = ENOMEM; 3580 goto fail; 3581 } 3582 3583 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3584 /* Set up some basics */ 3585 struct rx_ring *rxr = &que->rxr; 3586 rxr->sc = que->sc = sc; 3587 rxr->que = que; 3588 que->me = rxr->me = i; 3589 3590 /* get the virtual and physical address of hardware queues */ 3591 rxr->rx_base = 3592 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3593 rxr->rx_paddr = paddrs[i*nrxqs]; 3594 } 3595 3596 if (bootverbose) 3597 device_printf(iflib_get_dev(ctx), 3598 "allocated for %d rx_queues\n", sc->rx_num_queues); 3599 3600 return (0); 3601 fail: 3602 em_if_queues_free(ctx); 3603 return (error); 3604 } 3605 3606 static void 3607 em_if_queues_free(if_ctx_t ctx) 3608 { 3609 struct e1000_softc *sc = iflib_get_softc(ctx); 3610 struct em_tx_queue *tx_que = sc->tx_queues; 3611 struct em_rx_queue *rx_que = sc->rx_queues; 3612 3613 if (tx_que != NULL) { 3614 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3615 struct tx_ring *txr = &tx_que->txr; 3616 if (txr->tx_rsq == NULL) 3617 break; 3618 3619 free(txr->tx_rsq, M_DEVBUF); 3620 txr->tx_rsq = NULL; 3621 } 3622 free(sc->tx_queues, M_DEVBUF); 3623 sc->tx_queues = NULL; 3624 } 3625 3626 if (rx_que != NULL) { 3627 free(sc->rx_queues, M_DEVBUF); 3628 sc->rx_queues = NULL; 3629 } 3630 } 3631 3632 /********************************************************************* 3633 * 3634 * Enable transmit unit. 3635 * 3636 **********************************************************************/ 3637 static void 3638 em_initialize_transmit_unit(if_ctx_t ctx) 3639 { 3640 struct e1000_softc *sc = iflib_get_softc(ctx); 3641 if_softc_ctx_t scctx = sc->shared; 3642 struct em_tx_queue *que; 3643 struct tx_ring *txr; 3644 struct e1000_hw *hw = &sc->hw; 3645 u32 tctl, txdctl = 0, tarc, tipg = 0; 3646 3647 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3648 3649 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3650 u64 bus_addr; 3651 caddr_t offp, endp; 3652 3653 que = &sc->tx_queues[i]; 3654 txr = &que->txr; 3655 bus_addr = txr->tx_paddr; 3656 3657 /* Clear checksum offload context. */ 3658 offp = (caddr_t)&txr->csum_flags; 3659 endp = (caddr_t)(txr + 1); 3660 bzero(offp, endp - offp); 3661 3662 /* Base and Len of TX Ring */ 3663 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3664 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3665 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3666 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3667 /* Init the HEAD/TAIL indices */ 3668 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3669 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3670 3671 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3672 E1000_READ_REG(hw, E1000_TDBAL(i)), 3673 E1000_READ_REG(hw, E1000_TDLEN(i))); 3674 3675 txdctl = 0; /* clear txdctl */ 3676 txdctl |= 0x1f; /* PTHRESH */ 3677 txdctl |= 1 << 8; /* HTHRESH */ 3678 txdctl |= 1 << 16;/* WTHRESH */ 3679 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3680 txdctl |= E1000_TXDCTL_GRAN; 3681 txdctl |= 1 << 25; /* LWTHRESH */ 3682 3683 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3684 } 3685 3686 /* Set the default values for the Tx Inter Packet Gap timer */ 3687 switch (hw->mac.type) { 3688 case e1000_80003es2lan: 3689 tipg = DEFAULT_82543_TIPG_IPGR1; 3690 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3691 E1000_TIPG_IPGR2_SHIFT; 3692 break; 3693 case e1000_82542: 3694 tipg = DEFAULT_82542_TIPG_IPGT; 3695 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3696 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3697 break; 3698 default: 3699 if (hw->phy.media_type == e1000_media_type_fiber || 3700 hw->phy.media_type == e1000_media_type_internal_serdes) 3701 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3702 else 3703 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3704 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3705 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3706 } 3707 3708 if (hw->mac.type < igb_mac_min) { 3709 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3710 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3711 3712 if (sc->tx_int_delay.value > 0) 3713 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3714 } 3715 3716 if (hw->mac.type >= e1000_82540) 3717 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3718 3719 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3720 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3721 tarc |= TARC_SPEED_MODE_BIT; 3722 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3723 } else if (hw->mac.type == e1000_80003es2lan) { 3724 /* errata: program both queues to unweighted RR */ 3725 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3726 tarc |= 1; 3727 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3728 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3729 tarc |= 1; 3730 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3731 } else if (hw->mac.type == e1000_82574) { 3732 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3733 tarc |= TARC_ERRATA_BIT; 3734 if ( sc->tx_num_queues > 1) { 3735 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3736 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3737 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3738 } else 3739 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3740 } 3741 3742 /* Program the Transmit Control Register */ 3743 tctl = E1000_READ_REG(hw, E1000_TCTL); 3744 tctl &= ~E1000_TCTL_CT; 3745 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3746 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3747 3748 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3749 tctl |= E1000_TCTL_MULR; 3750 3751 /* This write will effectively turn on the transmit unit. */ 3752 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3753 3754 /* SPT and KBL errata workarounds */ 3755 if (hw->mac.type == e1000_pch_spt) { 3756 u32 reg; 3757 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3758 reg |= E1000_RCTL_RDMTS_HEX; 3759 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3760 /* i218-i219 Specification Update 1.5.4.5 */ 3761 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3762 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3763 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3764 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3765 } 3766 } 3767 3768 /********************************************************************* 3769 * 3770 * Enable receive unit. 3771 * 3772 **********************************************************************/ 3773 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3774 3775 static void 3776 em_initialize_receive_unit(if_ctx_t ctx) 3777 { 3778 struct e1000_softc *sc = iflib_get_softc(ctx); 3779 if_softc_ctx_t scctx = sc->shared; 3780 if_t ifp = iflib_get_ifp(ctx); 3781 struct e1000_hw *hw = &sc->hw; 3782 struct em_rx_queue *que; 3783 int i; 3784 uint32_t rctl, rxcsum; 3785 3786 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3787 3788 /* 3789 * Make sure receives are disabled while setting 3790 * up the descriptor ring 3791 */ 3792 rctl = E1000_READ_REG(hw, E1000_RCTL); 3793 /* Do not disable if ever enabled on this hardware */ 3794 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3795 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3796 3797 /* Setup the Receive Control Register */ 3798 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3799 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3800 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3801 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3802 3803 /* Do not store bad packets */ 3804 rctl &= ~E1000_RCTL_SBP; 3805 3806 /* Enable Long Packet receive */ 3807 if (if_getmtu(ifp) > ETHERMTU) 3808 rctl |= E1000_RCTL_LPE; 3809 else 3810 rctl &= ~E1000_RCTL_LPE; 3811 3812 /* Strip the CRC */ 3813 if (!em_disable_crc_stripping) 3814 rctl |= E1000_RCTL_SECRC; 3815 3816 /* lem/em default interrupt moderation */ 3817 if (hw->mac.type < igb_mac_min) { 3818 if (hw->mac.type >= e1000_82540) { 3819 E1000_WRITE_REG(hw, E1000_RADV, 3820 sc->rx_abs_int_delay.value); 3821 3822 /* Set the default interrupt throttling rate */ 3823 E1000_WRITE_REG(hw, E1000_ITR, 3824 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3825 } 3826 3827 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3828 * long latencies are observed, like Lenovo X60. This 3829 * change eliminates the problem, but since having positive 3830 * values in RDTR is a known source of problems on other 3831 * platforms another solution is being sought. 3832 */ 3833 if (hw->mac.type == e1000_82573) 3834 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3835 else 3836 E1000_WRITE_REG(hw, E1000_RDTR, 3837 sc->rx_int_delay.value); 3838 } 3839 3840 if (hw->mac.type >= em_mac_min) { 3841 uint32_t rfctl; 3842 /* Use extended rx descriptor formats */ 3843 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3844 rfctl |= E1000_RFCTL_EXTEN; 3845 3846 /* 3847 * When using MSI-X interrupts we need to throttle 3848 * using the EITR register (82574 only) 3849 */ 3850 if (hw->mac.type == e1000_82574) { 3851 for (int i = 0; i < 4; i++) 3852 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3853 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3854 /* Disable accelerated acknowledge */ 3855 rfctl |= E1000_RFCTL_ACK_DIS; 3856 } 3857 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3858 } 3859 3860 /* Set up L3 and L4 csum Rx descriptor offloads */ 3861 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3862 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3863 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3864 if (hw->mac.type > e1000_82575) 3865 rxcsum |= E1000_RXCSUM_CRCOFL; 3866 else if (hw->mac.type < em_mac_min && 3867 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3868 rxcsum |= E1000_RXCSUM_IPV6OFL; 3869 } else { 3870 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3871 if (hw->mac.type > e1000_82575) 3872 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3873 else if (hw->mac.type < em_mac_min) 3874 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3875 } 3876 3877 if (sc->rx_num_queues > 1) { 3878 /* RSS hash needed in the Rx descriptor */ 3879 rxcsum |= E1000_RXCSUM_PCSD; 3880 3881 if (hw->mac.type >= igb_mac_min) 3882 igb_initialize_rss_mapping(sc); 3883 else 3884 em_initialize_rss_mapping(sc); 3885 } 3886 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3887 3888 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3889 struct rx_ring *rxr = &que->rxr; 3890 /* Setup the Base and Length of the Rx Descriptor Ring */ 3891 u64 bus_addr = rxr->rx_paddr; 3892 #if 0 3893 u32 rdt = sc->rx_num_queues -1; /* default */ 3894 #endif 3895 3896 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3897 scctx->isc_nrxd[0] * 3898 sizeof(union e1000_rx_desc_extended)); 3899 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3900 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3901 /* Setup the Head and Tail Descriptor Pointers */ 3902 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3903 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3904 } 3905 3906 /* 3907 * Set PTHRESH for improved jumbo performance 3908 * According to 10.2.5.11 of Intel 82574 Datasheet, 3909 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3910 * Only write to RXDCTL(1) if there is a need for different 3911 * settings. 3912 */ 3913 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3914 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3915 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3916 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3917 } else if (hw->mac.type == e1000_82574) { 3918 for (int i = 0; i < sc->rx_num_queues; i++) { 3919 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3920 rxdctl |= 0x20; /* PTHRESH */ 3921 rxdctl |= 4 << 8; /* HTHRESH */ 3922 rxdctl |= 4 << 16;/* WTHRESH */ 3923 rxdctl |= 1 << 24; /* Switch to granularity */ 3924 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3925 } 3926 } else if (hw->mac.type >= igb_mac_min) { 3927 u32 psize, srrctl = 0; 3928 3929 if (if_getmtu(ifp) > ETHERMTU) { 3930 psize = scctx->isc_max_frame_size; 3931 /* are we on a vlan? */ 3932 if (if_vlantrunkinuse(ifp)) 3933 psize += VLAN_TAG_SIZE; 3934 3935 if (sc->vf_ifp) 3936 e1000_rlpml_set_vf(hw, psize); 3937 else 3938 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3939 } 3940 3941 /* Set maximum packet buffer len */ 3942 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3943 E1000_SRRCTL_BSIZEPKT_SHIFT; 3944 3945 /* 3946 * If TX flow control is disabled and there's >1 queue 3947 * defined, enable DROP. 3948 * 3949 * This drops frames rather than hanging the RX MAC for all 3950 * queues. 3951 */ 3952 if ((sc->rx_num_queues > 1) && 3953 (sc->fc == e1000_fc_none || 3954 sc->fc == e1000_fc_rx_pause)) { 3955 srrctl |= E1000_SRRCTL_DROP_EN; 3956 } 3957 /* Setup the Base and Length of the Rx Descriptor Rings */ 3958 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3959 i++, que++) { 3960 struct rx_ring *rxr = &que->rxr; 3961 u64 bus_addr = rxr->rx_paddr; 3962 u32 rxdctl; 3963 3964 #ifdef notyet 3965 /* Configure for header split? -- ignore for now */ 3966 rxr->hdr_split = igb_header_split; 3967 #else 3968 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3969 #endif 3970 3971 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3972 scctx->isc_nrxd[0] * 3973 sizeof(struct e1000_rx_desc)); 3974 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3975 (uint32_t)(bus_addr >> 32)); 3976 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3977 (uint32_t)bus_addr); 3978 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3979 /* Enable this Queue */ 3980 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3981 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3982 rxdctl &= 0xFFF00000; 3983 rxdctl |= IGB_RX_PTHRESH; 3984 rxdctl |= IGB_RX_HTHRESH << 8; 3985 rxdctl |= IGB_RX_WTHRESH << 16; 3986 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3987 } 3988 } else if (hw->mac.type >= e1000_pch2lan) { 3989 if (if_getmtu(ifp) > ETHERMTU) 3990 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3991 else 3992 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3993 } 3994 3995 /* Make sure VLAN Filters are off */ 3996 rctl &= ~E1000_RCTL_VFE; 3997 3998 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3999 if (hw->mac.type < igb_mac_min) { 4000 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 4001 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 4002 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 4003 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 4004 else if (sc->rx_mbuf_sz > 8192) 4005 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 4006 else { 4007 rctl |= E1000_RCTL_SZ_2048; 4008 rctl &= ~E1000_RCTL_BSEX; 4009 } 4010 } else 4011 rctl |= E1000_RCTL_SZ_2048; 4012 4013 /* 4014 * rctl bits 11:10 are as follows 4015 * lem: reserved 4016 * em: DTYPE 4017 * igb: reserved 4018 * and should be 00 on all of the above 4019 */ 4020 rctl &= ~0x00000C00; 4021 4022 /* Write out the settings */ 4023 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4024 4025 return; 4026 } 4027 4028 static void 4029 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 4030 { 4031 struct e1000_softc *sc = iflib_get_softc(ctx); 4032 u32 index, bit; 4033 4034 index = (vtag >> 5) & 0x7F; 4035 bit = vtag & 0x1F; 4036 sc->shadow_vfta[index] |= (1 << bit); 4037 ++sc->num_vlans; 4038 em_if_vlan_filter_write(sc); 4039 } 4040 4041 static void 4042 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4043 { 4044 struct e1000_softc *sc = iflib_get_softc(ctx); 4045 u32 index, bit; 4046 4047 index = (vtag >> 5) & 0x7F; 4048 bit = vtag & 0x1F; 4049 sc->shadow_vfta[index] &= ~(1 << bit); 4050 --sc->num_vlans; 4051 em_if_vlan_filter_write(sc); 4052 } 4053 4054 static bool 4055 em_if_vlan_filter_capable(if_ctx_t ctx) 4056 { 4057 if_t ifp = iflib_get_ifp(ctx); 4058 4059 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4060 !em_disable_crc_stripping) 4061 return (true); 4062 4063 return (false); 4064 } 4065 4066 static bool 4067 em_if_vlan_filter_used(if_ctx_t ctx) 4068 { 4069 struct e1000_softc *sc = iflib_get_softc(ctx); 4070 4071 if (!em_if_vlan_filter_capable(ctx)) 4072 return (false); 4073 4074 for (int i = 0; i < EM_VFTA_SIZE; i++) 4075 if (sc->shadow_vfta[i] != 0) 4076 return (true); 4077 4078 return (false); 4079 } 4080 4081 static void 4082 em_if_vlan_filter_enable(struct e1000_softc *sc) 4083 { 4084 struct e1000_hw *hw = &sc->hw; 4085 u32 reg; 4086 4087 reg = E1000_READ_REG(hw, E1000_RCTL); 4088 reg &= ~E1000_RCTL_CFIEN; 4089 reg |= E1000_RCTL_VFE; 4090 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4091 } 4092 4093 static void 4094 em_if_vlan_filter_disable(struct e1000_softc *sc) 4095 { 4096 struct e1000_hw *hw = &sc->hw; 4097 u32 reg; 4098 4099 reg = E1000_READ_REG(hw, E1000_RCTL); 4100 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4101 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4102 } 4103 4104 static void 4105 em_if_vlan_filter_write(struct e1000_softc *sc) 4106 { 4107 struct e1000_hw *hw = &sc->hw; 4108 4109 if (sc->vf_ifp) 4110 return; 4111 4112 /* Disable interrupts for lem(4) devices during the filter change */ 4113 if (hw->mac.type < em_mac_min) 4114 em_if_intr_disable(sc->ctx); 4115 4116 for (int i = 0; i < EM_VFTA_SIZE; i++) 4117 if (sc->shadow_vfta[i] != 0) { 4118 /* XXXKB: incomplete VF support, we returned above */ 4119 if (sc->vf_ifp) 4120 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], 4121 true); 4122 else 4123 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4124 } 4125 4126 /* Re-enable interrupts for lem-class devices */ 4127 if (hw->mac.type < em_mac_min) 4128 em_if_intr_enable(sc->ctx); 4129 } 4130 4131 static void 4132 em_setup_vlan_hw_support(if_ctx_t ctx) 4133 { 4134 struct e1000_softc *sc = iflib_get_softc(ctx); 4135 struct e1000_hw *hw = &sc->hw; 4136 if_t ifp = iflib_get_ifp(ctx); 4137 u32 reg; 4138 4139 /* XXXKB: Return early if we are a VF until VF decap and filter 4140 * management is ready and tested. 4141 */ 4142 if (sc->vf_ifp) 4143 return; 4144 4145 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4146 !em_disable_crc_stripping) { 4147 reg = E1000_READ_REG(hw, E1000_CTRL); 4148 reg |= E1000_CTRL_VME; 4149 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4150 } else { 4151 reg = E1000_READ_REG(hw, E1000_CTRL); 4152 reg &= ~E1000_CTRL_VME; 4153 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4154 } 4155 4156 /* If we aren't doing HW filtering, we're done */ 4157 if (!em_if_vlan_filter_capable(ctx)) { 4158 em_if_vlan_filter_disable(sc); 4159 return; 4160 } 4161 4162 /* 4163 * A soft reset zero's out the VFTA, so 4164 * we need to repopulate it now. 4165 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4166 * traffic through. This will write the entire table. 4167 */ 4168 em_if_vlan_register(ctx, 0); 4169 4170 /* Enable the Filter Table */ 4171 em_if_vlan_filter_enable(sc); 4172 } 4173 4174 static void 4175 em_if_intr_enable(if_ctx_t ctx) 4176 { 4177 struct e1000_softc *sc = iflib_get_softc(ctx); 4178 struct e1000_hw *hw = &sc->hw; 4179 u32 ims_mask = IMS_ENABLE_MASK; 4180 4181 if (sc->intr_type == IFLIB_INTR_MSIX) { 4182 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4183 ims_mask |= sc->ims; 4184 } 4185 4186 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4187 E1000_WRITE_FLUSH(hw); 4188 } 4189 4190 static void 4191 em_if_intr_disable(if_ctx_t ctx) 4192 { 4193 struct e1000_softc *sc = iflib_get_softc(ctx); 4194 struct e1000_hw *hw = &sc->hw; 4195 4196 if (sc->intr_type == IFLIB_INTR_MSIX) 4197 E1000_WRITE_REG(hw, EM_EIAC, 0); 4198 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4199 E1000_WRITE_FLUSH(hw); 4200 } 4201 4202 static void 4203 igb_if_intr_enable(if_ctx_t ctx) 4204 { 4205 struct e1000_softc *sc = iflib_get_softc(ctx); 4206 struct e1000_hw *hw = &sc->hw; 4207 u32 mask; 4208 4209 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4210 mask = (sc->que_mask | sc->link_mask); 4211 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4212 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4213 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4214 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4215 } else 4216 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4217 E1000_WRITE_FLUSH(hw); 4218 } 4219 4220 static void 4221 igb_if_intr_disable(if_ctx_t ctx) 4222 { 4223 struct e1000_softc *sc = iflib_get_softc(ctx); 4224 struct e1000_hw *hw = &sc->hw; 4225 4226 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4227 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4228 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4229 } 4230 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4231 E1000_WRITE_FLUSH(hw); 4232 } 4233 4234 /* 4235 * Bit of a misnomer, what this really means is 4236 * to enable OS management of the system... aka 4237 * to disable special hardware management features 4238 */ 4239 static void 4240 em_init_manageability(struct e1000_softc *sc) 4241 { 4242 /* A shared code workaround */ 4243 #define E1000_82542_MANC2H E1000_MANC2H 4244 if (sc->has_manage) { 4245 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4246 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4247 4248 /* disable hardware interception of ARP */ 4249 manc &= ~(E1000_MANC_ARP_EN); 4250 4251 /* enable receiving management packets to the host */ 4252 manc |= E1000_MANC_EN_MNG2HOST; 4253 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4254 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4255 manc2h |= E1000_MNG2HOST_PORT_623; 4256 manc2h |= E1000_MNG2HOST_PORT_664; 4257 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4258 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4259 } 4260 } 4261 4262 /* 4263 * Give control back to hardware management 4264 * controller if there is one. 4265 */ 4266 static void 4267 em_release_manageability(struct e1000_softc *sc) 4268 { 4269 if (sc->has_manage) { 4270 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4271 4272 /* re-enable hardware interception of ARP */ 4273 manc |= E1000_MANC_ARP_EN; 4274 manc &= ~E1000_MANC_EN_MNG2HOST; 4275 4276 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4277 } 4278 } 4279 4280 /* 4281 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4282 * For ASF and Pass Through versions of f/w this means 4283 * that the driver is loaded. For AMT version type f/w 4284 * this means that the network i/f is open. 4285 */ 4286 static void 4287 em_get_hw_control(struct e1000_softc *sc) 4288 { 4289 u32 ctrl_ext, swsm; 4290 4291 if (sc->vf_ifp) 4292 return; 4293 4294 if (sc->hw.mac.type == e1000_82573) { 4295 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4296 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4297 swsm | E1000_SWSM_DRV_LOAD); 4298 return; 4299 } 4300 /* else */ 4301 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4302 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4303 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4304 } 4305 4306 /* 4307 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4308 * For ASF and Pass Through versions of f/w this means that 4309 * the driver is no longer loaded. For AMT versions of the 4310 * f/w this means that the network i/f is closed. 4311 */ 4312 static void 4313 em_release_hw_control(struct e1000_softc *sc) 4314 { 4315 u32 ctrl_ext, swsm; 4316 4317 if (!sc->has_manage) 4318 return; 4319 4320 if (sc->hw.mac.type == e1000_82573) { 4321 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4322 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4323 swsm & ~E1000_SWSM_DRV_LOAD); 4324 return; 4325 } 4326 /* else */ 4327 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4328 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4329 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4330 return; 4331 } 4332 4333 static int 4334 em_is_valid_ether_addr(u8 *addr) 4335 { 4336 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4337 4338 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4339 return (false); 4340 } 4341 4342 return (true); 4343 } 4344 4345 static bool 4346 em_automask_tso(if_ctx_t ctx) 4347 { 4348 struct e1000_softc *sc = iflib_get_softc(ctx); 4349 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4350 if_t ifp = iflib_get_ifp(ctx); 4351 4352 if (!em_unsupported_tso && sc->link_speed && 4353 sc->link_speed != SPEED_1000 && 4354 scctx->isc_capenable & IFCAP_TSO) { 4355 device_printf(sc->dev, 4356 "Disabling TSO for 10/100 Ethernet.\n"); 4357 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4358 scctx->isc_capenable &= ~IFCAP_TSO; 4359 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4360 /* iflib_init_locked handles ifnet hwassistbits */ 4361 iflib_request_reset(ctx); 4362 return true; 4363 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4364 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4365 scctx->isc_capenable |= sc->tso_automasked; 4366 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4367 sc->tso_automasked = 0; 4368 /* iflib_init_locked handles ifnet hwassistbits */ 4369 iflib_request_reset(ctx); 4370 return true; 4371 } 4372 4373 return false; 4374 } 4375 4376 /* 4377 ** Parse the interface capabilities with regard 4378 ** to both system management and wake-on-lan for 4379 ** later use. 4380 */ 4381 static void 4382 em_get_wakeup(if_ctx_t ctx) 4383 { 4384 struct e1000_softc *sc = iflib_get_softc(ctx); 4385 device_t dev = iflib_get_dev(ctx); 4386 u16 eeprom_data = 0, device_id, apme_mask; 4387 4388 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4389 apme_mask = EM_EEPROM_APME; 4390 4391 switch (sc->hw.mac.type) { 4392 case e1000_82542: 4393 case e1000_82543: 4394 break; 4395 case e1000_82544: 4396 e1000_read_nvm(&sc->hw, 4397 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4398 apme_mask = EM_82544_APME; 4399 break; 4400 case e1000_82546: 4401 case e1000_82546_rev_3: 4402 if (sc->hw.bus.func == 1) { 4403 e1000_read_nvm(&sc->hw, 4404 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4405 break; 4406 } else 4407 e1000_read_nvm(&sc->hw, 4408 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4409 break; 4410 case e1000_82573: 4411 case e1000_82583: 4412 sc->has_amt = true; 4413 /* FALLTHROUGH */ 4414 case e1000_82571: 4415 case e1000_82572: 4416 case e1000_80003es2lan: 4417 if (sc->hw.bus.func == 1) { 4418 e1000_read_nvm(&sc->hw, 4419 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4420 break; 4421 } else 4422 e1000_read_nvm(&sc->hw, 4423 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4424 break; 4425 case e1000_ich8lan: 4426 case e1000_ich9lan: 4427 case e1000_ich10lan: 4428 case e1000_pchlan: 4429 case e1000_pch2lan: 4430 case e1000_pch_lpt: 4431 case e1000_pch_spt: 4432 case e1000_82575: /* listing all igb devices */ 4433 case e1000_82576: 4434 case e1000_82580: 4435 case e1000_i350: 4436 case e1000_i354: 4437 case e1000_i210: 4438 case e1000_i211: 4439 case e1000_vfadapt: 4440 case e1000_vfadapt_i350: 4441 apme_mask = E1000_WUC_APME; 4442 sc->has_amt = true; 4443 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4444 break; 4445 default: 4446 e1000_read_nvm(&sc->hw, 4447 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4448 break; 4449 } 4450 if (eeprom_data & apme_mask) 4451 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4452 /* 4453 * We have the eeprom settings, now apply the special cases 4454 * where the eeprom may be wrong or the board won't support 4455 * wake on lan on a particular port 4456 */ 4457 device_id = pci_get_device(dev); 4458 switch (device_id) { 4459 case E1000_DEV_ID_82546GB_PCIE: 4460 sc->wol = 0; 4461 break; 4462 case E1000_DEV_ID_82546EB_FIBER: 4463 case E1000_DEV_ID_82546GB_FIBER: 4464 /* Wake events only supported on port A for dual fiber 4465 * regardless of eeprom setting */ 4466 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4467 E1000_STATUS_FUNC_1) 4468 sc->wol = 0; 4469 break; 4470 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4471 /* if quad port adapter, disable WoL on all but port A */ 4472 if (global_quad_port_a != 0) 4473 sc->wol = 0; 4474 /* Reset for multiple quad port adapters */ 4475 if (++global_quad_port_a == 4) 4476 global_quad_port_a = 0; 4477 break; 4478 case E1000_DEV_ID_82571EB_FIBER: 4479 /* Wake events only supported on port A for dual fiber 4480 * regardless of eeprom setting */ 4481 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4482 E1000_STATUS_FUNC_1) 4483 sc->wol = 0; 4484 break; 4485 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4486 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4487 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4488 /* if quad port adapter, disable WoL on all but port A */ 4489 if (global_quad_port_a != 0) 4490 sc->wol = 0; 4491 /* Reset for multiple quad port adapters */ 4492 if (++global_quad_port_a == 4) 4493 global_quad_port_a = 0; 4494 break; 4495 } 4496 return; 4497 } 4498 4499 4500 /* 4501 * Enable PCI Wake On Lan capability 4502 */ 4503 static void 4504 em_enable_wakeup(if_ctx_t ctx) 4505 { 4506 struct e1000_softc *sc = iflib_get_softc(ctx); 4507 device_t dev = iflib_get_dev(ctx); 4508 if_t ifp = iflib_get_ifp(ctx); 4509 int error = 0; 4510 u32 pmc, ctrl, ctrl_ext, rctl; 4511 u16 status; 4512 4513 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4514 return; 4515 4516 /* 4517 * Determine type of Wakeup: note that wol 4518 * is set with all bits on by default. 4519 */ 4520 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4521 sc->wol &= ~E1000_WUFC_MAG; 4522 4523 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4524 sc->wol &= ~E1000_WUFC_EX; 4525 4526 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4527 sc->wol &= ~E1000_WUFC_MC; 4528 else { 4529 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4530 rctl |= E1000_RCTL_MPE; 4531 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4532 } 4533 4534 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4535 goto pme; 4536 4537 /* Advertise the wakeup capability */ 4538 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4539 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4540 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4541 4542 /* Keep the laser running on Fiber adapters */ 4543 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4544 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4545 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4546 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4547 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4548 } 4549 4550 if ((sc->hw.mac.type == e1000_ich8lan) || 4551 (sc->hw.mac.type == e1000_pchlan) || 4552 (sc->hw.mac.type == e1000_ich9lan) || 4553 (sc->hw.mac.type == e1000_ich10lan)) 4554 e1000_suspend_workarounds_ich8lan(&sc->hw); 4555 4556 if ( sc->hw.mac.type >= e1000_pchlan) { 4557 error = em_enable_phy_wakeup(sc); 4558 if (error) 4559 goto pme; 4560 } else { 4561 /* Enable wakeup by the MAC */ 4562 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4563 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4564 } 4565 4566 if (sc->hw.phy.type == e1000_phy_igp_3) 4567 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4568 4569 pme: 4570 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4571 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4572 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4573 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4574 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4575 4576 return; 4577 } 4578 4579 /* 4580 * WOL in the newer chipset interfaces (pchlan) 4581 * require thing to be copied into the phy 4582 */ 4583 static int 4584 em_enable_phy_wakeup(struct e1000_softc *sc) 4585 { 4586 struct e1000_hw *hw = &sc->hw; 4587 u32 mreg, ret = 0; 4588 u16 preg; 4589 4590 /* copy MAC RARs to PHY RARs */ 4591 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4592 4593 /* copy MAC MTA to PHY MTA */ 4594 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4595 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4596 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4597 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4598 (u16)((mreg >> 16) & 0xFFFF)); 4599 } 4600 4601 /* configure PHY Rx Control register */ 4602 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4603 mreg = E1000_READ_REG(hw, E1000_RCTL); 4604 if (mreg & E1000_RCTL_UPE) 4605 preg |= BM_RCTL_UPE; 4606 if (mreg & E1000_RCTL_MPE) 4607 preg |= BM_RCTL_MPE; 4608 preg &= ~(BM_RCTL_MO_MASK); 4609 if (mreg & E1000_RCTL_MO_3) 4610 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4611 << BM_RCTL_MO_SHIFT); 4612 if (mreg & E1000_RCTL_BAM) 4613 preg |= BM_RCTL_BAM; 4614 if (mreg & E1000_RCTL_PMCF) 4615 preg |= BM_RCTL_PMCF; 4616 mreg = E1000_READ_REG(hw, E1000_CTRL); 4617 if (mreg & E1000_CTRL_RFCE) 4618 preg |= BM_RCTL_RFCE; 4619 e1000_write_phy_reg(hw, BM_RCTL, preg); 4620 4621 /* enable PHY wakeup in MAC register */ 4622 E1000_WRITE_REG(hw, E1000_WUC, 4623 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4624 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4625 4626 /* configure and enable PHY wakeup in PHY registers */ 4627 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4628 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4629 4630 /* activate PHY wakeup */ 4631 ret = hw->phy.ops.acquire(hw); 4632 if (ret) { 4633 printf("Could not acquire PHY\n"); 4634 return ret; 4635 } 4636 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4637 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4638 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4639 if (ret) { 4640 printf("Could not read PHY page 769\n"); 4641 goto out; 4642 } 4643 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4644 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4645 if (ret) 4646 printf("Could not set PHY Host Wakeup bit\n"); 4647 out: 4648 hw->phy.ops.release(hw); 4649 4650 return ret; 4651 } 4652 4653 static void 4654 em_if_led_func(if_ctx_t ctx, int onoff) 4655 { 4656 struct e1000_softc *sc = iflib_get_softc(ctx); 4657 4658 if (onoff) { 4659 e1000_setup_led(&sc->hw); 4660 e1000_led_on(&sc->hw); 4661 } else { 4662 e1000_led_off(&sc->hw); 4663 e1000_cleanup_led(&sc->hw); 4664 } 4665 } 4666 4667 /* 4668 * Disable the L0S and L1 LINK states 4669 */ 4670 static void 4671 em_disable_aspm(struct e1000_softc *sc) 4672 { 4673 int base, reg; 4674 u16 link_cap,link_ctrl; 4675 device_t dev = sc->dev; 4676 4677 switch (sc->hw.mac.type) { 4678 case e1000_82573: 4679 case e1000_82574: 4680 case e1000_82583: 4681 break; 4682 default: 4683 return; 4684 } 4685 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4686 return; 4687 reg = base + PCIER_LINK_CAP; 4688 link_cap = pci_read_config(dev, reg, 2); 4689 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4690 return; 4691 reg = base + PCIER_LINK_CTL; 4692 link_ctrl = pci_read_config(dev, reg, 2); 4693 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4694 pci_write_config(dev, reg, link_ctrl, 2); 4695 return; 4696 } 4697 4698 /********************************************************************** 4699 * 4700 * Update the board statistics counters. 4701 * 4702 **********************************************************************/ 4703 static void 4704 em_update_stats_counters(struct e1000_softc *sc) 4705 { 4706 u64 prev_xoffrxc = sc->stats.xoffrxc; 4707 4708 if(sc->hw.phy.media_type == e1000_media_type_copper || 4709 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4710 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4711 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4712 } 4713 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4714 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4715 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4716 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4717 4718 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4719 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4720 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4721 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4722 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4723 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4724 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4725 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4726 /* 4727 ** For watchdog management we need to know if we have been 4728 ** paused during the last interval, so capture that here. 4729 */ 4730 if (sc->stats.xoffrxc != prev_xoffrxc) 4731 sc->shared->isc_pause_frames = 1; 4732 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4733 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4734 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4735 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4736 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4737 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4738 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4739 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4740 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4741 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4742 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4743 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4744 4745 /* For the 64-bit byte counters the low dword must be read first. */ 4746 /* Both registers clear on the read of the high dword */ 4747 4748 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4749 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4750 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4751 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4752 4753 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4754 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4755 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4756 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4757 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4758 4759 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4760 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4761 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4762 4763 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4764 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4765 4766 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4767 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4768 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4769 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4770 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4771 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4772 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4773 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4774 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4775 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4776 4777 /* Interrupt Counts */ 4778 4779 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4780 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4781 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4782 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4783 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4784 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4785 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4786 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4787 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4788 4789 if (sc->hw.mac.type >= e1000_82543) { 4790 sc->stats.algnerrc += 4791 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4792 sc->stats.rxerrc += 4793 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4794 sc->stats.tncrs += 4795 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4796 sc->stats.cexterr += 4797 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4798 sc->stats.tsctc += 4799 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4800 sc->stats.tsctfc += 4801 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4802 } 4803 } 4804 4805 static uint64_t 4806 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4807 { 4808 struct e1000_softc *sc = iflib_get_softc(ctx); 4809 if_t ifp = iflib_get_ifp(ctx); 4810 4811 switch (cnt) { 4812 case IFCOUNTER_COLLISIONS: 4813 return (sc->stats.colc); 4814 case IFCOUNTER_IERRORS: 4815 return (sc->dropped_pkts + sc->stats.rxerrc + 4816 sc->stats.crcerrs + sc->stats.algnerrc + 4817 sc->stats.ruc + sc->stats.roc + 4818 sc->stats.mpc + sc->stats.cexterr); 4819 case IFCOUNTER_OERRORS: 4820 return (sc->stats.ecol + sc->stats.latecol + 4821 sc->watchdog_events); 4822 default: 4823 return (if_get_counter_default(ifp, cnt)); 4824 } 4825 } 4826 4827 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4828 * @ctx: iflib context 4829 * @event: event code to check 4830 * 4831 * Defaults to returning false for unknown events. 4832 * 4833 * @returns true if iflib needs to reinit the interface 4834 */ 4835 static bool 4836 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4837 { 4838 switch (event) { 4839 case IFLIB_RESTART_VLAN_CONFIG: 4840 default: 4841 return (false); 4842 } 4843 } 4844 4845 /* Export a single 32-bit register via a read-only sysctl. */ 4846 static int 4847 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4848 { 4849 struct e1000_softc *sc; 4850 u_int val; 4851 4852 sc = oidp->oid_arg1; 4853 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4854 return (sysctl_handle_int(oidp, &val, 0, req)); 4855 } 4856 4857 /* Per queue holdoff interrupt rate handler */ 4858 static int 4859 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4860 { 4861 struct em_rx_queue *rque; 4862 struct em_tx_queue *tque; 4863 struct e1000_hw *hw; 4864 int error; 4865 u32 reg, usec, rate; 4866 4867 bool tx = oidp->oid_arg2; 4868 4869 if (tx) { 4870 tque = oidp->oid_arg1; 4871 hw = &tque->sc->hw; 4872 if (hw->mac.type >= igb_mac_min) 4873 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4874 else if (hw->mac.type == e1000_82574 && tque->msix) 4875 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4876 else 4877 reg = E1000_READ_REG(hw, E1000_ITR); 4878 } else { 4879 rque = oidp->oid_arg1; 4880 hw = &rque->sc->hw; 4881 if (hw->mac.type >= igb_mac_min) 4882 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4883 else if (hw->mac.type == e1000_82574 && rque->msix) 4884 reg = E1000_READ_REG(hw, 4885 E1000_EITR_82574(rque->msix)); 4886 else 4887 reg = E1000_READ_REG(hw, E1000_ITR); 4888 } 4889 4890 if (hw->mac.type < igb_mac_min) { 4891 if (reg > 0) 4892 rate = EM_INTS_TO_ITR(reg); 4893 else 4894 rate = 0; 4895 } else { 4896 usec = (reg & IGB_QVECTOR_MASK); 4897 if (usec > 0) 4898 rate = IGB_INTS_TO_EITR(usec); 4899 else 4900 rate = 0; 4901 } 4902 4903 error = sysctl_handle_int(oidp, &rate, 0, req); 4904 if (error || !req->newptr) 4905 return error; 4906 return 0; 4907 } 4908 4909 /* 4910 * Add sysctl variables, one per statistic, to the system. 4911 */ 4912 static void 4913 em_add_hw_stats(struct e1000_softc *sc) 4914 { 4915 device_t dev = iflib_get_dev(sc->ctx); 4916 struct em_tx_queue *tx_que = sc->tx_queues; 4917 struct em_rx_queue *rx_que = sc->rx_queues; 4918 4919 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4920 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4921 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4922 struct e1000_hw_stats *stats = &sc->stats; 4923 4924 struct sysctl_oid *stat_node, *queue_node, *int_node; 4925 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4926 4927 #define QUEUE_NAME_LEN 32 4928 char namebuf[QUEUE_NAME_LEN]; 4929 4930 /* Driver Statistics */ 4931 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4932 CTLFLAG_RD, &sc->dropped_pkts, 4933 "Driver dropped packets"); 4934 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4935 CTLFLAG_RD, &sc->link_irq, 4936 "Link MSI-X IRQ Handled"); 4937 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4938 CTLFLAG_RD, &sc->rx_overruns, 4939 "RX overruns"); 4940 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4941 CTLFLAG_RD, &sc->watchdog_events, 4942 "Watchdog timeouts"); 4943 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4944 CTLTYPE_UINT | CTLFLAG_RD, 4945 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4946 "Device Control Register"); 4947 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4948 CTLTYPE_UINT | CTLFLAG_RD, 4949 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4950 "Receiver Control Register"); 4951 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4952 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4953 "Flow Control High Watermark"); 4954 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4955 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4956 "Flow Control Low Watermark"); 4957 4958 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4959 struct tx_ring *txr = &tx_que->txr; 4960 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4961 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4962 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4963 queue_list = SYSCTL_CHILDREN(queue_node); 4964 4965 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4966 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4967 true, em_sysctl_interrupt_rate_handler, 4968 "IU", "Interrupt Rate"); 4969 4970 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4971 CTLTYPE_UINT | CTLFLAG_RD, sc, 4972 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4973 "Transmit Descriptor Head"); 4974 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4975 CTLTYPE_UINT | CTLFLAG_RD, sc, 4976 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4977 "Transmit Descriptor Tail"); 4978 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4979 CTLFLAG_RD, &txr->tx_irq, 4980 "Queue MSI-X Transmit Interrupts"); 4981 } 4982 4983 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4984 struct rx_ring *rxr = &rx_que->rxr; 4985 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4986 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4987 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4988 queue_list = SYSCTL_CHILDREN(queue_node); 4989 4990 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4991 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 4992 false, em_sysctl_interrupt_rate_handler, 4993 "IU", "Interrupt Rate"); 4994 4995 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4996 CTLTYPE_UINT | CTLFLAG_RD, sc, 4997 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4998 "Receive Descriptor Head"); 4999 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 5000 CTLTYPE_UINT | CTLFLAG_RD, sc, 5001 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 5002 "Receive Descriptor Tail"); 5003 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 5004 CTLFLAG_RD, &rxr->rx_irq, 5005 "Queue MSI-X Receive Interrupts"); 5006 } 5007 5008 /* MAC stats get their own sub node */ 5009 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 5010 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 5011 stat_list = SYSCTL_CHILDREN(stat_node); 5012 5013 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 5014 CTLFLAG_RD, &stats->ecol, 5015 "Excessive collisions"); 5016 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 5017 CTLFLAG_RD, &stats->scc, 5018 "Single collisions"); 5019 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 5020 CTLFLAG_RD, &stats->mcc, 5021 "Multiple collisions"); 5022 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 5023 CTLFLAG_RD, &stats->latecol, 5024 "Late collisions"); 5025 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 5026 CTLFLAG_RD, &stats->colc, 5027 "Collision Count"); 5028 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 5029 CTLFLAG_RD, &sc->stats.symerrs, 5030 "Symbol Errors"); 5031 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 5032 CTLFLAG_RD, &sc->stats.sec, 5033 "Sequence Errors"); 5034 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5035 CTLFLAG_RD, &sc->stats.dc, 5036 "Defer Count"); 5037 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5038 CTLFLAG_RD, &sc->stats.mpc, 5039 "Missed Packets"); 5040 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5041 CTLFLAG_RD, &sc->stats.rlec, 5042 "Receive Length Errors"); 5043 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5044 CTLFLAG_RD, &sc->stats.rnbc, 5045 "Receive No Buffers"); 5046 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5047 CTLFLAG_RD, &sc->stats.ruc, 5048 "Receive Undersize"); 5049 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5050 CTLFLAG_RD, &sc->stats.rfc, 5051 "Fragmented Packets Received "); 5052 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5053 CTLFLAG_RD, &sc->stats.roc, 5054 "Oversized Packets Received"); 5055 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5056 CTLFLAG_RD, &sc->stats.rjc, 5057 "Recevied Jabber"); 5058 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5059 CTLFLAG_RD, &sc->stats.rxerrc, 5060 "Receive Errors"); 5061 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5062 CTLFLAG_RD, &sc->stats.crcerrs, 5063 "CRC errors"); 5064 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5065 CTLFLAG_RD, &sc->stats.algnerrc, 5066 "Alignment Errors"); 5067 /* On 82575 these are collision counts */ 5068 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5069 CTLFLAG_RD, &sc->stats.cexterr, 5070 "Collision/Carrier extension errors"); 5071 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5072 CTLFLAG_RD, &sc->stats.xonrxc, 5073 "XON Received"); 5074 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5075 CTLFLAG_RD, &sc->stats.xontxc, 5076 "XON Transmitted"); 5077 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5078 CTLFLAG_RD, &sc->stats.xoffrxc, 5079 "XOFF Received"); 5080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5081 CTLFLAG_RD, &sc->stats.xofftxc, 5082 "XOFF Transmitted"); 5083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5084 CTLFLAG_RD, &sc->stats.fcruc, 5085 "Unsupported Flow Control Received"); 5086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5087 CTLFLAG_RD, &sc->stats.mgprc, 5088 "Management Packets Received"); 5089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5090 CTLFLAG_RD, &sc->stats.mgpdc, 5091 "Management Packets Dropped"); 5092 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5093 CTLFLAG_RD, &sc->stats.mgptc, 5094 "Management Packets Transmitted"); 5095 5096 /* Packet Reception Stats */ 5097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5098 CTLFLAG_RD, &sc->stats.tpr, 5099 "Total Packets Received "); 5100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5101 CTLFLAG_RD, &sc->stats.gprc, 5102 "Good Packets Received"); 5103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5104 CTLFLAG_RD, &sc->stats.bprc, 5105 "Broadcast Packets Received"); 5106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5107 CTLFLAG_RD, &sc->stats.mprc, 5108 "Multicast Packets Received"); 5109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5110 CTLFLAG_RD, &sc->stats.prc64, 5111 "64 byte frames received "); 5112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5113 CTLFLAG_RD, &sc->stats.prc127, 5114 "65-127 byte frames received"); 5115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5116 CTLFLAG_RD, &sc->stats.prc255, 5117 "128-255 byte frames received"); 5118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5119 CTLFLAG_RD, &sc->stats.prc511, 5120 "256-511 byte frames received"); 5121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5122 CTLFLAG_RD, &sc->stats.prc1023, 5123 "512-1023 byte frames received"); 5124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5125 CTLFLAG_RD, &sc->stats.prc1522, 5126 "1023-1522 byte frames received"); 5127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5128 CTLFLAG_RD, &sc->stats.gorc, 5129 "Good Octets Received"); 5130 5131 /* Packet Transmission Stats */ 5132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5133 CTLFLAG_RD, &sc->stats.gotc, 5134 "Good Octets Transmitted"); 5135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5136 CTLFLAG_RD, &sc->stats.tpt, 5137 "Total Packets Transmitted"); 5138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5139 CTLFLAG_RD, &sc->stats.gptc, 5140 "Good Packets Transmitted"); 5141 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5142 CTLFLAG_RD, &sc->stats.bptc, 5143 "Broadcast Packets Transmitted"); 5144 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5145 CTLFLAG_RD, &sc->stats.mptc, 5146 "Multicast Packets Transmitted"); 5147 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5148 CTLFLAG_RD, &sc->stats.ptc64, 5149 "64 byte frames transmitted "); 5150 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5151 CTLFLAG_RD, &sc->stats.ptc127, 5152 "65-127 byte frames transmitted"); 5153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5154 CTLFLAG_RD, &sc->stats.ptc255, 5155 "128-255 byte frames transmitted"); 5156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5157 CTLFLAG_RD, &sc->stats.ptc511, 5158 "256-511 byte frames transmitted"); 5159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5160 CTLFLAG_RD, &sc->stats.ptc1023, 5161 "512-1023 byte frames transmitted"); 5162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5163 CTLFLAG_RD, &sc->stats.ptc1522, 5164 "1024-1522 byte frames transmitted"); 5165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5166 CTLFLAG_RD, &sc->stats.tsctc, 5167 "TSO Contexts Transmitted"); 5168 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5169 CTLFLAG_RD, &sc->stats.tsctfc, 5170 "TSO Contexts Failed"); 5171 5172 /* Interrupt Stats */ 5173 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5174 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5175 int_list = SYSCTL_CHILDREN(int_node); 5176 5177 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5178 CTLFLAG_RD, &sc->stats.iac, 5179 "Interrupt Assertion Count"); 5180 5181 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5182 CTLFLAG_RD, &sc->stats.icrxptc, 5183 "Interrupt Cause Rx Pkt Timer Expire Count"); 5184 5185 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5186 CTLFLAG_RD, &sc->stats.icrxatc, 5187 "Interrupt Cause Rx Abs Timer Expire Count"); 5188 5189 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5190 CTLFLAG_RD, &sc->stats.ictxptc, 5191 "Interrupt Cause Tx Pkt Timer Expire Count"); 5192 5193 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5194 CTLFLAG_RD, &sc->stats.ictxatc, 5195 "Interrupt Cause Tx Abs Timer Expire Count"); 5196 5197 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5198 CTLFLAG_RD, &sc->stats.ictxqec, 5199 "Interrupt Cause Tx Queue Empty Count"); 5200 5201 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5202 CTLFLAG_RD, &sc->stats.ictxqmtc, 5203 "Interrupt Cause Tx Queue Min Thresh Count"); 5204 5205 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5206 CTLFLAG_RD, &sc->stats.icrxdmtc, 5207 "Interrupt Cause Rx Desc Min Thresh Count"); 5208 5209 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5210 CTLFLAG_RD, &sc->stats.icrxoc, 5211 "Interrupt Cause Receiver Overrun Count"); 5212 } 5213 5214 static void 5215 em_fw_version_locked(if_ctx_t ctx) 5216 { 5217 struct e1000_softc *sc = iflib_get_softc(ctx); 5218 struct e1000_hw *hw = &sc->hw; 5219 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5220 uint16_t eep = 0; 5221 5222 /* 5223 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5224 * the NVM locking model, so we do it in em_if_attach_pre() and store 5225 * the info in the softc 5226 */ 5227 ASSERT_CTX_LOCK_HELD(hw); 5228 5229 *fw_ver = (struct e1000_fw_version){0}; 5230 5231 if (hw->mac.type >= igb_mac_min) { 5232 /* 5233 * Use the Shared Code for igb(4) 5234 */ 5235 e1000_get_fw_version(hw, fw_ver); 5236 } else { 5237 /* 5238 * Otherwise, EEPROM version should be present on (almost?) 5239 * all devices here 5240 */ 5241 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5242 INIT_DEBUGOUT("can't get EEPROM version"); 5243 return; 5244 } 5245 5246 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5247 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5248 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5249 } 5250 } 5251 5252 static void 5253 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5254 { 5255 const char *space = ""; 5256 5257 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5258 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5259 fw_ver->eep_minor, fw_ver->eep_build); 5260 space = " "; 5261 } 5262 5263 if (fw_ver->invm_major || fw_ver->invm_minor || 5264 fw_ver->invm_img_type) { 5265 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5266 space, fw_ver->invm_major, fw_ver->invm_minor, 5267 fw_ver->invm_img_type); 5268 space = " "; 5269 } 5270 5271 if (fw_ver->or_valid) { 5272 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5273 space, fw_ver->or_major, fw_ver->or_build, 5274 fw_ver->or_patch); 5275 space = " "; 5276 } 5277 5278 if (fw_ver->etrack_id) 5279 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5280 } 5281 5282 static void 5283 em_print_fw_version(struct e1000_softc *sc ) 5284 { 5285 device_t dev = sc->dev; 5286 struct sbuf *buf; 5287 int error = 0; 5288 5289 buf = sbuf_new_auto(); 5290 if (!buf) { 5291 device_printf(dev, "Could not allocate sbuf for output.\n"); 5292 return; 5293 } 5294 5295 em_sbuf_fw_version(&sc->fw_ver, buf); 5296 5297 error = sbuf_finish(buf); 5298 if (error) 5299 device_printf(dev, "Error finishing sbuf: %d\n", error); 5300 else if (sbuf_len(buf)) 5301 device_printf(dev, "%s\n", sbuf_data(buf)); 5302 5303 sbuf_delete(buf); 5304 } 5305 5306 static int 5307 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5308 { 5309 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5310 device_t dev = sc->dev; 5311 struct sbuf *buf; 5312 int error = 0; 5313 5314 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5315 if (!buf) { 5316 device_printf(dev, "Could not allocate sbuf for output.\n"); 5317 return (ENOMEM); 5318 } 5319 5320 em_sbuf_fw_version(&sc->fw_ver, buf); 5321 5322 error = sbuf_finish(buf); 5323 if (error) 5324 device_printf(dev, "Error finishing sbuf: %d\n", error); 5325 5326 sbuf_delete(buf); 5327 5328 return (0); 5329 } 5330 5331 /********************************************************************** 5332 * 5333 * This routine provides a way to dump out the adapter eeprom, 5334 * often a useful debug/service tool. This only dumps the first 5335 * 32 words, stuff that matters is in that extent. 5336 * 5337 **********************************************************************/ 5338 static int 5339 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5340 { 5341 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5342 int error; 5343 int result; 5344 5345 result = -1; 5346 error = sysctl_handle_int(oidp, &result, 0, req); 5347 5348 if (error || !req->newptr) 5349 return (error); 5350 5351 /* 5352 * This value will cause a hex dump of the 5353 * first 32 16-bit words of the EEPROM to 5354 * the screen. 5355 */ 5356 if (result == 1) 5357 em_print_nvm_info(sc); 5358 5359 return (error); 5360 } 5361 5362 static void 5363 em_print_nvm_info(struct e1000_softc *sc) 5364 { 5365 struct e1000_hw *hw = &sc->hw; 5366 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5367 u16 eeprom_data; 5368 int i, j, row = 0; 5369 5370 /* Its a bit crude, but it gets the job done */ 5371 printf("\nInterface EEPROM Dump:\n"); 5372 printf("Offset\n0x0000 "); 5373 5374 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5375 sx_xlock(iflib_ctx_lock); 5376 ASSERT_CTX_LOCK_HELD(hw); 5377 for (i = 0, j = 0; i < 32; i++, j++) { 5378 if (j == 8) { /* Make the offset block */ 5379 j = 0; ++row; 5380 printf("\n0x00%x0 ",row); 5381 } 5382 e1000_read_nvm(hw, i, 1, &eeprom_data); 5383 printf("%04x ", eeprom_data); 5384 } 5385 sx_xunlock(iflib_ctx_lock); 5386 printf("\n"); 5387 } 5388 5389 static int 5390 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5391 { 5392 struct em_int_delay_info *info; 5393 struct e1000_softc *sc; 5394 u32 regval; 5395 int error, usecs, ticks; 5396 5397 info = (struct em_int_delay_info *) arg1; 5398 usecs = info->value; 5399 error = sysctl_handle_int(oidp, &usecs, 0, req); 5400 if (error != 0 || req->newptr == NULL) 5401 return (error); 5402 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5403 return (EINVAL); 5404 info->value = usecs; 5405 ticks = EM_USECS_TO_TICKS(usecs); 5406 if (info->offset == E1000_ITR) /* units are 256ns here */ 5407 ticks *= 4; 5408 5409 sc = info->sc; 5410 5411 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5412 regval = (regval & ~0xffff) | (ticks & 0xffff); 5413 /* Handle a few special cases. */ 5414 switch (info->offset) { 5415 case E1000_RDTR: 5416 break; 5417 case E1000_TIDV: 5418 if (ticks == 0) { 5419 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5420 /* Don't write 0 into the TIDV register. */ 5421 regval++; 5422 } else 5423 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5424 break; 5425 } 5426 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5427 return (0); 5428 } 5429 5430 static int 5431 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5432 { 5433 struct e1000_softc *sc; 5434 u32 reg, val, shift; 5435 int error, mask; 5436 5437 sc = oidp->oid_arg1; 5438 switch (oidp->oid_arg2) { 5439 case 0: 5440 reg = E1000_DTXTCPFLGL; 5441 shift = 0; 5442 break; 5443 case 1: 5444 reg = E1000_DTXTCPFLGL; 5445 shift = 16; 5446 break; 5447 case 2: 5448 reg = E1000_DTXTCPFLGH; 5449 shift = 0; 5450 break; 5451 default: 5452 return (EINVAL); 5453 break; 5454 } 5455 val = E1000_READ_REG(&sc->hw, reg); 5456 mask = (val >> shift) & 0xfff; 5457 error = sysctl_handle_int(oidp, &mask, 0, req); 5458 if (error != 0 || req->newptr == NULL) 5459 return (error); 5460 if (mask < 0 || mask > 0xfff) 5461 return (EINVAL); 5462 val = (val & ~(0xfff << shift)) | (mask << shift); 5463 E1000_WRITE_REG(&sc->hw, reg, val); 5464 return (0); 5465 } 5466 5467 static void 5468 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5469 const char *description, struct em_int_delay_info *info, int offset, 5470 int value) 5471 { 5472 info->sc = sc; 5473 info->offset = offset; 5474 info->value = value; 5475 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5476 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5477 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5478 info, 0, em_sysctl_int_delay, "I", description); 5479 } 5480 5481 /* 5482 * Set flow control using sysctl: 5483 * Flow control values: 5484 * 0 - off 5485 * 1 - rx pause 5486 * 2 - tx pause 5487 * 3 - full 5488 */ 5489 static int 5490 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5491 { 5492 int error; 5493 static int input = 3; /* default is full */ 5494 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5495 5496 error = sysctl_handle_int(oidp, &input, 0, req); 5497 5498 if ((error) || (req->newptr == NULL)) 5499 return (error); 5500 5501 if (input == sc->fc) /* no change? */ 5502 return (error); 5503 5504 switch (input) { 5505 case e1000_fc_rx_pause: 5506 case e1000_fc_tx_pause: 5507 case e1000_fc_full: 5508 case e1000_fc_none: 5509 sc->hw.fc.requested_mode = input; 5510 sc->fc = input; 5511 break; 5512 default: 5513 /* Do nothing */ 5514 return (error); 5515 } 5516 5517 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5518 e1000_force_mac_fc(&sc->hw); 5519 return (error); 5520 } 5521 5522 /* 5523 * Manage DMA Coalesce: 5524 * Control values: 5525 * 0/1 - off/on 5526 * Legal timer values are: 5527 * 250,500,1000-10000 in thousands 5528 */ 5529 static int 5530 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5531 { 5532 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5533 int error; 5534 5535 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5536 5537 if ((error) || (req->newptr == NULL)) 5538 return (error); 5539 5540 switch (sc->dmac) { 5541 case 0: 5542 /* Disabling */ 5543 break; 5544 case 1: /* Just enable and use default */ 5545 sc->dmac = 1000; 5546 break; 5547 case 250: 5548 case 500: 5549 case 1000: 5550 case 2000: 5551 case 3000: 5552 case 4000: 5553 case 5000: 5554 case 6000: 5555 case 7000: 5556 case 8000: 5557 case 9000: 5558 case 10000: 5559 /* Legal values - allow */ 5560 break; 5561 default: 5562 /* Do nothing, illegal value */ 5563 sc->dmac = 0; 5564 return (EINVAL); 5565 } 5566 /* Reinit the interface */ 5567 em_if_init(sc->ctx); 5568 return (error); 5569 } 5570 5571 /* 5572 * Manage Energy Efficient Ethernet: 5573 * Control values: 5574 * 0/1 - enabled/disabled 5575 */ 5576 static int 5577 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5578 { 5579 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5580 int error, value; 5581 5582 if (sc->hw.mac.type < igb_mac_min) 5583 value = sc->hw.dev_spec.ich8lan.eee_disable; 5584 else 5585 value = sc->hw.dev_spec._82575.eee_disable; 5586 error = sysctl_handle_int(oidp, &value, 0, req); 5587 if (error || req->newptr == NULL) 5588 return (error); 5589 if (sc->hw.mac.type < igb_mac_min) 5590 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5591 else 5592 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5593 em_if_init(sc->ctx); 5594 5595 return (0); 5596 } 5597 5598 static int 5599 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5600 { 5601 struct e1000_softc *sc; 5602 int error; 5603 int result; 5604 5605 result = -1; 5606 error = sysctl_handle_int(oidp, &result, 0, req); 5607 5608 if (error || !req->newptr) 5609 return (error); 5610 5611 if (result == 1) { 5612 sc = (struct e1000_softc *) arg1; 5613 em_print_debug_info(sc); 5614 } 5615 5616 return (error); 5617 } 5618 5619 static int 5620 em_get_rs(SYSCTL_HANDLER_ARGS) 5621 { 5622 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5623 int error; 5624 int result; 5625 5626 result = 0; 5627 error = sysctl_handle_int(oidp, &result, 0, req); 5628 5629 if (error || !req->newptr || result != 1) 5630 return (error); 5631 em_dump_rs(sc); 5632 5633 return (error); 5634 } 5635 5636 static void 5637 em_if_debug(if_ctx_t ctx) 5638 { 5639 em_dump_rs(iflib_get_softc(ctx)); 5640 } 5641 5642 /* 5643 * This routine is meant to be fluid, add whatever is 5644 * needed for debugging a problem. -jfv 5645 */ 5646 static void 5647 em_print_debug_info(struct e1000_softc *sc) 5648 { 5649 device_t dev = iflib_get_dev(sc->ctx); 5650 if_t ifp = iflib_get_ifp(sc->ctx); 5651 struct tx_ring *txr = &sc->tx_queues->txr; 5652 struct rx_ring *rxr = &sc->rx_queues->rxr; 5653 5654 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5655 printf("Interface is RUNNING "); 5656 else 5657 printf("Interface is NOT RUNNING\n"); 5658 5659 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5660 printf("and INACTIVE\n"); 5661 else 5662 printf("and ACTIVE\n"); 5663 5664 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5665 device_printf(dev, "TX Queue %d ------\n", i); 5666 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5667 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5668 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5669 5670 } 5671 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5672 device_printf(dev, "RX Queue %d ------\n", j); 5673 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5674 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5675 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5676 } 5677 } 5678 5679 /* 5680 * 82574 only: 5681 * Write a new value to the EEPROM increasing the number of MSI-X 5682 * vectors from 3 to 5, for proper multiqueue support. 5683 */ 5684 static void 5685 em_enable_vectors_82574(if_ctx_t ctx) 5686 { 5687 struct e1000_softc *sc = iflib_get_softc(ctx); 5688 struct e1000_hw *hw = &sc->hw; 5689 device_t dev = iflib_get_dev(ctx); 5690 u16 edata; 5691 5692 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5693 if (bootverbose) 5694 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5695 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5696 device_printf(dev, "Writing to eeprom: increasing " 5697 "reported MSI-X vectors from 3 to 5...\n"); 5698 edata &= ~(EM_NVM_MSIX_N_MASK); 5699 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5700 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5701 e1000_update_nvm_checksum(hw); 5702 device_printf(dev, "Writing to eeprom: done\n"); 5703 } 5704 } 5705