1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) PRO/1000 Network Connection"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) PRO/1000 Network Connection"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) PRO/1000 Network Connection"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) PRO/1000 Network Connection"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) PRO/1000 Network Connection"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) PRO/1000 Network Connection"), 183 /* required last entry */ 184 PVID_END 185 }; 186 187 static pci_vendor_info_t igb_vendor_info_array[] = 188 { 189 /* Intel(R) PRO/1000 Network Connection - igb */ 190 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 224 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 225 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 226 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 227 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 228 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 229 /* required last entry */ 230 PVID_END 231 }; 232 233 /********************************************************************* 234 * Function prototypes 235 *********************************************************************/ 236 static void *em_register(device_t dev); 237 static void *igb_register(device_t dev); 238 static int em_if_attach_pre(if_ctx_t ctx); 239 static int em_if_attach_post(if_ctx_t ctx); 240 static int em_if_detach(if_ctx_t ctx); 241 static int em_if_shutdown(if_ctx_t ctx); 242 static int em_if_suspend(if_ctx_t ctx); 243 static int em_if_resume(if_ctx_t ctx); 244 245 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 246 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 247 static void em_if_queues_free(if_ctx_t ctx); 248 249 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 250 static void em_if_init(if_ctx_t ctx); 251 static void em_if_stop(if_ctx_t ctx); 252 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 253 static int em_if_media_change(if_ctx_t ctx); 254 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 255 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 256 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 257 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 258 static void em_if_watchdog_reset(if_ctx_t ctx); 259 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 260 261 static void em_identify_hardware(if_ctx_t ctx); 262 static int em_allocate_pci_resources(if_ctx_t ctx); 263 static void em_free_pci_resources(if_ctx_t ctx); 264 static void em_reset(if_ctx_t ctx); 265 static int em_setup_interface(if_ctx_t ctx); 266 static int em_setup_msix(if_ctx_t ctx); 267 268 static void em_initialize_transmit_unit(if_ctx_t ctx); 269 static void em_initialize_receive_unit(if_ctx_t ctx); 270 271 static void em_if_intr_enable(if_ctx_t ctx); 272 static void em_if_intr_disable(if_ctx_t ctx); 273 static void igb_if_intr_enable(if_ctx_t ctx); 274 static void igb_if_intr_disable(if_ctx_t ctx); 275 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 276 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 277 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 278 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 279 static void em_if_multi_set(if_ctx_t ctx); 280 static void em_if_update_admin_status(if_ctx_t ctx); 281 static void em_if_debug(if_ctx_t ctx); 282 static void em_update_stats_counters(struct adapter *); 283 static void em_add_hw_stats(struct adapter *adapter); 284 static int em_if_set_promisc(if_ctx_t ctx, int flags); 285 static void em_setup_vlan_hw_support(struct adapter *); 286 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 287 static void em_print_nvm_info(struct adapter *); 288 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 289 static int em_get_rs(SYSCTL_HANDLER_ARGS); 290 static void em_print_debug_info(struct adapter *); 291 static int em_is_valid_ether_addr(u8 *); 292 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 293 static void em_add_int_delay_sysctl(struct adapter *, const char *, 294 const char *, struct em_int_delay_info *, int, int); 295 /* Management and WOL Support */ 296 static void em_init_manageability(struct adapter *); 297 static void em_release_manageability(struct adapter *); 298 static void em_get_hw_control(struct adapter *); 299 static void em_release_hw_control(struct adapter *); 300 static void em_get_wakeup(if_ctx_t ctx); 301 static void em_enable_wakeup(if_ctx_t ctx); 302 static int em_enable_phy_wakeup(struct adapter *); 303 static void em_disable_aspm(struct adapter *); 304 305 int em_intr(void *arg); 306 static void em_disable_promisc(if_ctx_t ctx); 307 308 /* MSI-X handlers */ 309 static int em_if_msix_intr_assign(if_ctx_t, int); 310 static int em_msix_link(void *); 311 static void em_handle_link(void *context); 312 313 static void em_enable_vectors_82574(if_ctx_t); 314 315 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 316 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 317 static void em_if_led_func(if_ctx_t ctx, int onoff); 318 319 static int em_get_regs(SYSCTL_HANDLER_ARGS); 320 321 static void lem_smartspeed(struct adapter *adapter); 322 static void igb_configure_queues(struct adapter *adapter); 323 324 325 /********************************************************************* 326 * FreeBSD Device Interface Entry Points 327 *********************************************************************/ 328 static device_method_t em_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, em_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 static device_method_t igb_methods[] = { 341 /* Device interface */ 342 DEVMETHOD(device_register, igb_register), 343 DEVMETHOD(device_probe, iflib_device_probe), 344 DEVMETHOD(device_attach, iflib_device_attach), 345 DEVMETHOD(device_detach, iflib_device_detach), 346 DEVMETHOD(device_shutdown, iflib_device_shutdown), 347 DEVMETHOD(device_suspend, iflib_device_suspend), 348 DEVMETHOD(device_resume, iflib_device_resume), 349 DEVMETHOD_END 350 }; 351 352 353 static driver_t em_driver = { 354 "em", em_methods, sizeof(struct adapter), 355 }; 356 357 static devclass_t em_devclass; 358 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 359 360 MODULE_DEPEND(em, pci, 1, 1, 1); 361 MODULE_DEPEND(em, ether, 1, 1, 1); 362 MODULE_DEPEND(em, iflib, 1, 1, 1); 363 364 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 365 366 static driver_t igb_driver = { 367 "igb", igb_methods, sizeof(struct adapter), 368 }; 369 370 static devclass_t igb_devclass; 371 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 372 373 MODULE_DEPEND(igb, pci, 1, 1, 1); 374 MODULE_DEPEND(igb, ether, 1, 1, 1); 375 MODULE_DEPEND(igb, iflib, 1, 1, 1); 376 377 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 378 379 static device_method_t em_if_methods[] = { 380 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 381 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 382 DEVMETHOD(ifdi_detach, em_if_detach), 383 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 384 DEVMETHOD(ifdi_suspend, em_if_suspend), 385 DEVMETHOD(ifdi_resume, em_if_resume), 386 DEVMETHOD(ifdi_init, em_if_init), 387 DEVMETHOD(ifdi_stop, em_if_stop), 388 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 389 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 390 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 391 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 392 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 393 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 394 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 395 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 396 DEVMETHOD(ifdi_media_status, em_if_media_status), 397 DEVMETHOD(ifdi_media_change, em_if_media_change), 398 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 399 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 400 DEVMETHOD(ifdi_timer, em_if_timer), 401 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 402 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 403 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 404 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 405 DEVMETHOD(ifdi_led_func, em_if_led_func), 406 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 407 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 408 DEVMETHOD(ifdi_debug, em_if_debug), 409 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 410 DEVMETHOD_END 411 }; 412 413 static driver_t em_if_driver = { 414 "em_if", em_if_methods, sizeof(struct adapter) 415 }; 416 417 static device_method_t igb_if_methods[] = { 418 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 419 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 420 DEVMETHOD(ifdi_detach, em_if_detach), 421 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 422 DEVMETHOD(ifdi_suspend, em_if_suspend), 423 DEVMETHOD(ifdi_resume, em_if_resume), 424 DEVMETHOD(ifdi_init, em_if_init), 425 DEVMETHOD(ifdi_stop, em_if_stop), 426 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 427 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 428 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 429 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 430 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 431 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 432 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 433 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 434 DEVMETHOD(ifdi_media_status, em_if_media_status), 435 DEVMETHOD(ifdi_media_change, em_if_media_change), 436 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 437 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 438 DEVMETHOD(ifdi_timer, em_if_timer), 439 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 440 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 441 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 442 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 443 DEVMETHOD(ifdi_led_func, em_if_led_func), 444 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 445 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 446 DEVMETHOD(ifdi_debug, em_if_debug), 447 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 448 DEVMETHOD_END 449 }; 450 451 static driver_t igb_if_driver = { 452 "igb_if", igb_if_methods, sizeof(struct adapter) 453 }; 454 455 /********************************************************************* 456 * Tunable default values. 457 *********************************************************************/ 458 459 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 460 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 461 462 #define MAX_INTS_PER_SEC 8000 463 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 464 465 /* Allow common code without TSO */ 466 #ifndef CSUM_TSO 467 #define CSUM_TSO 0 468 #endif 469 470 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 471 "EM driver parameters"); 472 473 static int em_disable_crc_stripping = 0; 474 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 475 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 476 477 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 478 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 479 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 480 0, "Default transmit interrupt delay in usecs"); 481 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 482 0, "Default receive interrupt delay in usecs"); 483 484 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 485 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 486 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 487 &em_tx_abs_int_delay_dflt, 0, 488 "Default transmit interrupt delay limit in usecs"); 489 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 490 &em_rx_abs_int_delay_dflt, 0, 491 "Default receive interrupt delay limit in usecs"); 492 493 static int em_smart_pwr_down = FALSE; 494 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 495 0, "Set to true to leave smart power down enabled on newer adapters"); 496 497 /* Controls whether promiscuous also shows bad packets */ 498 static int em_debug_sbp = TRUE; 499 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 500 "Show bad packets in promiscuous mode"); 501 502 /* How many packets rxeof tries to clean at a time */ 503 static int em_rx_process_limit = 100; 504 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 505 &em_rx_process_limit, 0, 506 "Maximum number of received packets to process " 507 "at a time, -1 means unlimited"); 508 509 /* Energy efficient ethernet - default to OFF */ 510 static int eee_setting = 1; 511 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 512 "Enable Energy Efficient Ethernet"); 513 514 /* 515 ** Tuneable Interrupt rate 516 */ 517 static int em_max_interrupt_rate = 8000; 518 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 519 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 520 521 522 523 /* Global used in WOL setup with multiport cards */ 524 static int global_quad_port_a = 0; 525 526 extern struct if_txrx igb_txrx; 527 extern struct if_txrx em_txrx; 528 extern struct if_txrx lem_txrx; 529 530 static struct if_shared_ctx em_sctx_init = { 531 .isc_magic = IFLIB_MAGIC, 532 .isc_q_align = PAGE_SIZE, 533 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 534 .isc_tx_maxsegsize = PAGE_SIZE, 535 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 536 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 537 .isc_rx_maxsize = MJUM9BYTES, 538 .isc_rx_nsegments = 1, 539 .isc_rx_maxsegsize = MJUM9BYTES, 540 .isc_nfl = 1, 541 .isc_nrxqs = 1, 542 .isc_ntxqs = 1, 543 .isc_admin_intrcnt = 1, 544 .isc_vendor_info = em_vendor_info_array, 545 .isc_driver_version = em_driver_version, 546 .isc_driver = &em_if_driver, 547 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 548 549 .isc_nrxd_min = {EM_MIN_RXD}, 550 .isc_ntxd_min = {EM_MIN_TXD}, 551 .isc_nrxd_max = {EM_MAX_RXD}, 552 .isc_ntxd_max = {EM_MAX_TXD}, 553 .isc_nrxd_default = {EM_DEFAULT_RXD}, 554 .isc_ntxd_default = {EM_DEFAULT_TXD}, 555 }; 556 557 static struct if_shared_ctx igb_sctx_init = { 558 .isc_magic = IFLIB_MAGIC, 559 .isc_q_align = PAGE_SIZE, 560 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 561 .isc_tx_maxsegsize = PAGE_SIZE, 562 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 563 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 564 .isc_rx_maxsize = MJUM9BYTES, 565 .isc_rx_nsegments = 1, 566 .isc_rx_maxsegsize = MJUM9BYTES, 567 .isc_nfl = 1, 568 .isc_nrxqs = 1, 569 .isc_ntxqs = 1, 570 .isc_admin_intrcnt = 1, 571 .isc_vendor_info = igb_vendor_info_array, 572 .isc_driver_version = em_driver_version, 573 .isc_driver = &igb_if_driver, 574 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 575 576 .isc_nrxd_min = {EM_MIN_RXD}, 577 .isc_ntxd_min = {EM_MIN_TXD}, 578 .isc_nrxd_max = {IGB_MAX_RXD}, 579 .isc_ntxd_max = {IGB_MAX_TXD}, 580 .isc_nrxd_default = {EM_DEFAULT_RXD}, 581 .isc_ntxd_default = {EM_DEFAULT_TXD}, 582 }; 583 584 /***************************************************************** 585 * 586 * Dump Registers 587 * 588 ****************************************************************/ 589 #define IGB_REGS_LEN 739 590 591 static int em_get_regs(SYSCTL_HANDLER_ARGS) 592 { 593 struct adapter *adapter = (struct adapter *)arg1; 594 struct e1000_hw *hw = &adapter->hw; 595 struct sbuf *sb; 596 u32 *regs_buff; 597 int rc; 598 599 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 600 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 601 602 rc = sysctl_wire_old_buffer(req, 0); 603 MPASS(rc == 0); 604 if (rc != 0) { 605 free(regs_buff, M_DEVBUF); 606 return (rc); 607 } 608 609 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 610 MPASS(sb != NULL); 611 if (sb == NULL) { 612 free(regs_buff, M_DEVBUF); 613 return (ENOMEM); 614 } 615 616 /* General Registers */ 617 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 618 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 619 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 620 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 621 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 622 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 623 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 624 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 625 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 626 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 627 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 628 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 629 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 630 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 631 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 632 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 633 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 634 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 635 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 636 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 637 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 638 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 639 640 sbuf_printf(sb, "General Registers\n"); 641 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 642 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 643 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 644 645 sbuf_printf(sb, "Interrupt Registers\n"); 646 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 647 648 sbuf_printf(sb, "RX Registers\n"); 649 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 650 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 651 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 652 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 653 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 654 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 655 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 656 657 sbuf_printf(sb, "TX Registers\n"); 658 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 659 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 660 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 661 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 662 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 663 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 664 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 665 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 666 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 667 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 668 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 669 670 free(regs_buff, M_DEVBUF); 671 672 #ifdef DUMP_DESCS 673 { 674 if_softc_ctx_t scctx = adapter->shared; 675 struct rx_ring *rxr = &rx_que->rxr; 676 struct tx_ring *txr = &tx_que->txr; 677 int ntxd = scctx->isc_ntxd[0]; 678 int nrxd = scctx->isc_nrxd[0]; 679 int j; 680 681 for (j = 0; j < nrxd; j++) { 682 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 683 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 684 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 685 } 686 687 for (j = 0; j < min(ntxd, 256); j++) { 688 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 689 690 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 691 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 692 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 693 694 } 695 } 696 #endif 697 698 rc = sbuf_finish(sb); 699 sbuf_delete(sb); 700 return(rc); 701 } 702 703 static void * 704 em_register(device_t dev) 705 { 706 return (&em_sctx_init); 707 } 708 709 static void * 710 igb_register(device_t dev) 711 { 712 return (&igb_sctx_init); 713 } 714 715 static int 716 em_set_num_queues(if_ctx_t ctx) 717 { 718 struct adapter *adapter = iflib_get_softc(ctx); 719 int maxqueues; 720 721 /* Sanity check based on HW */ 722 switch (adapter->hw.mac.type) { 723 case e1000_82576: 724 case e1000_82580: 725 case e1000_i350: 726 case e1000_i354: 727 maxqueues = 8; 728 break; 729 case e1000_i210: 730 case e1000_82575: 731 maxqueues = 4; 732 break; 733 case e1000_i211: 734 case e1000_82574: 735 maxqueues = 2; 736 break; 737 default: 738 maxqueues = 1; 739 break; 740 } 741 742 return (maxqueues); 743 } 744 745 #define LEM_CAPS \ 746 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 747 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 748 749 #define EM_CAPS \ 750 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 751 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 752 IFCAP_LRO | IFCAP_VLAN_HWTSO 753 754 #define IGB_CAPS \ 755 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 756 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 757 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 758 IFCAP_TSO6 759 760 /********************************************************************* 761 * Device initialization routine 762 * 763 * The attach entry point is called when the driver is being loaded. 764 * This routine identifies the type of hardware, allocates all resources 765 * and initializes the hardware. 766 * 767 * return 0 on success, positive on failure 768 *********************************************************************/ 769 static int 770 em_if_attach_pre(if_ctx_t ctx) 771 { 772 struct adapter *adapter; 773 if_softc_ctx_t scctx; 774 device_t dev; 775 struct e1000_hw *hw; 776 int error = 0; 777 778 INIT_DEBUGOUT("em_if_attach_pre: begin"); 779 dev = iflib_get_dev(ctx); 780 adapter = iflib_get_softc(ctx); 781 782 adapter->ctx = adapter->osdep.ctx = ctx; 783 adapter->dev = adapter->osdep.dev = dev; 784 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 785 adapter->media = iflib_get_media(ctx); 786 hw = &adapter->hw; 787 788 adapter->tx_process_limit = scctx->isc_ntxd[0]; 789 790 /* SYSCTL stuff */ 791 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 792 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 793 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 794 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 795 796 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 797 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 798 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 799 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 800 801 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 802 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 803 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 804 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 805 806 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 807 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 808 OID_AUTO, "reg_dump", 809 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 810 em_get_regs, "A", "Dump Registers"); 811 812 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 813 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 814 OID_AUTO, "rs_dump", 815 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 816 em_get_rs, "I", "Dump RS indexes"); 817 818 /* Determine hardware and mac info */ 819 em_identify_hardware(ctx); 820 821 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 822 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 823 if (bootverbose) 824 device_printf(dev, "attach_pre capping queues at %d\n", 825 scctx->isc_ntxqsets_max); 826 827 if (hw->mac.type >= igb_mac_min) { 828 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 829 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 830 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 831 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 832 scctx->isc_txrx = &igb_txrx; 833 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 834 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 835 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 836 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 837 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 838 CSUM_IP6_TCP | CSUM_IP6_UDP; 839 if (hw->mac.type != e1000_82575) 840 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 841 /* 842 ** Some new devices, as with ixgbe, now may 843 ** use a different BAR, so we need to keep 844 ** track of which is used. 845 */ 846 scctx->isc_msix_bar = pci_msix_table_bar(dev); 847 } else if (hw->mac.type >= em_mac_min) { 848 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 849 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 850 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 851 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 852 scctx->isc_txrx = &em_txrx; 853 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 854 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 855 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 856 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 857 /* 858 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 859 * by default as we don't have workarounds for all associated 860 * silicon errata. E. g., with several MACs such as 82573E, 861 * TSO only works at Gigabit speed and otherwise can cause the 862 * hardware to hang (which also would be next to impossible to 863 * work around given that already queued TSO-using descriptors 864 * would need to be flushed and vlan(4) reconfigured at runtime 865 * in case of a link speed change). Moreover, MACs like 82579 866 * still can hang at Gigabit even with all publicly documented 867 * TSO workarounds implemented. Generally, the penality of 868 * these workarounds is rather high and may involve copying 869 * mbuf data around so advantages of TSO lapse. Still, TSO may 870 * work for a few MACs of this class - at least when sticking 871 * with Gigabit - in which case users may enable TSO manually. 872 */ 873 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 874 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 875 /* 876 * We support MSI-X with 82574 only, but indicate to iflib(4) 877 * that it shall give MSI at least a try with other devices. 878 */ 879 if (hw->mac.type == e1000_82574) { 880 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 881 } else { 882 scctx->isc_msix_bar = -1; 883 scctx->isc_disable_msix = 1; 884 } 885 } else { 886 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 887 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 888 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 889 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 890 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 891 scctx->isc_txrx = &lem_txrx; 892 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 893 if (hw->mac.type < e1000_82543) 894 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 895 /* INTx only */ 896 scctx->isc_msix_bar = 0; 897 } 898 899 /* Setup PCI resources */ 900 if (em_allocate_pci_resources(ctx)) { 901 device_printf(dev, "Allocation of PCI resources failed\n"); 902 error = ENXIO; 903 goto err_pci; 904 } 905 906 /* 907 ** For ICH8 and family we need to 908 ** map the flash memory, and this 909 ** must happen after the MAC is 910 ** identified 911 */ 912 if ((hw->mac.type == e1000_ich8lan) || 913 (hw->mac.type == e1000_ich9lan) || 914 (hw->mac.type == e1000_ich10lan) || 915 (hw->mac.type == e1000_pchlan) || 916 (hw->mac.type == e1000_pch2lan) || 917 (hw->mac.type == e1000_pch_lpt)) { 918 int rid = EM_BAR_TYPE_FLASH; 919 adapter->flash = bus_alloc_resource_any(dev, 920 SYS_RES_MEMORY, &rid, RF_ACTIVE); 921 if (adapter->flash == NULL) { 922 device_printf(dev, "Mapping of Flash failed\n"); 923 error = ENXIO; 924 goto err_pci; 925 } 926 /* This is used in the shared code */ 927 hw->flash_address = (u8 *)adapter->flash; 928 adapter->osdep.flash_bus_space_tag = 929 rman_get_bustag(adapter->flash); 930 adapter->osdep.flash_bus_space_handle = 931 rman_get_bushandle(adapter->flash); 932 } 933 /* 934 ** In the new SPT device flash is not a 935 ** separate BAR, rather it is also in BAR0, 936 ** so use the same tag and an offset handle for the 937 ** FLASH read/write macros in the shared code. 938 */ 939 else if (hw->mac.type >= e1000_pch_spt) { 940 adapter->osdep.flash_bus_space_tag = 941 adapter->osdep.mem_bus_space_tag; 942 adapter->osdep.flash_bus_space_handle = 943 adapter->osdep.mem_bus_space_handle 944 + E1000_FLASH_BASE_ADDR; 945 } 946 947 /* Do Shared Code initialization */ 948 error = e1000_setup_init_funcs(hw, TRUE); 949 if (error) { 950 device_printf(dev, "Setup of Shared code failed, error %d\n", 951 error); 952 error = ENXIO; 953 goto err_pci; 954 } 955 956 em_setup_msix(ctx); 957 e1000_get_bus_info(hw); 958 959 /* Set up some sysctls for the tunable interrupt delays */ 960 em_add_int_delay_sysctl(adapter, "rx_int_delay", 961 "receive interrupt delay in usecs", &adapter->rx_int_delay, 962 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 963 em_add_int_delay_sysctl(adapter, "tx_int_delay", 964 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 965 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 966 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 967 "receive interrupt delay limit in usecs", 968 &adapter->rx_abs_int_delay, 969 E1000_REGISTER(hw, E1000_RADV), 970 em_rx_abs_int_delay_dflt); 971 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 972 "transmit interrupt delay limit in usecs", 973 &adapter->tx_abs_int_delay, 974 E1000_REGISTER(hw, E1000_TADV), 975 em_tx_abs_int_delay_dflt); 976 em_add_int_delay_sysctl(adapter, "itr", 977 "interrupt delay limit in usecs/4", 978 &adapter->tx_itr, 979 E1000_REGISTER(hw, E1000_ITR), 980 DEFAULT_ITR); 981 982 hw->mac.autoneg = DO_AUTO_NEG; 983 hw->phy.autoneg_wait_to_complete = FALSE; 984 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 985 986 if (hw->mac.type < em_mac_min) { 987 e1000_init_script_state_82541(hw, TRUE); 988 e1000_set_tbi_compatibility_82543(hw, TRUE); 989 } 990 /* Copper options */ 991 if (hw->phy.media_type == e1000_media_type_copper) { 992 hw->phy.mdix = AUTO_ALL_MODES; 993 hw->phy.disable_polarity_correction = FALSE; 994 hw->phy.ms_type = EM_MASTER_SLAVE; 995 } 996 997 /* 998 * Set the frame limits assuming 999 * standard ethernet sized frames. 1000 */ 1001 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1002 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1003 1004 /* 1005 * This controls when hardware reports transmit completion 1006 * status. 1007 */ 1008 hw->mac.report_tx_early = 1; 1009 1010 /* Allocate multicast array memory. */ 1011 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1012 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1013 if (adapter->mta == NULL) { 1014 device_printf(dev, "Can not allocate multicast setup array\n"); 1015 error = ENOMEM; 1016 goto err_late; 1017 } 1018 1019 /* Check SOL/IDER usage */ 1020 if (e1000_check_reset_block(hw)) 1021 device_printf(dev, "PHY reset is blocked" 1022 " due to SOL/IDER session.\n"); 1023 1024 /* Sysctl for setting Energy Efficient Ethernet */ 1025 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1026 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1027 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1028 OID_AUTO, "eee_control", 1029 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1030 adapter, 0, em_sysctl_eee, "I", 1031 "Disable Energy Efficient Ethernet"); 1032 1033 /* 1034 ** Start from a known state, this is 1035 ** important in reading the nvm and 1036 ** mac from that. 1037 */ 1038 e1000_reset_hw(hw); 1039 1040 /* Make sure we have a good EEPROM before we read from it */ 1041 if (e1000_validate_nvm_checksum(hw) < 0) { 1042 /* 1043 ** Some PCI-E parts fail the first check due to 1044 ** the link being in sleep state, call it again, 1045 ** if it fails a second time its a real issue. 1046 */ 1047 if (e1000_validate_nvm_checksum(hw) < 0) { 1048 device_printf(dev, 1049 "The EEPROM Checksum Is Not Valid\n"); 1050 error = EIO; 1051 goto err_late; 1052 } 1053 } 1054 1055 /* Copy the permanent MAC address out of the EEPROM */ 1056 if (e1000_read_mac_addr(hw) < 0) { 1057 device_printf(dev, "EEPROM read error while reading MAC" 1058 " address\n"); 1059 error = EIO; 1060 goto err_late; 1061 } 1062 1063 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1064 device_printf(dev, "Invalid MAC address\n"); 1065 error = EIO; 1066 goto err_late; 1067 } 1068 1069 /* Disable ULP support */ 1070 e1000_disable_ulp_lpt_lp(hw, TRUE); 1071 1072 /* 1073 * Get Wake-on-Lan and Management info for later use 1074 */ 1075 em_get_wakeup(ctx); 1076 1077 /* Enable only WOL MAGIC by default */ 1078 scctx->isc_capenable &= ~IFCAP_WOL; 1079 if (adapter->wol != 0) 1080 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1081 1082 iflib_set_mac(ctx, hw->mac.addr); 1083 1084 return (0); 1085 1086 err_late: 1087 em_release_hw_control(adapter); 1088 err_pci: 1089 em_free_pci_resources(ctx); 1090 free(adapter->mta, M_DEVBUF); 1091 1092 return (error); 1093 } 1094 1095 static int 1096 em_if_attach_post(if_ctx_t ctx) 1097 { 1098 struct adapter *adapter = iflib_get_softc(ctx); 1099 struct e1000_hw *hw = &adapter->hw; 1100 int error = 0; 1101 1102 /* Setup OS specific network interface */ 1103 error = em_setup_interface(ctx); 1104 if (error != 0) { 1105 device_printf(adapter->dev, "Interface setup failed: %d\n", error); 1106 goto err_late; 1107 } 1108 1109 em_reset(ctx); 1110 1111 /* Initialize statistics */ 1112 em_update_stats_counters(adapter); 1113 hw->mac.get_link_status = 1; 1114 em_if_update_admin_status(ctx); 1115 em_add_hw_stats(adapter); 1116 1117 /* Non-AMT based hardware can now take control from firmware */ 1118 if (adapter->has_manage && !adapter->has_amt) 1119 em_get_hw_control(adapter); 1120 1121 INIT_DEBUGOUT("em_if_attach_post: end"); 1122 1123 return (0); 1124 1125 err_late: 1126 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1127 return (error); 1128 } 1129 1130 /********************************************************************* 1131 * Device removal routine 1132 * 1133 * The detach entry point is called when the driver is being removed. 1134 * This routine stops the adapter and deallocates all the resources 1135 * that were allocated for driver operation. 1136 * 1137 * return 0 on success, positive on failure 1138 *********************************************************************/ 1139 static int 1140 em_if_detach(if_ctx_t ctx) 1141 { 1142 struct adapter *adapter = iflib_get_softc(ctx); 1143 1144 INIT_DEBUGOUT("em_if_detach: begin"); 1145 1146 e1000_phy_hw_reset(&adapter->hw); 1147 1148 em_release_manageability(adapter); 1149 em_release_hw_control(adapter); 1150 em_free_pci_resources(ctx); 1151 free(adapter->mta, M_DEVBUF); 1152 adapter->mta = NULL; 1153 1154 return (0); 1155 } 1156 1157 /********************************************************************* 1158 * 1159 * Shutdown entry point 1160 * 1161 **********************************************************************/ 1162 1163 static int 1164 em_if_shutdown(if_ctx_t ctx) 1165 { 1166 return em_if_suspend(ctx); 1167 } 1168 1169 /* 1170 * Suspend/resume device methods. 1171 */ 1172 static int 1173 em_if_suspend(if_ctx_t ctx) 1174 { 1175 struct adapter *adapter = iflib_get_softc(ctx); 1176 1177 em_release_manageability(adapter); 1178 em_release_hw_control(adapter); 1179 em_enable_wakeup(ctx); 1180 return (0); 1181 } 1182 1183 static int 1184 em_if_resume(if_ctx_t ctx) 1185 { 1186 struct adapter *adapter = iflib_get_softc(ctx); 1187 1188 if (adapter->hw.mac.type == e1000_pch2lan) 1189 e1000_resume_workarounds_pchlan(&adapter->hw); 1190 em_if_init(ctx); 1191 em_init_manageability(adapter); 1192 1193 return(0); 1194 } 1195 1196 static int 1197 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1198 { 1199 int max_frame_size; 1200 struct adapter *adapter = iflib_get_softc(ctx); 1201 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1202 1203 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1204 1205 switch (adapter->hw.mac.type) { 1206 case e1000_82571: 1207 case e1000_82572: 1208 case e1000_ich9lan: 1209 case e1000_ich10lan: 1210 case e1000_pch2lan: 1211 case e1000_pch_lpt: 1212 case e1000_pch_spt: 1213 case e1000_pch_cnp: 1214 case e1000_82574: 1215 case e1000_82583: 1216 case e1000_80003es2lan: 1217 /* 9K Jumbo Frame size */ 1218 max_frame_size = 9234; 1219 break; 1220 case e1000_pchlan: 1221 max_frame_size = 4096; 1222 break; 1223 case e1000_82542: 1224 case e1000_ich8lan: 1225 /* Adapters that do not support jumbo frames */ 1226 max_frame_size = ETHER_MAX_LEN; 1227 break; 1228 default: 1229 if (adapter->hw.mac.type >= igb_mac_min) 1230 max_frame_size = 9234; 1231 else /* lem */ 1232 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1233 } 1234 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1235 return (EINVAL); 1236 } 1237 1238 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1239 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1240 return (0); 1241 } 1242 1243 /********************************************************************* 1244 * Init entry point 1245 * 1246 * This routine is used in two ways. It is used by the stack as 1247 * init entry point in network interface structure. It is also used 1248 * by the driver as a hw/sw initialization routine to get to a 1249 * consistent state. 1250 * 1251 **********************************************************************/ 1252 static void 1253 em_if_init(if_ctx_t ctx) 1254 { 1255 struct adapter *adapter = iflib_get_softc(ctx); 1256 if_softc_ctx_t scctx = adapter->shared; 1257 struct ifnet *ifp = iflib_get_ifp(ctx); 1258 struct em_tx_queue *tx_que; 1259 int i; 1260 1261 INIT_DEBUGOUT("em_if_init: begin"); 1262 1263 /* Get the latest mac address, User can use a LAA */ 1264 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1265 ETHER_ADDR_LEN); 1266 1267 /* Put the address into the Receive Address Array */ 1268 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1269 1270 /* 1271 * With the 82571 adapter, RAR[0] may be overwritten 1272 * when the other port is reset, we make a duplicate 1273 * in RAR[14] for that eventuality, this assures 1274 * the interface continues to function. 1275 */ 1276 if (adapter->hw.mac.type == e1000_82571) { 1277 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1278 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1279 E1000_RAR_ENTRIES - 1); 1280 } 1281 1282 1283 /* Initialize the hardware */ 1284 em_reset(ctx); 1285 em_if_update_admin_status(ctx); 1286 1287 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1288 struct tx_ring *txr = &tx_que->txr; 1289 1290 txr->tx_rs_cidx = txr->tx_rs_pidx; 1291 1292 /* Initialize the last processed descriptor to be the end of 1293 * the ring, rather than the start, so that we avoid an 1294 * off-by-one error when calculating how many descriptors are 1295 * done in the credits_update function. 1296 */ 1297 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1298 } 1299 1300 /* Setup VLAN support, basic and offload if available */ 1301 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1302 1303 /* Clear bad data from Rx FIFOs */ 1304 if (adapter->hw.mac.type >= igb_mac_min) 1305 e1000_rx_fifo_flush_82575(&adapter->hw); 1306 1307 /* Configure for OS presence */ 1308 em_init_manageability(adapter); 1309 1310 /* Prepare transmit descriptors and buffers */ 1311 em_initialize_transmit_unit(ctx); 1312 1313 /* Setup Multicast table */ 1314 em_if_multi_set(ctx); 1315 1316 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1317 em_initialize_receive_unit(ctx); 1318 1319 /* Use real VLAN Filter support? */ 1320 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1321 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1322 /* Use real VLAN Filter support */ 1323 em_setup_vlan_hw_support(adapter); 1324 else { 1325 u32 ctrl; 1326 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1327 ctrl |= E1000_CTRL_VME; 1328 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1329 } 1330 } else { 1331 u32 ctrl; 1332 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1333 ctrl &= ~E1000_CTRL_VME; 1334 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1335 } 1336 1337 /* Don't lose promiscuous settings */ 1338 em_if_set_promisc(ctx, if_getflags(ifp)); 1339 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1340 1341 /* MSI-X configuration for 82574 */ 1342 if (adapter->hw.mac.type == e1000_82574) { 1343 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1344 1345 tmp |= E1000_CTRL_EXT_PBA_CLR; 1346 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1347 /* Set the IVAR - interrupt vector routing. */ 1348 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1349 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1350 igb_configure_queues(adapter); 1351 1352 /* this clears any pending interrupts */ 1353 E1000_READ_REG(&adapter->hw, E1000_ICR); 1354 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1355 1356 /* AMT based hardware can now take control from firmware */ 1357 if (adapter->has_manage && adapter->has_amt) 1358 em_get_hw_control(adapter); 1359 1360 /* Set Energy Efficient Ethernet */ 1361 if (adapter->hw.mac.type >= igb_mac_min && 1362 adapter->hw.phy.media_type == e1000_media_type_copper) { 1363 if (adapter->hw.mac.type == e1000_i354) 1364 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1365 else 1366 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1367 } 1368 } 1369 1370 /********************************************************************* 1371 * 1372 * Fast Legacy/MSI Combined Interrupt Service routine 1373 * 1374 *********************************************************************/ 1375 int 1376 em_intr(void *arg) 1377 { 1378 struct adapter *adapter = arg; 1379 if_ctx_t ctx = adapter->ctx; 1380 u32 reg_icr; 1381 1382 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1383 1384 /* Hot eject? */ 1385 if (reg_icr == 0xffffffff) 1386 return FILTER_STRAY; 1387 1388 /* Definitely not our interrupt. */ 1389 if (reg_icr == 0x0) 1390 return FILTER_STRAY; 1391 1392 /* 1393 * Starting with the 82571 chip, bit 31 should be used to 1394 * determine whether the interrupt belongs to us. 1395 */ 1396 if (adapter->hw.mac.type >= e1000_82571 && 1397 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1398 return FILTER_STRAY; 1399 1400 /* 1401 * Only MSI-X interrupts have one-shot behavior by taking advantage 1402 * of the EIAC register. Thus, explicitly disable interrupts. This 1403 * also works around the MSI message reordering errata on certain 1404 * systems. 1405 */ 1406 IFDI_INTR_DISABLE(ctx); 1407 1408 /* Link status change */ 1409 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1410 em_handle_link(ctx); 1411 1412 if (reg_icr & E1000_ICR_RXO) 1413 adapter->rx_overruns++; 1414 1415 return (FILTER_SCHEDULE_THREAD); 1416 } 1417 1418 static int 1419 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1420 { 1421 struct adapter *adapter = iflib_get_softc(ctx); 1422 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1423 1424 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1425 return (0); 1426 } 1427 1428 static int 1429 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1430 { 1431 struct adapter *adapter = iflib_get_softc(ctx); 1432 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1433 1434 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1435 return (0); 1436 } 1437 1438 static int 1439 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1440 { 1441 struct adapter *adapter = iflib_get_softc(ctx); 1442 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1443 1444 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1445 return (0); 1446 } 1447 1448 static int 1449 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1450 { 1451 struct adapter *adapter = iflib_get_softc(ctx); 1452 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1453 1454 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1455 return (0); 1456 } 1457 1458 /********************************************************************* 1459 * 1460 * MSI-X RX Interrupt Service routine 1461 * 1462 **********************************************************************/ 1463 static int 1464 em_msix_que(void *arg) 1465 { 1466 struct em_rx_queue *que = arg; 1467 1468 ++que->irqs; 1469 1470 return (FILTER_SCHEDULE_THREAD); 1471 } 1472 1473 /********************************************************************* 1474 * 1475 * MSI-X Link Fast Interrupt Service routine 1476 * 1477 **********************************************************************/ 1478 static int 1479 em_msix_link(void *arg) 1480 { 1481 struct adapter *adapter = arg; 1482 u32 reg_icr; 1483 1484 ++adapter->link_irq; 1485 MPASS(adapter->hw.back != NULL); 1486 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1487 1488 if (reg_icr & E1000_ICR_RXO) 1489 adapter->rx_overruns++; 1490 1491 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1492 em_handle_link(adapter->ctx); 1493 } else if (adapter->hw.mac.type == e1000_82574) { 1494 /* Only re-arm 82574 if em_if_update_admin_status() won't. */ 1495 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | 1496 E1000_IMS_LSC); 1497 } 1498 1499 if (adapter->hw.mac.type == e1000_82574) { 1500 /* 1501 * Because we must read the ICR for this interrupt it may 1502 * clear other causes using autoclear, for this reason we 1503 * simply create a soft interrupt for all these vectors. 1504 */ 1505 if (reg_icr) 1506 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1507 } else { 1508 /* Re-arm unconditionally */ 1509 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1510 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1511 } 1512 1513 return (FILTER_HANDLED); 1514 } 1515 1516 static void 1517 em_handle_link(void *context) 1518 { 1519 if_ctx_t ctx = context; 1520 struct adapter *adapter = iflib_get_softc(ctx); 1521 1522 adapter->hw.mac.get_link_status = 1; 1523 iflib_admin_intr_deferred(ctx); 1524 } 1525 1526 /********************************************************************* 1527 * 1528 * Media Ioctl callback 1529 * 1530 * This routine is called whenever the user queries the status of 1531 * the interface using ifconfig. 1532 * 1533 **********************************************************************/ 1534 static void 1535 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1536 { 1537 struct adapter *adapter = iflib_get_softc(ctx); 1538 u_char fiber_type = IFM_1000_SX; 1539 1540 INIT_DEBUGOUT("em_if_media_status: begin"); 1541 1542 iflib_admin_intr_deferred(ctx); 1543 1544 ifmr->ifm_status = IFM_AVALID; 1545 ifmr->ifm_active = IFM_ETHER; 1546 1547 if (!adapter->link_active) { 1548 return; 1549 } 1550 1551 ifmr->ifm_status |= IFM_ACTIVE; 1552 1553 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1554 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1555 if (adapter->hw.mac.type == e1000_82545) 1556 fiber_type = IFM_1000_LX; 1557 ifmr->ifm_active |= fiber_type | IFM_FDX; 1558 } else { 1559 switch (adapter->link_speed) { 1560 case 10: 1561 ifmr->ifm_active |= IFM_10_T; 1562 break; 1563 case 100: 1564 ifmr->ifm_active |= IFM_100_TX; 1565 break; 1566 case 1000: 1567 ifmr->ifm_active |= IFM_1000_T; 1568 break; 1569 } 1570 if (adapter->link_duplex == FULL_DUPLEX) 1571 ifmr->ifm_active |= IFM_FDX; 1572 else 1573 ifmr->ifm_active |= IFM_HDX; 1574 } 1575 } 1576 1577 /********************************************************************* 1578 * 1579 * Media Ioctl callback 1580 * 1581 * This routine is called when the user changes speed/duplex using 1582 * media/mediopt option with ifconfig. 1583 * 1584 **********************************************************************/ 1585 static int 1586 em_if_media_change(if_ctx_t ctx) 1587 { 1588 struct adapter *adapter = iflib_get_softc(ctx); 1589 struct ifmedia *ifm = iflib_get_media(ctx); 1590 1591 INIT_DEBUGOUT("em_if_media_change: begin"); 1592 1593 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1594 return (EINVAL); 1595 1596 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1597 case IFM_AUTO: 1598 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1599 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1600 break; 1601 case IFM_1000_LX: 1602 case IFM_1000_SX: 1603 case IFM_1000_T: 1604 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1605 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1606 break; 1607 case IFM_100_TX: 1608 adapter->hw.mac.autoneg = FALSE; 1609 adapter->hw.phy.autoneg_advertised = 0; 1610 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1611 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1612 else 1613 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1614 break; 1615 case IFM_10_T: 1616 adapter->hw.mac.autoneg = FALSE; 1617 adapter->hw.phy.autoneg_advertised = 0; 1618 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1619 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1620 else 1621 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1622 break; 1623 default: 1624 device_printf(adapter->dev, "Unsupported media type\n"); 1625 } 1626 1627 em_if_init(ctx); 1628 1629 return (0); 1630 } 1631 1632 static int 1633 em_if_set_promisc(if_ctx_t ctx, int flags) 1634 { 1635 struct adapter *adapter = iflib_get_softc(ctx); 1636 u32 reg_rctl; 1637 1638 em_disable_promisc(ctx); 1639 1640 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1641 1642 if (flags & IFF_PROMISC) { 1643 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1644 /* Turn this on if you want to see bad packets */ 1645 if (em_debug_sbp) 1646 reg_rctl |= E1000_RCTL_SBP; 1647 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1648 } else if (flags & IFF_ALLMULTI) { 1649 reg_rctl |= E1000_RCTL_MPE; 1650 reg_rctl &= ~E1000_RCTL_UPE; 1651 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1652 } 1653 return (0); 1654 } 1655 1656 static void 1657 em_disable_promisc(if_ctx_t ctx) 1658 { 1659 struct adapter *adapter = iflib_get_softc(ctx); 1660 struct ifnet *ifp = iflib_get_ifp(ctx); 1661 u32 reg_rctl; 1662 int mcnt = 0; 1663 1664 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1665 reg_rctl &= (~E1000_RCTL_UPE); 1666 if (if_getflags(ifp) & IFF_ALLMULTI) 1667 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1668 else 1669 mcnt = if_llmaddr_count(ifp); 1670 /* Don't disable if in MAX groups */ 1671 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1672 reg_rctl &= (~E1000_RCTL_MPE); 1673 reg_rctl &= (~E1000_RCTL_SBP); 1674 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1675 } 1676 1677 1678 static u_int 1679 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1680 { 1681 u8 *mta = arg; 1682 1683 if (cnt == MAX_NUM_MULTICAST_ADDRESSES) 1684 return (1); 1685 1686 bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1687 1688 return (1); 1689 } 1690 1691 /********************************************************************* 1692 * Multicast Update 1693 * 1694 * This routine is called whenever multicast address list is updated. 1695 * 1696 **********************************************************************/ 1697 1698 static void 1699 em_if_multi_set(if_ctx_t ctx) 1700 { 1701 struct adapter *adapter = iflib_get_softc(ctx); 1702 struct ifnet *ifp = iflib_get_ifp(ctx); 1703 u32 reg_rctl = 0; 1704 u8 *mta; /* Multicast array memory */ 1705 int mcnt = 0; 1706 1707 IOCTL_DEBUGOUT("em_set_multi: begin"); 1708 1709 mta = adapter->mta; 1710 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1711 1712 if (adapter->hw.mac.type == e1000_82542 && 1713 adapter->hw.revision_id == E1000_REVISION_2) { 1714 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1715 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1716 e1000_pci_clear_mwi(&adapter->hw); 1717 reg_rctl |= E1000_RCTL_RST; 1718 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1719 msec_delay(5); 1720 } 1721 1722 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1723 1724 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1725 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1726 reg_rctl |= E1000_RCTL_MPE; 1727 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1728 } else 1729 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1730 1731 if (adapter->hw.mac.type == e1000_82542 && 1732 adapter->hw.revision_id == E1000_REVISION_2) { 1733 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1734 reg_rctl &= ~E1000_RCTL_RST; 1735 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1736 msec_delay(5); 1737 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1738 e1000_pci_set_mwi(&adapter->hw); 1739 } 1740 } 1741 1742 /********************************************************************* 1743 * Timer routine 1744 * 1745 * This routine schedules em_if_update_admin_status() to check for 1746 * link status and to gather statistics as well as to perform some 1747 * controller-specific hardware patting. 1748 * 1749 **********************************************************************/ 1750 static void 1751 em_if_timer(if_ctx_t ctx, uint16_t qid) 1752 { 1753 1754 if (qid != 0) 1755 return; 1756 1757 iflib_admin_intr_deferred(ctx); 1758 } 1759 1760 static void 1761 em_if_update_admin_status(if_ctx_t ctx) 1762 { 1763 struct adapter *adapter = iflib_get_softc(ctx); 1764 struct e1000_hw *hw = &adapter->hw; 1765 device_t dev = iflib_get_dev(ctx); 1766 u32 link_check, thstat, ctrl; 1767 1768 link_check = thstat = ctrl = 0; 1769 /* Get the cached link value or read phy for real */ 1770 switch (hw->phy.media_type) { 1771 case e1000_media_type_copper: 1772 if (hw->mac.get_link_status) { 1773 if (hw->mac.type == e1000_pch_spt) 1774 msec_delay(50); 1775 /* Do the work to read phy */ 1776 e1000_check_for_link(hw); 1777 link_check = !hw->mac.get_link_status; 1778 if (link_check) /* ESB2 fix */ 1779 e1000_cfg_on_link_up(hw); 1780 } else { 1781 link_check = TRUE; 1782 } 1783 break; 1784 case e1000_media_type_fiber: 1785 e1000_check_for_link(hw); 1786 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1787 E1000_STATUS_LU); 1788 break; 1789 case e1000_media_type_internal_serdes: 1790 e1000_check_for_link(hw); 1791 link_check = hw->mac.serdes_has_link; 1792 break; 1793 /* VF device is type_unknown */ 1794 case e1000_media_type_unknown: 1795 e1000_check_for_link(hw); 1796 link_check = !hw->mac.get_link_status; 1797 /* FALLTHROUGH */ 1798 default: 1799 break; 1800 } 1801 1802 /* Check for thermal downshift or shutdown */ 1803 if (hw->mac.type == e1000_i350) { 1804 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1805 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1806 } 1807 1808 /* Now check for a transition */ 1809 if (link_check && (adapter->link_active == 0)) { 1810 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1811 &adapter->link_duplex); 1812 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1813 if ((adapter->link_speed != SPEED_1000) && 1814 ((hw->mac.type == e1000_82571) || 1815 (hw->mac.type == e1000_82572))) { 1816 int tarc0; 1817 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1818 tarc0 &= ~TARC_SPEED_MODE_BIT; 1819 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1820 } 1821 if (bootverbose) 1822 device_printf(dev, "Link is up %d Mbps %s\n", 1823 adapter->link_speed, 1824 ((adapter->link_duplex == FULL_DUPLEX) ? 1825 "Full Duplex" : "Half Duplex")); 1826 adapter->link_active = 1; 1827 adapter->smartspeed = 0; 1828 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1829 E1000_CTRL_EXT_LINK_MODE_GMII && 1830 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1831 device_printf(dev, "Link: thermal downshift\n"); 1832 /* Delay Link Up for Phy update */ 1833 if (((hw->mac.type == e1000_i210) || 1834 (hw->mac.type == e1000_i211)) && 1835 (hw->phy.id == I210_I_PHY_ID)) 1836 msec_delay(I210_LINK_DELAY); 1837 /* Reset if the media type changed. */ 1838 if (hw->dev_spec._82575.media_changed && 1839 hw->mac.type >= igb_mac_min) { 1840 hw->dev_spec._82575.media_changed = false; 1841 adapter->flags |= IGB_MEDIA_RESET; 1842 em_reset(ctx); 1843 } 1844 iflib_link_state_change(ctx, LINK_STATE_UP, 1845 IF_Mbps(adapter->link_speed)); 1846 } else if (!link_check && (adapter->link_active == 1)) { 1847 adapter->link_speed = 0; 1848 adapter->link_duplex = 0; 1849 adapter->link_active = 0; 1850 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1851 } 1852 em_update_stats_counters(adapter); 1853 1854 /* Reset LAA into RAR[0] on 82571 */ 1855 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1856 e1000_rar_set(hw, hw->mac.addr, 0); 1857 1858 if (hw->mac.type < em_mac_min) 1859 lem_smartspeed(adapter); 1860 else if (hw->mac.type == e1000_82574 && 1861 adapter->intr_type == IFLIB_INTR_MSIX) 1862 E1000_WRITE_REG(hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1863 } 1864 1865 static void 1866 em_if_watchdog_reset(if_ctx_t ctx) 1867 { 1868 struct adapter *adapter = iflib_get_softc(ctx); 1869 1870 /* 1871 * Just count the event; iflib(4) will already trigger a 1872 * sufficient reset of the controller. 1873 */ 1874 adapter->watchdog_events++; 1875 } 1876 1877 /********************************************************************* 1878 * 1879 * This routine disables all traffic on the adapter by issuing a 1880 * global reset on the MAC. 1881 * 1882 **********************************************************************/ 1883 static void 1884 em_if_stop(if_ctx_t ctx) 1885 { 1886 struct adapter *adapter = iflib_get_softc(ctx); 1887 1888 INIT_DEBUGOUT("em_if_stop: begin"); 1889 1890 e1000_reset_hw(&adapter->hw); 1891 if (adapter->hw.mac.type >= e1000_82544) 1892 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1893 1894 e1000_led_off(&adapter->hw); 1895 e1000_cleanup_led(&adapter->hw); 1896 } 1897 1898 /********************************************************************* 1899 * 1900 * Determine hardware revision. 1901 * 1902 **********************************************************************/ 1903 static void 1904 em_identify_hardware(if_ctx_t ctx) 1905 { 1906 device_t dev = iflib_get_dev(ctx); 1907 struct adapter *adapter = iflib_get_softc(ctx); 1908 1909 /* Make sure our PCI config space has the necessary stuff set */ 1910 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1911 1912 /* Save off the information about this board */ 1913 adapter->hw.vendor_id = pci_get_vendor(dev); 1914 adapter->hw.device_id = pci_get_device(dev); 1915 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1916 adapter->hw.subsystem_vendor_id = 1917 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1918 adapter->hw.subsystem_device_id = 1919 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1920 1921 /* Do Shared Code Init and Setup */ 1922 if (e1000_set_mac_type(&adapter->hw)) { 1923 device_printf(dev, "Setup init failure\n"); 1924 return; 1925 } 1926 } 1927 1928 static int 1929 em_allocate_pci_resources(if_ctx_t ctx) 1930 { 1931 struct adapter *adapter = iflib_get_softc(ctx); 1932 device_t dev = iflib_get_dev(ctx); 1933 int rid, val; 1934 1935 rid = PCIR_BAR(0); 1936 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1937 &rid, RF_ACTIVE); 1938 if (adapter->memory == NULL) { 1939 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1940 return (ENXIO); 1941 } 1942 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1943 adapter->osdep.mem_bus_space_handle = 1944 rman_get_bushandle(adapter->memory); 1945 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1946 1947 /* Only older adapters use IO mapping */ 1948 if (adapter->hw.mac.type < em_mac_min && 1949 adapter->hw.mac.type > e1000_82543) { 1950 /* Figure our where our IO BAR is ? */ 1951 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1952 val = pci_read_config(dev, rid, 4); 1953 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1954 break; 1955 } 1956 rid += 4; 1957 /* check for 64bit BAR */ 1958 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1959 rid += 4; 1960 } 1961 if (rid >= PCIR_CIS) { 1962 device_printf(dev, "Unable to locate IO BAR\n"); 1963 return (ENXIO); 1964 } 1965 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1966 &rid, RF_ACTIVE); 1967 if (adapter->ioport == NULL) { 1968 device_printf(dev, "Unable to allocate bus resource: " 1969 "ioport\n"); 1970 return (ENXIO); 1971 } 1972 adapter->hw.io_base = 0; 1973 adapter->osdep.io_bus_space_tag = 1974 rman_get_bustag(adapter->ioport); 1975 adapter->osdep.io_bus_space_handle = 1976 rman_get_bushandle(adapter->ioport); 1977 } 1978 1979 adapter->hw.back = &adapter->osdep; 1980 1981 return (0); 1982 } 1983 1984 /********************************************************************* 1985 * 1986 * Set up the MSI-X Interrupt handlers 1987 * 1988 **********************************************************************/ 1989 static int 1990 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1991 { 1992 struct adapter *adapter = iflib_get_softc(ctx); 1993 struct em_rx_queue *rx_que = adapter->rx_queues; 1994 struct em_tx_queue *tx_que = adapter->tx_queues; 1995 int error, rid, i, vector = 0, rx_vectors; 1996 char buf[16]; 1997 1998 /* First set up ring resources */ 1999 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2000 rid = vector + 1; 2001 snprintf(buf, sizeof(buf), "rxq%d", i); 2002 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2003 if (error) { 2004 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2005 adapter->rx_num_queues = i + 1; 2006 goto fail; 2007 } 2008 2009 rx_que->msix = vector; 2010 2011 /* 2012 * Set the bit to enable interrupt 2013 * in E1000_IMS -- bits 20 and 21 2014 * are for RX0 and RX1, note this has 2015 * NOTHING to do with the MSI-X vector 2016 */ 2017 if (adapter->hw.mac.type == e1000_82574) { 2018 rx_que->eims = 1 << (20 + i); 2019 adapter->ims |= rx_que->eims; 2020 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2021 } else if (adapter->hw.mac.type == e1000_82575) 2022 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2023 else 2024 rx_que->eims = 1 << vector; 2025 } 2026 rx_vectors = vector; 2027 2028 vector = 0; 2029 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2030 snprintf(buf, sizeof(buf), "txq%d", i); 2031 tx_que = &adapter->tx_queues[i]; 2032 iflib_softirq_alloc_generic(ctx, 2033 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2034 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2035 2036 tx_que->msix = (vector % adapter->rx_num_queues); 2037 2038 /* 2039 * Set the bit to enable interrupt 2040 * in E1000_IMS -- bits 22 and 23 2041 * are for TX0 and TX1, note this has 2042 * NOTHING to do with the MSI-X vector 2043 */ 2044 if (adapter->hw.mac.type == e1000_82574) { 2045 tx_que->eims = 1 << (22 + i); 2046 adapter->ims |= tx_que->eims; 2047 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2048 } else if (adapter->hw.mac.type == e1000_82575) { 2049 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2050 } else { 2051 tx_que->eims = 1 << i; 2052 } 2053 } 2054 2055 /* Link interrupt */ 2056 rid = rx_vectors + 1; 2057 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2058 2059 if (error) { 2060 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2061 goto fail; 2062 } 2063 adapter->linkvec = rx_vectors; 2064 if (adapter->hw.mac.type < igb_mac_min) { 2065 adapter->ivars |= (8 | rx_vectors) << 16; 2066 adapter->ivars |= 0x80000000; 2067 } 2068 return (0); 2069 fail: 2070 iflib_irq_free(ctx, &adapter->irq); 2071 rx_que = adapter->rx_queues; 2072 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2073 iflib_irq_free(ctx, &rx_que->que_irq); 2074 return (error); 2075 } 2076 2077 static void 2078 igb_configure_queues(struct adapter *adapter) 2079 { 2080 struct e1000_hw *hw = &adapter->hw; 2081 struct em_rx_queue *rx_que; 2082 struct em_tx_queue *tx_que; 2083 u32 tmp, ivar = 0, newitr = 0; 2084 2085 /* First turn on RSS capability */ 2086 if (hw->mac.type != e1000_82575) 2087 E1000_WRITE_REG(hw, E1000_GPIE, 2088 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2089 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2090 2091 /* Turn on MSI-X */ 2092 switch (hw->mac.type) { 2093 case e1000_82580: 2094 case e1000_i350: 2095 case e1000_i354: 2096 case e1000_i210: 2097 case e1000_i211: 2098 case e1000_vfadapt: 2099 case e1000_vfadapt_i350: 2100 /* RX entries */ 2101 for (int i = 0; i < adapter->rx_num_queues; i++) { 2102 u32 index = i >> 1; 2103 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2104 rx_que = &adapter->rx_queues[i]; 2105 if (i & 1) { 2106 ivar &= 0xFF00FFFF; 2107 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2108 } else { 2109 ivar &= 0xFFFFFF00; 2110 ivar |= rx_que->msix | E1000_IVAR_VALID; 2111 } 2112 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2113 } 2114 /* TX entries */ 2115 for (int i = 0; i < adapter->tx_num_queues; i++) { 2116 u32 index = i >> 1; 2117 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2118 tx_que = &adapter->tx_queues[i]; 2119 if (i & 1) { 2120 ivar &= 0x00FFFFFF; 2121 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2122 } else { 2123 ivar &= 0xFFFF00FF; 2124 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2125 } 2126 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2127 adapter->que_mask |= tx_que->eims; 2128 } 2129 2130 /* And for the link interrupt */ 2131 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2132 adapter->link_mask = 1 << adapter->linkvec; 2133 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2134 break; 2135 case e1000_82576: 2136 /* RX entries */ 2137 for (int i = 0; i < adapter->rx_num_queues; i++) { 2138 u32 index = i & 0x7; /* Each IVAR has two entries */ 2139 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2140 rx_que = &adapter->rx_queues[i]; 2141 if (i < 8) { 2142 ivar &= 0xFFFFFF00; 2143 ivar |= rx_que->msix | E1000_IVAR_VALID; 2144 } else { 2145 ivar &= 0xFF00FFFF; 2146 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2147 } 2148 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2149 adapter->que_mask |= rx_que->eims; 2150 } 2151 /* TX entries */ 2152 for (int i = 0; i < adapter->tx_num_queues; i++) { 2153 u32 index = i & 0x7; /* Each IVAR has two entries */ 2154 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2155 tx_que = &adapter->tx_queues[i]; 2156 if (i < 8) { 2157 ivar &= 0xFFFF00FF; 2158 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2159 } else { 2160 ivar &= 0x00FFFFFF; 2161 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2162 } 2163 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2164 adapter->que_mask |= tx_que->eims; 2165 } 2166 2167 /* And for the link interrupt */ 2168 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2169 adapter->link_mask = 1 << adapter->linkvec; 2170 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2171 break; 2172 2173 case e1000_82575: 2174 /* enable MSI-X support*/ 2175 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2176 tmp |= E1000_CTRL_EXT_PBA_CLR; 2177 /* Auto-Mask interrupts upon ICR read. */ 2178 tmp |= E1000_CTRL_EXT_EIAME; 2179 tmp |= E1000_CTRL_EXT_IRCA; 2180 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2181 2182 /* Queues */ 2183 for (int i = 0; i < adapter->rx_num_queues; i++) { 2184 rx_que = &adapter->rx_queues[i]; 2185 tmp = E1000_EICR_RX_QUEUE0 << i; 2186 tmp |= E1000_EICR_TX_QUEUE0 << i; 2187 rx_que->eims = tmp; 2188 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2189 i, rx_que->eims); 2190 adapter->que_mask |= rx_que->eims; 2191 } 2192 2193 /* Link */ 2194 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2195 E1000_EIMS_OTHER); 2196 adapter->link_mask |= E1000_EIMS_OTHER; 2197 default: 2198 break; 2199 } 2200 2201 /* Set the starting interrupt rate */ 2202 if (em_max_interrupt_rate > 0) 2203 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2204 2205 if (hw->mac.type == e1000_82575) 2206 newitr |= newitr << 16; 2207 else 2208 newitr |= E1000_EITR_CNT_IGNR; 2209 2210 for (int i = 0; i < adapter->rx_num_queues; i++) { 2211 rx_que = &adapter->rx_queues[i]; 2212 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2213 } 2214 2215 return; 2216 } 2217 2218 static void 2219 em_free_pci_resources(if_ctx_t ctx) 2220 { 2221 struct adapter *adapter = iflib_get_softc(ctx); 2222 struct em_rx_queue *que = adapter->rx_queues; 2223 device_t dev = iflib_get_dev(ctx); 2224 2225 /* Release all MSI-X queue resources */ 2226 if (adapter->intr_type == IFLIB_INTR_MSIX) 2227 iflib_irq_free(ctx, &adapter->irq); 2228 2229 if (que != NULL) { 2230 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2231 iflib_irq_free(ctx, &que->que_irq); 2232 } 2233 } 2234 2235 if (adapter->memory != NULL) { 2236 bus_release_resource(dev, SYS_RES_MEMORY, 2237 rman_get_rid(adapter->memory), adapter->memory); 2238 adapter->memory = NULL; 2239 } 2240 2241 if (adapter->flash != NULL) { 2242 bus_release_resource(dev, SYS_RES_MEMORY, 2243 rman_get_rid(adapter->flash), adapter->flash); 2244 adapter->flash = NULL; 2245 } 2246 2247 if (adapter->ioport != NULL) { 2248 bus_release_resource(dev, SYS_RES_IOPORT, 2249 rman_get_rid(adapter->ioport), adapter->ioport); 2250 adapter->ioport = NULL; 2251 } 2252 } 2253 2254 /* Set up MSI or MSI-X */ 2255 static int 2256 em_setup_msix(if_ctx_t ctx) 2257 { 2258 struct adapter *adapter = iflib_get_softc(ctx); 2259 2260 if (adapter->hw.mac.type == e1000_82574) { 2261 em_enable_vectors_82574(ctx); 2262 } 2263 return (0); 2264 } 2265 2266 /********************************************************************* 2267 * 2268 * Workaround for SmartSpeed on 82541 and 82547 controllers 2269 * 2270 **********************************************************************/ 2271 static void 2272 lem_smartspeed(struct adapter *adapter) 2273 { 2274 u16 phy_tmp; 2275 2276 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2277 adapter->hw.mac.autoneg == 0 || 2278 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2279 return; 2280 2281 if (adapter->smartspeed == 0) { 2282 /* If Master/Slave config fault is asserted twice, 2283 * we assume back-to-back */ 2284 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2285 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2286 return; 2287 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2288 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2289 e1000_read_phy_reg(&adapter->hw, 2290 PHY_1000T_CTRL, &phy_tmp); 2291 if(phy_tmp & CR_1000T_MS_ENABLE) { 2292 phy_tmp &= ~CR_1000T_MS_ENABLE; 2293 e1000_write_phy_reg(&adapter->hw, 2294 PHY_1000T_CTRL, phy_tmp); 2295 adapter->smartspeed++; 2296 if(adapter->hw.mac.autoneg && 2297 !e1000_copper_link_autoneg(&adapter->hw) && 2298 !e1000_read_phy_reg(&adapter->hw, 2299 PHY_CONTROL, &phy_tmp)) { 2300 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2301 MII_CR_RESTART_AUTO_NEG); 2302 e1000_write_phy_reg(&adapter->hw, 2303 PHY_CONTROL, phy_tmp); 2304 } 2305 } 2306 } 2307 return; 2308 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2309 /* If still no link, perhaps using 2/3 pair cable */ 2310 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2311 phy_tmp |= CR_1000T_MS_ENABLE; 2312 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2313 if(adapter->hw.mac.autoneg && 2314 !e1000_copper_link_autoneg(&adapter->hw) && 2315 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2316 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2317 MII_CR_RESTART_AUTO_NEG); 2318 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2319 } 2320 } 2321 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2322 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2323 adapter->smartspeed = 0; 2324 } 2325 2326 /********************************************************************* 2327 * 2328 * Initialize the DMA Coalescing feature 2329 * 2330 **********************************************************************/ 2331 static void 2332 igb_init_dmac(struct adapter *adapter, u32 pba) 2333 { 2334 device_t dev = adapter->dev; 2335 struct e1000_hw *hw = &adapter->hw; 2336 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2337 u16 hwm; 2338 u16 max_frame_size; 2339 2340 if (hw->mac.type == e1000_i211) 2341 return; 2342 2343 max_frame_size = adapter->shared->isc_max_frame_size; 2344 if (hw->mac.type > e1000_82580) { 2345 2346 if (adapter->dmac == 0) { /* Disabling it */ 2347 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2348 return; 2349 } else 2350 device_printf(dev, "DMA Coalescing enabled\n"); 2351 2352 /* Set starting threshold */ 2353 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2354 2355 hwm = 64 * pba - max_frame_size / 16; 2356 if (hwm < 64 * (pba - 6)) 2357 hwm = 64 * (pba - 6); 2358 reg = E1000_READ_REG(hw, E1000_FCRTC); 2359 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2360 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2361 & E1000_FCRTC_RTH_COAL_MASK); 2362 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2363 2364 2365 dmac = pba - max_frame_size / 512; 2366 if (dmac < pba - 10) 2367 dmac = pba - 10; 2368 reg = E1000_READ_REG(hw, E1000_DMACR); 2369 reg &= ~E1000_DMACR_DMACTHR_MASK; 2370 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2371 & E1000_DMACR_DMACTHR_MASK); 2372 2373 /* transition to L0x or L1 if available..*/ 2374 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2375 2376 /* Check if status is 2.5Gb backplane connection 2377 * before configuration of watchdog timer, which is 2378 * in msec values in 12.8usec intervals 2379 * watchdog timer= msec values in 32usec intervals 2380 * for non 2.5Gb connection 2381 */ 2382 if (hw->mac.type == e1000_i354) { 2383 int status = E1000_READ_REG(hw, E1000_STATUS); 2384 if ((status & E1000_STATUS_2P5_SKU) && 2385 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2386 reg |= ((adapter->dmac * 5) >> 6); 2387 else 2388 reg |= (adapter->dmac >> 5); 2389 } else { 2390 reg |= (adapter->dmac >> 5); 2391 } 2392 2393 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2394 2395 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2396 2397 /* Set the interval before transition */ 2398 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2399 if (hw->mac.type == e1000_i350) 2400 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2401 /* 2402 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2403 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2404 */ 2405 if (hw->mac.type == e1000_i354) { 2406 int status = E1000_READ_REG(hw, E1000_STATUS); 2407 if ((status & E1000_STATUS_2P5_SKU) && 2408 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2409 reg |= 0xA; 2410 else 2411 reg |= 0x4; 2412 } else { 2413 reg |= 0x4; 2414 } 2415 2416 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2417 2418 /* free space in tx packet buffer to wake from DMA coal */ 2419 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2420 (2 * max_frame_size)) >> 6); 2421 2422 /* make low power state decision controlled by DMA coal */ 2423 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2424 reg &= ~E1000_PCIEMISC_LX_DECISION; 2425 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2426 2427 } else if (hw->mac.type == e1000_82580) { 2428 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2429 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2430 reg & ~E1000_PCIEMISC_LX_DECISION); 2431 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2432 } 2433 } 2434 2435 /********************************************************************* 2436 * 2437 * Initialize the hardware to a configuration as specified by the 2438 * adapter structure. 2439 * 2440 **********************************************************************/ 2441 static void 2442 em_reset(if_ctx_t ctx) 2443 { 2444 device_t dev = iflib_get_dev(ctx); 2445 struct adapter *adapter = iflib_get_softc(ctx); 2446 struct ifnet *ifp = iflib_get_ifp(ctx); 2447 struct e1000_hw *hw = &adapter->hw; 2448 u16 rx_buffer_size; 2449 u32 pba; 2450 2451 INIT_DEBUGOUT("em_reset: begin"); 2452 /* Let the firmware know the OS is in control */ 2453 em_get_hw_control(adapter); 2454 2455 /* Set up smart power down as default off on newer adapters. */ 2456 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2457 hw->mac.type == e1000_82572)) { 2458 u16 phy_tmp = 0; 2459 2460 /* Speed up time to link by disabling smart power down. */ 2461 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2462 phy_tmp &= ~IGP02E1000_PM_SPD; 2463 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2464 } 2465 2466 /* 2467 * Packet Buffer Allocation (PBA) 2468 * Writing PBA sets the receive portion of the buffer 2469 * the remainder is used for the transmit buffer. 2470 */ 2471 switch (hw->mac.type) { 2472 /* Total Packet Buffer on these is 48K */ 2473 case e1000_82571: 2474 case e1000_82572: 2475 case e1000_80003es2lan: 2476 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2477 break; 2478 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2479 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2480 break; 2481 case e1000_82574: 2482 case e1000_82583: 2483 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2484 break; 2485 case e1000_ich8lan: 2486 pba = E1000_PBA_8K; 2487 break; 2488 case e1000_ich9lan: 2489 case e1000_ich10lan: 2490 /* Boost Receive side for jumbo frames */ 2491 if (hw->mac.max_frame_size > 4096) 2492 pba = E1000_PBA_14K; 2493 else 2494 pba = E1000_PBA_10K; 2495 break; 2496 case e1000_pchlan: 2497 case e1000_pch2lan: 2498 case e1000_pch_lpt: 2499 case e1000_pch_spt: 2500 case e1000_pch_cnp: 2501 pba = E1000_PBA_26K; 2502 break; 2503 case e1000_82575: 2504 pba = E1000_PBA_32K; 2505 break; 2506 case e1000_82576: 2507 case e1000_vfadapt: 2508 pba = E1000_READ_REG(hw, E1000_RXPBS); 2509 pba &= E1000_RXPBS_SIZE_MASK_82576; 2510 break; 2511 case e1000_82580: 2512 case e1000_i350: 2513 case e1000_i354: 2514 case e1000_vfadapt_i350: 2515 pba = E1000_READ_REG(hw, E1000_RXPBS); 2516 pba = e1000_rxpbs_adjust_82580(pba); 2517 break; 2518 case e1000_i210: 2519 case e1000_i211: 2520 pba = E1000_PBA_34K; 2521 break; 2522 default: 2523 if (hw->mac.max_frame_size > 8192) 2524 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2525 else 2526 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2527 } 2528 2529 /* Special needs in case of Jumbo frames */ 2530 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2531 u32 tx_space, min_tx, min_rx; 2532 pba = E1000_READ_REG(hw, E1000_PBA); 2533 tx_space = pba >> 16; 2534 pba &= 0xffff; 2535 min_tx = (hw->mac.max_frame_size + 2536 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2537 min_tx = roundup2(min_tx, 1024); 2538 min_tx >>= 10; 2539 min_rx = hw->mac.max_frame_size; 2540 min_rx = roundup2(min_rx, 1024); 2541 min_rx >>= 10; 2542 if (tx_space < min_tx && 2543 ((min_tx - tx_space) < pba)) { 2544 pba = pba - (min_tx - tx_space); 2545 /* 2546 * if short on rx space, rx wins 2547 * and must trump tx adjustment 2548 */ 2549 if (pba < min_rx) 2550 pba = min_rx; 2551 } 2552 E1000_WRITE_REG(hw, E1000_PBA, pba); 2553 } 2554 2555 if (hw->mac.type < igb_mac_min) 2556 E1000_WRITE_REG(hw, E1000_PBA, pba); 2557 2558 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2559 2560 /* 2561 * These parameters control the automatic generation (Tx) and 2562 * response (Rx) to Ethernet PAUSE frames. 2563 * - High water mark should allow for at least two frames to be 2564 * received after sending an XOFF. 2565 * - Low water mark works best when it is very near the high water mark. 2566 * This allows the receiver to restart by sending XON when it has 2567 * drained a bit. Here we use an arbitrary value of 1500 which will 2568 * restart after one full frame is pulled from the buffer. There 2569 * could be several smaller frames in the buffer and if so they will 2570 * not trigger the XON until their total number reduces the buffer 2571 * by 1500. 2572 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2573 */ 2574 rx_buffer_size = (pba & 0xffff) << 10; 2575 hw->fc.high_water = rx_buffer_size - 2576 roundup2(hw->mac.max_frame_size, 1024); 2577 hw->fc.low_water = hw->fc.high_water - 1500; 2578 2579 if (adapter->fc) /* locally set flow control value? */ 2580 hw->fc.requested_mode = adapter->fc; 2581 else 2582 hw->fc.requested_mode = e1000_fc_full; 2583 2584 if (hw->mac.type == e1000_80003es2lan) 2585 hw->fc.pause_time = 0xFFFF; 2586 else 2587 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2588 2589 hw->fc.send_xon = TRUE; 2590 2591 /* Device specific overrides/settings */ 2592 switch (hw->mac.type) { 2593 case e1000_pchlan: 2594 /* Workaround: no TX flow ctrl for PCH */ 2595 hw->fc.requested_mode = e1000_fc_rx_pause; 2596 hw->fc.pause_time = 0xFFFF; /* override */ 2597 if (if_getmtu(ifp) > ETHERMTU) { 2598 hw->fc.high_water = 0x3500; 2599 hw->fc.low_water = 0x1500; 2600 } else { 2601 hw->fc.high_water = 0x5000; 2602 hw->fc.low_water = 0x3000; 2603 } 2604 hw->fc.refresh_time = 0x1000; 2605 break; 2606 case e1000_pch2lan: 2607 case e1000_pch_lpt: 2608 case e1000_pch_spt: 2609 case e1000_pch_cnp: 2610 hw->fc.high_water = 0x5C20; 2611 hw->fc.low_water = 0x5048; 2612 hw->fc.pause_time = 0x0650; 2613 hw->fc.refresh_time = 0x0400; 2614 /* Jumbos need adjusted PBA */ 2615 if (if_getmtu(ifp) > ETHERMTU) 2616 E1000_WRITE_REG(hw, E1000_PBA, 12); 2617 else 2618 E1000_WRITE_REG(hw, E1000_PBA, 26); 2619 break; 2620 case e1000_82575: 2621 case e1000_82576: 2622 /* 8-byte granularity */ 2623 hw->fc.low_water = hw->fc.high_water - 8; 2624 break; 2625 case e1000_82580: 2626 case e1000_i350: 2627 case e1000_i354: 2628 case e1000_i210: 2629 case e1000_i211: 2630 case e1000_vfadapt: 2631 case e1000_vfadapt_i350: 2632 /* 16-byte granularity */ 2633 hw->fc.low_water = hw->fc.high_water - 16; 2634 break; 2635 case e1000_ich9lan: 2636 case e1000_ich10lan: 2637 if (if_getmtu(ifp) > ETHERMTU) { 2638 hw->fc.high_water = 0x2800; 2639 hw->fc.low_water = hw->fc.high_water - 8; 2640 break; 2641 } 2642 /* FALLTHROUGH */ 2643 default: 2644 if (hw->mac.type == e1000_80003es2lan) 2645 hw->fc.pause_time = 0xFFFF; 2646 break; 2647 } 2648 2649 /* Issue a global reset */ 2650 e1000_reset_hw(hw); 2651 if (hw->mac.type >= igb_mac_min) { 2652 E1000_WRITE_REG(hw, E1000_WUC, 0); 2653 } else { 2654 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2655 em_disable_aspm(adapter); 2656 } 2657 if (adapter->flags & IGB_MEDIA_RESET) { 2658 e1000_setup_init_funcs(hw, TRUE); 2659 e1000_get_bus_info(hw); 2660 adapter->flags &= ~IGB_MEDIA_RESET; 2661 } 2662 /* and a re-init */ 2663 if (e1000_init_hw(hw) < 0) { 2664 device_printf(dev, "Hardware Initialization Failed\n"); 2665 return; 2666 } 2667 if (hw->mac.type >= igb_mac_min) 2668 igb_init_dmac(adapter, pba); 2669 2670 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2671 e1000_get_phy_info(hw); 2672 e1000_check_for_link(hw); 2673 } 2674 2675 /* 2676 * Initialise the RSS mapping for NICs that support multiple transmit/ 2677 * receive rings. 2678 */ 2679 2680 #define RSSKEYLEN 10 2681 static void 2682 em_initialize_rss_mapping(struct adapter *adapter) 2683 { 2684 uint8_t rss_key[4 * RSSKEYLEN]; 2685 uint32_t reta = 0; 2686 struct e1000_hw *hw = &adapter->hw; 2687 int i; 2688 2689 /* 2690 * Configure RSS key 2691 */ 2692 arc4rand(rss_key, sizeof(rss_key), 0); 2693 for (i = 0; i < RSSKEYLEN; ++i) { 2694 uint32_t rssrk = 0; 2695 2696 rssrk = EM_RSSRK_VAL(rss_key, i); 2697 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2698 } 2699 2700 /* 2701 * Configure RSS redirect table in following fashion: 2702 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2703 */ 2704 for (i = 0; i < sizeof(reta); ++i) { 2705 uint32_t q; 2706 2707 q = (i % adapter->rx_num_queues) << 7; 2708 reta |= q << (8 * i); 2709 } 2710 2711 for (i = 0; i < 32; ++i) 2712 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2713 2714 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2715 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2716 E1000_MRQC_RSS_FIELD_IPV4 | 2717 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2718 E1000_MRQC_RSS_FIELD_IPV6_EX | 2719 E1000_MRQC_RSS_FIELD_IPV6); 2720 } 2721 2722 static void 2723 igb_initialize_rss_mapping(struct adapter *adapter) 2724 { 2725 struct e1000_hw *hw = &adapter->hw; 2726 int i; 2727 int queue_id; 2728 u32 reta; 2729 u32 rss_key[10], mrqc, shift = 0; 2730 2731 /* XXX? */ 2732 if (hw->mac.type == e1000_82575) 2733 shift = 6; 2734 2735 /* 2736 * The redirection table controls which destination 2737 * queue each bucket redirects traffic to. 2738 * Each DWORD represents four queues, with the LSB 2739 * being the first queue in the DWORD. 2740 * 2741 * This just allocates buckets to queues using round-robin 2742 * allocation. 2743 * 2744 * NOTE: It Just Happens to line up with the default 2745 * RSS allocation method. 2746 */ 2747 2748 /* Warning FM follows */ 2749 reta = 0; 2750 for (i = 0; i < 128; i++) { 2751 #ifdef RSS 2752 queue_id = rss_get_indirection_to_bucket(i); 2753 /* 2754 * If we have more queues than buckets, we'll 2755 * end up mapping buckets to a subset of the 2756 * queues. 2757 * 2758 * If we have more buckets than queues, we'll 2759 * end up instead assigning multiple buckets 2760 * to queues. 2761 * 2762 * Both are suboptimal, but we need to handle 2763 * the case so we don't go out of bounds 2764 * indexing arrays and such. 2765 */ 2766 queue_id = queue_id % adapter->rx_num_queues; 2767 #else 2768 queue_id = (i % adapter->rx_num_queues); 2769 #endif 2770 /* Adjust if required */ 2771 queue_id = queue_id << shift; 2772 2773 /* 2774 * The low 8 bits are for hash value (n+0); 2775 * The next 8 bits are for hash value (n+1), etc. 2776 */ 2777 reta = reta >> 8; 2778 reta = reta | ( ((uint32_t) queue_id) << 24); 2779 if ((i & 3) == 3) { 2780 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2781 reta = 0; 2782 } 2783 } 2784 2785 /* Now fill in hash table */ 2786 2787 /* 2788 * MRQC: Multiple Receive Queues Command 2789 * Set queuing to RSS control, number depends on the device. 2790 */ 2791 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2792 2793 #ifdef RSS 2794 /* XXX ew typecasting */ 2795 rss_getkey((uint8_t *) &rss_key); 2796 #else 2797 arc4rand(&rss_key, sizeof(rss_key), 0); 2798 #endif 2799 for (i = 0; i < 10; i++) 2800 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2801 2802 /* 2803 * Configure the RSS fields to hash upon. 2804 */ 2805 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2806 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2807 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2808 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2809 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2810 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2811 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2812 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2813 2814 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2815 } 2816 2817 /********************************************************************* 2818 * 2819 * Setup networking device structure and register interface media. 2820 * 2821 **********************************************************************/ 2822 static int 2823 em_setup_interface(if_ctx_t ctx) 2824 { 2825 struct ifnet *ifp = iflib_get_ifp(ctx); 2826 struct adapter *adapter = iflib_get_softc(ctx); 2827 if_softc_ctx_t scctx = adapter->shared; 2828 2829 INIT_DEBUGOUT("em_setup_interface: begin"); 2830 2831 /* Single Queue */ 2832 if (adapter->tx_num_queues == 1) { 2833 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2834 if_setsendqready(ifp); 2835 } 2836 2837 /* 2838 * Specify the media types supported by this adapter and register 2839 * callbacks to update media and link information 2840 */ 2841 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2842 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2843 u_char fiber_type = IFM_1000_SX; /* default type */ 2844 2845 if (adapter->hw.mac.type == e1000_82545) 2846 fiber_type = IFM_1000_LX; 2847 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2848 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2849 } else { 2850 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2851 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2852 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2853 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2854 if (adapter->hw.phy.type != e1000_phy_ife) { 2855 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2856 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2857 } 2858 } 2859 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2860 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2861 return (0); 2862 } 2863 2864 static int 2865 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2866 { 2867 struct adapter *adapter = iflib_get_softc(ctx); 2868 if_softc_ctx_t scctx = adapter->shared; 2869 int error = E1000_SUCCESS; 2870 struct em_tx_queue *que; 2871 int i, j; 2872 2873 MPASS(adapter->tx_num_queues > 0); 2874 MPASS(adapter->tx_num_queues == ntxqsets); 2875 2876 /* First allocate the top level queue structs */ 2877 if (!(adapter->tx_queues = 2878 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2879 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2880 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2881 return(ENOMEM); 2882 } 2883 2884 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2885 /* Set up some basics */ 2886 2887 struct tx_ring *txr = &que->txr; 2888 txr->adapter = que->adapter = adapter; 2889 que->me = txr->me = i; 2890 2891 /* Allocate report status array */ 2892 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2893 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2894 error = ENOMEM; 2895 goto fail; 2896 } 2897 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2898 txr->tx_rsq[j] = QIDX_INVALID; 2899 /* get the virtual and physical address of the hardware queues */ 2900 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2901 txr->tx_paddr = paddrs[i*ntxqs]; 2902 } 2903 2904 if (bootverbose) 2905 device_printf(iflib_get_dev(ctx), 2906 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2907 return (0); 2908 fail: 2909 em_if_queues_free(ctx); 2910 return (error); 2911 } 2912 2913 static int 2914 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2915 { 2916 struct adapter *adapter = iflib_get_softc(ctx); 2917 int error = E1000_SUCCESS; 2918 struct em_rx_queue *que; 2919 int i; 2920 2921 MPASS(adapter->rx_num_queues > 0); 2922 MPASS(adapter->rx_num_queues == nrxqsets); 2923 2924 /* First allocate the top level queue structs */ 2925 if (!(adapter->rx_queues = 2926 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2927 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2928 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2929 error = ENOMEM; 2930 goto fail; 2931 } 2932 2933 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2934 /* Set up some basics */ 2935 struct rx_ring *rxr = &que->rxr; 2936 rxr->adapter = que->adapter = adapter; 2937 rxr->que = que; 2938 que->me = rxr->me = i; 2939 2940 /* get the virtual and physical address of the hardware queues */ 2941 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2942 rxr->rx_paddr = paddrs[i*nrxqs]; 2943 } 2944 2945 if (bootverbose) 2946 device_printf(iflib_get_dev(ctx), 2947 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2948 2949 return (0); 2950 fail: 2951 em_if_queues_free(ctx); 2952 return (error); 2953 } 2954 2955 static void 2956 em_if_queues_free(if_ctx_t ctx) 2957 { 2958 struct adapter *adapter = iflib_get_softc(ctx); 2959 struct em_tx_queue *tx_que = adapter->tx_queues; 2960 struct em_rx_queue *rx_que = adapter->rx_queues; 2961 2962 if (tx_que != NULL) { 2963 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2964 struct tx_ring *txr = &tx_que->txr; 2965 if (txr->tx_rsq == NULL) 2966 break; 2967 2968 free(txr->tx_rsq, M_DEVBUF); 2969 txr->tx_rsq = NULL; 2970 } 2971 free(adapter->tx_queues, M_DEVBUF); 2972 adapter->tx_queues = NULL; 2973 } 2974 2975 if (rx_que != NULL) { 2976 free(adapter->rx_queues, M_DEVBUF); 2977 adapter->rx_queues = NULL; 2978 } 2979 } 2980 2981 /********************************************************************* 2982 * 2983 * Enable transmit unit. 2984 * 2985 **********************************************************************/ 2986 static void 2987 em_initialize_transmit_unit(if_ctx_t ctx) 2988 { 2989 struct adapter *adapter = iflib_get_softc(ctx); 2990 if_softc_ctx_t scctx = adapter->shared; 2991 struct em_tx_queue *que; 2992 struct tx_ring *txr; 2993 struct e1000_hw *hw = &adapter->hw; 2994 u32 tctl, txdctl = 0, tarc, tipg = 0; 2995 2996 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2997 2998 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2999 u64 bus_addr; 3000 caddr_t offp, endp; 3001 3002 que = &adapter->tx_queues[i]; 3003 txr = &que->txr; 3004 bus_addr = txr->tx_paddr; 3005 3006 /* Clear checksum offload context. */ 3007 offp = (caddr_t)&txr->csum_flags; 3008 endp = (caddr_t)(txr + 1); 3009 bzero(offp, endp - offp); 3010 3011 /* Base and Len of TX Ring */ 3012 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3013 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3014 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3015 (u32)(bus_addr >> 32)); 3016 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3017 (u32)bus_addr); 3018 /* Init the HEAD/TAIL indices */ 3019 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3020 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3021 3022 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3023 E1000_READ_REG(hw, E1000_TDBAL(i)), 3024 E1000_READ_REG(hw, E1000_TDLEN(i))); 3025 3026 txdctl = 0; /* clear txdctl */ 3027 txdctl |= 0x1f; /* PTHRESH */ 3028 txdctl |= 1 << 8; /* HTHRESH */ 3029 txdctl |= 1 << 16;/* WTHRESH */ 3030 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3031 txdctl |= E1000_TXDCTL_GRAN; 3032 txdctl |= 1 << 25; /* LWTHRESH */ 3033 3034 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3035 } 3036 3037 /* Set the default values for the Tx Inter Packet Gap timer */ 3038 switch (hw->mac.type) { 3039 case e1000_80003es2lan: 3040 tipg = DEFAULT_82543_TIPG_IPGR1; 3041 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3042 E1000_TIPG_IPGR2_SHIFT; 3043 break; 3044 case e1000_82542: 3045 tipg = DEFAULT_82542_TIPG_IPGT; 3046 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3047 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3048 break; 3049 default: 3050 if (hw->phy.media_type == e1000_media_type_fiber || 3051 hw->phy.media_type == e1000_media_type_internal_serdes) 3052 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3053 else 3054 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3055 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3056 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3057 } 3058 3059 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3060 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value); 3061 3062 if(hw->mac.type >= e1000_82540) 3063 E1000_WRITE_REG(hw, E1000_TADV, 3064 adapter->tx_abs_int_delay.value); 3065 3066 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3067 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3068 tarc |= TARC_SPEED_MODE_BIT; 3069 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3070 } else if (hw->mac.type == e1000_80003es2lan) { 3071 /* errata: program both queues to unweighted RR */ 3072 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3073 tarc |= 1; 3074 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3075 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3076 tarc |= 1; 3077 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3078 } else if (hw->mac.type == e1000_82574) { 3079 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3080 tarc |= TARC_ERRATA_BIT; 3081 if ( adapter->tx_num_queues > 1) { 3082 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3083 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3084 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3085 } else 3086 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3087 } 3088 3089 if (adapter->tx_int_delay.value > 0) 3090 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3091 3092 /* Program the Transmit Control Register */ 3093 tctl = E1000_READ_REG(hw, E1000_TCTL); 3094 tctl &= ~E1000_TCTL_CT; 3095 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3096 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3097 3098 if (hw->mac.type >= e1000_82571) 3099 tctl |= E1000_TCTL_MULR; 3100 3101 /* This write will effectively turn on the transmit unit. */ 3102 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3103 3104 /* SPT and KBL errata workarounds */ 3105 if (hw->mac.type == e1000_pch_spt) { 3106 u32 reg; 3107 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3108 reg |= E1000_RCTL_RDMTS_HEX; 3109 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3110 /* i218-i219 Specification Update 1.5.4.5 */ 3111 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3112 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3113 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3114 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3115 } 3116 } 3117 3118 /********************************************************************* 3119 * 3120 * Enable receive unit. 3121 * 3122 **********************************************************************/ 3123 3124 static void 3125 em_initialize_receive_unit(if_ctx_t ctx) 3126 { 3127 struct adapter *adapter = iflib_get_softc(ctx); 3128 if_softc_ctx_t scctx = adapter->shared; 3129 struct ifnet *ifp = iflib_get_ifp(ctx); 3130 struct e1000_hw *hw = &adapter->hw; 3131 struct em_rx_queue *que; 3132 int i; 3133 u32 rctl, rxcsum, rfctl; 3134 3135 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3136 3137 /* 3138 * Make sure receives are disabled while setting 3139 * up the descriptor ring 3140 */ 3141 rctl = E1000_READ_REG(hw, E1000_RCTL); 3142 /* Do not disable if ever enabled on this hardware */ 3143 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3144 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3145 3146 /* Setup the Receive Control Register */ 3147 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3148 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3149 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3150 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3151 3152 /* Do not store bad packets */ 3153 rctl &= ~E1000_RCTL_SBP; 3154 3155 /* Enable Long Packet receive */ 3156 if (if_getmtu(ifp) > ETHERMTU) 3157 rctl |= E1000_RCTL_LPE; 3158 else 3159 rctl &= ~E1000_RCTL_LPE; 3160 3161 /* Strip the CRC */ 3162 if (!em_disable_crc_stripping) 3163 rctl |= E1000_RCTL_SECRC; 3164 3165 if (hw->mac.type >= e1000_82540) { 3166 E1000_WRITE_REG(hw, E1000_RADV, 3167 adapter->rx_abs_int_delay.value); 3168 3169 /* 3170 * Set the interrupt throttling rate. Value is calculated 3171 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3172 */ 3173 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3174 } 3175 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value); 3176 3177 /* Use extended rx descriptor formats */ 3178 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3179 rfctl |= E1000_RFCTL_EXTEN; 3180 /* 3181 * When using MSI-X interrupts we need to throttle 3182 * using the EITR register (82574 only) 3183 */ 3184 if (hw->mac.type == e1000_82574) { 3185 for (int i = 0; i < 4; i++) 3186 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3187 DEFAULT_ITR); 3188 /* Disable accelerated acknowledge */ 3189 rfctl |= E1000_RFCTL_ACK_DIS; 3190 } 3191 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3192 3193 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3194 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3195 hw->mac.type >= e1000_82543) { 3196 if (adapter->tx_num_queues > 1) { 3197 if (hw->mac.type >= igb_mac_min) { 3198 rxcsum |= E1000_RXCSUM_PCSD; 3199 if (hw->mac.type != e1000_82575) 3200 rxcsum |= E1000_RXCSUM_CRCOFL; 3201 } else 3202 rxcsum |= E1000_RXCSUM_TUOFL | 3203 E1000_RXCSUM_IPOFL | 3204 E1000_RXCSUM_PCSD; 3205 } else { 3206 if (hw->mac.type >= igb_mac_min) 3207 rxcsum |= E1000_RXCSUM_IPPCSE; 3208 else 3209 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3210 if (hw->mac.type > e1000_82575) 3211 rxcsum |= E1000_RXCSUM_CRCOFL; 3212 } 3213 } else 3214 rxcsum &= ~E1000_RXCSUM_TUOFL; 3215 3216 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3217 3218 if (adapter->rx_num_queues > 1) { 3219 if (hw->mac.type >= igb_mac_min) 3220 igb_initialize_rss_mapping(adapter); 3221 else 3222 em_initialize_rss_mapping(adapter); 3223 } 3224 3225 /* 3226 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3227 * long latencies are observed, like Lenovo X60. This 3228 * change eliminates the problem, but since having positive 3229 * values in RDTR is a known source of problems on other 3230 * platforms another solution is being sought. 3231 */ 3232 if (hw->mac.type == e1000_82573) 3233 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3234 3235 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3236 struct rx_ring *rxr = &que->rxr; 3237 /* Setup the Base and Length of the Rx Descriptor Ring */ 3238 u64 bus_addr = rxr->rx_paddr; 3239 #if 0 3240 u32 rdt = adapter->rx_num_queues -1; /* default */ 3241 #endif 3242 3243 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3244 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3245 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3246 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3247 /* Setup the Head and Tail Descriptor Pointers */ 3248 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3249 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3250 } 3251 3252 /* 3253 * Set PTHRESH for improved jumbo performance 3254 * According to 10.2.5.11 of Intel 82574 Datasheet, 3255 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3256 * Only write to RXDCTL(1) if there is a need for different 3257 * settings. 3258 */ 3259 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3260 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3261 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3262 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3263 } else if (hw->mac.type == e1000_82574) { 3264 for (int i = 0; i < adapter->rx_num_queues; i++) { 3265 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3266 rxdctl |= 0x20; /* PTHRESH */ 3267 rxdctl |= 4 << 8; /* HTHRESH */ 3268 rxdctl |= 4 << 16;/* WTHRESH */ 3269 rxdctl |= 1 << 24; /* Switch to granularity */ 3270 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3271 } 3272 } else if (hw->mac.type >= igb_mac_min) { 3273 u32 psize, srrctl = 0; 3274 3275 if (if_getmtu(ifp) > ETHERMTU) { 3276 /* Set maximum packet len */ 3277 if (adapter->rx_mbuf_sz <= 4096) { 3278 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3279 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3280 } else if (adapter->rx_mbuf_sz > 4096) { 3281 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3282 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3283 } 3284 psize = scctx->isc_max_frame_size; 3285 /* are we on a vlan? */ 3286 if (ifp->if_vlantrunk != NULL) 3287 psize += VLAN_TAG_SIZE; 3288 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3289 } else { 3290 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3291 rctl |= E1000_RCTL_SZ_2048; 3292 } 3293 3294 /* 3295 * If TX flow control is disabled and there's >1 queue defined, 3296 * enable DROP. 3297 * 3298 * This drops frames rather than hanging the RX MAC for all queues. 3299 */ 3300 if ((adapter->rx_num_queues > 1) && 3301 (adapter->fc == e1000_fc_none || 3302 adapter->fc == e1000_fc_rx_pause)) { 3303 srrctl |= E1000_SRRCTL_DROP_EN; 3304 } 3305 /* Setup the Base and Length of the Rx Descriptor Rings */ 3306 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3307 struct rx_ring *rxr = &que->rxr; 3308 u64 bus_addr = rxr->rx_paddr; 3309 u32 rxdctl; 3310 3311 #ifdef notyet 3312 /* Configure for header split? -- ignore for now */ 3313 rxr->hdr_split = igb_header_split; 3314 #else 3315 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3316 #endif 3317 3318 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3319 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3320 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3321 (uint32_t)(bus_addr >> 32)); 3322 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3323 (uint32_t)bus_addr); 3324 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3325 /* Enable this Queue */ 3326 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3327 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3328 rxdctl &= 0xFFF00000; 3329 rxdctl |= IGB_RX_PTHRESH; 3330 rxdctl |= IGB_RX_HTHRESH << 8; 3331 rxdctl |= IGB_RX_WTHRESH << 16; 3332 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3333 } 3334 } else if (hw->mac.type >= e1000_pch2lan) { 3335 if (if_getmtu(ifp) > ETHERMTU) 3336 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3337 else 3338 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3339 } 3340 3341 /* Make sure VLAN Filters are off */ 3342 rctl &= ~E1000_RCTL_VFE; 3343 3344 if (hw->mac.type < igb_mac_min) { 3345 if (adapter->rx_mbuf_sz == MCLBYTES) 3346 rctl |= E1000_RCTL_SZ_2048; 3347 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3348 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3349 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3350 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3351 3352 /* ensure we clear use DTYPE of 00 here */ 3353 rctl &= ~0x00000C00; 3354 } 3355 3356 /* Write out the settings */ 3357 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3358 3359 return; 3360 } 3361 3362 static void 3363 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3364 { 3365 struct adapter *adapter = iflib_get_softc(ctx); 3366 u32 index, bit; 3367 3368 index = (vtag >> 5) & 0x7F; 3369 bit = vtag & 0x1F; 3370 adapter->shadow_vfta[index] |= (1 << bit); 3371 ++adapter->num_vlans; 3372 } 3373 3374 static void 3375 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3376 { 3377 struct adapter *adapter = iflib_get_softc(ctx); 3378 u32 index, bit; 3379 3380 index = (vtag >> 5) & 0x7F; 3381 bit = vtag & 0x1F; 3382 adapter->shadow_vfta[index] &= ~(1 << bit); 3383 --adapter->num_vlans; 3384 } 3385 3386 static void 3387 em_setup_vlan_hw_support(struct adapter *adapter) 3388 { 3389 struct e1000_hw *hw = &adapter->hw; 3390 u32 reg; 3391 3392 /* 3393 * We get here thru init_locked, meaning 3394 * a soft reset, this has already cleared 3395 * the VFTA and other state, so if there 3396 * have been no vlan's registered do nothing. 3397 */ 3398 if (adapter->num_vlans == 0) 3399 return; 3400 3401 /* 3402 * A soft reset zero's out the VFTA, so 3403 * we need to repopulate it now. 3404 */ 3405 for (int i = 0; i < EM_VFTA_SIZE; i++) 3406 if (adapter->shadow_vfta[i] != 0) 3407 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3408 i, adapter->shadow_vfta[i]); 3409 3410 reg = E1000_READ_REG(hw, E1000_CTRL); 3411 reg |= E1000_CTRL_VME; 3412 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3413 3414 /* Enable the Filter Table */ 3415 reg = E1000_READ_REG(hw, E1000_RCTL); 3416 reg &= ~E1000_RCTL_CFIEN; 3417 reg |= E1000_RCTL_VFE; 3418 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3419 } 3420 3421 static void 3422 em_if_intr_enable(if_ctx_t ctx) 3423 { 3424 struct adapter *adapter = iflib_get_softc(ctx); 3425 struct e1000_hw *hw = &adapter->hw; 3426 u32 ims_mask = IMS_ENABLE_MASK; 3427 3428 if (hw->mac.type == e1000_82574) { 3429 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3430 ims_mask |= adapter->ims; 3431 } 3432 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3433 } 3434 3435 static void 3436 em_if_intr_disable(if_ctx_t ctx) 3437 { 3438 struct adapter *adapter = iflib_get_softc(ctx); 3439 struct e1000_hw *hw = &adapter->hw; 3440 3441 if (hw->mac.type == e1000_82574) 3442 E1000_WRITE_REG(hw, EM_EIAC, 0); 3443 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3444 } 3445 3446 static void 3447 igb_if_intr_enable(if_ctx_t ctx) 3448 { 3449 struct adapter *adapter = iflib_get_softc(ctx); 3450 struct e1000_hw *hw = &adapter->hw; 3451 u32 mask; 3452 3453 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3454 mask = (adapter->que_mask | adapter->link_mask); 3455 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3456 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3457 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3458 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3459 } else 3460 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3461 E1000_WRITE_FLUSH(hw); 3462 } 3463 3464 static void 3465 igb_if_intr_disable(if_ctx_t ctx) 3466 { 3467 struct adapter *adapter = iflib_get_softc(ctx); 3468 struct e1000_hw *hw = &adapter->hw; 3469 3470 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3471 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3472 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3473 } 3474 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3475 E1000_WRITE_FLUSH(hw); 3476 } 3477 3478 /* 3479 * Bit of a misnomer, what this really means is 3480 * to enable OS management of the system... aka 3481 * to disable special hardware management features 3482 */ 3483 static void 3484 em_init_manageability(struct adapter *adapter) 3485 { 3486 /* A shared code workaround */ 3487 #define E1000_82542_MANC2H E1000_MANC2H 3488 if (adapter->has_manage) { 3489 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3490 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3491 3492 /* disable hardware interception of ARP */ 3493 manc &= ~(E1000_MANC_ARP_EN); 3494 3495 /* enable receiving management packets to the host */ 3496 manc |= E1000_MANC_EN_MNG2HOST; 3497 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3498 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3499 manc2h |= E1000_MNG2HOST_PORT_623; 3500 manc2h |= E1000_MNG2HOST_PORT_664; 3501 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3502 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3503 } 3504 } 3505 3506 /* 3507 * Give control back to hardware management 3508 * controller if there is one. 3509 */ 3510 static void 3511 em_release_manageability(struct adapter *adapter) 3512 { 3513 if (adapter->has_manage) { 3514 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3515 3516 /* re-enable hardware interception of ARP */ 3517 manc |= E1000_MANC_ARP_EN; 3518 manc &= ~E1000_MANC_EN_MNG2HOST; 3519 3520 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3521 } 3522 } 3523 3524 /* 3525 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3526 * For ASF and Pass Through versions of f/w this means 3527 * that the driver is loaded. For AMT version type f/w 3528 * this means that the network i/f is open. 3529 */ 3530 static void 3531 em_get_hw_control(struct adapter *adapter) 3532 { 3533 u32 ctrl_ext, swsm; 3534 3535 if (adapter->vf_ifp) 3536 return; 3537 3538 if (adapter->hw.mac.type == e1000_82573) { 3539 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3540 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3541 swsm | E1000_SWSM_DRV_LOAD); 3542 return; 3543 } 3544 /* else */ 3545 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3546 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3547 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3548 } 3549 3550 /* 3551 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3552 * For ASF and Pass Through versions of f/w this means that 3553 * the driver is no longer loaded. For AMT versions of the 3554 * f/w this means that the network i/f is closed. 3555 */ 3556 static void 3557 em_release_hw_control(struct adapter *adapter) 3558 { 3559 u32 ctrl_ext, swsm; 3560 3561 if (!adapter->has_manage) 3562 return; 3563 3564 if (adapter->hw.mac.type == e1000_82573) { 3565 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3566 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3567 swsm & ~E1000_SWSM_DRV_LOAD); 3568 return; 3569 } 3570 /* else */ 3571 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3572 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3574 return; 3575 } 3576 3577 static int 3578 em_is_valid_ether_addr(u8 *addr) 3579 { 3580 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3581 3582 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3583 return (FALSE); 3584 } 3585 3586 return (TRUE); 3587 } 3588 3589 /* 3590 ** Parse the interface capabilities with regard 3591 ** to both system management and wake-on-lan for 3592 ** later use. 3593 */ 3594 static void 3595 em_get_wakeup(if_ctx_t ctx) 3596 { 3597 struct adapter *adapter = iflib_get_softc(ctx); 3598 device_t dev = iflib_get_dev(ctx); 3599 u16 eeprom_data = 0, device_id, apme_mask; 3600 3601 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3602 apme_mask = EM_EEPROM_APME; 3603 3604 switch (adapter->hw.mac.type) { 3605 case e1000_82542: 3606 case e1000_82543: 3607 break; 3608 case e1000_82544: 3609 e1000_read_nvm(&adapter->hw, 3610 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3611 apme_mask = EM_82544_APME; 3612 break; 3613 case e1000_82546: 3614 case e1000_82546_rev_3: 3615 if (adapter->hw.bus.func == 1) { 3616 e1000_read_nvm(&adapter->hw, 3617 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3618 break; 3619 } else 3620 e1000_read_nvm(&adapter->hw, 3621 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3622 break; 3623 case e1000_82573: 3624 case e1000_82583: 3625 adapter->has_amt = TRUE; 3626 /* FALLTHROUGH */ 3627 case e1000_82571: 3628 case e1000_82572: 3629 case e1000_80003es2lan: 3630 if (adapter->hw.bus.func == 1) { 3631 e1000_read_nvm(&adapter->hw, 3632 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3633 break; 3634 } else 3635 e1000_read_nvm(&adapter->hw, 3636 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3637 break; 3638 case e1000_ich8lan: 3639 case e1000_ich9lan: 3640 case e1000_ich10lan: 3641 case e1000_pchlan: 3642 case e1000_pch2lan: 3643 case e1000_pch_lpt: 3644 case e1000_pch_spt: 3645 case e1000_82575: /* listing all igb devices */ 3646 case e1000_82576: 3647 case e1000_82580: 3648 case e1000_i350: 3649 case e1000_i354: 3650 case e1000_i210: 3651 case e1000_i211: 3652 case e1000_vfadapt: 3653 case e1000_vfadapt_i350: 3654 apme_mask = E1000_WUC_APME; 3655 adapter->has_amt = TRUE; 3656 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3657 break; 3658 default: 3659 e1000_read_nvm(&adapter->hw, 3660 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3661 break; 3662 } 3663 if (eeprom_data & apme_mask) 3664 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3665 /* 3666 * We have the eeprom settings, now apply the special cases 3667 * where the eeprom may be wrong or the board won't support 3668 * wake on lan on a particular port 3669 */ 3670 device_id = pci_get_device(dev); 3671 switch (device_id) { 3672 case E1000_DEV_ID_82546GB_PCIE: 3673 adapter->wol = 0; 3674 break; 3675 case E1000_DEV_ID_82546EB_FIBER: 3676 case E1000_DEV_ID_82546GB_FIBER: 3677 /* Wake events only supported on port A for dual fiber 3678 * regardless of eeprom setting */ 3679 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3680 E1000_STATUS_FUNC_1) 3681 adapter->wol = 0; 3682 break; 3683 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3684 /* if quad port adapter, disable WoL on all but port A */ 3685 if (global_quad_port_a != 0) 3686 adapter->wol = 0; 3687 /* Reset for multiple quad port adapters */ 3688 if (++global_quad_port_a == 4) 3689 global_quad_port_a = 0; 3690 break; 3691 case E1000_DEV_ID_82571EB_FIBER: 3692 /* Wake events only supported on port A for dual fiber 3693 * regardless of eeprom setting */ 3694 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3695 E1000_STATUS_FUNC_1) 3696 adapter->wol = 0; 3697 break; 3698 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3699 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3700 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3701 /* if quad port adapter, disable WoL on all but port A */ 3702 if (global_quad_port_a != 0) 3703 adapter->wol = 0; 3704 /* Reset for multiple quad port adapters */ 3705 if (++global_quad_port_a == 4) 3706 global_quad_port_a = 0; 3707 break; 3708 } 3709 return; 3710 } 3711 3712 3713 /* 3714 * Enable PCI Wake On Lan capability 3715 */ 3716 static void 3717 em_enable_wakeup(if_ctx_t ctx) 3718 { 3719 struct adapter *adapter = iflib_get_softc(ctx); 3720 device_t dev = iflib_get_dev(ctx); 3721 if_t ifp = iflib_get_ifp(ctx); 3722 int error = 0; 3723 u32 pmc, ctrl, ctrl_ext, rctl; 3724 u16 status; 3725 3726 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3727 return; 3728 3729 /* 3730 * Determine type of Wakeup: note that wol 3731 * is set with all bits on by default. 3732 */ 3733 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3734 adapter->wol &= ~E1000_WUFC_MAG; 3735 3736 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3737 adapter->wol &= ~E1000_WUFC_EX; 3738 3739 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3740 adapter->wol &= ~E1000_WUFC_MC; 3741 else { 3742 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3743 rctl |= E1000_RCTL_MPE; 3744 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3745 } 3746 3747 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3748 goto pme; 3749 3750 /* Advertise the wakeup capability */ 3751 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3752 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3753 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3754 3755 /* Keep the laser running on Fiber adapters */ 3756 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3757 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3758 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3759 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3760 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3761 } 3762 3763 if ((adapter->hw.mac.type == e1000_ich8lan) || 3764 (adapter->hw.mac.type == e1000_pchlan) || 3765 (adapter->hw.mac.type == e1000_ich9lan) || 3766 (adapter->hw.mac.type == e1000_ich10lan)) 3767 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3768 3769 if ( adapter->hw.mac.type >= e1000_pchlan) { 3770 error = em_enable_phy_wakeup(adapter); 3771 if (error) 3772 goto pme; 3773 } else { 3774 /* Enable wakeup by the MAC */ 3775 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3776 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3777 } 3778 3779 if (adapter->hw.phy.type == e1000_phy_igp_3) 3780 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3781 3782 pme: 3783 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3784 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3785 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3786 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3787 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3788 3789 return; 3790 } 3791 3792 /* 3793 * WOL in the newer chipset interfaces (pchlan) 3794 * require thing to be copied into the phy 3795 */ 3796 static int 3797 em_enable_phy_wakeup(struct adapter *adapter) 3798 { 3799 struct e1000_hw *hw = &adapter->hw; 3800 u32 mreg, ret = 0; 3801 u16 preg; 3802 3803 /* copy MAC RARs to PHY RARs */ 3804 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3805 3806 /* copy MAC MTA to PHY MTA */ 3807 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3808 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3809 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3810 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3811 (u16)((mreg >> 16) & 0xFFFF)); 3812 } 3813 3814 /* configure PHY Rx Control register */ 3815 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3816 mreg = E1000_READ_REG(hw, E1000_RCTL); 3817 if (mreg & E1000_RCTL_UPE) 3818 preg |= BM_RCTL_UPE; 3819 if (mreg & E1000_RCTL_MPE) 3820 preg |= BM_RCTL_MPE; 3821 preg &= ~(BM_RCTL_MO_MASK); 3822 if (mreg & E1000_RCTL_MO_3) 3823 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3824 << BM_RCTL_MO_SHIFT); 3825 if (mreg & E1000_RCTL_BAM) 3826 preg |= BM_RCTL_BAM; 3827 if (mreg & E1000_RCTL_PMCF) 3828 preg |= BM_RCTL_PMCF; 3829 mreg = E1000_READ_REG(hw, E1000_CTRL); 3830 if (mreg & E1000_CTRL_RFCE) 3831 preg |= BM_RCTL_RFCE; 3832 e1000_write_phy_reg(hw, BM_RCTL, preg); 3833 3834 /* enable PHY wakeup in MAC register */ 3835 E1000_WRITE_REG(hw, E1000_WUC, 3836 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3837 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3838 3839 /* configure and enable PHY wakeup in PHY registers */ 3840 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol); 3841 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3842 3843 /* activate PHY wakeup */ 3844 ret = hw->phy.ops.acquire(hw); 3845 if (ret) { 3846 printf("Could not acquire PHY\n"); 3847 return ret; 3848 } 3849 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3850 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3851 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3852 if (ret) { 3853 printf("Could not read PHY page 769\n"); 3854 goto out; 3855 } 3856 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3857 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3858 if (ret) 3859 printf("Could not set PHY Host Wakeup bit\n"); 3860 out: 3861 hw->phy.ops.release(hw); 3862 3863 return ret; 3864 } 3865 3866 static void 3867 em_if_led_func(if_ctx_t ctx, int onoff) 3868 { 3869 struct adapter *adapter = iflib_get_softc(ctx); 3870 3871 if (onoff) { 3872 e1000_setup_led(&adapter->hw); 3873 e1000_led_on(&adapter->hw); 3874 } else { 3875 e1000_led_off(&adapter->hw); 3876 e1000_cleanup_led(&adapter->hw); 3877 } 3878 } 3879 3880 /* 3881 * Disable the L0S and L1 LINK states 3882 */ 3883 static void 3884 em_disable_aspm(struct adapter *adapter) 3885 { 3886 int base, reg; 3887 u16 link_cap,link_ctrl; 3888 device_t dev = adapter->dev; 3889 3890 switch (adapter->hw.mac.type) { 3891 case e1000_82573: 3892 case e1000_82574: 3893 case e1000_82583: 3894 break; 3895 default: 3896 return; 3897 } 3898 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3899 return; 3900 reg = base + PCIER_LINK_CAP; 3901 link_cap = pci_read_config(dev, reg, 2); 3902 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3903 return; 3904 reg = base + PCIER_LINK_CTL; 3905 link_ctrl = pci_read_config(dev, reg, 2); 3906 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3907 pci_write_config(dev, reg, link_ctrl, 2); 3908 return; 3909 } 3910 3911 /********************************************************************** 3912 * 3913 * Update the board statistics counters. 3914 * 3915 **********************************************************************/ 3916 static void 3917 em_update_stats_counters(struct adapter *adapter) 3918 { 3919 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3920 3921 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3922 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3923 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3924 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3925 } 3926 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3927 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3928 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3929 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3930 3931 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3932 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3933 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3934 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3935 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3936 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3937 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3938 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3939 /* 3940 ** For watchdog management we need to know if we have been 3941 ** paused during the last interval, so capture that here. 3942 */ 3943 if (adapter->stats.xoffrxc != prev_xoffrxc) 3944 adapter->shared->isc_pause_frames = 1; 3945 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3946 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3947 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3948 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3949 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3950 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3951 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3952 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3953 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3954 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3955 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3956 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3957 3958 /* For the 64-bit byte counters the low dword must be read first. */ 3959 /* Both registers clear on the read of the high dword */ 3960 3961 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3962 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3963 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3964 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3965 3966 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3967 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3968 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3969 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3970 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3971 3972 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3973 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3974 3975 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3976 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3977 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3978 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3979 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3980 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3981 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3982 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3983 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3984 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3985 3986 /* Interrupt Counts */ 3987 3988 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3989 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3990 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3991 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3992 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3993 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3994 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3995 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3996 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3997 3998 if (adapter->hw.mac.type >= e1000_82543) { 3999 adapter->stats.algnerrc += 4000 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4001 adapter->stats.rxerrc += 4002 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4003 adapter->stats.tncrs += 4004 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4005 adapter->stats.cexterr += 4006 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4007 adapter->stats.tsctc += 4008 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4009 adapter->stats.tsctfc += 4010 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4011 } 4012 } 4013 4014 static uint64_t 4015 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4016 { 4017 struct adapter *adapter = iflib_get_softc(ctx); 4018 struct ifnet *ifp = iflib_get_ifp(ctx); 4019 4020 switch (cnt) { 4021 case IFCOUNTER_COLLISIONS: 4022 return (adapter->stats.colc); 4023 case IFCOUNTER_IERRORS: 4024 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4025 adapter->stats.crcerrs + adapter->stats.algnerrc + 4026 adapter->stats.ruc + adapter->stats.roc + 4027 adapter->stats.mpc + adapter->stats.cexterr); 4028 case IFCOUNTER_OERRORS: 4029 return (adapter->stats.ecol + adapter->stats.latecol + 4030 adapter->watchdog_events); 4031 default: 4032 return (if_get_counter_default(ifp, cnt)); 4033 } 4034 } 4035 4036 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4037 * @ctx: iflib context 4038 * @event: event code to check 4039 * 4040 * Defaults to returning true for unknown events. 4041 * 4042 * @returns true if iflib needs to reinit the interface 4043 */ 4044 static bool 4045 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4046 { 4047 switch (event) { 4048 case IFLIB_RESTART_VLAN_CONFIG: 4049 default: 4050 return (true); 4051 } 4052 } 4053 4054 /* Export a single 32-bit register via a read-only sysctl. */ 4055 static int 4056 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4057 { 4058 struct adapter *adapter; 4059 u_int val; 4060 4061 adapter = oidp->oid_arg1; 4062 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4063 return (sysctl_handle_int(oidp, &val, 0, req)); 4064 } 4065 4066 /* 4067 * Add sysctl variables, one per statistic, to the system. 4068 */ 4069 static void 4070 em_add_hw_stats(struct adapter *adapter) 4071 { 4072 device_t dev = iflib_get_dev(adapter->ctx); 4073 struct em_tx_queue *tx_que = adapter->tx_queues; 4074 struct em_rx_queue *rx_que = adapter->rx_queues; 4075 4076 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4077 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4078 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4079 struct e1000_hw_stats *stats = &adapter->stats; 4080 4081 struct sysctl_oid *stat_node, *queue_node, *int_node; 4082 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4083 4084 #define QUEUE_NAME_LEN 32 4085 char namebuf[QUEUE_NAME_LEN]; 4086 4087 /* Driver Statistics */ 4088 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4089 CTLFLAG_RD, &adapter->dropped_pkts, 4090 "Driver dropped packets"); 4091 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4092 CTLFLAG_RD, &adapter->link_irq, 4093 "Link MSI-X IRQ Handled"); 4094 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4095 CTLFLAG_RD, &adapter->rx_overruns, 4096 "RX overruns"); 4097 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4098 CTLFLAG_RD, &adapter->watchdog_events, 4099 "Watchdog timeouts"); 4100 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4101 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4102 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4103 "Device Control Register"); 4104 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4105 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4106 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4107 "Receiver Control Register"); 4108 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4109 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4110 "Flow Control High Watermark"); 4111 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4112 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4113 "Flow Control Low Watermark"); 4114 4115 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4116 struct tx_ring *txr = &tx_que->txr; 4117 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4118 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4119 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4120 queue_list = SYSCTL_CHILDREN(queue_node); 4121 4122 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4123 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4124 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4125 "Transmit Descriptor Head"); 4126 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4127 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4128 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4129 "Transmit Descriptor Tail"); 4130 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4131 CTLFLAG_RD, &txr->tx_irq, 4132 "Queue MSI-X Transmit Interrupts"); 4133 } 4134 4135 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4136 struct rx_ring *rxr = &rx_que->rxr; 4137 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4138 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4139 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4140 queue_list = SYSCTL_CHILDREN(queue_node); 4141 4142 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4143 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4144 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4145 "Receive Descriptor Head"); 4146 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4147 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4148 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4149 "Receive Descriptor Tail"); 4150 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4151 CTLFLAG_RD, &rxr->rx_irq, 4152 "Queue MSI-X Receive Interrupts"); 4153 } 4154 4155 /* MAC stats get their own sub node */ 4156 4157 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4158 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4159 stat_list = SYSCTL_CHILDREN(stat_node); 4160 4161 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4162 CTLFLAG_RD, &stats->ecol, 4163 "Excessive collisions"); 4164 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4165 CTLFLAG_RD, &stats->scc, 4166 "Single collisions"); 4167 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4168 CTLFLAG_RD, &stats->mcc, 4169 "Multiple collisions"); 4170 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4171 CTLFLAG_RD, &stats->latecol, 4172 "Late collisions"); 4173 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4174 CTLFLAG_RD, &stats->colc, 4175 "Collision Count"); 4176 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4177 CTLFLAG_RD, &adapter->stats.symerrs, 4178 "Symbol Errors"); 4179 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4180 CTLFLAG_RD, &adapter->stats.sec, 4181 "Sequence Errors"); 4182 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4183 CTLFLAG_RD, &adapter->stats.dc, 4184 "Defer Count"); 4185 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4186 CTLFLAG_RD, &adapter->stats.mpc, 4187 "Missed Packets"); 4188 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4189 CTLFLAG_RD, &adapter->stats.rnbc, 4190 "Receive No Buffers"); 4191 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4192 CTLFLAG_RD, &adapter->stats.ruc, 4193 "Receive Undersize"); 4194 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4195 CTLFLAG_RD, &adapter->stats.rfc, 4196 "Fragmented Packets Received "); 4197 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4198 CTLFLAG_RD, &adapter->stats.roc, 4199 "Oversized Packets Received"); 4200 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4201 CTLFLAG_RD, &adapter->stats.rjc, 4202 "Recevied Jabber"); 4203 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4204 CTLFLAG_RD, &adapter->stats.rxerrc, 4205 "Receive Errors"); 4206 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4207 CTLFLAG_RD, &adapter->stats.crcerrs, 4208 "CRC errors"); 4209 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4210 CTLFLAG_RD, &adapter->stats.algnerrc, 4211 "Alignment Errors"); 4212 /* On 82575 these are collision counts */ 4213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4214 CTLFLAG_RD, &adapter->stats.cexterr, 4215 "Collision/Carrier extension errors"); 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4217 CTLFLAG_RD, &adapter->stats.xonrxc, 4218 "XON Received"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4220 CTLFLAG_RD, &adapter->stats.xontxc, 4221 "XON Transmitted"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4223 CTLFLAG_RD, &adapter->stats.xoffrxc, 4224 "XOFF Received"); 4225 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4226 CTLFLAG_RD, &adapter->stats.xofftxc, 4227 "XOFF Transmitted"); 4228 4229 /* Packet Reception Stats */ 4230 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4231 CTLFLAG_RD, &adapter->stats.tpr, 4232 "Total Packets Received "); 4233 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4234 CTLFLAG_RD, &adapter->stats.gprc, 4235 "Good Packets Received"); 4236 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4237 CTLFLAG_RD, &adapter->stats.bprc, 4238 "Broadcast Packets Received"); 4239 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4240 CTLFLAG_RD, &adapter->stats.mprc, 4241 "Multicast Packets Received"); 4242 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4243 CTLFLAG_RD, &adapter->stats.prc64, 4244 "64 byte frames received "); 4245 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4246 CTLFLAG_RD, &adapter->stats.prc127, 4247 "65-127 byte frames received"); 4248 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4249 CTLFLAG_RD, &adapter->stats.prc255, 4250 "128-255 byte frames received"); 4251 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4252 CTLFLAG_RD, &adapter->stats.prc511, 4253 "256-511 byte frames received"); 4254 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4255 CTLFLAG_RD, &adapter->stats.prc1023, 4256 "512-1023 byte frames received"); 4257 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4258 CTLFLAG_RD, &adapter->stats.prc1522, 4259 "1023-1522 byte frames received"); 4260 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4261 CTLFLAG_RD, &adapter->stats.gorc, 4262 "Good Octets Received"); 4263 4264 /* Packet Transmission Stats */ 4265 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4266 CTLFLAG_RD, &adapter->stats.gotc, 4267 "Good Octets Transmitted"); 4268 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4269 CTLFLAG_RD, &adapter->stats.tpt, 4270 "Total Packets Transmitted"); 4271 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4272 CTLFLAG_RD, &adapter->stats.gptc, 4273 "Good Packets Transmitted"); 4274 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4275 CTLFLAG_RD, &adapter->stats.bptc, 4276 "Broadcast Packets Transmitted"); 4277 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4278 CTLFLAG_RD, &adapter->stats.mptc, 4279 "Multicast Packets Transmitted"); 4280 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4281 CTLFLAG_RD, &adapter->stats.ptc64, 4282 "64 byte frames transmitted "); 4283 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4284 CTLFLAG_RD, &adapter->stats.ptc127, 4285 "65-127 byte frames transmitted"); 4286 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4287 CTLFLAG_RD, &adapter->stats.ptc255, 4288 "128-255 byte frames transmitted"); 4289 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4290 CTLFLAG_RD, &adapter->stats.ptc511, 4291 "256-511 byte frames transmitted"); 4292 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4293 CTLFLAG_RD, &adapter->stats.ptc1023, 4294 "512-1023 byte frames transmitted"); 4295 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4296 CTLFLAG_RD, &adapter->stats.ptc1522, 4297 "1024-1522 byte frames transmitted"); 4298 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4299 CTLFLAG_RD, &adapter->stats.tsctc, 4300 "TSO Contexts Transmitted"); 4301 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4302 CTLFLAG_RD, &adapter->stats.tsctfc, 4303 "TSO Contexts Failed"); 4304 4305 4306 /* Interrupt Stats */ 4307 4308 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4309 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4310 int_list = SYSCTL_CHILDREN(int_node); 4311 4312 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4313 CTLFLAG_RD, &adapter->stats.iac, 4314 "Interrupt Assertion Count"); 4315 4316 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4317 CTLFLAG_RD, &adapter->stats.icrxptc, 4318 "Interrupt Cause Rx Pkt Timer Expire Count"); 4319 4320 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4321 CTLFLAG_RD, &adapter->stats.icrxatc, 4322 "Interrupt Cause Rx Abs Timer Expire Count"); 4323 4324 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4325 CTLFLAG_RD, &adapter->stats.ictxptc, 4326 "Interrupt Cause Tx Pkt Timer Expire Count"); 4327 4328 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4329 CTLFLAG_RD, &adapter->stats.ictxatc, 4330 "Interrupt Cause Tx Abs Timer Expire Count"); 4331 4332 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4333 CTLFLAG_RD, &adapter->stats.ictxqec, 4334 "Interrupt Cause Tx Queue Empty Count"); 4335 4336 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4337 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4338 "Interrupt Cause Tx Queue Min Thresh Count"); 4339 4340 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4341 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4342 "Interrupt Cause Rx Desc Min Thresh Count"); 4343 4344 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4345 CTLFLAG_RD, &adapter->stats.icrxoc, 4346 "Interrupt Cause Receiver Overrun Count"); 4347 } 4348 4349 /********************************************************************** 4350 * 4351 * This routine provides a way to dump out the adapter eeprom, 4352 * often a useful debug/service tool. This only dumps the first 4353 * 32 words, stuff that matters is in that extent. 4354 * 4355 **********************************************************************/ 4356 static int 4357 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4358 { 4359 struct adapter *adapter = (struct adapter *)arg1; 4360 int error; 4361 int result; 4362 4363 result = -1; 4364 error = sysctl_handle_int(oidp, &result, 0, req); 4365 4366 if (error || !req->newptr) 4367 return (error); 4368 4369 /* 4370 * This value will cause a hex dump of the 4371 * first 32 16-bit words of the EEPROM to 4372 * the screen. 4373 */ 4374 if (result == 1) 4375 em_print_nvm_info(adapter); 4376 4377 return (error); 4378 } 4379 4380 static void 4381 em_print_nvm_info(struct adapter *adapter) 4382 { 4383 u16 eeprom_data; 4384 int i, j, row = 0; 4385 4386 /* Its a bit crude, but it gets the job done */ 4387 printf("\nInterface EEPROM Dump:\n"); 4388 printf("Offset\n0x0000 "); 4389 for (i = 0, j = 0; i < 32; i++, j++) { 4390 if (j == 8) { /* Make the offset block */ 4391 j = 0; ++row; 4392 printf("\n0x00%x0 ",row); 4393 } 4394 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4395 printf("%04x ", eeprom_data); 4396 } 4397 printf("\n"); 4398 } 4399 4400 static int 4401 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4402 { 4403 struct em_int_delay_info *info; 4404 struct adapter *adapter; 4405 u32 regval; 4406 int error, usecs, ticks; 4407 4408 info = (struct em_int_delay_info *) arg1; 4409 usecs = info->value; 4410 error = sysctl_handle_int(oidp, &usecs, 0, req); 4411 if (error != 0 || req->newptr == NULL) 4412 return (error); 4413 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4414 return (EINVAL); 4415 info->value = usecs; 4416 ticks = EM_USECS_TO_TICKS(usecs); 4417 if (info->offset == E1000_ITR) /* units are 256ns here */ 4418 ticks *= 4; 4419 4420 adapter = info->adapter; 4421 4422 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4423 regval = (regval & ~0xffff) | (ticks & 0xffff); 4424 /* Handle a few special cases. */ 4425 switch (info->offset) { 4426 case E1000_RDTR: 4427 break; 4428 case E1000_TIDV: 4429 if (ticks == 0) { 4430 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4431 /* Don't write 0 into the TIDV register. */ 4432 regval++; 4433 } else 4434 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4435 break; 4436 } 4437 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4438 return (0); 4439 } 4440 4441 static void 4442 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4443 const char *description, struct em_int_delay_info *info, 4444 int offset, int value) 4445 { 4446 info->adapter = adapter; 4447 info->offset = offset; 4448 info->value = value; 4449 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4450 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4451 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4452 info, 0, em_sysctl_int_delay, "I", description); 4453 } 4454 4455 /* 4456 * Set flow control using sysctl: 4457 * Flow control values: 4458 * 0 - off 4459 * 1 - rx pause 4460 * 2 - tx pause 4461 * 3 - full 4462 */ 4463 static int 4464 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4465 { 4466 int error; 4467 static int input = 3; /* default is full */ 4468 struct adapter *adapter = (struct adapter *) arg1; 4469 4470 error = sysctl_handle_int(oidp, &input, 0, req); 4471 4472 if ((error) || (req->newptr == NULL)) 4473 return (error); 4474 4475 if (input == adapter->fc) /* no change? */ 4476 return (error); 4477 4478 switch (input) { 4479 case e1000_fc_rx_pause: 4480 case e1000_fc_tx_pause: 4481 case e1000_fc_full: 4482 case e1000_fc_none: 4483 adapter->hw.fc.requested_mode = input; 4484 adapter->fc = input; 4485 break; 4486 default: 4487 /* Do nothing */ 4488 return (error); 4489 } 4490 4491 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4492 e1000_force_mac_fc(&adapter->hw); 4493 return (error); 4494 } 4495 4496 /* 4497 * Manage Energy Efficient Ethernet: 4498 * Control values: 4499 * 0/1 - enabled/disabled 4500 */ 4501 static int 4502 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4503 { 4504 struct adapter *adapter = (struct adapter *) arg1; 4505 int error, value; 4506 4507 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4508 error = sysctl_handle_int(oidp, &value, 0, req); 4509 if (error || req->newptr == NULL) 4510 return (error); 4511 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4512 em_if_init(adapter->ctx); 4513 4514 return (0); 4515 } 4516 4517 static int 4518 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4519 { 4520 struct adapter *adapter; 4521 int error; 4522 int result; 4523 4524 result = -1; 4525 error = sysctl_handle_int(oidp, &result, 0, req); 4526 4527 if (error || !req->newptr) 4528 return (error); 4529 4530 if (result == 1) { 4531 adapter = (struct adapter *) arg1; 4532 em_print_debug_info(adapter); 4533 } 4534 4535 return (error); 4536 } 4537 4538 static int 4539 em_get_rs(SYSCTL_HANDLER_ARGS) 4540 { 4541 struct adapter *adapter = (struct adapter *) arg1; 4542 int error; 4543 int result; 4544 4545 result = 0; 4546 error = sysctl_handle_int(oidp, &result, 0, req); 4547 4548 if (error || !req->newptr || result != 1) 4549 return (error); 4550 em_dump_rs(adapter); 4551 4552 return (error); 4553 } 4554 4555 static void 4556 em_if_debug(if_ctx_t ctx) 4557 { 4558 em_dump_rs(iflib_get_softc(ctx)); 4559 } 4560 4561 /* 4562 * This routine is meant to be fluid, add whatever is 4563 * needed for debugging a problem. -jfv 4564 */ 4565 static void 4566 em_print_debug_info(struct adapter *adapter) 4567 { 4568 device_t dev = iflib_get_dev(adapter->ctx); 4569 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4570 struct tx_ring *txr = &adapter->tx_queues->txr; 4571 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4572 4573 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4574 printf("Interface is RUNNING "); 4575 else 4576 printf("Interface is NOT RUNNING\n"); 4577 4578 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4579 printf("and INACTIVE\n"); 4580 else 4581 printf("and ACTIVE\n"); 4582 4583 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4584 device_printf(dev, "TX Queue %d ------\n", i); 4585 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4586 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4587 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4588 4589 } 4590 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4591 device_printf(dev, "RX Queue %d ------\n", j); 4592 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4593 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4594 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4595 } 4596 } 4597 4598 /* 4599 * 82574 only: 4600 * Write a new value to the EEPROM increasing the number of MSI-X 4601 * vectors from 3 to 5, for proper multiqueue support. 4602 */ 4603 static void 4604 em_enable_vectors_82574(if_ctx_t ctx) 4605 { 4606 struct adapter *adapter = iflib_get_softc(ctx); 4607 struct e1000_hw *hw = &adapter->hw; 4608 device_t dev = iflib_get_dev(ctx); 4609 u16 edata; 4610 4611 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4612 if (bootverbose) 4613 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4614 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4615 device_printf(dev, "Writing to eeprom: increasing " 4616 "reported MSI-X vectors from 3 to 5...\n"); 4617 edata &= ~(EM_NVM_MSIX_N_MASK); 4618 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4619 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4620 e1000_update_nvm_checksum(hw); 4621 device_printf(dev, "Writing to eeprom: done\n"); 4622 } 4623 } 4624