1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) PRO/1000 Network Connection"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) PRO/1000 Network Connection"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) PRO/1000 Network Connection"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) PRO/1000 Network Connection"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) PRO/1000 Network Connection"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) PRO/1000 Network Connection"), 183 /* required last entry */ 184 PVID_END 185 }; 186 187 static pci_vendor_info_t igb_vendor_info_array[] = 188 { 189 /* Intel(R) PRO/1000 Network Connection - igb */ 190 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 224 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 225 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 226 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 227 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 228 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 229 /* required last entry */ 230 PVID_END 231 }; 232 233 /********************************************************************* 234 * Function prototypes 235 *********************************************************************/ 236 static void *em_register(device_t dev); 237 static void *igb_register(device_t dev); 238 static int em_if_attach_pre(if_ctx_t ctx); 239 static int em_if_attach_post(if_ctx_t ctx); 240 static int em_if_detach(if_ctx_t ctx); 241 static int em_if_shutdown(if_ctx_t ctx); 242 static int em_if_suspend(if_ctx_t ctx); 243 static int em_if_resume(if_ctx_t ctx); 244 245 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 246 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 247 static void em_if_queues_free(if_ctx_t ctx); 248 249 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 250 static void em_if_init(if_ctx_t ctx); 251 static void em_if_stop(if_ctx_t ctx); 252 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 253 static int em_if_media_change(if_ctx_t ctx); 254 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 255 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 256 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 257 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 258 static void em_if_watchdog_reset(if_ctx_t ctx); 259 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 260 261 static void em_identify_hardware(if_ctx_t ctx); 262 static int em_allocate_pci_resources(if_ctx_t ctx); 263 static void em_free_pci_resources(if_ctx_t ctx); 264 static void em_reset(if_ctx_t ctx); 265 static int em_setup_interface(if_ctx_t ctx); 266 static int em_setup_msix(if_ctx_t ctx); 267 268 static void em_initialize_transmit_unit(if_ctx_t ctx); 269 static void em_initialize_receive_unit(if_ctx_t ctx); 270 271 static void em_if_intr_enable(if_ctx_t ctx); 272 static void em_if_intr_disable(if_ctx_t ctx); 273 static void igb_if_intr_enable(if_ctx_t ctx); 274 static void igb_if_intr_disable(if_ctx_t ctx); 275 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 276 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 277 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 278 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 279 static void em_if_multi_set(if_ctx_t ctx); 280 static void em_if_update_admin_status(if_ctx_t ctx); 281 static void em_if_debug(if_ctx_t ctx); 282 static void em_update_stats_counters(struct adapter *); 283 static void em_add_hw_stats(struct adapter *adapter); 284 static int em_if_set_promisc(if_ctx_t ctx, int flags); 285 static void em_setup_vlan_hw_support(struct adapter *); 286 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 287 static void em_print_nvm_info(struct adapter *); 288 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 289 static int em_get_rs(SYSCTL_HANDLER_ARGS); 290 static void em_print_debug_info(struct adapter *); 291 static int em_is_valid_ether_addr(u8 *); 292 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 293 static void em_add_int_delay_sysctl(struct adapter *, const char *, 294 const char *, struct em_int_delay_info *, int, int); 295 /* Management and WOL Support */ 296 static void em_init_manageability(struct adapter *); 297 static void em_release_manageability(struct adapter *); 298 static void em_get_hw_control(struct adapter *); 299 static void em_release_hw_control(struct adapter *); 300 static void em_get_wakeup(if_ctx_t ctx); 301 static void em_enable_wakeup(if_ctx_t ctx); 302 static int em_enable_phy_wakeup(struct adapter *); 303 static void em_disable_aspm(struct adapter *); 304 305 int em_intr(void *arg); 306 static void em_disable_promisc(if_ctx_t ctx); 307 308 /* MSI-X handlers */ 309 static int em_if_msix_intr_assign(if_ctx_t, int); 310 static int em_msix_link(void *); 311 static void em_handle_link(void *context); 312 313 static void em_enable_vectors_82574(if_ctx_t); 314 315 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 316 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 317 static void em_if_led_func(if_ctx_t ctx, int onoff); 318 319 static int em_get_regs(SYSCTL_HANDLER_ARGS); 320 321 static void lem_smartspeed(struct adapter *adapter); 322 static void igb_configure_queues(struct adapter *adapter); 323 324 325 /********************************************************************* 326 * FreeBSD Device Interface Entry Points 327 *********************************************************************/ 328 static device_method_t em_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, em_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 static device_method_t igb_methods[] = { 341 /* Device interface */ 342 DEVMETHOD(device_register, igb_register), 343 DEVMETHOD(device_probe, iflib_device_probe), 344 DEVMETHOD(device_attach, iflib_device_attach), 345 DEVMETHOD(device_detach, iflib_device_detach), 346 DEVMETHOD(device_shutdown, iflib_device_shutdown), 347 DEVMETHOD(device_suspend, iflib_device_suspend), 348 DEVMETHOD(device_resume, iflib_device_resume), 349 DEVMETHOD_END 350 }; 351 352 353 static driver_t em_driver = { 354 "em", em_methods, sizeof(struct adapter), 355 }; 356 357 static devclass_t em_devclass; 358 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 359 360 MODULE_DEPEND(em, pci, 1, 1, 1); 361 MODULE_DEPEND(em, ether, 1, 1, 1); 362 MODULE_DEPEND(em, iflib, 1, 1, 1); 363 364 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 365 366 static driver_t igb_driver = { 367 "igb", igb_methods, sizeof(struct adapter), 368 }; 369 370 static devclass_t igb_devclass; 371 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 372 373 MODULE_DEPEND(igb, pci, 1, 1, 1); 374 MODULE_DEPEND(igb, ether, 1, 1, 1); 375 MODULE_DEPEND(igb, iflib, 1, 1, 1); 376 377 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 378 379 static device_method_t em_if_methods[] = { 380 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 381 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 382 DEVMETHOD(ifdi_detach, em_if_detach), 383 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 384 DEVMETHOD(ifdi_suspend, em_if_suspend), 385 DEVMETHOD(ifdi_resume, em_if_resume), 386 DEVMETHOD(ifdi_init, em_if_init), 387 DEVMETHOD(ifdi_stop, em_if_stop), 388 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 389 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 390 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 391 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 392 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 393 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 394 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 395 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 396 DEVMETHOD(ifdi_media_status, em_if_media_status), 397 DEVMETHOD(ifdi_media_change, em_if_media_change), 398 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 399 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 400 DEVMETHOD(ifdi_timer, em_if_timer), 401 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 402 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 403 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 404 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 405 DEVMETHOD(ifdi_led_func, em_if_led_func), 406 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 407 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 408 DEVMETHOD(ifdi_debug, em_if_debug), 409 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 410 DEVMETHOD_END 411 }; 412 413 static driver_t em_if_driver = { 414 "em_if", em_if_methods, sizeof(struct adapter) 415 }; 416 417 static device_method_t igb_if_methods[] = { 418 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 419 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 420 DEVMETHOD(ifdi_detach, em_if_detach), 421 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 422 DEVMETHOD(ifdi_suspend, em_if_suspend), 423 DEVMETHOD(ifdi_resume, em_if_resume), 424 DEVMETHOD(ifdi_init, em_if_init), 425 DEVMETHOD(ifdi_stop, em_if_stop), 426 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 427 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 428 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 429 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 430 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 431 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 432 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 433 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 434 DEVMETHOD(ifdi_media_status, em_if_media_status), 435 DEVMETHOD(ifdi_media_change, em_if_media_change), 436 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 437 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 438 DEVMETHOD(ifdi_timer, em_if_timer), 439 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 440 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 441 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 442 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 443 DEVMETHOD(ifdi_led_func, em_if_led_func), 444 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 445 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 446 DEVMETHOD(ifdi_debug, em_if_debug), 447 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 448 DEVMETHOD_END 449 }; 450 451 static driver_t igb_if_driver = { 452 "igb_if", igb_if_methods, sizeof(struct adapter) 453 }; 454 455 /********************************************************************* 456 * Tunable default values. 457 *********************************************************************/ 458 459 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 460 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 461 462 #define MAX_INTS_PER_SEC 8000 463 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 464 465 /* Allow common code without TSO */ 466 #ifndef CSUM_TSO 467 #define CSUM_TSO 0 468 #endif 469 470 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 471 "EM driver parameters"); 472 473 static int em_disable_crc_stripping = 0; 474 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 475 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 476 477 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 478 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 479 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 480 0, "Default transmit interrupt delay in usecs"); 481 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 482 0, "Default receive interrupt delay in usecs"); 483 484 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 485 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 486 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 487 &em_tx_abs_int_delay_dflt, 0, 488 "Default transmit interrupt delay limit in usecs"); 489 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 490 &em_rx_abs_int_delay_dflt, 0, 491 "Default receive interrupt delay limit in usecs"); 492 493 static int em_smart_pwr_down = FALSE; 494 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 495 0, "Set to true to leave smart power down enabled on newer adapters"); 496 497 /* Controls whether promiscuous also shows bad packets */ 498 static int em_debug_sbp = TRUE; 499 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 500 "Show bad packets in promiscuous mode"); 501 502 /* How many packets rxeof tries to clean at a time */ 503 static int em_rx_process_limit = 100; 504 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 505 &em_rx_process_limit, 0, 506 "Maximum number of received packets to process " 507 "at a time, -1 means unlimited"); 508 509 /* Energy efficient ethernet - default to OFF */ 510 static int eee_setting = 1; 511 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 512 "Enable Energy Efficient Ethernet"); 513 514 /* 515 ** Tuneable Interrupt rate 516 */ 517 static int em_max_interrupt_rate = 8000; 518 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 519 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 520 521 522 523 /* Global used in WOL setup with multiport cards */ 524 static int global_quad_port_a = 0; 525 526 extern struct if_txrx igb_txrx; 527 extern struct if_txrx em_txrx; 528 extern struct if_txrx lem_txrx; 529 530 static struct if_shared_ctx em_sctx_init = { 531 .isc_magic = IFLIB_MAGIC, 532 .isc_q_align = PAGE_SIZE, 533 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 534 .isc_tx_maxsegsize = PAGE_SIZE, 535 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 536 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 537 .isc_rx_maxsize = MJUM9BYTES, 538 .isc_rx_nsegments = 1, 539 .isc_rx_maxsegsize = MJUM9BYTES, 540 .isc_nfl = 1, 541 .isc_nrxqs = 1, 542 .isc_ntxqs = 1, 543 .isc_admin_intrcnt = 1, 544 .isc_vendor_info = em_vendor_info_array, 545 .isc_driver_version = em_driver_version, 546 .isc_driver = &em_if_driver, 547 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 548 549 .isc_nrxd_min = {EM_MIN_RXD}, 550 .isc_ntxd_min = {EM_MIN_TXD}, 551 .isc_nrxd_max = {EM_MAX_RXD}, 552 .isc_ntxd_max = {EM_MAX_TXD}, 553 .isc_nrxd_default = {EM_DEFAULT_RXD}, 554 .isc_ntxd_default = {EM_DEFAULT_TXD}, 555 }; 556 557 if_shared_ctx_t em_sctx = &em_sctx_init; 558 559 static struct if_shared_ctx igb_sctx_init = { 560 .isc_magic = IFLIB_MAGIC, 561 .isc_q_align = PAGE_SIZE, 562 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 563 .isc_tx_maxsegsize = PAGE_SIZE, 564 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 565 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 566 .isc_rx_maxsize = MJUM9BYTES, 567 .isc_rx_nsegments = 1, 568 .isc_rx_maxsegsize = MJUM9BYTES, 569 .isc_nfl = 1, 570 .isc_nrxqs = 1, 571 .isc_ntxqs = 1, 572 .isc_admin_intrcnt = 1, 573 .isc_vendor_info = igb_vendor_info_array, 574 .isc_driver_version = em_driver_version, 575 .isc_driver = &igb_if_driver, 576 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 577 578 .isc_nrxd_min = {EM_MIN_RXD}, 579 .isc_ntxd_min = {EM_MIN_TXD}, 580 .isc_nrxd_max = {IGB_MAX_RXD}, 581 .isc_ntxd_max = {IGB_MAX_TXD}, 582 .isc_nrxd_default = {EM_DEFAULT_RXD}, 583 .isc_ntxd_default = {EM_DEFAULT_TXD}, 584 }; 585 586 if_shared_ctx_t igb_sctx = &igb_sctx_init; 587 588 /***************************************************************** 589 * 590 * Dump Registers 591 * 592 ****************************************************************/ 593 #define IGB_REGS_LEN 739 594 595 static int em_get_regs(SYSCTL_HANDLER_ARGS) 596 { 597 struct adapter *adapter = (struct adapter *)arg1; 598 struct e1000_hw *hw = &adapter->hw; 599 struct sbuf *sb; 600 u32 *regs_buff; 601 int rc; 602 603 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 604 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 605 606 rc = sysctl_wire_old_buffer(req, 0); 607 MPASS(rc == 0); 608 if (rc != 0) { 609 free(regs_buff, M_DEVBUF); 610 return (rc); 611 } 612 613 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 614 MPASS(sb != NULL); 615 if (sb == NULL) { 616 free(regs_buff, M_DEVBUF); 617 return (ENOMEM); 618 } 619 620 /* General Registers */ 621 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 622 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 623 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 624 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 625 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 626 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 627 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 628 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 629 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 630 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 631 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 632 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 633 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 634 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 635 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 636 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 637 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 638 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 639 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 640 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 641 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 642 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 643 644 sbuf_printf(sb, "General Registers\n"); 645 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 646 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 647 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 648 649 sbuf_printf(sb, "Interrupt Registers\n"); 650 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 651 652 sbuf_printf(sb, "RX Registers\n"); 653 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 654 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 655 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 656 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 657 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 658 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 659 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 660 661 sbuf_printf(sb, "TX Registers\n"); 662 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 663 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 664 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 665 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 666 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 667 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 668 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 669 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 670 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 671 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 672 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 673 674 free(regs_buff, M_DEVBUF); 675 676 #ifdef DUMP_DESCS 677 { 678 if_softc_ctx_t scctx = adapter->shared; 679 struct rx_ring *rxr = &rx_que->rxr; 680 struct tx_ring *txr = &tx_que->txr; 681 int ntxd = scctx->isc_ntxd[0]; 682 int nrxd = scctx->isc_nrxd[0]; 683 int j; 684 685 for (j = 0; j < nrxd; j++) { 686 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 687 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 688 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 689 } 690 691 for (j = 0; j < min(ntxd, 256); j++) { 692 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 693 694 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 695 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 696 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 697 698 } 699 } 700 #endif 701 702 rc = sbuf_finish(sb); 703 sbuf_delete(sb); 704 return(rc); 705 } 706 707 static void * 708 em_register(device_t dev) 709 { 710 return (em_sctx); 711 } 712 713 static void * 714 igb_register(device_t dev) 715 { 716 return (igb_sctx); 717 } 718 719 static int 720 em_set_num_queues(if_ctx_t ctx) 721 { 722 struct adapter *adapter = iflib_get_softc(ctx); 723 int maxqueues; 724 725 /* Sanity check based on HW */ 726 switch (adapter->hw.mac.type) { 727 case e1000_82576: 728 case e1000_82580: 729 case e1000_i350: 730 case e1000_i354: 731 maxqueues = 8; 732 break; 733 case e1000_i210: 734 case e1000_82575: 735 maxqueues = 4; 736 break; 737 case e1000_i211: 738 case e1000_82574: 739 maxqueues = 2; 740 break; 741 default: 742 maxqueues = 1; 743 break; 744 } 745 746 return (maxqueues); 747 } 748 749 #define LEM_CAPS \ 750 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 751 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 752 753 #define EM_CAPS \ 754 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 755 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 756 IFCAP_LRO | IFCAP_VLAN_HWTSO 757 758 #define IGB_CAPS \ 759 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 760 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 761 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 762 IFCAP_TSO6 763 764 /********************************************************************* 765 * Device initialization routine 766 * 767 * The attach entry point is called when the driver is being loaded. 768 * This routine identifies the type of hardware, allocates all resources 769 * and initializes the hardware. 770 * 771 * return 0 on success, positive on failure 772 *********************************************************************/ 773 static int 774 em_if_attach_pre(if_ctx_t ctx) 775 { 776 struct adapter *adapter; 777 if_softc_ctx_t scctx; 778 device_t dev; 779 struct e1000_hw *hw; 780 int error = 0; 781 782 INIT_DEBUGOUT("em_if_attach_pre: begin"); 783 dev = iflib_get_dev(ctx); 784 adapter = iflib_get_softc(ctx); 785 786 adapter->ctx = adapter->osdep.ctx = ctx; 787 adapter->dev = adapter->osdep.dev = dev; 788 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 789 adapter->media = iflib_get_media(ctx); 790 hw = &adapter->hw; 791 792 adapter->tx_process_limit = scctx->isc_ntxd[0]; 793 794 /* SYSCTL stuff */ 795 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 796 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 797 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 798 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 799 800 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 801 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 802 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 803 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 804 805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 808 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 809 810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812 OID_AUTO, "reg_dump", 813 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 814 em_get_regs, "A", "Dump Registers"); 815 816 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 817 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 818 OID_AUTO, "rs_dump", 819 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 820 em_get_rs, "I", "Dump RS indexes"); 821 822 /* Determine hardware and mac info */ 823 em_identify_hardware(ctx); 824 825 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 826 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 827 if (bootverbose) 828 device_printf(dev, "attach_pre capping queues at %d\n", 829 scctx->isc_ntxqsets_max); 830 831 if (hw->mac.type >= igb_mac_min) { 832 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 833 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 834 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 835 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 836 scctx->isc_txrx = &igb_txrx; 837 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 838 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 839 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 840 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 841 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 842 CSUM_IP6_TCP | CSUM_IP6_UDP; 843 if (hw->mac.type != e1000_82575) 844 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 845 /* 846 ** Some new devices, as with ixgbe, now may 847 ** use a different BAR, so we need to keep 848 ** track of which is used. 849 */ 850 scctx->isc_msix_bar = pci_msix_table_bar(dev); 851 } else if (hw->mac.type >= em_mac_min) { 852 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 853 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 854 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 855 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 856 scctx->isc_txrx = &em_txrx; 857 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 858 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 859 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 860 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 861 /* 862 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 863 * by default as we don't have workarounds for all associated 864 * silicon errata. E. g., with several MACs such as 82573E, 865 * TSO only works at Gigabit speed and otherwise can cause the 866 * hardware to hang (which also would be next to impossible to 867 * work around given that already queued TSO-using descriptors 868 * would need to be flushed and vlan(4) reconfigured at runtime 869 * in case of a link speed change). Moreover, MACs like 82579 870 * still can hang at Gigabit even with all publicly documented 871 * TSO workarounds implemented. Generally, the penality of 872 * these workarounds is rather high and may involve copying 873 * mbuf data around so advantages of TSO lapse. Still, TSO may 874 * work for a few MACs of this class - at least when sticking 875 * with Gigabit - in which case users may enable TSO manually. 876 */ 877 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 878 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 879 /* 880 * We support MSI-X with 82574 only, but indicate to iflib(4) 881 * that it shall give MSI at least a try with other devices. 882 */ 883 if (hw->mac.type == e1000_82574) { 884 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 885 } else { 886 scctx->isc_msix_bar = -1; 887 scctx->isc_disable_msix = 1; 888 } 889 } else { 890 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 891 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 892 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 893 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 894 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 895 scctx->isc_txrx = &lem_txrx; 896 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 897 if (hw->mac.type < e1000_82543) 898 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 899 /* INTx only */ 900 scctx->isc_msix_bar = 0; 901 } 902 903 /* Setup PCI resources */ 904 if (em_allocate_pci_resources(ctx)) { 905 device_printf(dev, "Allocation of PCI resources failed\n"); 906 error = ENXIO; 907 goto err_pci; 908 } 909 910 /* 911 ** For ICH8 and family we need to 912 ** map the flash memory, and this 913 ** must happen after the MAC is 914 ** identified 915 */ 916 if ((hw->mac.type == e1000_ich8lan) || 917 (hw->mac.type == e1000_ich9lan) || 918 (hw->mac.type == e1000_ich10lan) || 919 (hw->mac.type == e1000_pchlan) || 920 (hw->mac.type == e1000_pch2lan) || 921 (hw->mac.type == e1000_pch_lpt)) { 922 int rid = EM_BAR_TYPE_FLASH; 923 adapter->flash = bus_alloc_resource_any(dev, 924 SYS_RES_MEMORY, &rid, RF_ACTIVE); 925 if (adapter->flash == NULL) { 926 device_printf(dev, "Mapping of Flash failed\n"); 927 error = ENXIO; 928 goto err_pci; 929 } 930 /* This is used in the shared code */ 931 hw->flash_address = (u8 *)adapter->flash; 932 adapter->osdep.flash_bus_space_tag = 933 rman_get_bustag(adapter->flash); 934 adapter->osdep.flash_bus_space_handle = 935 rman_get_bushandle(adapter->flash); 936 } 937 /* 938 ** In the new SPT device flash is not a 939 ** separate BAR, rather it is also in BAR0, 940 ** so use the same tag and an offset handle for the 941 ** FLASH read/write macros in the shared code. 942 */ 943 else if (hw->mac.type >= e1000_pch_spt) { 944 adapter->osdep.flash_bus_space_tag = 945 adapter->osdep.mem_bus_space_tag; 946 adapter->osdep.flash_bus_space_handle = 947 adapter->osdep.mem_bus_space_handle 948 + E1000_FLASH_BASE_ADDR; 949 } 950 951 /* Do Shared Code initialization */ 952 error = e1000_setup_init_funcs(hw, TRUE); 953 if (error) { 954 device_printf(dev, "Setup of Shared code failed, error %d\n", 955 error); 956 error = ENXIO; 957 goto err_pci; 958 } 959 960 em_setup_msix(ctx); 961 e1000_get_bus_info(hw); 962 963 /* Set up some sysctls for the tunable interrupt delays */ 964 em_add_int_delay_sysctl(adapter, "rx_int_delay", 965 "receive interrupt delay in usecs", &adapter->rx_int_delay, 966 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 967 em_add_int_delay_sysctl(adapter, "tx_int_delay", 968 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 969 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 970 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 971 "receive interrupt delay limit in usecs", 972 &adapter->rx_abs_int_delay, 973 E1000_REGISTER(hw, E1000_RADV), 974 em_rx_abs_int_delay_dflt); 975 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 976 "transmit interrupt delay limit in usecs", 977 &adapter->tx_abs_int_delay, 978 E1000_REGISTER(hw, E1000_TADV), 979 em_tx_abs_int_delay_dflt); 980 em_add_int_delay_sysctl(adapter, "itr", 981 "interrupt delay limit in usecs/4", 982 &adapter->tx_itr, 983 E1000_REGISTER(hw, E1000_ITR), 984 DEFAULT_ITR); 985 986 hw->mac.autoneg = DO_AUTO_NEG; 987 hw->phy.autoneg_wait_to_complete = FALSE; 988 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 989 990 if (hw->mac.type < em_mac_min) { 991 e1000_init_script_state_82541(hw, TRUE); 992 e1000_set_tbi_compatibility_82543(hw, TRUE); 993 } 994 /* Copper options */ 995 if (hw->phy.media_type == e1000_media_type_copper) { 996 hw->phy.mdix = AUTO_ALL_MODES; 997 hw->phy.disable_polarity_correction = FALSE; 998 hw->phy.ms_type = EM_MASTER_SLAVE; 999 } 1000 1001 /* 1002 * Set the frame limits assuming 1003 * standard ethernet sized frames. 1004 */ 1005 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1006 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1007 1008 /* 1009 * This controls when hardware reports transmit completion 1010 * status. 1011 */ 1012 hw->mac.report_tx_early = 1; 1013 1014 /* Allocate multicast array memory. */ 1015 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1016 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1017 if (adapter->mta == NULL) { 1018 device_printf(dev, "Can not allocate multicast setup array\n"); 1019 error = ENOMEM; 1020 goto err_late; 1021 } 1022 1023 /* Check SOL/IDER usage */ 1024 if (e1000_check_reset_block(hw)) 1025 device_printf(dev, "PHY reset is blocked" 1026 " due to SOL/IDER session.\n"); 1027 1028 /* Sysctl for setting Energy Efficient Ethernet */ 1029 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1030 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1031 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1032 OID_AUTO, "eee_control", 1033 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1034 adapter, 0, em_sysctl_eee, "I", 1035 "Disable Energy Efficient Ethernet"); 1036 1037 /* 1038 ** Start from a known state, this is 1039 ** important in reading the nvm and 1040 ** mac from that. 1041 */ 1042 e1000_reset_hw(hw); 1043 1044 /* Make sure we have a good EEPROM before we read from it */ 1045 if (e1000_validate_nvm_checksum(hw) < 0) { 1046 /* 1047 ** Some PCI-E parts fail the first check due to 1048 ** the link being in sleep state, call it again, 1049 ** if it fails a second time its a real issue. 1050 */ 1051 if (e1000_validate_nvm_checksum(hw) < 0) { 1052 device_printf(dev, 1053 "The EEPROM Checksum Is Not Valid\n"); 1054 error = EIO; 1055 goto err_late; 1056 } 1057 } 1058 1059 /* Copy the permanent MAC address out of the EEPROM */ 1060 if (e1000_read_mac_addr(hw) < 0) { 1061 device_printf(dev, "EEPROM read error while reading MAC" 1062 " address\n"); 1063 error = EIO; 1064 goto err_late; 1065 } 1066 1067 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1068 device_printf(dev, "Invalid MAC address\n"); 1069 error = EIO; 1070 goto err_late; 1071 } 1072 1073 /* Disable ULP support */ 1074 e1000_disable_ulp_lpt_lp(hw, TRUE); 1075 1076 /* 1077 * Get Wake-on-Lan and Management info for later use 1078 */ 1079 em_get_wakeup(ctx); 1080 1081 /* Enable only WOL MAGIC by default */ 1082 scctx->isc_capenable &= ~IFCAP_WOL; 1083 if (adapter->wol != 0) 1084 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1085 1086 iflib_set_mac(ctx, hw->mac.addr); 1087 1088 return (0); 1089 1090 err_late: 1091 em_release_hw_control(adapter); 1092 err_pci: 1093 em_free_pci_resources(ctx); 1094 free(adapter->mta, M_DEVBUF); 1095 1096 return (error); 1097 } 1098 1099 static int 1100 em_if_attach_post(if_ctx_t ctx) 1101 { 1102 struct adapter *adapter = iflib_get_softc(ctx); 1103 struct e1000_hw *hw = &adapter->hw; 1104 int error = 0; 1105 1106 /* Setup OS specific network interface */ 1107 error = em_setup_interface(ctx); 1108 if (error != 0) { 1109 goto err_late; 1110 } 1111 1112 em_reset(ctx); 1113 1114 /* Initialize statistics */ 1115 em_update_stats_counters(adapter); 1116 hw->mac.get_link_status = 1; 1117 em_if_update_admin_status(ctx); 1118 em_add_hw_stats(adapter); 1119 1120 /* Non-AMT based hardware can now take control from firmware */ 1121 if (adapter->has_manage && !adapter->has_amt) 1122 em_get_hw_control(adapter); 1123 1124 INIT_DEBUGOUT("em_if_attach_post: end"); 1125 1126 return (error); 1127 1128 err_late: 1129 em_release_hw_control(adapter); 1130 em_free_pci_resources(ctx); 1131 em_if_queues_free(ctx); 1132 free(adapter->mta, M_DEVBUF); 1133 1134 return (error); 1135 } 1136 1137 /********************************************************************* 1138 * Device removal routine 1139 * 1140 * The detach entry point is called when the driver is being removed. 1141 * This routine stops the adapter and deallocates all the resources 1142 * that were allocated for driver operation. 1143 * 1144 * return 0 on success, positive on failure 1145 *********************************************************************/ 1146 static int 1147 em_if_detach(if_ctx_t ctx) 1148 { 1149 struct adapter *adapter = iflib_get_softc(ctx); 1150 1151 INIT_DEBUGOUT("em_if_detach: begin"); 1152 1153 e1000_phy_hw_reset(&adapter->hw); 1154 1155 em_release_manageability(adapter); 1156 em_release_hw_control(adapter); 1157 em_free_pci_resources(ctx); 1158 1159 return (0); 1160 } 1161 1162 /********************************************************************* 1163 * 1164 * Shutdown entry point 1165 * 1166 **********************************************************************/ 1167 1168 static int 1169 em_if_shutdown(if_ctx_t ctx) 1170 { 1171 return em_if_suspend(ctx); 1172 } 1173 1174 /* 1175 * Suspend/resume device methods. 1176 */ 1177 static int 1178 em_if_suspend(if_ctx_t ctx) 1179 { 1180 struct adapter *adapter = iflib_get_softc(ctx); 1181 1182 em_release_manageability(adapter); 1183 em_release_hw_control(adapter); 1184 em_enable_wakeup(ctx); 1185 return (0); 1186 } 1187 1188 static int 1189 em_if_resume(if_ctx_t ctx) 1190 { 1191 struct adapter *adapter = iflib_get_softc(ctx); 1192 1193 if (adapter->hw.mac.type == e1000_pch2lan) 1194 e1000_resume_workarounds_pchlan(&adapter->hw); 1195 em_if_init(ctx); 1196 em_init_manageability(adapter); 1197 1198 return(0); 1199 } 1200 1201 static int 1202 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1203 { 1204 int max_frame_size; 1205 struct adapter *adapter = iflib_get_softc(ctx); 1206 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1207 1208 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1209 1210 switch (adapter->hw.mac.type) { 1211 case e1000_82571: 1212 case e1000_82572: 1213 case e1000_ich9lan: 1214 case e1000_ich10lan: 1215 case e1000_pch2lan: 1216 case e1000_pch_lpt: 1217 case e1000_pch_spt: 1218 case e1000_pch_cnp: 1219 case e1000_82574: 1220 case e1000_82583: 1221 case e1000_80003es2lan: 1222 /* 9K Jumbo Frame size */ 1223 max_frame_size = 9234; 1224 break; 1225 case e1000_pchlan: 1226 max_frame_size = 4096; 1227 break; 1228 case e1000_82542: 1229 case e1000_ich8lan: 1230 /* Adapters that do not support jumbo frames */ 1231 max_frame_size = ETHER_MAX_LEN; 1232 break; 1233 default: 1234 if (adapter->hw.mac.type >= igb_mac_min) 1235 max_frame_size = 9234; 1236 else /* lem */ 1237 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1238 } 1239 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1240 return (EINVAL); 1241 } 1242 1243 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1244 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1245 return (0); 1246 } 1247 1248 /********************************************************************* 1249 * Init entry point 1250 * 1251 * This routine is used in two ways. It is used by the stack as 1252 * init entry point in network interface structure. It is also used 1253 * by the driver as a hw/sw initialization routine to get to a 1254 * consistent state. 1255 * 1256 **********************************************************************/ 1257 static void 1258 em_if_init(if_ctx_t ctx) 1259 { 1260 struct adapter *adapter = iflib_get_softc(ctx); 1261 if_softc_ctx_t scctx = adapter->shared; 1262 struct ifnet *ifp = iflib_get_ifp(ctx); 1263 struct em_tx_queue *tx_que; 1264 int i; 1265 1266 INIT_DEBUGOUT("em_if_init: begin"); 1267 1268 /* Get the latest mac address, User can use a LAA */ 1269 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1270 ETHER_ADDR_LEN); 1271 1272 /* Put the address into the Receive Address Array */ 1273 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1274 1275 /* 1276 * With the 82571 adapter, RAR[0] may be overwritten 1277 * when the other port is reset, we make a duplicate 1278 * in RAR[14] for that eventuality, this assures 1279 * the interface continues to function. 1280 */ 1281 if (adapter->hw.mac.type == e1000_82571) { 1282 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1283 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1284 E1000_RAR_ENTRIES - 1); 1285 } 1286 1287 1288 /* Initialize the hardware */ 1289 em_reset(ctx); 1290 em_if_update_admin_status(ctx); 1291 1292 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1293 struct tx_ring *txr = &tx_que->txr; 1294 1295 txr->tx_rs_cidx = txr->tx_rs_pidx; 1296 1297 /* Initialize the last processed descriptor to be the end of 1298 * the ring, rather than the start, so that we avoid an 1299 * off-by-one error when calculating how many descriptors are 1300 * done in the credits_update function. 1301 */ 1302 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1303 } 1304 1305 /* Setup VLAN support, basic and offload if available */ 1306 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1307 1308 /* Clear bad data from Rx FIFOs */ 1309 if (adapter->hw.mac.type >= igb_mac_min) 1310 e1000_rx_fifo_flush_82575(&adapter->hw); 1311 1312 /* Configure for OS presence */ 1313 em_init_manageability(adapter); 1314 1315 /* Prepare transmit descriptors and buffers */ 1316 em_initialize_transmit_unit(ctx); 1317 1318 /* Setup Multicast table */ 1319 em_if_multi_set(ctx); 1320 1321 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1322 em_initialize_receive_unit(ctx); 1323 1324 /* Use real VLAN Filter support? */ 1325 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1326 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1327 /* Use real VLAN Filter support */ 1328 em_setup_vlan_hw_support(adapter); 1329 else { 1330 u32 ctrl; 1331 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1332 ctrl |= E1000_CTRL_VME; 1333 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1334 } 1335 } else { 1336 u32 ctrl; 1337 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1338 ctrl &= ~E1000_CTRL_VME; 1339 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1340 } 1341 1342 /* Don't lose promiscuous settings */ 1343 em_if_set_promisc(ctx, if_getflags(ifp)); 1344 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1345 1346 /* MSI-X configuration for 82574 */ 1347 if (adapter->hw.mac.type == e1000_82574) { 1348 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1349 1350 tmp |= E1000_CTRL_EXT_PBA_CLR; 1351 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1352 /* Set the IVAR - interrupt vector routing. */ 1353 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1354 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1355 igb_configure_queues(adapter); 1356 1357 /* this clears any pending interrupts */ 1358 E1000_READ_REG(&adapter->hw, E1000_ICR); 1359 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1360 1361 /* AMT based hardware can now take control from firmware */ 1362 if (adapter->has_manage && adapter->has_amt) 1363 em_get_hw_control(adapter); 1364 1365 /* Set Energy Efficient Ethernet */ 1366 if (adapter->hw.mac.type >= igb_mac_min && 1367 adapter->hw.phy.media_type == e1000_media_type_copper) { 1368 if (adapter->hw.mac.type == e1000_i354) 1369 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1370 else 1371 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1372 } 1373 } 1374 1375 /********************************************************************* 1376 * 1377 * Fast Legacy/MSI Combined Interrupt Service routine 1378 * 1379 *********************************************************************/ 1380 int 1381 em_intr(void *arg) 1382 { 1383 struct adapter *adapter = arg; 1384 if_ctx_t ctx = adapter->ctx; 1385 u32 reg_icr; 1386 1387 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1388 1389 /* Hot eject? */ 1390 if (reg_icr == 0xffffffff) 1391 return FILTER_STRAY; 1392 1393 /* Definitely not our interrupt. */ 1394 if (reg_icr == 0x0) 1395 return FILTER_STRAY; 1396 1397 /* 1398 * Starting with the 82571 chip, bit 31 should be used to 1399 * determine whether the interrupt belongs to us. 1400 */ 1401 if (adapter->hw.mac.type >= e1000_82571 && 1402 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1403 return FILTER_STRAY; 1404 1405 /* 1406 * Only MSI-X interrupts have one-shot behavior by taking advantage 1407 * of the EIAC register. Thus, explicitly disable interrupts. This 1408 * also works around the MSI message reordering errata on certain 1409 * systems. 1410 */ 1411 IFDI_INTR_DISABLE(ctx); 1412 1413 /* Link status change */ 1414 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1415 em_handle_link(ctx); 1416 1417 if (reg_icr & E1000_ICR_RXO) 1418 adapter->rx_overruns++; 1419 1420 return (FILTER_SCHEDULE_THREAD); 1421 } 1422 1423 static int 1424 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1425 { 1426 struct adapter *adapter = iflib_get_softc(ctx); 1427 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1428 1429 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1430 return (0); 1431 } 1432 1433 static int 1434 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1435 { 1436 struct adapter *adapter = iflib_get_softc(ctx); 1437 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1438 1439 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1440 return (0); 1441 } 1442 1443 static int 1444 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1445 { 1446 struct adapter *adapter = iflib_get_softc(ctx); 1447 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1448 1449 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1450 return (0); 1451 } 1452 1453 static int 1454 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1455 { 1456 struct adapter *adapter = iflib_get_softc(ctx); 1457 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1458 1459 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1460 return (0); 1461 } 1462 1463 /********************************************************************* 1464 * 1465 * MSI-X RX Interrupt Service routine 1466 * 1467 **********************************************************************/ 1468 static int 1469 em_msix_que(void *arg) 1470 { 1471 struct em_rx_queue *que = arg; 1472 1473 ++que->irqs; 1474 1475 return (FILTER_SCHEDULE_THREAD); 1476 } 1477 1478 /********************************************************************* 1479 * 1480 * MSI-X Link Fast Interrupt Service routine 1481 * 1482 **********************************************************************/ 1483 static int 1484 em_msix_link(void *arg) 1485 { 1486 struct adapter *adapter = arg; 1487 u32 reg_icr; 1488 1489 ++adapter->link_irq; 1490 MPASS(adapter->hw.back != NULL); 1491 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1492 1493 if (reg_icr & E1000_ICR_RXO) 1494 adapter->rx_overruns++; 1495 1496 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1497 em_handle_link(adapter->ctx); 1498 } else if (adapter->hw.mac.type == e1000_82574) { 1499 /* Only re-arm 82574 if em_if_update_admin_status() won't. */ 1500 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | 1501 E1000_IMS_LSC); 1502 } 1503 1504 if (adapter->hw.mac.type == e1000_82574) { 1505 /* 1506 * Because we must read the ICR for this interrupt it may 1507 * clear other causes using autoclear, for this reason we 1508 * simply create a soft interrupt for all these vectors. 1509 */ 1510 if (reg_icr) 1511 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1512 } else { 1513 /* Re-arm unconditionally */ 1514 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1515 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1516 } 1517 1518 return (FILTER_HANDLED); 1519 } 1520 1521 static void 1522 em_handle_link(void *context) 1523 { 1524 if_ctx_t ctx = context; 1525 struct adapter *adapter = iflib_get_softc(ctx); 1526 1527 adapter->hw.mac.get_link_status = 1; 1528 iflib_admin_intr_deferred(ctx); 1529 } 1530 1531 /********************************************************************* 1532 * 1533 * Media Ioctl callback 1534 * 1535 * This routine is called whenever the user queries the status of 1536 * the interface using ifconfig. 1537 * 1538 **********************************************************************/ 1539 static void 1540 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1541 { 1542 struct adapter *adapter = iflib_get_softc(ctx); 1543 u_char fiber_type = IFM_1000_SX; 1544 1545 INIT_DEBUGOUT("em_if_media_status: begin"); 1546 1547 iflib_admin_intr_deferred(ctx); 1548 1549 ifmr->ifm_status = IFM_AVALID; 1550 ifmr->ifm_active = IFM_ETHER; 1551 1552 if (!adapter->link_active) { 1553 return; 1554 } 1555 1556 ifmr->ifm_status |= IFM_ACTIVE; 1557 1558 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1559 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1560 if (adapter->hw.mac.type == e1000_82545) 1561 fiber_type = IFM_1000_LX; 1562 ifmr->ifm_active |= fiber_type | IFM_FDX; 1563 } else { 1564 switch (adapter->link_speed) { 1565 case 10: 1566 ifmr->ifm_active |= IFM_10_T; 1567 break; 1568 case 100: 1569 ifmr->ifm_active |= IFM_100_TX; 1570 break; 1571 case 1000: 1572 ifmr->ifm_active |= IFM_1000_T; 1573 break; 1574 } 1575 if (adapter->link_duplex == FULL_DUPLEX) 1576 ifmr->ifm_active |= IFM_FDX; 1577 else 1578 ifmr->ifm_active |= IFM_HDX; 1579 } 1580 } 1581 1582 /********************************************************************* 1583 * 1584 * Media Ioctl callback 1585 * 1586 * This routine is called when the user changes speed/duplex using 1587 * media/mediopt option with ifconfig. 1588 * 1589 **********************************************************************/ 1590 static int 1591 em_if_media_change(if_ctx_t ctx) 1592 { 1593 struct adapter *adapter = iflib_get_softc(ctx); 1594 struct ifmedia *ifm = iflib_get_media(ctx); 1595 1596 INIT_DEBUGOUT("em_if_media_change: begin"); 1597 1598 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1599 return (EINVAL); 1600 1601 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1602 case IFM_AUTO: 1603 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1604 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1605 break; 1606 case IFM_1000_LX: 1607 case IFM_1000_SX: 1608 case IFM_1000_T: 1609 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1610 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1611 break; 1612 case IFM_100_TX: 1613 adapter->hw.mac.autoneg = FALSE; 1614 adapter->hw.phy.autoneg_advertised = 0; 1615 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1616 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1617 else 1618 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1619 break; 1620 case IFM_10_T: 1621 adapter->hw.mac.autoneg = FALSE; 1622 adapter->hw.phy.autoneg_advertised = 0; 1623 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1624 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1625 else 1626 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1627 break; 1628 default: 1629 device_printf(adapter->dev, "Unsupported media type\n"); 1630 } 1631 1632 em_if_init(ctx); 1633 1634 return (0); 1635 } 1636 1637 static int 1638 em_if_set_promisc(if_ctx_t ctx, int flags) 1639 { 1640 struct adapter *adapter = iflib_get_softc(ctx); 1641 u32 reg_rctl; 1642 1643 em_disable_promisc(ctx); 1644 1645 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1646 1647 if (flags & IFF_PROMISC) { 1648 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1649 /* Turn this on if you want to see bad packets */ 1650 if (em_debug_sbp) 1651 reg_rctl |= E1000_RCTL_SBP; 1652 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1653 } else if (flags & IFF_ALLMULTI) { 1654 reg_rctl |= E1000_RCTL_MPE; 1655 reg_rctl &= ~E1000_RCTL_UPE; 1656 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1657 } 1658 return (0); 1659 } 1660 1661 static void 1662 em_disable_promisc(if_ctx_t ctx) 1663 { 1664 struct adapter *adapter = iflib_get_softc(ctx); 1665 struct ifnet *ifp = iflib_get_ifp(ctx); 1666 u32 reg_rctl; 1667 int mcnt = 0; 1668 1669 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1670 reg_rctl &= (~E1000_RCTL_UPE); 1671 if (if_getflags(ifp) & IFF_ALLMULTI) 1672 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1673 else 1674 mcnt = if_llmaddr_count(ifp); 1675 /* Don't disable if in MAX groups */ 1676 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1677 reg_rctl &= (~E1000_RCTL_MPE); 1678 reg_rctl &= (~E1000_RCTL_SBP); 1679 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1680 } 1681 1682 1683 static u_int 1684 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1685 { 1686 u8 *mta = arg; 1687 1688 if (cnt == MAX_NUM_MULTICAST_ADDRESSES) 1689 return (1); 1690 1691 bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1692 1693 return (1); 1694 } 1695 1696 /********************************************************************* 1697 * Multicast Update 1698 * 1699 * This routine is called whenever multicast address list is updated. 1700 * 1701 **********************************************************************/ 1702 1703 static void 1704 em_if_multi_set(if_ctx_t ctx) 1705 { 1706 struct adapter *adapter = iflib_get_softc(ctx); 1707 struct ifnet *ifp = iflib_get_ifp(ctx); 1708 u32 reg_rctl = 0; 1709 u8 *mta; /* Multicast array memory */ 1710 int mcnt = 0; 1711 1712 IOCTL_DEBUGOUT("em_set_multi: begin"); 1713 1714 mta = adapter->mta; 1715 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1716 1717 if (adapter->hw.mac.type == e1000_82542 && 1718 adapter->hw.revision_id == E1000_REVISION_2) { 1719 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1720 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1721 e1000_pci_clear_mwi(&adapter->hw); 1722 reg_rctl |= E1000_RCTL_RST; 1723 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1724 msec_delay(5); 1725 } 1726 1727 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1728 1729 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1730 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1731 reg_rctl |= E1000_RCTL_MPE; 1732 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1733 } else 1734 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1735 1736 if (adapter->hw.mac.type == e1000_82542 && 1737 adapter->hw.revision_id == E1000_REVISION_2) { 1738 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1739 reg_rctl &= ~E1000_RCTL_RST; 1740 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1741 msec_delay(5); 1742 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1743 e1000_pci_set_mwi(&adapter->hw); 1744 } 1745 } 1746 1747 /********************************************************************* 1748 * Timer routine 1749 * 1750 * This routine schedules em_if_update_admin_status() to check for 1751 * link status and to gather statistics as well as to perform some 1752 * controller-specific hardware patting. 1753 * 1754 **********************************************************************/ 1755 static void 1756 em_if_timer(if_ctx_t ctx, uint16_t qid) 1757 { 1758 1759 if (qid != 0) 1760 return; 1761 1762 iflib_admin_intr_deferred(ctx); 1763 } 1764 1765 static void 1766 em_if_update_admin_status(if_ctx_t ctx) 1767 { 1768 struct adapter *adapter = iflib_get_softc(ctx); 1769 struct e1000_hw *hw = &adapter->hw; 1770 device_t dev = iflib_get_dev(ctx); 1771 u32 link_check, thstat, ctrl; 1772 1773 link_check = thstat = ctrl = 0; 1774 /* Get the cached link value or read phy for real */ 1775 switch (hw->phy.media_type) { 1776 case e1000_media_type_copper: 1777 if (hw->mac.get_link_status) { 1778 if (hw->mac.type == e1000_pch_spt) 1779 msec_delay(50); 1780 /* Do the work to read phy */ 1781 e1000_check_for_link(hw); 1782 link_check = !hw->mac.get_link_status; 1783 if (link_check) /* ESB2 fix */ 1784 e1000_cfg_on_link_up(hw); 1785 } else { 1786 link_check = TRUE; 1787 } 1788 break; 1789 case e1000_media_type_fiber: 1790 e1000_check_for_link(hw); 1791 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1792 E1000_STATUS_LU); 1793 break; 1794 case e1000_media_type_internal_serdes: 1795 e1000_check_for_link(hw); 1796 link_check = hw->mac.serdes_has_link; 1797 break; 1798 /* VF device is type_unknown */ 1799 case e1000_media_type_unknown: 1800 e1000_check_for_link(hw); 1801 link_check = !hw->mac.get_link_status; 1802 /* FALLTHROUGH */ 1803 default: 1804 break; 1805 } 1806 1807 /* Check for thermal downshift or shutdown */ 1808 if (hw->mac.type == e1000_i350) { 1809 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1810 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1811 } 1812 1813 /* Now check for a transition */ 1814 if (link_check && (adapter->link_active == 0)) { 1815 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1816 &adapter->link_duplex); 1817 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1818 if ((adapter->link_speed != SPEED_1000) && 1819 ((hw->mac.type == e1000_82571) || 1820 (hw->mac.type == e1000_82572))) { 1821 int tarc0; 1822 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1823 tarc0 &= ~TARC_SPEED_MODE_BIT; 1824 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1825 } 1826 if (bootverbose) 1827 device_printf(dev, "Link is up %d Mbps %s\n", 1828 adapter->link_speed, 1829 ((adapter->link_duplex == FULL_DUPLEX) ? 1830 "Full Duplex" : "Half Duplex")); 1831 adapter->link_active = 1; 1832 adapter->smartspeed = 0; 1833 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1834 E1000_CTRL_EXT_LINK_MODE_GMII && 1835 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1836 device_printf(dev, "Link: thermal downshift\n"); 1837 /* Delay Link Up for Phy update */ 1838 if (((hw->mac.type == e1000_i210) || 1839 (hw->mac.type == e1000_i211)) && 1840 (hw->phy.id == I210_I_PHY_ID)) 1841 msec_delay(I210_LINK_DELAY); 1842 /* Reset if the media type changed. */ 1843 if (hw->dev_spec._82575.media_changed && 1844 hw->mac.type >= igb_mac_min) { 1845 hw->dev_spec._82575.media_changed = false; 1846 adapter->flags |= IGB_MEDIA_RESET; 1847 em_reset(ctx); 1848 } 1849 iflib_link_state_change(ctx, LINK_STATE_UP, 1850 IF_Mbps(adapter->link_speed)); 1851 } else if (!link_check && (adapter->link_active == 1)) { 1852 adapter->link_speed = 0; 1853 adapter->link_duplex = 0; 1854 adapter->link_active = 0; 1855 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1856 } 1857 em_update_stats_counters(adapter); 1858 1859 /* Reset LAA into RAR[0] on 82571 */ 1860 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1861 e1000_rar_set(hw, hw->mac.addr, 0); 1862 1863 if (hw->mac.type < em_mac_min) 1864 lem_smartspeed(adapter); 1865 else if (hw->mac.type == e1000_82574 && 1866 adapter->intr_type == IFLIB_INTR_MSIX) 1867 E1000_WRITE_REG(hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1868 } 1869 1870 static void 1871 em_if_watchdog_reset(if_ctx_t ctx) 1872 { 1873 struct adapter *adapter = iflib_get_softc(ctx); 1874 1875 /* 1876 * Just count the event; iflib(4) will already trigger a 1877 * sufficient reset of the controller. 1878 */ 1879 adapter->watchdog_events++; 1880 } 1881 1882 /********************************************************************* 1883 * 1884 * This routine disables all traffic on the adapter by issuing a 1885 * global reset on the MAC. 1886 * 1887 **********************************************************************/ 1888 static void 1889 em_if_stop(if_ctx_t ctx) 1890 { 1891 struct adapter *adapter = iflib_get_softc(ctx); 1892 1893 INIT_DEBUGOUT("em_if_stop: begin"); 1894 1895 e1000_reset_hw(&adapter->hw); 1896 if (adapter->hw.mac.type >= e1000_82544) 1897 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1898 1899 e1000_led_off(&adapter->hw); 1900 e1000_cleanup_led(&adapter->hw); 1901 } 1902 1903 /********************************************************************* 1904 * 1905 * Determine hardware revision. 1906 * 1907 **********************************************************************/ 1908 static void 1909 em_identify_hardware(if_ctx_t ctx) 1910 { 1911 device_t dev = iflib_get_dev(ctx); 1912 struct adapter *adapter = iflib_get_softc(ctx); 1913 1914 /* Make sure our PCI config space has the necessary stuff set */ 1915 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1916 1917 /* Save off the information about this board */ 1918 adapter->hw.vendor_id = pci_get_vendor(dev); 1919 adapter->hw.device_id = pci_get_device(dev); 1920 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1921 adapter->hw.subsystem_vendor_id = 1922 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1923 adapter->hw.subsystem_device_id = 1924 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1925 1926 /* Do Shared Code Init and Setup */ 1927 if (e1000_set_mac_type(&adapter->hw)) { 1928 device_printf(dev, "Setup init failure\n"); 1929 return; 1930 } 1931 } 1932 1933 static int 1934 em_allocate_pci_resources(if_ctx_t ctx) 1935 { 1936 struct adapter *adapter = iflib_get_softc(ctx); 1937 device_t dev = iflib_get_dev(ctx); 1938 int rid, val; 1939 1940 rid = PCIR_BAR(0); 1941 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1942 &rid, RF_ACTIVE); 1943 if (adapter->memory == NULL) { 1944 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1945 return (ENXIO); 1946 } 1947 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1948 adapter->osdep.mem_bus_space_handle = 1949 rman_get_bushandle(adapter->memory); 1950 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1951 1952 /* Only older adapters use IO mapping */ 1953 if (adapter->hw.mac.type < em_mac_min && 1954 adapter->hw.mac.type > e1000_82543) { 1955 /* Figure our where our IO BAR is ? */ 1956 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1957 val = pci_read_config(dev, rid, 4); 1958 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1959 break; 1960 } 1961 rid += 4; 1962 /* check for 64bit BAR */ 1963 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1964 rid += 4; 1965 } 1966 if (rid >= PCIR_CIS) { 1967 device_printf(dev, "Unable to locate IO BAR\n"); 1968 return (ENXIO); 1969 } 1970 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1971 &rid, RF_ACTIVE); 1972 if (adapter->ioport == NULL) { 1973 device_printf(dev, "Unable to allocate bus resource: " 1974 "ioport\n"); 1975 return (ENXIO); 1976 } 1977 adapter->hw.io_base = 0; 1978 adapter->osdep.io_bus_space_tag = 1979 rman_get_bustag(adapter->ioport); 1980 adapter->osdep.io_bus_space_handle = 1981 rman_get_bushandle(adapter->ioport); 1982 } 1983 1984 adapter->hw.back = &adapter->osdep; 1985 1986 return (0); 1987 } 1988 1989 /********************************************************************* 1990 * 1991 * Set up the MSI-X Interrupt handlers 1992 * 1993 **********************************************************************/ 1994 static int 1995 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1996 { 1997 struct adapter *adapter = iflib_get_softc(ctx); 1998 struct em_rx_queue *rx_que = adapter->rx_queues; 1999 struct em_tx_queue *tx_que = adapter->tx_queues; 2000 int error, rid, i, vector = 0, rx_vectors; 2001 char buf[16]; 2002 2003 /* First set up ring resources */ 2004 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2005 rid = vector + 1; 2006 snprintf(buf, sizeof(buf), "rxq%d", i); 2007 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2008 if (error) { 2009 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2010 adapter->rx_num_queues = i + 1; 2011 goto fail; 2012 } 2013 2014 rx_que->msix = vector; 2015 2016 /* 2017 * Set the bit to enable interrupt 2018 * in E1000_IMS -- bits 20 and 21 2019 * are for RX0 and RX1, note this has 2020 * NOTHING to do with the MSI-X vector 2021 */ 2022 if (adapter->hw.mac.type == e1000_82574) { 2023 rx_que->eims = 1 << (20 + i); 2024 adapter->ims |= rx_que->eims; 2025 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2026 } else if (adapter->hw.mac.type == e1000_82575) 2027 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2028 else 2029 rx_que->eims = 1 << vector; 2030 } 2031 rx_vectors = vector; 2032 2033 vector = 0; 2034 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2035 snprintf(buf, sizeof(buf), "txq%d", i); 2036 tx_que = &adapter->tx_queues[i]; 2037 iflib_softirq_alloc_generic(ctx, 2038 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2039 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2040 2041 tx_que->msix = (vector % adapter->rx_num_queues); 2042 2043 /* 2044 * Set the bit to enable interrupt 2045 * in E1000_IMS -- bits 22 and 23 2046 * are for TX0 and TX1, note this has 2047 * NOTHING to do with the MSI-X vector 2048 */ 2049 if (adapter->hw.mac.type == e1000_82574) { 2050 tx_que->eims = 1 << (22 + i); 2051 adapter->ims |= tx_que->eims; 2052 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2053 } else if (adapter->hw.mac.type == e1000_82575) { 2054 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2055 } else { 2056 tx_que->eims = 1 << i; 2057 } 2058 } 2059 2060 /* Link interrupt */ 2061 rid = rx_vectors + 1; 2062 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2063 2064 if (error) { 2065 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2066 goto fail; 2067 } 2068 adapter->linkvec = rx_vectors; 2069 if (adapter->hw.mac.type < igb_mac_min) { 2070 adapter->ivars |= (8 | rx_vectors) << 16; 2071 adapter->ivars |= 0x80000000; 2072 } 2073 return (0); 2074 fail: 2075 iflib_irq_free(ctx, &adapter->irq); 2076 rx_que = adapter->rx_queues; 2077 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2078 iflib_irq_free(ctx, &rx_que->que_irq); 2079 return (error); 2080 } 2081 2082 static void 2083 igb_configure_queues(struct adapter *adapter) 2084 { 2085 struct e1000_hw *hw = &adapter->hw; 2086 struct em_rx_queue *rx_que; 2087 struct em_tx_queue *tx_que; 2088 u32 tmp, ivar = 0, newitr = 0; 2089 2090 /* First turn on RSS capability */ 2091 if (hw->mac.type != e1000_82575) 2092 E1000_WRITE_REG(hw, E1000_GPIE, 2093 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2094 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2095 2096 /* Turn on MSI-X */ 2097 switch (hw->mac.type) { 2098 case e1000_82580: 2099 case e1000_i350: 2100 case e1000_i354: 2101 case e1000_i210: 2102 case e1000_i211: 2103 case e1000_vfadapt: 2104 case e1000_vfadapt_i350: 2105 /* RX entries */ 2106 for (int i = 0; i < adapter->rx_num_queues; i++) { 2107 u32 index = i >> 1; 2108 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2109 rx_que = &adapter->rx_queues[i]; 2110 if (i & 1) { 2111 ivar &= 0xFF00FFFF; 2112 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2113 } else { 2114 ivar &= 0xFFFFFF00; 2115 ivar |= rx_que->msix | E1000_IVAR_VALID; 2116 } 2117 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2118 } 2119 /* TX entries */ 2120 for (int i = 0; i < adapter->tx_num_queues; i++) { 2121 u32 index = i >> 1; 2122 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2123 tx_que = &adapter->tx_queues[i]; 2124 if (i & 1) { 2125 ivar &= 0x00FFFFFF; 2126 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2127 } else { 2128 ivar &= 0xFFFF00FF; 2129 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2130 } 2131 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2132 adapter->que_mask |= tx_que->eims; 2133 } 2134 2135 /* And for the link interrupt */ 2136 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2137 adapter->link_mask = 1 << adapter->linkvec; 2138 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2139 break; 2140 case e1000_82576: 2141 /* RX entries */ 2142 for (int i = 0; i < adapter->rx_num_queues; i++) { 2143 u32 index = i & 0x7; /* Each IVAR has two entries */ 2144 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2145 rx_que = &adapter->rx_queues[i]; 2146 if (i < 8) { 2147 ivar &= 0xFFFFFF00; 2148 ivar |= rx_que->msix | E1000_IVAR_VALID; 2149 } else { 2150 ivar &= 0xFF00FFFF; 2151 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2152 } 2153 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2154 adapter->que_mask |= rx_que->eims; 2155 } 2156 /* TX entries */ 2157 for (int i = 0; i < adapter->tx_num_queues; i++) { 2158 u32 index = i & 0x7; /* Each IVAR has two entries */ 2159 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2160 tx_que = &adapter->tx_queues[i]; 2161 if (i < 8) { 2162 ivar &= 0xFFFF00FF; 2163 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2164 } else { 2165 ivar &= 0x00FFFFFF; 2166 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2167 } 2168 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2169 adapter->que_mask |= tx_que->eims; 2170 } 2171 2172 /* And for the link interrupt */ 2173 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2174 adapter->link_mask = 1 << adapter->linkvec; 2175 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2176 break; 2177 2178 case e1000_82575: 2179 /* enable MSI-X support*/ 2180 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2181 tmp |= E1000_CTRL_EXT_PBA_CLR; 2182 /* Auto-Mask interrupts upon ICR read. */ 2183 tmp |= E1000_CTRL_EXT_EIAME; 2184 tmp |= E1000_CTRL_EXT_IRCA; 2185 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2186 2187 /* Queues */ 2188 for (int i = 0; i < adapter->rx_num_queues; i++) { 2189 rx_que = &adapter->rx_queues[i]; 2190 tmp = E1000_EICR_RX_QUEUE0 << i; 2191 tmp |= E1000_EICR_TX_QUEUE0 << i; 2192 rx_que->eims = tmp; 2193 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2194 i, rx_que->eims); 2195 adapter->que_mask |= rx_que->eims; 2196 } 2197 2198 /* Link */ 2199 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2200 E1000_EIMS_OTHER); 2201 adapter->link_mask |= E1000_EIMS_OTHER; 2202 default: 2203 break; 2204 } 2205 2206 /* Set the starting interrupt rate */ 2207 if (em_max_interrupt_rate > 0) 2208 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2209 2210 if (hw->mac.type == e1000_82575) 2211 newitr |= newitr << 16; 2212 else 2213 newitr |= E1000_EITR_CNT_IGNR; 2214 2215 for (int i = 0; i < adapter->rx_num_queues; i++) { 2216 rx_que = &adapter->rx_queues[i]; 2217 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2218 } 2219 2220 return; 2221 } 2222 2223 static void 2224 em_free_pci_resources(if_ctx_t ctx) 2225 { 2226 struct adapter *adapter = iflib_get_softc(ctx); 2227 struct em_rx_queue *que = adapter->rx_queues; 2228 device_t dev = iflib_get_dev(ctx); 2229 2230 /* Release all MSI-X queue resources */ 2231 if (adapter->intr_type == IFLIB_INTR_MSIX) 2232 iflib_irq_free(ctx, &adapter->irq); 2233 2234 if (que != NULL) { 2235 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2236 iflib_irq_free(ctx, &que->que_irq); 2237 } 2238 } 2239 2240 if (adapter->memory != NULL) { 2241 bus_release_resource(dev, SYS_RES_MEMORY, 2242 rman_get_rid(adapter->memory), adapter->memory); 2243 adapter->memory = NULL; 2244 } 2245 2246 if (adapter->flash != NULL) { 2247 bus_release_resource(dev, SYS_RES_MEMORY, 2248 rman_get_rid(adapter->flash), adapter->flash); 2249 adapter->flash = NULL; 2250 } 2251 2252 if (adapter->ioport != NULL) { 2253 bus_release_resource(dev, SYS_RES_IOPORT, 2254 rman_get_rid(adapter->ioport), adapter->ioport); 2255 adapter->ioport = NULL; 2256 } 2257 } 2258 2259 /* Set up MSI or MSI-X */ 2260 static int 2261 em_setup_msix(if_ctx_t ctx) 2262 { 2263 struct adapter *adapter = iflib_get_softc(ctx); 2264 2265 if (adapter->hw.mac.type == e1000_82574) { 2266 em_enable_vectors_82574(ctx); 2267 } 2268 return (0); 2269 } 2270 2271 /********************************************************************* 2272 * 2273 * Workaround for SmartSpeed on 82541 and 82547 controllers 2274 * 2275 **********************************************************************/ 2276 static void 2277 lem_smartspeed(struct adapter *adapter) 2278 { 2279 u16 phy_tmp; 2280 2281 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2282 adapter->hw.mac.autoneg == 0 || 2283 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2284 return; 2285 2286 if (adapter->smartspeed == 0) { 2287 /* If Master/Slave config fault is asserted twice, 2288 * we assume back-to-back */ 2289 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2290 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2291 return; 2292 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2293 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2294 e1000_read_phy_reg(&adapter->hw, 2295 PHY_1000T_CTRL, &phy_tmp); 2296 if(phy_tmp & CR_1000T_MS_ENABLE) { 2297 phy_tmp &= ~CR_1000T_MS_ENABLE; 2298 e1000_write_phy_reg(&adapter->hw, 2299 PHY_1000T_CTRL, phy_tmp); 2300 adapter->smartspeed++; 2301 if(adapter->hw.mac.autoneg && 2302 !e1000_copper_link_autoneg(&adapter->hw) && 2303 !e1000_read_phy_reg(&adapter->hw, 2304 PHY_CONTROL, &phy_tmp)) { 2305 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2306 MII_CR_RESTART_AUTO_NEG); 2307 e1000_write_phy_reg(&adapter->hw, 2308 PHY_CONTROL, phy_tmp); 2309 } 2310 } 2311 } 2312 return; 2313 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2314 /* If still no link, perhaps using 2/3 pair cable */ 2315 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2316 phy_tmp |= CR_1000T_MS_ENABLE; 2317 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2318 if(adapter->hw.mac.autoneg && 2319 !e1000_copper_link_autoneg(&adapter->hw) && 2320 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2321 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2322 MII_CR_RESTART_AUTO_NEG); 2323 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2324 } 2325 } 2326 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2327 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2328 adapter->smartspeed = 0; 2329 } 2330 2331 /********************************************************************* 2332 * 2333 * Initialize the DMA Coalescing feature 2334 * 2335 **********************************************************************/ 2336 static void 2337 igb_init_dmac(struct adapter *adapter, u32 pba) 2338 { 2339 device_t dev = adapter->dev; 2340 struct e1000_hw *hw = &adapter->hw; 2341 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2342 u16 hwm; 2343 u16 max_frame_size; 2344 2345 if (hw->mac.type == e1000_i211) 2346 return; 2347 2348 max_frame_size = adapter->shared->isc_max_frame_size; 2349 if (hw->mac.type > e1000_82580) { 2350 2351 if (adapter->dmac == 0) { /* Disabling it */ 2352 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2353 return; 2354 } else 2355 device_printf(dev, "DMA Coalescing enabled\n"); 2356 2357 /* Set starting threshold */ 2358 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2359 2360 hwm = 64 * pba - max_frame_size / 16; 2361 if (hwm < 64 * (pba - 6)) 2362 hwm = 64 * (pba - 6); 2363 reg = E1000_READ_REG(hw, E1000_FCRTC); 2364 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2365 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2366 & E1000_FCRTC_RTH_COAL_MASK); 2367 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2368 2369 2370 dmac = pba - max_frame_size / 512; 2371 if (dmac < pba - 10) 2372 dmac = pba - 10; 2373 reg = E1000_READ_REG(hw, E1000_DMACR); 2374 reg &= ~E1000_DMACR_DMACTHR_MASK; 2375 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2376 & E1000_DMACR_DMACTHR_MASK); 2377 2378 /* transition to L0x or L1 if available..*/ 2379 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2380 2381 /* Check if status is 2.5Gb backplane connection 2382 * before configuration of watchdog timer, which is 2383 * in msec values in 12.8usec intervals 2384 * watchdog timer= msec values in 32usec intervals 2385 * for non 2.5Gb connection 2386 */ 2387 if (hw->mac.type == e1000_i354) { 2388 int status = E1000_READ_REG(hw, E1000_STATUS); 2389 if ((status & E1000_STATUS_2P5_SKU) && 2390 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2391 reg |= ((adapter->dmac * 5) >> 6); 2392 else 2393 reg |= (adapter->dmac >> 5); 2394 } else { 2395 reg |= (adapter->dmac >> 5); 2396 } 2397 2398 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2399 2400 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2401 2402 /* Set the interval before transition */ 2403 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2404 if (hw->mac.type == e1000_i350) 2405 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2406 /* 2407 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2408 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2409 */ 2410 if (hw->mac.type == e1000_i354) { 2411 int status = E1000_READ_REG(hw, E1000_STATUS); 2412 if ((status & E1000_STATUS_2P5_SKU) && 2413 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2414 reg |= 0xA; 2415 else 2416 reg |= 0x4; 2417 } else { 2418 reg |= 0x4; 2419 } 2420 2421 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2422 2423 /* free space in tx packet buffer to wake from DMA coal */ 2424 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2425 (2 * max_frame_size)) >> 6); 2426 2427 /* make low power state decision controlled by DMA coal */ 2428 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2429 reg &= ~E1000_PCIEMISC_LX_DECISION; 2430 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2431 2432 } else if (hw->mac.type == e1000_82580) { 2433 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2434 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2435 reg & ~E1000_PCIEMISC_LX_DECISION); 2436 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2437 } 2438 } 2439 2440 /********************************************************************* 2441 * 2442 * Initialize the hardware to a configuration as specified by the 2443 * adapter structure. 2444 * 2445 **********************************************************************/ 2446 static void 2447 em_reset(if_ctx_t ctx) 2448 { 2449 device_t dev = iflib_get_dev(ctx); 2450 struct adapter *adapter = iflib_get_softc(ctx); 2451 struct ifnet *ifp = iflib_get_ifp(ctx); 2452 struct e1000_hw *hw = &adapter->hw; 2453 u16 rx_buffer_size; 2454 u32 pba; 2455 2456 INIT_DEBUGOUT("em_reset: begin"); 2457 /* Let the firmware know the OS is in control */ 2458 em_get_hw_control(adapter); 2459 2460 /* Set up smart power down as default off on newer adapters. */ 2461 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2462 hw->mac.type == e1000_82572)) { 2463 u16 phy_tmp = 0; 2464 2465 /* Speed up time to link by disabling smart power down. */ 2466 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2467 phy_tmp &= ~IGP02E1000_PM_SPD; 2468 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2469 } 2470 2471 /* 2472 * Packet Buffer Allocation (PBA) 2473 * Writing PBA sets the receive portion of the buffer 2474 * the remainder is used for the transmit buffer. 2475 */ 2476 switch (hw->mac.type) { 2477 /* Total Packet Buffer on these is 48K */ 2478 case e1000_82571: 2479 case e1000_82572: 2480 case e1000_80003es2lan: 2481 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2482 break; 2483 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2484 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2485 break; 2486 case e1000_82574: 2487 case e1000_82583: 2488 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2489 break; 2490 case e1000_ich8lan: 2491 pba = E1000_PBA_8K; 2492 break; 2493 case e1000_ich9lan: 2494 case e1000_ich10lan: 2495 /* Boost Receive side for jumbo frames */ 2496 if (hw->mac.max_frame_size > 4096) 2497 pba = E1000_PBA_14K; 2498 else 2499 pba = E1000_PBA_10K; 2500 break; 2501 case e1000_pchlan: 2502 case e1000_pch2lan: 2503 case e1000_pch_lpt: 2504 case e1000_pch_spt: 2505 case e1000_pch_cnp: 2506 pba = E1000_PBA_26K; 2507 break; 2508 case e1000_82575: 2509 pba = E1000_PBA_32K; 2510 break; 2511 case e1000_82576: 2512 case e1000_vfadapt: 2513 pba = E1000_READ_REG(hw, E1000_RXPBS); 2514 pba &= E1000_RXPBS_SIZE_MASK_82576; 2515 break; 2516 case e1000_82580: 2517 case e1000_i350: 2518 case e1000_i354: 2519 case e1000_vfadapt_i350: 2520 pba = E1000_READ_REG(hw, E1000_RXPBS); 2521 pba = e1000_rxpbs_adjust_82580(pba); 2522 break; 2523 case e1000_i210: 2524 case e1000_i211: 2525 pba = E1000_PBA_34K; 2526 break; 2527 default: 2528 if (hw->mac.max_frame_size > 8192) 2529 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2530 else 2531 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2532 } 2533 2534 /* Special needs in case of Jumbo frames */ 2535 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2536 u32 tx_space, min_tx, min_rx; 2537 pba = E1000_READ_REG(hw, E1000_PBA); 2538 tx_space = pba >> 16; 2539 pba &= 0xffff; 2540 min_tx = (hw->mac.max_frame_size + 2541 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2542 min_tx = roundup2(min_tx, 1024); 2543 min_tx >>= 10; 2544 min_rx = hw->mac.max_frame_size; 2545 min_rx = roundup2(min_rx, 1024); 2546 min_rx >>= 10; 2547 if (tx_space < min_tx && 2548 ((min_tx - tx_space) < pba)) { 2549 pba = pba - (min_tx - tx_space); 2550 /* 2551 * if short on rx space, rx wins 2552 * and must trump tx adjustment 2553 */ 2554 if (pba < min_rx) 2555 pba = min_rx; 2556 } 2557 E1000_WRITE_REG(hw, E1000_PBA, pba); 2558 } 2559 2560 if (hw->mac.type < igb_mac_min) 2561 E1000_WRITE_REG(hw, E1000_PBA, pba); 2562 2563 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2564 2565 /* 2566 * These parameters control the automatic generation (Tx) and 2567 * response (Rx) to Ethernet PAUSE frames. 2568 * - High water mark should allow for at least two frames to be 2569 * received after sending an XOFF. 2570 * - Low water mark works best when it is very near the high water mark. 2571 * This allows the receiver to restart by sending XON when it has 2572 * drained a bit. Here we use an arbitrary value of 1500 which will 2573 * restart after one full frame is pulled from the buffer. There 2574 * could be several smaller frames in the buffer and if so they will 2575 * not trigger the XON until their total number reduces the buffer 2576 * by 1500. 2577 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2578 */ 2579 rx_buffer_size = (pba & 0xffff) << 10; 2580 hw->fc.high_water = rx_buffer_size - 2581 roundup2(hw->mac.max_frame_size, 1024); 2582 hw->fc.low_water = hw->fc.high_water - 1500; 2583 2584 if (adapter->fc) /* locally set flow control value? */ 2585 hw->fc.requested_mode = adapter->fc; 2586 else 2587 hw->fc.requested_mode = e1000_fc_full; 2588 2589 if (hw->mac.type == e1000_80003es2lan) 2590 hw->fc.pause_time = 0xFFFF; 2591 else 2592 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2593 2594 hw->fc.send_xon = TRUE; 2595 2596 /* Device specific overrides/settings */ 2597 switch (hw->mac.type) { 2598 case e1000_pchlan: 2599 /* Workaround: no TX flow ctrl for PCH */ 2600 hw->fc.requested_mode = e1000_fc_rx_pause; 2601 hw->fc.pause_time = 0xFFFF; /* override */ 2602 if (if_getmtu(ifp) > ETHERMTU) { 2603 hw->fc.high_water = 0x3500; 2604 hw->fc.low_water = 0x1500; 2605 } else { 2606 hw->fc.high_water = 0x5000; 2607 hw->fc.low_water = 0x3000; 2608 } 2609 hw->fc.refresh_time = 0x1000; 2610 break; 2611 case e1000_pch2lan: 2612 case e1000_pch_lpt: 2613 case e1000_pch_spt: 2614 case e1000_pch_cnp: 2615 hw->fc.high_water = 0x5C20; 2616 hw->fc.low_water = 0x5048; 2617 hw->fc.pause_time = 0x0650; 2618 hw->fc.refresh_time = 0x0400; 2619 /* Jumbos need adjusted PBA */ 2620 if (if_getmtu(ifp) > ETHERMTU) 2621 E1000_WRITE_REG(hw, E1000_PBA, 12); 2622 else 2623 E1000_WRITE_REG(hw, E1000_PBA, 26); 2624 break; 2625 case e1000_82575: 2626 case e1000_82576: 2627 /* 8-byte granularity */ 2628 hw->fc.low_water = hw->fc.high_water - 8; 2629 break; 2630 case e1000_82580: 2631 case e1000_i350: 2632 case e1000_i354: 2633 case e1000_i210: 2634 case e1000_i211: 2635 case e1000_vfadapt: 2636 case e1000_vfadapt_i350: 2637 /* 16-byte granularity */ 2638 hw->fc.low_water = hw->fc.high_water - 16; 2639 break; 2640 case e1000_ich9lan: 2641 case e1000_ich10lan: 2642 if (if_getmtu(ifp) > ETHERMTU) { 2643 hw->fc.high_water = 0x2800; 2644 hw->fc.low_water = hw->fc.high_water - 8; 2645 break; 2646 } 2647 /* FALLTHROUGH */ 2648 default: 2649 if (hw->mac.type == e1000_80003es2lan) 2650 hw->fc.pause_time = 0xFFFF; 2651 break; 2652 } 2653 2654 /* Issue a global reset */ 2655 e1000_reset_hw(hw); 2656 if (hw->mac.type >= igb_mac_min) { 2657 E1000_WRITE_REG(hw, E1000_WUC, 0); 2658 } else { 2659 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2660 em_disable_aspm(adapter); 2661 } 2662 if (adapter->flags & IGB_MEDIA_RESET) { 2663 e1000_setup_init_funcs(hw, TRUE); 2664 e1000_get_bus_info(hw); 2665 adapter->flags &= ~IGB_MEDIA_RESET; 2666 } 2667 /* and a re-init */ 2668 if (e1000_init_hw(hw) < 0) { 2669 device_printf(dev, "Hardware Initialization Failed\n"); 2670 return; 2671 } 2672 if (hw->mac.type >= igb_mac_min) 2673 igb_init_dmac(adapter, pba); 2674 2675 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2676 e1000_get_phy_info(hw); 2677 e1000_check_for_link(hw); 2678 } 2679 2680 /* 2681 * Initialise the RSS mapping for NICs that support multiple transmit/ 2682 * receive rings. 2683 */ 2684 2685 #define RSSKEYLEN 10 2686 static void 2687 em_initialize_rss_mapping(struct adapter *adapter) 2688 { 2689 uint8_t rss_key[4 * RSSKEYLEN]; 2690 uint32_t reta = 0; 2691 struct e1000_hw *hw = &adapter->hw; 2692 int i; 2693 2694 /* 2695 * Configure RSS key 2696 */ 2697 arc4rand(rss_key, sizeof(rss_key), 0); 2698 for (i = 0; i < RSSKEYLEN; ++i) { 2699 uint32_t rssrk = 0; 2700 2701 rssrk = EM_RSSRK_VAL(rss_key, i); 2702 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2703 } 2704 2705 /* 2706 * Configure RSS redirect table in following fashion: 2707 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2708 */ 2709 for (i = 0; i < sizeof(reta); ++i) { 2710 uint32_t q; 2711 2712 q = (i % adapter->rx_num_queues) << 7; 2713 reta |= q << (8 * i); 2714 } 2715 2716 for (i = 0; i < 32; ++i) 2717 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2718 2719 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2720 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2721 E1000_MRQC_RSS_FIELD_IPV4 | 2722 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2723 E1000_MRQC_RSS_FIELD_IPV6_EX | 2724 E1000_MRQC_RSS_FIELD_IPV6); 2725 } 2726 2727 static void 2728 igb_initialize_rss_mapping(struct adapter *adapter) 2729 { 2730 struct e1000_hw *hw = &adapter->hw; 2731 int i; 2732 int queue_id; 2733 u32 reta; 2734 u32 rss_key[10], mrqc, shift = 0; 2735 2736 /* XXX? */ 2737 if (hw->mac.type == e1000_82575) 2738 shift = 6; 2739 2740 /* 2741 * The redirection table controls which destination 2742 * queue each bucket redirects traffic to. 2743 * Each DWORD represents four queues, with the LSB 2744 * being the first queue in the DWORD. 2745 * 2746 * This just allocates buckets to queues using round-robin 2747 * allocation. 2748 * 2749 * NOTE: It Just Happens to line up with the default 2750 * RSS allocation method. 2751 */ 2752 2753 /* Warning FM follows */ 2754 reta = 0; 2755 for (i = 0; i < 128; i++) { 2756 #ifdef RSS 2757 queue_id = rss_get_indirection_to_bucket(i); 2758 /* 2759 * If we have more queues than buckets, we'll 2760 * end up mapping buckets to a subset of the 2761 * queues. 2762 * 2763 * If we have more buckets than queues, we'll 2764 * end up instead assigning multiple buckets 2765 * to queues. 2766 * 2767 * Both are suboptimal, but we need to handle 2768 * the case so we don't go out of bounds 2769 * indexing arrays and such. 2770 */ 2771 queue_id = queue_id % adapter->rx_num_queues; 2772 #else 2773 queue_id = (i % adapter->rx_num_queues); 2774 #endif 2775 /* Adjust if required */ 2776 queue_id = queue_id << shift; 2777 2778 /* 2779 * The low 8 bits are for hash value (n+0); 2780 * The next 8 bits are for hash value (n+1), etc. 2781 */ 2782 reta = reta >> 8; 2783 reta = reta | ( ((uint32_t) queue_id) << 24); 2784 if ((i & 3) == 3) { 2785 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2786 reta = 0; 2787 } 2788 } 2789 2790 /* Now fill in hash table */ 2791 2792 /* 2793 * MRQC: Multiple Receive Queues Command 2794 * Set queuing to RSS control, number depends on the device. 2795 */ 2796 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2797 2798 #ifdef RSS 2799 /* XXX ew typecasting */ 2800 rss_getkey((uint8_t *) &rss_key); 2801 #else 2802 arc4rand(&rss_key, sizeof(rss_key), 0); 2803 #endif 2804 for (i = 0; i < 10; i++) 2805 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2806 2807 /* 2808 * Configure the RSS fields to hash upon. 2809 */ 2810 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2811 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2812 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2813 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2814 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2815 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2816 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2817 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2818 2819 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2820 } 2821 2822 /********************************************************************* 2823 * 2824 * Setup networking device structure and register interface media. 2825 * 2826 **********************************************************************/ 2827 static int 2828 em_setup_interface(if_ctx_t ctx) 2829 { 2830 struct ifnet *ifp = iflib_get_ifp(ctx); 2831 struct adapter *adapter = iflib_get_softc(ctx); 2832 if_softc_ctx_t scctx = adapter->shared; 2833 2834 INIT_DEBUGOUT("em_setup_interface: begin"); 2835 2836 /* Single Queue */ 2837 if (adapter->tx_num_queues == 1) { 2838 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2839 if_setsendqready(ifp); 2840 } 2841 2842 /* 2843 * Specify the media types supported by this adapter and register 2844 * callbacks to update media and link information 2845 */ 2846 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2847 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2848 u_char fiber_type = IFM_1000_SX; /* default type */ 2849 2850 if (adapter->hw.mac.type == e1000_82545) 2851 fiber_type = IFM_1000_LX; 2852 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2853 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2854 } else { 2855 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2856 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2857 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2858 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2859 if (adapter->hw.phy.type != e1000_phy_ife) { 2860 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2861 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2862 } 2863 } 2864 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2865 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2866 return (0); 2867 } 2868 2869 static int 2870 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2871 { 2872 struct adapter *adapter = iflib_get_softc(ctx); 2873 if_softc_ctx_t scctx = adapter->shared; 2874 int error = E1000_SUCCESS; 2875 struct em_tx_queue *que; 2876 int i, j; 2877 2878 MPASS(adapter->tx_num_queues > 0); 2879 MPASS(adapter->tx_num_queues == ntxqsets); 2880 2881 /* First allocate the top level queue structs */ 2882 if (!(adapter->tx_queues = 2883 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2884 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2885 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2886 return(ENOMEM); 2887 } 2888 2889 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2890 /* Set up some basics */ 2891 2892 struct tx_ring *txr = &que->txr; 2893 txr->adapter = que->adapter = adapter; 2894 que->me = txr->me = i; 2895 2896 /* Allocate report status array */ 2897 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2898 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2899 error = ENOMEM; 2900 goto fail; 2901 } 2902 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2903 txr->tx_rsq[j] = QIDX_INVALID; 2904 /* get the virtual and physical address of the hardware queues */ 2905 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2906 txr->tx_paddr = paddrs[i*ntxqs]; 2907 } 2908 2909 if (bootverbose) 2910 device_printf(iflib_get_dev(ctx), 2911 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2912 return (0); 2913 fail: 2914 em_if_queues_free(ctx); 2915 return (error); 2916 } 2917 2918 static int 2919 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2920 { 2921 struct adapter *adapter = iflib_get_softc(ctx); 2922 int error = E1000_SUCCESS; 2923 struct em_rx_queue *que; 2924 int i; 2925 2926 MPASS(adapter->rx_num_queues > 0); 2927 MPASS(adapter->rx_num_queues == nrxqsets); 2928 2929 /* First allocate the top level queue structs */ 2930 if (!(adapter->rx_queues = 2931 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2932 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2933 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2934 error = ENOMEM; 2935 goto fail; 2936 } 2937 2938 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2939 /* Set up some basics */ 2940 struct rx_ring *rxr = &que->rxr; 2941 rxr->adapter = que->adapter = adapter; 2942 rxr->que = que; 2943 que->me = rxr->me = i; 2944 2945 /* get the virtual and physical address of the hardware queues */ 2946 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2947 rxr->rx_paddr = paddrs[i*nrxqs]; 2948 } 2949 2950 if (bootverbose) 2951 device_printf(iflib_get_dev(ctx), 2952 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2953 2954 return (0); 2955 fail: 2956 em_if_queues_free(ctx); 2957 return (error); 2958 } 2959 2960 static void 2961 em_if_queues_free(if_ctx_t ctx) 2962 { 2963 struct adapter *adapter = iflib_get_softc(ctx); 2964 struct em_tx_queue *tx_que = adapter->tx_queues; 2965 struct em_rx_queue *rx_que = adapter->rx_queues; 2966 2967 if (tx_que != NULL) { 2968 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2969 struct tx_ring *txr = &tx_que->txr; 2970 if (txr->tx_rsq == NULL) 2971 break; 2972 2973 free(txr->tx_rsq, M_DEVBUF); 2974 txr->tx_rsq = NULL; 2975 } 2976 free(adapter->tx_queues, M_DEVBUF); 2977 adapter->tx_queues = NULL; 2978 } 2979 2980 if (rx_que != NULL) { 2981 free(adapter->rx_queues, M_DEVBUF); 2982 adapter->rx_queues = NULL; 2983 } 2984 2985 em_release_hw_control(adapter); 2986 2987 if (adapter->mta != NULL) { 2988 free(adapter->mta, M_DEVBUF); 2989 } 2990 } 2991 2992 /********************************************************************* 2993 * 2994 * Enable transmit unit. 2995 * 2996 **********************************************************************/ 2997 static void 2998 em_initialize_transmit_unit(if_ctx_t ctx) 2999 { 3000 struct adapter *adapter = iflib_get_softc(ctx); 3001 if_softc_ctx_t scctx = adapter->shared; 3002 struct em_tx_queue *que; 3003 struct tx_ring *txr; 3004 struct e1000_hw *hw = &adapter->hw; 3005 u32 tctl, txdctl = 0, tarc, tipg = 0; 3006 3007 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3008 3009 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 3010 u64 bus_addr; 3011 caddr_t offp, endp; 3012 3013 que = &adapter->tx_queues[i]; 3014 txr = &que->txr; 3015 bus_addr = txr->tx_paddr; 3016 3017 /* Clear checksum offload context. */ 3018 offp = (caddr_t)&txr->csum_flags; 3019 endp = (caddr_t)(txr + 1); 3020 bzero(offp, endp - offp); 3021 3022 /* Base and Len of TX Ring */ 3023 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3024 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3025 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3026 (u32)(bus_addr >> 32)); 3027 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3028 (u32)bus_addr); 3029 /* Init the HEAD/TAIL indices */ 3030 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3031 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3032 3033 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3034 E1000_READ_REG(hw, E1000_TDBAL(i)), 3035 E1000_READ_REG(hw, E1000_TDLEN(i))); 3036 3037 txdctl = 0; /* clear txdctl */ 3038 txdctl |= 0x1f; /* PTHRESH */ 3039 txdctl |= 1 << 8; /* HTHRESH */ 3040 txdctl |= 1 << 16;/* WTHRESH */ 3041 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3042 txdctl |= E1000_TXDCTL_GRAN; 3043 txdctl |= 1 << 25; /* LWTHRESH */ 3044 3045 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3046 } 3047 3048 /* Set the default values for the Tx Inter Packet Gap timer */ 3049 switch (hw->mac.type) { 3050 case e1000_80003es2lan: 3051 tipg = DEFAULT_82543_TIPG_IPGR1; 3052 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3053 E1000_TIPG_IPGR2_SHIFT; 3054 break; 3055 case e1000_82542: 3056 tipg = DEFAULT_82542_TIPG_IPGT; 3057 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3058 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3059 break; 3060 default: 3061 if (hw->phy.media_type == e1000_media_type_fiber || 3062 hw->phy.media_type == e1000_media_type_internal_serdes) 3063 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3064 else 3065 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3066 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3067 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3068 } 3069 3070 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3071 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value); 3072 3073 if(hw->mac.type >= e1000_82540) 3074 E1000_WRITE_REG(hw, E1000_TADV, 3075 adapter->tx_abs_int_delay.value); 3076 3077 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3078 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3079 tarc |= TARC_SPEED_MODE_BIT; 3080 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3081 } else if (hw->mac.type == e1000_80003es2lan) { 3082 /* errata: program both queues to unweighted RR */ 3083 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3084 tarc |= 1; 3085 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3086 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3087 tarc |= 1; 3088 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3089 } else if (hw->mac.type == e1000_82574) { 3090 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3091 tarc |= TARC_ERRATA_BIT; 3092 if ( adapter->tx_num_queues > 1) { 3093 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3094 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3095 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3096 } else 3097 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3098 } 3099 3100 if (adapter->tx_int_delay.value > 0) 3101 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3102 3103 /* Program the Transmit Control Register */ 3104 tctl = E1000_READ_REG(hw, E1000_TCTL); 3105 tctl &= ~E1000_TCTL_CT; 3106 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3107 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3108 3109 if (hw->mac.type >= e1000_82571) 3110 tctl |= E1000_TCTL_MULR; 3111 3112 /* This write will effectively turn on the transmit unit. */ 3113 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3114 3115 /* SPT and KBL errata workarounds */ 3116 if (hw->mac.type == e1000_pch_spt) { 3117 u32 reg; 3118 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3119 reg |= E1000_RCTL_RDMTS_HEX; 3120 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3121 /* i218-i219 Specification Update 1.5.4.5 */ 3122 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3123 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3124 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3125 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3126 } 3127 } 3128 3129 /********************************************************************* 3130 * 3131 * Enable receive unit. 3132 * 3133 **********************************************************************/ 3134 3135 static void 3136 em_initialize_receive_unit(if_ctx_t ctx) 3137 { 3138 struct adapter *adapter = iflib_get_softc(ctx); 3139 if_softc_ctx_t scctx = adapter->shared; 3140 struct ifnet *ifp = iflib_get_ifp(ctx); 3141 struct e1000_hw *hw = &adapter->hw; 3142 struct em_rx_queue *que; 3143 int i; 3144 u32 rctl, rxcsum, rfctl; 3145 3146 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3147 3148 /* 3149 * Make sure receives are disabled while setting 3150 * up the descriptor ring 3151 */ 3152 rctl = E1000_READ_REG(hw, E1000_RCTL); 3153 /* Do not disable if ever enabled on this hardware */ 3154 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3155 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3156 3157 /* Setup the Receive Control Register */ 3158 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3159 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3160 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3161 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3162 3163 /* Do not store bad packets */ 3164 rctl &= ~E1000_RCTL_SBP; 3165 3166 /* Enable Long Packet receive */ 3167 if (if_getmtu(ifp) > ETHERMTU) 3168 rctl |= E1000_RCTL_LPE; 3169 else 3170 rctl &= ~E1000_RCTL_LPE; 3171 3172 /* Strip the CRC */ 3173 if (!em_disable_crc_stripping) 3174 rctl |= E1000_RCTL_SECRC; 3175 3176 if (hw->mac.type >= e1000_82540) { 3177 E1000_WRITE_REG(hw, E1000_RADV, 3178 adapter->rx_abs_int_delay.value); 3179 3180 /* 3181 * Set the interrupt throttling rate. Value is calculated 3182 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3183 */ 3184 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3185 } 3186 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value); 3187 3188 /* Use extended rx descriptor formats */ 3189 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3190 rfctl |= E1000_RFCTL_EXTEN; 3191 /* 3192 * When using MSI-X interrupts we need to throttle 3193 * using the EITR register (82574 only) 3194 */ 3195 if (hw->mac.type == e1000_82574) { 3196 for (int i = 0; i < 4; i++) 3197 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3198 DEFAULT_ITR); 3199 /* Disable accelerated acknowledge */ 3200 rfctl |= E1000_RFCTL_ACK_DIS; 3201 } 3202 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3203 3204 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3205 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3206 hw->mac.type >= e1000_82543) { 3207 if (adapter->tx_num_queues > 1) { 3208 if (hw->mac.type >= igb_mac_min) { 3209 rxcsum |= E1000_RXCSUM_PCSD; 3210 if (hw->mac.type != e1000_82575) 3211 rxcsum |= E1000_RXCSUM_CRCOFL; 3212 } else 3213 rxcsum |= E1000_RXCSUM_TUOFL | 3214 E1000_RXCSUM_IPOFL | 3215 E1000_RXCSUM_PCSD; 3216 } else { 3217 if (hw->mac.type >= igb_mac_min) 3218 rxcsum |= E1000_RXCSUM_IPPCSE; 3219 else 3220 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3221 if (hw->mac.type > e1000_82575) 3222 rxcsum |= E1000_RXCSUM_CRCOFL; 3223 } 3224 } else 3225 rxcsum &= ~E1000_RXCSUM_TUOFL; 3226 3227 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3228 3229 if (adapter->rx_num_queues > 1) { 3230 if (hw->mac.type >= igb_mac_min) 3231 igb_initialize_rss_mapping(adapter); 3232 else 3233 em_initialize_rss_mapping(adapter); 3234 } 3235 3236 /* 3237 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3238 * long latencies are observed, like Lenovo X60. This 3239 * change eliminates the problem, but since having positive 3240 * values in RDTR is a known source of problems on other 3241 * platforms another solution is being sought. 3242 */ 3243 if (hw->mac.type == e1000_82573) 3244 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3245 3246 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3247 struct rx_ring *rxr = &que->rxr; 3248 /* Setup the Base and Length of the Rx Descriptor Ring */ 3249 u64 bus_addr = rxr->rx_paddr; 3250 #if 0 3251 u32 rdt = adapter->rx_num_queues -1; /* default */ 3252 #endif 3253 3254 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3255 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3256 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3257 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3258 /* Setup the Head and Tail Descriptor Pointers */ 3259 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3260 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3261 } 3262 3263 /* 3264 * Set PTHRESH for improved jumbo performance 3265 * According to 10.2.5.11 of Intel 82574 Datasheet, 3266 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3267 * Only write to RXDCTL(1) if there is a need for different 3268 * settings. 3269 */ 3270 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3271 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3272 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3273 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3274 } else if (hw->mac.type == e1000_82574) { 3275 for (int i = 0; i < adapter->rx_num_queues; i++) { 3276 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3277 rxdctl |= 0x20; /* PTHRESH */ 3278 rxdctl |= 4 << 8; /* HTHRESH */ 3279 rxdctl |= 4 << 16;/* WTHRESH */ 3280 rxdctl |= 1 << 24; /* Switch to granularity */ 3281 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3282 } 3283 } else if (hw->mac.type >= igb_mac_min) { 3284 u32 psize, srrctl = 0; 3285 3286 if (if_getmtu(ifp) > ETHERMTU) { 3287 /* Set maximum packet len */ 3288 if (adapter->rx_mbuf_sz <= 4096) { 3289 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3290 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3291 } else if (adapter->rx_mbuf_sz > 4096) { 3292 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3293 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3294 } 3295 psize = scctx->isc_max_frame_size; 3296 /* are we on a vlan? */ 3297 if (ifp->if_vlantrunk != NULL) 3298 psize += VLAN_TAG_SIZE; 3299 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3300 } else { 3301 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3302 rctl |= E1000_RCTL_SZ_2048; 3303 } 3304 3305 /* 3306 * If TX flow control is disabled and there's >1 queue defined, 3307 * enable DROP. 3308 * 3309 * This drops frames rather than hanging the RX MAC for all queues. 3310 */ 3311 if ((adapter->rx_num_queues > 1) && 3312 (adapter->fc == e1000_fc_none || 3313 adapter->fc == e1000_fc_rx_pause)) { 3314 srrctl |= E1000_SRRCTL_DROP_EN; 3315 } 3316 /* Setup the Base and Length of the Rx Descriptor Rings */ 3317 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3318 struct rx_ring *rxr = &que->rxr; 3319 u64 bus_addr = rxr->rx_paddr; 3320 u32 rxdctl; 3321 3322 #ifdef notyet 3323 /* Configure for header split? -- ignore for now */ 3324 rxr->hdr_split = igb_header_split; 3325 #else 3326 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3327 #endif 3328 3329 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3330 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3331 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3332 (uint32_t)(bus_addr >> 32)); 3333 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3334 (uint32_t)bus_addr); 3335 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3336 /* Enable this Queue */ 3337 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3338 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3339 rxdctl &= 0xFFF00000; 3340 rxdctl |= IGB_RX_PTHRESH; 3341 rxdctl |= IGB_RX_HTHRESH << 8; 3342 rxdctl |= IGB_RX_WTHRESH << 16; 3343 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3344 } 3345 } else if (hw->mac.type >= e1000_pch2lan) { 3346 if (if_getmtu(ifp) > ETHERMTU) 3347 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3348 else 3349 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3350 } 3351 3352 /* Make sure VLAN Filters are off */ 3353 rctl &= ~E1000_RCTL_VFE; 3354 3355 if (hw->mac.type < igb_mac_min) { 3356 if (adapter->rx_mbuf_sz == MCLBYTES) 3357 rctl |= E1000_RCTL_SZ_2048; 3358 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3359 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3360 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3361 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3362 3363 /* ensure we clear use DTYPE of 00 here */ 3364 rctl &= ~0x00000C00; 3365 } 3366 3367 /* Write out the settings */ 3368 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3369 3370 return; 3371 } 3372 3373 static void 3374 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3375 { 3376 struct adapter *adapter = iflib_get_softc(ctx); 3377 u32 index, bit; 3378 3379 index = (vtag >> 5) & 0x7F; 3380 bit = vtag & 0x1F; 3381 adapter->shadow_vfta[index] |= (1 << bit); 3382 ++adapter->num_vlans; 3383 } 3384 3385 static void 3386 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3387 { 3388 struct adapter *adapter = iflib_get_softc(ctx); 3389 u32 index, bit; 3390 3391 index = (vtag >> 5) & 0x7F; 3392 bit = vtag & 0x1F; 3393 adapter->shadow_vfta[index] &= ~(1 << bit); 3394 --adapter->num_vlans; 3395 } 3396 3397 static void 3398 em_setup_vlan_hw_support(struct adapter *adapter) 3399 { 3400 struct e1000_hw *hw = &adapter->hw; 3401 u32 reg; 3402 3403 /* 3404 * We get here thru init_locked, meaning 3405 * a soft reset, this has already cleared 3406 * the VFTA and other state, so if there 3407 * have been no vlan's registered do nothing. 3408 */ 3409 if (adapter->num_vlans == 0) 3410 return; 3411 3412 /* 3413 * A soft reset zero's out the VFTA, so 3414 * we need to repopulate it now. 3415 */ 3416 for (int i = 0; i < EM_VFTA_SIZE; i++) 3417 if (adapter->shadow_vfta[i] != 0) 3418 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3419 i, adapter->shadow_vfta[i]); 3420 3421 reg = E1000_READ_REG(hw, E1000_CTRL); 3422 reg |= E1000_CTRL_VME; 3423 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3424 3425 /* Enable the Filter Table */ 3426 reg = E1000_READ_REG(hw, E1000_RCTL); 3427 reg &= ~E1000_RCTL_CFIEN; 3428 reg |= E1000_RCTL_VFE; 3429 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3430 } 3431 3432 static void 3433 em_if_intr_enable(if_ctx_t ctx) 3434 { 3435 struct adapter *adapter = iflib_get_softc(ctx); 3436 struct e1000_hw *hw = &adapter->hw; 3437 u32 ims_mask = IMS_ENABLE_MASK; 3438 3439 if (hw->mac.type == e1000_82574) { 3440 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3441 ims_mask |= adapter->ims; 3442 } 3443 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3444 } 3445 3446 static void 3447 em_if_intr_disable(if_ctx_t ctx) 3448 { 3449 struct adapter *adapter = iflib_get_softc(ctx); 3450 struct e1000_hw *hw = &adapter->hw; 3451 3452 if (hw->mac.type == e1000_82574) 3453 E1000_WRITE_REG(hw, EM_EIAC, 0); 3454 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3455 } 3456 3457 static void 3458 igb_if_intr_enable(if_ctx_t ctx) 3459 { 3460 struct adapter *adapter = iflib_get_softc(ctx); 3461 struct e1000_hw *hw = &adapter->hw; 3462 u32 mask; 3463 3464 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3465 mask = (adapter->que_mask | adapter->link_mask); 3466 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3467 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3468 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3469 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3470 } else 3471 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3472 E1000_WRITE_FLUSH(hw); 3473 } 3474 3475 static void 3476 igb_if_intr_disable(if_ctx_t ctx) 3477 { 3478 struct adapter *adapter = iflib_get_softc(ctx); 3479 struct e1000_hw *hw = &adapter->hw; 3480 3481 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3482 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3483 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3484 } 3485 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3486 E1000_WRITE_FLUSH(hw); 3487 } 3488 3489 /* 3490 * Bit of a misnomer, what this really means is 3491 * to enable OS management of the system... aka 3492 * to disable special hardware management features 3493 */ 3494 static void 3495 em_init_manageability(struct adapter *adapter) 3496 { 3497 /* A shared code workaround */ 3498 #define E1000_82542_MANC2H E1000_MANC2H 3499 if (adapter->has_manage) { 3500 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3501 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3502 3503 /* disable hardware interception of ARP */ 3504 manc &= ~(E1000_MANC_ARP_EN); 3505 3506 /* enable receiving management packets to the host */ 3507 manc |= E1000_MANC_EN_MNG2HOST; 3508 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3509 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3510 manc2h |= E1000_MNG2HOST_PORT_623; 3511 manc2h |= E1000_MNG2HOST_PORT_664; 3512 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3513 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3514 } 3515 } 3516 3517 /* 3518 * Give control back to hardware management 3519 * controller if there is one. 3520 */ 3521 static void 3522 em_release_manageability(struct adapter *adapter) 3523 { 3524 if (adapter->has_manage) { 3525 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3526 3527 /* re-enable hardware interception of ARP */ 3528 manc |= E1000_MANC_ARP_EN; 3529 manc &= ~E1000_MANC_EN_MNG2HOST; 3530 3531 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3532 } 3533 } 3534 3535 /* 3536 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3537 * For ASF and Pass Through versions of f/w this means 3538 * that the driver is loaded. For AMT version type f/w 3539 * this means that the network i/f is open. 3540 */ 3541 static void 3542 em_get_hw_control(struct adapter *adapter) 3543 { 3544 u32 ctrl_ext, swsm; 3545 3546 if (adapter->vf_ifp) 3547 return; 3548 3549 if (adapter->hw.mac.type == e1000_82573) { 3550 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3551 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3552 swsm | E1000_SWSM_DRV_LOAD); 3553 return; 3554 } 3555 /* else */ 3556 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3557 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3558 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3559 } 3560 3561 /* 3562 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3563 * For ASF and Pass Through versions of f/w this means that 3564 * the driver is no longer loaded. For AMT versions of the 3565 * f/w this means that the network i/f is closed. 3566 */ 3567 static void 3568 em_release_hw_control(struct adapter *adapter) 3569 { 3570 u32 ctrl_ext, swsm; 3571 3572 if (!adapter->has_manage) 3573 return; 3574 3575 if (adapter->hw.mac.type == e1000_82573) { 3576 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3577 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3578 swsm & ~E1000_SWSM_DRV_LOAD); 3579 return; 3580 } 3581 /* else */ 3582 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3583 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3584 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3585 return; 3586 } 3587 3588 static int 3589 em_is_valid_ether_addr(u8 *addr) 3590 { 3591 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3592 3593 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3594 return (FALSE); 3595 } 3596 3597 return (TRUE); 3598 } 3599 3600 /* 3601 ** Parse the interface capabilities with regard 3602 ** to both system management and wake-on-lan for 3603 ** later use. 3604 */ 3605 static void 3606 em_get_wakeup(if_ctx_t ctx) 3607 { 3608 struct adapter *adapter = iflib_get_softc(ctx); 3609 device_t dev = iflib_get_dev(ctx); 3610 u16 eeprom_data = 0, device_id, apme_mask; 3611 3612 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3613 apme_mask = EM_EEPROM_APME; 3614 3615 switch (adapter->hw.mac.type) { 3616 case e1000_82542: 3617 case e1000_82543: 3618 break; 3619 case e1000_82544: 3620 e1000_read_nvm(&adapter->hw, 3621 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3622 apme_mask = EM_82544_APME; 3623 break; 3624 case e1000_82546: 3625 case e1000_82546_rev_3: 3626 if (adapter->hw.bus.func == 1) { 3627 e1000_read_nvm(&adapter->hw, 3628 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3629 break; 3630 } else 3631 e1000_read_nvm(&adapter->hw, 3632 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3633 break; 3634 case e1000_82573: 3635 case e1000_82583: 3636 adapter->has_amt = TRUE; 3637 /* FALLTHROUGH */ 3638 case e1000_82571: 3639 case e1000_82572: 3640 case e1000_80003es2lan: 3641 if (adapter->hw.bus.func == 1) { 3642 e1000_read_nvm(&adapter->hw, 3643 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3644 break; 3645 } else 3646 e1000_read_nvm(&adapter->hw, 3647 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3648 break; 3649 case e1000_ich8lan: 3650 case e1000_ich9lan: 3651 case e1000_ich10lan: 3652 case e1000_pchlan: 3653 case e1000_pch2lan: 3654 case e1000_pch_lpt: 3655 case e1000_pch_spt: 3656 case e1000_82575: /* listing all igb devices */ 3657 case e1000_82576: 3658 case e1000_82580: 3659 case e1000_i350: 3660 case e1000_i354: 3661 case e1000_i210: 3662 case e1000_i211: 3663 case e1000_vfadapt: 3664 case e1000_vfadapt_i350: 3665 apme_mask = E1000_WUC_APME; 3666 adapter->has_amt = TRUE; 3667 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3668 break; 3669 default: 3670 e1000_read_nvm(&adapter->hw, 3671 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3672 break; 3673 } 3674 if (eeprom_data & apme_mask) 3675 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3676 /* 3677 * We have the eeprom settings, now apply the special cases 3678 * where the eeprom may be wrong or the board won't support 3679 * wake on lan on a particular port 3680 */ 3681 device_id = pci_get_device(dev); 3682 switch (device_id) { 3683 case E1000_DEV_ID_82546GB_PCIE: 3684 adapter->wol = 0; 3685 break; 3686 case E1000_DEV_ID_82546EB_FIBER: 3687 case E1000_DEV_ID_82546GB_FIBER: 3688 /* Wake events only supported on port A for dual fiber 3689 * regardless of eeprom setting */ 3690 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3691 E1000_STATUS_FUNC_1) 3692 adapter->wol = 0; 3693 break; 3694 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3695 /* if quad port adapter, disable WoL on all but port A */ 3696 if (global_quad_port_a != 0) 3697 adapter->wol = 0; 3698 /* Reset for multiple quad port adapters */ 3699 if (++global_quad_port_a == 4) 3700 global_quad_port_a = 0; 3701 break; 3702 case E1000_DEV_ID_82571EB_FIBER: 3703 /* Wake events only supported on port A for dual fiber 3704 * regardless of eeprom setting */ 3705 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3706 E1000_STATUS_FUNC_1) 3707 adapter->wol = 0; 3708 break; 3709 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3710 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3711 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3712 /* if quad port adapter, disable WoL on all but port A */ 3713 if (global_quad_port_a != 0) 3714 adapter->wol = 0; 3715 /* Reset for multiple quad port adapters */ 3716 if (++global_quad_port_a == 4) 3717 global_quad_port_a = 0; 3718 break; 3719 } 3720 return; 3721 } 3722 3723 3724 /* 3725 * Enable PCI Wake On Lan capability 3726 */ 3727 static void 3728 em_enable_wakeup(if_ctx_t ctx) 3729 { 3730 struct adapter *adapter = iflib_get_softc(ctx); 3731 device_t dev = iflib_get_dev(ctx); 3732 if_t ifp = iflib_get_ifp(ctx); 3733 int error = 0; 3734 u32 pmc, ctrl, ctrl_ext, rctl; 3735 u16 status; 3736 3737 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3738 return; 3739 3740 /* 3741 * Determine type of Wakeup: note that wol 3742 * is set with all bits on by default. 3743 */ 3744 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3745 adapter->wol &= ~E1000_WUFC_MAG; 3746 3747 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3748 adapter->wol &= ~E1000_WUFC_EX; 3749 3750 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3751 adapter->wol &= ~E1000_WUFC_MC; 3752 else { 3753 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3754 rctl |= E1000_RCTL_MPE; 3755 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3756 } 3757 3758 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3759 goto pme; 3760 3761 /* Advertise the wakeup capability */ 3762 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3763 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3764 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3765 3766 /* Keep the laser running on Fiber adapters */ 3767 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3768 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3769 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3770 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3771 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3772 } 3773 3774 if ((adapter->hw.mac.type == e1000_ich8lan) || 3775 (adapter->hw.mac.type == e1000_pchlan) || 3776 (adapter->hw.mac.type == e1000_ich9lan) || 3777 (adapter->hw.mac.type == e1000_ich10lan)) 3778 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3779 3780 if ( adapter->hw.mac.type >= e1000_pchlan) { 3781 error = em_enable_phy_wakeup(adapter); 3782 if (error) 3783 goto pme; 3784 } else { 3785 /* Enable wakeup by the MAC */ 3786 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3787 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3788 } 3789 3790 if (adapter->hw.phy.type == e1000_phy_igp_3) 3791 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3792 3793 pme: 3794 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3795 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3796 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3797 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3798 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3799 3800 return; 3801 } 3802 3803 /* 3804 * WOL in the newer chipset interfaces (pchlan) 3805 * require thing to be copied into the phy 3806 */ 3807 static int 3808 em_enable_phy_wakeup(struct adapter *adapter) 3809 { 3810 struct e1000_hw *hw = &adapter->hw; 3811 u32 mreg, ret = 0; 3812 u16 preg; 3813 3814 /* copy MAC RARs to PHY RARs */ 3815 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3816 3817 /* copy MAC MTA to PHY MTA */ 3818 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3819 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3820 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3821 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3822 (u16)((mreg >> 16) & 0xFFFF)); 3823 } 3824 3825 /* configure PHY Rx Control register */ 3826 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3827 mreg = E1000_READ_REG(hw, E1000_RCTL); 3828 if (mreg & E1000_RCTL_UPE) 3829 preg |= BM_RCTL_UPE; 3830 if (mreg & E1000_RCTL_MPE) 3831 preg |= BM_RCTL_MPE; 3832 preg &= ~(BM_RCTL_MO_MASK); 3833 if (mreg & E1000_RCTL_MO_3) 3834 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3835 << BM_RCTL_MO_SHIFT); 3836 if (mreg & E1000_RCTL_BAM) 3837 preg |= BM_RCTL_BAM; 3838 if (mreg & E1000_RCTL_PMCF) 3839 preg |= BM_RCTL_PMCF; 3840 mreg = E1000_READ_REG(hw, E1000_CTRL); 3841 if (mreg & E1000_CTRL_RFCE) 3842 preg |= BM_RCTL_RFCE; 3843 e1000_write_phy_reg(hw, BM_RCTL, preg); 3844 3845 /* enable PHY wakeup in MAC register */ 3846 E1000_WRITE_REG(hw, E1000_WUC, 3847 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3848 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3849 3850 /* configure and enable PHY wakeup in PHY registers */ 3851 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol); 3852 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3853 3854 /* activate PHY wakeup */ 3855 ret = hw->phy.ops.acquire(hw); 3856 if (ret) { 3857 printf("Could not acquire PHY\n"); 3858 return ret; 3859 } 3860 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3861 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3862 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3863 if (ret) { 3864 printf("Could not read PHY page 769\n"); 3865 goto out; 3866 } 3867 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3868 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3869 if (ret) 3870 printf("Could not set PHY Host Wakeup bit\n"); 3871 out: 3872 hw->phy.ops.release(hw); 3873 3874 return ret; 3875 } 3876 3877 static void 3878 em_if_led_func(if_ctx_t ctx, int onoff) 3879 { 3880 struct adapter *adapter = iflib_get_softc(ctx); 3881 3882 if (onoff) { 3883 e1000_setup_led(&adapter->hw); 3884 e1000_led_on(&adapter->hw); 3885 } else { 3886 e1000_led_off(&adapter->hw); 3887 e1000_cleanup_led(&adapter->hw); 3888 } 3889 } 3890 3891 /* 3892 * Disable the L0S and L1 LINK states 3893 */ 3894 static void 3895 em_disable_aspm(struct adapter *adapter) 3896 { 3897 int base, reg; 3898 u16 link_cap,link_ctrl; 3899 device_t dev = adapter->dev; 3900 3901 switch (adapter->hw.mac.type) { 3902 case e1000_82573: 3903 case e1000_82574: 3904 case e1000_82583: 3905 break; 3906 default: 3907 return; 3908 } 3909 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3910 return; 3911 reg = base + PCIER_LINK_CAP; 3912 link_cap = pci_read_config(dev, reg, 2); 3913 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3914 return; 3915 reg = base + PCIER_LINK_CTL; 3916 link_ctrl = pci_read_config(dev, reg, 2); 3917 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3918 pci_write_config(dev, reg, link_ctrl, 2); 3919 return; 3920 } 3921 3922 /********************************************************************** 3923 * 3924 * Update the board statistics counters. 3925 * 3926 **********************************************************************/ 3927 static void 3928 em_update_stats_counters(struct adapter *adapter) 3929 { 3930 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3931 3932 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3933 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3934 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3935 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3936 } 3937 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3938 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3939 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3940 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3941 3942 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3943 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3944 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3945 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3946 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3947 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3948 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3949 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3950 /* 3951 ** For watchdog management we need to know if we have been 3952 ** paused during the last interval, so capture that here. 3953 */ 3954 if (adapter->stats.xoffrxc != prev_xoffrxc) 3955 adapter->shared->isc_pause_frames = 1; 3956 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3957 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3958 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3959 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3960 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3961 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3962 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3963 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3964 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3965 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3966 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3967 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3968 3969 /* For the 64-bit byte counters the low dword must be read first. */ 3970 /* Both registers clear on the read of the high dword */ 3971 3972 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3973 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3974 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3975 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3976 3977 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3978 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3979 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3980 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3981 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3982 3983 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3984 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3985 3986 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3987 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3988 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3989 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3990 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3991 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3992 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3993 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3994 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3995 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3996 3997 /* Interrupt Counts */ 3998 3999 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 4000 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 4001 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 4002 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 4003 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 4004 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 4005 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 4006 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 4007 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 4008 4009 if (adapter->hw.mac.type >= e1000_82543) { 4010 adapter->stats.algnerrc += 4011 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4012 adapter->stats.rxerrc += 4013 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4014 adapter->stats.tncrs += 4015 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4016 adapter->stats.cexterr += 4017 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4018 adapter->stats.tsctc += 4019 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4020 adapter->stats.tsctfc += 4021 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4022 } 4023 } 4024 4025 static uint64_t 4026 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4027 { 4028 struct adapter *adapter = iflib_get_softc(ctx); 4029 struct ifnet *ifp = iflib_get_ifp(ctx); 4030 4031 switch (cnt) { 4032 case IFCOUNTER_COLLISIONS: 4033 return (adapter->stats.colc); 4034 case IFCOUNTER_IERRORS: 4035 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4036 adapter->stats.crcerrs + adapter->stats.algnerrc + 4037 adapter->stats.ruc + adapter->stats.roc + 4038 adapter->stats.mpc + adapter->stats.cexterr); 4039 case IFCOUNTER_OERRORS: 4040 return (adapter->stats.ecol + adapter->stats.latecol + 4041 adapter->watchdog_events); 4042 default: 4043 return (if_get_counter_default(ifp, cnt)); 4044 } 4045 } 4046 4047 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4048 * @ctx: iflib context 4049 * @event: event code to check 4050 * 4051 * Defaults to returning true for unknown events. 4052 * 4053 * @returns true if iflib needs to reinit the interface 4054 */ 4055 static bool 4056 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4057 { 4058 switch (event) { 4059 case IFLIB_RESTART_VLAN_CONFIG: 4060 default: 4061 return (true); 4062 } 4063 } 4064 4065 /* Export a single 32-bit register via a read-only sysctl. */ 4066 static int 4067 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4068 { 4069 struct adapter *adapter; 4070 u_int val; 4071 4072 adapter = oidp->oid_arg1; 4073 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4074 return (sysctl_handle_int(oidp, &val, 0, req)); 4075 } 4076 4077 /* 4078 * Add sysctl variables, one per statistic, to the system. 4079 */ 4080 static void 4081 em_add_hw_stats(struct adapter *adapter) 4082 { 4083 device_t dev = iflib_get_dev(adapter->ctx); 4084 struct em_tx_queue *tx_que = adapter->tx_queues; 4085 struct em_rx_queue *rx_que = adapter->rx_queues; 4086 4087 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4088 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4089 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4090 struct e1000_hw_stats *stats = &adapter->stats; 4091 4092 struct sysctl_oid *stat_node, *queue_node, *int_node; 4093 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4094 4095 #define QUEUE_NAME_LEN 32 4096 char namebuf[QUEUE_NAME_LEN]; 4097 4098 /* Driver Statistics */ 4099 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4100 CTLFLAG_RD, &adapter->dropped_pkts, 4101 "Driver dropped packets"); 4102 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4103 CTLFLAG_RD, &adapter->link_irq, 4104 "Link MSI-X IRQ Handled"); 4105 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4106 CTLFLAG_RD, &adapter->rx_overruns, 4107 "RX overruns"); 4108 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4109 CTLFLAG_RD, &adapter->watchdog_events, 4110 "Watchdog timeouts"); 4111 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4112 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4113 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4114 "Device Control Register"); 4115 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4116 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4117 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4118 "Receiver Control Register"); 4119 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4120 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4121 "Flow Control High Watermark"); 4122 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4123 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4124 "Flow Control Low Watermark"); 4125 4126 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4127 struct tx_ring *txr = &tx_que->txr; 4128 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4129 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4130 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4131 queue_list = SYSCTL_CHILDREN(queue_node); 4132 4133 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4134 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4135 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4136 "Transmit Descriptor Head"); 4137 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4138 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4139 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4140 "Transmit Descriptor Tail"); 4141 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4142 CTLFLAG_RD, &txr->tx_irq, 4143 "Queue MSI-X Transmit Interrupts"); 4144 } 4145 4146 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4147 struct rx_ring *rxr = &rx_que->rxr; 4148 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4149 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4150 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4151 queue_list = SYSCTL_CHILDREN(queue_node); 4152 4153 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4154 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4155 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4156 "Receive Descriptor Head"); 4157 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4158 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4159 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4160 "Receive Descriptor Tail"); 4161 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4162 CTLFLAG_RD, &rxr->rx_irq, 4163 "Queue MSI-X Receive Interrupts"); 4164 } 4165 4166 /* MAC stats get their own sub node */ 4167 4168 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4169 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4170 stat_list = SYSCTL_CHILDREN(stat_node); 4171 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4173 CTLFLAG_RD, &stats->ecol, 4174 "Excessive collisions"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4176 CTLFLAG_RD, &stats->scc, 4177 "Single collisions"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4179 CTLFLAG_RD, &stats->mcc, 4180 "Multiple collisions"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4182 CTLFLAG_RD, &stats->latecol, 4183 "Late collisions"); 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4185 CTLFLAG_RD, &stats->colc, 4186 "Collision Count"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4188 CTLFLAG_RD, &adapter->stats.symerrs, 4189 "Symbol Errors"); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4191 CTLFLAG_RD, &adapter->stats.sec, 4192 "Sequence Errors"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4194 CTLFLAG_RD, &adapter->stats.dc, 4195 "Defer Count"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4197 CTLFLAG_RD, &adapter->stats.mpc, 4198 "Missed Packets"); 4199 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4200 CTLFLAG_RD, &adapter->stats.rnbc, 4201 "Receive No Buffers"); 4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4203 CTLFLAG_RD, &adapter->stats.ruc, 4204 "Receive Undersize"); 4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4206 CTLFLAG_RD, &adapter->stats.rfc, 4207 "Fragmented Packets Received "); 4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4209 CTLFLAG_RD, &adapter->stats.roc, 4210 "Oversized Packets Received"); 4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4212 CTLFLAG_RD, &adapter->stats.rjc, 4213 "Recevied Jabber"); 4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4215 CTLFLAG_RD, &adapter->stats.rxerrc, 4216 "Receive Errors"); 4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4218 CTLFLAG_RD, &adapter->stats.crcerrs, 4219 "CRC errors"); 4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4221 CTLFLAG_RD, &adapter->stats.algnerrc, 4222 "Alignment Errors"); 4223 /* On 82575 these are collision counts */ 4224 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4225 CTLFLAG_RD, &adapter->stats.cexterr, 4226 "Collision/Carrier extension errors"); 4227 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4228 CTLFLAG_RD, &adapter->stats.xonrxc, 4229 "XON Received"); 4230 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4231 CTLFLAG_RD, &adapter->stats.xontxc, 4232 "XON Transmitted"); 4233 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4234 CTLFLAG_RD, &adapter->stats.xoffrxc, 4235 "XOFF Received"); 4236 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4237 CTLFLAG_RD, &adapter->stats.xofftxc, 4238 "XOFF Transmitted"); 4239 4240 /* Packet Reception Stats */ 4241 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4242 CTLFLAG_RD, &adapter->stats.tpr, 4243 "Total Packets Received "); 4244 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4245 CTLFLAG_RD, &adapter->stats.gprc, 4246 "Good Packets Received"); 4247 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4248 CTLFLAG_RD, &adapter->stats.bprc, 4249 "Broadcast Packets Received"); 4250 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4251 CTLFLAG_RD, &adapter->stats.mprc, 4252 "Multicast Packets Received"); 4253 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4254 CTLFLAG_RD, &adapter->stats.prc64, 4255 "64 byte frames received "); 4256 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4257 CTLFLAG_RD, &adapter->stats.prc127, 4258 "65-127 byte frames received"); 4259 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4260 CTLFLAG_RD, &adapter->stats.prc255, 4261 "128-255 byte frames received"); 4262 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4263 CTLFLAG_RD, &adapter->stats.prc511, 4264 "256-511 byte frames received"); 4265 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4266 CTLFLAG_RD, &adapter->stats.prc1023, 4267 "512-1023 byte frames received"); 4268 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4269 CTLFLAG_RD, &adapter->stats.prc1522, 4270 "1023-1522 byte frames received"); 4271 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4272 CTLFLAG_RD, &adapter->stats.gorc, 4273 "Good Octets Received"); 4274 4275 /* Packet Transmission Stats */ 4276 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4277 CTLFLAG_RD, &adapter->stats.gotc, 4278 "Good Octets Transmitted"); 4279 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4280 CTLFLAG_RD, &adapter->stats.tpt, 4281 "Total Packets Transmitted"); 4282 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4283 CTLFLAG_RD, &adapter->stats.gptc, 4284 "Good Packets Transmitted"); 4285 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4286 CTLFLAG_RD, &adapter->stats.bptc, 4287 "Broadcast Packets Transmitted"); 4288 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4289 CTLFLAG_RD, &adapter->stats.mptc, 4290 "Multicast Packets Transmitted"); 4291 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4292 CTLFLAG_RD, &adapter->stats.ptc64, 4293 "64 byte frames transmitted "); 4294 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4295 CTLFLAG_RD, &adapter->stats.ptc127, 4296 "65-127 byte frames transmitted"); 4297 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4298 CTLFLAG_RD, &adapter->stats.ptc255, 4299 "128-255 byte frames transmitted"); 4300 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4301 CTLFLAG_RD, &adapter->stats.ptc511, 4302 "256-511 byte frames transmitted"); 4303 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4304 CTLFLAG_RD, &adapter->stats.ptc1023, 4305 "512-1023 byte frames transmitted"); 4306 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4307 CTLFLAG_RD, &adapter->stats.ptc1522, 4308 "1024-1522 byte frames transmitted"); 4309 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4310 CTLFLAG_RD, &adapter->stats.tsctc, 4311 "TSO Contexts Transmitted"); 4312 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4313 CTLFLAG_RD, &adapter->stats.tsctfc, 4314 "TSO Contexts Failed"); 4315 4316 4317 /* Interrupt Stats */ 4318 4319 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4320 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4321 int_list = SYSCTL_CHILDREN(int_node); 4322 4323 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4324 CTLFLAG_RD, &adapter->stats.iac, 4325 "Interrupt Assertion Count"); 4326 4327 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4328 CTLFLAG_RD, &adapter->stats.icrxptc, 4329 "Interrupt Cause Rx Pkt Timer Expire Count"); 4330 4331 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4332 CTLFLAG_RD, &adapter->stats.icrxatc, 4333 "Interrupt Cause Rx Abs Timer Expire Count"); 4334 4335 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4336 CTLFLAG_RD, &adapter->stats.ictxptc, 4337 "Interrupt Cause Tx Pkt Timer Expire Count"); 4338 4339 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4340 CTLFLAG_RD, &adapter->stats.ictxatc, 4341 "Interrupt Cause Tx Abs Timer Expire Count"); 4342 4343 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4344 CTLFLAG_RD, &adapter->stats.ictxqec, 4345 "Interrupt Cause Tx Queue Empty Count"); 4346 4347 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4348 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4349 "Interrupt Cause Tx Queue Min Thresh Count"); 4350 4351 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4352 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4353 "Interrupt Cause Rx Desc Min Thresh Count"); 4354 4355 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4356 CTLFLAG_RD, &adapter->stats.icrxoc, 4357 "Interrupt Cause Receiver Overrun Count"); 4358 } 4359 4360 /********************************************************************** 4361 * 4362 * This routine provides a way to dump out the adapter eeprom, 4363 * often a useful debug/service tool. This only dumps the first 4364 * 32 words, stuff that matters is in that extent. 4365 * 4366 **********************************************************************/ 4367 static int 4368 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4369 { 4370 struct adapter *adapter = (struct adapter *)arg1; 4371 int error; 4372 int result; 4373 4374 result = -1; 4375 error = sysctl_handle_int(oidp, &result, 0, req); 4376 4377 if (error || !req->newptr) 4378 return (error); 4379 4380 /* 4381 * This value will cause a hex dump of the 4382 * first 32 16-bit words of the EEPROM to 4383 * the screen. 4384 */ 4385 if (result == 1) 4386 em_print_nvm_info(adapter); 4387 4388 return (error); 4389 } 4390 4391 static void 4392 em_print_nvm_info(struct adapter *adapter) 4393 { 4394 u16 eeprom_data; 4395 int i, j, row = 0; 4396 4397 /* Its a bit crude, but it gets the job done */ 4398 printf("\nInterface EEPROM Dump:\n"); 4399 printf("Offset\n0x0000 "); 4400 for (i = 0, j = 0; i < 32; i++, j++) { 4401 if (j == 8) { /* Make the offset block */ 4402 j = 0; ++row; 4403 printf("\n0x00%x0 ",row); 4404 } 4405 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4406 printf("%04x ", eeprom_data); 4407 } 4408 printf("\n"); 4409 } 4410 4411 static int 4412 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4413 { 4414 struct em_int_delay_info *info; 4415 struct adapter *adapter; 4416 u32 regval; 4417 int error, usecs, ticks; 4418 4419 info = (struct em_int_delay_info *) arg1; 4420 usecs = info->value; 4421 error = sysctl_handle_int(oidp, &usecs, 0, req); 4422 if (error != 0 || req->newptr == NULL) 4423 return (error); 4424 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4425 return (EINVAL); 4426 info->value = usecs; 4427 ticks = EM_USECS_TO_TICKS(usecs); 4428 if (info->offset == E1000_ITR) /* units are 256ns here */ 4429 ticks *= 4; 4430 4431 adapter = info->adapter; 4432 4433 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4434 regval = (regval & ~0xffff) | (ticks & 0xffff); 4435 /* Handle a few special cases. */ 4436 switch (info->offset) { 4437 case E1000_RDTR: 4438 break; 4439 case E1000_TIDV: 4440 if (ticks == 0) { 4441 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4442 /* Don't write 0 into the TIDV register. */ 4443 regval++; 4444 } else 4445 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4446 break; 4447 } 4448 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4449 return (0); 4450 } 4451 4452 static void 4453 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4454 const char *description, struct em_int_delay_info *info, 4455 int offset, int value) 4456 { 4457 info->adapter = adapter; 4458 info->offset = offset; 4459 info->value = value; 4460 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4461 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4462 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4463 info, 0, em_sysctl_int_delay, "I", description); 4464 } 4465 4466 /* 4467 * Set flow control using sysctl: 4468 * Flow control values: 4469 * 0 - off 4470 * 1 - rx pause 4471 * 2 - tx pause 4472 * 3 - full 4473 */ 4474 static int 4475 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4476 { 4477 int error; 4478 static int input = 3; /* default is full */ 4479 struct adapter *adapter = (struct adapter *) arg1; 4480 4481 error = sysctl_handle_int(oidp, &input, 0, req); 4482 4483 if ((error) || (req->newptr == NULL)) 4484 return (error); 4485 4486 if (input == adapter->fc) /* no change? */ 4487 return (error); 4488 4489 switch (input) { 4490 case e1000_fc_rx_pause: 4491 case e1000_fc_tx_pause: 4492 case e1000_fc_full: 4493 case e1000_fc_none: 4494 adapter->hw.fc.requested_mode = input; 4495 adapter->fc = input; 4496 break; 4497 default: 4498 /* Do nothing */ 4499 return (error); 4500 } 4501 4502 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4503 e1000_force_mac_fc(&adapter->hw); 4504 return (error); 4505 } 4506 4507 /* 4508 * Manage Energy Efficient Ethernet: 4509 * Control values: 4510 * 0/1 - enabled/disabled 4511 */ 4512 static int 4513 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4514 { 4515 struct adapter *adapter = (struct adapter *) arg1; 4516 int error, value; 4517 4518 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4519 error = sysctl_handle_int(oidp, &value, 0, req); 4520 if (error || req->newptr == NULL) 4521 return (error); 4522 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4523 em_if_init(adapter->ctx); 4524 4525 return (0); 4526 } 4527 4528 static int 4529 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4530 { 4531 struct adapter *adapter; 4532 int error; 4533 int result; 4534 4535 result = -1; 4536 error = sysctl_handle_int(oidp, &result, 0, req); 4537 4538 if (error || !req->newptr) 4539 return (error); 4540 4541 if (result == 1) { 4542 adapter = (struct adapter *) arg1; 4543 em_print_debug_info(adapter); 4544 } 4545 4546 return (error); 4547 } 4548 4549 static int 4550 em_get_rs(SYSCTL_HANDLER_ARGS) 4551 { 4552 struct adapter *adapter = (struct adapter *) arg1; 4553 int error; 4554 int result; 4555 4556 result = 0; 4557 error = sysctl_handle_int(oidp, &result, 0, req); 4558 4559 if (error || !req->newptr || result != 1) 4560 return (error); 4561 em_dump_rs(adapter); 4562 4563 return (error); 4564 } 4565 4566 static void 4567 em_if_debug(if_ctx_t ctx) 4568 { 4569 em_dump_rs(iflib_get_softc(ctx)); 4570 } 4571 4572 /* 4573 * This routine is meant to be fluid, add whatever is 4574 * needed for debugging a problem. -jfv 4575 */ 4576 static void 4577 em_print_debug_info(struct adapter *adapter) 4578 { 4579 device_t dev = iflib_get_dev(adapter->ctx); 4580 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4581 struct tx_ring *txr = &adapter->tx_queues->txr; 4582 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4583 4584 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4585 printf("Interface is RUNNING "); 4586 else 4587 printf("Interface is NOT RUNNING\n"); 4588 4589 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4590 printf("and INACTIVE\n"); 4591 else 4592 printf("and ACTIVE\n"); 4593 4594 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4595 device_printf(dev, "TX Queue %d ------\n", i); 4596 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4597 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4598 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4599 4600 } 4601 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4602 device_printf(dev, "RX Queue %d ------\n", j); 4603 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4604 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4605 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4606 } 4607 } 4608 4609 /* 4610 * 82574 only: 4611 * Write a new value to the EEPROM increasing the number of MSI-X 4612 * vectors from 3 to 5, for proper multiqueue support. 4613 */ 4614 static void 4615 em_enable_vectors_82574(if_ctx_t ctx) 4616 { 4617 struct adapter *adapter = iflib_get_softc(ctx); 4618 struct e1000_hw *hw = &adapter->hw; 4619 device_t dev = iflib_get_dev(ctx); 4620 u16 edata; 4621 4622 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4623 if (bootverbose) 4624 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4625 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4626 device_printf(dev, "Writing to eeprom: increasing " 4627 "reported MSI-X vectors from 3 to 5...\n"); 4628 edata &= ~(EM_NVM_MSIX_N_MASK); 4629 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4630 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4631 e1000_update_nvm_checksum(hw); 4632 device_printf(dev, "Writing to eeprom: done\n"); 4633 } 4634 } 4635