1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 334 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 335 const char *, struct em_int_delay_info *, int, int); 336 /* Management and WOL Support */ 337 static void em_init_manageability(struct e1000_softc *); 338 static void em_release_manageability(struct e1000_softc *); 339 static void em_get_hw_control(struct e1000_softc *); 340 static void em_release_hw_control(struct e1000_softc *); 341 static void em_get_wakeup(if_ctx_t); 342 static void em_enable_wakeup(if_ctx_t); 343 static int em_enable_phy_wakeup(struct e1000_softc *); 344 static void em_disable_aspm(struct e1000_softc *); 345 346 int em_intr(void *); 347 348 /* MSI-X handlers */ 349 static int em_if_msix_intr_assign(if_ctx_t, int); 350 static int em_msix_link(void *); 351 static void em_handle_link(void *); 352 353 static void em_enable_vectors_82574(if_ctx_t); 354 355 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 356 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 357 static void em_if_led_func(if_ctx_t, int); 358 359 static int em_get_regs(SYSCTL_HANDLER_ARGS); 360 361 static void lem_smartspeed(struct e1000_softc *); 362 static void igb_configure_queues(struct e1000_softc *); 363 static void em_flush_desc_rings(struct e1000_softc *); 364 365 366 /********************************************************************* 367 * FreeBSD Device Interface Entry Points 368 *********************************************************************/ 369 static device_method_t em_methods[] = { 370 /* Device interface */ 371 DEVMETHOD(device_register, em_register), 372 DEVMETHOD(device_probe, iflib_device_probe), 373 DEVMETHOD(device_attach, iflib_device_attach), 374 DEVMETHOD(device_detach, iflib_device_detach), 375 DEVMETHOD(device_shutdown, iflib_device_shutdown), 376 DEVMETHOD(device_suspend, iflib_device_suspend), 377 DEVMETHOD(device_resume, iflib_device_resume), 378 DEVMETHOD_END 379 }; 380 381 static device_method_t igb_methods[] = { 382 /* Device interface */ 383 DEVMETHOD(device_register, igb_register), 384 DEVMETHOD(device_probe, iflib_device_probe), 385 DEVMETHOD(device_attach, iflib_device_attach), 386 DEVMETHOD(device_detach, iflib_device_detach), 387 DEVMETHOD(device_shutdown, iflib_device_shutdown), 388 DEVMETHOD(device_suspend, iflib_device_suspend), 389 DEVMETHOD(device_resume, iflib_device_resume), 390 DEVMETHOD_END 391 }; 392 393 394 static driver_t em_driver = { 395 "em", em_methods, sizeof(struct e1000_softc), 396 }; 397 398 DRIVER_MODULE(em, pci, em_driver, 0, 0); 399 400 MODULE_DEPEND(em, pci, 1, 1, 1); 401 MODULE_DEPEND(em, ether, 1, 1, 1); 402 MODULE_DEPEND(em, iflib, 1, 1, 1); 403 404 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 405 406 static driver_t igb_driver = { 407 "igb", igb_methods, sizeof(struct e1000_softc), 408 }; 409 410 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 411 412 MODULE_DEPEND(igb, pci, 1, 1, 1); 413 MODULE_DEPEND(igb, ether, 1, 1, 1); 414 MODULE_DEPEND(igb, iflib, 1, 1, 1); 415 416 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 417 418 static device_method_t em_if_methods[] = { 419 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 420 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 421 DEVMETHOD(ifdi_detach, em_if_detach), 422 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 423 DEVMETHOD(ifdi_suspend, em_if_suspend), 424 DEVMETHOD(ifdi_resume, em_if_resume), 425 DEVMETHOD(ifdi_init, em_if_init), 426 DEVMETHOD(ifdi_stop, em_if_stop), 427 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 428 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 429 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 430 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 431 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 432 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 433 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 434 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 435 DEVMETHOD(ifdi_media_status, em_if_media_status), 436 DEVMETHOD(ifdi_media_change, em_if_media_change), 437 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 438 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 439 DEVMETHOD(ifdi_timer, em_if_timer), 440 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 441 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 442 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 443 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 444 DEVMETHOD(ifdi_led_func, em_if_led_func), 445 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 446 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 447 DEVMETHOD(ifdi_debug, em_if_debug), 448 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 449 DEVMETHOD_END 450 }; 451 452 static driver_t em_if_driver = { 453 "em_if", em_if_methods, sizeof(struct e1000_softc) 454 }; 455 456 static device_method_t igb_if_methods[] = { 457 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 458 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 459 DEVMETHOD(ifdi_detach, em_if_detach), 460 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 461 DEVMETHOD(ifdi_suspend, em_if_suspend), 462 DEVMETHOD(ifdi_resume, em_if_resume), 463 DEVMETHOD(ifdi_init, em_if_init), 464 DEVMETHOD(ifdi_stop, em_if_stop), 465 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 466 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 467 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 468 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 469 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 470 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 471 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 472 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 473 DEVMETHOD(ifdi_media_status, em_if_media_status), 474 DEVMETHOD(ifdi_media_change, em_if_media_change), 475 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 476 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 477 DEVMETHOD(ifdi_timer, em_if_timer), 478 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 479 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 480 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 481 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 482 DEVMETHOD(ifdi_led_func, em_if_led_func), 483 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 484 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 485 DEVMETHOD(ifdi_debug, em_if_debug), 486 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 487 DEVMETHOD_END 488 }; 489 490 static driver_t igb_if_driver = { 491 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 492 }; 493 494 /********************************************************************* 495 * Tunable default values. 496 *********************************************************************/ 497 498 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 499 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 500 501 #define MAX_INTS_PER_SEC 8000 502 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 503 504 /* Allow common code without TSO */ 505 #ifndef CSUM_TSO 506 #define CSUM_TSO 0 507 #endif 508 509 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 510 "EM driver parameters"); 511 512 static int em_disable_crc_stripping = 0; 513 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 514 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 515 516 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 517 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 518 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 519 0, "Default transmit interrupt delay in usecs"); 520 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 521 0, "Default receive interrupt delay in usecs"); 522 523 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 524 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 525 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 526 &em_tx_abs_int_delay_dflt, 0, 527 "Default transmit interrupt delay limit in usecs"); 528 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 529 &em_rx_abs_int_delay_dflt, 0, 530 "Default receive interrupt delay limit in usecs"); 531 532 static int em_smart_pwr_down = false; 533 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 534 0, "Set to true to leave smart power down enabled on newer adapters"); 535 536 /* Controls whether promiscuous also shows bad packets */ 537 static int em_debug_sbp = false; 538 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 539 "Show bad packets in promiscuous mode"); 540 541 /* How many packets rxeof tries to clean at a time */ 542 static int em_rx_process_limit = 100; 543 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 544 &em_rx_process_limit, 0, 545 "Maximum number of received packets to process " 546 "at a time, -1 means unlimited"); 547 548 /* Energy efficient ethernet - default to OFF */ 549 static int eee_setting = 1; 550 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 551 "Enable Energy Efficient Ethernet"); 552 553 /* 554 ** Tuneable Interrupt rate 555 */ 556 static int em_max_interrupt_rate = 8000; 557 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 558 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 559 560 561 562 /* Global used in WOL setup with multiport cards */ 563 static int global_quad_port_a = 0; 564 565 extern struct if_txrx igb_txrx; 566 extern struct if_txrx em_txrx; 567 extern struct if_txrx lem_txrx; 568 569 static struct if_shared_ctx em_sctx_init = { 570 .isc_magic = IFLIB_MAGIC, 571 .isc_q_align = PAGE_SIZE, 572 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 573 .isc_tx_maxsegsize = PAGE_SIZE, 574 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 575 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 576 .isc_rx_maxsize = MJUM9BYTES, 577 .isc_rx_nsegments = 1, 578 .isc_rx_maxsegsize = MJUM9BYTES, 579 .isc_nfl = 1, 580 .isc_nrxqs = 1, 581 .isc_ntxqs = 1, 582 .isc_admin_intrcnt = 1, 583 .isc_vendor_info = em_vendor_info_array, 584 .isc_driver_version = em_driver_version, 585 .isc_driver = &em_if_driver, 586 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 587 588 .isc_nrxd_min = {EM_MIN_RXD}, 589 .isc_ntxd_min = {EM_MIN_TXD}, 590 .isc_nrxd_max = {EM_MAX_RXD}, 591 .isc_ntxd_max = {EM_MAX_TXD}, 592 .isc_nrxd_default = {EM_DEFAULT_RXD}, 593 .isc_ntxd_default = {EM_DEFAULT_TXD}, 594 }; 595 596 static struct if_shared_ctx igb_sctx_init = { 597 .isc_magic = IFLIB_MAGIC, 598 .isc_q_align = PAGE_SIZE, 599 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 600 .isc_tx_maxsegsize = PAGE_SIZE, 601 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 602 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 603 .isc_rx_maxsize = MJUM9BYTES, 604 .isc_rx_nsegments = 1, 605 .isc_rx_maxsegsize = MJUM9BYTES, 606 .isc_nfl = 1, 607 .isc_nrxqs = 1, 608 .isc_ntxqs = 1, 609 .isc_admin_intrcnt = 1, 610 .isc_vendor_info = igb_vendor_info_array, 611 .isc_driver_version = igb_driver_version, 612 .isc_driver = &igb_if_driver, 613 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 614 615 .isc_nrxd_min = {EM_MIN_RXD}, 616 .isc_ntxd_min = {EM_MIN_TXD}, 617 .isc_nrxd_max = {IGB_MAX_RXD}, 618 .isc_ntxd_max = {IGB_MAX_TXD}, 619 .isc_nrxd_default = {EM_DEFAULT_RXD}, 620 .isc_ntxd_default = {EM_DEFAULT_TXD}, 621 }; 622 623 /***************************************************************** 624 * 625 * Dump Registers 626 * 627 ****************************************************************/ 628 #define IGB_REGS_LEN 739 629 630 static int em_get_regs(SYSCTL_HANDLER_ARGS) 631 { 632 struct e1000_softc *sc = (struct e1000_softc *)arg1; 633 struct e1000_hw *hw = &sc->hw; 634 struct sbuf *sb; 635 u32 *regs_buff; 636 int rc; 637 638 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 639 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 640 641 rc = sysctl_wire_old_buffer(req, 0); 642 MPASS(rc == 0); 643 if (rc != 0) { 644 free(regs_buff, M_DEVBUF); 645 return (rc); 646 } 647 648 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 649 MPASS(sb != NULL); 650 if (sb == NULL) { 651 free(regs_buff, M_DEVBUF); 652 return (ENOMEM); 653 } 654 655 /* General Registers */ 656 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 657 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 658 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 659 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 660 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 661 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 662 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 663 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 664 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 665 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 666 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 667 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 668 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 669 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 670 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 671 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 672 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 673 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 674 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 675 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 676 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 677 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 678 679 sbuf_printf(sb, "General Registers\n"); 680 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 681 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 682 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 683 684 sbuf_printf(sb, "Interrupt Registers\n"); 685 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 686 687 sbuf_printf(sb, "RX Registers\n"); 688 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 689 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 690 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 691 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 692 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 693 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 694 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 695 696 sbuf_printf(sb, "TX Registers\n"); 697 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 698 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 699 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 700 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 701 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 702 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 703 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 704 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 705 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 706 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 707 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 708 709 free(regs_buff, M_DEVBUF); 710 711 #ifdef DUMP_DESCS 712 { 713 if_softc_ctx_t scctx = sc->shared; 714 struct rx_ring *rxr = &rx_que->rxr; 715 struct tx_ring *txr = &tx_que->txr; 716 int ntxd = scctx->isc_ntxd[0]; 717 int nrxd = scctx->isc_nrxd[0]; 718 int j; 719 720 for (j = 0; j < nrxd; j++) { 721 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 722 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 723 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 724 } 725 726 for (j = 0; j < min(ntxd, 256); j++) { 727 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 728 729 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 730 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 731 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 732 733 } 734 } 735 #endif 736 737 rc = sbuf_finish(sb); 738 sbuf_delete(sb); 739 return(rc); 740 } 741 742 static void * 743 em_register(device_t dev) 744 { 745 return (&em_sctx_init); 746 } 747 748 static void * 749 igb_register(device_t dev) 750 { 751 return (&igb_sctx_init); 752 } 753 754 static int 755 em_set_num_queues(if_ctx_t ctx) 756 { 757 struct e1000_softc *sc = iflib_get_softc(ctx); 758 int maxqueues; 759 760 /* Sanity check based on HW */ 761 switch (sc->hw.mac.type) { 762 case e1000_82576: 763 case e1000_82580: 764 case e1000_i350: 765 case e1000_i354: 766 maxqueues = 8; 767 break; 768 case e1000_i210: 769 case e1000_82575: 770 maxqueues = 4; 771 break; 772 case e1000_i211: 773 case e1000_82574: 774 maxqueues = 2; 775 break; 776 default: 777 maxqueues = 1; 778 break; 779 } 780 781 return (maxqueues); 782 } 783 784 #define LEM_CAPS \ 785 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 786 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 787 IFCAP_LRO | IFCAP_VLAN_HWTSO| IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 788 IFCAP_TSO6 789 790 #define EM_CAPS \ 791 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 792 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 793 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 794 IFCAP_TSO6 795 796 #define IGB_CAPS \ 797 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 798 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 799 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 800 IFCAP_TSO6 801 802 /********************************************************************* 803 * Device initialization routine 804 * 805 * The attach entry point is called when the driver is being loaded. 806 * This routine identifies the type of hardware, allocates all resources 807 * and initializes the hardware. 808 * 809 * return 0 on success, positive on failure 810 *********************************************************************/ 811 static int 812 em_if_attach_pre(if_ctx_t ctx) 813 { 814 struct e1000_softc *sc; 815 if_softc_ctx_t scctx; 816 device_t dev; 817 struct e1000_hw *hw; 818 struct sysctl_oid_list *child; 819 struct sysctl_ctx_list *ctx_list; 820 int error = 0; 821 822 INIT_DEBUGOUT("em_if_attach_pre: begin"); 823 dev = iflib_get_dev(ctx); 824 sc = iflib_get_softc(ctx); 825 826 sc->ctx = sc->osdep.ctx = ctx; 827 sc->dev = sc->osdep.dev = dev; 828 scctx = sc->shared = iflib_get_softc_ctx(ctx); 829 sc->media = iflib_get_media(ctx); 830 hw = &sc->hw; 831 832 sc->tx_process_limit = scctx->isc_ntxd[0]; 833 834 /* Determine hardware and mac info */ 835 em_identify_hardware(ctx); 836 837 /* SYSCTL stuff */ 838 ctx_list = device_get_sysctl_ctx(dev); 839 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 840 841 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 842 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 843 em_sysctl_nvm_info, "I", "NVM Information"); 844 845 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 846 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 847 em_sysctl_print_fw_version, "A", 848 "Prints FW/NVM Versions"); 849 850 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 851 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 852 em_sysctl_debug_info, "I", "Debug Information"); 853 854 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 855 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 856 em_set_flowcntl, "I", "Flow Control"); 857 858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 859 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 860 em_get_regs, "A", "Dump Registers"); 861 862 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 863 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 864 em_get_rs, "I", "Dump RS indexes"); 865 866 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 867 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 868 if (bootverbose) 869 device_printf(dev, "attach_pre capping queues at %d\n", 870 scctx->isc_ntxqsets_max); 871 872 if (hw->mac.type >= igb_mac_min) { 873 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 874 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 875 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 876 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 877 scctx->isc_txrx = &igb_txrx; 878 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 879 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 880 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 881 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 882 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 883 CSUM_IP6_TCP | CSUM_IP6_UDP; 884 if (hw->mac.type != e1000_82575) 885 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 886 /* 887 ** Some new devices, as with ixgbe, now may 888 ** use a different BAR, so we need to keep 889 ** track of which is used. 890 */ 891 scctx->isc_msix_bar = pci_msix_table_bar(dev); 892 } else if (hw->mac.type >= em_mac_min) { 893 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 894 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 895 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 896 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 897 scctx->isc_txrx = &em_txrx; 898 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 899 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 900 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 901 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 902 /* 903 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO,TSO6} 904 * by default as we don't have workarounds for all associated 905 * silicon errata. E. g., with several MACs such as 82573E, 906 * TSO only works at Gigabit speed and otherwise can cause the 907 * hardware to hang (which also would be next to impossible to 908 * work around given that already queued TSO-using descriptors 909 * would need to be flushed and vlan(4) reconfigured at runtime 910 * in case of a link speed change). Moreover, MACs like 82579 911 * still can hang at Gigabit even with all publicly documented 912 * TSO workarounds implemented. Generally, the penality of 913 * these workarounds is rather high and may involve copying 914 * mbuf data around so advantages of TSO lapse. Still, TSO may 915 * work for a few MACs of this class - at least when sticking 916 * with Gigabit - in which case users may enable TSO manually. 917 */ 918 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO | IFCAP_TSO6); 919 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 920 CSUM_IP6_TCP | CSUM_IP6_UDP; 921 /* 922 * We support MSI-X with 82574 only, but indicate to iflib(4) 923 * that it shall give MSI at least a try with other devices. 924 */ 925 if (hw->mac.type == e1000_82574) { 926 scctx->isc_msix_bar = pci_msix_table_bar(dev); 927 } else { 928 scctx->isc_msix_bar = -1; 929 scctx->isc_disable_msix = 1; 930 } 931 } else { 932 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 933 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 934 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 935 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 936 scctx->isc_txrx = &lem_txrx; 937 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 938 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 939 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 940 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 941 /* 942 * For LEM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO,TSO6} 943 * by default as we don't have workarounds for all associated 944 * silicon errata. TSO4 may work on > 82544 but its status 945 * is unknown by the authors. Please report any success or failures. 946 */ 947 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO | IFCAP_TSO6); 948 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 949 CSUM_IP6_TCP | CSUM_IP6_UDP; 950 951 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 952 if (hw->mac.type == e1000_82542 || hw->mac.type == e1000_82547 || 953 hw->mac.type == e1000_82547_rev_2) 954 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 955 IFCAP_HWCSUM_IPV6); 956 /* 82541ER doesn't do HW tagging */ 957 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 958 scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING; 959 /* INTx only */ 960 scctx->isc_msix_bar = 0; 961 } 962 963 /* Setup PCI resources */ 964 if (em_allocate_pci_resources(ctx)) { 965 device_printf(dev, "Allocation of PCI resources failed\n"); 966 error = ENXIO; 967 goto err_pci; 968 } 969 970 /* 971 ** For ICH8 and family we need to 972 ** map the flash memory, and this 973 ** must happen after the MAC is 974 ** identified 975 */ 976 if ((hw->mac.type == e1000_ich8lan) || 977 (hw->mac.type == e1000_ich9lan) || 978 (hw->mac.type == e1000_ich10lan) || 979 (hw->mac.type == e1000_pchlan) || 980 (hw->mac.type == e1000_pch2lan) || 981 (hw->mac.type == e1000_pch_lpt)) { 982 int rid = EM_BAR_TYPE_FLASH; 983 sc->flash = bus_alloc_resource_any(dev, 984 SYS_RES_MEMORY, &rid, RF_ACTIVE); 985 if (sc->flash == NULL) { 986 device_printf(dev, "Mapping of Flash failed\n"); 987 error = ENXIO; 988 goto err_pci; 989 } 990 /* This is used in the shared code */ 991 hw->flash_address = (u8 *)sc->flash; 992 sc->osdep.flash_bus_space_tag = 993 rman_get_bustag(sc->flash); 994 sc->osdep.flash_bus_space_handle = 995 rman_get_bushandle(sc->flash); 996 } 997 /* 998 ** In the new SPT device flash is not a 999 ** separate BAR, rather it is also in BAR0, 1000 ** so use the same tag and an offset handle for the 1001 ** FLASH read/write macros in the shared code. 1002 */ 1003 else if (hw->mac.type >= e1000_pch_spt) { 1004 sc->osdep.flash_bus_space_tag = 1005 sc->osdep.mem_bus_space_tag; 1006 sc->osdep.flash_bus_space_handle = 1007 sc->osdep.mem_bus_space_handle 1008 + E1000_FLASH_BASE_ADDR; 1009 } 1010 1011 /* Do Shared Code initialization */ 1012 error = e1000_setup_init_funcs(hw, true); 1013 if (error) { 1014 device_printf(dev, "Setup of Shared code failed, error %d\n", 1015 error); 1016 error = ENXIO; 1017 goto err_pci; 1018 } 1019 1020 em_setup_msix(ctx); 1021 e1000_get_bus_info(hw); 1022 1023 /* Set up some sysctls for the tunable interrupt delays */ 1024 em_add_int_delay_sysctl(sc, "rx_int_delay", 1025 "receive interrupt delay in usecs", &sc->rx_int_delay, 1026 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1027 em_add_int_delay_sysctl(sc, "tx_int_delay", 1028 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1029 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1030 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1031 "receive interrupt delay limit in usecs", 1032 &sc->rx_abs_int_delay, 1033 E1000_REGISTER(hw, E1000_RADV), 1034 em_rx_abs_int_delay_dflt); 1035 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1036 "transmit interrupt delay limit in usecs", 1037 &sc->tx_abs_int_delay, 1038 E1000_REGISTER(hw, E1000_TADV), 1039 em_tx_abs_int_delay_dflt); 1040 em_add_int_delay_sysctl(sc, "itr", 1041 "interrupt delay limit in usecs/4", 1042 &sc->tx_itr, 1043 E1000_REGISTER(hw, E1000_ITR), 1044 DEFAULT_ITR); 1045 1046 hw->mac.autoneg = DO_AUTO_NEG; 1047 hw->phy.autoneg_wait_to_complete = false; 1048 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1049 1050 if (hw->mac.type < em_mac_min) { 1051 e1000_init_script_state_82541(hw, true); 1052 e1000_set_tbi_compatibility_82543(hw, true); 1053 } 1054 /* Copper options */ 1055 if (hw->phy.media_type == e1000_media_type_copper) { 1056 hw->phy.mdix = AUTO_ALL_MODES; 1057 hw->phy.disable_polarity_correction = false; 1058 hw->phy.ms_type = EM_MASTER_SLAVE; 1059 } 1060 1061 /* 1062 * Set the frame limits assuming 1063 * standard ethernet sized frames. 1064 */ 1065 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1066 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1067 1068 /* 1069 * This controls when hardware reports transmit completion 1070 * status. 1071 */ 1072 hw->mac.report_tx_early = 1; 1073 1074 /* Allocate multicast array memory. */ 1075 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1076 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1077 if (sc->mta == NULL) { 1078 device_printf(dev, "Can not allocate multicast setup array\n"); 1079 error = ENOMEM; 1080 goto err_late; 1081 } 1082 1083 /* Check SOL/IDER usage */ 1084 if (e1000_check_reset_block(hw)) 1085 device_printf(dev, "PHY reset is blocked" 1086 " due to SOL/IDER session.\n"); 1087 1088 /* Sysctl for setting Energy Efficient Ethernet */ 1089 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1090 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1091 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1092 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1093 1094 /* 1095 ** Start from a known state, this is 1096 ** important in reading the nvm and 1097 ** mac from that. 1098 */ 1099 e1000_reset_hw(hw); 1100 1101 /* Make sure we have a good EEPROM before we read from it */ 1102 if (e1000_validate_nvm_checksum(hw) < 0) { 1103 /* 1104 ** Some PCI-E parts fail the first check due to 1105 ** the link being in sleep state, call it again, 1106 ** if it fails a second time its a real issue. 1107 */ 1108 if (e1000_validate_nvm_checksum(hw) < 0) { 1109 device_printf(dev, 1110 "The EEPROM Checksum Is Not Valid\n"); 1111 error = EIO; 1112 goto err_late; 1113 } 1114 } 1115 1116 /* Copy the permanent MAC address out of the EEPROM */ 1117 if (e1000_read_mac_addr(hw) < 0) { 1118 device_printf(dev, "EEPROM read error while reading MAC" 1119 " address\n"); 1120 error = EIO; 1121 goto err_late; 1122 } 1123 1124 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1125 if (sc->vf_ifp) { 1126 ether_gen_addr(iflib_get_ifp(ctx), 1127 (struct ether_addr *)hw->mac.addr); 1128 } else { 1129 device_printf(dev, "Invalid MAC address\n"); 1130 error = EIO; 1131 goto err_late; 1132 } 1133 } 1134 1135 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1136 em_fw_version_locked(ctx); 1137 1138 em_print_fw_version(sc); 1139 1140 /* 1141 * Get Wake-on-Lan and Management info for later use 1142 */ 1143 em_get_wakeup(ctx); 1144 1145 /* Enable only WOL MAGIC by default */ 1146 scctx->isc_capenable &= ~IFCAP_WOL; 1147 if (sc->wol != 0) 1148 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1149 1150 iflib_set_mac(ctx, hw->mac.addr); 1151 1152 return (0); 1153 1154 err_late: 1155 em_release_hw_control(sc); 1156 err_pci: 1157 em_free_pci_resources(ctx); 1158 free(sc->mta, M_DEVBUF); 1159 1160 return (error); 1161 } 1162 1163 static int 1164 em_if_attach_post(if_ctx_t ctx) 1165 { 1166 struct e1000_softc *sc = iflib_get_softc(ctx); 1167 struct e1000_hw *hw = &sc->hw; 1168 int error = 0; 1169 1170 /* Setup OS specific network interface */ 1171 error = em_setup_interface(ctx); 1172 if (error != 0) { 1173 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1174 goto err_late; 1175 } 1176 1177 em_reset(ctx); 1178 1179 /* Initialize statistics */ 1180 em_update_stats_counters(sc); 1181 hw->mac.get_link_status = 1; 1182 em_if_update_admin_status(ctx); 1183 em_add_hw_stats(sc); 1184 1185 /* Non-AMT based hardware can now take control from firmware */ 1186 if (sc->has_manage && !sc->has_amt) 1187 em_get_hw_control(sc); 1188 1189 INIT_DEBUGOUT("em_if_attach_post: end"); 1190 1191 return (0); 1192 1193 err_late: 1194 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1195 return (error); 1196 } 1197 1198 /********************************************************************* 1199 * Device removal routine 1200 * 1201 * The detach entry point is called when the driver is being removed. 1202 * This routine stops the adapter and deallocates all the resources 1203 * that were allocated for driver operation. 1204 * 1205 * return 0 on success, positive on failure 1206 *********************************************************************/ 1207 static int 1208 em_if_detach(if_ctx_t ctx) 1209 { 1210 struct e1000_softc *sc = iflib_get_softc(ctx); 1211 1212 INIT_DEBUGOUT("em_if_detach: begin"); 1213 1214 e1000_phy_hw_reset(&sc->hw); 1215 1216 em_release_manageability(sc); 1217 em_release_hw_control(sc); 1218 em_free_pci_resources(ctx); 1219 free(sc->mta, M_DEVBUF); 1220 sc->mta = NULL; 1221 1222 return (0); 1223 } 1224 1225 /********************************************************************* 1226 * 1227 * Shutdown entry point 1228 * 1229 **********************************************************************/ 1230 1231 static int 1232 em_if_shutdown(if_ctx_t ctx) 1233 { 1234 return em_if_suspend(ctx); 1235 } 1236 1237 /* 1238 * Suspend/resume device methods. 1239 */ 1240 static int 1241 em_if_suspend(if_ctx_t ctx) 1242 { 1243 struct e1000_softc *sc = iflib_get_softc(ctx); 1244 1245 em_release_manageability(sc); 1246 em_release_hw_control(sc); 1247 em_enable_wakeup(ctx); 1248 return (0); 1249 } 1250 1251 static int 1252 em_if_resume(if_ctx_t ctx) 1253 { 1254 struct e1000_softc *sc = iflib_get_softc(ctx); 1255 1256 if (sc->hw.mac.type == e1000_pch2lan) 1257 e1000_resume_workarounds_pchlan(&sc->hw); 1258 em_if_init(ctx); 1259 em_init_manageability(sc); 1260 1261 return(0); 1262 } 1263 1264 static int 1265 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1266 { 1267 int max_frame_size; 1268 struct e1000_softc *sc = iflib_get_softc(ctx); 1269 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1270 1271 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1272 1273 switch (sc->hw.mac.type) { 1274 case e1000_82571: 1275 case e1000_82572: 1276 case e1000_ich9lan: 1277 case e1000_ich10lan: 1278 case e1000_pch2lan: 1279 case e1000_pch_lpt: 1280 case e1000_pch_spt: 1281 case e1000_pch_cnp: 1282 case e1000_pch_tgp: 1283 case e1000_pch_adp: 1284 case e1000_pch_mtp: 1285 case e1000_pch_ptp: 1286 case e1000_82574: 1287 case e1000_82583: 1288 case e1000_80003es2lan: 1289 /* 9K Jumbo Frame size */ 1290 max_frame_size = 9234; 1291 break; 1292 case e1000_pchlan: 1293 max_frame_size = 4096; 1294 break; 1295 case e1000_82542: 1296 case e1000_ich8lan: 1297 /* Adapters that do not support jumbo frames */ 1298 max_frame_size = ETHER_MAX_LEN; 1299 break; 1300 default: 1301 if (sc->hw.mac.type >= igb_mac_min) 1302 max_frame_size = 9234; 1303 else /* lem */ 1304 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1305 } 1306 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1307 return (EINVAL); 1308 } 1309 1310 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1311 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1312 return (0); 1313 } 1314 1315 /********************************************************************* 1316 * Init entry point 1317 * 1318 * This routine is used in two ways. It is used by the stack as 1319 * init entry point in network interface structure. It is also used 1320 * by the driver as a hw/sw initialization routine to get to a 1321 * consistent state. 1322 * 1323 **********************************************************************/ 1324 static void 1325 em_if_init(if_ctx_t ctx) 1326 { 1327 struct e1000_softc *sc = iflib_get_softc(ctx); 1328 if_softc_ctx_t scctx = sc->shared; 1329 if_t ifp = iflib_get_ifp(ctx); 1330 struct em_tx_queue *tx_que; 1331 int i; 1332 1333 INIT_DEBUGOUT("em_if_init: begin"); 1334 1335 /* Get the latest mac address, User can use a LAA */ 1336 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1337 ETHER_ADDR_LEN); 1338 1339 /* Put the address into the Receive Address Array */ 1340 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1341 1342 /* 1343 * With the 82571 adapter, RAR[0] may be overwritten 1344 * when the other port is reset, we make a duplicate 1345 * in RAR[14] for that eventuality, this assures 1346 * the interface continues to function. 1347 */ 1348 if (sc->hw.mac.type == e1000_82571) { 1349 e1000_set_laa_state_82571(&sc->hw, true); 1350 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1351 E1000_RAR_ENTRIES - 1); 1352 } 1353 1354 /* Initialize the hardware */ 1355 em_reset(ctx); 1356 em_if_update_admin_status(ctx); 1357 1358 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1359 struct tx_ring *txr = &tx_que->txr; 1360 1361 txr->tx_rs_cidx = txr->tx_rs_pidx; 1362 1363 /* Initialize the last processed descriptor to be the end of 1364 * the ring, rather than the start, so that we avoid an 1365 * off-by-one error when calculating how many descriptors are 1366 * done in the credits_update function. 1367 */ 1368 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1369 } 1370 1371 /* Setup VLAN support, basic and offload if available */ 1372 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1373 1374 /* Clear bad data from Rx FIFOs */ 1375 if (sc->hw.mac.type >= igb_mac_min) 1376 e1000_rx_fifo_flush_base(&sc->hw); 1377 1378 /* Configure for OS presence */ 1379 em_init_manageability(sc); 1380 1381 /* Prepare transmit descriptors and buffers */ 1382 em_initialize_transmit_unit(ctx); 1383 1384 /* Setup Multicast table */ 1385 em_if_multi_set(ctx); 1386 1387 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1388 em_initialize_receive_unit(ctx); 1389 1390 /* Set up VLAN support and filter */ 1391 em_setup_vlan_hw_support(ctx); 1392 1393 /* Don't lose promiscuous settings */ 1394 em_if_set_promisc(ctx, if_getflags(ifp)); 1395 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1396 1397 /* MSI-X configuration for 82574 */ 1398 if (sc->hw.mac.type == e1000_82574) { 1399 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1400 1401 tmp |= E1000_CTRL_EXT_PBA_CLR; 1402 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1403 /* Set the IVAR - interrupt vector routing. */ 1404 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1405 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1406 igb_configure_queues(sc); 1407 1408 /* this clears any pending interrupts */ 1409 E1000_READ_REG(&sc->hw, E1000_ICR); 1410 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1411 1412 /* AMT based hardware can now take control from firmware */ 1413 if (sc->has_manage && sc->has_amt) 1414 em_get_hw_control(sc); 1415 1416 /* Set Energy Efficient Ethernet */ 1417 if (sc->hw.mac.type >= igb_mac_min && 1418 sc->hw.phy.media_type == e1000_media_type_copper) { 1419 if (sc->hw.mac.type == e1000_i354) 1420 e1000_set_eee_i354(&sc->hw, true, true); 1421 else 1422 e1000_set_eee_i350(&sc->hw, true, true); 1423 } 1424 } 1425 1426 /********************************************************************* 1427 * 1428 * Fast Legacy/MSI Combined Interrupt Service routine 1429 * 1430 *********************************************************************/ 1431 int 1432 em_intr(void *arg) 1433 { 1434 struct e1000_softc *sc = arg; 1435 if_ctx_t ctx = sc->ctx; 1436 u32 reg_icr; 1437 1438 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1439 1440 /* Hot eject? */ 1441 if (reg_icr == 0xffffffff) 1442 return FILTER_STRAY; 1443 1444 /* Definitely not our interrupt. */ 1445 if (reg_icr == 0x0) 1446 return FILTER_STRAY; 1447 1448 /* 1449 * Starting with the 82571 chip, bit 31 should be used to 1450 * determine whether the interrupt belongs to us. 1451 */ 1452 if (sc->hw.mac.type >= e1000_82571 && 1453 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1454 return FILTER_STRAY; 1455 1456 /* 1457 * Only MSI-X interrupts have one-shot behavior by taking advantage 1458 * of the EIAC register. Thus, explicitly disable interrupts. This 1459 * also works around the MSI message reordering errata on certain 1460 * systems. 1461 */ 1462 IFDI_INTR_DISABLE(ctx); 1463 1464 /* Link status change */ 1465 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1466 em_handle_link(ctx); 1467 1468 if (reg_icr & E1000_ICR_RXO) 1469 sc->rx_overruns++; 1470 1471 return (FILTER_SCHEDULE_THREAD); 1472 } 1473 1474 static int 1475 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1476 { 1477 struct e1000_softc *sc = iflib_get_softc(ctx); 1478 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1479 1480 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1481 return (0); 1482 } 1483 1484 static int 1485 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1486 { 1487 struct e1000_softc *sc = iflib_get_softc(ctx); 1488 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1489 1490 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1491 return (0); 1492 } 1493 1494 static int 1495 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1496 { 1497 struct e1000_softc *sc = iflib_get_softc(ctx); 1498 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1499 1500 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1501 return (0); 1502 } 1503 1504 static int 1505 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1506 { 1507 struct e1000_softc *sc = iflib_get_softc(ctx); 1508 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1509 1510 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1511 return (0); 1512 } 1513 1514 /********************************************************************* 1515 * 1516 * MSI-X RX Interrupt Service routine 1517 * 1518 **********************************************************************/ 1519 static int 1520 em_msix_que(void *arg) 1521 { 1522 struct em_rx_queue *que = arg; 1523 1524 ++que->irqs; 1525 1526 return (FILTER_SCHEDULE_THREAD); 1527 } 1528 1529 /********************************************************************* 1530 * 1531 * MSI-X Link Fast Interrupt Service routine 1532 * 1533 **********************************************************************/ 1534 static int 1535 em_msix_link(void *arg) 1536 { 1537 struct e1000_softc *sc = arg; 1538 u32 reg_icr; 1539 1540 ++sc->link_irq; 1541 MPASS(sc->hw.back != NULL); 1542 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1543 1544 if (reg_icr & E1000_ICR_RXO) 1545 sc->rx_overruns++; 1546 1547 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1548 em_handle_link(sc->ctx); 1549 1550 /* Re-arm unconditionally */ 1551 if (sc->hw.mac.type >= igb_mac_min) { 1552 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1553 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1554 } else if (sc->hw.mac.type == e1000_82574) { 1555 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1556 E1000_IMS_OTHER); 1557 /* 1558 * Because we must read the ICR for this interrupt it may 1559 * clear other causes using autoclear, for this reason we 1560 * simply create a soft interrupt for all these vectors. 1561 */ 1562 if (reg_icr) 1563 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1564 } else 1565 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1566 1567 return (FILTER_HANDLED); 1568 } 1569 1570 static void 1571 em_handle_link(void *context) 1572 { 1573 if_ctx_t ctx = context; 1574 struct e1000_softc *sc = iflib_get_softc(ctx); 1575 1576 sc->hw.mac.get_link_status = 1; 1577 iflib_admin_intr_deferred(ctx); 1578 } 1579 1580 /********************************************************************* 1581 * 1582 * Media Ioctl callback 1583 * 1584 * This routine is called whenever the user queries the status of 1585 * the interface using ifconfig. 1586 * 1587 **********************************************************************/ 1588 static void 1589 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1590 { 1591 struct e1000_softc *sc = iflib_get_softc(ctx); 1592 u_char fiber_type = IFM_1000_SX; 1593 1594 INIT_DEBUGOUT("em_if_media_status: begin"); 1595 1596 iflib_admin_intr_deferred(ctx); 1597 1598 ifmr->ifm_status = IFM_AVALID; 1599 ifmr->ifm_active = IFM_ETHER; 1600 1601 if (!sc->link_active) { 1602 return; 1603 } 1604 1605 ifmr->ifm_status |= IFM_ACTIVE; 1606 1607 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1608 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1609 if (sc->hw.mac.type == e1000_82545) 1610 fiber_type = IFM_1000_LX; 1611 ifmr->ifm_active |= fiber_type | IFM_FDX; 1612 } else { 1613 switch (sc->link_speed) { 1614 case 10: 1615 ifmr->ifm_active |= IFM_10_T; 1616 break; 1617 case 100: 1618 ifmr->ifm_active |= IFM_100_TX; 1619 break; 1620 case 1000: 1621 ifmr->ifm_active |= IFM_1000_T; 1622 break; 1623 } 1624 if (sc->link_duplex == FULL_DUPLEX) 1625 ifmr->ifm_active |= IFM_FDX; 1626 else 1627 ifmr->ifm_active |= IFM_HDX; 1628 } 1629 } 1630 1631 /********************************************************************* 1632 * 1633 * Media Ioctl callback 1634 * 1635 * This routine is called when the user changes speed/duplex using 1636 * media/mediopt option with ifconfig. 1637 * 1638 **********************************************************************/ 1639 static int 1640 em_if_media_change(if_ctx_t ctx) 1641 { 1642 struct e1000_softc *sc = iflib_get_softc(ctx); 1643 struct ifmedia *ifm = iflib_get_media(ctx); 1644 1645 INIT_DEBUGOUT("em_if_media_change: begin"); 1646 1647 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1648 return (EINVAL); 1649 1650 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1651 case IFM_AUTO: 1652 sc->hw.mac.autoneg = DO_AUTO_NEG; 1653 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1654 break; 1655 case IFM_1000_LX: 1656 case IFM_1000_SX: 1657 case IFM_1000_T: 1658 sc->hw.mac.autoneg = DO_AUTO_NEG; 1659 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1660 break; 1661 case IFM_100_TX: 1662 sc->hw.mac.autoneg = false; 1663 sc->hw.phy.autoneg_advertised = 0; 1664 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1665 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1666 else 1667 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1668 break; 1669 case IFM_10_T: 1670 sc->hw.mac.autoneg = false; 1671 sc->hw.phy.autoneg_advertised = 0; 1672 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1673 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1674 else 1675 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1676 break; 1677 default: 1678 device_printf(sc->dev, "Unsupported media type\n"); 1679 } 1680 1681 em_if_init(ctx); 1682 1683 return (0); 1684 } 1685 1686 static int 1687 em_if_set_promisc(if_ctx_t ctx, int flags) 1688 { 1689 struct e1000_softc *sc = iflib_get_softc(ctx); 1690 if_t ifp = iflib_get_ifp(ctx); 1691 u32 reg_rctl; 1692 int mcnt = 0; 1693 1694 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1695 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1696 if (flags & IFF_ALLMULTI) 1697 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1698 else 1699 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1700 1701 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1702 reg_rctl &= (~E1000_RCTL_MPE); 1703 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1704 1705 if (flags & IFF_PROMISC) { 1706 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1707 em_if_vlan_filter_disable(sc); 1708 /* Turn this on if you want to see bad packets */ 1709 if (em_debug_sbp) 1710 reg_rctl |= E1000_RCTL_SBP; 1711 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1712 } else { 1713 if (flags & IFF_ALLMULTI) { 1714 reg_rctl |= E1000_RCTL_MPE; 1715 reg_rctl &= ~E1000_RCTL_UPE; 1716 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1717 } 1718 if (em_if_vlan_filter_used(ctx)) 1719 em_if_vlan_filter_enable(sc); 1720 } 1721 return (0); 1722 } 1723 1724 static u_int 1725 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1726 { 1727 u8 *mta = arg; 1728 1729 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1730 return (0); 1731 1732 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1733 1734 return (1); 1735 } 1736 1737 /********************************************************************* 1738 * Multicast Update 1739 * 1740 * This routine is called whenever multicast address list is updated. 1741 * 1742 **********************************************************************/ 1743 static void 1744 em_if_multi_set(if_ctx_t ctx) 1745 { 1746 struct e1000_softc *sc = iflib_get_softc(ctx); 1747 if_t ifp = iflib_get_ifp(ctx); 1748 u8 *mta; /* Multicast array memory */ 1749 u32 reg_rctl = 0; 1750 int mcnt = 0; 1751 1752 IOCTL_DEBUGOUT("em_set_multi: begin"); 1753 1754 mta = sc->mta; 1755 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1756 1757 if (sc->hw.mac.type == e1000_82542 && 1758 sc->hw.revision_id == E1000_REVISION_2) { 1759 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1760 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1761 e1000_pci_clear_mwi(&sc->hw); 1762 reg_rctl |= E1000_RCTL_RST; 1763 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1764 msec_delay(5); 1765 } 1766 1767 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1768 1769 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1770 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1771 1772 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1773 1774 if (if_getflags(ifp) & IFF_PROMISC) 1775 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1776 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1777 if_getflags(ifp) & IFF_ALLMULTI) { 1778 reg_rctl |= E1000_RCTL_MPE; 1779 reg_rctl &= ~E1000_RCTL_UPE; 1780 } else 1781 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1782 1783 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1784 1785 if (sc->hw.mac.type == e1000_82542 && 1786 sc->hw.revision_id == E1000_REVISION_2) { 1787 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1788 reg_rctl &= ~E1000_RCTL_RST; 1789 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1790 msec_delay(5); 1791 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1792 e1000_pci_set_mwi(&sc->hw); 1793 } 1794 } 1795 1796 /********************************************************************* 1797 * Timer routine 1798 * 1799 * This routine schedules em_if_update_admin_status() to check for 1800 * link status and to gather statistics as well as to perform some 1801 * controller-specific hardware patting. 1802 * 1803 **********************************************************************/ 1804 static void 1805 em_if_timer(if_ctx_t ctx, uint16_t qid) 1806 { 1807 1808 if (qid != 0) 1809 return; 1810 1811 iflib_admin_intr_deferred(ctx); 1812 } 1813 1814 static void 1815 em_if_update_admin_status(if_ctx_t ctx) 1816 { 1817 struct e1000_softc *sc = iflib_get_softc(ctx); 1818 struct e1000_hw *hw = &sc->hw; 1819 device_t dev = iflib_get_dev(ctx); 1820 u32 link_check, thstat, ctrl; 1821 1822 link_check = thstat = ctrl = 0; 1823 /* Get the cached link value or read phy for real */ 1824 switch (hw->phy.media_type) { 1825 case e1000_media_type_copper: 1826 if (hw->mac.get_link_status) { 1827 if (hw->mac.type == e1000_pch_spt) 1828 msec_delay(50); 1829 /* Do the work to read phy */ 1830 e1000_check_for_link(hw); 1831 link_check = !hw->mac.get_link_status; 1832 if (link_check) /* ESB2 fix */ 1833 e1000_cfg_on_link_up(hw); 1834 } else { 1835 link_check = true; 1836 } 1837 break; 1838 case e1000_media_type_fiber: 1839 e1000_check_for_link(hw); 1840 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1841 E1000_STATUS_LU); 1842 break; 1843 case e1000_media_type_internal_serdes: 1844 e1000_check_for_link(hw); 1845 link_check = hw->mac.serdes_has_link; 1846 break; 1847 /* VF device is type_unknown */ 1848 case e1000_media_type_unknown: 1849 e1000_check_for_link(hw); 1850 link_check = !hw->mac.get_link_status; 1851 /* FALLTHROUGH */ 1852 default: 1853 break; 1854 } 1855 1856 /* Check for thermal downshift or shutdown */ 1857 if (hw->mac.type == e1000_i350) { 1858 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1859 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1860 } 1861 1862 /* Now check for a transition */ 1863 if (link_check && (sc->link_active == 0)) { 1864 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1865 &sc->link_duplex); 1866 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1867 if ((sc->link_speed != SPEED_1000) && 1868 ((hw->mac.type == e1000_82571) || 1869 (hw->mac.type == e1000_82572))) { 1870 int tarc0; 1871 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1872 tarc0 &= ~TARC_SPEED_MODE_BIT; 1873 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1874 } 1875 if (bootverbose) 1876 device_printf(dev, "Link is up %d Mbps %s\n", 1877 sc->link_speed, 1878 ((sc->link_duplex == FULL_DUPLEX) ? 1879 "Full Duplex" : "Half Duplex")); 1880 sc->link_active = 1; 1881 sc->smartspeed = 0; 1882 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1883 E1000_CTRL_EXT_LINK_MODE_GMII && 1884 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1885 device_printf(dev, "Link: thermal downshift\n"); 1886 /* Delay Link Up for Phy update */ 1887 if (((hw->mac.type == e1000_i210) || 1888 (hw->mac.type == e1000_i211)) && 1889 (hw->phy.id == I210_I_PHY_ID)) 1890 msec_delay(I210_LINK_DELAY); 1891 /* Reset if the media type changed. */ 1892 if (hw->dev_spec._82575.media_changed && 1893 hw->mac.type >= igb_mac_min) { 1894 hw->dev_spec._82575.media_changed = false; 1895 sc->flags |= IGB_MEDIA_RESET; 1896 em_reset(ctx); 1897 } 1898 iflib_link_state_change(ctx, LINK_STATE_UP, 1899 IF_Mbps(sc->link_speed)); 1900 } else if (!link_check && (sc->link_active == 1)) { 1901 sc->link_speed = 0; 1902 sc->link_duplex = 0; 1903 sc->link_active = 0; 1904 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1905 } 1906 em_update_stats_counters(sc); 1907 1908 /* Reset LAA into RAR[0] on 82571 */ 1909 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1910 e1000_rar_set(hw, hw->mac.addr, 0); 1911 1912 if (hw->mac.type < em_mac_min) 1913 lem_smartspeed(sc); 1914 } 1915 1916 static void 1917 em_if_watchdog_reset(if_ctx_t ctx) 1918 { 1919 struct e1000_softc *sc = iflib_get_softc(ctx); 1920 1921 /* 1922 * Just count the event; iflib(4) will already trigger a 1923 * sufficient reset of the controller. 1924 */ 1925 sc->watchdog_events++; 1926 } 1927 1928 /********************************************************************* 1929 * 1930 * This routine disables all traffic on the adapter by issuing a 1931 * global reset on the MAC. 1932 * 1933 **********************************************************************/ 1934 static void 1935 em_if_stop(if_ctx_t ctx) 1936 { 1937 struct e1000_softc *sc = iflib_get_softc(ctx); 1938 1939 INIT_DEBUGOUT("em_if_stop: begin"); 1940 1941 /* I219 needs special flushing to avoid hangs */ 1942 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1943 em_flush_desc_rings(sc); 1944 1945 e1000_reset_hw(&sc->hw); 1946 if (sc->hw.mac.type >= e1000_82544) 1947 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1948 1949 e1000_led_off(&sc->hw); 1950 e1000_cleanup_led(&sc->hw); 1951 } 1952 1953 /********************************************************************* 1954 * 1955 * Determine hardware revision. 1956 * 1957 **********************************************************************/ 1958 static void 1959 em_identify_hardware(if_ctx_t ctx) 1960 { 1961 device_t dev = iflib_get_dev(ctx); 1962 struct e1000_softc *sc = iflib_get_softc(ctx); 1963 1964 /* Make sure our PCI config space has the necessary stuff set */ 1965 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1966 1967 /* Save off the information about this board */ 1968 sc->hw.vendor_id = pci_get_vendor(dev); 1969 sc->hw.device_id = pci_get_device(dev); 1970 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1971 sc->hw.subsystem_vendor_id = 1972 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1973 sc->hw.subsystem_device_id = 1974 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1975 1976 /* Do Shared Code Init and Setup */ 1977 if (e1000_set_mac_type(&sc->hw)) { 1978 device_printf(dev, "Setup init failure\n"); 1979 return; 1980 } 1981 1982 /* Are we a VF device? */ 1983 if ((sc->hw.mac.type == e1000_vfadapt) || 1984 (sc->hw.mac.type == e1000_vfadapt_i350)) 1985 sc->vf_ifp = 1; 1986 else 1987 sc->vf_ifp = 0; 1988 } 1989 1990 static int 1991 em_allocate_pci_resources(if_ctx_t ctx) 1992 { 1993 struct e1000_softc *sc = iflib_get_softc(ctx); 1994 device_t dev = iflib_get_dev(ctx); 1995 int rid, val; 1996 1997 rid = PCIR_BAR(0); 1998 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1999 &rid, RF_ACTIVE); 2000 if (sc->memory == NULL) { 2001 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2002 return (ENXIO); 2003 } 2004 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2005 sc->osdep.mem_bus_space_handle = 2006 rman_get_bushandle(sc->memory); 2007 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2008 2009 /* Only older adapters use IO mapping */ 2010 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2011 /* Figure our where our IO BAR is ? */ 2012 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2013 val = pci_read_config(dev, rid, 4); 2014 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2015 break; 2016 } 2017 rid += 4; 2018 /* check for 64bit BAR */ 2019 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2020 rid += 4; 2021 } 2022 if (rid >= PCIR_CIS) { 2023 device_printf(dev, "Unable to locate IO BAR\n"); 2024 return (ENXIO); 2025 } 2026 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2027 &rid, RF_ACTIVE); 2028 if (sc->ioport == NULL) { 2029 device_printf(dev, "Unable to allocate bus resource: " 2030 "ioport\n"); 2031 return (ENXIO); 2032 } 2033 sc->hw.io_base = 0; 2034 sc->osdep.io_bus_space_tag = 2035 rman_get_bustag(sc->ioport); 2036 sc->osdep.io_bus_space_handle = 2037 rman_get_bushandle(sc->ioport); 2038 } 2039 2040 sc->hw.back = &sc->osdep; 2041 2042 return (0); 2043 } 2044 2045 /********************************************************************* 2046 * 2047 * Set up the MSI-X Interrupt handlers 2048 * 2049 **********************************************************************/ 2050 static int 2051 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2052 { 2053 struct e1000_softc *sc = iflib_get_softc(ctx); 2054 struct em_rx_queue *rx_que = sc->rx_queues; 2055 struct em_tx_queue *tx_que = sc->tx_queues; 2056 int error, rid, i, vector = 0, rx_vectors; 2057 char buf[16]; 2058 2059 /* First set up ring resources */ 2060 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2061 rid = vector + 1; 2062 snprintf(buf, sizeof(buf), "rxq%d", i); 2063 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2064 if (error) { 2065 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2066 sc->rx_num_queues = i + 1; 2067 goto fail; 2068 } 2069 2070 rx_que->msix = vector; 2071 2072 /* 2073 * Set the bit to enable interrupt 2074 * in E1000_IMS -- bits 20 and 21 2075 * are for RX0 and RX1, note this has 2076 * NOTHING to do with the MSI-X vector 2077 */ 2078 if (sc->hw.mac.type == e1000_82574) { 2079 rx_que->eims = 1 << (20 + i); 2080 sc->ims |= rx_que->eims; 2081 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2082 } else if (sc->hw.mac.type == e1000_82575) 2083 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2084 else 2085 rx_que->eims = 1 << vector; 2086 } 2087 rx_vectors = vector; 2088 2089 vector = 0; 2090 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2091 snprintf(buf, sizeof(buf), "txq%d", i); 2092 tx_que = &sc->tx_queues[i]; 2093 iflib_softirq_alloc_generic(ctx, 2094 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2095 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2096 2097 tx_que->msix = (vector % sc->rx_num_queues); 2098 2099 /* 2100 * Set the bit to enable interrupt 2101 * in E1000_IMS -- bits 22 and 23 2102 * are for TX0 and TX1, note this has 2103 * NOTHING to do with the MSI-X vector 2104 */ 2105 if (sc->hw.mac.type == e1000_82574) { 2106 tx_que->eims = 1 << (22 + i); 2107 sc->ims |= tx_que->eims; 2108 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2109 } else if (sc->hw.mac.type == e1000_82575) { 2110 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2111 } else { 2112 tx_que->eims = 1 << i; 2113 } 2114 } 2115 2116 /* Link interrupt */ 2117 rid = rx_vectors + 1; 2118 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2119 2120 if (error) { 2121 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2122 goto fail; 2123 } 2124 sc->linkvec = rx_vectors; 2125 if (sc->hw.mac.type < igb_mac_min) { 2126 sc->ivars |= (8 | rx_vectors) << 16; 2127 sc->ivars |= 0x80000000; 2128 /* Enable the "Other" interrupt type for link status change */ 2129 sc->ims |= E1000_IMS_OTHER; 2130 } 2131 2132 return (0); 2133 fail: 2134 iflib_irq_free(ctx, &sc->irq); 2135 rx_que = sc->rx_queues; 2136 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2137 iflib_irq_free(ctx, &rx_que->que_irq); 2138 return (error); 2139 } 2140 2141 static void 2142 igb_configure_queues(struct e1000_softc *sc) 2143 { 2144 struct e1000_hw *hw = &sc->hw; 2145 struct em_rx_queue *rx_que; 2146 struct em_tx_queue *tx_que; 2147 u32 tmp, ivar = 0, newitr = 0; 2148 2149 /* First turn on RSS capability */ 2150 if (hw->mac.type != e1000_82575) 2151 E1000_WRITE_REG(hw, E1000_GPIE, 2152 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2153 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2154 2155 /* Turn on MSI-X */ 2156 switch (hw->mac.type) { 2157 case e1000_82580: 2158 case e1000_i350: 2159 case e1000_i354: 2160 case e1000_i210: 2161 case e1000_i211: 2162 case e1000_vfadapt: 2163 case e1000_vfadapt_i350: 2164 /* RX entries */ 2165 for (int i = 0; i < sc->rx_num_queues; i++) { 2166 u32 index = i >> 1; 2167 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2168 rx_que = &sc->rx_queues[i]; 2169 if (i & 1) { 2170 ivar &= 0xFF00FFFF; 2171 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2172 } else { 2173 ivar &= 0xFFFFFF00; 2174 ivar |= rx_que->msix | E1000_IVAR_VALID; 2175 } 2176 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2177 } 2178 /* TX entries */ 2179 for (int i = 0; i < sc->tx_num_queues; i++) { 2180 u32 index = i >> 1; 2181 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2182 tx_que = &sc->tx_queues[i]; 2183 if (i & 1) { 2184 ivar &= 0x00FFFFFF; 2185 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2186 } else { 2187 ivar &= 0xFFFF00FF; 2188 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2189 } 2190 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2191 sc->que_mask |= tx_que->eims; 2192 } 2193 2194 /* And for the link interrupt */ 2195 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2196 sc->link_mask = 1 << sc->linkvec; 2197 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2198 break; 2199 case e1000_82576: 2200 /* RX entries */ 2201 for (int i = 0; i < sc->rx_num_queues; i++) { 2202 u32 index = i & 0x7; /* Each IVAR has two entries */ 2203 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2204 rx_que = &sc->rx_queues[i]; 2205 if (i < 8) { 2206 ivar &= 0xFFFFFF00; 2207 ivar |= rx_que->msix | E1000_IVAR_VALID; 2208 } else { 2209 ivar &= 0xFF00FFFF; 2210 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2211 } 2212 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2213 sc->que_mask |= rx_que->eims; 2214 } 2215 /* TX entries */ 2216 for (int i = 0; i < sc->tx_num_queues; i++) { 2217 u32 index = i & 0x7; /* Each IVAR has two entries */ 2218 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2219 tx_que = &sc->tx_queues[i]; 2220 if (i < 8) { 2221 ivar &= 0xFFFF00FF; 2222 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2223 } else { 2224 ivar &= 0x00FFFFFF; 2225 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2226 } 2227 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2228 sc->que_mask |= tx_que->eims; 2229 } 2230 2231 /* And for the link interrupt */ 2232 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2233 sc->link_mask = 1 << sc->linkvec; 2234 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2235 break; 2236 2237 case e1000_82575: 2238 /* enable MSI-X support*/ 2239 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2240 tmp |= E1000_CTRL_EXT_PBA_CLR; 2241 /* Auto-Mask interrupts upon ICR read. */ 2242 tmp |= E1000_CTRL_EXT_EIAME; 2243 tmp |= E1000_CTRL_EXT_IRCA; 2244 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2245 2246 /* Queues */ 2247 for (int i = 0; i < sc->rx_num_queues; i++) { 2248 rx_que = &sc->rx_queues[i]; 2249 tmp = E1000_EICR_RX_QUEUE0 << i; 2250 tmp |= E1000_EICR_TX_QUEUE0 << i; 2251 rx_que->eims = tmp; 2252 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2253 i, rx_que->eims); 2254 sc->que_mask |= rx_que->eims; 2255 } 2256 2257 /* Link */ 2258 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2259 E1000_EIMS_OTHER); 2260 sc->link_mask |= E1000_EIMS_OTHER; 2261 default: 2262 break; 2263 } 2264 2265 /* Set the starting interrupt rate */ 2266 if (em_max_interrupt_rate > 0) 2267 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2268 2269 if (hw->mac.type == e1000_82575) 2270 newitr |= newitr << 16; 2271 else 2272 newitr |= E1000_EITR_CNT_IGNR; 2273 2274 for (int i = 0; i < sc->rx_num_queues; i++) { 2275 rx_que = &sc->rx_queues[i]; 2276 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2277 } 2278 2279 return; 2280 } 2281 2282 static void 2283 em_free_pci_resources(if_ctx_t ctx) 2284 { 2285 struct e1000_softc *sc = iflib_get_softc(ctx); 2286 struct em_rx_queue *que = sc->rx_queues; 2287 device_t dev = iflib_get_dev(ctx); 2288 2289 /* Release all MSI-X queue resources */ 2290 if (sc->intr_type == IFLIB_INTR_MSIX) 2291 iflib_irq_free(ctx, &sc->irq); 2292 2293 if (que != NULL) { 2294 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2295 iflib_irq_free(ctx, &que->que_irq); 2296 } 2297 } 2298 2299 if (sc->memory != NULL) { 2300 bus_release_resource(dev, SYS_RES_MEMORY, 2301 rman_get_rid(sc->memory), sc->memory); 2302 sc->memory = NULL; 2303 } 2304 2305 if (sc->flash != NULL) { 2306 bus_release_resource(dev, SYS_RES_MEMORY, 2307 rman_get_rid(sc->flash), sc->flash); 2308 sc->flash = NULL; 2309 } 2310 2311 if (sc->ioport != NULL) { 2312 bus_release_resource(dev, SYS_RES_IOPORT, 2313 rman_get_rid(sc->ioport), sc->ioport); 2314 sc->ioport = NULL; 2315 } 2316 } 2317 2318 /* Set up MSI or MSI-X */ 2319 static int 2320 em_setup_msix(if_ctx_t ctx) 2321 { 2322 struct e1000_softc *sc = iflib_get_softc(ctx); 2323 2324 if (sc->hw.mac.type == e1000_82574) { 2325 em_enable_vectors_82574(ctx); 2326 } 2327 return (0); 2328 } 2329 2330 /********************************************************************* 2331 * 2332 * Workaround for SmartSpeed on 82541 and 82547 controllers 2333 * 2334 **********************************************************************/ 2335 static void 2336 lem_smartspeed(struct e1000_softc *sc) 2337 { 2338 u16 phy_tmp; 2339 2340 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2341 sc->hw.mac.autoneg == 0 || 2342 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2343 return; 2344 2345 if (sc->smartspeed == 0) { 2346 /* If Master/Slave config fault is asserted twice, 2347 * we assume back-to-back */ 2348 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2349 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2350 return; 2351 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2352 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2353 e1000_read_phy_reg(&sc->hw, 2354 PHY_1000T_CTRL, &phy_tmp); 2355 if(phy_tmp & CR_1000T_MS_ENABLE) { 2356 phy_tmp &= ~CR_1000T_MS_ENABLE; 2357 e1000_write_phy_reg(&sc->hw, 2358 PHY_1000T_CTRL, phy_tmp); 2359 sc->smartspeed++; 2360 if(sc->hw.mac.autoneg && 2361 !e1000_copper_link_autoneg(&sc->hw) && 2362 !e1000_read_phy_reg(&sc->hw, 2363 PHY_CONTROL, &phy_tmp)) { 2364 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2365 MII_CR_RESTART_AUTO_NEG); 2366 e1000_write_phy_reg(&sc->hw, 2367 PHY_CONTROL, phy_tmp); 2368 } 2369 } 2370 } 2371 return; 2372 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2373 /* If still no link, perhaps using 2/3 pair cable */ 2374 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2375 phy_tmp |= CR_1000T_MS_ENABLE; 2376 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2377 if(sc->hw.mac.autoneg && 2378 !e1000_copper_link_autoneg(&sc->hw) && 2379 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2380 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2381 MII_CR_RESTART_AUTO_NEG); 2382 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2383 } 2384 } 2385 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2386 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2387 sc->smartspeed = 0; 2388 } 2389 2390 /********************************************************************* 2391 * 2392 * Initialize the DMA Coalescing feature 2393 * 2394 **********************************************************************/ 2395 static void 2396 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2397 { 2398 device_t dev = sc->dev; 2399 struct e1000_hw *hw = &sc->hw; 2400 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2401 u16 hwm; 2402 u16 max_frame_size; 2403 2404 if (hw->mac.type == e1000_i211) 2405 return; 2406 2407 max_frame_size = sc->shared->isc_max_frame_size; 2408 if (hw->mac.type > e1000_82580) { 2409 2410 if (sc->dmac == 0) { /* Disabling it */ 2411 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2412 return; 2413 } else 2414 device_printf(dev, "DMA Coalescing enabled\n"); 2415 2416 /* Set starting threshold */ 2417 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2418 2419 hwm = 64 * pba - max_frame_size / 16; 2420 if (hwm < 64 * (pba - 6)) 2421 hwm = 64 * (pba - 6); 2422 reg = E1000_READ_REG(hw, E1000_FCRTC); 2423 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2424 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2425 & E1000_FCRTC_RTH_COAL_MASK); 2426 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2427 2428 2429 dmac = pba - max_frame_size / 512; 2430 if (dmac < pba - 10) 2431 dmac = pba - 10; 2432 reg = E1000_READ_REG(hw, E1000_DMACR); 2433 reg &= ~E1000_DMACR_DMACTHR_MASK; 2434 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2435 & E1000_DMACR_DMACTHR_MASK); 2436 2437 /* transition to L0x or L1 if available..*/ 2438 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2439 2440 /* Check if status is 2.5Gb backplane connection 2441 * before configuration of watchdog timer, which is 2442 * in msec values in 12.8usec intervals 2443 * watchdog timer= msec values in 32usec intervals 2444 * for non 2.5Gb connection 2445 */ 2446 if (hw->mac.type == e1000_i354) { 2447 int status = E1000_READ_REG(hw, E1000_STATUS); 2448 if ((status & E1000_STATUS_2P5_SKU) && 2449 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2450 reg |= ((sc->dmac * 5) >> 6); 2451 else 2452 reg |= (sc->dmac >> 5); 2453 } else { 2454 reg |= (sc->dmac >> 5); 2455 } 2456 2457 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2458 2459 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2460 2461 /* Set the interval before transition */ 2462 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2463 if (hw->mac.type == e1000_i350) 2464 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2465 /* 2466 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2467 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2468 */ 2469 if (hw->mac.type == e1000_i354) { 2470 int status = E1000_READ_REG(hw, E1000_STATUS); 2471 if ((status & E1000_STATUS_2P5_SKU) && 2472 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2473 reg |= 0xA; 2474 else 2475 reg |= 0x4; 2476 } else { 2477 reg |= 0x4; 2478 } 2479 2480 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2481 2482 /* free space in tx packet buffer to wake from DMA coal */ 2483 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2484 (2 * max_frame_size)) >> 6); 2485 2486 /* make low power state decision controlled by DMA coal */ 2487 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2488 reg &= ~E1000_PCIEMISC_LX_DECISION; 2489 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2490 2491 } else if (hw->mac.type == e1000_82580) { 2492 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2493 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2494 reg & ~E1000_PCIEMISC_LX_DECISION); 2495 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2496 } 2497 } 2498 /********************************************************************* 2499 * The 3 following flush routines are used as a workaround in the 2500 * I219 client parts and only for them. 2501 * 2502 * em_flush_tx_ring - remove all descriptors from the tx_ring 2503 * 2504 * We want to clear all pending descriptors from the TX ring. 2505 * zeroing happens when the HW reads the regs. We assign the ring itself as 2506 * the data of the next descriptor. We don't care about the data we are about 2507 * to reset the HW. 2508 **********************************************************************/ 2509 static void 2510 em_flush_tx_ring(struct e1000_softc *sc) 2511 { 2512 struct e1000_hw *hw = &sc->hw; 2513 struct tx_ring *txr = &sc->tx_queues->txr; 2514 struct e1000_tx_desc *txd; 2515 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2516 u16 size = 512; 2517 2518 tctl = E1000_READ_REG(hw, E1000_TCTL); 2519 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2520 2521 txd = &txr->tx_base[txr->tx_cidx_processed]; 2522 2523 /* Just use the ring as a dummy buffer addr */ 2524 txd->buffer_addr = txr->tx_paddr; 2525 txd->lower.data = htole32(txd_lower | size); 2526 txd->upper.data = 0; 2527 2528 /* flush descriptors to memory before notifying the HW */ 2529 wmb(); 2530 2531 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2532 mb(); 2533 usec_delay(250); 2534 } 2535 2536 /********************************************************************* 2537 * em_flush_rx_ring - remove all descriptors from the rx_ring 2538 * 2539 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2540 **********************************************************************/ 2541 static void 2542 em_flush_rx_ring(struct e1000_softc *sc) 2543 { 2544 struct e1000_hw *hw = &sc->hw; 2545 u32 rctl, rxdctl; 2546 2547 rctl = E1000_READ_REG(hw, E1000_RCTL); 2548 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2549 E1000_WRITE_FLUSH(hw); 2550 usec_delay(150); 2551 2552 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2553 /* zero the lower 14 bits (prefetch and host thresholds) */ 2554 rxdctl &= 0xffffc000; 2555 /* 2556 * update thresholds: prefetch threshold to 31, host threshold to 1 2557 * and make sure the granularity is "descriptors" and not "cache lines" 2558 */ 2559 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2560 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2561 2562 /* momentarily enable the RX ring for the changes to take effect */ 2563 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2564 E1000_WRITE_FLUSH(hw); 2565 usec_delay(150); 2566 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2567 } 2568 2569 /********************************************************************* 2570 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2571 * 2572 * In I219, the descriptor rings must be emptied before resetting the HW 2573 * or before changing the device state to D3 during runtime (runtime PM). 2574 * 2575 * Failure to do this will cause the HW to enter a unit hang state which can 2576 * only be released by PCI reset on the device 2577 * 2578 **********************************************************************/ 2579 static void 2580 em_flush_desc_rings(struct e1000_softc *sc) 2581 { 2582 struct e1000_hw *hw = &sc->hw; 2583 device_t dev = sc->dev; 2584 u16 hang_state; 2585 u32 fext_nvm11, tdlen; 2586 2587 /* First, disable MULR fix in FEXTNVM11 */ 2588 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2589 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2590 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2591 2592 /* do nothing if we're not in faulty state, or if the queue is empty */ 2593 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2594 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2595 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2596 return; 2597 em_flush_tx_ring(sc); 2598 2599 /* recheck, maybe the fault is caused by the rx ring */ 2600 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2601 if (hang_state & FLUSH_DESC_REQUIRED) 2602 em_flush_rx_ring(sc); 2603 } 2604 2605 2606 /********************************************************************* 2607 * 2608 * Initialize the hardware to a configuration as specified by the 2609 * sc structure. 2610 * 2611 **********************************************************************/ 2612 static void 2613 em_reset(if_ctx_t ctx) 2614 { 2615 device_t dev = iflib_get_dev(ctx); 2616 struct e1000_softc *sc = iflib_get_softc(ctx); 2617 if_t ifp = iflib_get_ifp(ctx); 2618 struct e1000_hw *hw = &sc->hw; 2619 u32 rx_buffer_size; 2620 u32 pba; 2621 2622 INIT_DEBUGOUT("em_reset: begin"); 2623 /* Let the firmware know the OS is in control */ 2624 em_get_hw_control(sc); 2625 2626 /* Set up smart power down as default off on newer adapters. */ 2627 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2628 hw->mac.type == e1000_82572)) { 2629 u16 phy_tmp = 0; 2630 2631 /* Speed up time to link by disabling smart power down. */ 2632 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2633 phy_tmp &= ~IGP02E1000_PM_SPD; 2634 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2635 } 2636 2637 /* 2638 * Packet Buffer Allocation (PBA) 2639 * Writing PBA sets the receive portion of the buffer 2640 * the remainder is used for the transmit buffer. 2641 */ 2642 switch (hw->mac.type) { 2643 /* 82547: Total Packet Buffer is 40K */ 2644 case e1000_82547: 2645 case e1000_82547_rev_2: 2646 if (hw->mac.max_frame_size > 8192) 2647 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2648 else 2649 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2650 break; 2651 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2652 case e1000_82571: 2653 case e1000_82572: 2654 case e1000_80003es2lan: 2655 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2656 break; 2657 /* 82573: Total Packet Buffer is 32K */ 2658 case e1000_82573: 2659 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2660 break; 2661 case e1000_82574: 2662 case e1000_82583: 2663 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2664 break; 2665 case e1000_ich8lan: 2666 pba = E1000_PBA_8K; 2667 break; 2668 case e1000_ich9lan: 2669 case e1000_ich10lan: 2670 /* Boost Receive side for jumbo frames */ 2671 if (hw->mac.max_frame_size > 4096) 2672 pba = E1000_PBA_14K; 2673 else 2674 pba = E1000_PBA_10K; 2675 break; 2676 case e1000_pchlan: 2677 case e1000_pch2lan: 2678 case e1000_pch_lpt: 2679 case e1000_pch_spt: 2680 case e1000_pch_cnp: 2681 case e1000_pch_tgp: 2682 case e1000_pch_adp: 2683 case e1000_pch_mtp: 2684 case e1000_pch_ptp: 2685 pba = E1000_PBA_26K; 2686 break; 2687 case e1000_82575: 2688 pba = E1000_PBA_32K; 2689 break; 2690 case e1000_82576: 2691 case e1000_vfadapt: 2692 pba = E1000_READ_REG(hw, E1000_RXPBS); 2693 pba &= E1000_RXPBS_SIZE_MASK_82576; 2694 break; 2695 case e1000_82580: 2696 case e1000_i350: 2697 case e1000_i354: 2698 case e1000_vfadapt_i350: 2699 pba = E1000_READ_REG(hw, E1000_RXPBS); 2700 pba = e1000_rxpbs_adjust_82580(pba); 2701 break; 2702 case e1000_i210: 2703 case e1000_i211: 2704 pba = E1000_PBA_34K; 2705 break; 2706 default: 2707 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2708 if (hw->mac.max_frame_size > 8192) 2709 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2710 else 2711 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2712 } 2713 2714 /* Special needs in case of Jumbo frames */ 2715 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2716 u32 tx_space, min_tx, min_rx; 2717 pba = E1000_READ_REG(hw, E1000_PBA); 2718 tx_space = pba >> 16; 2719 pba &= 0xffff; 2720 min_tx = (hw->mac.max_frame_size + 2721 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2722 min_tx = roundup2(min_tx, 1024); 2723 min_tx >>= 10; 2724 min_rx = hw->mac.max_frame_size; 2725 min_rx = roundup2(min_rx, 1024); 2726 min_rx >>= 10; 2727 if (tx_space < min_tx && 2728 ((min_tx - tx_space) < pba)) { 2729 pba = pba - (min_tx - tx_space); 2730 /* 2731 * if short on rx space, rx wins 2732 * and must trump tx adjustment 2733 */ 2734 if (pba < min_rx) 2735 pba = min_rx; 2736 } 2737 E1000_WRITE_REG(hw, E1000_PBA, pba); 2738 } 2739 2740 if (hw->mac.type < igb_mac_min) 2741 E1000_WRITE_REG(hw, E1000_PBA, pba); 2742 2743 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2744 2745 /* 2746 * These parameters control the automatic generation (Tx) and 2747 * response (Rx) to Ethernet PAUSE frames. 2748 * - High water mark should allow for at least two frames to be 2749 * received after sending an XOFF. 2750 * - Low water mark works best when it is very near the high water mark. 2751 * This allows the receiver to restart by sending XON when it has 2752 * drained a bit. Here we use an arbitrary value of 1500 which will 2753 * restart after one full frame is pulled from the buffer. There 2754 * could be several smaller frames in the buffer and if so they will 2755 * not trigger the XON until their total number reduces the buffer 2756 * by 1500. 2757 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2758 */ 2759 rx_buffer_size = (pba & 0xffff) << 10; 2760 hw->fc.high_water = rx_buffer_size - 2761 roundup2(hw->mac.max_frame_size, 1024); 2762 hw->fc.low_water = hw->fc.high_water - 1500; 2763 2764 if (sc->fc) /* locally set flow control value? */ 2765 hw->fc.requested_mode = sc->fc; 2766 else 2767 hw->fc.requested_mode = e1000_fc_full; 2768 2769 if (hw->mac.type == e1000_80003es2lan) 2770 hw->fc.pause_time = 0xFFFF; 2771 else 2772 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2773 2774 hw->fc.send_xon = true; 2775 2776 /* Device specific overrides/settings */ 2777 switch (hw->mac.type) { 2778 case e1000_pchlan: 2779 /* Workaround: no TX flow ctrl for PCH */ 2780 hw->fc.requested_mode = e1000_fc_rx_pause; 2781 hw->fc.pause_time = 0xFFFF; /* override */ 2782 if (if_getmtu(ifp) > ETHERMTU) { 2783 hw->fc.high_water = 0x3500; 2784 hw->fc.low_water = 0x1500; 2785 } else { 2786 hw->fc.high_water = 0x5000; 2787 hw->fc.low_water = 0x3000; 2788 } 2789 hw->fc.refresh_time = 0x1000; 2790 break; 2791 case e1000_pch2lan: 2792 case e1000_pch_lpt: 2793 case e1000_pch_spt: 2794 case e1000_pch_cnp: 2795 case e1000_pch_tgp: 2796 case e1000_pch_adp: 2797 case e1000_pch_mtp: 2798 case e1000_pch_ptp: 2799 hw->fc.high_water = 0x5C20; 2800 hw->fc.low_water = 0x5048; 2801 hw->fc.pause_time = 0x0650; 2802 hw->fc.refresh_time = 0x0400; 2803 /* Jumbos need adjusted PBA */ 2804 if (if_getmtu(ifp) > ETHERMTU) 2805 E1000_WRITE_REG(hw, E1000_PBA, 12); 2806 else 2807 E1000_WRITE_REG(hw, E1000_PBA, 26); 2808 break; 2809 case e1000_82575: 2810 case e1000_82576: 2811 /* 8-byte granularity */ 2812 hw->fc.low_water = hw->fc.high_water - 8; 2813 break; 2814 case e1000_82580: 2815 case e1000_i350: 2816 case e1000_i354: 2817 case e1000_i210: 2818 case e1000_i211: 2819 case e1000_vfadapt: 2820 case e1000_vfadapt_i350: 2821 /* 16-byte granularity */ 2822 hw->fc.low_water = hw->fc.high_water - 16; 2823 break; 2824 case e1000_ich9lan: 2825 case e1000_ich10lan: 2826 if (if_getmtu(ifp) > ETHERMTU) { 2827 hw->fc.high_water = 0x2800; 2828 hw->fc.low_water = hw->fc.high_water - 8; 2829 break; 2830 } 2831 /* FALLTHROUGH */ 2832 default: 2833 if (hw->mac.type == e1000_80003es2lan) 2834 hw->fc.pause_time = 0xFFFF; 2835 break; 2836 } 2837 2838 /* I219 needs some special flushing to avoid hangs */ 2839 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2840 em_flush_desc_rings(sc); 2841 2842 /* Issue a global reset */ 2843 e1000_reset_hw(hw); 2844 if (hw->mac.type >= igb_mac_min) { 2845 E1000_WRITE_REG(hw, E1000_WUC, 0); 2846 } else { 2847 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2848 em_disable_aspm(sc); 2849 } 2850 if (sc->flags & IGB_MEDIA_RESET) { 2851 e1000_setup_init_funcs(hw, true); 2852 e1000_get_bus_info(hw); 2853 sc->flags &= ~IGB_MEDIA_RESET; 2854 } 2855 /* and a re-init */ 2856 if (e1000_init_hw(hw) < 0) { 2857 device_printf(dev, "Hardware Initialization Failed\n"); 2858 return; 2859 } 2860 if (hw->mac.type >= igb_mac_min) 2861 igb_init_dmac(sc, pba); 2862 2863 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2864 e1000_get_phy_info(hw); 2865 e1000_check_for_link(hw); 2866 } 2867 2868 /* 2869 * Initialise the RSS mapping for NICs that support multiple transmit/ 2870 * receive rings. 2871 */ 2872 2873 #define RSSKEYLEN 10 2874 static void 2875 em_initialize_rss_mapping(struct e1000_softc *sc) 2876 { 2877 uint8_t rss_key[4 * RSSKEYLEN]; 2878 uint32_t reta = 0; 2879 struct e1000_hw *hw = &sc->hw; 2880 int i; 2881 2882 /* 2883 * Configure RSS key 2884 */ 2885 arc4rand(rss_key, sizeof(rss_key), 0); 2886 for (i = 0; i < RSSKEYLEN; ++i) { 2887 uint32_t rssrk = 0; 2888 2889 rssrk = EM_RSSRK_VAL(rss_key, i); 2890 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2891 } 2892 2893 /* 2894 * Configure RSS redirect table in following fashion: 2895 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2896 */ 2897 for (i = 0; i < sizeof(reta); ++i) { 2898 uint32_t q; 2899 2900 q = (i % sc->rx_num_queues) << 7; 2901 reta |= q << (8 * i); 2902 } 2903 2904 for (i = 0; i < 32; ++i) 2905 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2906 2907 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2908 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2909 E1000_MRQC_RSS_FIELD_IPV4 | 2910 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2911 E1000_MRQC_RSS_FIELD_IPV6_EX | 2912 E1000_MRQC_RSS_FIELD_IPV6); 2913 } 2914 2915 static void 2916 igb_initialize_rss_mapping(struct e1000_softc *sc) 2917 { 2918 struct e1000_hw *hw = &sc->hw; 2919 int i; 2920 int queue_id; 2921 u32 reta; 2922 u32 rss_key[10], mrqc, shift = 0; 2923 2924 /* XXX? */ 2925 if (hw->mac.type == e1000_82575) 2926 shift = 6; 2927 2928 /* 2929 * The redirection table controls which destination 2930 * queue each bucket redirects traffic to. 2931 * Each DWORD represents four queues, with the LSB 2932 * being the first queue in the DWORD. 2933 * 2934 * This just allocates buckets to queues using round-robin 2935 * allocation. 2936 * 2937 * NOTE: It Just Happens to line up with the default 2938 * RSS allocation method. 2939 */ 2940 2941 /* Warning FM follows */ 2942 reta = 0; 2943 for (i = 0; i < 128; i++) { 2944 #ifdef RSS 2945 queue_id = rss_get_indirection_to_bucket(i); 2946 /* 2947 * If we have more queues than buckets, we'll 2948 * end up mapping buckets to a subset of the 2949 * queues. 2950 * 2951 * If we have more buckets than queues, we'll 2952 * end up instead assigning multiple buckets 2953 * to queues. 2954 * 2955 * Both are suboptimal, but we need to handle 2956 * the case so we don't go out of bounds 2957 * indexing arrays and such. 2958 */ 2959 queue_id = queue_id % sc->rx_num_queues; 2960 #else 2961 queue_id = (i % sc->rx_num_queues); 2962 #endif 2963 /* Adjust if required */ 2964 queue_id = queue_id << shift; 2965 2966 /* 2967 * The low 8 bits are for hash value (n+0); 2968 * The next 8 bits are for hash value (n+1), etc. 2969 */ 2970 reta = reta >> 8; 2971 reta = reta | ( ((uint32_t) queue_id) << 24); 2972 if ((i & 3) == 3) { 2973 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2974 reta = 0; 2975 } 2976 } 2977 2978 /* Now fill in hash table */ 2979 2980 /* 2981 * MRQC: Multiple Receive Queues Command 2982 * Set queuing to RSS control, number depends on the device. 2983 */ 2984 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2985 2986 #ifdef RSS 2987 /* XXX ew typecasting */ 2988 rss_getkey((uint8_t *) &rss_key); 2989 #else 2990 arc4rand(&rss_key, sizeof(rss_key), 0); 2991 #endif 2992 for (i = 0; i < 10; i++) 2993 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2994 2995 /* 2996 * Configure the RSS fields to hash upon. 2997 */ 2998 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2999 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3000 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3001 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3002 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3003 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3004 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3005 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3006 3007 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3008 } 3009 3010 /********************************************************************* 3011 * 3012 * Setup networking device structure and register interface media. 3013 * 3014 **********************************************************************/ 3015 static int 3016 em_setup_interface(if_ctx_t ctx) 3017 { 3018 if_t ifp = iflib_get_ifp(ctx); 3019 struct e1000_softc *sc = iflib_get_softc(ctx); 3020 if_softc_ctx_t scctx = sc->shared; 3021 3022 INIT_DEBUGOUT("em_setup_interface: begin"); 3023 3024 /* Single Queue */ 3025 if (sc->tx_num_queues == 1) { 3026 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3027 if_setsendqready(ifp); 3028 } 3029 3030 /* 3031 * Specify the media types supported by this adapter and register 3032 * callbacks to update media and link information 3033 */ 3034 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3035 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3036 u_char fiber_type = IFM_1000_SX; /* default type */ 3037 3038 if (sc->hw.mac.type == e1000_82545) 3039 fiber_type = IFM_1000_LX; 3040 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3041 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3042 } else { 3043 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3044 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3045 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3046 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3047 if (sc->hw.phy.type != e1000_phy_ife) { 3048 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3049 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3050 } 3051 } 3052 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3053 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3054 return (0); 3055 } 3056 3057 static int 3058 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3059 { 3060 struct e1000_softc *sc = iflib_get_softc(ctx); 3061 if_softc_ctx_t scctx = sc->shared; 3062 int error = E1000_SUCCESS; 3063 struct em_tx_queue *que; 3064 int i, j; 3065 3066 MPASS(sc->tx_num_queues > 0); 3067 MPASS(sc->tx_num_queues == ntxqsets); 3068 3069 /* First allocate the top level queue structs */ 3070 if (!(sc->tx_queues = 3071 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3072 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3073 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3074 return(ENOMEM); 3075 } 3076 3077 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3078 /* Set up some basics */ 3079 3080 struct tx_ring *txr = &que->txr; 3081 txr->sc = que->sc = sc; 3082 que->me = txr->me = i; 3083 3084 /* Allocate report status array */ 3085 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3086 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3087 error = ENOMEM; 3088 goto fail; 3089 } 3090 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3091 txr->tx_rsq[j] = QIDX_INVALID; 3092 /* get the virtual and physical address of the hardware queues */ 3093 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3094 txr->tx_paddr = paddrs[i*ntxqs]; 3095 } 3096 3097 if (bootverbose) 3098 device_printf(iflib_get_dev(ctx), 3099 "allocated for %d tx_queues\n", sc->tx_num_queues); 3100 return (0); 3101 fail: 3102 em_if_queues_free(ctx); 3103 return (error); 3104 } 3105 3106 static int 3107 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3108 { 3109 struct e1000_softc *sc = iflib_get_softc(ctx); 3110 int error = E1000_SUCCESS; 3111 struct em_rx_queue *que; 3112 int i; 3113 3114 MPASS(sc->rx_num_queues > 0); 3115 MPASS(sc->rx_num_queues == nrxqsets); 3116 3117 /* First allocate the top level queue structs */ 3118 if (!(sc->rx_queues = 3119 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3120 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3121 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3122 error = ENOMEM; 3123 goto fail; 3124 } 3125 3126 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3127 /* Set up some basics */ 3128 struct rx_ring *rxr = &que->rxr; 3129 rxr->sc = que->sc = sc; 3130 rxr->que = que; 3131 que->me = rxr->me = i; 3132 3133 /* get the virtual and physical address of the hardware queues */ 3134 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3135 rxr->rx_paddr = paddrs[i*nrxqs]; 3136 } 3137 3138 if (bootverbose) 3139 device_printf(iflib_get_dev(ctx), 3140 "allocated for %d rx_queues\n", sc->rx_num_queues); 3141 3142 return (0); 3143 fail: 3144 em_if_queues_free(ctx); 3145 return (error); 3146 } 3147 3148 static void 3149 em_if_queues_free(if_ctx_t ctx) 3150 { 3151 struct e1000_softc *sc = iflib_get_softc(ctx); 3152 struct em_tx_queue *tx_que = sc->tx_queues; 3153 struct em_rx_queue *rx_que = sc->rx_queues; 3154 3155 if (tx_que != NULL) { 3156 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3157 struct tx_ring *txr = &tx_que->txr; 3158 if (txr->tx_rsq == NULL) 3159 break; 3160 3161 free(txr->tx_rsq, M_DEVBUF); 3162 txr->tx_rsq = NULL; 3163 } 3164 free(sc->tx_queues, M_DEVBUF); 3165 sc->tx_queues = NULL; 3166 } 3167 3168 if (rx_que != NULL) { 3169 free(sc->rx_queues, M_DEVBUF); 3170 sc->rx_queues = NULL; 3171 } 3172 } 3173 3174 /********************************************************************* 3175 * 3176 * Enable transmit unit. 3177 * 3178 **********************************************************************/ 3179 static void 3180 em_initialize_transmit_unit(if_ctx_t ctx) 3181 { 3182 struct e1000_softc *sc = iflib_get_softc(ctx); 3183 if_softc_ctx_t scctx = sc->shared; 3184 struct em_tx_queue *que; 3185 struct tx_ring *txr; 3186 struct e1000_hw *hw = &sc->hw; 3187 u32 tctl, txdctl = 0, tarc, tipg = 0; 3188 3189 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3190 3191 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3192 u64 bus_addr; 3193 caddr_t offp, endp; 3194 3195 que = &sc->tx_queues[i]; 3196 txr = &que->txr; 3197 bus_addr = txr->tx_paddr; 3198 3199 /* Clear checksum offload context. */ 3200 offp = (caddr_t)&txr->csum_flags; 3201 endp = (caddr_t)(txr + 1); 3202 bzero(offp, endp - offp); 3203 3204 /* Base and Len of TX Ring */ 3205 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3206 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3207 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3208 (u32)(bus_addr >> 32)); 3209 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3210 (u32)bus_addr); 3211 /* Init the HEAD/TAIL indices */ 3212 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3213 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3214 3215 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3216 E1000_READ_REG(hw, E1000_TDBAL(i)), 3217 E1000_READ_REG(hw, E1000_TDLEN(i))); 3218 3219 txdctl = 0; /* clear txdctl */ 3220 txdctl |= 0x1f; /* PTHRESH */ 3221 txdctl |= 1 << 8; /* HTHRESH */ 3222 txdctl |= 1 << 16;/* WTHRESH */ 3223 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3224 txdctl |= E1000_TXDCTL_GRAN; 3225 txdctl |= 1 << 25; /* LWTHRESH */ 3226 3227 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3228 } 3229 3230 /* Set the default values for the Tx Inter Packet Gap timer */ 3231 switch (hw->mac.type) { 3232 case e1000_80003es2lan: 3233 tipg = DEFAULT_82543_TIPG_IPGR1; 3234 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3235 E1000_TIPG_IPGR2_SHIFT; 3236 break; 3237 case e1000_82542: 3238 tipg = DEFAULT_82542_TIPG_IPGT; 3239 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3240 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3241 break; 3242 default: 3243 if (hw->phy.media_type == e1000_media_type_fiber || 3244 hw->phy.media_type == e1000_media_type_internal_serdes) 3245 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3246 else 3247 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3248 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3249 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3250 } 3251 3252 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3253 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3254 3255 if(hw->mac.type >= e1000_82540) 3256 E1000_WRITE_REG(hw, E1000_TADV, 3257 sc->tx_abs_int_delay.value); 3258 3259 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3260 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3261 tarc |= TARC_SPEED_MODE_BIT; 3262 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3263 } else if (hw->mac.type == e1000_80003es2lan) { 3264 /* errata: program both queues to unweighted RR */ 3265 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3266 tarc |= 1; 3267 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3268 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3269 tarc |= 1; 3270 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3271 } else if (hw->mac.type == e1000_82574) { 3272 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3273 tarc |= TARC_ERRATA_BIT; 3274 if ( sc->tx_num_queues > 1) { 3275 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3276 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3277 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3278 } else 3279 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3280 } 3281 3282 if (sc->tx_int_delay.value > 0) 3283 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3284 3285 /* Program the Transmit Control Register */ 3286 tctl = E1000_READ_REG(hw, E1000_TCTL); 3287 tctl &= ~E1000_TCTL_CT; 3288 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3289 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3290 3291 if (hw->mac.type >= e1000_82571) 3292 tctl |= E1000_TCTL_MULR; 3293 3294 /* This write will effectively turn on the transmit unit. */ 3295 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3296 3297 /* SPT and KBL errata workarounds */ 3298 if (hw->mac.type == e1000_pch_spt) { 3299 u32 reg; 3300 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3301 reg |= E1000_RCTL_RDMTS_HEX; 3302 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3303 /* i218-i219 Specification Update 1.5.4.5 */ 3304 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3305 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3306 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3307 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3308 } 3309 } 3310 3311 /********************************************************************* 3312 * 3313 * Enable receive unit. 3314 * 3315 **********************************************************************/ 3316 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3317 3318 static void 3319 em_initialize_receive_unit(if_ctx_t ctx) 3320 { 3321 struct e1000_softc *sc = iflib_get_softc(ctx); 3322 if_softc_ctx_t scctx = sc->shared; 3323 if_t ifp = iflib_get_ifp(ctx); 3324 struct e1000_hw *hw = &sc->hw; 3325 struct em_rx_queue *que; 3326 int i; 3327 uint32_t rctl, rxcsum; 3328 3329 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3330 3331 /* 3332 * Make sure receives are disabled while setting 3333 * up the descriptor ring 3334 */ 3335 rctl = E1000_READ_REG(hw, E1000_RCTL); 3336 /* Do not disable if ever enabled on this hardware */ 3337 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3338 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3339 3340 /* Setup the Receive Control Register */ 3341 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3342 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3343 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3344 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3345 3346 /* Do not store bad packets */ 3347 rctl &= ~E1000_RCTL_SBP; 3348 3349 /* Enable Long Packet receive */ 3350 if (if_getmtu(ifp) > ETHERMTU) 3351 rctl |= E1000_RCTL_LPE; 3352 else 3353 rctl &= ~E1000_RCTL_LPE; 3354 3355 /* Strip the CRC */ 3356 if (!em_disable_crc_stripping) 3357 rctl |= E1000_RCTL_SECRC; 3358 3359 if (hw->mac.type >= e1000_82540) { 3360 E1000_WRITE_REG(hw, E1000_RADV, 3361 sc->rx_abs_int_delay.value); 3362 3363 /* 3364 * Set the interrupt throttling rate. Value is calculated 3365 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3366 */ 3367 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3368 } 3369 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3370 3371 if (hw->mac.type >= em_mac_min) { 3372 uint32_t rfctl; 3373 /* Use extended rx descriptor formats */ 3374 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3375 rfctl |= E1000_RFCTL_EXTEN; 3376 3377 /* 3378 * When using MSI-X interrupts we need to throttle 3379 * using the EITR register (82574 only) 3380 */ 3381 if (hw->mac.type == e1000_82574) { 3382 for (int i = 0; i < 4; i++) 3383 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3384 DEFAULT_ITR); 3385 /* Disable accelerated acknowledge */ 3386 rfctl |= E1000_RFCTL_ACK_DIS; 3387 } 3388 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3389 } 3390 3391 /* Set up L3 and L4 csum Rx descriptor offloads */ 3392 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3393 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3394 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3395 if (hw->mac.type > e1000_82575) 3396 rxcsum |= E1000_RXCSUM_CRCOFL; 3397 else if (hw->mac.type < em_mac_min && 3398 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3399 rxcsum |= E1000_RXCSUM_IPV6OFL; 3400 } else { 3401 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3402 if (hw->mac.type > e1000_82575) 3403 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3404 else if (hw->mac.type < em_mac_min) 3405 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3406 } 3407 3408 if (sc->rx_num_queues > 1) { 3409 /* RSS hash needed in the Rx descriptor */ 3410 rxcsum |= E1000_RXCSUM_PCSD; 3411 3412 if (hw->mac.type >= igb_mac_min) 3413 igb_initialize_rss_mapping(sc); 3414 else 3415 em_initialize_rss_mapping(sc); 3416 } 3417 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3418 3419 /* 3420 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3421 * long latencies are observed, like Lenovo X60. This 3422 * change eliminates the problem, but since having positive 3423 * values in RDTR is a known source of problems on other 3424 * platforms another solution is being sought. 3425 */ 3426 if (hw->mac.type == e1000_82573) 3427 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3428 3429 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3430 struct rx_ring *rxr = &que->rxr; 3431 /* Setup the Base and Length of the Rx Descriptor Ring */ 3432 u64 bus_addr = rxr->rx_paddr; 3433 #if 0 3434 u32 rdt = sc->rx_num_queues -1; /* default */ 3435 #endif 3436 3437 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3438 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3439 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3440 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3441 /* Setup the Head and Tail Descriptor Pointers */ 3442 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3443 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3444 } 3445 3446 /* 3447 * Set PTHRESH for improved jumbo performance 3448 * According to 10.2.5.11 of Intel 82574 Datasheet, 3449 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3450 * Only write to RXDCTL(1) if there is a need for different 3451 * settings. 3452 */ 3453 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3454 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3455 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3456 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3457 } else if (hw->mac.type == e1000_82574) { 3458 for (int i = 0; i < sc->rx_num_queues; i++) { 3459 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3460 rxdctl |= 0x20; /* PTHRESH */ 3461 rxdctl |= 4 << 8; /* HTHRESH */ 3462 rxdctl |= 4 << 16;/* WTHRESH */ 3463 rxdctl |= 1 << 24; /* Switch to granularity */ 3464 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3465 } 3466 } else if (hw->mac.type >= igb_mac_min) { 3467 u32 psize, srrctl = 0; 3468 3469 if (if_getmtu(ifp) > ETHERMTU) { 3470 psize = scctx->isc_max_frame_size; 3471 /* are we on a vlan? */ 3472 if (if_vlantrunkinuse(ifp)) 3473 psize += VLAN_TAG_SIZE; 3474 3475 if (sc->vf_ifp) 3476 e1000_rlpml_set_vf(hw, psize); 3477 else 3478 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3479 } 3480 3481 /* Set maximum packet buffer len */ 3482 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3483 E1000_SRRCTL_BSIZEPKT_SHIFT; 3484 3485 /* 3486 * If TX flow control is disabled and there's >1 queue defined, 3487 * enable DROP. 3488 * 3489 * This drops frames rather than hanging the RX MAC for all queues. 3490 */ 3491 if ((sc->rx_num_queues > 1) && 3492 (sc->fc == e1000_fc_none || 3493 sc->fc == e1000_fc_rx_pause)) { 3494 srrctl |= E1000_SRRCTL_DROP_EN; 3495 } 3496 /* Setup the Base and Length of the Rx Descriptor Rings */ 3497 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3498 struct rx_ring *rxr = &que->rxr; 3499 u64 bus_addr = rxr->rx_paddr; 3500 u32 rxdctl; 3501 3502 #ifdef notyet 3503 /* Configure for header split? -- ignore for now */ 3504 rxr->hdr_split = igb_header_split; 3505 #else 3506 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3507 #endif 3508 3509 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3510 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3511 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3512 (uint32_t)(bus_addr >> 32)); 3513 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3514 (uint32_t)bus_addr); 3515 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3516 /* Enable this Queue */ 3517 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3518 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3519 rxdctl &= 0xFFF00000; 3520 rxdctl |= IGB_RX_PTHRESH; 3521 rxdctl |= IGB_RX_HTHRESH << 8; 3522 rxdctl |= IGB_RX_WTHRESH << 16; 3523 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3524 } 3525 } else if (hw->mac.type >= e1000_pch2lan) { 3526 if (if_getmtu(ifp) > ETHERMTU) 3527 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3528 else 3529 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3530 } 3531 3532 /* Make sure VLAN Filters are off */ 3533 rctl &= ~E1000_RCTL_VFE; 3534 3535 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3536 if (hw->mac.type < igb_mac_min) { 3537 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3538 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3539 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3540 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3541 else if (sc->rx_mbuf_sz > 8192) 3542 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3543 else { 3544 rctl |= E1000_RCTL_SZ_2048; 3545 rctl &= ~E1000_RCTL_BSEX; 3546 } 3547 } else 3548 rctl |= E1000_RCTL_SZ_2048; 3549 3550 /* 3551 * rctl bits 11:10 are as follows 3552 * lem: reserved 3553 * em: DTYPE 3554 * igb: reserved 3555 * and should be 00 on all of the above 3556 */ 3557 rctl &= ~0x00000C00; 3558 3559 /* Write out the settings */ 3560 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3561 3562 return; 3563 } 3564 3565 static void 3566 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3567 { 3568 struct e1000_softc *sc = iflib_get_softc(ctx); 3569 u32 index, bit; 3570 3571 index = (vtag >> 5) & 0x7F; 3572 bit = vtag & 0x1F; 3573 sc->shadow_vfta[index] |= (1 << bit); 3574 ++sc->num_vlans; 3575 em_if_vlan_filter_write(sc); 3576 } 3577 3578 static void 3579 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3580 { 3581 struct e1000_softc *sc = iflib_get_softc(ctx); 3582 u32 index, bit; 3583 3584 index = (vtag >> 5) & 0x7F; 3585 bit = vtag & 0x1F; 3586 sc->shadow_vfta[index] &= ~(1 << bit); 3587 --sc->num_vlans; 3588 em_if_vlan_filter_write(sc); 3589 } 3590 3591 static bool 3592 em_if_vlan_filter_capable(if_ctx_t ctx) 3593 { 3594 if_t ifp = iflib_get_ifp(ctx); 3595 3596 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3597 !em_disable_crc_stripping) 3598 return (true); 3599 3600 return (false); 3601 } 3602 3603 static bool 3604 em_if_vlan_filter_used(if_ctx_t ctx) 3605 { 3606 struct e1000_softc *sc = iflib_get_softc(ctx); 3607 3608 if (!em_if_vlan_filter_capable(ctx)) 3609 return (false); 3610 3611 for (int i = 0; i < EM_VFTA_SIZE; i++) 3612 if (sc->shadow_vfta[i] != 0) 3613 return (true); 3614 3615 return (false); 3616 } 3617 3618 static void 3619 em_if_vlan_filter_enable(struct e1000_softc *sc) 3620 { 3621 struct e1000_hw *hw = &sc->hw; 3622 u32 reg; 3623 3624 reg = E1000_READ_REG(hw, E1000_RCTL); 3625 reg &= ~E1000_RCTL_CFIEN; 3626 reg |= E1000_RCTL_VFE; 3627 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3628 } 3629 3630 static void 3631 em_if_vlan_filter_disable(struct e1000_softc *sc) 3632 { 3633 struct e1000_hw *hw = &sc->hw; 3634 u32 reg; 3635 3636 reg = E1000_READ_REG(hw, E1000_RCTL); 3637 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3638 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3639 } 3640 3641 static void 3642 em_if_vlan_filter_write(struct e1000_softc *sc) 3643 { 3644 struct e1000_hw *hw = &sc->hw; 3645 3646 if (sc->vf_ifp) 3647 return; 3648 3649 /* Disable interrupts for lem-class devices during the filter change */ 3650 if (hw->mac.type < em_mac_min) 3651 em_if_intr_disable(sc->ctx); 3652 3653 for (int i = 0; i < EM_VFTA_SIZE; i++) 3654 if (sc->shadow_vfta[i] != 0) { 3655 /* XXXKB: incomplete VF support, we return early above */ 3656 if (sc->vf_ifp) 3657 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3658 else 3659 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3660 } 3661 3662 /* Re-enable interrupts for lem-class devices */ 3663 if (hw->mac.type < em_mac_min) 3664 em_if_intr_enable(sc->ctx); 3665 } 3666 3667 static void 3668 em_setup_vlan_hw_support(if_ctx_t ctx) 3669 { 3670 struct e1000_softc *sc = iflib_get_softc(ctx); 3671 struct e1000_hw *hw = &sc->hw; 3672 if_t ifp = iflib_get_ifp(ctx); 3673 u32 reg; 3674 3675 /* XXXKB: Return early if we are a VF until VF decap and filter management 3676 * is ready and tested. 3677 */ 3678 if (sc->vf_ifp) 3679 return; 3680 3681 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3682 !em_disable_crc_stripping) { 3683 reg = E1000_READ_REG(hw, E1000_CTRL); 3684 reg |= E1000_CTRL_VME; 3685 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3686 } else { 3687 reg = E1000_READ_REG(hw, E1000_CTRL); 3688 reg &= ~E1000_CTRL_VME; 3689 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3690 } 3691 3692 /* If we aren't doing HW filtering, we're done */ 3693 if (!em_if_vlan_filter_capable(ctx)) { 3694 em_if_vlan_filter_disable(sc); 3695 return; 3696 } 3697 3698 /* 3699 * A soft reset zero's out the VFTA, so 3700 * we need to repopulate it now. 3701 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3702 * traffic through. This will write the entire table. 3703 */ 3704 em_if_vlan_register(ctx, 0); 3705 3706 /* Enable the Filter Table */ 3707 em_if_vlan_filter_enable(sc); 3708 } 3709 3710 static void 3711 em_if_intr_enable(if_ctx_t ctx) 3712 { 3713 struct e1000_softc *sc = iflib_get_softc(ctx); 3714 struct e1000_hw *hw = &sc->hw; 3715 u32 ims_mask = IMS_ENABLE_MASK; 3716 3717 if (sc->intr_type == IFLIB_INTR_MSIX) { 3718 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3719 ims_mask |= sc->ims; 3720 } 3721 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3722 E1000_WRITE_FLUSH(hw); 3723 } 3724 3725 static void 3726 em_if_intr_disable(if_ctx_t ctx) 3727 { 3728 struct e1000_softc *sc = iflib_get_softc(ctx); 3729 struct e1000_hw *hw = &sc->hw; 3730 3731 if (sc->intr_type == IFLIB_INTR_MSIX) 3732 E1000_WRITE_REG(hw, EM_EIAC, 0); 3733 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3734 E1000_WRITE_FLUSH(hw); 3735 } 3736 3737 static void 3738 igb_if_intr_enable(if_ctx_t ctx) 3739 { 3740 struct e1000_softc *sc = iflib_get_softc(ctx); 3741 struct e1000_hw *hw = &sc->hw; 3742 u32 mask; 3743 3744 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3745 mask = (sc->que_mask | sc->link_mask); 3746 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3747 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3748 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3749 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3750 } else 3751 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3752 E1000_WRITE_FLUSH(hw); 3753 } 3754 3755 static void 3756 igb_if_intr_disable(if_ctx_t ctx) 3757 { 3758 struct e1000_softc *sc = iflib_get_softc(ctx); 3759 struct e1000_hw *hw = &sc->hw; 3760 3761 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3762 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3763 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3764 } 3765 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3766 E1000_WRITE_FLUSH(hw); 3767 } 3768 3769 /* 3770 * Bit of a misnomer, what this really means is 3771 * to enable OS management of the system... aka 3772 * to disable special hardware management features 3773 */ 3774 static void 3775 em_init_manageability(struct e1000_softc *sc) 3776 { 3777 /* A shared code workaround */ 3778 #define E1000_82542_MANC2H E1000_MANC2H 3779 if (sc->has_manage) { 3780 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3781 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3782 3783 /* disable hardware interception of ARP */ 3784 manc &= ~(E1000_MANC_ARP_EN); 3785 3786 /* enable receiving management packets to the host */ 3787 manc |= E1000_MANC_EN_MNG2HOST; 3788 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3789 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3790 manc2h |= E1000_MNG2HOST_PORT_623; 3791 manc2h |= E1000_MNG2HOST_PORT_664; 3792 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3793 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3794 } 3795 } 3796 3797 /* 3798 * Give control back to hardware management 3799 * controller if there is one. 3800 */ 3801 static void 3802 em_release_manageability(struct e1000_softc *sc) 3803 { 3804 if (sc->has_manage) { 3805 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3806 3807 /* re-enable hardware interception of ARP */ 3808 manc |= E1000_MANC_ARP_EN; 3809 manc &= ~E1000_MANC_EN_MNG2HOST; 3810 3811 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3812 } 3813 } 3814 3815 /* 3816 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3817 * For ASF and Pass Through versions of f/w this means 3818 * that the driver is loaded. For AMT version type f/w 3819 * this means that the network i/f is open. 3820 */ 3821 static void 3822 em_get_hw_control(struct e1000_softc *sc) 3823 { 3824 u32 ctrl_ext, swsm; 3825 3826 if (sc->vf_ifp) 3827 return; 3828 3829 if (sc->hw.mac.type == e1000_82573) { 3830 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3831 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3832 swsm | E1000_SWSM_DRV_LOAD); 3833 return; 3834 } 3835 /* else */ 3836 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3837 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3838 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3839 } 3840 3841 /* 3842 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3843 * For ASF and Pass Through versions of f/w this means that 3844 * the driver is no longer loaded. For AMT versions of the 3845 * f/w this means that the network i/f is closed. 3846 */ 3847 static void 3848 em_release_hw_control(struct e1000_softc *sc) 3849 { 3850 u32 ctrl_ext, swsm; 3851 3852 if (!sc->has_manage) 3853 return; 3854 3855 if (sc->hw.mac.type == e1000_82573) { 3856 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3857 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3858 swsm & ~E1000_SWSM_DRV_LOAD); 3859 return; 3860 } 3861 /* else */ 3862 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3863 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3864 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3865 return; 3866 } 3867 3868 static int 3869 em_is_valid_ether_addr(u8 *addr) 3870 { 3871 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3872 3873 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3874 return (false); 3875 } 3876 3877 return (true); 3878 } 3879 3880 /* 3881 ** Parse the interface capabilities with regard 3882 ** to both system management and wake-on-lan for 3883 ** later use. 3884 */ 3885 static void 3886 em_get_wakeup(if_ctx_t ctx) 3887 { 3888 struct e1000_softc *sc = iflib_get_softc(ctx); 3889 device_t dev = iflib_get_dev(ctx); 3890 u16 eeprom_data = 0, device_id, apme_mask; 3891 3892 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3893 apme_mask = EM_EEPROM_APME; 3894 3895 switch (sc->hw.mac.type) { 3896 case e1000_82542: 3897 case e1000_82543: 3898 break; 3899 case e1000_82544: 3900 e1000_read_nvm(&sc->hw, 3901 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3902 apme_mask = EM_82544_APME; 3903 break; 3904 case e1000_82546: 3905 case e1000_82546_rev_3: 3906 if (sc->hw.bus.func == 1) { 3907 e1000_read_nvm(&sc->hw, 3908 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3909 break; 3910 } else 3911 e1000_read_nvm(&sc->hw, 3912 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3913 break; 3914 case e1000_82573: 3915 case e1000_82583: 3916 sc->has_amt = true; 3917 /* FALLTHROUGH */ 3918 case e1000_82571: 3919 case e1000_82572: 3920 case e1000_80003es2lan: 3921 if (sc->hw.bus.func == 1) { 3922 e1000_read_nvm(&sc->hw, 3923 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3924 break; 3925 } else 3926 e1000_read_nvm(&sc->hw, 3927 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3928 break; 3929 case e1000_ich8lan: 3930 case e1000_ich9lan: 3931 case e1000_ich10lan: 3932 case e1000_pchlan: 3933 case e1000_pch2lan: 3934 case e1000_pch_lpt: 3935 case e1000_pch_spt: 3936 case e1000_82575: /* listing all igb devices */ 3937 case e1000_82576: 3938 case e1000_82580: 3939 case e1000_i350: 3940 case e1000_i354: 3941 case e1000_i210: 3942 case e1000_i211: 3943 case e1000_vfadapt: 3944 case e1000_vfadapt_i350: 3945 apme_mask = E1000_WUC_APME; 3946 sc->has_amt = true; 3947 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3948 break; 3949 default: 3950 e1000_read_nvm(&sc->hw, 3951 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3952 break; 3953 } 3954 if (eeprom_data & apme_mask) 3955 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3956 /* 3957 * We have the eeprom settings, now apply the special cases 3958 * where the eeprom may be wrong or the board won't support 3959 * wake on lan on a particular port 3960 */ 3961 device_id = pci_get_device(dev); 3962 switch (device_id) { 3963 case E1000_DEV_ID_82546GB_PCIE: 3964 sc->wol = 0; 3965 break; 3966 case E1000_DEV_ID_82546EB_FIBER: 3967 case E1000_DEV_ID_82546GB_FIBER: 3968 /* Wake events only supported on port A for dual fiber 3969 * regardless of eeprom setting */ 3970 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3971 E1000_STATUS_FUNC_1) 3972 sc->wol = 0; 3973 break; 3974 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3975 /* if quad port adapter, disable WoL on all but port A */ 3976 if (global_quad_port_a != 0) 3977 sc->wol = 0; 3978 /* Reset for multiple quad port adapters */ 3979 if (++global_quad_port_a == 4) 3980 global_quad_port_a = 0; 3981 break; 3982 case E1000_DEV_ID_82571EB_FIBER: 3983 /* Wake events only supported on port A for dual fiber 3984 * regardless of eeprom setting */ 3985 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3986 E1000_STATUS_FUNC_1) 3987 sc->wol = 0; 3988 break; 3989 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3990 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3991 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3992 /* if quad port adapter, disable WoL on all but port A */ 3993 if (global_quad_port_a != 0) 3994 sc->wol = 0; 3995 /* Reset for multiple quad port adapters */ 3996 if (++global_quad_port_a == 4) 3997 global_quad_port_a = 0; 3998 break; 3999 } 4000 return; 4001 } 4002 4003 4004 /* 4005 * Enable PCI Wake On Lan capability 4006 */ 4007 static void 4008 em_enable_wakeup(if_ctx_t ctx) 4009 { 4010 struct e1000_softc *sc = iflib_get_softc(ctx); 4011 device_t dev = iflib_get_dev(ctx); 4012 if_t ifp = iflib_get_ifp(ctx); 4013 int error = 0; 4014 u32 pmc, ctrl, ctrl_ext, rctl; 4015 u16 status; 4016 4017 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4018 return; 4019 4020 /* 4021 * Determine type of Wakeup: note that wol 4022 * is set with all bits on by default. 4023 */ 4024 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4025 sc->wol &= ~E1000_WUFC_MAG; 4026 4027 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4028 sc->wol &= ~E1000_WUFC_EX; 4029 4030 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4031 sc->wol &= ~E1000_WUFC_MC; 4032 else { 4033 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4034 rctl |= E1000_RCTL_MPE; 4035 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4036 } 4037 4038 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4039 goto pme; 4040 4041 /* Advertise the wakeup capability */ 4042 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4043 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4044 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4045 4046 /* Keep the laser running on Fiber adapters */ 4047 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4048 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4049 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4050 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4051 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4052 } 4053 4054 if ((sc->hw.mac.type == e1000_ich8lan) || 4055 (sc->hw.mac.type == e1000_pchlan) || 4056 (sc->hw.mac.type == e1000_ich9lan) || 4057 (sc->hw.mac.type == e1000_ich10lan)) 4058 e1000_suspend_workarounds_ich8lan(&sc->hw); 4059 4060 if ( sc->hw.mac.type >= e1000_pchlan) { 4061 error = em_enable_phy_wakeup(sc); 4062 if (error) 4063 goto pme; 4064 } else { 4065 /* Enable wakeup by the MAC */ 4066 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4067 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4068 } 4069 4070 if (sc->hw.phy.type == e1000_phy_igp_3) 4071 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4072 4073 pme: 4074 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4075 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4076 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4077 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4078 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4079 4080 return; 4081 } 4082 4083 /* 4084 * WOL in the newer chipset interfaces (pchlan) 4085 * require thing to be copied into the phy 4086 */ 4087 static int 4088 em_enable_phy_wakeup(struct e1000_softc *sc) 4089 { 4090 struct e1000_hw *hw = &sc->hw; 4091 u32 mreg, ret = 0; 4092 u16 preg; 4093 4094 /* copy MAC RARs to PHY RARs */ 4095 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4096 4097 /* copy MAC MTA to PHY MTA */ 4098 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4099 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4100 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4101 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4102 (u16)((mreg >> 16) & 0xFFFF)); 4103 } 4104 4105 /* configure PHY Rx Control register */ 4106 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4107 mreg = E1000_READ_REG(hw, E1000_RCTL); 4108 if (mreg & E1000_RCTL_UPE) 4109 preg |= BM_RCTL_UPE; 4110 if (mreg & E1000_RCTL_MPE) 4111 preg |= BM_RCTL_MPE; 4112 preg &= ~(BM_RCTL_MO_MASK); 4113 if (mreg & E1000_RCTL_MO_3) 4114 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4115 << BM_RCTL_MO_SHIFT); 4116 if (mreg & E1000_RCTL_BAM) 4117 preg |= BM_RCTL_BAM; 4118 if (mreg & E1000_RCTL_PMCF) 4119 preg |= BM_RCTL_PMCF; 4120 mreg = E1000_READ_REG(hw, E1000_CTRL); 4121 if (mreg & E1000_CTRL_RFCE) 4122 preg |= BM_RCTL_RFCE; 4123 e1000_write_phy_reg(hw, BM_RCTL, preg); 4124 4125 /* enable PHY wakeup in MAC register */ 4126 E1000_WRITE_REG(hw, E1000_WUC, 4127 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4128 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4129 4130 /* configure and enable PHY wakeup in PHY registers */ 4131 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4132 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4133 4134 /* activate PHY wakeup */ 4135 ret = hw->phy.ops.acquire(hw); 4136 if (ret) { 4137 printf("Could not acquire PHY\n"); 4138 return ret; 4139 } 4140 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4141 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4142 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4143 if (ret) { 4144 printf("Could not read PHY page 769\n"); 4145 goto out; 4146 } 4147 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4148 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4149 if (ret) 4150 printf("Could not set PHY Host Wakeup bit\n"); 4151 out: 4152 hw->phy.ops.release(hw); 4153 4154 return ret; 4155 } 4156 4157 static void 4158 em_if_led_func(if_ctx_t ctx, int onoff) 4159 { 4160 struct e1000_softc *sc = iflib_get_softc(ctx); 4161 4162 if (onoff) { 4163 e1000_setup_led(&sc->hw); 4164 e1000_led_on(&sc->hw); 4165 } else { 4166 e1000_led_off(&sc->hw); 4167 e1000_cleanup_led(&sc->hw); 4168 } 4169 } 4170 4171 /* 4172 * Disable the L0S and L1 LINK states 4173 */ 4174 static void 4175 em_disable_aspm(struct e1000_softc *sc) 4176 { 4177 int base, reg; 4178 u16 link_cap,link_ctrl; 4179 device_t dev = sc->dev; 4180 4181 switch (sc->hw.mac.type) { 4182 case e1000_82573: 4183 case e1000_82574: 4184 case e1000_82583: 4185 break; 4186 default: 4187 return; 4188 } 4189 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4190 return; 4191 reg = base + PCIER_LINK_CAP; 4192 link_cap = pci_read_config(dev, reg, 2); 4193 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4194 return; 4195 reg = base + PCIER_LINK_CTL; 4196 link_ctrl = pci_read_config(dev, reg, 2); 4197 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4198 pci_write_config(dev, reg, link_ctrl, 2); 4199 return; 4200 } 4201 4202 /********************************************************************** 4203 * 4204 * Update the board statistics counters. 4205 * 4206 **********************************************************************/ 4207 static void 4208 em_update_stats_counters(struct e1000_softc *sc) 4209 { 4210 u64 prev_xoffrxc = sc->stats.xoffrxc; 4211 4212 if(sc->hw.phy.media_type == e1000_media_type_copper || 4213 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4214 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4215 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4216 } 4217 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4218 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4219 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4220 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4221 4222 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4223 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4224 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4225 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4226 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4227 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4228 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4229 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4230 /* 4231 ** For watchdog management we need to know if we have been 4232 ** paused during the last interval, so capture that here. 4233 */ 4234 if (sc->stats.xoffrxc != prev_xoffrxc) 4235 sc->shared->isc_pause_frames = 1; 4236 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4237 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4238 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4239 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4240 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4241 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4242 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4243 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4244 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4245 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4246 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4247 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4248 4249 /* For the 64-bit byte counters the low dword must be read first. */ 4250 /* Both registers clear on the read of the high dword */ 4251 4252 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4253 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4254 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4255 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4256 4257 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4258 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4259 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4260 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4261 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4262 4263 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4264 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4265 4266 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4267 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4268 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4269 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4270 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4271 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4272 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4273 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4274 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4275 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4276 4277 /* Interrupt Counts */ 4278 4279 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4280 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4281 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4282 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4283 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4284 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4285 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4286 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4287 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4288 4289 if (sc->hw.mac.type >= e1000_82543) { 4290 sc->stats.algnerrc += 4291 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4292 sc->stats.rxerrc += 4293 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4294 sc->stats.tncrs += 4295 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4296 sc->stats.cexterr += 4297 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4298 sc->stats.tsctc += 4299 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4300 sc->stats.tsctfc += 4301 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4302 } 4303 } 4304 4305 static uint64_t 4306 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4307 { 4308 struct e1000_softc *sc = iflib_get_softc(ctx); 4309 if_t ifp = iflib_get_ifp(ctx); 4310 4311 switch (cnt) { 4312 case IFCOUNTER_COLLISIONS: 4313 return (sc->stats.colc); 4314 case IFCOUNTER_IERRORS: 4315 return (sc->dropped_pkts + sc->stats.rxerrc + 4316 sc->stats.crcerrs + sc->stats.algnerrc + 4317 sc->stats.ruc + sc->stats.roc + 4318 sc->stats.mpc + sc->stats.cexterr); 4319 case IFCOUNTER_OERRORS: 4320 return (sc->stats.ecol + sc->stats.latecol + 4321 sc->watchdog_events); 4322 default: 4323 return (if_get_counter_default(ifp, cnt)); 4324 } 4325 } 4326 4327 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4328 * @ctx: iflib context 4329 * @event: event code to check 4330 * 4331 * Defaults to returning true for unknown events. 4332 * 4333 * @returns true if iflib needs to reinit the interface 4334 */ 4335 static bool 4336 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4337 { 4338 switch (event) { 4339 case IFLIB_RESTART_VLAN_CONFIG: 4340 return (false); 4341 default: 4342 return (true); 4343 } 4344 } 4345 4346 /* Export a single 32-bit register via a read-only sysctl. */ 4347 static int 4348 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4349 { 4350 struct e1000_softc *sc; 4351 u_int val; 4352 4353 sc = oidp->oid_arg1; 4354 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4355 return (sysctl_handle_int(oidp, &val, 0, req)); 4356 } 4357 4358 /* 4359 * Add sysctl variables, one per statistic, to the system. 4360 */ 4361 static void 4362 em_add_hw_stats(struct e1000_softc *sc) 4363 { 4364 device_t dev = iflib_get_dev(sc->ctx); 4365 struct em_tx_queue *tx_que = sc->tx_queues; 4366 struct em_rx_queue *rx_que = sc->rx_queues; 4367 4368 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4369 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4370 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4371 struct e1000_hw_stats *stats = &sc->stats; 4372 4373 struct sysctl_oid *stat_node, *queue_node, *int_node; 4374 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4375 4376 #define QUEUE_NAME_LEN 32 4377 char namebuf[QUEUE_NAME_LEN]; 4378 4379 /* Driver Statistics */ 4380 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4381 CTLFLAG_RD, &sc->dropped_pkts, 4382 "Driver dropped packets"); 4383 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4384 CTLFLAG_RD, &sc->link_irq, 4385 "Link MSI-X IRQ Handled"); 4386 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4387 CTLFLAG_RD, &sc->rx_overruns, 4388 "RX overruns"); 4389 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4390 CTLFLAG_RD, &sc->watchdog_events, 4391 "Watchdog timeouts"); 4392 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4393 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4394 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4395 "Device Control Register"); 4396 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4397 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4398 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4399 "Receiver Control Register"); 4400 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4401 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4402 "Flow Control High Watermark"); 4403 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4404 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4405 "Flow Control Low Watermark"); 4406 4407 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4408 struct tx_ring *txr = &tx_que->txr; 4409 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4410 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4411 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4412 queue_list = SYSCTL_CHILDREN(queue_node); 4413 4414 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4415 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4416 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4417 "Transmit Descriptor Head"); 4418 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4419 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4420 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4421 "Transmit Descriptor Tail"); 4422 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4423 CTLFLAG_RD, &txr->tx_irq, 4424 "Queue MSI-X Transmit Interrupts"); 4425 } 4426 4427 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4428 struct rx_ring *rxr = &rx_que->rxr; 4429 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4430 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4431 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4432 queue_list = SYSCTL_CHILDREN(queue_node); 4433 4434 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4435 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4436 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4437 "Receive Descriptor Head"); 4438 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4439 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4440 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4441 "Receive Descriptor Tail"); 4442 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4443 CTLFLAG_RD, &rxr->rx_irq, 4444 "Queue MSI-X Receive Interrupts"); 4445 } 4446 4447 /* MAC stats get their own sub node */ 4448 4449 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4450 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4451 stat_list = SYSCTL_CHILDREN(stat_node); 4452 4453 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4454 CTLFLAG_RD, &stats->ecol, 4455 "Excessive collisions"); 4456 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4457 CTLFLAG_RD, &stats->scc, 4458 "Single collisions"); 4459 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4460 CTLFLAG_RD, &stats->mcc, 4461 "Multiple collisions"); 4462 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4463 CTLFLAG_RD, &stats->latecol, 4464 "Late collisions"); 4465 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4466 CTLFLAG_RD, &stats->colc, 4467 "Collision Count"); 4468 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4469 CTLFLAG_RD, &sc->stats.symerrs, 4470 "Symbol Errors"); 4471 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4472 CTLFLAG_RD, &sc->stats.sec, 4473 "Sequence Errors"); 4474 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4475 CTLFLAG_RD, &sc->stats.dc, 4476 "Defer Count"); 4477 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4478 CTLFLAG_RD, &sc->stats.mpc, 4479 "Missed Packets"); 4480 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4481 CTLFLAG_RD, &sc->stats.rnbc, 4482 "Receive No Buffers"); 4483 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4484 CTLFLAG_RD, &sc->stats.ruc, 4485 "Receive Undersize"); 4486 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4487 CTLFLAG_RD, &sc->stats.rfc, 4488 "Fragmented Packets Received "); 4489 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4490 CTLFLAG_RD, &sc->stats.roc, 4491 "Oversized Packets Received"); 4492 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4493 CTLFLAG_RD, &sc->stats.rjc, 4494 "Recevied Jabber"); 4495 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4496 CTLFLAG_RD, &sc->stats.rxerrc, 4497 "Receive Errors"); 4498 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4499 CTLFLAG_RD, &sc->stats.crcerrs, 4500 "CRC errors"); 4501 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4502 CTLFLAG_RD, &sc->stats.algnerrc, 4503 "Alignment Errors"); 4504 /* On 82575 these are collision counts */ 4505 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4506 CTLFLAG_RD, &sc->stats.cexterr, 4507 "Collision/Carrier extension errors"); 4508 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4509 CTLFLAG_RD, &sc->stats.xonrxc, 4510 "XON Received"); 4511 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4512 CTLFLAG_RD, &sc->stats.xontxc, 4513 "XON Transmitted"); 4514 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4515 CTLFLAG_RD, &sc->stats.xoffrxc, 4516 "XOFF Received"); 4517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4518 CTLFLAG_RD, &sc->stats.xofftxc, 4519 "XOFF Transmitted"); 4520 4521 /* Packet Reception Stats */ 4522 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4523 CTLFLAG_RD, &sc->stats.tpr, 4524 "Total Packets Received "); 4525 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4526 CTLFLAG_RD, &sc->stats.gprc, 4527 "Good Packets Received"); 4528 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4529 CTLFLAG_RD, &sc->stats.bprc, 4530 "Broadcast Packets Received"); 4531 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4532 CTLFLAG_RD, &sc->stats.mprc, 4533 "Multicast Packets Received"); 4534 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4535 CTLFLAG_RD, &sc->stats.prc64, 4536 "64 byte frames received "); 4537 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4538 CTLFLAG_RD, &sc->stats.prc127, 4539 "65-127 byte frames received"); 4540 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4541 CTLFLAG_RD, &sc->stats.prc255, 4542 "128-255 byte frames received"); 4543 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4544 CTLFLAG_RD, &sc->stats.prc511, 4545 "256-511 byte frames received"); 4546 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4547 CTLFLAG_RD, &sc->stats.prc1023, 4548 "512-1023 byte frames received"); 4549 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4550 CTLFLAG_RD, &sc->stats.prc1522, 4551 "1023-1522 byte frames received"); 4552 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4553 CTLFLAG_RD, &sc->stats.gorc, 4554 "Good Octets Received"); 4555 4556 /* Packet Transmission Stats */ 4557 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4558 CTLFLAG_RD, &sc->stats.gotc, 4559 "Good Octets Transmitted"); 4560 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4561 CTLFLAG_RD, &sc->stats.tpt, 4562 "Total Packets Transmitted"); 4563 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4564 CTLFLAG_RD, &sc->stats.gptc, 4565 "Good Packets Transmitted"); 4566 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4567 CTLFLAG_RD, &sc->stats.bptc, 4568 "Broadcast Packets Transmitted"); 4569 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4570 CTLFLAG_RD, &sc->stats.mptc, 4571 "Multicast Packets Transmitted"); 4572 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4573 CTLFLAG_RD, &sc->stats.ptc64, 4574 "64 byte frames transmitted "); 4575 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4576 CTLFLAG_RD, &sc->stats.ptc127, 4577 "65-127 byte frames transmitted"); 4578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4579 CTLFLAG_RD, &sc->stats.ptc255, 4580 "128-255 byte frames transmitted"); 4581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4582 CTLFLAG_RD, &sc->stats.ptc511, 4583 "256-511 byte frames transmitted"); 4584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4585 CTLFLAG_RD, &sc->stats.ptc1023, 4586 "512-1023 byte frames transmitted"); 4587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4588 CTLFLAG_RD, &sc->stats.ptc1522, 4589 "1024-1522 byte frames transmitted"); 4590 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4591 CTLFLAG_RD, &sc->stats.tsctc, 4592 "TSO Contexts Transmitted"); 4593 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4594 CTLFLAG_RD, &sc->stats.tsctfc, 4595 "TSO Contexts Failed"); 4596 4597 4598 /* Interrupt Stats */ 4599 4600 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4601 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4602 int_list = SYSCTL_CHILDREN(int_node); 4603 4604 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4605 CTLFLAG_RD, &sc->stats.iac, 4606 "Interrupt Assertion Count"); 4607 4608 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4609 CTLFLAG_RD, &sc->stats.icrxptc, 4610 "Interrupt Cause Rx Pkt Timer Expire Count"); 4611 4612 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4613 CTLFLAG_RD, &sc->stats.icrxatc, 4614 "Interrupt Cause Rx Abs Timer Expire Count"); 4615 4616 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4617 CTLFLAG_RD, &sc->stats.ictxptc, 4618 "Interrupt Cause Tx Pkt Timer Expire Count"); 4619 4620 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4621 CTLFLAG_RD, &sc->stats.ictxatc, 4622 "Interrupt Cause Tx Abs Timer Expire Count"); 4623 4624 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4625 CTLFLAG_RD, &sc->stats.ictxqec, 4626 "Interrupt Cause Tx Queue Empty Count"); 4627 4628 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4629 CTLFLAG_RD, &sc->stats.ictxqmtc, 4630 "Interrupt Cause Tx Queue Min Thresh Count"); 4631 4632 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4633 CTLFLAG_RD, &sc->stats.icrxdmtc, 4634 "Interrupt Cause Rx Desc Min Thresh Count"); 4635 4636 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4637 CTLFLAG_RD, &sc->stats.icrxoc, 4638 "Interrupt Cause Receiver Overrun Count"); 4639 } 4640 4641 static void 4642 em_fw_version_locked(if_ctx_t ctx) 4643 { 4644 struct e1000_softc *sc = iflib_get_softc(ctx); 4645 struct e1000_hw *hw = &sc->hw; 4646 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4647 uint16_t eep = 0; 4648 4649 /* 4650 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4651 * NVM locking model, so we do it in em_if_attach_pre() and store the 4652 * info in the softc 4653 */ 4654 ASSERT_CTX_LOCK_HELD(hw); 4655 4656 *fw_ver = (struct e1000_fw_version){0}; 4657 4658 if (hw->mac.type >= igb_mac_min) { 4659 /* 4660 * Use the Shared Code for igb(4) 4661 */ 4662 e1000_get_fw_version(hw, fw_ver); 4663 } else { 4664 /* 4665 * Otherwise, EEPROM version should be present on (almost?) all 4666 * devices here 4667 */ 4668 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4669 INIT_DEBUGOUT("can't get EEPROM version"); 4670 return; 4671 } 4672 4673 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4674 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4675 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4676 } 4677 } 4678 4679 static void 4680 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4681 { 4682 const char *space = ""; 4683 4684 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4685 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4686 fw_ver->eep_minor, fw_ver->eep_build); 4687 space = " "; 4688 } 4689 4690 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4691 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4692 space, fw_ver->invm_major, fw_ver->invm_minor, 4693 fw_ver->invm_img_type); 4694 space = " "; 4695 } 4696 4697 if (fw_ver->or_valid) { 4698 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4699 space, fw_ver->or_major, fw_ver->or_build, 4700 fw_ver->or_patch); 4701 space = " "; 4702 } 4703 4704 if (fw_ver->etrack_id) 4705 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4706 } 4707 4708 static void 4709 em_print_fw_version(struct e1000_softc *sc ) 4710 { 4711 device_t dev = sc->dev; 4712 struct sbuf *buf; 4713 int error = 0; 4714 4715 buf = sbuf_new_auto(); 4716 if (!buf) { 4717 device_printf(dev, "Could not allocate sbuf for output.\n"); 4718 return; 4719 } 4720 4721 em_sbuf_fw_version(&sc->fw_ver, buf); 4722 4723 error = sbuf_finish(buf); 4724 if (error) 4725 device_printf(dev, "Error finishing sbuf: %d\n", error); 4726 else if (sbuf_len(buf)) 4727 device_printf(dev, "%s\n", sbuf_data(buf)); 4728 4729 sbuf_delete(buf); 4730 } 4731 4732 static int 4733 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4734 { 4735 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4736 device_t dev = sc->dev; 4737 struct sbuf *buf; 4738 int error = 0; 4739 4740 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4741 if (!buf) { 4742 device_printf(dev, "Could not allocate sbuf for output.\n"); 4743 return (ENOMEM); 4744 } 4745 4746 em_sbuf_fw_version(&sc->fw_ver, buf); 4747 4748 error = sbuf_finish(buf); 4749 if (error) 4750 device_printf(dev, "Error finishing sbuf: %d\n", error); 4751 4752 sbuf_delete(buf); 4753 4754 return (0); 4755 } 4756 4757 /********************************************************************** 4758 * 4759 * This routine provides a way to dump out the adapter eeprom, 4760 * often a useful debug/service tool. This only dumps the first 4761 * 32 words, stuff that matters is in that extent. 4762 * 4763 **********************************************************************/ 4764 static int 4765 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4766 { 4767 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4768 int error; 4769 int result; 4770 4771 result = -1; 4772 error = sysctl_handle_int(oidp, &result, 0, req); 4773 4774 if (error || !req->newptr) 4775 return (error); 4776 4777 /* 4778 * This value will cause a hex dump of the 4779 * first 32 16-bit words of the EEPROM to 4780 * the screen. 4781 */ 4782 if (result == 1) 4783 em_print_nvm_info(sc); 4784 4785 return (error); 4786 } 4787 4788 static void 4789 em_print_nvm_info(struct e1000_softc *sc) 4790 { 4791 struct e1000_hw *hw = &sc->hw; 4792 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4793 u16 eeprom_data; 4794 int i, j, row = 0; 4795 4796 /* Its a bit crude, but it gets the job done */ 4797 printf("\nInterface EEPROM Dump:\n"); 4798 printf("Offset\n0x0000 "); 4799 4800 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4801 sx_xlock(iflib_ctx_lock); 4802 ASSERT_CTX_LOCK_HELD(hw); 4803 for (i = 0, j = 0; i < 32; i++, j++) { 4804 if (j == 8) { /* Make the offset block */ 4805 j = 0; ++row; 4806 printf("\n0x00%x0 ",row); 4807 } 4808 e1000_read_nvm(hw, i, 1, &eeprom_data); 4809 printf("%04x ", eeprom_data); 4810 } 4811 sx_xunlock(iflib_ctx_lock); 4812 printf("\n"); 4813 } 4814 4815 static int 4816 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4817 { 4818 struct em_int_delay_info *info; 4819 struct e1000_softc *sc; 4820 u32 regval; 4821 int error, usecs, ticks; 4822 4823 info = (struct em_int_delay_info *) arg1; 4824 usecs = info->value; 4825 error = sysctl_handle_int(oidp, &usecs, 0, req); 4826 if (error != 0 || req->newptr == NULL) 4827 return (error); 4828 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4829 return (EINVAL); 4830 info->value = usecs; 4831 ticks = EM_USECS_TO_TICKS(usecs); 4832 if (info->offset == E1000_ITR) /* units are 256ns here */ 4833 ticks *= 4; 4834 4835 sc = info->sc; 4836 4837 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4838 regval = (regval & ~0xffff) | (ticks & 0xffff); 4839 /* Handle a few special cases. */ 4840 switch (info->offset) { 4841 case E1000_RDTR: 4842 break; 4843 case E1000_TIDV: 4844 if (ticks == 0) { 4845 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4846 /* Don't write 0 into the TIDV register. */ 4847 regval++; 4848 } else 4849 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4850 break; 4851 } 4852 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4853 return (0); 4854 } 4855 4856 static void 4857 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4858 const char *description, struct em_int_delay_info *info, 4859 int offset, int value) 4860 { 4861 info->sc = sc; 4862 info->offset = offset; 4863 info->value = value; 4864 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4865 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4866 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4867 info, 0, em_sysctl_int_delay, "I", description); 4868 } 4869 4870 /* 4871 * Set flow control using sysctl: 4872 * Flow control values: 4873 * 0 - off 4874 * 1 - rx pause 4875 * 2 - tx pause 4876 * 3 - full 4877 */ 4878 static int 4879 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4880 { 4881 int error; 4882 static int input = 3; /* default is full */ 4883 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4884 4885 error = sysctl_handle_int(oidp, &input, 0, req); 4886 4887 if ((error) || (req->newptr == NULL)) 4888 return (error); 4889 4890 if (input == sc->fc) /* no change? */ 4891 return (error); 4892 4893 switch (input) { 4894 case e1000_fc_rx_pause: 4895 case e1000_fc_tx_pause: 4896 case e1000_fc_full: 4897 case e1000_fc_none: 4898 sc->hw.fc.requested_mode = input; 4899 sc->fc = input; 4900 break; 4901 default: 4902 /* Do nothing */ 4903 return (error); 4904 } 4905 4906 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4907 e1000_force_mac_fc(&sc->hw); 4908 return (error); 4909 } 4910 4911 /* 4912 * Manage Energy Efficient Ethernet: 4913 * Control values: 4914 * 0/1 - enabled/disabled 4915 */ 4916 static int 4917 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4918 { 4919 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4920 int error, value; 4921 4922 value = sc->hw.dev_spec.ich8lan.eee_disable; 4923 error = sysctl_handle_int(oidp, &value, 0, req); 4924 if (error || req->newptr == NULL) 4925 return (error); 4926 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4927 em_if_init(sc->ctx); 4928 4929 return (0); 4930 } 4931 4932 static int 4933 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4934 { 4935 struct e1000_softc *sc; 4936 int error; 4937 int result; 4938 4939 result = -1; 4940 error = sysctl_handle_int(oidp, &result, 0, req); 4941 4942 if (error || !req->newptr) 4943 return (error); 4944 4945 if (result == 1) { 4946 sc = (struct e1000_softc *) arg1; 4947 em_print_debug_info(sc); 4948 } 4949 4950 return (error); 4951 } 4952 4953 static int 4954 em_get_rs(SYSCTL_HANDLER_ARGS) 4955 { 4956 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4957 int error; 4958 int result; 4959 4960 result = 0; 4961 error = sysctl_handle_int(oidp, &result, 0, req); 4962 4963 if (error || !req->newptr || result != 1) 4964 return (error); 4965 em_dump_rs(sc); 4966 4967 return (error); 4968 } 4969 4970 static void 4971 em_if_debug(if_ctx_t ctx) 4972 { 4973 em_dump_rs(iflib_get_softc(ctx)); 4974 } 4975 4976 /* 4977 * This routine is meant to be fluid, add whatever is 4978 * needed for debugging a problem. -jfv 4979 */ 4980 static void 4981 em_print_debug_info(struct e1000_softc *sc) 4982 { 4983 device_t dev = iflib_get_dev(sc->ctx); 4984 if_t ifp = iflib_get_ifp(sc->ctx); 4985 struct tx_ring *txr = &sc->tx_queues->txr; 4986 struct rx_ring *rxr = &sc->rx_queues->rxr; 4987 4988 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4989 printf("Interface is RUNNING "); 4990 else 4991 printf("Interface is NOT RUNNING\n"); 4992 4993 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4994 printf("and INACTIVE\n"); 4995 else 4996 printf("and ACTIVE\n"); 4997 4998 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4999 device_printf(dev, "TX Queue %d ------\n", i); 5000 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5001 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5002 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5003 5004 } 5005 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5006 device_printf(dev, "RX Queue %d ------\n", j); 5007 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5008 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5009 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5010 } 5011 } 5012 5013 /* 5014 * 82574 only: 5015 * Write a new value to the EEPROM increasing the number of MSI-X 5016 * vectors from 3 to 5, for proper multiqueue support. 5017 */ 5018 static void 5019 em_enable_vectors_82574(if_ctx_t ctx) 5020 { 5021 struct e1000_softc *sc = iflib_get_softc(ctx); 5022 struct e1000_hw *hw = &sc->hw; 5023 device_t dev = iflib_get_dev(ctx); 5024 u16 edata; 5025 5026 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5027 if (bootverbose) 5028 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5029 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5030 device_printf(dev, "Writing to eeprom: increasing " 5031 "reported MSI-X vectors from 3 to 5...\n"); 5032 edata &= ~(EM_NVM_MSIX_N_MASK); 5033 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5034 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5035 e1000_update_nvm_checksum(hw); 5036 device_printf(dev, "Writing to eeprom: done\n"); 5037 } 5038 } 5039