1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "if_em.h" 30 #include <sys/sbuf.h> 31 #include <machine/_inttypes.h> 32 33 #define em_mac_min e1000_82571 34 #define igb_mac_min e1000_82575 35 36 /********************************************************************* 37 * Driver version: 38 *********************************************************************/ 39 static const char em_driver_version[] = "7.7.8-fbsd"; 40 static const char igb_driver_version[] = "2.5.19-fbsd"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static const pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 static const pci_vendor_info_t igb_vendor_info_array[] = 218 { 219 /* Intel(R) - igb-class devices */ 220 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 222 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 223 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 224 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 226 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 227 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 232 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 234 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 236 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 237 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 243 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 244 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 246 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 247 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 251 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 253 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 254 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 256 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 257 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 260 /* required last entry */ 261 PVID_END 262 }; 263 264 /********************************************************************* 265 * Function prototypes 266 *********************************************************************/ 267 static void *em_register(device_t); 268 static void *igb_register(device_t); 269 static int em_if_attach_pre(if_ctx_t); 270 static int em_if_attach_post(if_ctx_t); 271 static int em_if_detach(if_ctx_t); 272 static int em_if_shutdown(if_ctx_t); 273 static int em_if_suspend(if_ctx_t); 274 static int em_if_resume(if_ctx_t); 275 276 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 277 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static void em_if_queues_free(if_ctx_t); 279 280 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 281 static void em_if_init(if_ctx_t); 282 static void em_if_stop(if_ctx_t); 283 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 284 static int em_if_media_change(if_ctx_t); 285 static int em_if_mtu_set(if_ctx_t, uint32_t); 286 static void em_if_timer(if_ctx_t, uint16_t); 287 static void em_if_vlan_register(if_ctx_t, u16); 288 static void em_if_vlan_unregister(if_ctx_t, u16); 289 static void em_if_watchdog_reset(if_ctx_t); 290 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 291 292 static void em_identify_hardware(if_ctx_t); 293 static int em_allocate_pci_resources(if_ctx_t); 294 static void em_free_pci_resources(if_ctx_t); 295 static void em_reset(if_ctx_t); 296 static int em_setup_interface(if_ctx_t); 297 static int em_setup_msix(if_ctx_t); 298 299 static void em_initialize_transmit_unit(if_ctx_t); 300 static void em_initialize_receive_unit(if_ctx_t); 301 302 static void em_if_intr_enable(if_ctx_t); 303 static void em_if_intr_disable(if_ctx_t); 304 static void igb_if_intr_enable(if_ctx_t); 305 static void igb_if_intr_disable(if_ctx_t); 306 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 307 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 310 static void em_if_multi_set(if_ctx_t); 311 static void em_if_update_admin_status(if_ctx_t); 312 static void em_if_debug(if_ctx_t); 313 static void em_update_stats_counters(struct e1000_softc *); 314 static void em_add_hw_stats(struct e1000_softc *); 315 static int em_if_set_promisc(if_ctx_t, int); 316 static bool em_if_vlan_filter_capable(if_ctx_t); 317 static bool em_if_vlan_filter_used(if_ctx_t); 318 static void em_if_vlan_filter_enable(struct e1000_softc *); 319 static void em_if_vlan_filter_disable(struct e1000_softc *); 320 static void em_if_vlan_filter_write(struct e1000_softc *); 321 static void em_setup_vlan_hw_support(if_ctx_t ctx); 322 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 323 static void em_print_nvm_info(struct e1000_softc *); 324 static void em_fw_version_locked(if_ctx_t); 325 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 326 static void em_print_fw_version(struct e1000_softc *); 327 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 328 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 329 static int em_get_rs(SYSCTL_HANDLER_ARGS); 330 static void em_print_debug_info(struct e1000_softc *); 331 static int em_is_valid_ether_addr(u8 *); 332 static bool em_automask_tso(if_ctx_t); 333 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 334 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 335 const char *, struct em_int_delay_info *, int, int); 336 /* Management and WOL Support */ 337 static void em_init_manageability(struct e1000_softc *); 338 static void em_release_manageability(struct e1000_softc *); 339 static void em_get_hw_control(struct e1000_softc *); 340 static void em_release_hw_control(struct e1000_softc *); 341 static void em_get_wakeup(if_ctx_t); 342 static void em_enable_wakeup(if_ctx_t); 343 static int em_enable_phy_wakeup(struct e1000_softc *); 344 static void em_disable_aspm(struct e1000_softc *); 345 346 int em_intr(void *); 347 348 /* MSI-X handlers */ 349 static int em_if_msix_intr_assign(if_ctx_t, int); 350 static int em_msix_link(void *); 351 static void em_handle_link(void *); 352 353 static void em_enable_vectors_82574(if_ctx_t); 354 355 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 356 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 357 static void em_if_led_func(if_ctx_t, int); 358 359 static int em_get_regs(SYSCTL_HANDLER_ARGS); 360 361 static void lem_smartspeed(struct e1000_softc *); 362 static void igb_configure_queues(struct e1000_softc *); 363 static void em_flush_desc_rings(struct e1000_softc *); 364 365 366 /********************************************************************* 367 * FreeBSD Device Interface Entry Points 368 *********************************************************************/ 369 static device_method_t em_methods[] = { 370 /* Device interface */ 371 DEVMETHOD(device_register, em_register), 372 DEVMETHOD(device_probe, iflib_device_probe), 373 DEVMETHOD(device_attach, iflib_device_attach), 374 DEVMETHOD(device_detach, iflib_device_detach), 375 DEVMETHOD(device_shutdown, iflib_device_shutdown), 376 DEVMETHOD(device_suspend, iflib_device_suspend), 377 DEVMETHOD(device_resume, iflib_device_resume), 378 DEVMETHOD_END 379 }; 380 381 static device_method_t igb_methods[] = { 382 /* Device interface */ 383 DEVMETHOD(device_register, igb_register), 384 DEVMETHOD(device_probe, iflib_device_probe), 385 DEVMETHOD(device_attach, iflib_device_attach), 386 DEVMETHOD(device_detach, iflib_device_detach), 387 DEVMETHOD(device_shutdown, iflib_device_shutdown), 388 DEVMETHOD(device_suspend, iflib_device_suspend), 389 DEVMETHOD(device_resume, iflib_device_resume), 390 DEVMETHOD_END 391 }; 392 393 394 static driver_t em_driver = { 395 "em", em_methods, sizeof(struct e1000_softc), 396 }; 397 398 DRIVER_MODULE(em, pci, em_driver, 0, 0); 399 400 MODULE_DEPEND(em, pci, 1, 1, 1); 401 MODULE_DEPEND(em, ether, 1, 1, 1); 402 MODULE_DEPEND(em, iflib, 1, 1, 1); 403 404 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 405 406 static driver_t igb_driver = { 407 "igb", igb_methods, sizeof(struct e1000_softc), 408 }; 409 410 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 411 412 MODULE_DEPEND(igb, pci, 1, 1, 1); 413 MODULE_DEPEND(igb, ether, 1, 1, 1); 414 MODULE_DEPEND(igb, iflib, 1, 1, 1); 415 416 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 417 418 static device_method_t em_if_methods[] = { 419 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 420 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 421 DEVMETHOD(ifdi_detach, em_if_detach), 422 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 423 DEVMETHOD(ifdi_suspend, em_if_suspend), 424 DEVMETHOD(ifdi_resume, em_if_resume), 425 DEVMETHOD(ifdi_init, em_if_init), 426 DEVMETHOD(ifdi_stop, em_if_stop), 427 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 428 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 429 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 430 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 431 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 432 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 433 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 434 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 435 DEVMETHOD(ifdi_media_status, em_if_media_status), 436 DEVMETHOD(ifdi_media_change, em_if_media_change), 437 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 438 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 439 DEVMETHOD(ifdi_timer, em_if_timer), 440 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 441 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 442 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 443 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 444 DEVMETHOD(ifdi_led_func, em_if_led_func), 445 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 446 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 447 DEVMETHOD(ifdi_debug, em_if_debug), 448 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 449 DEVMETHOD_END 450 }; 451 452 static driver_t em_if_driver = { 453 "em_if", em_if_methods, sizeof(struct e1000_softc) 454 }; 455 456 static device_method_t igb_if_methods[] = { 457 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 458 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 459 DEVMETHOD(ifdi_detach, em_if_detach), 460 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 461 DEVMETHOD(ifdi_suspend, em_if_suspend), 462 DEVMETHOD(ifdi_resume, em_if_resume), 463 DEVMETHOD(ifdi_init, em_if_init), 464 DEVMETHOD(ifdi_stop, em_if_stop), 465 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 466 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 467 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 468 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 469 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 470 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 471 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 472 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 473 DEVMETHOD(ifdi_media_status, em_if_media_status), 474 DEVMETHOD(ifdi_media_change, em_if_media_change), 475 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 476 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 477 DEVMETHOD(ifdi_timer, em_if_timer), 478 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 479 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 480 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 481 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 482 DEVMETHOD(ifdi_led_func, em_if_led_func), 483 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 484 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 485 DEVMETHOD(ifdi_debug, em_if_debug), 486 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 487 DEVMETHOD_END 488 }; 489 490 static driver_t igb_if_driver = { 491 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 492 }; 493 494 /********************************************************************* 495 * Tunable default values. 496 *********************************************************************/ 497 498 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 499 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 500 501 #define MAX_INTS_PER_SEC 8000 502 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 503 504 /* Allow common code without TSO */ 505 #ifndef CSUM_TSO 506 #define CSUM_TSO 0 507 #endif 508 509 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 510 "EM driver parameters"); 511 512 static int em_disable_crc_stripping = 0; 513 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 514 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 515 516 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 517 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 518 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 519 0, "Default transmit interrupt delay in usecs"); 520 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 521 0, "Default receive interrupt delay in usecs"); 522 523 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 524 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 525 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 526 &em_tx_abs_int_delay_dflt, 0, 527 "Default transmit interrupt delay limit in usecs"); 528 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 529 &em_rx_abs_int_delay_dflt, 0, 530 "Default receive interrupt delay limit in usecs"); 531 532 static int em_smart_pwr_down = false; 533 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 534 0, "Set to true to leave smart power down enabled on newer adapters"); 535 536 static bool em_unsupported_tso = false; 537 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 538 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 539 540 /* Controls whether promiscuous also shows bad packets */ 541 static int em_debug_sbp = false; 542 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 543 "Show bad packets in promiscuous mode"); 544 545 /* How many packets rxeof tries to clean at a time */ 546 static int em_rx_process_limit = 100; 547 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 548 &em_rx_process_limit, 0, 549 "Maximum number of received packets to process " 550 "at a time, -1 means unlimited"); 551 552 /* Energy efficient ethernet - default to OFF */ 553 static int eee_setting = 1; 554 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 555 "Enable Energy Efficient Ethernet"); 556 557 /* 558 ** Tuneable Interrupt rate 559 */ 560 static int em_max_interrupt_rate = 8000; 561 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 562 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 563 564 565 566 /* Global used in WOL setup with multiport cards */ 567 static int global_quad_port_a = 0; 568 569 extern struct if_txrx igb_txrx; 570 extern struct if_txrx em_txrx; 571 extern struct if_txrx lem_txrx; 572 573 static struct if_shared_ctx em_sctx_init = { 574 .isc_magic = IFLIB_MAGIC, 575 .isc_q_align = PAGE_SIZE, 576 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 577 .isc_tx_maxsegsize = PAGE_SIZE, 578 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 579 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 580 .isc_rx_maxsize = MJUM9BYTES, 581 .isc_rx_nsegments = 1, 582 .isc_rx_maxsegsize = MJUM9BYTES, 583 .isc_nfl = 1, 584 .isc_nrxqs = 1, 585 .isc_ntxqs = 1, 586 .isc_admin_intrcnt = 1, 587 .isc_vendor_info = em_vendor_info_array, 588 .isc_driver_version = em_driver_version, 589 .isc_driver = &em_if_driver, 590 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 591 592 .isc_nrxd_min = {EM_MIN_RXD}, 593 .isc_ntxd_min = {EM_MIN_TXD}, 594 .isc_nrxd_max = {EM_MAX_RXD}, 595 .isc_ntxd_max = {EM_MAX_TXD}, 596 .isc_nrxd_default = {EM_DEFAULT_RXD}, 597 .isc_ntxd_default = {EM_DEFAULT_TXD}, 598 }; 599 600 static struct if_shared_ctx igb_sctx_init = { 601 .isc_magic = IFLIB_MAGIC, 602 .isc_q_align = PAGE_SIZE, 603 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 604 .isc_tx_maxsegsize = PAGE_SIZE, 605 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 606 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 607 .isc_rx_maxsize = MJUM9BYTES, 608 .isc_rx_nsegments = 1, 609 .isc_rx_maxsegsize = MJUM9BYTES, 610 .isc_nfl = 1, 611 .isc_nrxqs = 1, 612 .isc_ntxqs = 1, 613 .isc_admin_intrcnt = 1, 614 .isc_vendor_info = igb_vendor_info_array, 615 .isc_driver_version = igb_driver_version, 616 .isc_driver = &igb_if_driver, 617 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 618 619 .isc_nrxd_min = {EM_MIN_RXD}, 620 .isc_ntxd_min = {EM_MIN_TXD}, 621 .isc_nrxd_max = {IGB_MAX_RXD}, 622 .isc_ntxd_max = {IGB_MAX_TXD}, 623 .isc_nrxd_default = {EM_DEFAULT_RXD}, 624 .isc_ntxd_default = {EM_DEFAULT_TXD}, 625 }; 626 627 /***************************************************************** 628 * 629 * Dump Registers 630 * 631 ****************************************************************/ 632 #define IGB_REGS_LEN 739 633 634 static int em_get_regs(SYSCTL_HANDLER_ARGS) 635 { 636 struct e1000_softc *sc = (struct e1000_softc *)arg1; 637 struct e1000_hw *hw = &sc->hw; 638 struct sbuf *sb; 639 u32 *regs_buff; 640 int rc; 641 642 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 643 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 644 645 rc = sysctl_wire_old_buffer(req, 0); 646 MPASS(rc == 0); 647 if (rc != 0) { 648 free(regs_buff, M_DEVBUF); 649 return (rc); 650 } 651 652 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 653 MPASS(sb != NULL); 654 if (sb == NULL) { 655 free(regs_buff, M_DEVBUF); 656 return (ENOMEM); 657 } 658 659 /* General Registers */ 660 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 661 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 662 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 663 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 664 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 665 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 666 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 667 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 668 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 669 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 670 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 671 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 672 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 673 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 674 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 675 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 676 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 677 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 678 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 679 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 680 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 681 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 682 683 sbuf_printf(sb, "General Registers\n"); 684 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 685 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 686 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 687 688 sbuf_printf(sb, "Interrupt Registers\n"); 689 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 690 691 sbuf_printf(sb, "RX Registers\n"); 692 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 693 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 694 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 695 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 696 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 697 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 698 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 699 700 sbuf_printf(sb, "TX Registers\n"); 701 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 702 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 703 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 704 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 705 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 706 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 707 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 708 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 709 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 710 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 711 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 712 713 free(regs_buff, M_DEVBUF); 714 715 #ifdef DUMP_DESCS 716 { 717 if_softc_ctx_t scctx = sc->shared; 718 struct rx_ring *rxr = &rx_que->rxr; 719 struct tx_ring *txr = &tx_que->txr; 720 int ntxd = scctx->isc_ntxd[0]; 721 int nrxd = scctx->isc_nrxd[0]; 722 int j; 723 724 for (j = 0; j < nrxd; j++) { 725 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 726 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 727 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 728 } 729 730 for (j = 0; j < min(ntxd, 256); j++) { 731 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 732 733 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 734 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 735 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 736 737 } 738 } 739 #endif 740 741 rc = sbuf_finish(sb); 742 sbuf_delete(sb); 743 return(rc); 744 } 745 746 static void * 747 em_register(device_t dev) 748 { 749 return (&em_sctx_init); 750 } 751 752 static void * 753 igb_register(device_t dev) 754 { 755 return (&igb_sctx_init); 756 } 757 758 static int 759 em_set_num_queues(if_ctx_t ctx) 760 { 761 struct e1000_softc *sc = iflib_get_softc(ctx); 762 int maxqueues; 763 764 /* Sanity check based on HW */ 765 switch (sc->hw.mac.type) { 766 case e1000_82576: 767 case e1000_82580: 768 case e1000_i350: 769 case e1000_i354: 770 maxqueues = 8; 771 break; 772 case e1000_i210: 773 case e1000_82575: 774 maxqueues = 4; 775 break; 776 case e1000_i211: 777 case e1000_82574: 778 maxqueues = 2; 779 break; 780 default: 781 maxqueues = 1; 782 break; 783 } 784 785 return (maxqueues); 786 } 787 788 #define LEM_CAPS \ 789 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 790 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 791 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 792 793 #define EM_CAPS \ 794 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 795 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 796 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 797 IFCAP_TSO6 798 799 #define IGB_CAPS \ 800 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 801 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 802 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 803 IFCAP_TSO6 804 805 /********************************************************************* 806 * Device initialization routine 807 * 808 * The attach entry point is called when the driver is being loaded. 809 * This routine identifies the type of hardware, allocates all resources 810 * and initializes the hardware. 811 * 812 * return 0 on success, positive on failure 813 *********************************************************************/ 814 static int 815 em_if_attach_pre(if_ctx_t ctx) 816 { 817 struct e1000_softc *sc; 818 if_softc_ctx_t scctx; 819 device_t dev; 820 struct e1000_hw *hw; 821 struct sysctl_oid_list *child; 822 struct sysctl_ctx_list *ctx_list; 823 int error = 0; 824 825 INIT_DEBUGOUT("em_if_attach_pre: begin"); 826 dev = iflib_get_dev(ctx); 827 sc = iflib_get_softc(ctx); 828 829 sc->ctx = sc->osdep.ctx = ctx; 830 sc->dev = sc->osdep.dev = dev; 831 scctx = sc->shared = iflib_get_softc_ctx(ctx); 832 sc->media = iflib_get_media(ctx); 833 hw = &sc->hw; 834 835 sc->tx_process_limit = scctx->isc_ntxd[0]; 836 837 /* Determine hardware and mac info */ 838 em_identify_hardware(ctx); 839 840 /* SYSCTL stuff */ 841 ctx_list = device_get_sysctl_ctx(dev); 842 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 843 844 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 845 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 846 em_sysctl_nvm_info, "I", "NVM Information"); 847 848 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 849 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 850 em_sysctl_print_fw_version, "A", 851 "Prints FW/NVM Versions"); 852 853 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 854 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 855 em_sysctl_debug_info, "I", "Debug Information"); 856 857 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 858 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 859 em_set_flowcntl, "I", "Flow Control"); 860 861 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 862 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 863 em_get_regs, "A", "Dump Registers"); 864 865 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 866 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 867 em_get_rs, "I", "Dump RS indexes"); 868 869 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 870 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 871 if (bootverbose) 872 device_printf(dev, "attach_pre capping queues at %d\n", 873 scctx->isc_ntxqsets_max); 874 875 if (hw->mac.type >= igb_mac_min) { 876 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 877 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 878 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 879 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 880 scctx->isc_txrx = &igb_txrx; 881 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 882 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 883 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 884 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 885 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 886 CSUM_IP6_TCP | CSUM_IP6_UDP; 887 if (hw->mac.type != e1000_82575) 888 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 889 /* 890 ** Some new devices, as with ixgbe, now may 891 ** use a different BAR, so we need to keep 892 ** track of which is used. 893 */ 894 scctx->isc_msix_bar = pci_msix_table_bar(dev); 895 } else if (hw->mac.type >= em_mac_min) { 896 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 897 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 898 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 899 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 900 scctx->isc_txrx = &em_txrx; 901 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 902 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 903 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 904 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 905 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 906 CSUM_IP6_TCP | CSUM_IP6_UDP; 907 908 /* Disable TSO on all em(4) until ring stalls can be debugged */ 909 scctx->isc_capenable &= ~IFCAP_TSO; 910 911 /* 912 * Disable TSO on SPT due to errata that downclocks DMA performance 913 * i218-i219 Specification Update 1.5.4.5 914 */ 915 if (hw->mac.type == e1000_pch_spt) 916 scctx->isc_capenable &= ~IFCAP_TSO; 917 918 /* 919 * We support MSI-X with 82574 only, but indicate to iflib(4) 920 * that it shall give MSI at least a try with other devices. 921 */ 922 if (hw->mac.type == e1000_82574) { 923 scctx->isc_msix_bar = pci_msix_table_bar(dev); 924 } else { 925 scctx->isc_msix_bar = -1; 926 scctx->isc_disable_msix = 1; 927 } 928 } else { 929 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 930 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 931 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 932 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 933 scctx->isc_txrx = &lem_txrx; 934 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 935 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 936 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 937 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 938 if (em_unsupported_tso) 939 scctx->isc_capabilities |= IFCAP_TSO6; 940 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 941 CSUM_IP6_TCP | CSUM_IP6_UDP; 942 943 /* Disable TSO on all lem(4) until ring stalls can be debugged */ 944 scctx->isc_capenable &= ~IFCAP_TSO; 945 946 /* 82541ER doesn't do HW tagging */ 947 if (hw->device_id == E1000_DEV_ID_82541ER || 948 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 949 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 950 scctx->isc_capenable = scctx->isc_capabilities; 951 } 952 /* This is the first e1000 chip and it does not do offloads */ 953 if (hw->mac.type == e1000_82542) { 954 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 955 IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING | 956 IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO); 957 scctx->isc_capenable = scctx->isc_capabilities; 958 } 959 /* These can't do TSO for various reasons */ 960 if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 || 961 hw->mac.type == e1000_82547_rev_2) { 962 scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 963 scctx->isc_capenable = scctx->isc_capabilities; 964 } 965 /* XXXKB: No IPv6 before this? */ 966 if (hw->mac.type < e1000_82545){ 967 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 968 scctx->isc_capenable = scctx->isc_capabilities; 969 } 970 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 971 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 972 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 973 IFCAP_HWCSUM_IPV6); 974 975 /* INTx only */ 976 scctx->isc_msix_bar = 0; 977 } 978 979 /* Setup PCI resources */ 980 if (em_allocate_pci_resources(ctx)) { 981 device_printf(dev, "Allocation of PCI resources failed\n"); 982 error = ENXIO; 983 goto err_pci; 984 } 985 986 /* 987 ** For ICH8 and family we need to 988 ** map the flash memory, and this 989 ** must happen after the MAC is 990 ** identified 991 */ 992 if ((hw->mac.type == e1000_ich8lan) || 993 (hw->mac.type == e1000_ich9lan) || 994 (hw->mac.type == e1000_ich10lan) || 995 (hw->mac.type == e1000_pchlan) || 996 (hw->mac.type == e1000_pch2lan) || 997 (hw->mac.type == e1000_pch_lpt)) { 998 int rid = EM_BAR_TYPE_FLASH; 999 sc->flash = bus_alloc_resource_any(dev, 1000 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1001 if (sc->flash == NULL) { 1002 device_printf(dev, "Mapping of Flash failed\n"); 1003 error = ENXIO; 1004 goto err_pci; 1005 } 1006 /* This is used in the shared code */ 1007 hw->flash_address = (u8 *)sc->flash; 1008 sc->osdep.flash_bus_space_tag = 1009 rman_get_bustag(sc->flash); 1010 sc->osdep.flash_bus_space_handle = 1011 rman_get_bushandle(sc->flash); 1012 } 1013 /* 1014 ** In the new SPT device flash is not a 1015 ** separate BAR, rather it is also in BAR0, 1016 ** so use the same tag and an offset handle for the 1017 ** FLASH read/write macros in the shared code. 1018 */ 1019 else if (hw->mac.type >= e1000_pch_spt) { 1020 sc->osdep.flash_bus_space_tag = 1021 sc->osdep.mem_bus_space_tag; 1022 sc->osdep.flash_bus_space_handle = 1023 sc->osdep.mem_bus_space_handle 1024 + E1000_FLASH_BASE_ADDR; 1025 } 1026 1027 /* Do Shared Code initialization */ 1028 error = e1000_setup_init_funcs(hw, true); 1029 if (error) { 1030 device_printf(dev, "Setup of Shared code failed, error %d\n", 1031 error); 1032 error = ENXIO; 1033 goto err_pci; 1034 } 1035 1036 em_setup_msix(ctx); 1037 e1000_get_bus_info(hw); 1038 1039 /* Set up some sysctls for the tunable interrupt delays */ 1040 em_add_int_delay_sysctl(sc, "rx_int_delay", 1041 "receive interrupt delay in usecs", &sc->rx_int_delay, 1042 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1043 em_add_int_delay_sysctl(sc, "tx_int_delay", 1044 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1045 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1046 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1047 "receive interrupt delay limit in usecs", 1048 &sc->rx_abs_int_delay, 1049 E1000_REGISTER(hw, E1000_RADV), 1050 em_rx_abs_int_delay_dflt); 1051 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1052 "transmit interrupt delay limit in usecs", 1053 &sc->tx_abs_int_delay, 1054 E1000_REGISTER(hw, E1000_TADV), 1055 em_tx_abs_int_delay_dflt); 1056 em_add_int_delay_sysctl(sc, "itr", 1057 "interrupt delay limit in usecs/4", 1058 &sc->tx_itr, 1059 E1000_REGISTER(hw, E1000_ITR), 1060 DEFAULT_ITR); 1061 1062 hw->mac.autoneg = DO_AUTO_NEG; 1063 hw->phy.autoneg_wait_to_complete = false; 1064 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1065 1066 if (hw->mac.type < em_mac_min) { 1067 e1000_init_script_state_82541(hw, true); 1068 e1000_set_tbi_compatibility_82543(hw, true); 1069 } 1070 /* Copper options */ 1071 if (hw->phy.media_type == e1000_media_type_copper) { 1072 hw->phy.mdix = AUTO_ALL_MODES; 1073 hw->phy.disable_polarity_correction = false; 1074 hw->phy.ms_type = EM_MASTER_SLAVE; 1075 } 1076 1077 /* 1078 * Set the frame limits assuming 1079 * standard ethernet sized frames. 1080 */ 1081 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1082 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1083 1084 /* 1085 * This controls when hardware reports transmit completion 1086 * status. 1087 */ 1088 hw->mac.report_tx_early = 1; 1089 1090 /* Allocate multicast array memory. */ 1091 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1092 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1093 if (sc->mta == NULL) { 1094 device_printf(dev, "Can not allocate multicast setup array\n"); 1095 error = ENOMEM; 1096 goto err_late; 1097 } 1098 1099 /* Clear the IFCAP_TSO auto mask */ 1100 sc->tso_automasked = 0; 1101 1102 /* Check SOL/IDER usage */ 1103 if (e1000_check_reset_block(hw)) 1104 device_printf(dev, "PHY reset is blocked" 1105 " due to SOL/IDER session.\n"); 1106 1107 /* Sysctl for setting Energy Efficient Ethernet */ 1108 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1109 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1110 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1111 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1112 1113 /* 1114 ** Start from a known state, this is 1115 ** important in reading the nvm and 1116 ** mac from that. 1117 */ 1118 e1000_reset_hw(hw); 1119 1120 /* Make sure we have a good EEPROM before we read from it */ 1121 if (e1000_validate_nvm_checksum(hw) < 0) { 1122 /* 1123 ** Some PCI-E parts fail the first check due to 1124 ** the link being in sleep state, call it again, 1125 ** if it fails a second time its a real issue. 1126 */ 1127 if (e1000_validate_nvm_checksum(hw) < 0) { 1128 device_printf(dev, 1129 "The EEPROM Checksum Is Not Valid\n"); 1130 error = EIO; 1131 goto err_late; 1132 } 1133 } 1134 1135 /* Copy the permanent MAC address out of the EEPROM */ 1136 if (e1000_read_mac_addr(hw) < 0) { 1137 device_printf(dev, "EEPROM read error while reading MAC" 1138 " address\n"); 1139 error = EIO; 1140 goto err_late; 1141 } 1142 1143 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1144 if (sc->vf_ifp) { 1145 ether_gen_addr(iflib_get_ifp(ctx), 1146 (struct ether_addr *)hw->mac.addr); 1147 } else { 1148 device_printf(dev, "Invalid MAC address\n"); 1149 error = EIO; 1150 goto err_late; 1151 } 1152 } 1153 1154 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1155 em_fw_version_locked(ctx); 1156 1157 em_print_fw_version(sc); 1158 1159 /* 1160 * Get Wake-on-Lan and Management info for later use 1161 */ 1162 em_get_wakeup(ctx); 1163 1164 /* Enable only WOL MAGIC by default */ 1165 scctx->isc_capenable &= ~IFCAP_WOL; 1166 if (sc->wol != 0) 1167 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1168 1169 iflib_set_mac(ctx, hw->mac.addr); 1170 1171 return (0); 1172 1173 err_late: 1174 em_release_hw_control(sc); 1175 err_pci: 1176 em_free_pci_resources(ctx); 1177 free(sc->mta, M_DEVBUF); 1178 1179 return (error); 1180 } 1181 1182 static int 1183 em_if_attach_post(if_ctx_t ctx) 1184 { 1185 struct e1000_softc *sc = iflib_get_softc(ctx); 1186 struct e1000_hw *hw = &sc->hw; 1187 int error = 0; 1188 1189 /* Setup OS specific network interface */ 1190 error = em_setup_interface(ctx); 1191 if (error != 0) { 1192 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1193 goto err_late; 1194 } 1195 1196 em_reset(ctx); 1197 1198 /* Initialize statistics */ 1199 em_update_stats_counters(sc); 1200 hw->mac.get_link_status = 1; 1201 em_if_update_admin_status(ctx); 1202 em_add_hw_stats(sc); 1203 1204 /* Non-AMT based hardware can now take control from firmware */ 1205 if (sc->has_manage && !sc->has_amt) 1206 em_get_hw_control(sc); 1207 1208 INIT_DEBUGOUT("em_if_attach_post: end"); 1209 1210 return (0); 1211 1212 err_late: 1213 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1214 return (error); 1215 } 1216 1217 /********************************************************************* 1218 * Device removal routine 1219 * 1220 * The detach entry point is called when the driver is being removed. 1221 * This routine stops the adapter and deallocates all the resources 1222 * that were allocated for driver operation. 1223 * 1224 * return 0 on success, positive on failure 1225 *********************************************************************/ 1226 static int 1227 em_if_detach(if_ctx_t ctx) 1228 { 1229 struct e1000_softc *sc = iflib_get_softc(ctx); 1230 1231 INIT_DEBUGOUT("em_if_detach: begin"); 1232 1233 e1000_phy_hw_reset(&sc->hw); 1234 1235 em_release_manageability(sc); 1236 em_release_hw_control(sc); 1237 em_free_pci_resources(ctx); 1238 free(sc->mta, M_DEVBUF); 1239 sc->mta = NULL; 1240 1241 return (0); 1242 } 1243 1244 /********************************************************************* 1245 * 1246 * Shutdown entry point 1247 * 1248 **********************************************************************/ 1249 1250 static int 1251 em_if_shutdown(if_ctx_t ctx) 1252 { 1253 return em_if_suspend(ctx); 1254 } 1255 1256 /* 1257 * Suspend/resume device methods. 1258 */ 1259 static int 1260 em_if_suspend(if_ctx_t ctx) 1261 { 1262 struct e1000_softc *sc = iflib_get_softc(ctx); 1263 1264 em_release_manageability(sc); 1265 em_release_hw_control(sc); 1266 em_enable_wakeup(ctx); 1267 return (0); 1268 } 1269 1270 static int 1271 em_if_resume(if_ctx_t ctx) 1272 { 1273 struct e1000_softc *sc = iflib_get_softc(ctx); 1274 1275 if (sc->hw.mac.type == e1000_pch2lan) 1276 e1000_resume_workarounds_pchlan(&sc->hw); 1277 em_if_init(ctx); 1278 em_init_manageability(sc); 1279 1280 return(0); 1281 } 1282 1283 static int 1284 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1285 { 1286 int max_frame_size; 1287 struct e1000_softc *sc = iflib_get_softc(ctx); 1288 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1289 1290 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1291 1292 switch (sc->hw.mac.type) { 1293 case e1000_82571: 1294 case e1000_82572: 1295 case e1000_ich9lan: 1296 case e1000_ich10lan: 1297 case e1000_pch2lan: 1298 case e1000_pch_lpt: 1299 case e1000_pch_spt: 1300 case e1000_pch_cnp: 1301 case e1000_pch_tgp: 1302 case e1000_pch_adp: 1303 case e1000_pch_mtp: 1304 case e1000_pch_ptp: 1305 case e1000_82574: 1306 case e1000_82583: 1307 case e1000_80003es2lan: 1308 /* 9K Jumbo Frame size */ 1309 max_frame_size = 9234; 1310 break; 1311 case e1000_pchlan: 1312 max_frame_size = 4096; 1313 break; 1314 case e1000_82542: 1315 case e1000_ich8lan: 1316 /* Adapters that do not support jumbo frames */ 1317 max_frame_size = ETHER_MAX_LEN; 1318 break; 1319 default: 1320 if (sc->hw.mac.type >= igb_mac_min) 1321 max_frame_size = 9234; 1322 else /* lem */ 1323 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1324 } 1325 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1326 return (EINVAL); 1327 } 1328 1329 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1330 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1331 return (0); 1332 } 1333 1334 /********************************************************************* 1335 * Init entry point 1336 * 1337 * This routine is used in two ways. It is used by the stack as 1338 * init entry point in network interface structure. It is also used 1339 * by the driver as a hw/sw initialization routine to get to a 1340 * consistent state. 1341 * 1342 **********************************************************************/ 1343 static void 1344 em_if_init(if_ctx_t ctx) 1345 { 1346 struct e1000_softc *sc = iflib_get_softc(ctx); 1347 if_softc_ctx_t scctx = sc->shared; 1348 if_t ifp = iflib_get_ifp(ctx); 1349 struct em_tx_queue *tx_que; 1350 int i; 1351 1352 INIT_DEBUGOUT("em_if_init: begin"); 1353 1354 /* Get the latest mac address, User can use a LAA */ 1355 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1356 ETHER_ADDR_LEN); 1357 1358 /* Put the address into the Receive Address Array */ 1359 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1360 1361 /* 1362 * With the 82571 adapter, RAR[0] may be overwritten 1363 * when the other port is reset, we make a duplicate 1364 * in RAR[14] for that eventuality, this assures 1365 * the interface continues to function. 1366 */ 1367 if (sc->hw.mac.type == e1000_82571) { 1368 e1000_set_laa_state_82571(&sc->hw, true); 1369 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1370 E1000_RAR_ENTRIES - 1); 1371 } 1372 1373 /* Initialize the hardware */ 1374 em_reset(ctx); 1375 em_if_update_admin_status(ctx); 1376 1377 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1378 struct tx_ring *txr = &tx_que->txr; 1379 1380 txr->tx_rs_cidx = txr->tx_rs_pidx; 1381 1382 /* Initialize the last processed descriptor to be the end of 1383 * the ring, rather than the start, so that we avoid an 1384 * off-by-one error when calculating how many descriptors are 1385 * done in the credits_update function. 1386 */ 1387 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1388 } 1389 1390 /* Setup VLAN support, basic and offload if available */ 1391 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1392 1393 /* Clear bad data from Rx FIFOs */ 1394 if (sc->hw.mac.type >= igb_mac_min) 1395 e1000_rx_fifo_flush_base(&sc->hw); 1396 1397 /* Configure for OS presence */ 1398 em_init_manageability(sc); 1399 1400 /* Prepare transmit descriptors and buffers */ 1401 em_initialize_transmit_unit(ctx); 1402 1403 /* Setup Multicast table */ 1404 em_if_multi_set(ctx); 1405 1406 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1407 em_initialize_receive_unit(ctx); 1408 1409 /* Set up VLAN support and filter */ 1410 em_setup_vlan_hw_support(ctx); 1411 1412 /* Don't lose promiscuous settings */ 1413 em_if_set_promisc(ctx, if_getflags(ifp)); 1414 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1415 1416 /* MSI-X configuration for 82574 */ 1417 if (sc->hw.mac.type == e1000_82574) { 1418 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1419 1420 tmp |= E1000_CTRL_EXT_PBA_CLR; 1421 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1422 /* Set the IVAR - interrupt vector routing. */ 1423 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1424 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1425 igb_configure_queues(sc); 1426 1427 /* this clears any pending interrupts */ 1428 E1000_READ_REG(&sc->hw, E1000_ICR); 1429 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1430 1431 /* AMT based hardware can now take control from firmware */ 1432 if (sc->has_manage && sc->has_amt) 1433 em_get_hw_control(sc); 1434 1435 /* Set Energy Efficient Ethernet */ 1436 if (sc->hw.mac.type >= igb_mac_min && 1437 sc->hw.phy.media_type == e1000_media_type_copper) { 1438 if (sc->hw.mac.type == e1000_i354) 1439 e1000_set_eee_i354(&sc->hw, true, true); 1440 else 1441 e1000_set_eee_i350(&sc->hw, true, true); 1442 } 1443 } 1444 1445 /********************************************************************* 1446 * 1447 * Fast Legacy/MSI Combined Interrupt Service routine 1448 * 1449 *********************************************************************/ 1450 int 1451 em_intr(void *arg) 1452 { 1453 struct e1000_softc *sc = arg; 1454 if_ctx_t ctx = sc->ctx; 1455 u32 reg_icr; 1456 1457 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1458 1459 /* Hot eject? */ 1460 if (reg_icr == 0xffffffff) 1461 return FILTER_STRAY; 1462 1463 /* Definitely not our interrupt. */ 1464 if (reg_icr == 0x0) 1465 return FILTER_STRAY; 1466 1467 /* 1468 * Starting with the 82571 chip, bit 31 should be used to 1469 * determine whether the interrupt belongs to us. 1470 */ 1471 if (sc->hw.mac.type >= e1000_82571 && 1472 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1473 return FILTER_STRAY; 1474 1475 /* 1476 * Only MSI-X interrupts have one-shot behavior by taking advantage 1477 * of the EIAC register. Thus, explicitly disable interrupts. This 1478 * also works around the MSI message reordering errata on certain 1479 * systems. 1480 */ 1481 IFDI_INTR_DISABLE(ctx); 1482 1483 /* Link status change */ 1484 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1485 em_handle_link(ctx); 1486 1487 if (reg_icr & E1000_ICR_RXO) 1488 sc->rx_overruns++; 1489 1490 return (FILTER_SCHEDULE_THREAD); 1491 } 1492 1493 static int 1494 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1495 { 1496 struct e1000_softc *sc = iflib_get_softc(ctx); 1497 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1498 1499 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1500 return (0); 1501 } 1502 1503 static int 1504 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1505 { 1506 struct e1000_softc *sc = iflib_get_softc(ctx); 1507 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1508 1509 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1510 return (0); 1511 } 1512 1513 static int 1514 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1515 { 1516 struct e1000_softc *sc = iflib_get_softc(ctx); 1517 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1518 1519 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1520 return (0); 1521 } 1522 1523 static int 1524 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1525 { 1526 struct e1000_softc *sc = iflib_get_softc(ctx); 1527 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1528 1529 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1530 return (0); 1531 } 1532 1533 /********************************************************************* 1534 * 1535 * MSI-X RX Interrupt Service routine 1536 * 1537 **********************************************************************/ 1538 static int 1539 em_msix_que(void *arg) 1540 { 1541 struct em_rx_queue *que = arg; 1542 1543 ++que->irqs; 1544 1545 return (FILTER_SCHEDULE_THREAD); 1546 } 1547 1548 /********************************************************************* 1549 * 1550 * MSI-X Link Fast Interrupt Service routine 1551 * 1552 **********************************************************************/ 1553 static int 1554 em_msix_link(void *arg) 1555 { 1556 struct e1000_softc *sc = arg; 1557 u32 reg_icr; 1558 1559 ++sc->link_irq; 1560 MPASS(sc->hw.back != NULL); 1561 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1562 1563 if (reg_icr & E1000_ICR_RXO) 1564 sc->rx_overruns++; 1565 1566 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1567 em_handle_link(sc->ctx); 1568 1569 /* Re-arm unconditionally */ 1570 if (sc->hw.mac.type >= igb_mac_min) { 1571 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1572 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1573 } else if (sc->hw.mac.type == e1000_82574) { 1574 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1575 E1000_IMS_OTHER); 1576 /* 1577 * Because we must read the ICR for this interrupt it may 1578 * clear other causes using autoclear, for this reason we 1579 * simply create a soft interrupt for all these vectors. 1580 */ 1581 if (reg_icr) 1582 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1583 } else 1584 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1585 1586 return (FILTER_HANDLED); 1587 } 1588 1589 static void 1590 em_handle_link(void *context) 1591 { 1592 if_ctx_t ctx = context; 1593 struct e1000_softc *sc = iflib_get_softc(ctx); 1594 1595 sc->hw.mac.get_link_status = 1; 1596 iflib_admin_intr_deferred(ctx); 1597 } 1598 1599 /********************************************************************* 1600 * 1601 * Media Ioctl callback 1602 * 1603 * This routine is called whenever the user queries the status of 1604 * the interface using ifconfig. 1605 * 1606 **********************************************************************/ 1607 static void 1608 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1609 { 1610 struct e1000_softc *sc = iflib_get_softc(ctx); 1611 u_char fiber_type = IFM_1000_SX; 1612 1613 INIT_DEBUGOUT("em_if_media_status: begin"); 1614 1615 iflib_admin_intr_deferred(ctx); 1616 1617 ifmr->ifm_status = IFM_AVALID; 1618 ifmr->ifm_active = IFM_ETHER; 1619 1620 if (!sc->link_active) { 1621 return; 1622 } 1623 1624 ifmr->ifm_status |= IFM_ACTIVE; 1625 1626 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1627 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1628 if (sc->hw.mac.type == e1000_82545) 1629 fiber_type = IFM_1000_LX; 1630 ifmr->ifm_active |= fiber_type | IFM_FDX; 1631 } else { 1632 switch (sc->link_speed) { 1633 case 10: 1634 ifmr->ifm_active |= IFM_10_T; 1635 break; 1636 case 100: 1637 ifmr->ifm_active |= IFM_100_TX; 1638 break; 1639 case 1000: 1640 ifmr->ifm_active |= IFM_1000_T; 1641 break; 1642 } 1643 if (sc->link_duplex == FULL_DUPLEX) 1644 ifmr->ifm_active |= IFM_FDX; 1645 else 1646 ifmr->ifm_active |= IFM_HDX; 1647 } 1648 } 1649 1650 /********************************************************************* 1651 * 1652 * Media Ioctl callback 1653 * 1654 * This routine is called when the user changes speed/duplex using 1655 * media/mediopt option with ifconfig. 1656 * 1657 **********************************************************************/ 1658 static int 1659 em_if_media_change(if_ctx_t ctx) 1660 { 1661 struct e1000_softc *sc = iflib_get_softc(ctx); 1662 struct ifmedia *ifm = iflib_get_media(ctx); 1663 1664 INIT_DEBUGOUT("em_if_media_change: begin"); 1665 1666 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1667 return (EINVAL); 1668 1669 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1670 case IFM_AUTO: 1671 sc->hw.mac.autoneg = DO_AUTO_NEG; 1672 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1673 break; 1674 case IFM_1000_LX: 1675 case IFM_1000_SX: 1676 case IFM_1000_T: 1677 sc->hw.mac.autoneg = DO_AUTO_NEG; 1678 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1679 break; 1680 case IFM_100_TX: 1681 sc->hw.mac.autoneg = false; 1682 sc->hw.phy.autoneg_advertised = 0; 1683 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1684 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1685 else 1686 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1687 break; 1688 case IFM_10_T: 1689 sc->hw.mac.autoneg = false; 1690 sc->hw.phy.autoneg_advertised = 0; 1691 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1692 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1693 else 1694 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1695 break; 1696 default: 1697 device_printf(sc->dev, "Unsupported media type\n"); 1698 } 1699 1700 em_if_init(ctx); 1701 1702 return (0); 1703 } 1704 1705 static int 1706 em_if_set_promisc(if_ctx_t ctx, int flags) 1707 { 1708 struct e1000_softc *sc = iflib_get_softc(ctx); 1709 if_t ifp = iflib_get_ifp(ctx); 1710 u32 reg_rctl; 1711 int mcnt = 0; 1712 1713 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1714 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1715 if (flags & IFF_ALLMULTI) 1716 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1717 else 1718 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1719 1720 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1721 reg_rctl &= (~E1000_RCTL_MPE); 1722 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1723 1724 if (flags & IFF_PROMISC) { 1725 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1726 em_if_vlan_filter_disable(sc); 1727 /* Turn this on if you want to see bad packets */ 1728 if (em_debug_sbp) 1729 reg_rctl |= E1000_RCTL_SBP; 1730 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1731 } else { 1732 if (flags & IFF_ALLMULTI) { 1733 reg_rctl |= E1000_RCTL_MPE; 1734 reg_rctl &= ~E1000_RCTL_UPE; 1735 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1736 } 1737 if (em_if_vlan_filter_used(ctx)) 1738 em_if_vlan_filter_enable(sc); 1739 } 1740 return (0); 1741 } 1742 1743 static u_int 1744 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1745 { 1746 u8 *mta = arg; 1747 1748 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1749 return (0); 1750 1751 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1752 1753 return (1); 1754 } 1755 1756 /********************************************************************* 1757 * Multicast Update 1758 * 1759 * This routine is called whenever multicast address list is updated. 1760 * 1761 **********************************************************************/ 1762 static void 1763 em_if_multi_set(if_ctx_t ctx) 1764 { 1765 struct e1000_softc *sc = iflib_get_softc(ctx); 1766 if_t ifp = iflib_get_ifp(ctx); 1767 u8 *mta; /* Multicast array memory */ 1768 u32 reg_rctl = 0; 1769 int mcnt = 0; 1770 1771 IOCTL_DEBUGOUT("em_set_multi: begin"); 1772 1773 mta = sc->mta; 1774 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1775 1776 if (sc->hw.mac.type == e1000_82542 && 1777 sc->hw.revision_id == E1000_REVISION_2) { 1778 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1779 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1780 e1000_pci_clear_mwi(&sc->hw); 1781 reg_rctl |= E1000_RCTL_RST; 1782 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1783 msec_delay(5); 1784 } 1785 1786 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1787 1788 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1789 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1790 1791 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1792 1793 if (if_getflags(ifp) & IFF_PROMISC) 1794 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1795 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1796 if_getflags(ifp) & IFF_ALLMULTI) { 1797 reg_rctl |= E1000_RCTL_MPE; 1798 reg_rctl &= ~E1000_RCTL_UPE; 1799 } else 1800 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1801 1802 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1803 1804 if (sc->hw.mac.type == e1000_82542 && 1805 sc->hw.revision_id == E1000_REVISION_2) { 1806 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1807 reg_rctl &= ~E1000_RCTL_RST; 1808 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1809 msec_delay(5); 1810 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1811 e1000_pci_set_mwi(&sc->hw); 1812 } 1813 } 1814 1815 /********************************************************************* 1816 * Timer routine 1817 * 1818 * This routine schedules em_if_update_admin_status() to check for 1819 * link status and to gather statistics as well as to perform some 1820 * controller-specific hardware patting. 1821 * 1822 **********************************************************************/ 1823 static void 1824 em_if_timer(if_ctx_t ctx, uint16_t qid) 1825 { 1826 1827 if (qid != 0) 1828 return; 1829 1830 iflib_admin_intr_deferred(ctx); 1831 } 1832 1833 static void 1834 em_if_update_admin_status(if_ctx_t ctx) 1835 { 1836 struct e1000_softc *sc = iflib_get_softc(ctx); 1837 struct e1000_hw *hw = &sc->hw; 1838 device_t dev = iflib_get_dev(ctx); 1839 u32 link_check, thstat, ctrl; 1840 bool automasked = false; 1841 1842 link_check = thstat = ctrl = 0; 1843 /* Get the cached link value or read phy for real */ 1844 switch (hw->phy.media_type) { 1845 case e1000_media_type_copper: 1846 if (hw->mac.get_link_status) { 1847 if (hw->mac.type == e1000_pch_spt) 1848 msec_delay(50); 1849 /* Do the work to read phy */ 1850 e1000_check_for_link(hw); 1851 link_check = !hw->mac.get_link_status; 1852 if (link_check) /* ESB2 fix */ 1853 e1000_cfg_on_link_up(hw); 1854 } else { 1855 link_check = true; 1856 } 1857 break; 1858 case e1000_media_type_fiber: 1859 e1000_check_for_link(hw); 1860 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1861 E1000_STATUS_LU); 1862 break; 1863 case e1000_media_type_internal_serdes: 1864 e1000_check_for_link(hw); 1865 link_check = hw->mac.serdes_has_link; 1866 break; 1867 /* VF device is type_unknown */ 1868 case e1000_media_type_unknown: 1869 e1000_check_for_link(hw); 1870 link_check = !hw->mac.get_link_status; 1871 /* FALLTHROUGH */ 1872 default: 1873 break; 1874 } 1875 1876 /* Check for thermal downshift or shutdown */ 1877 if (hw->mac.type == e1000_i350) { 1878 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1879 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1880 } 1881 1882 /* Now check for a transition */ 1883 if (link_check && (sc->link_active == 0)) { 1884 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1885 &sc->link_duplex); 1886 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1887 if ((sc->link_speed != SPEED_1000) && 1888 ((hw->mac.type == e1000_82571) || 1889 (hw->mac.type == e1000_82572))) { 1890 int tarc0; 1891 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1892 tarc0 &= ~TARC_SPEED_MODE_BIT; 1893 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1894 } 1895 if (bootverbose) 1896 device_printf(dev, "Link is up %d Mbps %s\n", 1897 sc->link_speed, 1898 ((sc->link_duplex == FULL_DUPLEX) ? 1899 "Full Duplex" : "Half Duplex")); 1900 sc->link_active = 1; 1901 sc->smartspeed = 0; 1902 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1903 E1000_CTRL_EXT_LINK_MODE_GMII && 1904 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1905 device_printf(dev, "Link: thermal downshift\n"); 1906 /* Delay Link Up for Phy update */ 1907 if (((hw->mac.type == e1000_i210) || 1908 (hw->mac.type == e1000_i211)) && 1909 (hw->phy.id == I210_I_PHY_ID)) 1910 msec_delay(I210_LINK_DELAY); 1911 /* Reset if the media type changed. */ 1912 if (hw->dev_spec._82575.media_changed && 1913 hw->mac.type >= igb_mac_min) { 1914 hw->dev_spec._82575.media_changed = false; 1915 sc->flags |= IGB_MEDIA_RESET; 1916 em_reset(ctx); 1917 } 1918 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 1919 if (hw->mac.type < igb_mac_min) 1920 automasked = em_automask_tso(ctx); 1921 1922 /* Automasking resets the interface, so don't mark it up yet */ 1923 if (!automasked) 1924 iflib_link_state_change(ctx, LINK_STATE_UP, 1925 IF_Mbps(sc->link_speed)); 1926 } else if (!link_check && (sc->link_active == 1)) { 1927 sc->link_speed = 0; 1928 sc->link_duplex = 0; 1929 sc->link_active = 0; 1930 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1931 } 1932 em_update_stats_counters(sc); 1933 1934 /* Reset LAA into RAR[0] on 82571 */ 1935 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1936 e1000_rar_set(hw, hw->mac.addr, 0); 1937 1938 if (hw->mac.type < em_mac_min) 1939 lem_smartspeed(sc); 1940 } 1941 1942 static void 1943 em_if_watchdog_reset(if_ctx_t ctx) 1944 { 1945 struct e1000_softc *sc = iflib_get_softc(ctx); 1946 1947 /* 1948 * Just count the event; iflib(4) will already trigger a 1949 * sufficient reset of the controller. 1950 */ 1951 sc->watchdog_events++; 1952 } 1953 1954 /********************************************************************* 1955 * 1956 * This routine disables all traffic on the adapter by issuing a 1957 * global reset on the MAC. 1958 * 1959 **********************************************************************/ 1960 static void 1961 em_if_stop(if_ctx_t ctx) 1962 { 1963 struct e1000_softc *sc = iflib_get_softc(ctx); 1964 1965 INIT_DEBUGOUT("em_if_stop: begin"); 1966 1967 /* I219 needs special flushing to avoid hangs */ 1968 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1969 em_flush_desc_rings(sc); 1970 1971 e1000_reset_hw(&sc->hw); 1972 if (sc->hw.mac.type >= e1000_82544) 1973 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1974 1975 e1000_led_off(&sc->hw); 1976 e1000_cleanup_led(&sc->hw); 1977 } 1978 1979 /********************************************************************* 1980 * 1981 * Determine hardware revision. 1982 * 1983 **********************************************************************/ 1984 static void 1985 em_identify_hardware(if_ctx_t ctx) 1986 { 1987 device_t dev = iflib_get_dev(ctx); 1988 struct e1000_softc *sc = iflib_get_softc(ctx); 1989 1990 /* Make sure our PCI config space has the necessary stuff set */ 1991 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1992 1993 /* Save off the information about this board */ 1994 sc->hw.vendor_id = pci_get_vendor(dev); 1995 sc->hw.device_id = pci_get_device(dev); 1996 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1997 sc->hw.subsystem_vendor_id = 1998 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1999 sc->hw.subsystem_device_id = 2000 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2001 2002 /* Do Shared Code Init and Setup */ 2003 if (e1000_set_mac_type(&sc->hw)) { 2004 device_printf(dev, "Setup init failure\n"); 2005 return; 2006 } 2007 2008 /* Are we a VF device? */ 2009 if ((sc->hw.mac.type == e1000_vfadapt) || 2010 (sc->hw.mac.type == e1000_vfadapt_i350)) 2011 sc->vf_ifp = 1; 2012 else 2013 sc->vf_ifp = 0; 2014 } 2015 2016 static int 2017 em_allocate_pci_resources(if_ctx_t ctx) 2018 { 2019 struct e1000_softc *sc = iflib_get_softc(ctx); 2020 device_t dev = iflib_get_dev(ctx); 2021 int rid, val; 2022 2023 rid = PCIR_BAR(0); 2024 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2025 &rid, RF_ACTIVE); 2026 if (sc->memory == NULL) { 2027 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2028 return (ENXIO); 2029 } 2030 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2031 sc->osdep.mem_bus_space_handle = 2032 rman_get_bushandle(sc->memory); 2033 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2034 2035 /* Only older adapters use IO mapping */ 2036 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2037 /* Figure our where our IO BAR is ? */ 2038 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2039 val = pci_read_config(dev, rid, 4); 2040 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2041 break; 2042 } 2043 rid += 4; 2044 /* check for 64bit BAR */ 2045 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2046 rid += 4; 2047 } 2048 if (rid >= PCIR_CIS) { 2049 device_printf(dev, "Unable to locate IO BAR\n"); 2050 return (ENXIO); 2051 } 2052 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2053 &rid, RF_ACTIVE); 2054 if (sc->ioport == NULL) { 2055 device_printf(dev, "Unable to allocate bus resource: " 2056 "ioport\n"); 2057 return (ENXIO); 2058 } 2059 sc->hw.io_base = 0; 2060 sc->osdep.io_bus_space_tag = 2061 rman_get_bustag(sc->ioport); 2062 sc->osdep.io_bus_space_handle = 2063 rman_get_bushandle(sc->ioport); 2064 } 2065 2066 sc->hw.back = &sc->osdep; 2067 2068 return (0); 2069 } 2070 2071 /********************************************************************* 2072 * 2073 * Set up the MSI-X Interrupt handlers 2074 * 2075 **********************************************************************/ 2076 static int 2077 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2078 { 2079 struct e1000_softc *sc = iflib_get_softc(ctx); 2080 struct em_rx_queue *rx_que = sc->rx_queues; 2081 struct em_tx_queue *tx_que = sc->tx_queues; 2082 int error, rid, i, vector = 0, rx_vectors; 2083 char buf[16]; 2084 2085 /* First set up ring resources */ 2086 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2087 rid = vector + 1; 2088 snprintf(buf, sizeof(buf), "rxq%d", i); 2089 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2090 if (error) { 2091 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2092 sc->rx_num_queues = i + 1; 2093 goto fail; 2094 } 2095 2096 rx_que->msix = vector; 2097 2098 /* 2099 * Set the bit to enable interrupt 2100 * in E1000_IMS -- bits 20 and 21 2101 * are for RX0 and RX1, note this has 2102 * NOTHING to do with the MSI-X vector 2103 */ 2104 if (sc->hw.mac.type == e1000_82574) { 2105 rx_que->eims = 1 << (20 + i); 2106 sc->ims |= rx_que->eims; 2107 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2108 } else if (sc->hw.mac.type == e1000_82575) 2109 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2110 else 2111 rx_que->eims = 1 << vector; 2112 } 2113 rx_vectors = vector; 2114 2115 vector = 0; 2116 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2117 snprintf(buf, sizeof(buf), "txq%d", i); 2118 tx_que = &sc->tx_queues[i]; 2119 iflib_softirq_alloc_generic(ctx, 2120 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2121 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2122 2123 tx_que->msix = (vector % sc->rx_num_queues); 2124 2125 /* 2126 * Set the bit to enable interrupt 2127 * in E1000_IMS -- bits 22 and 23 2128 * are for TX0 and TX1, note this has 2129 * NOTHING to do with the MSI-X vector 2130 */ 2131 if (sc->hw.mac.type == e1000_82574) { 2132 tx_que->eims = 1 << (22 + i); 2133 sc->ims |= tx_que->eims; 2134 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2135 } else if (sc->hw.mac.type == e1000_82575) { 2136 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2137 } else { 2138 tx_que->eims = 1 << i; 2139 } 2140 } 2141 2142 /* Link interrupt */ 2143 rid = rx_vectors + 1; 2144 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2145 2146 if (error) { 2147 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2148 goto fail; 2149 } 2150 sc->linkvec = rx_vectors; 2151 if (sc->hw.mac.type < igb_mac_min) { 2152 sc->ivars |= (8 | rx_vectors) << 16; 2153 sc->ivars |= 0x80000000; 2154 /* Enable the "Other" interrupt type for link status change */ 2155 sc->ims |= E1000_IMS_OTHER; 2156 } 2157 2158 return (0); 2159 fail: 2160 iflib_irq_free(ctx, &sc->irq); 2161 rx_que = sc->rx_queues; 2162 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2163 iflib_irq_free(ctx, &rx_que->que_irq); 2164 return (error); 2165 } 2166 2167 static void 2168 igb_configure_queues(struct e1000_softc *sc) 2169 { 2170 struct e1000_hw *hw = &sc->hw; 2171 struct em_rx_queue *rx_que; 2172 struct em_tx_queue *tx_que; 2173 u32 tmp, ivar = 0, newitr = 0; 2174 2175 /* First turn on RSS capability */ 2176 if (hw->mac.type != e1000_82575) 2177 E1000_WRITE_REG(hw, E1000_GPIE, 2178 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2179 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2180 2181 /* Turn on MSI-X */ 2182 switch (hw->mac.type) { 2183 case e1000_82580: 2184 case e1000_i350: 2185 case e1000_i354: 2186 case e1000_i210: 2187 case e1000_i211: 2188 case e1000_vfadapt: 2189 case e1000_vfadapt_i350: 2190 /* RX entries */ 2191 for (int i = 0; i < sc->rx_num_queues; i++) { 2192 u32 index = i >> 1; 2193 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2194 rx_que = &sc->rx_queues[i]; 2195 if (i & 1) { 2196 ivar &= 0xFF00FFFF; 2197 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2198 } else { 2199 ivar &= 0xFFFFFF00; 2200 ivar |= rx_que->msix | E1000_IVAR_VALID; 2201 } 2202 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2203 } 2204 /* TX entries */ 2205 for (int i = 0; i < sc->tx_num_queues; i++) { 2206 u32 index = i >> 1; 2207 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2208 tx_que = &sc->tx_queues[i]; 2209 if (i & 1) { 2210 ivar &= 0x00FFFFFF; 2211 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2212 } else { 2213 ivar &= 0xFFFF00FF; 2214 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2215 } 2216 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2217 sc->que_mask |= tx_que->eims; 2218 } 2219 2220 /* And for the link interrupt */ 2221 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2222 sc->link_mask = 1 << sc->linkvec; 2223 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2224 break; 2225 case e1000_82576: 2226 /* RX entries */ 2227 for (int i = 0; i < sc->rx_num_queues; i++) { 2228 u32 index = i & 0x7; /* Each IVAR has two entries */ 2229 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2230 rx_que = &sc->rx_queues[i]; 2231 if (i < 8) { 2232 ivar &= 0xFFFFFF00; 2233 ivar |= rx_que->msix | E1000_IVAR_VALID; 2234 } else { 2235 ivar &= 0xFF00FFFF; 2236 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2237 } 2238 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2239 sc->que_mask |= rx_que->eims; 2240 } 2241 /* TX entries */ 2242 for (int i = 0; i < sc->tx_num_queues; i++) { 2243 u32 index = i & 0x7; /* Each IVAR has two entries */ 2244 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2245 tx_que = &sc->tx_queues[i]; 2246 if (i < 8) { 2247 ivar &= 0xFFFF00FF; 2248 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2249 } else { 2250 ivar &= 0x00FFFFFF; 2251 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2252 } 2253 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2254 sc->que_mask |= tx_que->eims; 2255 } 2256 2257 /* And for the link interrupt */ 2258 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2259 sc->link_mask = 1 << sc->linkvec; 2260 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2261 break; 2262 2263 case e1000_82575: 2264 /* enable MSI-X support*/ 2265 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2266 tmp |= E1000_CTRL_EXT_PBA_CLR; 2267 /* Auto-Mask interrupts upon ICR read. */ 2268 tmp |= E1000_CTRL_EXT_EIAME; 2269 tmp |= E1000_CTRL_EXT_IRCA; 2270 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2271 2272 /* Queues */ 2273 for (int i = 0; i < sc->rx_num_queues; i++) { 2274 rx_que = &sc->rx_queues[i]; 2275 tmp = E1000_EICR_RX_QUEUE0 << i; 2276 tmp |= E1000_EICR_TX_QUEUE0 << i; 2277 rx_que->eims = tmp; 2278 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2279 i, rx_que->eims); 2280 sc->que_mask |= rx_que->eims; 2281 } 2282 2283 /* Link */ 2284 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2285 E1000_EIMS_OTHER); 2286 sc->link_mask |= E1000_EIMS_OTHER; 2287 default: 2288 break; 2289 } 2290 2291 /* Set the starting interrupt rate */ 2292 if (em_max_interrupt_rate > 0) 2293 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2294 2295 if (hw->mac.type == e1000_82575) 2296 newitr |= newitr << 16; 2297 else 2298 newitr |= E1000_EITR_CNT_IGNR; 2299 2300 for (int i = 0; i < sc->rx_num_queues; i++) { 2301 rx_que = &sc->rx_queues[i]; 2302 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2303 } 2304 2305 return; 2306 } 2307 2308 static void 2309 em_free_pci_resources(if_ctx_t ctx) 2310 { 2311 struct e1000_softc *sc = iflib_get_softc(ctx); 2312 struct em_rx_queue *que = sc->rx_queues; 2313 device_t dev = iflib_get_dev(ctx); 2314 2315 /* Release all MSI-X queue resources */ 2316 if (sc->intr_type == IFLIB_INTR_MSIX) 2317 iflib_irq_free(ctx, &sc->irq); 2318 2319 if (que != NULL) { 2320 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2321 iflib_irq_free(ctx, &que->que_irq); 2322 } 2323 } 2324 2325 if (sc->memory != NULL) { 2326 bus_release_resource(dev, SYS_RES_MEMORY, 2327 rman_get_rid(sc->memory), sc->memory); 2328 sc->memory = NULL; 2329 } 2330 2331 if (sc->flash != NULL) { 2332 bus_release_resource(dev, SYS_RES_MEMORY, 2333 rman_get_rid(sc->flash), sc->flash); 2334 sc->flash = NULL; 2335 } 2336 2337 if (sc->ioport != NULL) { 2338 bus_release_resource(dev, SYS_RES_IOPORT, 2339 rman_get_rid(sc->ioport), sc->ioport); 2340 sc->ioport = NULL; 2341 } 2342 } 2343 2344 /* Set up MSI or MSI-X */ 2345 static int 2346 em_setup_msix(if_ctx_t ctx) 2347 { 2348 struct e1000_softc *sc = iflib_get_softc(ctx); 2349 2350 if (sc->hw.mac.type == e1000_82574) { 2351 em_enable_vectors_82574(ctx); 2352 } 2353 return (0); 2354 } 2355 2356 /********************************************************************* 2357 * 2358 * Workaround for SmartSpeed on 82541 and 82547 controllers 2359 * 2360 **********************************************************************/ 2361 static void 2362 lem_smartspeed(struct e1000_softc *sc) 2363 { 2364 u16 phy_tmp; 2365 2366 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2367 sc->hw.mac.autoneg == 0 || 2368 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2369 return; 2370 2371 if (sc->smartspeed == 0) { 2372 /* If Master/Slave config fault is asserted twice, 2373 * we assume back-to-back */ 2374 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2375 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2376 return; 2377 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2378 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2379 e1000_read_phy_reg(&sc->hw, 2380 PHY_1000T_CTRL, &phy_tmp); 2381 if(phy_tmp & CR_1000T_MS_ENABLE) { 2382 phy_tmp &= ~CR_1000T_MS_ENABLE; 2383 e1000_write_phy_reg(&sc->hw, 2384 PHY_1000T_CTRL, phy_tmp); 2385 sc->smartspeed++; 2386 if(sc->hw.mac.autoneg && 2387 !e1000_copper_link_autoneg(&sc->hw) && 2388 !e1000_read_phy_reg(&sc->hw, 2389 PHY_CONTROL, &phy_tmp)) { 2390 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2391 MII_CR_RESTART_AUTO_NEG); 2392 e1000_write_phy_reg(&sc->hw, 2393 PHY_CONTROL, phy_tmp); 2394 } 2395 } 2396 } 2397 return; 2398 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2399 /* If still no link, perhaps using 2/3 pair cable */ 2400 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2401 phy_tmp |= CR_1000T_MS_ENABLE; 2402 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2403 if(sc->hw.mac.autoneg && 2404 !e1000_copper_link_autoneg(&sc->hw) && 2405 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2406 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2407 MII_CR_RESTART_AUTO_NEG); 2408 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2409 } 2410 } 2411 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2412 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2413 sc->smartspeed = 0; 2414 } 2415 2416 /********************************************************************* 2417 * 2418 * Initialize the DMA Coalescing feature 2419 * 2420 **********************************************************************/ 2421 static void 2422 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2423 { 2424 device_t dev = sc->dev; 2425 struct e1000_hw *hw = &sc->hw; 2426 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2427 u16 hwm; 2428 u16 max_frame_size; 2429 2430 if (hw->mac.type == e1000_i211) 2431 return; 2432 2433 max_frame_size = sc->shared->isc_max_frame_size; 2434 if (hw->mac.type > e1000_82580) { 2435 2436 if (sc->dmac == 0) { /* Disabling it */ 2437 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2438 return; 2439 } else 2440 device_printf(dev, "DMA Coalescing enabled\n"); 2441 2442 /* Set starting threshold */ 2443 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2444 2445 hwm = 64 * pba - max_frame_size / 16; 2446 if (hwm < 64 * (pba - 6)) 2447 hwm = 64 * (pba - 6); 2448 reg = E1000_READ_REG(hw, E1000_FCRTC); 2449 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2450 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2451 & E1000_FCRTC_RTH_COAL_MASK); 2452 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2453 2454 2455 dmac = pba - max_frame_size / 512; 2456 if (dmac < pba - 10) 2457 dmac = pba - 10; 2458 reg = E1000_READ_REG(hw, E1000_DMACR); 2459 reg &= ~E1000_DMACR_DMACTHR_MASK; 2460 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2461 & E1000_DMACR_DMACTHR_MASK); 2462 2463 /* transition to L0x or L1 if available..*/ 2464 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2465 2466 /* Check if status is 2.5Gb backplane connection 2467 * before configuration of watchdog timer, which is 2468 * in msec values in 12.8usec intervals 2469 * watchdog timer= msec values in 32usec intervals 2470 * for non 2.5Gb connection 2471 */ 2472 if (hw->mac.type == e1000_i354) { 2473 int status = E1000_READ_REG(hw, E1000_STATUS); 2474 if ((status & E1000_STATUS_2P5_SKU) && 2475 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2476 reg |= ((sc->dmac * 5) >> 6); 2477 else 2478 reg |= (sc->dmac >> 5); 2479 } else { 2480 reg |= (sc->dmac >> 5); 2481 } 2482 2483 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2484 2485 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2486 2487 /* Set the interval before transition */ 2488 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2489 if (hw->mac.type == e1000_i350) 2490 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2491 /* 2492 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2493 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2494 */ 2495 if (hw->mac.type == e1000_i354) { 2496 int status = E1000_READ_REG(hw, E1000_STATUS); 2497 if ((status & E1000_STATUS_2P5_SKU) && 2498 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2499 reg |= 0xA; 2500 else 2501 reg |= 0x4; 2502 } else { 2503 reg |= 0x4; 2504 } 2505 2506 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2507 2508 /* free space in tx packet buffer to wake from DMA coal */ 2509 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2510 (2 * max_frame_size)) >> 6); 2511 2512 /* make low power state decision controlled by DMA coal */ 2513 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2514 reg &= ~E1000_PCIEMISC_LX_DECISION; 2515 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2516 2517 } else if (hw->mac.type == e1000_82580) { 2518 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2519 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2520 reg & ~E1000_PCIEMISC_LX_DECISION); 2521 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2522 } 2523 } 2524 /********************************************************************* 2525 * The 3 following flush routines are used as a workaround in the 2526 * I219 client parts and only for them. 2527 * 2528 * em_flush_tx_ring - remove all descriptors from the tx_ring 2529 * 2530 * We want to clear all pending descriptors from the TX ring. 2531 * zeroing happens when the HW reads the regs. We assign the ring itself as 2532 * the data of the next descriptor. We don't care about the data we are about 2533 * to reset the HW. 2534 **********************************************************************/ 2535 static void 2536 em_flush_tx_ring(struct e1000_softc *sc) 2537 { 2538 struct e1000_hw *hw = &sc->hw; 2539 struct tx_ring *txr = &sc->tx_queues->txr; 2540 struct e1000_tx_desc *txd; 2541 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2542 u16 size = 512; 2543 2544 tctl = E1000_READ_REG(hw, E1000_TCTL); 2545 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2546 2547 txd = &txr->tx_base[txr->tx_cidx_processed]; 2548 2549 /* Just use the ring as a dummy buffer addr */ 2550 txd->buffer_addr = txr->tx_paddr; 2551 txd->lower.data = htole32(txd_lower | size); 2552 txd->upper.data = 0; 2553 2554 /* flush descriptors to memory before notifying the HW */ 2555 wmb(); 2556 2557 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2558 mb(); 2559 usec_delay(250); 2560 } 2561 2562 /********************************************************************* 2563 * em_flush_rx_ring - remove all descriptors from the rx_ring 2564 * 2565 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2566 **********************************************************************/ 2567 static void 2568 em_flush_rx_ring(struct e1000_softc *sc) 2569 { 2570 struct e1000_hw *hw = &sc->hw; 2571 u32 rctl, rxdctl; 2572 2573 rctl = E1000_READ_REG(hw, E1000_RCTL); 2574 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2575 E1000_WRITE_FLUSH(hw); 2576 usec_delay(150); 2577 2578 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2579 /* zero the lower 14 bits (prefetch and host thresholds) */ 2580 rxdctl &= 0xffffc000; 2581 /* 2582 * update thresholds: prefetch threshold to 31, host threshold to 1 2583 * and make sure the granularity is "descriptors" and not "cache lines" 2584 */ 2585 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2586 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2587 2588 /* momentarily enable the RX ring for the changes to take effect */ 2589 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2590 E1000_WRITE_FLUSH(hw); 2591 usec_delay(150); 2592 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2593 } 2594 2595 /********************************************************************* 2596 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2597 * 2598 * In I219, the descriptor rings must be emptied before resetting the HW 2599 * or before changing the device state to D3 during runtime (runtime PM). 2600 * 2601 * Failure to do this will cause the HW to enter a unit hang state which can 2602 * only be released by PCI reset on the device 2603 * 2604 **********************************************************************/ 2605 static void 2606 em_flush_desc_rings(struct e1000_softc *sc) 2607 { 2608 struct e1000_hw *hw = &sc->hw; 2609 device_t dev = sc->dev; 2610 u16 hang_state; 2611 u32 fext_nvm11, tdlen; 2612 2613 /* First, disable MULR fix in FEXTNVM11 */ 2614 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2615 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2616 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2617 2618 /* do nothing if we're not in faulty state, or if the queue is empty */ 2619 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2620 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2621 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2622 return; 2623 em_flush_tx_ring(sc); 2624 2625 /* recheck, maybe the fault is caused by the rx ring */ 2626 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2627 if (hang_state & FLUSH_DESC_REQUIRED) 2628 em_flush_rx_ring(sc); 2629 } 2630 2631 2632 /********************************************************************* 2633 * 2634 * Initialize the hardware to a configuration as specified by the 2635 * sc structure. 2636 * 2637 **********************************************************************/ 2638 static void 2639 em_reset(if_ctx_t ctx) 2640 { 2641 device_t dev = iflib_get_dev(ctx); 2642 struct e1000_softc *sc = iflib_get_softc(ctx); 2643 if_t ifp = iflib_get_ifp(ctx); 2644 struct e1000_hw *hw = &sc->hw; 2645 u32 rx_buffer_size; 2646 u32 pba; 2647 2648 INIT_DEBUGOUT("em_reset: begin"); 2649 /* Let the firmware know the OS is in control */ 2650 em_get_hw_control(sc); 2651 2652 /* Set up smart power down as default off on newer adapters. */ 2653 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2654 hw->mac.type == e1000_82572)) { 2655 u16 phy_tmp = 0; 2656 2657 /* Speed up time to link by disabling smart power down. */ 2658 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2659 phy_tmp &= ~IGP02E1000_PM_SPD; 2660 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2661 } 2662 2663 /* 2664 * Packet Buffer Allocation (PBA) 2665 * Writing PBA sets the receive portion of the buffer 2666 * the remainder is used for the transmit buffer. 2667 */ 2668 switch (hw->mac.type) { 2669 /* 82547: Total Packet Buffer is 40K */ 2670 case e1000_82547: 2671 case e1000_82547_rev_2: 2672 if (hw->mac.max_frame_size > 8192) 2673 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2674 else 2675 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2676 break; 2677 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2678 case e1000_82571: 2679 case e1000_82572: 2680 case e1000_80003es2lan: 2681 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2682 break; 2683 /* 82573: Total Packet Buffer is 32K */ 2684 case e1000_82573: 2685 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2686 break; 2687 case e1000_82574: 2688 case e1000_82583: 2689 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2690 break; 2691 case e1000_ich8lan: 2692 pba = E1000_PBA_8K; 2693 break; 2694 case e1000_ich9lan: 2695 case e1000_ich10lan: 2696 /* Boost Receive side for jumbo frames */ 2697 if (hw->mac.max_frame_size > 4096) 2698 pba = E1000_PBA_14K; 2699 else 2700 pba = E1000_PBA_10K; 2701 break; 2702 case e1000_pchlan: 2703 case e1000_pch2lan: 2704 case e1000_pch_lpt: 2705 case e1000_pch_spt: 2706 case e1000_pch_cnp: 2707 case e1000_pch_tgp: 2708 case e1000_pch_adp: 2709 case e1000_pch_mtp: 2710 case e1000_pch_ptp: 2711 pba = E1000_PBA_26K; 2712 break; 2713 case e1000_82575: 2714 pba = E1000_PBA_32K; 2715 break; 2716 case e1000_82576: 2717 case e1000_vfadapt: 2718 pba = E1000_READ_REG(hw, E1000_RXPBS); 2719 pba &= E1000_RXPBS_SIZE_MASK_82576; 2720 break; 2721 case e1000_82580: 2722 case e1000_i350: 2723 case e1000_i354: 2724 case e1000_vfadapt_i350: 2725 pba = E1000_READ_REG(hw, E1000_RXPBS); 2726 pba = e1000_rxpbs_adjust_82580(pba); 2727 break; 2728 case e1000_i210: 2729 case e1000_i211: 2730 pba = E1000_PBA_34K; 2731 break; 2732 default: 2733 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2734 if (hw->mac.max_frame_size > 8192) 2735 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2736 else 2737 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2738 } 2739 2740 /* Special needs in case of Jumbo frames */ 2741 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2742 u32 tx_space, min_tx, min_rx; 2743 pba = E1000_READ_REG(hw, E1000_PBA); 2744 tx_space = pba >> 16; 2745 pba &= 0xffff; 2746 min_tx = (hw->mac.max_frame_size + 2747 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2748 min_tx = roundup2(min_tx, 1024); 2749 min_tx >>= 10; 2750 min_rx = hw->mac.max_frame_size; 2751 min_rx = roundup2(min_rx, 1024); 2752 min_rx >>= 10; 2753 if (tx_space < min_tx && 2754 ((min_tx - tx_space) < pba)) { 2755 pba = pba - (min_tx - tx_space); 2756 /* 2757 * if short on rx space, rx wins 2758 * and must trump tx adjustment 2759 */ 2760 if (pba < min_rx) 2761 pba = min_rx; 2762 } 2763 E1000_WRITE_REG(hw, E1000_PBA, pba); 2764 } 2765 2766 if (hw->mac.type < igb_mac_min) 2767 E1000_WRITE_REG(hw, E1000_PBA, pba); 2768 2769 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2770 2771 /* 2772 * These parameters control the automatic generation (Tx) and 2773 * response (Rx) to Ethernet PAUSE frames. 2774 * - High water mark should allow for at least two frames to be 2775 * received after sending an XOFF. 2776 * - Low water mark works best when it is very near the high water mark. 2777 * This allows the receiver to restart by sending XON when it has 2778 * drained a bit. Here we use an arbitrary value of 1500 which will 2779 * restart after one full frame is pulled from the buffer. There 2780 * could be several smaller frames in the buffer and if so they will 2781 * not trigger the XON until their total number reduces the buffer 2782 * by 1500. 2783 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2784 */ 2785 rx_buffer_size = (pba & 0xffff) << 10; 2786 hw->fc.high_water = rx_buffer_size - 2787 roundup2(hw->mac.max_frame_size, 1024); 2788 hw->fc.low_water = hw->fc.high_water - 1500; 2789 2790 if (sc->fc) /* locally set flow control value? */ 2791 hw->fc.requested_mode = sc->fc; 2792 else 2793 hw->fc.requested_mode = e1000_fc_full; 2794 2795 if (hw->mac.type == e1000_80003es2lan) 2796 hw->fc.pause_time = 0xFFFF; 2797 else 2798 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2799 2800 hw->fc.send_xon = true; 2801 2802 /* Device specific overrides/settings */ 2803 switch (hw->mac.type) { 2804 case e1000_pchlan: 2805 /* Workaround: no TX flow ctrl for PCH */ 2806 hw->fc.requested_mode = e1000_fc_rx_pause; 2807 hw->fc.pause_time = 0xFFFF; /* override */ 2808 if (if_getmtu(ifp) > ETHERMTU) { 2809 hw->fc.high_water = 0x3500; 2810 hw->fc.low_water = 0x1500; 2811 } else { 2812 hw->fc.high_water = 0x5000; 2813 hw->fc.low_water = 0x3000; 2814 } 2815 hw->fc.refresh_time = 0x1000; 2816 break; 2817 case e1000_pch2lan: 2818 case e1000_pch_lpt: 2819 case e1000_pch_spt: 2820 case e1000_pch_cnp: 2821 case e1000_pch_tgp: 2822 case e1000_pch_adp: 2823 case e1000_pch_mtp: 2824 case e1000_pch_ptp: 2825 hw->fc.high_water = 0x5C20; 2826 hw->fc.low_water = 0x5048; 2827 hw->fc.pause_time = 0x0650; 2828 hw->fc.refresh_time = 0x0400; 2829 /* Jumbos need adjusted PBA */ 2830 if (if_getmtu(ifp) > ETHERMTU) 2831 E1000_WRITE_REG(hw, E1000_PBA, 12); 2832 else 2833 E1000_WRITE_REG(hw, E1000_PBA, 26); 2834 break; 2835 case e1000_82575: 2836 case e1000_82576: 2837 /* 8-byte granularity */ 2838 hw->fc.low_water = hw->fc.high_water - 8; 2839 break; 2840 case e1000_82580: 2841 case e1000_i350: 2842 case e1000_i354: 2843 case e1000_i210: 2844 case e1000_i211: 2845 case e1000_vfadapt: 2846 case e1000_vfadapt_i350: 2847 /* 16-byte granularity */ 2848 hw->fc.low_water = hw->fc.high_water - 16; 2849 break; 2850 case e1000_ich9lan: 2851 case e1000_ich10lan: 2852 if (if_getmtu(ifp) > ETHERMTU) { 2853 hw->fc.high_water = 0x2800; 2854 hw->fc.low_water = hw->fc.high_water - 8; 2855 break; 2856 } 2857 /* FALLTHROUGH */ 2858 default: 2859 if (hw->mac.type == e1000_80003es2lan) 2860 hw->fc.pause_time = 0xFFFF; 2861 break; 2862 } 2863 2864 /* I219 needs some special flushing to avoid hangs */ 2865 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2866 em_flush_desc_rings(sc); 2867 2868 /* Issue a global reset */ 2869 e1000_reset_hw(hw); 2870 if (hw->mac.type >= igb_mac_min) { 2871 E1000_WRITE_REG(hw, E1000_WUC, 0); 2872 } else { 2873 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2874 em_disable_aspm(sc); 2875 } 2876 if (sc->flags & IGB_MEDIA_RESET) { 2877 e1000_setup_init_funcs(hw, true); 2878 e1000_get_bus_info(hw); 2879 sc->flags &= ~IGB_MEDIA_RESET; 2880 } 2881 /* and a re-init */ 2882 if (e1000_init_hw(hw) < 0) { 2883 device_printf(dev, "Hardware Initialization Failed\n"); 2884 return; 2885 } 2886 if (hw->mac.type >= igb_mac_min) 2887 igb_init_dmac(sc, pba); 2888 2889 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2890 e1000_get_phy_info(hw); 2891 e1000_check_for_link(hw); 2892 } 2893 2894 /* 2895 * Initialise the RSS mapping for NICs that support multiple transmit/ 2896 * receive rings. 2897 */ 2898 2899 #define RSSKEYLEN 10 2900 static void 2901 em_initialize_rss_mapping(struct e1000_softc *sc) 2902 { 2903 uint8_t rss_key[4 * RSSKEYLEN]; 2904 uint32_t reta = 0; 2905 struct e1000_hw *hw = &sc->hw; 2906 int i; 2907 2908 /* 2909 * Configure RSS key 2910 */ 2911 arc4rand(rss_key, sizeof(rss_key), 0); 2912 for (i = 0; i < RSSKEYLEN; ++i) { 2913 uint32_t rssrk = 0; 2914 2915 rssrk = EM_RSSRK_VAL(rss_key, i); 2916 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2917 } 2918 2919 /* 2920 * Configure RSS redirect table in following fashion: 2921 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2922 */ 2923 for (i = 0; i < sizeof(reta); ++i) { 2924 uint32_t q; 2925 2926 q = (i % sc->rx_num_queues) << 7; 2927 reta |= q << (8 * i); 2928 } 2929 2930 for (i = 0; i < 32; ++i) 2931 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2932 2933 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2934 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2935 E1000_MRQC_RSS_FIELD_IPV4 | 2936 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2937 E1000_MRQC_RSS_FIELD_IPV6_EX | 2938 E1000_MRQC_RSS_FIELD_IPV6); 2939 } 2940 2941 static void 2942 igb_initialize_rss_mapping(struct e1000_softc *sc) 2943 { 2944 struct e1000_hw *hw = &sc->hw; 2945 int i; 2946 int queue_id; 2947 u32 reta; 2948 u32 rss_key[10], mrqc, shift = 0; 2949 2950 /* XXX? */ 2951 if (hw->mac.type == e1000_82575) 2952 shift = 6; 2953 2954 /* 2955 * The redirection table controls which destination 2956 * queue each bucket redirects traffic to. 2957 * Each DWORD represents four queues, with the LSB 2958 * being the first queue in the DWORD. 2959 * 2960 * This just allocates buckets to queues using round-robin 2961 * allocation. 2962 * 2963 * NOTE: It Just Happens to line up with the default 2964 * RSS allocation method. 2965 */ 2966 2967 /* Warning FM follows */ 2968 reta = 0; 2969 for (i = 0; i < 128; i++) { 2970 #ifdef RSS 2971 queue_id = rss_get_indirection_to_bucket(i); 2972 /* 2973 * If we have more queues than buckets, we'll 2974 * end up mapping buckets to a subset of the 2975 * queues. 2976 * 2977 * If we have more buckets than queues, we'll 2978 * end up instead assigning multiple buckets 2979 * to queues. 2980 * 2981 * Both are suboptimal, but we need to handle 2982 * the case so we don't go out of bounds 2983 * indexing arrays and such. 2984 */ 2985 queue_id = queue_id % sc->rx_num_queues; 2986 #else 2987 queue_id = (i % sc->rx_num_queues); 2988 #endif 2989 /* Adjust if required */ 2990 queue_id = queue_id << shift; 2991 2992 /* 2993 * The low 8 bits are for hash value (n+0); 2994 * The next 8 bits are for hash value (n+1), etc. 2995 */ 2996 reta = reta >> 8; 2997 reta = reta | ( ((uint32_t) queue_id) << 24); 2998 if ((i & 3) == 3) { 2999 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3000 reta = 0; 3001 } 3002 } 3003 3004 /* Now fill in hash table */ 3005 3006 /* 3007 * MRQC: Multiple Receive Queues Command 3008 * Set queuing to RSS control, number depends on the device. 3009 */ 3010 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3011 3012 #ifdef RSS 3013 /* XXX ew typecasting */ 3014 rss_getkey((uint8_t *) &rss_key); 3015 #else 3016 arc4rand(&rss_key, sizeof(rss_key), 0); 3017 #endif 3018 for (i = 0; i < 10; i++) 3019 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3020 3021 /* 3022 * Configure the RSS fields to hash upon. 3023 */ 3024 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3025 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3026 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3027 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3028 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3029 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3030 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3031 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3032 3033 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3034 } 3035 3036 /********************************************************************* 3037 * 3038 * Setup networking device structure and register interface media. 3039 * 3040 **********************************************************************/ 3041 static int 3042 em_setup_interface(if_ctx_t ctx) 3043 { 3044 if_t ifp = iflib_get_ifp(ctx); 3045 struct e1000_softc *sc = iflib_get_softc(ctx); 3046 if_softc_ctx_t scctx = sc->shared; 3047 3048 INIT_DEBUGOUT("em_setup_interface: begin"); 3049 3050 /* Single Queue */ 3051 if (sc->tx_num_queues == 1) { 3052 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3053 if_setsendqready(ifp); 3054 } 3055 3056 /* 3057 * Specify the media types supported by this adapter and register 3058 * callbacks to update media and link information 3059 */ 3060 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3061 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3062 u_char fiber_type = IFM_1000_SX; /* default type */ 3063 3064 if (sc->hw.mac.type == e1000_82545) 3065 fiber_type = IFM_1000_LX; 3066 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3067 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3068 } else { 3069 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3070 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3071 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3072 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3073 if (sc->hw.phy.type != e1000_phy_ife) { 3074 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3075 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3076 } 3077 } 3078 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3079 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3080 return (0); 3081 } 3082 3083 static int 3084 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3085 { 3086 struct e1000_softc *sc = iflib_get_softc(ctx); 3087 if_softc_ctx_t scctx = sc->shared; 3088 int error = E1000_SUCCESS; 3089 struct em_tx_queue *que; 3090 int i, j; 3091 3092 MPASS(sc->tx_num_queues > 0); 3093 MPASS(sc->tx_num_queues == ntxqsets); 3094 3095 /* First allocate the top level queue structs */ 3096 if (!(sc->tx_queues = 3097 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3098 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3099 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3100 return(ENOMEM); 3101 } 3102 3103 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3104 /* Set up some basics */ 3105 3106 struct tx_ring *txr = &que->txr; 3107 txr->sc = que->sc = sc; 3108 que->me = txr->me = i; 3109 3110 /* Allocate report status array */ 3111 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3112 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3113 error = ENOMEM; 3114 goto fail; 3115 } 3116 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3117 txr->tx_rsq[j] = QIDX_INVALID; 3118 /* get the virtual and physical address of the hardware queues */ 3119 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3120 txr->tx_paddr = paddrs[i*ntxqs]; 3121 } 3122 3123 if (bootverbose) 3124 device_printf(iflib_get_dev(ctx), 3125 "allocated for %d tx_queues\n", sc->tx_num_queues); 3126 return (0); 3127 fail: 3128 em_if_queues_free(ctx); 3129 return (error); 3130 } 3131 3132 static int 3133 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3134 { 3135 struct e1000_softc *sc = iflib_get_softc(ctx); 3136 int error = E1000_SUCCESS; 3137 struct em_rx_queue *que; 3138 int i; 3139 3140 MPASS(sc->rx_num_queues > 0); 3141 MPASS(sc->rx_num_queues == nrxqsets); 3142 3143 /* First allocate the top level queue structs */ 3144 if (!(sc->rx_queues = 3145 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3146 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3147 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3148 error = ENOMEM; 3149 goto fail; 3150 } 3151 3152 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3153 /* Set up some basics */ 3154 struct rx_ring *rxr = &que->rxr; 3155 rxr->sc = que->sc = sc; 3156 rxr->que = que; 3157 que->me = rxr->me = i; 3158 3159 /* get the virtual and physical address of the hardware queues */ 3160 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3161 rxr->rx_paddr = paddrs[i*nrxqs]; 3162 } 3163 3164 if (bootverbose) 3165 device_printf(iflib_get_dev(ctx), 3166 "allocated for %d rx_queues\n", sc->rx_num_queues); 3167 3168 return (0); 3169 fail: 3170 em_if_queues_free(ctx); 3171 return (error); 3172 } 3173 3174 static void 3175 em_if_queues_free(if_ctx_t ctx) 3176 { 3177 struct e1000_softc *sc = iflib_get_softc(ctx); 3178 struct em_tx_queue *tx_que = sc->tx_queues; 3179 struct em_rx_queue *rx_que = sc->rx_queues; 3180 3181 if (tx_que != NULL) { 3182 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3183 struct tx_ring *txr = &tx_que->txr; 3184 if (txr->tx_rsq == NULL) 3185 break; 3186 3187 free(txr->tx_rsq, M_DEVBUF); 3188 txr->tx_rsq = NULL; 3189 } 3190 free(sc->tx_queues, M_DEVBUF); 3191 sc->tx_queues = NULL; 3192 } 3193 3194 if (rx_que != NULL) { 3195 free(sc->rx_queues, M_DEVBUF); 3196 sc->rx_queues = NULL; 3197 } 3198 } 3199 3200 /********************************************************************* 3201 * 3202 * Enable transmit unit. 3203 * 3204 **********************************************************************/ 3205 static void 3206 em_initialize_transmit_unit(if_ctx_t ctx) 3207 { 3208 struct e1000_softc *sc = iflib_get_softc(ctx); 3209 if_softc_ctx_t scctx = sc->shared; 3210 struct em_tx_queue *que; 3211 struct tx_ring *txr; 3212 struct e1000_hw *hw = &sc->hw; 3213 u32 tctl, txdctl = 0, tarc, tipg = 0; 3214 3215 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3216 3217 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3218 u64 bus_addr; 3219 caddr_t offp, endp; 3220 3221 que = &sc->tx_queues[i]; 3222 txr = &que->txr; 3223 bus_addr = txr->tx_paddr; 3224 3225 /* Clear checksum offload context. */ 3226 offp = (caddr_t)&txr->csum_flags; 3227 endp = (caddr_t)(txr + 1); 3228 bzero(offp, endp - offp); 3229 3230 /* Base and Len of TX Ring */ 3231 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3232 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3233 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3234 (u32)(bus_addr >> 32)); 3235 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3236 (u32)bus_addr); 3237 /* Init the HEAD/TAIL indices */ 3238 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3239 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3240 3241 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3242 E1000_READ_REG(hw, E1000_TDBAL(i)), 3243 E1000_READ_REG(hw, E1000_TDLEN(i))); 3244 3245 txdctl = 0; /* clear txdctl */ 3246 txdctl |= 0x1f; /* PTHRESH */ 3247 txdctl |= 1 << 8; /* HTHRESH */ 3248 txdctl |= 1 << 16;/* WTHRESH */ 3249 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3250 txdctl |= E1000_TXDCTL_GRAN; 3251 txdctl |= 1 << 25; /* LWTHRESH */ 3252 3253 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3254 } 3255 3256 /* Set the default values for the Tx Inter Packet Gap timer */ 3257 switch (hw->mac.type) { 3258 case e1000_80003es2lan: 3259 tipg = DEFAULT_82543_TIPG_IPGR1; 3260 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3261 E1000_TIPG_IPGR2_SHIFT; 3262 break; 3263 case e1000_82542: 3264 tipg = DEFAULT_82542_TIPG_IPGT; 3265 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3266 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3267 break; 3268 default: 3269 if (hw->phy.media_type == e1000_media_type_fiber || 3270 hw->phy.media_type == e1000_media_type_internal_serdes) 3271 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3272 else 3273 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3274 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3275 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3276 } 3277 3278 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3279 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3280 3281 if(hw->mac.type >= e1000_82540) 3282 E1000_WRITE_REG(hw, E1000_TADV, 3283 sc->tx_abs_int_delay.value); 3284 3285 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3286 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3287 tarc |= TARC_SPEED_MODE_BIT; 3288 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3289 } else if (hw->mac.type == e1000_80003es2lan) { 3290 /* errata: program both queues to unweighted RR */ 3291 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3292 tarc |= 1; 3293 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3294 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3295 tarc |= 1; 3296 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3297 } else if (hw->mac.type == e1000_82574) { 3298 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3299 tarc |= TARC_ERRATA_BIT; 3300 if ( sc->tx_num_queues > 1) { 3301 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3302 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3303 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3304 } else 3305 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3306 } 3307 3308 if (sc->tx_int_delay.value > 0) 3309 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3310 3311 /* Program the Transmit Control Register */ 3312 tctl = E1000_READ_REG(hw, E1000_TCTL); 3313 tctl &= ~E1000_TCTL_CT; 3314 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3315 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3316 3317 if (hw->mac.type >= e1000_82571) 3318 tctl |= E1000_TCTL_MULR; 3319 3320 /* This write will effectively turn on the transmit unit. */ 3321 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3322 3323 /* SPT and KBL errata workarounds */ 3324 if (hw->mac.type == e1000_pch_spt) { 3325 u32 reg; 3326 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3327 reg |= E1000_RCTL_RDMTS_HEX; 3328 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3329 /* i218-i219 Specification Update 1.5.4.5 */ 3330 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3331 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3332 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3333 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3334 } 3335 } 3336 3337 /********************************************************************* 3338 * 3339 * Enable receive unit. 3340 * 3341 **********************************************************************/ 3342 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3343 3344 static void 3345 em_initialize_receive_unit(if_ctx_t ctx) 3346 { 3347 struct e1000_softc *sc = iflib_get_softc(ctx); 3348 if_softc_ctx_t scctx = sc->shared; 3349 if_t ifp = iflib_get_ifp(ctx); 3350 struct e1000_hw *hw = &sc->hw; 3351 struct em_rx_queue *que; 3352 int i; 3353 uint32_t rctl, rxcsum; 3354 3355 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3356 3357 /* 3358 * Make sure receives are disabled while setting 3359 * up the descriptor ring 3360 */ 3361 rctl = E1000_READ_REG(hw, E1000_RCTL); 3362 /* Do not disable if ever enabled on this hardware */ 3363 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3364 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3365 3366 /* Setup the Receive Control Register */ 3367 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3368 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3369 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3370 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3371 3372 /* Do not store bad packets */ 3373 rctl &= ~E1000_RCTL_SBP; 3374 3375 /* Enable Long Packet receive */ 3376 if (if_getmtu(ifp) > ETHERMTU) 3377 rctl |= E1000_RCTL_LPE; 3378 else 3379 rctl &= ~E1000_RCTL_LPE; 3380 3381 /* Strip the CRC */ 3382 if (!em_disable_crc_stripping) 3383 rctl |= E1000_RCTL_SECRC; 3384 3385 if (hw->mac.type >= e1000_82540) { 3386 E1000_WRITE_REG(hw, E1000_RADV, 3387 sc->rx_abs_int_delay.value); 3388 3389 /* 3390 * Set the interrupt throttling rate. Value is calculated 3391 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3392 */ 3393 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3394 } 3395 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3396 3397 if (hw->mac.type >= em_mac_min) { 3398 uint32_t rfctl; 3399 /* Use extended rx descriptor formats */ 3400 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3401 rfctl |= E1000_RFCTL_EXTEN; 3402 3403 /* 3404 * When using MSI-X interrupts we need to throttle 3405 * using the EITR register (82574 only) 3406 */ 3407 if (hw->mac.type == e1000_82574) { 3408 for (int i = 0; i < 4; i++) 3409 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3410 DEFAULT_ITR); 3411 /* Disable accelerated acknowledge */ 3412 rfctl |= E1000_RFCTL_ACK_DIS; 3413 } 3414 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3415 } 3416 3417 /* Set up L3 and L4 csum Rx descriptor offloads */ 3418 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3419 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3420 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3421 if (hw->mac.type > e1000_82575) 3422 rxcsum |= E1000_RXCSUM_CRCOFL; 3423 else if (hw->mac.type < em_mac_min && 3424 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3425 rxcsum |= E1000_RXCSUM_IPV6OFL; 3426 } else { 3427 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3428 if (hw->mac.type > e1000_82575) 3429 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3430 else if (hw->mac.type < em_mac_min) 3431 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3432 } 3433 3434 if (sc->rx_num_queues > 1) { 3435 /* RSS hash needed in the Rx descriptor */ 3436 rxcsum |= E1000_RXCSUM_PCSD; 3437 3438 if (hw->mac.type >= igb_mac_min) 3439 igb_initialize_rss_mapping(sc); 3440 else 3441 em_initialize_rss_mapping(sc); 3442 } 3443 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3444 3445 /* 3446 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3447 * long latencies are observed, like Lenovo X60. This 3448 * change eliminates the problem, but since having positive 3449 * values in RDTR is a known source of problems on other 3450 * platforms another solution is being sought. 3451 */ 3452 if (hw->mac.type == e1000_82573) 3453 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3454 3455 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3456 struct rx_ring *rxr = &que->rxr; 3457 /* Setup the Base and Length of the Rx Descriptor Ring */ 3458 u64 bus_addr = rxr->rx_paddr; 3459 #if 0 3460 u32 rdt = sc->rx_num_queues -1; /* default */ 3461 #endif 3462 3463 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3464 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3465 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3466 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3467 /* Setup the Head and Tail Descriptor Pointers */ 3468 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3469 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3470 } 3471 3472 /* 3473 * Set PTHRESH for improved jumbo performance 3474 * According to 10.2.5.11 of Intel 82574 Datasheet, 3475 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3476 * Only write to RXDCTL(1) if there is a need for different 3477 * settings. 3478 */ 3479 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3480 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3481 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3482 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3483 } else if (hw->mac.type == e1000_82574) { 3484 for (int i = 0; i < sc->rx_num_queues; i++) { 3485 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3486 rxdctl |= 0x20; /* PTHRESH */ 3487 rxdctl |= 4 << 8; /* HTHRESH */ 3488 rxdctl |= 4 << 16;/* WTHRESH */ 3489 rxdctl |= 1 << 24; /* Switch to granularity */ 3490 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3491 } 3492 } else if (hw->mac.type >= igb_mac_min) { 3493 u32 psize, srrctl = 0; 3494 3495 if (if_getmtu(ifp) > ETHERMTU) { 3496 psize = scctx->isc_max_frame_size; 3497 /* are we on a vlan? */ 3498 if (if_vlantrunkinuse(ifp)) 3499 psize += VLAN_TAG_SIZE; 3500 3501 if (sc->vf_ifp) 3502 e1000_rlpml_set_vf(hw, psize); 3503 else 3504 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3505 } 3506 3507 /* Set maximum packet buffer len */ 3508 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3509 E1000_SRRCTL_BSIZEPKT_SHIFT; 3510 3511 /* 3512 * If TX flow control is disabled and there's >1 queue defined, 3513 * enable DROP. 3514 * 3515 * This drops frames rather than hanging the RX MAC for all queues. 3516 */ 3517 if ((sc->rx_num_queues > 1) && 3518 (sc->fc == e1000_fc_none || 3519 sc->fc == e1000_fc_rx_pause)) { 3520 srrctl |= E1000_SRRCTL_DROP_EN; 3521 } 3522 /* Setup the Base and Length of the Rx Descriptor Rings */ 3523 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3524 struct rx_ring *rxr = &que->rxr; 3525 u64 bus_addr = rxr->rx_paddr; 3526 u32 rxdctl; 3527 3528 #ifdef notyet 3529 /* Configure for header split? -- ignore for now */ 3530 rxr->hdr_split = igb_header_split; 3531 #else 3532 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3533 #endif 3534 3535 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3536 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3537 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3538 (uint32_t)(bus_addr >> 32)); 3539 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3540 (uint32_t)bus_addr); 3541 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3542 /* Enable this Queue */ 3543 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3544 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3545 rxdctl &= 0xFFF00000; 3546 rxdctl |= IGB_RX_PTHRESH; 3547 rxdctl |= IGB_RX_HTHRESH << 8; 3548 rxdctl |= IGB_RX_WTHRESH << 16; 3549 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3550 } 3551 } else if (hw->mac.type >= e1000_pch2lan) { 3552 if (if_getmtu(ifp) > ETHERMTU) 3553 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3554 else 3555 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3556 } 3557 3558 /* Make sure VLAN Filters are off */ 3559 rctl &= ~E1000_RCTL_VFE; 3560 3561 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3562 if (hw->mac.type < igb_mac_min) { 3563 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3564 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3565 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3566 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3567 else if (sc->rx_mbuf_sz > 8192) 3568 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3569 else { 3570 rctl |= E1000_RCTL_SZ_2048; 3571 rctl &= ~E1000_RCTL_BSEX; 3572 } 3573 } else 3574 rctl |= E1000_RCTL_SZ_2048; 3575 3576 /* 3577 * rctl bits 11:10 are as follows 3578 * lem: reserved 3579 * em: DTYPE 3580 * igb: reserved 3581 * and should be 00 on all of the above 3582 */ 3583 rctl &= ~0x00000C00; 3584 3585 /* Write out the settings */ 3586 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3587 3588 return; 3589 } 3590 3591 static void 3592 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3593 { 3594 struct e1000_softc *sc = iflib_get_softc(ctx); 3595 u32 index, bit; 3596 3597 index = (vtag >> 5) & 0x7F; 3598 bit = vtag & 0x1F; 3599 sc->shadow_vfta[index] |= (1 << bit); 3600 ++sc->num_vlans; 3601 em_if_vlan_filter_write(sc); 3602 } 3603 3604 static void 3605 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3606 { 3607 struct e1000_softc *sc = iflib_get_softc(ctx); 3608 u32 index, bit; 3609 3610 index = (vtag >> 5) & 0x7F; 3611 bit = vtag & 0x1F; 3612 sc->shadow_vfta[index] &= ~(1 << bit); 3613 --sc->num_vlans; 3614 em_if_vlan_filter_write(sc); 3615 } 3616 3617 static bool 3618 em_if_vlan_filter_capable(if_ctx_t ctx) 3619 { 3620 if_t ifp = iflib_get_ifp(ctx); 3621 3622 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3623 !em_disable_crc_stripping) 3624 return (true); 3625 3626 return (false); 3627 } 3628 3629 static bool 3630 em_if_vlan_filter_used(if_ctx_t ctx) 3631 { 3632 struct e1000_softc *sc = iflib_get_softc(ctx); 3633 3634 if (!em_if_vlan_filter_capable(ctx)) 3635 return (false); 3636 3637 for (int i = 0; i < EM_VFTA_SIZE; i++) 3638 if (sc->shadow_vfta[i] != 0) 3639 return (true); 3640 3641 return (false); 3642 } 3643 3644 static void 3645 em_if_vlan_filter_enable(struct e1000_softc *sc) 3646 { 3647 struct e1000_hw *hw = &sc->hw; 3648 u32 reg; 3649 3650 reg = E1000_READ_REG(hw, E1000_RCTL); 3651 reg &= ~E1000_RCTL_CFIEN; 3652 reg |= E1000_RCTL_VFE; 3653 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3654 } 3655 3656 static void 3657 em_if_vlan_filter_disable(struct e1000_softc *sc) 3658 { 3659 struct e1000_hw *hw = &sc->hw; 3660 u32 reg; 3661 3662 reg = E1000_READ_REG(hw, E1000_RCTL); 3663 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3664 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3665 } 3666 3667 static void 3668 em_if_vlan_filter_write(struct e1000_softc *sc) 3669 { 3670 struct e1000_hw *hw = &sc->hw; 3671 3672 if (sc->vf_ifp) 3673 return; 3674 3675 /* Disable interrupts for lem-class devices during the filter change */ 3676 if (hw->mac.type < em_mac_min) 3677 em_if_intr_disable(sc->ctx); 3678 3679 for (int i = 0; i < EM_VFTA_SIZE; i++) 3680 if (sc->shadow_vfta[i] != 0) { 3681 /* XXXKB: incomplete VF support, we return early above */ 3682 if (sc->vf_ifp) 3683 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3684 else 3685 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3686 } 3687 3688 /* Re-enable interrupts for lem-class devices */ 3689 if (hw->mac.type < em_mac_min) 3690 em_if_intr_enable(sc->ctx); 3691 } 3692 3693 static void 3694 em_setup_vlan_hw_support(if_ctx_t ctx) 3695 { 3696 struct e1000_softc *sc = iflib_get_softc(ctx); 3697 struct e1000_hw *hw = &sc->hw; 3698 if_t ifp = iflib_get_ifp(ctx); 3699 u32 reg; 3700 3701 /* XXXKB: Return early if we are a VF until VF decap and filter management 3702 * is ready and tested. 3703 */ 3704 if (sc->vf_ifp) 3705 return; 3706 3707 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3708 !em_disable_crc_stripping) { 3709 reg = E1000_READ_REG(hw, E1000_CTRL); 3710 reg |= E1000_CTRL_VME; 3711 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3712 } else { 3713 reg = E1000_READ_REG(hw, E1000_CTRL); 3714 reg &= ~E1000_CTRL_VME; 3715 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3716 } 3717 3718 /* If we aren't doing HW filtering, we're done */ 3719 if (!em_if_vlan_filter_capable(ctx)) { 3720 em_if_vlan_filter_disable(sc); 3721 return; 3722 } 3723 3724 /* 3725 * A soft reset zero's out the VFTA, so 3726 * we need to repopulate it now. 3727 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3728 * traffic through. This will write the entire table. 3729 */ 3730 em_if_vlan_register(ctx, 0); 3731 3732 /* Enable the Filter Table */ 3733 em_if_vlan_filter_enable(sc); 3734 } 3735 3736 static void 3737 em_if_intr_enable(if_ctx_t ctx) 3738 { 3739 struct e1000_softc *sc = iflib_get_softc(ctx); 3740 struct e1000_hw *hw = &sc->hw; 3741 u32 ims_mask = IMS_ENABLE_MASK; 3742 3743 if (sc->intr_type == IFLIB_INTR_MSIX) { 3744 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3745 ims_mask |= sc->ims; 3746 } 3747 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3748 E1000_WRITE_FLUSH(hw); 3749 } 3750 3751 static void 3752 em_if_intr_disable(if_ctx_t ctx) 3753 { 3754 struct e1000_softc *sc = iflib_get_softc(ctx); 3755 struct e1000_hw *hw = &sc->hw; 3756 3757 if (sc->intr_type == IFLIB_INTR_MSIX) 3758 E1000_WRITE_REG(hw, EM_EIAC, 0); 3759 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3760 E1000_WRITE_FLUSH(hw); 3761 } 3762 3763 static void 3764 igb_if_intr_enable(if_ctx_t ctx) 3765 { 3766 struct e1000_softc *sc = iflib_get_softc(ctx); 3767 struct e1000_hw *hw = &sc->hw; 3768 u32 mask; 3769 3770 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3771 mask = (sc->que_mask | sc->link_mask); 3772 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3773 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3774 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3775 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3776 } else 3777 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3778 E1000_WRITE_FLUSH(hw); 3779 } 3780 3781 static void 3782 igb_if_intr_disable(if_ctx_t ctx) 3783 { 3784 struct e1000_softc *sc = iflib_get_softc(ctx); 3785 struct e1000_hw *hw = &sc->hw; 3786 3787 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3788 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3789 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3790 } 3791 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3792 E1000_WRITE_FLUSH(hw); 3793 } 3794 3795 /* 3796 * Bit of a misnomer, what this really means is 3797 * to enable OS management of the system... aka 3798 * to disable special hardware management features 3799 */ 3800 static void 3801 em_init_manageability(struct e1000_softc *sc) 3802 { 3803 /* A shared code workaround */ 3804 #define E1000_82542_MANC2H E1000_MANC2H 3805 if (sc->has_manage) { 3806 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3807 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3808 3809 /* disable hardware interception of ARP */ 3810 manc &= ~(E1000_MANC_ARP_EN); 3811 3812 /* enable receiving management packets to the host */ 3813 manc |= E1000_MANC_EN_MNG2HOST; 3814 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3815 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3816 manc2h |= E1000_MNG2HOST_PORT_623; 3817 manc2h |= E1000_MNG2HOST_PORT_664; 3818 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3819 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3820 } 3821 } 3822 3823 /* 3824 * Give control back to hardware management 3825 * controller if there is one. 3826 */ 3827 static void 3828 em_release_manageability(struct e1000_softc *sc) 3829 { 3830 if (sc->has_manage) { 3831 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3832 3833 /* re-enable hardware interception of ARP */ 3834 manc |= E1000_MANC_ARP_EN; 3835 manc &= ~E1000_MANC_EN_MNG2HOST; 3836 3837 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3838 } 3839 } 3840 3841 /* 3842 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3843 * For ASF and Pass Through versions of f/w this means 3844 * that the driver is loaded. For AMT version type f/w 3845 * this means that the network i/f is open. 3846 */ 3847 static void 3848 em_get_hw_control(struct e1000_softc *sc) 3849 { 3850 u32 ctrl_ext, swsm; 3851 3852 if (sc->vf_ifp) 3853 return; 3854 3855 if (sc->hw.mac.type == e1000_82573) { 3856 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3857 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3858 swsm | E1000_SWSM_DRV_LOAD); 3859 return; 3860 } 3861 /* else */ 3862 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3863 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3864 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3865 } 3866 3867 /* 3868 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3869 * For ASF and Pass Through versions of f/w this means that 3870 * the driver is no longer loaded. For AMT versions of the 3871 * f/w this means that the network i/f is closed. 3872 */ 3873 static void 3874 em_release_hw_control(struct e1000_softc *sc) 3875 { 3876 u32 ctrl_ext, swsm; 3877 3878 if (!sc->has_manage) 3879 return; 3880 3881 if (sc->hw.mac.type == e1000_82573) { 3882 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3883 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3884 swsm & ~E1000_SWSM_DRV_LOAD); 3885 return; 3886 } 3887 /* else */ 3888 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3889 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3890 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3891 return; 3892 } 3893 3894 static int 3895 em_is_valid_ether_addr(u8 *addr) 3896 { 3897 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3898 3899 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3900 return (false); 3901 } 3902 3903 return (true); 3904 } 3905 3906 static bool 3907 em_automask_tso(if_ctx_t ctx) 3908 { 3909 struct e1000_softc *sc = iflib_get_softc(ctx); 3910 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 3911 if_t ifp = iflib_get_ifp(ctx); 3912 3913 if (!em_unsupported_tso && sc->link_speed && 3914 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 3915 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 3916 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 3917 scctx->isc_capenable &= ~IFCAP_TSO; 3918 if_setcapenablebit(ifp, 0, IFCAP_TSO); 3919 /* iflib_init_locked handles ifnet hwassistbits */ 3920 iflib_request_reset(ctx); 3921 return true; 3922 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 3923 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 3924 scctx->isc_capenable |= sc->tso_automasked; 3925 if_setcapenablebit(ifp, sc->tso_automasked, 0); 3926 sc->tso_automasked = 0; 3927 /* iflib_init_locked handles ifnet hwassistbits */ 3928 iflib_request_reset(ctx); 3929 return true; 3930 } 3931 3932 return false; 3933 } 3934 3935 /* 3936 ** Parse the interface capabilities with regard 3937 ** to both system management and wake-on-lan for 3938 ** later use. 3939 */ 3940 static void 3941 em_get_wakeup(if_ctx_t ctx) 3942 { 3943 struct e1000_softc *sc = iflib_get_softc(ctx); 3944 device_t dev = iflib_get_dev(ctx); 3945 u16 eeprom_data = 0, device_id, apme_mask; 3946 3947 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3948 apme_mask = EM_EEPROM_APME; 3949 3950 switch (sc->hw.mac.type) { 3951 case e1000_82542: 3952 case e1000_82543: 3953 break; 3954 case e1000_82544: 3955 e1000_read_nvm(&sc->hw, 3956 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3957 apme_mask = EM_82544_APME; 3958 break; 3959 case e1000_82546: 3960 case e1000_82546_rev_3: 3961 if (sc->hw.bus.func == 1) { 3962 e1000_read_nvm(&sc->hw, 3963 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3964 break; 3965 } else 3966 e1000_read_nvm(&sc->hw, 3967 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3968 break; 3969 case e1000_82573: 3970 case e1000_82583: 3971 sc->has_amt = true; 3972 /* FALLTHROUGH */ 3973 case e1000_82571: 3974 case e1000_82572: 3975 case e1000_80003es2lan: 3976 if (sc->hw.bus.func == 1) { 3977 e1000_read_nvm(&sc->hw, 3978 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3979 break; 3980 } else 3981 e1000_read_nvm(&sc->hw, 3982 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3983 break; 3984 case e1000_ich8lan: 3985 case e1000_ich9lan: 3986 case e1000_ich10lan: 3987 case e1000_pchlan: 3988 case e1000_pch2lan: 3989 case e1000_pch_lpt: 3990 case e1000_pch_spt: 3991 case e1000_82575: /* listing all igb devices */ 3992 case e1000_82576: 3993 case e1000_82580: 3994 case e1000_i350: 3995 case e1000_i354: 3996 case e1000_i210: 3997 case e1000_i211: 3998 case e1000_vfadapt: 3999 case e1000_vfadapt_i350: 4000 apme_mask = E1000_WUC_APME; 4001 sc->has_amt = true; 4002 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4003 break; 4004 default: 4005 e1000_read_nvm(&sc->hw, 4006 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4007 break; 4008 } 4009 if (eeprom_data & apme_mask) 4010 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4011 /* 4012 * We have the eeprom settings, now apply the special cases 4013 * where the eeprom may be wrong or the board won't support 4014 * wake on lan on a particular port 4015 */ 4016 device_id = pci_get_device(dev); 4017 switch (device_id) { 4018 case E1000_DEV_ID_82546GB_PCIE: 4019 sc->wol = 0; 4020 break; 4021 case E1000_DEV_ID_82546EB_FIBER: 4022 case E1000_DEV_ID_82546GB_FIBER: 4023 /* Wake events only supported on port A for dual fiber 4024 * regardless of eeprom setting */ 4025 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4026 E1000_STATUS_FUNC_1) 4027 sc->wol = 0; 4028 break; 4029 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4030 /* if quad port adapter, disable WoL on all but port A */ 4031 if (global_quad_port_a != 0) 4032 sc->wol = 0; 4033 /* Reset for multiple quad port adapters */ 4034 if (++global_quad_port_a == 4) 4035 global_quad_port_a = 0; 4036 break; 4037 case E1000_DEV_ID_82571EB_FIBER: 4038 /* Wake events only supported on port A for dual fiber 4039 * regardless of eeprom setting */ 4040 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4041 E1000_STATUS_FUNC_1) 4042 sc->wol = 0; 4043 break; 4044 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4045 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4046 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4047 /* if quad port adapter, disable WoL on all but port A */ 4048 if (global_quad_port_a != 0) 4049 sc->wol = 0; 4050 /* Reset for multiple quad port adapters */ 4051 if (++global_quad_port_a == 4) 4052 global_quad_port_a = 0; 4053 break; 4054 } 4055 return; 4056 } 4057 4058 4059 /* 4060 * Enable PCI Wake On Lan capability 4061 */ 4062 static void 4063 em_enable_wakeup(if_ctx_t ctx) 4064 { 4065 struct e1000_softc *sc = iflib_get_softc(ctx); 4066 device_t dev = iflib_get_dev(ctx); 4067 if_t ifp = iflib_get_ifp(ctx); 4068 int error = 0; 4069 u32 pmc, ctrl, ctrl_ext, rctl; 4070 u16 status; 4071 4072 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4073 return; 4074 4075 /* 4076 * Determine type of Wakeup: note that wol 4077 * is set with all bits on by default. 4078 */ 4079 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4080 sc->wol &= ~E1000_WUFC_MAG; 4081 4082 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4083 sc->wol &= ~E1000_WUFC_EX; 4084 4085 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4086 sc->wol &= ~E1000_WUFC_MC; 4087 else { 4088 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4089 rctl |= E1000_RCTL_MPE; 4090 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4091 } 4092 4093 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4094 goto pme; 4095 4096 /* Advertise the wakeup capability */ 4097 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4098 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4099 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4100 4101 /* Keep the laser running on Fiber adapters */ 4102 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4103 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4104 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4105 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4106 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4107 } 4108 4109 if ((sc->hw.mac.type == e1000_ich8lan) || 4110 (sc->hw.mac.type == e1000_pchlan) || 4111 (sc->hw.mac.type == e1000_ich9lan) || 4112 (sc->hw.mac.type == e1000_ich10lan)) 4113 e1000_suspend_workarounds_ich8lan(&sc->hw); 4114 4115 if ( sc->hw.mac.type >= e1000_pchlan) { 4116 error = em_enable_phy_wakeup(sc); 4117 if (error) 4118 goto pme; 4119 } else { 4120 /* Enable wakeup by the MAC */ 4121 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4122 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4123 } 4124 4125 if (sc->hw.phy.type == e1000_phy_igp_3) 4126 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4127 4128 pme: 4129 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4130 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4131 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4132 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4133 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4134 4135 return; 4136 } 4137 4138 /* 4139 * WOL in the newer chipset interfaces (pchlan) 4140 * require thing to be copied into the phy 4141 */ 4142 static int 4143 em_enable_phy_wakeup(struct e1000_softc *sc) 4144 { 4145 struct e1000_hw *hw = &sc->hw; 4146 u32 mreg, ret = 0; 4147 u16 preg; 4148 4149 /* copy MAC RARs to PHY RARs */ 4150 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4151 4152 /* copy MAC MTA to PHY MTA */ 4153 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4154 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4155 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4156 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4157 (u16)((mreg >> 16) & 0xFFFF)); 4158 } 4159 4160 /* configure PHY Rx Control register */ 4161 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4162 mreg = E1000_READ_REG(hw, E1000_RCTL); 4163 if (mreg & E1000_RCTL_UPE) 4164 preg |= BM_RCTL_UPE; 4165 if (mreg & E1000_RCTL_MPE) 4166 preg |= BM_RCTL_MPE; 4167 preg &= ~(BM_RCTL_MO_MASK); 4168 if (mreg & E1000_RCTL_MO_3) 4169 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4170 << BM_RCTL_MO_SHIFT); 4171 if (mreg & E1000_RCTL_BAM) 4172 preg |= BM_RCTL_BAM; 4173 if (mreg & E1000_RCTL_PMCF) 4174 preg |= BM_RCTL_PMCF; 4175 mreg = E1000_READ_REG(hw, E1000_CTRL); 4176 if (mreg & E1000_CTRL_RFCE) 4177 preg |= BM_RCTL_RFCE; 4178 e1000_write_phy_reg(hw, BM_RCTL, preg); 4179 4180 /* enable PHY wakeup in MAC register */ 4181 E1000_WRITE_REG(hw, E1000_WUC, 4182 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4183 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4184 4185 /* configure and enable PHY wakeup in PHY registers */ 4186 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4187 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4188 4189 /* activate PHY wakeup */ 4190 ret = hw->phy.ops.acquire(hw); 4191 if (ret) { 4192 printf("Could not acquire PHY\n"); 4193 return ret; 4194 } 4195 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4196 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4197 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4198 if (ret) { 4199 printf("Could not read PHY page 769\n"); 4200 goto out; 4201 } 4202 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4203 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4204 if (ret) 4205 printf("Could not set PHY Host Wakeup bit\n"); 4206 out: 4207 hw->phy.ops.release(hw); 4208 4209 return ret; 4210 } 4211 4212 static void 4213 em_if_led_func(if_ctx_t ctx, int onoff) 4214 { 4215 struct e1000_softc *sc = iflib_get_softc(ctx); 4216 4217 if (onoff) { 4218 e1000_setup_led(&sc->hw); 4219 e1000_led_on(&sc->hw); 4220 } else { 4221 e1000_led_off(&sc->hw); 4222 e1000_cleanup_led(&sc->hw); 4223 } 4224 } 4225 4226 /* 4227 * Disable the L0S and L1 LINK states 4228 */ 4229 static void 4230 em_disable_aspm(struct e1000_softc *sc) 4231 { 4232 int base, reg; 4233 u16 link_cap,link_ctrl; 4234 device_t dev = sc->dev; 4235 4236 switch (sc->hw.mac.type) { 4237 case e1000_82573: 4238 case e1000_82574: 4239 case e1000_82583: 4240 break; 4241 default: 4242 return; 4243 } 4244 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4245 return; 4246 reg = base + PCIER_LINK_CAP; 4247 link_cap = pci_read_config(dev, reg, 2); 4248 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4249 return; 4250 reg = base + PCIER_LINK_CTL; 4251 link_ctrl = pci_read_config(dev, reg, 2); 4252 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4253 pci_write_config(dev, reg, link_ctrl, 2); 4254 return; 4255 } 4256 4257 /********************************************************************** 4258 * 4259 * Update the board statistics counters. 4260 * 4261 **********************************************************************/ 4262 static void 4263 em_update_stats_counters(struct e1000_softc *sc) 4264 { 4265 u64 prev_xoffrxc = sc->stats.xoffrxc; 4266 4267 if(sc->hw.phy.media_type == e1000_media_type_copper || 4268 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4269 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4270 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4271 } 4272 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4273 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4274 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4275 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4276 4277 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4278 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4279 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4280 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4281 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4282 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4283 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4284 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4285 /* 4286 ** For watchdog management we need to know if we have been 4287 ** paused during the last interval, so capture that here. 4288 */ 4289 if (sc->stats.xoffrxc != prev_xoffrxc) 4290 sc->shared->isc_pause_frames = 1; 4291 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4292 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4293 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4294 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4295 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4296 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4297 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4298 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4299 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4300 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4301 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4302 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4303 4304 /* For the 64-bit byte counters the low dword must be read first. */ 4305 /* Both registers clear on the read of the high dword */ 4306 4307 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4308 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4309 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4310 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4311 4312 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4313 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4314 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4315 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4316 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4317 4318 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4319 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4320 4321 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4322 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4323 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4324 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4325 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4326 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4327 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4328 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4329 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4330 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4331 4332 /* Interrupt Counts */ 4333 4334 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4335 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4336 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4337 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4338 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4339 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4340 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4341 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4342 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4343 4344 if (sc->hw.mac.type >= e1000_82543) { 4345 sc->stats.algnerrc += 4346 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4347 sc->stats.rxerrc += 4348 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4349 sc->stats.tncrs += 4350 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4351 sc->stats.cexterr += 4352 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4353 sc->stats.tsctc += 4354 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4355 sc->stats.tsctfc += 4356 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4357 } 4358 } 4359 4360 static uint64_t 4361 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4362 { 4363 struct e1000_softc *sc = iflib_get_softc(ctx); 4364 if_t ifp = iflib_get_ifp(ctx); 4365 4366 switch (cnt) { 4367 case IFCOUNTER_COLLISIONS: 4368 return (sc->stats.colc); 4369 case IFCOUNTER_IERRORS: 4370 return (sc->dropped_pkts + sc->stats.rxerrc + 4371 sc->stats.crcerrs + sc->stats.algnerrc + 4372 sc->stats.ruc + sc->stats.roc + 4373 sc->stats.mpc + sc->stats.cexterr); 4374 case IFCOUNTER_OERRORS: 4375 return (sc->stats.ecol + sc->stats.latecol + 4376 sc->watchdog_events); 4377 default: 4378 return (if_get_counter_default(ifp, cnt)); 4379 } 4380 } 4381 4382 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4383 * @ctx: iflib context 4384 * @event: event code to check 4385 * 4386 * Defaults to returning false for unknown events. 4387 * 4388 * @returns true if iflib needs to reinit the interface 4389 */ 4390 static bool 4391 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4392 { 4393 switch (event) { 4394 case IFLIB_RESTART_VLAN_CONFIG: 4395 default: 4396 return (false); 4397 } 4398 } 4399 4400 /* Export a single 32-bit register via a read-only sysctl. */ 4401 static int 4402 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4403 { 4404 struct e1000_softc *sc; 4405 u_int val; 4406 4407 sc = oidp->oid_arg1; 4408 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4409 return (sysctl_handle_int(oidp, &val, 0, req)); 4410 } 4411 4412 /* 4413 * Add sysctl variables, one per statistic, to the system. 4414 */ 4415 static void 4416 em_add_hw_stats(struct e1000_softc *sc) 4417 { 4418 device_t dev = iflib_get_dev(sc->ctx); 4419 struct em_tx_queue *tx_que = sc->tx_queues; 4420 struct em_rx_queue *rx_que = sc->rx_queues; 4421 4422 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4423 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4424 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4425 struct e1000_hw_stats *stats = &sc->stats; 4426 4427 struct sysctl_oid *stat_node, *queue_node, *int_node; 4428 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4429 4430 #define QUEUE_NAME_LEN 32 4431 char namebuf[QUEUE_NAME_LEN]; 4432 4433 /* Driver Statistics */ 4434 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4435 CTLFLAG_RD, &sc->dropped_pkts, 4436 "Driver dropped packets"); 4437 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4438 CTLFLAG_RD, &sc->link_irq, 4439 "Link MSI-X IRQ Handled"); 4440 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4441 CTLFLAG_RD, &sc->rx_overruns, 4442 "RX overruns"); 4443 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4444 CTLFLAG_RD, &sc->watchdog_events, 4445 "Watchdog timeouts"); 4446 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4447 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4448 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4449 "Device Control Register"); 4450 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4451 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4452 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4453 "Receiver Control Register"); 4454 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4455 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4456 "Flow Control High Watermark"); 4457 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4458 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4459 "Flow Control Low Watermark"); 4460 4461 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4462 struct tx_ring *txr = &tx_que->txr; 4463 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4464 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4465 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4466 queue_list = SYSCTL_CHILDREN(queue_node); 4467 4468 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4469 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4470 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4471 "Transmit Descriptor Head"); 4472 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4473 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4474 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4475 "Transmit Descriptor Tail"); 4476 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4477 CTLFLAG_RD, &txr->tx_irq, 4478 "Queue MSI-X Transmit Interrupts"); 4479 } 4480 4481 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4482 struct rx_ring *rxr = &rx_que->rxr; 4483 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4484 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4485 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4486 queue_list = SYSCTL_CHILDREN(queue_node); 4487 4488 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4489 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4490 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4491 "Receive Descriptor Head"); 4492 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4493 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4494 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4495 "Receive Descriptor Tail"); 4496 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4497 CTLFLAG_RD, &rxr->rx_irq, 4498 "Queue MSI-X Receive Interrupts"); 4499 } 4500 4501 /* MAC stats get their own sub node */ 4502 4503 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4504 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4505 stat_list = SYSCTL_CHILDREN(stat_node); 4506 4507 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4508 CTLFLAG_RD, &stats->ecol, 4509 "Excessive collisions"); 4510 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4511 CTLFLAG_RD, &stats->scc, 4512 "Single collisions"); 4513 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4514 CTLFLAG_RD, &stats->mcc, 4515 "Multiple collisions"); 4516 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4517 CTLFLAG_RD, &stats->latecol, 4518 "Late collisions"); 4519 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4520 CTLFLAG_RD, &stats->colc, 4521 "Collision Count"); 4522 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4523 CTLFLAG_RD, &sc->stats.symerrs, 4524 "Symbol Errors"); 4525 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4526 CTLFLAG_RD, &sc->stats.sec, 4527 "Sequence Errors"); 4528 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4529 CTLFLAG_RD, &sc->stats.dc, 4530 "Defer Count"); 4531 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4532 CTLFLAG_RD, &sc->stats.mpc, 4533 "Missed Packets"); 4534 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4535 CTLFLAG_RD, &sc->stats.rnbc, 4536 "Receive No Buffers"); 4537 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4538 CTLFLAG_RD, &sc->stats.ruc, 4539 "Receive Undersize"); 4540 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4541 CTLFLAG_RD, &sc->stats.rfc, 4542 "Fragmented Packets Received "); 4543 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4544 CTLFLAG_RD, &sc->stats.roc, 4545 "Oversized Packets Received"); 4546 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4547 CTLFLAG_RD, &sc->stats.rjc, 4548 "Recevied Jabber"); 4549 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4550 CTLFLAG_RD, &sc->stats.rxerrc, 4551 "Receive Errors"); 4552 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4553 CTLFLAG_RD, &sc->stats.crcerrs, 4554 "CRC errors"); 4555 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4556 CTLFLAG_RD, &sc->stats.algnerrc, 4557 "Alignment Errors"); 4558 /* On 82575 these are collision counts */ 4559 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4560 CTLFLAG_RD, &sc->stats.cexterr, 4561 "Collision/Carrier extension errors"); 4562 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4563 CTLFLAG_RD, &sc->stats.xonrxc, 4564 "XON Received"); 4565 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4566 CTLFLAG_RD, &sc->stats.xontxc, 4567 "XON Transmitted"); 4568 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4569 CTLFLAG_RD, &sc->stats.xoffrxc, 4570 "XOFF Received"); 4571 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4572 CTLFLAG_RD, &sc->stats.xofftxc, 4573 "XOFF Transmitted"); 4574 4575 /* Packet Reception Stats */ 4576 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4577 CTLFLAG_RD, &sc->stats.tpr, 4578 "Total Packets Received "); 4579 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4580 CTLFLAG_RD, &sc->stats.gprc, 4581 "Good Packets Received"); 4582 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4583 CTLFLAG_RD, &sc->stats.bprc, 4584 "Broadcast Packets Received"); 4585 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4586 CTLFLAG_RD, &sc->stats.mprc, 4587 "Multicast Packets Received"); 4588 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4589 CTLFLAG_RD, &sc->stats.prc64, 4590 "64 byte frames received "); 4591 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4592 CTLFLAG_RD, &sc->stats.prc127, 4593 "65-127 byte frames received"); 4594 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4595 CTLFLAG_RD, &sc->stats.prc255, 4596 "128-255 byte frames received"); 4597 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4598 CTLFLAG_RD, &sc->stats.prc511, 4599 "256-511 byte frames received"); 4600 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4601 CTLFLAG_RD, &sc->stats.prc1023, 4602 "512-1023 byte frames received"); 4603 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4604 CTLFLAG_RD, &sc->stats.prc1522, 4605 "1023-1522 byte frames received"); 4606 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4607 CTLFLAG_RD, &sc->stats.gorc, 4608 "Good Octets Received"); 4609 4610 /* Packet Transmission Stats */ 4611 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4612 CTLFLAG_RD, &sc->stats.gotc, 4613 "Good Octets Transmitted"); 4614 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4615 CTLFLAG_RD, &sc->stats.tpt, 4616 "Total Packets Transmitted"); 4617 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4618 CTLFLAG_RD, &sc->stats.gptc, 4619 "Good Packets Transmitted"); 4620 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4621 CTLFLAG_RD, &sc->stats.bptc, 4622 "Broadcast Packets Transmitted"); 4623 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4624 CTLFLAG_RD, &sc->stats.mptc, 4625 "Multicast Packets Transmitted"); 4626 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4627 CTLFLAG_RD, &sc->stats.ptc64, 4628 "64 byte frames transmitted "); 4629 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4630 CTLFLAG_RD, &sc->stats.ptc127, 4631 "65-127 byte frames transmitted"); 4632 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4633 CTLFLAG_RD, &sc->stats.ptc255, 4634 "128-255 byte frames transmitted"); 4635 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4636 CTLFLAG_RD, &sc->stats.ptc511, 4637 "256-511 byte frames transmitted"); 4638 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4639 CTLFLAG_RD, &sc->stats.ptc1023, 4640 "512-1023 byte frames transmitted"); 4641 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4642 CTLFLAG_RD, &sc->stats.ptc1522, 4643 "1024-1522 byte frames transmitted"); 4644 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4645 CTLFLAG_RD, &sc->stats.tsctc, 4646 "TSO Contexts Transmitted"); 4647 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4648 CTLFLAG_RD, &sc->stats.tsctfc, 4649 "TSO Contexts Failed"); 4650 4651 4652 /* Interrupt Stats */ 4653 4654 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4655 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4656 int_list = SYSCTL_CHILDREN(int_node); 4657 4658 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4659 CTLFLAG_RD, &sc->stats.iac, 4660 "Interrupt Assertion Count"); 4661 4662 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4663 CTLFLAG_RD, &sc->stats.icrxptc, 4664 "Interrupt Cause Rx Pkt Timer Expire Count"); 4665 4666 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4667 CTLFLAG_RD, &sc->stats.icrxatc, 4668 "Interrupt Cause Rx Abs Timer Expire Count"); 4669 4670 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4671 CTLFLAG_RD, &sc->stats.ictxptc, 4672 "Interrupt Cause Tx Pkt Timer Expire Count"); 4673 4674 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4675 CTLFLAG_RD, &sc->stats.ictxatc, 4676 "Interrupt Cause Tx Abs Timer Expire Count"); 4677 4678 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4679 CTLFLAG_RD, &sc->stats.ictxqec, 4680 "Interrupt Cause Tx Queue Empty Count"); 4681 4682 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4683 CTLFLAG_RD, &sc->stats.ictxqmtc, 4684 "Interrupt Cause Tx Queue Min Thresh Count"); 4685 4686 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4687 CTLFLAG_RD, &sc->stats.icrxdmtc, 4688 "Interrupt Cause Rx Desc Min Thresh Count"); 4689 4690 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4691 CTLFLAG_RD, &sc->stats.icrxoc, 4692 "Interrupt Cause Receiver Overrun Count"); 4693 } 4694 4695 static void 4696 em_fw_version_locked(if_ctx_t ctx) 4697 { 4698 struct e1000_softc *sc = iflib_get_softc(ctx); 4699 struct e1000_hw *hw = &sc->hw; 4700 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4701 uint16_t eep = 0; 4702 4703 /* 4704 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4705 * NVM locking model, so we do it in em_if_attach_pre() and store the 4706 * info in the softc 4707 */ 4708 ASSERT_CTX_LOCK_HELD(hw); 4709 4710 *fw_ver = (struct e1000_fw_version){0}; 4711 4712 if (hw->mac.type >= igb_mac_min) { 4713 /* 4714 * Use the Shared Code for igb(4) 4715 */ 4716 e1000_get_fw_version(hw, fw_ver); 4717 } else { 4718 /* 4719 * Otherwise, EEPROM version should be present on (almost?) all 4720 * devices here 4721 */ 4722 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4723 INIT_DEBUGOUT("can't get EEPROM version"); 4724 return; 4725 } 4726 4727 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4728 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4729 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4730 } 4731 } 4732 4733 static void 4734 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4735 { 4736 const char *space = ""; 4737 4738 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4739 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4740 fw_ver->eep_minor, fw_ver->eep_build); 4741 space = " "; 4742 } 4743 4744 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4745 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4746 space, fw_ver->invm_major, fw_ver->invm_minor, 4747 fw_ver->invm_img_type); 4748 space = " "; 4749 } 4750 4751 if (fw_ver->or_valid) { 4752 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4753 space, fw_ver->or_major, fw_ver->or_build, 4754 fw_ver->or_patch); 4755 space = " "; 4756 } 4757 4758 if (fw_ver->etrack_id) 4759 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4760 } 4761 4762 static void 4763 em_print_fw_version(struct e1000_softc *sc ) 4764 { 4765 device_t dev = sc->dev; 4766 struct sbuf *buf; 4767 int error = 0; 4768 4769 buf = sbuf_new_auto(); 4770 if (!buf) { 4771 device_printf(dev, "Could not allocate sbuf for output.\n"); 4772 return; 4773 } 4774 4775 em_sbuf_fw_version(&sc->fw_ver, buf); 4776 4777 error = sbuf_finish(buf); 4778 if (error) 4779 device_printf(dev, "Error finishing sbuf: %d\n", error); 4780 else if (sbuf_len(buf)) 4781 device_printf(dev, "%s\n", sbuf_data(buf)); 4782 4783 sbuf_delete(buf); 4784 } 4785 4786 static int 4787 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4788 { 4789 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4790 device_t dev = sc->dev; 4791 struct sbuf *buf; 4792 int error = 0; 4793 4794 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4795 if (!buf) { 4796 device_printf(dev, "Could not allocate sbuf for output.\n"); 4797 return (ENOMEM); 4798 } 4799 4800 em_sbuf_fw_version(&sc->fw_ver, buf); 4801 4802 error = sbuf_finish(buf); 4803 if (error) 4804 device_printf(dev, "Error finishing sbuf: %d\n", error); 4805 4806 sbuf_delete(buf); 4807 4808 return (0); 4809 } 4810 4811 /********************************************************************** 4812 * 4813 * This routine provides a way to dump out the adapter eeprom, 4814 * often a useful debug/service tool. This only dumps the first 4815 * 32 words, stuff that matters is in that extent. 4816 * 4817 **********************************************************************/ 4818 static int 4819 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4820 { 4821 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4822 int error; 4823 int result; 4824 4825 result = -1; 4826 error = sysctl_handle_int(oidp, &result, 0, req); 4827 4828 if (error || !req->newptr) 4829 return (error); 4830 4831 /* 4832 * This value will cause a hex dump of the 4833 * first 32 16-bit words of the EEPROM to 4834 * the screen. 4835 */ 4836 if (result == 1) 4837 em_print_nvm_info(sc); 4838 4839 return (error); 4840 } 4841 4842 static void 4843 em_print_nvm_info(struct e1000_softc *sc) 4844 { 4845 struct e1000_hw *hw = &sc->hw; 4846 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4847 u16 eeprom_data; 4848 int i, j, row = 0; 4849 4850 /* Its a bit crude, but it gets the job done */ 4851 printf("\nInterface EEPROM Dump:\n"); 4852 printf("Offset\n0x0000 "); 4853 4854 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4855 sx_xlock(iflib_ctx_lock); 4856 ASSERT_CTX_LOCK_HELD(hw); 4857 for (i = 0, j = 0; i < 32; i++, j++) { 4858 if (j == 8) { /* Make the offset block */ 4859 j = 0; ++row; 4860 printf("\n0x00%x0 ",row); 4861 } 4862 e1000_read_nvm(hw, i, 1, &eeprom_data); 4863 printf("%04x ", eeprom_data); 4864 } 4865 sx_xunlock(iflib_ctx_lock); 4866 printf("\n"); 4867 } 4868 4869 static int 4870 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4871 { 4872 struct em_int_delay_info *info; 4873 struct e1000_softc *sc; 4874 u32 regval; 4875 int error, usecs, ticks; 4876 4877 info = (struct em_int_delay_info *) arg1; 4878 usecs = info->value; 4879 error = sysctl_handle_int(oidp, &usecs, 0, req); 4880 if (error != 0 || req->newptr == NULL) 4881 return (error); 4882 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4883 return (EINVAL); 4884 info->value = usecs; 4885 ticks = EM_USECS_TO_TICKS(usecs); 4886 if (info->offset == E1000_ITR) /* units are 256ns here */ 4887 ticks *= 4; 4888 4889 sc = info->sc; 4890 4891 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4892 regval = (regval & ~0xffff) | (ticks & 0xffff); 4893 /* Handle a few special cases. */ 4894 switch (info->offset) { 4895 case E1000_RDTR: 4896 break; 4897 case E1000_TIDV: 4898 if (ticks == 0) { 4899 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4900 /* Don't write 0 into the TIDV register. */ 4901 regval++; 4902 } else 4903 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4904 break; 4905 } 4906 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4907 return (0); 4908 } 4909 4910 static void 4911 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4912 const char *description, struct em_int_delay_info *info, 4913 int offset, int value) 4914 { 4915 info->sc = sc; 4916 info->offset = offset; 4917 info->value = value; 4918 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4919 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4920 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4921 info, 0, em_sysctl_int_delay, "I", description); 4922 } 4923 4924 /* 4925 * Set flow control using sysctl: 4926 * Flow control values: 4927 * 0 - off 4928 * 1 - rx pause 4929 * 2 - tx pause 4930 * 3 - full 4931 */ 4932 static int 4933 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4934 { 4935 int error; 4936 static int input = 3; /* default is full */ 4937 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4938 4939 error = sysctl_handle_int(oidp, &input, 0, req); 4940 4941 if ((error) || (req->newptr == NULL)) 4942 return (error); 4943 4944 if (input == sc->fc) /* no change? */ 4945 return (error); 4946 4947 switch (input) { 4948 case e1000_fc_rx_pause: 4949 case e1000_fc_tx_pause: 4950 case e1000_fc_full: 4951 case e1000_fc_none: 4952 sc->hw.fc.requested_mode = input; 4953 sc->fc = input; 4954 break; 4955 default: 4956 /* Do nothing */ 4957 return (error); 4958 } 4959 4960 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4961 e1000_force_mac_fc(&sc->hw); 4962 return (error); 4963 } 4964 4965 /* 4966 * Manage Energy Efficient Ethernet: 4967 * Control values: 4968 * 0/1 - enabled/disabled 4969 */ 4970 static int 4971 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4972 { 4973 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4974 int error, value; 4975 4976 value = sc->hw.dev_spec.ich8lan.eee_disable; 4977 error = sysctl_handle_int(oidp, &value, 0, req); 4978 if (error || req->newptr == NULL) 4979 return (error); 4980 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4981 em_if_init(sc->ctx); 4982 4983 return (0); 4984 } 4985 4986 static int 4987 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4988 { 4989 struct e1000_softc *sc; 4990 int error; 4991 int result; 4992 4993 result = -1; 4994 error = sysctl_handle_int(oidp, &result, 0, req); 4995 4996 if (error || !req->newptr) 4997 return (error); 4998 4999 if (result == 1) { 5000 sc = (struct e1000_softc *) arg1; 5001 em_print_debug_info(sc); 5002 } 5003 5004 return (error); 5005 } 5006 5007 static int 5008 em_get_rs(SYSCTL_HANDLER_ARGS) 5009 { 5010 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5011 int error; 5012 int result; 5013 5014 result = 0; 5015 error = sysctl_handle_int(oidp, &result, 0, req); 5016 5017 if (error || !req->newptr || result != 1) 5018 return (error); 5019 em_dump_rs(sc); 5020 5021 return (error); 5022 } 5023 5024 static void 5025 em_if_debug(if_ctx_t ctx) 5026 { 5027 em_dump_rs(iflib_get_softc(ctx)); 5028 } 5029 5030 /* 5031 * This routine is meant to be fluid, add whatever is 5032 * needed for debugging a problem. -jfv 5033 */ 5034 static void 5035 em_print_debug_info(struct e1000_softc *sc) 5036 { 5037 device_t dev = iflib_get_dev(sc->ctx); 5038 if_t ifp = iflib_get_ifp(sc->ctx); 5039 struct tx_ring *txr = &sc->tx_queues->txr; 5040 struct rx_ring *rxr = &sc->rx_queues->rxr; 5041 5042 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5043 printf("Interface is RUNNING "); 5044 else 5045 printf("Interface is NOT RUNNING\n"); 5046 5047 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5048 printf("and INACTIVE\n"); 5049 else 5050 printf("and ACTIVE\n"); 5051 5052 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5053 device_printf(dev, "TX Queue %d ------\n", i); 5054 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5055 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5056 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5057 5058 } 5059 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5060 device_printf(dev, "RX Queue %d ------\n", j); 5061 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5062 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5063 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5064 } 5065 } 5066 5067 /* 5068 * 82574 only: 5069 * Write a new value to the EEPROM increasing the number of MSI-X 5070 * vectors from 3 to 5, for proper multiqueue support. 5071 */ 5072 static void 5073 em_enable_vectors_82574(if_ctx_t ctx) 5074 { 5075 struct e1000_softc *sc = iflib_get_softc(ctx); 5076 struct e1000_hw *hw = &sc->hw; 5077 device_t dev = iflib_get_dev(ctx); 5078 u16 edata; 5079 5080 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5081 if (bootverbose) 5082 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5083 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5084 device_printf(dev, "Writing to eeprom: increasing " 5085 "reported MSI-X vectors from 3 to 5...\n"); 5086 edata &= ~(EM_NVM_MSIX_N_MASK); 5087 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5088 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5089 e1000_update_nvm_checksum(hw); 5090 device_printf(dev, "Writing to eeprom: done\n"); 5091 } 5092 } 5093