1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 /* required last entry */ 170 PVID_END 171 }; 172 173 static pci_vendor_info_t igb_vendor_info_array[] = 174 { 175 /* Intel(R) PRO/1000 Network Connection - igb */ 176 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 /* required last entry */ 216 PVID_END 217 }; 218 219 /********************************************************************* 220 * Function prototypes 221 *********************************************************************/ 222 static void *em_register(device_t dev); 223 static void *igb_register(device_t dev); 224 static int em_if_attach_pre(if_ctx_t ctx); 225 static int em_if_attach_post(if_ctx_t ctx); 226 static int em_if_detach(if_ctx_t ctx); 227 static int em_if_shutdown(if_ctx_t ctx); 228 static int em_if_suspend(if_ctx_t ctx); 229 static int em_if_resume(if_ctx_t ctx); 230 231 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 232 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 233 static void em_if_queues_free(if_ctx_t ctx); 234 235 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 236 static void em_if_init(if_ctx_t ctx); 237 static void em_if_stop(if_ctx_t ctx); 238 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 239 static int em_if_media_change(if_ctx_t ctx); 240 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 241 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 242 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 243 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 244 245 static void em_identify_hardware(if_ctx_t ctx); 246 static int em_allocate_pci_resources(if_ctx_t ctx); 247 static void em_free_pci_resources(if_ctx_t ctx); 248 static void em_reset(if_ctx_t ctx); 249 static int em_setup_interface(if_ctx_t ctx); 250 static int em_setup_msix(if_ctx_t ctx); 251 252 static void em_initialize_transmit_unit(if_ctx_t ctx); 253 static void em_initialize_receive_unit(if_ctx_t ctx); 254 255 static void em_if_enable_intr(if_ctx_t ctx); 256 static void em_if_disable_intr(if_ctx_t ctx); 257 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 258 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 259 static void em_if_multi_set(if_ctx_t ctx); 260 static void em_if_update_admin_status(if_ctx_t ctx); 261 static void em_if_debug(if_ctx_t ctx); 262 static void em_update_stats_counters(struct adapter *); 263 static void em_add_hw_stats(struct adapter *adapter); 264 static int em_if_set_promisc(if_ctx_t ctx, int flags); 265 static void em_setup_vlan_hw_support(struct adapter *); 266 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 267 static void em_print_nvm_info(struct adapter *); 268 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 269 static int em_get_rs(SYSCTL_HANDLER_ARGS); 270 static void em_print_debug_info(struct adapter *); 271 static int em_is_valid_ether_addr(u8 *); 272 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 273 static void em_add_int_delay_sysctl(struct adapter *, const char *, 274 const char *, struct em_int_delay_info *, int, int); 275 /* Management and WOL Support */ 276 static void em_init_manageability(struct adapter *); 277 static void em_release_manageability(struct adapter *); 278 static void em_get_hw_control(struct adapter *); 279 static void em_release_hw_control(struct adapter *); 280 static void em_get_wakeup(if_ctx_t ctx); 281 static void em_enable_wakeup(if_ctx_t ctx); 282 static int em_enable_phy_wakeup(struct adapter *); 283 static void em_disable_aspm(struct adapter *); 284 285 int em_intr(void *arg); 286 static void em_disable_promisc(if_ctx_t ctx); 287 288 /* MSIX handlers */ 289 static int em_if_msix_intr_assign(if_ctx_t, int); 290 static int em_msix_link(void *); 291 static void em_handle_link(void *context); 292 293 static void em_enable_vectors_82574(if_ctx_t); 294 295 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 296 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 297 static void em_if_led_func(if_ctx_t ctx, int onoff); 298 299 static int em_get_regs(SYSCTL_HANDLER_ARGS); 300 301 static void lem_smartspeed(struct adapter *adapter); 302 static void igb_configure_queues(struct adapter *adapter); 303 304 305 /********************************************************************* 306 * FreeBSD Device Interface Entry Points 307 *********************************************************************/ 308 static device_method_t em_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_register, em_register), 311 DEVMETHOD(device_probe, iflib_device_probe), 312 DEVMETHOD(device_attach, iflib_device_attach), 313 DEVMETHOD(device_detach, iflib_device_detach), 314 DEVMETHOD(device_shutdown, iflib_device_shutdown), 315 DEVMETHOD(device_suspend, iflib_device_suspend), 316 DEVMETHOD(device_resume, iflib_device_resume), 317 DEVMETHOD_END 318 }; 319 320 static device_method_t igb_methods[] = { 321 /* Device interface */ 322 DEVMETHOD(device_register, igb_register), 323 DEVMETHOD(device_probe, iflib_device_probe), 324 DEVMETHOD(device_attach, iflib_device_attach), 325 DEVMETHOD(device_detach, iflib_device_detach), 326 DEVMETHOD(device_shutdown, iflib_device_shutdown), 327 DEVMETHOD(device_suspend, iflib_device_suspend), 328 DEVMETHOD(device_resume, iflib_device_resume), 329 DEVMETHOD_END 330 }; 331 332 333 static driver_t em_driver = { 334 "em", em_methods, sizeof(struct adapter), 335 }; 336 337 static devclass_t em_devclass; 338 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 339 340 MODULE_DEPEND(em, pci, 1, 1, 1); 341 MODULE_DEPEND(em, ether, 1, 1, 1); 342 MODULE_DEPEND(em, iflib, 1, 1, 1); 343 344 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 345 346 static driver_t igb_driver = { 347 "igb", igb_methods, sizeof(struct adapter), 348 }; 349 350 static devclass_t igb_devclass; 351 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 352 353 MODULE_DEPEND(igb, pci, 1, 1, 1); 354 MODULE_DEPEND(igb, ether, 1, 1, 1); 355 MODULE_DEPEND(igb, iflib, 1, 1, 1); 356 357 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 358 359 static device_method_t em_if_methods[] = { 360 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 361 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 362 DEVMETHOD(ifdi_detach, em_if_detach), 363 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 364 DEVMETHOD(ifdi_suspend, em_if_suspend), 365 DEVMETHOD(ifdi_resume, em_if_resume), 366 DEVMETHOD(ifdi_init, em_if_init), 367 DEVMETHOD(ifdi_stop, em_if_stop), 368 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 369 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 370 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 371 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 372 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 373 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 374 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 375 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 376 DEVMETHOD(ifdi_media_status, em_if_media_status), 377 DEVMETHOD(ifdi_media_change, em_if_media_change), 378 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 379 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 380 DEVMETHOD(ifdi_timer, em_if_timer), 381 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 382 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 383 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 384 DEVMETHOD(ifdi_led_func, em_if_led_func), 385 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 386 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 387 DEVMETHOD(ifdi_debug, em_if_debug), 388 DEVMETHOD_END 389 }; 390 391 /* 392 * note that if (adapter->msix_mem) is replaced by: 393 * if (adapter->intr_type == IFLIB_INTR_MSIX) 394 */ 395 static driver_t em_if_driver = { 396 "em_if", em_if_methods, sizeof(struct adapter) 397 }; 398 399 /********************************************************************* 400 * Tunable default values. 401 *********************************************************************/ 402 403 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 404 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 405 #define M_TSO_LEN 66 406 407 #define MAX_INTS_PER_SEC 8000 408 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 409 410 /* Allow common code without TSO */ 411 #ifndef CSUM_TSO 412 #define CSUM_TSO 0 413 #endif 414 415 #define TSO_WORKAROUND 4 416 417 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 418 419 static int em_disable_crc_stripping = 0; 420 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 421 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 422 423 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 424 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 425 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 426 0, "Default transmit interrupt delay in usecs"); 427 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 428 0, "Default receive interrupt delay in usecs"); 429 430 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 431 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 432 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 433 &em_tx_abs_int_delay_dflt, 0, 434 "Default transmit interrupt delay limit in usecs"); 435 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 436 &em_rx_abs_int_delay_dflt, 0, 437 "Default receive interrupt delay limit in usecs"); 438 439 static int em_smart_pwr_down = FALSE; 440 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 441 0, "Set to true to leave smart power down enabled on newer adapters"); 442 443 /* Controls whether promiscuous also shows bad packets */ 444 static int em_debug_sbp = TRUE; 445 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 446 "Show bad packets in promiscuous mode"); 447 448 /* How many packets rxeof tries to clean at a time */ 449 static int em_rx_process_limit = 100; 450 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 451 &em_rx_process_limit, 0, 452 "Maximum number of received packets to process " 453 "at a time, -1 means unlimited"); 454 455 /* Energy efficient ethernet - default to OFF */ 456 static int eee_setting = 1; 457 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 458 "Enable Energy Efficient Ethernet"); 459 460 /* 461 ** Tuneable Interrupt rate 462 */ 463 static int em_max_interrupt_rate = 8000; 464 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 465 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 466 467 468 469 /* Global used in WOL setup with multiport cards */ 470 static int global_quad_port_a = 0; 471 472 extern struct if_txrx igb_txrx; 473 extern struct if_txrx em_txrx; 474 extern struct if_txrx lem_txrx; 475 476 static struct if_shared_ctx em_sctx_init = { 477 .isc_magic = IFLIB_MAGIC, 478 .isc_q_align = PAGE_SIZE, 479 .isc_tx_maxsize = EM_TSO_SIZE, 480 .isc_tx_maxsegsize = PAGE_SIZE, 481 .isc_rx_maxsize = MJUM9BYTES, 482 .isc_rx_nsegments = 1, 483 .isc_rx_maxsegsize = MJUM9BYTES, 484 .isc_nfl = 1, 485 .isc_nrxqs = 1, 486 .isc_ntxqs = 1, 487 .isc_admin_intrcnt = 1, 488 .isc_vendor_info = em_vendor_info_array, 489 .isc_driver_version = em_driver_version, 490 .isc_driver = &em_if_driver, 491 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 492 493 .isc_nrxd_min = {EM_MIN_RXD}, 494 .isc_ntxd_min = {EM_MIN_TXD}, 495 .isc_nrxd_max = {EM_MAX_RXD}, 496 .isc_ntxd_max = {EM_MAX_TXD}, 497 .isc_nrxd_default = {EM_DEFAULT_RXD}, 498 .isc_ntxd_default = {EM_DEFAULT_TXD}, 499 }; 500 501 if_shared_ctx_t em_sctx = &em_sctx_init; 502 503 504 static struct if_shared_ctx igb_sctx_init = { 505 .isc_magic = IFLIB_MAGIC, 506 .isc_q_align = PAGE_SIZE, 507 .isc_tx_maxsize = EM_TSO_SIZE, 508 .isc_tx_maxsegsize = PAGE_SIZE, 509 .isc_rx_maxsize = MJUM9BYTES, 510 .isc_rx_nsegments = 1, 511 .isc_rx_maxsegsize = MJUM9BYTES, 512 .isc_nfl = 1, 513 .isc_nrxqs = 1, 514 .isc_ntxqs = 1, 515 .isc_admin_intrcnt = 1, 516 .isc_vendor_info = igb_vendor_info_array, 517 .isc_driver_version = em_driver_version, 518 .isc_driver = &em_if_driver, 519 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 520 521 .isc_nrxd_min = {EM_MIN_RXD}, 522 .isc_ntxd_min = {EM_MIN_TXD}, 523 .isc_nrxd_max = {IGB_MAX_RXD}, 524 .isc_ntxd_max = {IGB_MAX_TXD}, 525 .isc_nrxd_default = {EM_DEFAULT_RXD}, 526 .isc_ntxd_default = {EM_DEFAULT_TXD}, 527 }; 528 529 if_shared_ctx_t igb_sctx = &igb_sctx_init; 530 531 /***************************************************************** 532 * 533 * Dump Registers 534 * 535 ****************************************************************/ 536 #define IGB_REGS_LEN 739 537 538 static int em_get_regs(SYSCTL_HANDLER_ARGS) 539 { 540 struct adapter *adapter = (struct adapter *)arg1; 541 struct e1000_hw *hw = &adapter->hw; 542 struct sbuf *sb; 543 u32 *regs_buff; 544 int rc; 545 546 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 547 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 548 549 rc = sysctl_wire_old_buffer(req, 0); 550 MPASS(rc == 0); 551 if (rc != 0) { 552 free(regs_buff, M_DEVBUF); 553 return (rc); 554 } 555 556 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 557 MPASS(sb != NULL); 558 if (sb == NULL) { 559 free(regs_buff, M_DEVBUF); 560 return (ENOMEM); 561 } 562 563 /* General Registers */ 564 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 565 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 566 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 567 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 568 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 569 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 570 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 571 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 572 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 573 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 574 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 575 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 576 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 577 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 578 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 579 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 580 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 581 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 582 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 583 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 584 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 585 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 586 587 sbuf_printf(sb, "General Registers\n"); 588 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 589 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 590 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 591 592 sbuf_printf(sb, "Interrupt Registers\n"); 593 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 594 595 sbuf_printf(sb, "RX Registers\n"); 596 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 597 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 598 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 599 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 600 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 601 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 602 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 603 604 sbuf_printf(sb, "TX Registers\n"); 605 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 606 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 607 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 608 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 609 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 610 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 611 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 612 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 613 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 614 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 615 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 616 617 free(regs_buff, M_DEVBUF); 618 619 #ifdef DUMP_DESCS 620 { 621 if_softc_ctx_t scctx = adapter->shared; 622 struct rx_ring *rxr = &rx_que->rxr; 623 struct tx_ring *txr = &tx_que->txr; 624 int ntxd = scctx->isc_ntxd[0]; 625 int nrxd = scctx->isc_nrxd[0]; 626 int j; 627 628 for (j = 0; j < nrxd; j++) { 629 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 630 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 631 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 632 } 633 634 for (j = 0; j < min(ntxd, 256); j++) { 635 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 636 637 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 638 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 639 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 640 641 } 642 } 643 #endif 644 645 rc = sbuf_finish(sb); 646 sbuf_delete(sb); 647 return(rc); 648 } 649 650 static void * 651 em_register(device_t dev) 652 { 653 return (em_sctx); 654 } 655 656 static void * 657 igb_register(device_t dev) 658 { 659 return (igb_sctx); 660 } 661 662 static int 663 em_set_num_queues(if_ctx_t ctx) 664 { 665 struct adapter *adapter = iflib_get_softc(ctx); 666 int maxqueues; 667 668 /* Sanity check based on HW */ 669 switch (adapter->hw.mac.type) { 670 case e1000_82576: 671 case e1000_82580: 672 case e1000_i350: 673 case e1000_i354: 674 maxqueues = 8; 675 break; 676 case e1000_i210: 677 case e1000_82575: 678 maxqueues = 4; 679 break; 680 case e1000_i211: 681 case e1000_82574: 682 maxqueues = 2; 683 break; 684 default: 685 maxqueues = 1; 686 break; 687 } 688 689 return (maxqueues); 690 } 691 692 693 #define EM_CAPS \ 694 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 695 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 696 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 697 698 #define IGB_CAPS \ 699 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 700 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 701 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 702 703 /********************************************************************* 704 * Device initialization routine 705 * 706 * The attach entry point is called when the driver is being loaded. 707 * This routine identifies the type of hardware, allocates all resources 708 * and initializes the hardware. 709 * 710 * return 0 on success, positive on failure 711 *********************************************************************/ 712 713 static int 714 em_if_attach_pre(if_ctx_t ctx) 715 { 716 struct adapter *adapter; 717 if_softc_ctx_t scctx; 718 device_t dev; 719 struct e1000_hw *hw; 720 int error = 0; 721 722 INIT_DEBUGOUT("em_if_attach_pre begin"); 723 dev = iflib_get_dev(ctx); 724 adapter = iflib_get_softc(ctx); 725 726 if (resource_disabled("em", device_get_unit(dev))) { 727 device_printf(dev, "Disabled by device hint\n"); 728 return (ENXIO); 729 } 730 731 adapter->ctx = ctx; 732 adapter->dev = adapter->osdep.dev = dev; 733 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 734 adapter->media = iflib_get_media(ctx); 735 hw = &adapter->hw; 736 737 adapter->tx_process_limit = scctx->isc_ntxd[0]; 738 739 /* SYSCTL stuff */ 740 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 741 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 742 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 743 em_sysctl_nvm_info, "I", "NVM Information"); 744 745 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 746 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 747 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 748 em_sysctl_debug_info, "I", "Debug Information"); 749 750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 751 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 752 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 753 em_set_flowcntl, "I", "Flow Control"); 754 755 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 756 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 757 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 758 em_get_regs, "A", "Dump Registers"); 759 760 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 761 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 762 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 763 em_get_rs, "I", "Dump RS indexes"); 764 765 /* Determine hardware and mac info */ 766 em_identify_hardware(ctx); 767 768 /* Set isc_msix_bar */ 769 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 770 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 771 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 772 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 773 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 774 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 775 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 776 777 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 778 779 780 if (adapter->hw.mac.type >= igb_mac_min) { 781 int try_second_bar; 782 783 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 784 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 785 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 786 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 787 scctx->isc_txrx = &igb_txrx; 788 scctx->isc_capenable = IGB_CAPS; 789 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 790 | CSUM_IP6_UDP | CSUM_IP6_TCP; 791 if (adapter->hw.mac.type != e1000_82575) 792 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 793 794 /* 795 ** Some new devices, as with ixgbe, now may 796 ** use a different BAR, so we need to keep 797 ** track of which is used. 798 */ 799 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 800 if (try_second_bar == 0) 801 scctx->isc_msix_bar += 4; 802 803 } else if (adapter->hw.mac.type >= em_mac_min) { 804 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 805 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 806 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 807 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 808 scctx->isc_txrx = &em_txrx; 809 scctx->isc_capenable = EM_CAPS; 810 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 811 } else { 812 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 813 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 814 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 815 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 816 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 817 scctx->isc_txrx = &lem_txrx; 818 scctx->isc_capenable = EM_CAPS; 819 if (adapter->hw.mac.type < e1000_82543) 820 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 821 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 822 scctx->isc_msix_bar = 0; 823 } 824 825 /* Setup PCI resources */ 826 if (em_allocate_pci_resources(ctx)) { 827 device_printf(dev, "Allocation of PCI resources failed\n"); 828 error = ENXIO; 829 goto err_pci; 830 } 831 832 /* 833 ** For ICH8 and family we need to 834 ** map the flash memory, and this 835 ** must happen after the MAC is 836 ** identified 837 */ 838 if ((hw->mac.type == e1000_ich8lan) || 839 (hw->mac.type == e1000_ich9lan) || 840 (hw->mac.type == e1000_ich10lan) || 841 (hw->mac.type == e1000_pchlan) || 842 (hw->mac.type == e1000_pch2lan) || 843 (hw->mac.type == e1000_pch_lpt)) { 844 int rid = EM_BAR_TYPE_FLASH; 845 adapter->flash = bus_alloc_resource_any(dev, 846 SYS_RES_MEMORY, &rid, RF_ACTIVE); 847 if (adapter->flash == NULL) { 848 device_printf(dev, "Mapping of Flash failed\n"); 849 error = ENXIO; 850 goto err_pci; 851 } 852 /* This is used in the shared code */ 853 hw->flash_address = (u8 *)adapter->flash; 854 adapter->osdep.flash_bus_space_tag = 855 rman_get_bustag(adapter->flash); 856 adapter->osdep.flash_bus_space_handle = 857 rman_get_bushandle(adapter->flash); 858 } 859 /* 860 ** In the new SPT device flash is not a 861 ** separate BAR, rather it is also in BAR0, 862 ** so use the same tag and an offset handle for the 863 ** FLASH read/write macros in the shared code. 864 */ 865 else if (hw->mac.type == e1000_pch_spt) { 866 adapter->osdep.flash_bus_space_tag = 867 adapter->osdep.mem_bus_space_tag; 868 adapter->osdep.flash_bus_space_handle = 869 adapter->osdep.mem_bus_space_handle 870 + E1000_FLASH_BASE_ADDR; 871 } 872 873 /* Do Shared Code initialization */ 874 error = e1000_setup_init_funcs(hw, TRUE); 875 if (error) { 876 device_printf(dev, "Setup of Shared code failed, error %d\n", 877 error); 878 error = ENXIO; 879 goto err_pci; 880 } 881 882 em_setup_msix(ctx); 883 e1000_get_bus_info(hw); 884 885 /* Set up some sysctls for the tunable interrupt delays */ 886 em_add_int_delay_sysctl(adapter, "rx_int_delay", 887 "receive interrupt delay in usecs", &adapter->rx_int_delay, 888 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 889 em_add_int_delay_sysctl(adapter, "tx_int_delay", 890 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 891 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 892 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 893 "receive interrupt delay limit in usecs", 894 &adapter->rx_abs_int_delay, 895 E1000_REGISTER(hw, E1000_RADV), 896 em_rx_abs_int_delay_dflt); 897 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 898 "transmit interrupt delay limit in usecs", 899 &adapter->tx_abs_int_delay, 900 E1000_REGISTER(hw, E1000_TADV), 901 em_tx_abs_int_delay_dflt); 902 em_add_int_delay_sysctl(adapter, "itr", 903 "interrupt delay limit in usecs/4", 904 &adapter->tx_itr, 905 E1000_REGISTER(hw, E1000_ITR), 906 DEFAULT_ITR); 907 908 hw->mac.autoneg = DO_AUTO_NEG; 909 hw->phy.autoneg_wait_to_complete = FALSE; 910 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 911 912 if (adapter->hw.mac.type < em_mac_min) { 913 e1000_init_script_state_82541(&adapter->hw, TRUE); 914 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 915 } 916 /* Copper options */ 917 if (hw->phy.media_type == e1000_media_type_copper) { 918 hw->phy.mdix = AUTO_ALL_MODES; 919 hw->phy.disable_polarity_correction = FALSE; 920 hw->phy.ms_type = EM_MASTER_SLAVE; 921 } 922 923 /* 924 * Set the frame limits assuming 925 * standard ethernet sized frames. 926 */ 927 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 928 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 929 930 /* 931 * This controls when hardware reports transmit completion 932 * status. 933 */ 934 hw->mac.report_tx_early = 1; 935 936 /* Allocate multicast array memory. */ 937 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 938 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 939 if (adapter->mta == NULL) { 940 device_printf(dev, "Can not allocate multicast setup array\n"); 941 error = ENOMEM; 942 goto err_late; 943 } 944 945 /* Check SOL/IDER usage */ 946 if (e1000_check_reset_block(hw)) 947 device_printf(dev, "PHY reset is blocked" 948 " due to SOL/IDER session.\n"); 949 950 /* Sysctl for setting Energy Efficient Ethernet */ 951 hw->dev_spec.ich8lan.eee_disable = eee_setting; 952 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 953 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 954 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 955 adapter, 0, em_sysctl_eee, "I", 956 "Disable Energy Efficient Ethernet"); 957 958 /* 959 ** Start from a known state, this is 960 ** important in reading the nvm and 961 ** mac from that. 962 */ 963 e1000_reset_hw(hw); 964 965 /* Make sure we have a good EEPROM before we read from it */ 966 if (e1000_validate_nvm_checksum(hw) < 0) { 967 /* 968 ** Some PCI-E parts fail the first check due to 969 ** the link being in sleep state, call it again, 970 ** if it fails a second time its a real issue. 971 */ 972 if (e1000_validate_nvm_checksum(hw) < 0) { 973 device_printf(dev, 974 "The EEPROM Checksum Is Not Valid\n"); 975 error = EIO; 976 goto err_late; 977 } 978 } 979 980 /* Copy the permanent MAC address out of the EEPROM */ 981 if (e1000_read_mac_addr(hw) < 0) { 982 device_printf(dev, "EEPROM read error while reading MAC" 983 " address\n"); 984 error = EIO; 985 goto err_late; 986 } 987 988 if (!em_is_valid_ether_addr(hw->mac.addr)) { 989 device_printf(dev, "Invalid MAC address\n"); 990 error = EIO; 991 goto err_late; 992 } 993 994 /* Disable ULP support */ 995 e1000_disable_ulp_lpt_lp(hw, TRUE); 996 997 /* 998 * Get Wake-on-Lan and Management info for later use 999 */ 1000 em_get_wakeup(ctx); 1001 1002 iflib_set_mac(ctx, hw->mac.addr); 1003 1004 return (0); 1005 1006 err_late: 1007 em_release_hw_control(adapter); 1008 err_pci: 1009 em_free_pci_resources(ctx); 1010 free(adapter->mta, M_DEVBUF); 1011 1012 return (error); 1013 } 1014 1015 static int 1016 em_if_attach_post(if_ctx_t ctx) 1017 { 1018 struct adapter *adapter = iflib_get_softc(ctx); 1019 struct e1000_hw *hw = &adapter->hw; 1020 int error = 0; 1021 1022 /* Setup OS specific network interface */ 1023 error = em_setup_interface(ctx); 1024 if (error != 0) { 1025 goto err_late; 1026 } 1027 1028 em_reset(ctx); 1029 1030 /* Initialize statistics */ 1031 em_update_stats_counters(adapter); 1032 hw->mac.get_link_status = 1; 1033 em_if_update_admin_status(ctx); 1034 em_add_hw_stats(adapter); 1035 1036 /* Non-AMT based hardware can now take control from firmware */ 1037 if (adapter->has_manage && !adapter->has_amt) 1038 em_get_hw_control(adapter); 1039 1040 INIT_DEBUGOUT("em_if_attach_post: end"); 1041 1042 return (error); 1043 1044 err_late: 1045 em_release_hw_control(adapter); 1046 em_free_pci_resources(ctx); 1047 em_if_queues_free(ctx); 1048 free(adapter->mta, M_DEVBUF); 1049 1050 return (error); 1051 } 1052 1053 /********************************************************************* 1054 * Device removal routine 1055 * 1056 * The detach entry point is called when the driver is being removed. 1057 * This routine stops the adapter and deallocates all the resources 1058 * that were allocated for driver operation. 1059 * 1060 * return 0 on success, positive on failure 1061 *********************************************************************/ 1062 1063 static int 1064 em_if_detach(if_ctx_t ctx) 1065 { 1066 struct adapter *adapter = iflib_get_softc(ctx); 1067 1068 INIT_DEBUGOUT("em_detach: begin"); 1069 1070 e1000_phy_hw_reset(&adapter->hw); 1071 1072 em_release_manageability(adapter); 1073 em_release_hw_control(adapter); 1074 em_free_pci_resources(ctx); 1075 1076 return (0); 1077 } 1078 1079 /********************************************************************* 1080 * 1081 * Shutdown entry point 1082 * 1083 **********************************************************************/ 1084 1085 static int 1086 em_if_shutdown(if_ctx_t ctx) 1087 { 1088 return em_if_suspend(ctx); 1089 } 1090 1091 /* 1092 * Suspend/resume device methods. 1093 */ 1094 static int 1095 em_if_suspend(if_ctx_t ctx) 1096 { 1097 struct adapter *adapter = iflib_get_softc(ctx); 1098 1099 em_release_manageability(adapter); 1100 em_release_hw_control(adapter); 1101 em_enable_wakeup(ctx); 1102 return (0); 1103 } 1104 1105 static int 1106 em_if_resume(if_ctx_t ctx) 1107 { 1108 struct adapter *adapter = iflib_get_softc(ctx); 1109 1110 if (adapter->hw.mac.type == e1000_pch2lan) 1111 e1000_resume_workarounds_pchlan(&adapter->hw); 1112 em_if_init(ctx); 1113 em_init_manageability(adapter); 1114 1115 return(0); 1116 } 1117 1118 static int 1119 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1120 { 1121 int max_frame_size; 1122 struct adapter *adapter = iflib_get_softc(ctx); 1123 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1124 1125 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1126 1127 switch (adapter->hw.mac.type) { 1128 case e1000_82571: 1129 case e1000_82572: 1130 case e1000_ich9lan: 1131 case e1000_ich10lan: 1132 case e1000_pch2lan: 1133 case e1000_pch_lpt: 1134 case e1000_pch_spt: 1135 case e1000_82574: 1136 case e1000_82583: 1137 case e1000_80003es2lan: 1138 /* 9K Jumbo Frame size */ 1139 max_frame_size = 9234; 1140 break; 1141 case e1000_pchlan: 1142 max_frame_size = 4096; 1143 break; 1144 case e1000_82542: 1145 case e1000_ich8lan: 1146 /* Adapters that do not support jumbo frames */ 1147 max_frame_size = ETHER_MAX_LEN; 1148 break; 1149 default: 1150 if (adapter->hw.mac.type >= igb_mac_min) 1151 max_frame_size = 9234; 1152 else /* lem */ 1153 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1154 } 1155 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1156 return (EINVAL); 1157 } 1158 1159 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1160 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1161 return (0); 1162 } 1163 1164 /********************************************************************* 1165 * Init entry point 1166 * 1167 * This routine is used in two ways. It is used by the stack as 1168 * init entry point in network interface structure. It is also used 1169 * by the driver as a hw/sw initialization routine to get to a 1170 * consistent state. 1171 * 1172 * return 0 on success, positive on failure 1173 **********************************************************************/ 1174 1175 static void 1176 em_if_init(if_ctx_t ctx) 1177 { 1178 struct adapter *adapter = iflib_get_softc(ctx); 1179 struct ifnet *ifp = iflib_get_ifp(ctx); 1180 struct em_tx_queue *tx_que; 1181 int i; 1182 INIT_DEBUGOUT("em_if_init: begin"); 1183 1184 /* Get the latest mac address, User can use a LAA */ 1185 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1186 ETHER_ADDR_LEN); 1187 1188 /* Put the address into the Receive Address Array */ 1189 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1190 1191 /* 1192 * With the 82571 adapter, RAR[0] may be overwritten 1193 * when the other port is reset, we make a duplicate 1194 * in RAR[14] for that eventuality, this assures 1195 * the interface continues to function. 1196 */ 1197 if (adapter->hw.mac.type == e1000_82571) { 1198 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1199 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1200 E1000_RAR_ENTRIES - 1); 1201 } 1202 1203 1204 /* Initialize the hardware */ 1205 em_reset(ctx); 1206 em_if_update_admin_status(ctx); 1207 1208 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1209 struct tx_ring *txr = &tx_que->txr; 1210 1211 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1212 } 1213 1214 /* Setup VLAN support, basic and offload if available */ 1215 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1216 1217 /* Clear bad data from Rx FIFOs */ 1218 if (adapter->hw.mac.type >= igb_mac_min) 1219 e1000_rx_fifo_flush_82575(&adapter->hw); 1220 1221 /* Configure for OS presence */ 1222 em_init_manageability(adapter); 1223 1224 /* Prepare transmit descriptors and buffers */ 1225 em_initialize_transmit_unit(ctx); 1226 1227 /* Setup Multicast table */ 1228 em_if_multi_set(ctx); 1229 1230 /* 1231 * Figure out the desired mbuf 1232 * pool for doing jumbos 1233 */ 1234 if (adapter->hw.mac.max_frame_size <= 2048) 1235 adapter->rx_mbuf_sz = MCLBYTES; 1236 #ifndef CONTIGMALLOC_WORKS 1237 else 1238 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1239 #else 1240 else if (adapter->hw.mac.max_frame_size <= 4096) 1241 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1242 else 1243 adapter->rx_mbuf_sz = MJUM9BYTES; 1244 #endif 1245 em_initialize_receive_unit(ctx); 1246 1247 /* Use real VLAN Filter support? */ 1248 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1249 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1250 /* Use real VLAN Filter support */ 1251 em_setup_vlan_hw_support(adapter); 1252 else { 1253 u32 ctrl; 1254 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1255 ctrl |= E1000_CTRL_VME; 1256 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1257 } 1258 } 1259 1260 /* Don't lose promiscuous settings */ 1261 em_if_set_promisc(ctx, IFF_PROMISC); 1262 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1263 1264 /* MSI/X configuration for 82574 */ 1265 if (adapter->hw.mac.type == e1000_82574) { 1266 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1267 1268 tmp |= E1000_CTRL_EXT_PBA_CLR; 1269 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1270 /* Set the IVAR - interrupt vector routing. */ 1271 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1272 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1273 igb_configure_queues(adapter); 1274 1275 /* this clears any pending interrupts */ 1276 E1000_READ_REG(&adapter->hw, E1000_ICR); 1277 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1278 1279 /* AMT based hardware can now take control from firmware */ 1280 if (adapter->has_manage && adapter->has_amt) 1281 em_get_hw_control(adapter); 1282 1283 /* Set Energy Efficient Ethernet */ 1284 if (adapter->hw.mac.type >= igb_mac_min && 1285 adapter->hw.phy.media_type == e1000_media_type_copper) { 1286 if (adapter->hw.mac.type == e1000_i354) 1287 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1288 else 1289 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1290 } 1291 } 1292 1293 /********************************************************************* 1294 * 1295 * Fast Legacy/MSI Combined Interrupt Service routine 1296 * 1297 *********************************************************************/ 1298 int 1299 em_intr(void *arg) 1300 { 1301 struct adapter *adapter = arg; 1302 if_ctx_t ctx = adapter->ctx; 1303 u32 reg_icr; 1304 1305 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1306 1307 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1308 goto skip_stray; 1309 /* Hot eject? */ 1310 if (reg_icr == 0xffffffff) 1311 return FILTER_STRAY; 1312 1313 /* Definitely not our interrupt. */ 1314 if (reg_icr == 0x0) 1315 return FILTER_STRAY; 1316 1317 /* 1318 * Starting with the 82571 chip, bit 31 should be used to 1319 * determine whether the interrupt belongs to us. 1320 */ 1321 if (adapter->hw.mac.type >= e1000_82571 && 1322 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1323 return FILTER_STRAY; 1324 1325 skip_stray: 1326 /* Link status change */ 1327 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1328 adapter->hw.mac.get_link_status = 1; 1329 iflib_admin_intr_deferred(ctx); 1330 } 1331 1332 if (reg_icr & E1000_ICR_RXO) 1333 adapter->rx_overruns++; 1334 1335 return (FILTER_SCHEDULE_THREAD); 1336 } 1337 1338 static void 1339 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1340 { 1341 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1342 } 1343 1344 static void 1345 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1346 { 1347 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1348 } 1349 1350 static void 1351 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1352 { 1353 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1354 } 1355 1356 static void 1357 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1358 { 1359 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1360 } 1361 1362 static int 1363 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1364 { 1365 struct adapter *adapter = iflib_get_softc(ctx); 1366 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1367 1368 if (adapter->hw.mac.type >= igb_mac_min) 1369 igb_rx_enable_queue(adapter, rxq); 1370 else 1371 em_rx_enable_queue(adapter, rxq); 1372 return (0); 1373 } 1374 1375 static int 1376 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1377 { 1378 struct adapter *adapter = iflib_get_softc(ctx); 1379 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1380 1381 if (adapter->hw.mac.type >= igb_mac_min) 1382 igb_tx_enable_queue(adapter, txq); 1383 else 1384 em_tx_enable_queue(adapter, txq); 1385 return (0); 1386 } 1387 1388 /********************************************************************* 1389 * 1390 * MSIX RX Interrupt Service routine 1391 * 1392 **********************************************************************/ 1393 static int 1394 em_msix_que(void *arg) 1395 { 1396 struct em_rx_queue *que = arg; 1397 1398 ++que->irqs; 1399 1400 return (FILTER_SCHEDULE_THREAD); 1401 } 1402 1403 /********************************************************************* 1404 * 1405 * MSIX Link Fast Interrupt Service routine 1406 * 1407 **********************************************************************/ 1408 static int 1409 em_msix_link(void *arg) 1410 { 1411 struct adapter *adapter = arg; 1412 u32 reg_icr; 1413 1414 ++adapter->link_irq; 1415 MPASS(adapter->hw.back != NULL); 1416 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1417 1418 if (reg_icr & E1000_ICR_RXO) 1419 adapter->rx_overruns++; 1420 1421 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1422 em_handle_link(adapter->ctx); 1423 } else { 1424 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1425 EM_MSIX_LINK | E1000_IMS_LSC); 1426 if (adapter->hw.mac.type >= igb_mac_min) 1427 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1428 } 1429 1430 /* 1431 * Because we must read the ICR for this interrupt 1432 * it may clear other causes using autoclear, for 1433 * this reason we simply create a soft interrupt 1434 * for all these vectors. 1435 */ 1436 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1437 E1000_WRITE_REG(&adapter->hw, 1438 E1000_ICS, adapter->ims); 1439 } 1440 1441 return (FILTER_HANDLED); 1442 } 1443 1444 static void 1445 em_handle_link(void *context) 1446 { 1447 if_ctx_t ctx = context; 1448 struct adapter *adapter = iflib_get_softc(ctx); 1449 1450 adapter->hw.mac.get_link_status = 1; 1451 iflib_admin_intr_deferred(ctx); 1452 } 1453 1454 1455 /********************************************************************* 1456 * 1457 * Media Ioctl callback 1458 * 1459 * This routine is called whenever the user queries the status of 1460 * the interface using ifconfig. 1461 * 1462 **********************************************************************/ 1463 static void 1464 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1465 { 1466 struct adapter *adapter = iflib_get_softc(ctx); 1467 u_char fiber_type = IFM_1000_SX; 1468 1469 INIT_DEBUGOUT("em_if_media_status: begin"); 1470 1471 iflib_admin_intr_deferred(ctx); 1472 1473 ifmr->ifm_status = IFM_AVALID; 1474 ifmr->ifm_active = IFM_ETHER; 1475 1476 if (!adapter->link_active) { 1477 return; 1478 } 1479 1480 ifmr->ifm_status |= IFM_ACTIVE; 1481 1482 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1483 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1484 if (adapter->hw.mac.type == e1000_82545) 1485 fiber_type = IFM_1000_LX; 1486 ifmr->ifm_active |= fiber_type | IFM_FDX; 1487 } else { 1488 switch (adapter->link_speed) { 1489 case 10: 1490 ifmr->ifm_active |= IFM_10_T; 1491 break; 1492 case 100: 1493 ifmr->ifm_active |= IFM_100_TX; 1494 break; 1495 case 1000: 1496 ifmr->ifm_active |= IFM_1000_T; 1497 break; 1498 } 1499 if (adapter->link_duplex == FULL_DUPLEX) 1500 ifmr->ifm_active |= IFM_FDX; 1501 else 1502 ifmr->ifm_active |= IFM_HDX; 1503 } 1504 } 1505 1506 /********************************************************************* 1507 * 1508 * Media Ioctl callback 1509 * 1510 * This routine is called when the user changes speed/duplex using 1511 * media/mediopt option with ifconfig. 1512 * 1513 **********************************************************************/ 1514 static int 1515 em_if_media_change(if_ctx_t ctx) 1516 { 1517 struct adapter *adapter = iflib_get_softc(ctx); 1518 struct ifmedia *ifm = iflib_get_media(ctx); 1519 1520 INIT_DEBUGOUT("em_if_media_change: begin"); 1521 1522 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1523 return (EINVAL); 1524 1525 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1526 case IFM_AUTO: 1527 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1528 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1529 break; 1530 case IFM_1000_LX: 1531 case IFM_1000_SX: 1532 case IFM_1000_T: 1533 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1534 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1535 break; 1536 case IFM_100_TX: 1537 adapter->hw.mac.autoneg = FALSE; 1538 adapter->hw.phy.autoneg_advertised = 0; 1539 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1540 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1541 else 1542 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1543 break; 1544 case IFM_10_T: 1545 adapter->hw.mac.autoneg = FALSE; 1546 adapter->hw.phy.autoneg_advertised = 0; 1547 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1548 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1549 else 1550 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1551 break; 1552 default: 1553 device_printf(adapter->dev, "Unsupported media type\n"); 1554 } 1555 1556 em_if_init(ctx); 1557 1558 return (0); 1559 } 1560 1561 static int 1562 em_if_set_promisc(if_ctx_t ctx, int flags) 1563 { 1564 struct adapter *adapter = iflib_get_softc(ctx); 1565 u32 reg_rctl; 1566 1567 em_disable_promisc(ctx); 1568 1569 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1570 1571 if (flags & IFF_PROMISC) { 1572 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1573 /* Turn this on if you want to see bad packets */ 1574 if (em_debug_sbp) 1575 reg_rctl |= E1000_RCTL_SBP; 1576 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1577 } else if (flags & IFF_ALLMULTI) { 1578 reg_rctl |= E1000_RCTL_MPE; 1579 reg_rctl &= ~E1000_RCTL_UPE; 1580 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1581 } 1582 return (0); 1583 } 1584 1585 static void 1586 em_disable_promisc(if_ctx_t ctx) 1587 { 1588 struct adapter *adapter = iflib_get_softc(ctx); 1589 struct ifnet *ifp = iflib_get_ifp(ctx); 1590 u32 reg_rctl; 1591 int mcnt = 0; 1592 1593 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1594 reg_rctl &= (~E1000_RCTL_UPE); 1595 if (if_getflags(ifp) & IFF_ALLMULTI) 1596 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1597 else 1598 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1599 /* Don't disable if in MAX groups */ 1600 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1601 reg_rctl &= (~E1000_RCTL_MPE); 1602 reg_rctl &= (~E1000_RCTL_SBP); 1603 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1604 } 1605 1606 1607 /********************************************************************* 1608 * Multicast Update 1609 * 1610 * This routine is called whenever multicast address list is updated. 1611 * 1612 **********************************************************************/ 1613 1614 static void 1615 em_if_multi_set(if_ctx_t ctx) 1616 { 1617 struct adapter *adapter = iflib_get_softc(ctx); 1618 struct ifnet *ifp = iflib_get_ifp(ctx); 1619 u32 reg_rctl = 0; 1620 u8 *mta; /* Multicast array memory */ 1621 int mcnt = 0; 1622 1623 IOCTL_DEBUGOUT("em_set_multi: begin"); 1624 1625 mta = adapter->mta; 1626 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1627 1628 if (adapter->hw.mac.type == e1000_82542 && 1629 adapter->hw.revision_id == E1000_REVISION_2) { 1630 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1631 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1632 e1000_pci_clear_mwi(&adapter->hw); 1633 reg_rctl |= E1000_RCTL_RST; 1634 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1635 msec_delay(5); 1636 } 1637 1638 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1639 1640 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1641 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1642 reg_rctl |= E1000_RCTL_MPE; 1643 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1644 } else 1645 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1646 1647 if (adapter->hw.mac.type == e1000_82542 && 1648 adapter->hw.revision_id == E1000_REVISION_2) { 1649 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1650 reg_rctl &= ~E1000_RCTL_RST; 1651 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1652 msec_delay(5); 1653 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1654 e1000_pci_set_mwi(&adapter->hw); 1655 } 1656 } 1657 1658 1659 /********************************************************************* 1660 * Timer routine 1661 * 1662 * This routine checks for link status and updates statistics. 1663 * 1664 **********************************************************************/ 1665 1666 static void 1667 em_if_timer(if_ctx_t ctx, uint16_t qid) 1668 { 1669 struct adapter *adapter = iflib_get_softc(ctx); 1670 struct em_rx_queue *que; 1671 int i; 1672 int trigger = 0; 1673 1674 if (qid != 0) 1675 return; 1676 1677 iflib_admin_intr_deferred(ctx); 1678 /* Reset LAA into RAR[0] on 82571 */ 1679 if ((adapter->hw.mac.type == e1000_82571) && 1680 e1000_get_laa_state_82571(&adapter->hw)) 1681 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1682 1683 if (adapter->hw.mac.type < em_mac_min) 1684 lem_smartspeed(adapter); 1685 1686 /* Mask to use in the irq trigger */ 1687 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1688 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1689 trigger |= que->eims; 1690 } else { 1691 trigger = E1000_ICS_RXDMT0; 1692 } 1693 } 1694 1695 1696 static void 1697 em_if_update_admin_status(if_ctx_t ctx) 1698 { 1699 struct adapter *adapter = iflib_get_softc(ctx); 1700 struct e1000_hw *hw = &adapter->hw; 1701 struct ifnet *ifp = iflib_get_ifp(ctx); 1702 device_t dev = iflib_get_dev(ctx); 1703 u32 link_check, thstat, ctrl; 1704 1705 link_check = thstat = ctrl = 0; 1706 /* Get the cached link value or read phy for real */ 1707 switch (hw->phy.media_type) { 1708 case e1000_media_type_copper: 1709 if (hw->mac.get_link_status) { 1710 if (hw->mac.type == e1000_pch_spt) 1711 msec_delay(50); 1712 /* Do the work to read phy */ 1713 e1000_check_for_link(hw); 1714 link_check = !hw->mac.get_link_status; 1715 if (link_check) /* ESB2 fix */ 1716 e1000_cfg_on_link_up(hw); 1717 } else { 1718 link_check = TRUE; 1719 } 1720 break; 1721 case e1000_media_type_fiber: 1722 e1000_check_for_link(hw); 1723 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1724 E1000_STATUS_LU); 1725 break; 1726 case e1000_media_type_internal_serdes: 1727 e1000_check_for_link(hw); 1728 link_check = adapter->hw.mac.serdes_has_link; 1729 break; 1730 /* VF device is type_unknown */ 1731 case e1000_media_type_unknown: 1732 e1000_check_for_link(hw); 1733 link_check = !hw->mac.get_link_status; 1734 /* FALLTHROUGH */ 1735 default: 1736 break; 1737 } 1738 1739 /* Check for thermal downshift or shutdown */ 1740 if (hw->mac.type == e1000_i350) { 1741 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1742 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1743 } 1744 1745 /* Now check for a transition */ 1746 if (link_check && (adapter->link_active == 0)) { 1747 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1748 &adapter->link_duplex); 1749 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1750 if ((adapter->link_speed != SPEED_1000) && 1751 ((hw->mac.type == e1000_82571) || 1752 (hw->mac.type == e1000_82572))) { 1753 int tarc0; 1754 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1755 tarc0 &= ~TARC_SPEED_MODE_BIT; 1756 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1757 } 1758 if (bootverbose) 1759 device_printf(dev, "Link is up %d Mbps %s\n", 1760 adapter->link_speed, 1761 ((adapter->link_duplex == FULL_DUPLEX) ? 1762 "Full Duplex" : "Half Duplex")); 1763 adapter->link_active = 1; 1764 adapter->smartspeed = 0; 1765 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1766 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && 1767 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1768 device_printf(dev, "Link: thermal downshift\n"); 1769 /* Delay Link Up for Phy update */ 1770 if (((hw->mac.type == e1000_i210) || 1771 (hw->mac.type == e1000_i211)) && 1772 (hw->phy.id == I210_I_PHY_ID)) 1773 msec_delay(I210_LINK_DELAY); 1774 /* Reset if the media type changed. */ 1775 if ((hw->dev_spec._82575.media_changed) && 1776 (adapter->hw.mac.type >= igb_mac_min)) { 1777 hw->dev_spec._82575.media_changed = false; 1778 adapter->flags |= IGB_MEDIA_RESET; 1779 em_reset(ctx); 1780 } 1781 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1782 printf("Link state changed to up\n"); 1783 } else if (!link_check && (adapter->link_active == 1)) { 1784 if_setbaudrate(ifp, 0); 1785 adapter->link_speed = 0; 1786 adapter->link_duplex = 0; 1787 if (bootverbose) 1788 device_printf(dev, "Link is Down\n"); 1789 adapter->link_active = 0; 1790 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1791 printf("link state changed to down\n"); 1792 } 1793 em_update_stats_counters(adapter); 1794 1795 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1796 } 1797 1798 /********************************************************************* 1799 * 1800 * This routine disables all traffic on the adapter by issuing a 1801 * global reset on the MAC and deallocates TX/RX buffers. 1802 * 1803 * This routine should always be called with BOTH the CORE 1804 * and TX locks. 1805 **********************************************************************/ 1806 1807 static void 1808 em_if_stop(if_ctx_t ctx) 1809 { 1810 struct adapter *adapter = iflib_get_softc(ctx); 1811 1812 INIT_DEBUGOUT("em_stop: begin"); 1813 1814 e1000_reset_hw(&adapter->hw); 1815 if (adapter->hw.mac.type >= e1000_82544) 1816 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1817 1818 e1000_led_off(&adapter->hw); 1819 e1000_cleanup_led(&adapter->hw); 1820 } 1821 1822 1823 /********************************************************************* 1824 * 1825 * Determine hardware revision. 1826 * 1827 **********************************************************************/ 1828 static void 1829 em_identify_hardware(if_ctx_t ctx) 1830 { 1831 device_t dev = iflib_get_dev(ctx); 1832 struct adapter *adapter = iflib_get_softc(ctx); 1833 1834 /* Make sure our PCI config space has the necessary stuff set */ 1835 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1836 1837 /* Save off the information about this board */ 1838 adapter->hw.vendor_id = pci_get_vendor(dev); 1839 adapter->hw.device_id = pci_get_device(dev); 1840 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1841 adapter->hw.subsystem_vendor_id = 1842 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1843 adapter->hw.subsystem_device_id = 1844 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1845 1846 /* Do Shared Code Init and Setup */ 1847 if (e1000_set_mac_type(&adapter->hw)) { 1848 device_printf(dev, "Setup init failure\n"); 1849 return; 1850 } 1851 } 1852 1853 static int 1854 em_allocate_pci_resources(if_ctx_t ctx) 1855 { 1856 struct adapter *adapter = iflib_get_softc(ctx); 1857 device_t dev = iflib_get_dev(ctx); 1858 int rid, val; 1859 1860 rid = PCIR_BAR(0); 1861 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1862 &rid, RF_ACTIVE); 1863 if (adapter->memory == NULL) { 1864 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1865 return (ENXIO); 1866 } 1867 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1868 adapter->osdep.mem_bus_space_handle = 1869 rman_get_bushandle(adapter->memory); 1870 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1871 1872 /* Only older adapters use IO mapping */ 1873 if (adapter->hw.mac.type < em_mac_min && 1874 adapter->hw.mac.type > e1000_82543) { 1875 /* Figure our where our IO BAR is ? */ 1876 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1877 val = pci_read_config(dev, rid, 4); 1878 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1879 adapter->io_rid = rid; 1880 break; 1881 } 1882 rid += 4; 1883 /* check for 64bit BAR */ 1884 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1885 rid += 4; 1886 } 1887 if (rid >= PCIR_CIS) { 1888 device_printf(dev, "Unable to locate IO BAR\n"); 1889 return (ENXIO); 1890 } 1891 adapter->ioport = bus_alloc_resource_any(dev, 1892 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1893 if (adapter->ioport == NULL) { 1894 device_printf(dev, "Unable to allocate bus resource: " 1895 "ioport\n"); 1896 return (ENXIO); 1897 } 1898 adapter->hw.io_base = 0; 1899 adapter->osdep.io_bus_space_tag = 1900 rman_get_bustag(adapter->ioport); 1901 adapter->osdep.io_bus_space_handle = 1902 rman_get_bushandle(adapter->ioport); 1903 } 1904 1905 adapter->hw.back = &adapter->osdep; 1906 1907 return (0); 1908 } 1909 1910 /********************************************************************* 1911 * 1912 * Setup the MSIX Interrupt handlers 1913 * 1914 **********************************************************************/ 1915 static int 1916 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1917 { 1918 struct adapter *adapter = iflib_get_softc(ctx); 1919 struct em_rx_queue *rx_que = adapter->rx_queues; 1920 struct em_tx_queue *tx_que = adapter->tx_queues; 1921 int error, rid, i, vector = 0, rx_vectors; 1922 char buf[16]; 1923 1924 /* First set up ring resources */ 1925 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1926 rid = vector + 1; 1927 snprintf(buf, sizeof(buf), "rxq%d", i); 1928 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1929 if (error) { 1930 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1931 adapter->rx_num_queues = i + 1; 1932 goto fail; 1933 } 1934 1935 rx_que->msix = vector; 1936 1937 /* 1938 * Set the bit to enable interrupt 1939 * in E1000_IMS -- bits 20 and 21 1940 * are for RX0 and RX1, note this has 1941 * NOTHING to do with the MSIX vector 1942 */ 1943 if (adapter->hw.mac.type == e1000_82574) { 1944 rx_que->eims = 1 << (20 + i); 1945 adapter->ims |= rx_que->eims; 1946 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1947 } else if (adapter->hw.mac.type == e1000_82575) 1948 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1949 else 1950 rx_que->eims = 1 << vector; 1951 } 1952 rx_vectors = vector; 1953 1954 vector = 0; 1955 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1956 rid = vector + 1; 1957 snprintf(buf, sizeof(buf), "txq%d", i); 1958 tx_que = &adapter->tx_queues[i]; 1959 iflib_softirq_alloc_generic(ctx, 1960 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1961 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1962 1963 tx_que->msix = (vector % adapter->tx_num_queues); 1964 1965 /* 1966 * Set the bit to enable interrupt 1967 * in E1000_IMS -- bits 22 and 23 1968 * are for TX0 and TX1, note this has 1969 * NOTHING to do with the MSIX vector 1970 */ 1971 if (adapter->hw.mac.type == e1000_82574) { 1972 tx_que->eims = 1 << (22 + i); 1973 adapter->ims |= tx_que->eims; 1974 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1975 } else if (adapter->hw.mac.type == e1000_82575) { 1976 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1977 } else { 1978 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1979 } 1980 } 1981 1982 /* Link interrupt */ 1983 rid = rx_vectors + 1; 1984 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1985 1986 if (error) { 1987 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1988 goto fail; 1989 } 1990 adapter->linkvec = rx_vectors; 1991 if (adapter->hw.mac.type < igb_mac_min) { 1992 adapter->ivars |= (8 | rx_vectors) << 16; 1993 adapter->ivars |= 0x80000000; 1994 } 1995 return (0); 1996 fail: 1997 iflib_irq_free(ctx, &adapter->irq); 1998 rx_que = adapter->rx_queues; 1999 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2000 iflib_irq_free(ctx, &rx_que->que_irq); 2001 return (error); 2002 } 2003 2004 static void 2005 igb_configure_queues(struct adapter *adapter) 2006 { 2007 struct e1000_hw *hw = &adapter->hw; 2008 struct em_rx_queue *rx_que; 2009 struct em_tx_queue *tx_que; 2010 u32 tmp, ivar = 0, newitr = 0; 2011 2012 /* First turn on RSS capability */ 2013 if (adapter->hw.mac.type != e1000_82575) 2014 E1000_WRITE_REG(hw, E1000_GPIE, 2015 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2016 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2017 2018 /* Turn on MSIX */ 2019 switch (adapter->hw.mac.type) { 2020 case e1000_82580: 2021 case e1000_i350: 2022 case e1000_i354: 2023 case e1000_i210: 2024 case e1000_i211: 2025 case e1000_vfadapt: 2026 case e1000_vfadapt_i350: 2027 /* RX entries */ 2028 for (int i = 0; i < adapter->rx_num_queues; i++) { 2029 u32 index = i >> 1; 2030 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2031 rx_que = &adapter->rx_queues[i]; 2032 if (i & 1) { 2033 ivar &= 0xFF00FFFF; 2034 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2035 } else { 2036 ivar &= 0xFFFFFF00; 2037 ivar |= rx_que->msix | E1000_IVAR_VALID; 2038 } 2039 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2040 } 2041 /* TX entries */ 2042 for (int i = 0; i < adapter->tx_num_queues; i++) { 2043 u32 index = i >> 1; 2044 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2045 tx_que = &adapter->tx_queues[i]; 2046 if (i & 1) { 2047 ivar &= 0x00FFFFFF; 2048 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2049 } else { 2050 ivar &= 0xFFFF00FF; 2051 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2052 } 2053 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2054 adapter->que_mask |= tx_que->eims; 2055 } 2056 2057 /* And for the link interrupt */ 2058 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2059 adapter->link_mask = 1 << adapter->linkvec; 2060 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2061 break; 2062 case e1000_82576: 2063 /* RX entries */ 2064 for (int i = 0; i < adapter->rx_num_queues; i++) { 2065 u32 index = i & 0x7; /* Each IVAR has two entries */ 2066 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2067 rx_que = &adapter->rx_queues[i]; 2068 if (i < 8) { 2069 ivar &= 0xFFFFFF00; 2070 ivar |= rx_que->msix | E1000_IVAR_VALID; 2071 } else { 2072 ivar &= 0xFF00FFFF; 2073 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2074 } 2075 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2076 adapter->que_mask |= rx_que->eims; 2077 } 2078 /* TX entries */ 2079 for (int i = 0; i < adapter->tx_num_queues; i++) { 2080 u32 index = i & 0x7; /* Each IVAR has two entries */ 2081 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2082 tx_que = &adapter->tx_queues[i]; 2083 if (i < 8) { 2084 ivar &= 0xFFFF00FF; 2085 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2086 } else { 2087 ivar &= 0x00FFFFFF; 2088 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2089 } 2090 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2091 adapter->que_mask |= tx_que->eims; 2092 } 2093 2094 /* And for the link interrupt */ 2095 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2096 adapter->link_mask = 1 << adapter->linkvec; 2097 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2098 break; 2099 2100 case e1000_82575: 2101 /* enable MSI-X support*/ 2102 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2103 tmp |= E1000_CTRL_EXT_PBA_CLR; 2104 /* Auto-Mask interrupts upon ICR read. */ 2105 tmp |= E1000_CTRL_EXT_EIAME; 2106 tmp |= E1000_CTRL_EXT_IRCA; 2107 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2108 2109 /* Queues */ 2110 for (int i = 0; i < adapter->rx_num_queues; i++) { 2111 rx_que = &adapter->rx_queues[i]; 2112 tmp = E1000_EICR_RX_QUEUE0 << i; 2113 tmp |= E1000_EICR_TX_QUEUE0 << i; 2114 rx_que->eims = tmp; 2115 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2116 i, rx_que->eims); 2117 adapter->que_mask |= rx_que->eims; 2118 } 2119 2120 /* Link */ 2121 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2122 E1000_EIMS_OTHER); 2123 adapter->link_mask |= E1000_EIMS_OTHER; 2124 default: 2125 break; 2126 } 2127 2128 /* Set the starting interrupt rate */ 2129 if (em_max_interrupt_rate > 0) 2130 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2131 2132 if (hw->mac.type == e1000_82575) 2133 newitr |= newitr << 16; 2134 else 2135 newitr |= E1000_EITR_CNT_IGNR; 2136 2137 for (int i = 0; i < adapter->rx_num_queues; i++) { 2138 rx_que = &adapter->rx_queues[i]; 2139 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2140 } 2141 2142 return; 2143 } 2144 2145 static void 2146 em_free_pci_resources(if_ctx_t ctx) 2147 { 2148 struct adapter *adapter = iflib_get_softc(ctx); 2149 struct em_rx_queue *que = adapter->rx_queues; 2150 device_t dev = iflib_get_dev(ctx); 2151 2152 /* Release all msix queue resources */ 2153 if (adapter->intr_type == IFLIB_INTR_MSIX) 2154 iflib_irq_free(ctx, &adapter->irq); 2155 2156 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2157 iflib_irq_free(ctx, &que->que_irq); 2158 } 2159 2160 /* First release all the interrupt resources */ 2161 if (adapter->memory != NULL) { 2162 bus_release_resource(dev, SYS_RES_MEMORY, 2163 PCIR_BAR(0), adapter->memory); 2164 adapter->memory = NULL; 2165 } 2166 2167 if (adapter->flash != NULL) { 2168 bus_release_resource(dev, SYS_RES_MEMORY, 2169 EM_FLASH, adapter->flash); 2170 adapter->flash = NULL; 2171 } 2172 if (adapter->ioport != NULL) 2173 bus_release_resource(dev, SYS_RES_IOPORT, 2174 adapter->io_rid, adapter->ioport); 2175 } 2176 2177 /* Setup MSI or MSI/X */ 2178 static int 2179 em_setup_msix(if_ctx_t ctx) 2180 { 2181 struct adapter *adapter = iflib_get_softc(ctx); 2182 2183 if (adapter->hw.mac.type == e1000_82574) { 2184 em_enable_vectors_82574(ctx); 2185 } 2186 return (0); 2187 } 2188 2189 /********************************************************************* 2190 * 2191 * Initialize the hardware to a configuration 2192 * as specified by the adapter structure. 2193 * 2194 **********************************************************************/ 2195 2196 static void 2197 lem_smartspeed(struct adapter *adapter) 2198 { 2199 u16 phy_tmp; 2200 2201 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2202 adapter->hw.mac.autoneg == 0 || 2203 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2204 return; 2205 2206 if (adapter->smartspeed == 0) { 2207 /* If Master/Slave config fault is asserted twice, 2208 * we assume back-to-back */ 2209 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2210 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2211 return; 2212 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2213 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2214 e1000_read_phy_reg(&adapter->hw, 2215 PHY_1000T_CTRL, &phy_tmp); 2216 if(phy_tmp & CR_1000T_MS_ENABLE) { 2217 phy_tmp &= ~CR_1000T_MS_ENABLE; 2218 e1000_write_phy_reg(&adapter->hw, 2219 PHY_1000T_CTRL, phy_tmp); 2220 adapter->smartspeed++; 2221 if(adapter->hw.mac.autoneg && 2222 !e1000_copper_link_autoneg(&adapter->hw) && 2223 !e1000_read_phy_reg(&adapter->hw, 2224 PHY_CONTROL, &phy_tmp)) { 2225 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2226 MII_CR_RESTART_AUTO_NEG); 2227 e1000_write_phy_reg(&adapter->hw, 2228 PHY_CONTROL, phy_tmp); 2229 } 2230 } 2231 } 2232 return; 2233 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2234 /* If still no link, perhaps using 2/3 pair cable */ 2235 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2236 phy_tmp |= CR_1000T_MS_ENABLE; 2237 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2238 if(adapter->hw.mac.autoneg && 2239 !e1000_copper_link_autoneg(&adapter->hw) && 2240 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2241 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2242 MII_CR_RESTART_AUTO_NEG); 2243 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2244 } 2245 } 2246 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2247 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2248 adapter->smartspeed = 0; 2249 } 2250 2251 /********************************************************************* 2252 * 2253 * Initialize the DMA Coalescing feature 2254 * 2255 **********************************************************************/ 2256 static void 2257 igb_init_dmac(struct adapter *adapter, u32 pba) 2258 { 2259 device_t dev = adapter->dev; 2260 struct e1000_hw *hw = &adapter->hw; 2261 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2262 u16 hwm; 2263 u16 max_frame_size; 2264 2265 if (hw->mac.type == e1000_i211) 2266 return; 2267 2268 max_frame_size = adapter->shared->isc_max_frame_size; 2269 if (hw->mac.type > e1000_82580) { 2270 2271 if (adapter->dmac == 0) { /* Disabling it */ 2272 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2273 return; 2274 } else 2275 device_printf(dev, "DMA Coalescing enabled\n"); 2276 2277 /* Set starting threshold */ 2278 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2279 2280 hwm = 64 * pba - max_frame_size / 16; 2281 if (hwm < 64 * (pba - 6)) 2282 hwm = 64 * (pba - 6); 2283 reg = E1000_READ_REG(hw, E1000_FCRTC); 2284 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2285 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2286 & E1000_FCRTC_RTH_COAL_MASK); 2287 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2288 2289 2290 dmac = pba - max_frame_size / 512; 2291 if (dmac < pba - 10) 2292 dmac = pba - 10; 2293 reg = E1000_READ_REG(hw, E1000_DMACR); 2294 reg &= ~E1000_DMACR_DMACTHR_MASK; 2295 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2296 & E1000_DMACR_DMACTHR_MASK); 2297 2298 /* transition to L0x or L1 if available..*/ 2299 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2300 2301 /* Check if status is 2.5Gb backplane connection 2302 * before configuration of watchdog timer, which is 2303 * in msec values in 12.8usec intervals 2304 * watchdog timer= msec values in 32usec intervals 2305 * for non 2.5Gb connection 2306 */ 2307 if (hw->mac.type == e1000_i354) { 2308 int status = E1000_READ_REG(hw, E1000_STATUS); 2309 if ((status & E1000_STATUS_2P5_SKU) && 2310 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2311 reg |= ((adapter->dmac * 5) >> 6); 2312 else 2313 reg |= (adapter->dmac >> 5); 2314 } else { 2315 reg |= (adapter->dmac >> 5); 2316 } 2317 2318 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2319 2320 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2321 2322 /* Set the interval before transition */ 2323 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2324 if (hw->mac.type == e1000_i350) 2325 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2326 /* 2327 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2328 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2329 */ 2330 if (hw->mac.type == e1000_i354) { 2331 int status = E1000_READ_REG(hw, E1000_STATUS); 2332 if ((status & E1000_STATUS_2P5_SKU) && 2333 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2334 reg |= 0xA; 2335 else 2336 reg |= 0x4; 2337 } else { 2338 reg |= 0x4; 2339 } 2340 2341 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2342 2343 /* free space in tx packet buffer to wake from DMA coal */ 2344 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2345 (2 * max_frame_size)) >> 6); 2346 2347 /* make low power state decision controlled by DMA coal */ 2348 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2349 reg &= ~E1000_PCIEMISC_LX_DECISION; 2350 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2351 2352 } else if (hw->mac.type == e1000_82580) { 2353 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2354 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2355 reg & ~E1000_PCIEMISC_LX_DECISION); 2356 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2357 } 2358 } 2359 2360 static void 2361 em_reset(if_ctx_t ctx) 2362 { 2363 device_t dev = iflib_get_dev(ctx); 2364 struct adapter *adapter = iflib_get_softc(ctx); 2365 struct ifnet *ifp = iflib_get_ifp(ctx); 2366 struct e1000_hw *hw = &adapter->hw; 2367 u16 rx_buffer_size; 2368 u32 pba; 2369 2370 INIT_DEBUGOUT("em_reset: begin"); 2371 /* Let the firmware know the OS is in control */ 2372 em_get_hw_control(adapter); 2373 2374 /* Set up smart power down as default off on newer adapters. */ 2375 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2376 hw->mac.type == e1000_82572)) { 2377 u16 phy_tmp = 0; 2378 2379 /* Speed up time to link by disabling smart power down. */ 2380 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2381 phy_tmp &= ~IGP02E1000_PM_SPD; 2382 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2383 } 2384 2385 /* 2386 * Packet Buffer Allocation (PBA) 2387 * Writing PBA sets the receive portion of the buffer 2388 * the remainder is used for the transmit buffer. 2389 */ 2390 switch (hw->mac.type) { 2391 /* Total Packet Buffer on these is 48K */ 2392 case e1000_82571: 2393 case e1000_82572: 2394 case e1000_80003es2lan: 2395 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2396 break; 2397 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2398 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2399 break; 2400 case e1000_82574: 2401 case e1000_82583: 2402 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2403 break; 2404 case e1000_ich8lan: 2405 pba = E1000_PBA_8K; 2406 break; 2407 case e1000_ich9lan: 2408 case e1000_ich10lan: 2409 /* Boost Receive side for jumbo frames */ 2410 if (adapter->hw.mac.max_frame_size > 4096) 2411 pba = E1000_PBA_14K; 2412 else 2413 pba = E1000_PBA_10K; 2414 break; 2415 case e1000_pchlan: 2416 case e1000_pch2lan: 2417 case e1000_pch_lpt: 2418 case e1000_pch_spt: 2419 pba = E1000_PBA_26K; 2420 break; 2421 case e1000_82575: 2422 pba = E1000_PBA_32K; 2423 break; 2424 case e1000_82576: 2425 case e1000_vfadapt: 2426 pba = E1000_READ_REG(hw, E1000_RXPBS); 2427 pba &= E1000_RXPBS_SIZE_MASK_82576; 2428 break; 2429 case e1000_82580: 2430 case e1000_i350: 2431 case e1000_i354: 2432 case e1000_vfadapt_i350: 2433 pba = E1000_READ_REG(hw, E1000_RXPBS); 2434 pba = e1000_rxpbs_adjust_82580(pba); 2435 break; 2436 case e1000_i210: 2437 case e1000_i211: 2438 pba = E1000_PBA_34K; 2439 break; 2440 default: 2441 if (adapter->hw.mac.max_frame_size > 8192) 2442 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2443 else 2444 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2445 } 2446 2447 /* Special needs in case of Jumbo frames */ 2448 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2449 u32 tx_space, min_tx, min_rx; 2450 pba = E1000_READ_REG(hw, E1000_PBA); 2451 tx_space = pba >> 16; 2452 pba &= 0xffff; 2453 min_tx = (adapter->hw.mac.max_frame_size + 2454 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2455 min_tx = roundup2(min_tx, 1024); 2456 min_tx >>= 10; 2457 min_rx = adapter->hw.mac.max_frame_size; 2458 min_rx = roundup2(min_rx, 1024); 2459 min_rx >>= 10; 2460 if (tx_space < min_tx && 2461 ((min_tx - tx_space) < pba)) { 2462 pba = pba - (min_tx - tx_space); 2463 /* 2464 * if short on rx space, rx wins 2465 * and must trump tx adjustment 2466 */ 2467 if (pba < min_rx) 2468 pba = min_rx; 2469 } 2470 E1000_WRITE_REG(hw, E1000_PBA, pba); 2471 } 2472 2473 if (hw->mac.type < igb_mac_min) 2474 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2475 2476 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2477 2478 /* 2479 * These parameters control the automatic generation (Tx) and 2480 * response (Rx) to Ethernet PAUSE frames. 2481 * - High water mark should allow for at least two frames to be 2482 * received after sending an XOFF. 2483 * - Low water mark works best when it is very near the high water mark. 2484 * This allows the receiver to restart by sending XON when it has 2485 * drained a bit. Here we use an arbitrary value of 1500 which will 2486 * restart after one full frame is pulled from the buffer. There 2487 * could be several smaller frames in the buffer and if so they will 2488 * not trigger the XON until their total number reduces the buffer 2489 * by 1500. 2490 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2491 */ 2492 rx_buffer_size = (pba & 0xffff) << 10; 2493 hw->fc.high_water = rx_buffer_size - 2494 roundup2(adapter->hw.mac.max_frame_size, 1024); 2495 hw->fc.low_water = hw->fc.high_water - 1500; 2496 2497 if (adapter->fc) /* locally set flow control value? */ 2498 hw->fc.requested_mode = adapter->fc; 2499 else 2500 hw->fc.requested_mode = e1000_fc_full; 2501 2502 if (hw->mac.type == e1000_80003es2lan) 2503 hw->fc.pause_time = 0xFFFF; 2504 else 2505 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2506 2507 hw->fc.send_xon = TRUE; 2508 2509 /* Device specific overrides/settings */ 2510 switch (hw->mac.type) { 2511 case e1000_pchlan: 2512 /* Workaround: no TX flow ctrl for PCH */ 2513 hw->fc.requested_mode = e1000_fc_rx_pause; 2514 hw->fc.pause_time = 0xFFFF; /* override */ 2515 if (if_getmtu(ifp) > ETHERMTU) { 2516 hw->fc.high_water = 0x3500; 2517 hw->fc.low_water = 0x1500; 2518 } else { 2519 hw->fc.high_water = 0x5000; 2520 hw->fc.low_water = 0x3000; 2521 } 2522 hw->fc.refresh_time = 0x1000; 2523 break; 2524 case e1000_pch2lan: 2525 case e1000_pch_lpt: 2526 case e1000_pch_spt: 2527 hw->fc.high_water = 0x5C20; 2528 hw->fc.low_water = 0x5048; 2529 hw->fc.pause_time = 0x0650; 2530 hw->fc.refresh_time = 0x0400; 2531 /* Jumbos need adjusted PBA */ 2532 if (if_getmtu(ifp) > ETHERMTU) 2533 E1000_WRITE_REG(hw, E1000_PBA, 12); 2534 else 2535 E1000_WRITE_REG(hw, E1000_PBA, 26); 2536 break; 2537 case e1000_82575: 2538 case e1000_82576: 2539 /* 8-byte granularity */ 2540 hw->fc.low_water = hw->fc.high_water - 8; 2541 break; 2542 case e1000_82580: 2543 case e1000_i350: 2544 case e1000_i354: 2545 case e1000_i210: 2546 case e1000_i211: 2547 case e1000_vfadapt: 2548 case e1000_vfadapt_i350: 2549 /* 16-byte granularity */ 2550 hw->fc.low_water = hw->fc.high_water - 16; 2551 break; 2552 case e1000_ich9lan: 2553 case e1000_ich10lan: 2554 if (if_getmtu(ifp) > ETHERMTU) { 2555 hw->fc.high_water = 0x2800; 2556 hw->fc.low_water = hw->fc.high_water - 8; 2557 break; 2558 } 2559 /* FALLTHROUGH */ 2560 default: 2561 if (hw->mac.type == e1000_80003es2lan) 2562 hw->fc.pause_time = 0xFFFF; 2563 break; 2564 } 2565 2566 /* Issue a global reset */ 2567 e1000_reset_hw(hw); 2568 if (adapter->hw.mac.type >= igb_mac_min) { 2569 E1000_WRITE_REG(hw, E1000_WUC, 0); 2570 } else { 2571 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2572 em_disable_aspm(adapter); 2573 } 2574 if (adapter->flags & IGB_MEDIA_RESET) { 2575 e1000_setup_init_funcs(hw, TRUE); 2576 e1000_get_bus_info(hw); 2577 adapter->flags &= ~IGB_MEDIA_RESET; 2578 } 2579 /* and a re-init */ 2580 if (e1000_init_hw(hw) < 0) { 2581 device_printf(dev, "Hardware Initialization Failed\n"); 2582 return; 2583 } 2584 if (adapter->hw.mac.type >= igb_mac_min) 2585 igb_init_dmac(adapter, pba); 2586 2587 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2588 e1000_get_phy_info(hw); 2589 e1000_check_for_link(hw); 2590 } 2591 2592 #define RSSKEYLEN 10 2593 static void 2594 em_initialize_rss_mapping(struct adapter *adapter) 2595 { 2596 uint8_t rss_key[4 * RSSKEYLEN]; 2597 uint32_t reta = 0; 2598 struct e1000_hw *hw = &adapter->hw; 2599 int i; 2600 2601 /* 2602 * Configure RSS key 2603 */ 2604 arc4rand(rss_key, sizeof(rss_key), 0); 2605 for (i = 0; i < RSSKEYLEN; ++i) { 2606 uint32_t rssrk = 0; 2607 2608 rssrk = EM_RSSRK_VAL(rss_key, i); 2609 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2610 } 2611 2612 /* 2613 * Configure RSS redirect table in following fashion: 2614 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2615 */ 2616 for (i = 0; i < sizeof(reta); ++i) { 2617 uint32_t q; 2618 2619 q = (i % adapter->rx_num_queues) << 7; 2620 reta |= q << (8 * i); 2621 } 2622 2623 for (i = 0; i < 32; ++i) 2624 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2625 2626 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2627 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2628 E1000_MRQC_RSS_FIELD_IPV4 | 2629 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2630 E1000_MRQC_RSS_FIELD_IPV6_EX | 2631 E1000_MRQC_RSS_FIELD_IPV6); 2632 2633 } 2634 2635 static void 2636 igb_initialize_rss_mapping(struct adapter *adapter) 2637 { 2638 struct e1000_hw *hw = &adapter->hw; 2639 int i; 2640 int queue_id; 2641 u32 reta; 2642 u32 rss_key[10], mrqc, shift = 0; 2643 2644 /* XXX? */ 2645 if (adapter->hw.mac.type == e1000_82575) 2646 shift = 6; 2647 2648 /* 2649 * The redirection table controls which destination 2650 * queue each bucket redirects traffic to. 2651 * Each DWORD represents four queues, with the LSB 2652 * being the first queue in the DWORD. 2653 * 2654 * This just allocates buckets to queues using round-robin 2655 * allocation. 2656 * 2657 * NOTE: It Just Happens to line up with the default 2658 * RSS allocation method. 2659 */ 2660 2661 /* Warning FM follows */ 2662 reta = 0; 2663 for (i = 0; i < 128; i++) { 2664 #ifdef RSS 2665 queue_id = rss_get_indirection_to_bucket(i); 2666 /* 2667 * If we have more queues than buckets, we'll 2668 * end up mapping buckets to a subset of the 2669 * queues. 2670 * 2671 * If we have more buckets than queues, we'll 2672 * end up instead assigning multiple buckets 2673 * to queues. 2674 * 2675 * Both are suboptimal, but we need to handle 2676 * the case so we don't go out of bounds 2677 * indexing arrays and such. 2678 */ 2679 queue_id = queue_id % adapter->rx_num_queues; 2680 #else 2681 queue_id = (i % adapter->rx_num_queues); 2682 #endif 2683 /* Adjust if required */ 2684 queue_id = queue_id << shift; 2685 2686 /* 2687 * The low 8 bits are for hash value (n+0); 2688 * The next 8 bits are for hash value (n+1), etc. 2689 */ 2690 reta = reta >> 8; 2691 reta = reta | ( ((uint32_t) queue_id) << 24); 2692 if ((i & 3) == 3) { 2693 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2694 reta = 0; 2695 } 2696 } 2697 2698 /* Now fill in hash table */ 2699 2700 /* 2701 * MRQC: Multiple Receive Queues Command 2702 * Set queuing to RSS control, number depends on the device. 2703 */ 2704 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2705 2706 #ifdef RSS 2707 /* XXX ew typecasting */ 2708 rss_getkey((uint8_t *) &rss_key); 2709 #else 2710 arc4rand(&rss_key, sizeof(rss_key), 0); 2711 #endif 2712 for (i = 0; i < 10; i++) 2713 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2714 2715 /* 2716 * Configure the RSS fields to hash upon. 2717 */ 2718 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2719 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2720 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2721 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2722 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2723 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2724 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2725 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2726 2727 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2728 } 2729 2730 /********************************************************************* 2731 * 2732 * Setup networking device structure and register an interface. 2733 * 2734 **********************************************************************/ 2735 static int 2736 em_setup_interface(if_ctx_t ctx) 2737 { 2738 struct ifnet *ifp = iflib_get_ifp(ctx); 2739 struct adapter *adapter = iflib_get_softc(ctx); 2740 if_softc_ctx_t scctx = adapter->shared; 2741 uint64_t cap = 0; 2742 2743 INIT_DEBUGOUT("em_setup_interface: begin"); 2744 2745 /* TSO parameters */ 2746 if_sethwtsomax(ifp, IP_MAXPACKET); 2747 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2748 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2749 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2750 2751 /* Single Queue */ 2752 if (adapter->tx_num_queues == 1) { 2753 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2754 if_setsendqready(ifp); 2755 } 2756 2757 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2758 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2759 2760 /* 2761 * Tell the upper layer(s) we 2762 * support full VLAN capability 2763 */ 2764 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2765 if_setcapabilitiesbit(ifp, cap, 0); 2766 2767 /* 2768 * Don't turn this on by default, if vlans are 2769 * created on another pseudo device (eg. lagg) 2770 * then vlan events are not passed thru, breaking 2771 * operation, but with HW FILTER off it works. If 2772 * using vlans directly on the em driver you can 2773 * enable this and get full hardware tag filtering. 2774 */ 2775 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2776 2777 /* Enable only WOL MAGIC by default */ 2778 if (adapter->wol) { 2779 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2780 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2781 } else { 2782 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2783 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2784 } 2785 2786 /* 2787 * Specify the media types supported by this adapter and register 2788 * callbacks to update media and link information 2789 */ 2790 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2791 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2792 u_char fiber_type = IFM_1000_SX; /* default type */ 2793 2794 if (adapter->hw.mac.type == e1000_82545) 2795 fiber_type = IFM_1000_LX; 2796 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2797 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2798 } else { 2799 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2800 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2801 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2802 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2803 if (adapter->hw.phy.type != e1000_phy_ife) { 2804 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2805 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2806 } 2807 } 2808 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2809 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2810 return (0); 2811 } 2812 2813 static int 2814 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2815 { 2816 struct adapter *adapter = iflib_get_softc(ctx); 2817 if_softc_ctx_t scctx = adapter->shared; 2818 int error = E1000_SUCCESS; 2819 struct em_tx_queue *que; 2820 int i, j; 2821 2822 MPASS(adapter->tx_num_queues > 0); 2823 MPASS(adapter->tx_num_queues == ntxqsets); 2824 2825 /* First allocate the top level queue structs */ 2826 if (!(adapter->tx_queues = 2827 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2828 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2829 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2830 return(ENOMEM); 2831 } 2832 2833 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2834 /* Set up some basics */ 2835 2836 struct tx_ring *txr = &que->txr; 2837 txr->adapter = que->adapter = adapter; 2838 que->me = txr->me = i; 2839 2840 /* Allocate report status array */ 2841 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2842 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2843 error = ENOMEM; 2844 goto fail; 2845 } 2846 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2847 txr->tx_rsq[j] = QIDX_INVALID; 2848 /* get the virtual and physical address of the hardware queues */ 2849 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2850 txr->tx_paddr = paddrs[i*ntxqs]; 2851 } 2852 2853 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2854 return (0); 2855 fail: 2856 em_if_queues_free(ctx); 2857 return (error); 2858 } 2859 2860 static int 2861 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2862 { 2863 struct adapter *adapter = iflib_get_softc(ctx); 2864 int error = E1000_SUCCESS; 2865 struct em_rx_queue *que; 2866 int i; 2867 2868 MPASS(adapter->rx_num_queues > 0); 2869 MPASS(adapter->rx_num_queues == nrxqsets); 2870 2871 /* First allocate the top level queue structs */ 2872 if (!(adapter->rx_queues = 2873 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2874 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2875 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2876 error = ENOMEM; 2877 goto fail; 2878 } 2879 2880 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2881 /* Set up some basics */ 2882 struct rx_ring *rxr = &que->rxr; 2883 rxr->adapter = que->adapter = adapter; 2884 rxr->que = que; 2885 que->me = rxr->me = i; 2886 2887 /* get the virtual and physical address of the hardware queues */ 2888 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2889 rxr->rx_paddr = paddrs[i*nrxqs]; 2890 } 2891 2892 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2893 2894 return (0); 2895 fail: 2896 em_if_queues_free(ctx); 2897 return (error); 2898 } 2899 2900 static void 2901 em_if_queues_free(if_ctx_t ctx) 2902 { 2903 struct adapter *adapter = iflib_get_softc(ctx); 2904 struct em_tx_queue *tx_que = adapter->tx_queues; 2905 struct em_rx_queue *rx_que = adapter->rx_queues; 2906 2907 if (tx_que != NULL) { 2908 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2909 struct tx_ring *txr = &tx_que->txr; 2910 if (txr->tx_rsq == NULL) 2911 break; 2912 2913 free(txr->tx_rsq, M_DEVBUF); 2914 txr->tx_rsq = NULL; 2915 } 2916 free(adapter->tx_queues, M_DEVBUF); 2917 adapter->tx_queues = NULL; 2918 } 2919 2920 if (rx_que != NULL) { 2921 free(adapter->rx_queues, M_DEVBUF); 2922 adapter->rx_queues = NULL; 2923 } 2924 2925 em_release_hw_control(adapter); 2926 2927 if (adapter->mta != NULL) { 2928 free(adapter->mta, M_DEVBUF); 2929 } 2930 } 2931 2932 /********************************************************************* 2933 * 2934 * Enable transmit unit. 2935 * 2936 **********************************************************************/ 2937 static void 2938 em_initialize_transmit_unit(if_ctx_t ctx) 2939 { 2940 struct adapter *adapter = iflib_get_softc(ctx); 2941 if_softc_ctx_t scctx = adapter->shared; 2942 struct em_tx_queue *que; 2943 struct tx_ring *txr; 2944 struct e1000_hw *hw = &adapter->hw; 2945 u32 tctl, txdctl = 0, tarc, tipg = 0; 2946 2947 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2948 2949 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2950 u64 bus_addr; 2951 caddr_t offp, endp; 2952 2953 que = &adapter->tx_queues[i]; 2954 txr = &que->txr; 2955 bus_addr = txr->tx_paddr; 2956 2957 /* Clear checksum offload context. */ 2958 offp = (caddr_t)&txr->csum_flags; 2959 endp = (caddr_t)(txr + 1); 2960 bzero(offp, endp - offp); 2961 2962 /* Base and Len of TX Ring */ 2963 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2964 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2965 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2966 (u32)(bus_addr >> 32)); 2967 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2968 (u32)bus_addr); 2969 /* Init the HEAD/TAIL indices */ 2970 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2971 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2972 2973 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2974 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2975 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2976 2977 txdctl = 0; /* clear txdctl */ 2978 txdctl |= 0x1f; /* PTHRESH */ 2979 txdctl |= 1 << 8; /* HTHRESH */ 2980 txdctl |= 1 << 16;/* WTHRESH */ 2981 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2982 txdctl |= E1000_TXDCTL_GRAN; 2983 txdctl |= 1 << 25; /* LWTHRESH */ 2984 2985 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2986 } 2987 2988 /* Set the default values for the Tx Inter Packet Gap timer */ 2989 switch (adapter->hw.mac.type) { 2990 case e1000_80003es2lan: 2991 tipg = DEFAULT_82543_TIPG_IPGR1; 2992 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2993 E1000_TIPG_IPGR2_SHIFT; 2994 break; 2995 case e1000_82542: 2996 tipg = DEFAULT_82542_TIPG_IPGT; 2997 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2998 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2999 break; 3000 default: 3001 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3002 (adapter->hw.phy.media_type == 3003 e1000_media_type_internal_serdes)) 3004 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3005 else 3006 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3007 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3008 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3009 } 3010 3011 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3012 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3013 3014 if(adapter->hw.mac.type >= e1000_82540) 3015 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3016 adapter->tx_abs_int_delay.value); 3017 3018 if ((adapter->hw.mac.type == e1000_82571) || 3019 (adapter->hw.mac.type == e1000_82572)) { 3020 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3021 tarc |= TARC_SPEED_MODE_BIT; 3022 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3023 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3024 /* errata: program both queues to unweighted RR */ 3025 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3026 tarc |= 1; 3027 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3028 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3029 tarc |= 1; 3030 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3031 } else if (adapter->hw.mac.type == e1000_82574) { 3032 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3033 tarc |= TARC_ERRATA_BIT; 3034 if ( adapter->tx_num_queues > 1) { 3035 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3036 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3037 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3038 } else 3039 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3040 } 3041 3042 if (adapter->tx_int_delay.value > 0) 3043 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3044 3045 /* Program the Transmit Control Register */ 3046 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3047 tctl &= ~E1000_TCTL_CT; 3048 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3049 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3050 3051 if (adapter->hw.mac.type >= e1000_82571) 3052 tctl |= E1000_TCTL_MULR; 3053 3054 /* This write will effectively turn on the transmit unit. */ 3055 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3056 3057 if (hw->mac.type == e1000_pch_spt) { 3058 u32 reg; 3059 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3060 reg |= E1000_RCTL_RDMTS_HEX; 3061 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3062 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3063 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 3064 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3065 } 3066 } 3067 3068 /********************************************************************* 3069 * 3070 * Enable receive unit. 3071 * 3072 **********************************************************************/ 3073 3074 static void 3075 em_initialize_receive_unit(if_ctx_t ctx) 3076 { 3077 struct adapter *adapter = iflib_get_softc(ctx); 3078 if_softc_ctx_t scctx = adapter->shared; 3079 struct ifnet *ifp = iflib_get_ifp(ctx); 3080 struct e1000_hw *hw = &adapter->hw; 3081 struct em_rx_queue *que; 3082 int i; 3083 u32 rctl, rxcsum, rfctl; 3084 3085 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3086 3087 /* 3088 * Make sure receives are disabled while setting 3089 * up the descriptor ring 3090 */ 3091 rctl = E1000_READ_REG(hw, E1000_RCTL); 3092 /* Do not disable if ever enabled on this hardware */ 3093 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3094 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3095 3096 /* Setup the Receive Control Register */ 3097 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3098 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3099 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3100 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3101 3102 /* Do not store bad packets */ 3103 rctl &= ~E1000_RCTL_SBP; 3104 3105 /* Enable Long Packet receive */ 3106 if (if_getmtu(ifp) > ETHERMTU) 3107 rctl |= E1000_RCTL_LPE; 3108 else 3109 rctl &= ~E1000_RCTL_LPE; 3110 3111 /* Strip the CRC */ 3112 if (!em_disable_crc_stripping) 3113 rctl |= E1000_RCTL_SECRC; 3114 3115 if (adapter->hw.mac.type >= e1000_82540) { 3116 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3117 adapter->rx_abs_int_delay.value); 3118 3119 /* 3120 * Set the interrupt throttling rate. Value is calculated 3121 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3122 */ 3123 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3124 } 3125 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3126 adapter->rx_int_delay.value); 3127 3128 /* Use extended rx descriptor formats */ 3129 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3130 rfctl |= E1000_RFCTL_EXTEN; 3131 /* 3132 * When using MSIX interrupts we need to throttle 3133 * using the EITR register (82574 only) 3134 */ 3135 if (hw->mac.type == e1000_82574) { 3136 for (int i = 0; i < 4; i++) 3137 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3138 DEFAULT_ITR); 3139 /* Disable accelerated acknowledge */ 3140 rfctl |= E1000_RFCTL_ACK_DIS; 3141 } 3142 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3143 3144 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3145 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3146 adapter->hw.mac.type >= e1000_82543) { 3147 if (adapter->tx_num_queues > 1) { 3148 if (adapter->hw.mac.type >= igb_mac_min) { 3149 rxcsum |= E1000_RXCSUM_PCSD; 3150 if (hw->mac.type != e1000_82575) 3151 rxcsum |= E1000_RXCSUM_CRCOFL; 3152 } else 3153 rxcsum |= E1000_RXCSUM_TUOFL | 3154 E1000_RXCSUM_IPOFL | 3155 E1000_RXCSUM_PCSD; 3156 } else { 3157 if (adapter->hw.mac.type >= igb_mac_min) 3158 rxcsum |= E1000_RXCSUM_IPPCSE; 3159 else 3160 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3161 if (adapter->hw.mac.type > e1000_82575) 3162 rxcsum |= E1000_RXCSUM_CRCOFL; 3163 } 3164 } else 3165 rxcsum &= ~E1000_RXCSUM_TUOFL; 3166 3167 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3168 3169 if (adapter->rx_num_queues > 1) { 3170 if (adapter->hw.mac.type >= igb_mac_min) 3171 igb_initialize_rss_mapping(adapter); 3172 else 3173 em_initialize_rss_mapping(adapter); 3174 } 3175 3176 /* 3177 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3178 * long latencies are observed, like Lenovo X60. This 3179 * change eliminates the problem, but since having positive 3180 * values in RDTR is a known source of problems on other 3181 * platforms another solution is being sought. 3182 */ 3183 if (hw->mac.type == e1000_82573) 3184 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3185 3186 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3187 struct rx_ring *rxr = &que->rxr; 3188 /* Setup the Base and Length of the Rx Descriptor Ring */ 3189 u64 bus_addr = rxr->rx_paddr; 3190 #if 0 3191 u32 rdt = adapter->rx_num_queues -1; /* default */ 3192 #endif 3193 3194 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3195 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3196 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3197 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3198 /* Setup the Head and Tail Descriptor Pointers */ 3199 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3200 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3201 } 3202 3203 /* 3204 * Set PTHRESH for improved jumbo performance 3205 * According to 10.2.5.11 of Intel 82574 Datasheet, 3206 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3207 * Only write to RXDCTL(1) if there is a need for different 3208 * settings. 3209 */ 3210 3211 if (((adapter->hw.mac.type == e1000_ich9lan) || 3212 (adapter->hw.mac.type == e1000_pch2lan) || 3213 (adapter->hw.mac.type == e1000_ich10lan)) && 3214 (if_getmtu(ifp) > ETHERMTU)) { 3215 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3216 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3217 } else if (adapter->hw.mac.type == e1000_82574) { 3218 for (int i = 0; i < adapter->rx_num_queues; i++) { 3219 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3220 rxdctl |= 0x20; /* PTHRESH */ 3221 rxdctl |= 4 << 8; /* HTHRESH */ 3222 rxdctl |= 4 << 16;/* WTHRESH */ 3223 rxdctl |= 1 << 24; /* Switch to granularity */ 3224 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3225 } 3226 } else if (adapter->hw.mac.type >= igb_mac_min) { 3227 u32 psize, srrctl = 0; 3228 3229 if (if_getmtu(ifp) > ETHERMTU) { 3230 /* Set maximum packet len */ 3231 if (adapter->rx_mbuf_sz <= 4096) { 3232 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3233 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3234 } else if (adapter->rx_mbuf_sz > 4096) { 3235 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3236 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3237 } 3238 psize = scctx->isc_max_frame_size; 3239 /* are we on a vlan? */ 3240 if (ifp->if_vlantrunk != NULL) 3241 psize += VLAN_TAG_SIZE; 3242 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3243 } else { 3244 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3245 rctl |= E1000_RCTL_SZ_2048; 3246 } 3247 3248 /* 3249 * If TX flow control is disabled and there's >1 queue defined, 3250 * enable DROP. 3251 * 3252 * This drops frames rather than hanging the RX MAC for all queues. 3253 */ 3254 if ((adapter->rx_num_queues > 1) && 3255 (adapter->fc == e1000_fc_none || 3256 adapter->fc == e1000_fc_rx_pause)) { 3257 srrctl |= E1000_SRRCTL_DROP_EN; 3258 } 3259 /* Setup the Base and Length of the Rx Descriptor Rings */ 3260 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3261 struct rx_ring *rxr = &que->rxr; 3262 u64 bus_addr = rxr->rx_paddr; 3263 u32 rxdctl; 3264 3265 #ifdef notyet 3266 /* Configure for header split? -- ignore for now */ 3267 rxr->hdr_split = igb_header_split; 3268 #else 3269 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3270 #endif 3271 3272 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3273 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3274 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3275 (uint32_t)(bus_addr >> 32)); 3276 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3277 (uint32_t)bus_addr); 3278 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3279 /* Enable this Queue */ 3280 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3281 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3282 rxdctl &= 0xFFF00000; 3283 rxdctl |= IGB_RX_PTHRESH; 3284 rxdctl |= IGB_RX_HTHRESH << 8; 3285 rxdctl |= IGB_RX_WTHRESH << 16; 3286 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3287 } 3288 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3289 if (if_getmtu(ifp) > ETHERMTU) 3290 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3291 else 3292 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3293 } 3294 3295 /* Make sure VLAN Filters are off */ 3296 rctl &= ~E1000_RCTL_VFE; 3297 3298 if (adapter->hw.mac.type < igb_mac_min) { 3299 if (adapter->rx_mbuf_sz == MCLBYTES) 3300 rctl |= E1000_RCTL_SZ_2048; 3301 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3302 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3303 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3304 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3305 3306 /* ensure we clear use DTYPE of 00 here */ 3307 rctl &= ~0x00000C00; 3308 } 3309 3310 /* Write out the settings */ 3311 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3312 3313 return; 3314 } 3315 3316 static void 3317 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3318 { 3319 struct adapter *adapter = iflib_get_softc(ctx); 3320 u32 index, bit; 3321 3322 index = (vtag >> 5) & 0x7F; 3323 bit = vtag & 0x1F; 3324 adapter->shadow_vfta[index] |= (1 << bit); 3325 ++adapter->num_vlans; 3326 } 3327 3328 static void 3329 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3330 { 3331 struct adapter *adapter = iflib_get_softc(ctx); 3332 u32 index, bit; 3333 3334 index = (vtag >> 5) & 0x7F; 3335 bit = vtag & 0x1F; 3336 adapter->shadow_vfta[index] &= ~(1 << bit); 3337 --adapter->num_vlans; 3338 } 3339 3340 static void 3341 em_setup_vlan_hw_support(struct adapter *adapter) 3342 { 3343 struct e1000_hw *hw = &adapter->hw; 3344 u32 reg; 3345 3346 /* 3347 * We get here thru init_locked, meaning 3348 * a soft reset, this has already cleared 3349 * the VFTA and other state, so if there 3350 * have been no vlan's registered do nothing. 3351 */ 3352 if (adapter->num_vlans == 0) 3353 return; 3354 3355 /* 3356 * A soft reset zero's out the VFTA, so 3357 * we need to repopulate it now. 3358 */ 3359 for (int i = 0; i < EM_VFTA_SIZE; i++) 3360 if (adapter->shadow_vfta[i] != 0) 3361 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3362 i, adapter->shadow_vfta[i]); 3363 3364 reg = E1000_READ_REG(hw, E1000_CTRL); 3365 reg |= E1000_CTRL_VME; 3366 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3367 3368 /* Enable the Filter Table */ 3369 reg = E1000_READ_REG(hw, E1000_RCTL); 3370 reg &= ~E1000_RCTL_CFIEN; 3371 reg |= E1000_RCTL_VFE; 3372 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3373 } 3374 3375 static void 3376 em_if_enable_intr(if_ctx_t ctx) 3377 { 3378 struct adapter *adapter = iflib_get_softc(ctx); 3379 struct e1000_hw *hw = &adapter->hw; 3380 u32 ims_mask = IMS_ENABLE_MASK; 3381 3382 if (hw->mac.type == e1000_82574) { 3383 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3384 ims_mask |= adapter->ims; 3385 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3386 u32 mask = (adapter->que_mask | adapter->link_mask); 3387 3388 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3389 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3390 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3391 ims_mask = E1000_IMS_LSC; 3392 } 3393 3394 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3395 } 3396 3397 static void 3398 em_if_disable_intr(if_ctx_t ctx) 3399 { 3400 struct adapter *adapter = iflib_get_softc(ctx); 3401 struct e1000_hw *hw = &adapter->hw; 3402 3403 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3404 if (hw->mac.type >= igb_mac_min) 3405 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3406 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3407 } 3408 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3409 } 3410 3411 /* 3412 * Bit of a misnomer, what this really means is 3413 * to enable OS management of the system... aka 3414 * to disable special hardware management features 3415 */ 3416 static void 3417 em_init_manageability(struct adapter *adapter) 3418 { 3419 /* A shared code workaround */ 3420 #define E1000_82542_MANC2H E1000_MANC2H 3421 if (adapter->has_manage) { 3422 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3423 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3424 3425 /* disable hardware interception of ARP */ 3426 manc &= ~(E1000_MANC_ARP_EN); 3427 3428 /* enable receiving management packets to the host */ 3429 manc |= E1000_MANC_EN_MNG2HOST; 3430 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3431 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3432 manc2h |= E1000_MNG2HOST_PORT_623; 3433 manc2h |= E1000_MNG2HOST_PORT_664; 3434 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3435 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3436 } 3437 } 3438 3439 /* 3440 * Give control back to hardware management 3441 * controller if there is one. 3442 */ 3443 static void 3444 em_release_manageability(struct adapter *adapter) 3445 { 3446 if (adapter->has_manage) { 3447 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3448 3449 /* re-enable hardware interception of ARP */ 3450 manc |= E1000_MANC_ARP_EN; 3451 manc &= ~E1000_MANC_EN_MNG2HOST; 3452 3453 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3454 } 3455 } 3456 3457 /* 3458 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3459 * For ASF and Pass Through versions of f/w this means 3460 * that the driver is loaded. For AMT version type f/w 3461 * this means that the network i/f is open. 3462 */ 3463 static void 3464 em_get_hw_control(struct adapter *adapter) 3465 { 3466 u32 ctrl_ext, swsm; 3467 3468 if (adapter->vf_ifp) 3469 return; 3470 3471 if (adapter->hw.mac.type == e1000_82573) { 3472 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3473 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3474 swsm | E1000_SWSM_DRV_LOAD); 3475 return; 3476 } 3477 /* else */ 3478 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3479 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3480 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3481 } 3482 3483 /* 3484 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3485 * For ASF and Pass Through versions of f/w this means that 3486 * the driver is no longer loaded. For AMT versions of the 3487 * f/w this means that the network i/f is closed. 3488 */ 3489 static void 3490 em_release_hw_control(struct adapter *adapter) 3491 { 3492 u32 ctrl_ext, swsm; 3493 3494 if (!adapter->has_manage) 3495 return; 3496 3497 if (adapter->hw.mac.type == e1000_82573) { 3498 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3499 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3500 swsm & ~E1000_SWSM_DRV_LOAD); 3501 return; 3502 } 3503 /* else */ 3504 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3505 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3506 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3507 return; 3508 } 3509 3510 static int 3511 em_is_valid_ether_addr(u8 *addr) 3512 { 3513 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3514 3515 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3516 return (FALSE); 3517 } 3518 3519 return (TRUE); 3520 } 3521 3522 /* 3523 ** Parse the interface capabilities with regard 3524 ** to both system management and wake-on-lan for 3525 ** later use. 3526 */ 3527 static void 3528 em_get_wakeup(if_ctx_t ctx) 3529 { 3530 struct adapter *adapter = iflib_get_softc(ctx); 3531 device_t dev = iflib_get_dev(ctx); 3532 u16 eeprom_data = 0, device_id, apme_mask; 3533 3534 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3535 apme_mask = EM_EEPROM_APME; 3536 3537 switch (adapter->hw.mac.type) { 3538 case e1000_82542: 3539 case e1000_82543: 3540 break; 3541 case e1000_82544: 3542 e1000_read_nvm(&adapter->hw, 3543 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3544 apme_mask = EM_82544_APME; 3545 break; 3546 case e1000_82546: 3547 case e1000_82546_rev_3: 3548 if (adapter->hw.bus.func == 1) { 3549 e1000_read_nvm(&adapter->hw, 3550 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3551 break; 3552 } else 3553 e1000_read_nvm(&adapter->hw, 3554 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3555 break; 3556 case e1000_82573: 3557 case e1000_82583: 3558 adapter->has_amt = TRUE; 3559 /* FALLTHROUGH */ 3560 case e1000_82571: 3561 case e1000_82572: 3562 case e1000_80003es2lan: 3563 if (adapter->hw.bus.func == 1) { 3564 e1000_read_nvm(&adapter->hw, 3565 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3566 break; 3567 } else 3568 e1000_read_nvm(&adapter->hw, 3569 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3570 break; 3571 case e1000_ich8lan: 3572 case e1000_ich9lan: 3573 case e1000_ich10lan: 3574 case e1000_pchlan: 3575 case e1000_pch2lan: 3576 case e1000_pch_lpt: 3577 case e1000_pch_spt: 3578 case e1000_82575: /* listing all igb devices */ 3579 case e1000_82576: 3580 case e1000_82580: 3581 case e1000_i350: 3582 case e1000_i354: 3583 case e1000_i210: 3584 case e1000_i211: 3585 case e1000_vfadapt: 3586 case e1000_vfadapt_i350: 3587 apme_mask = E1000_WUC_APME; 3588 adapter->has_amt = TRUE; 3589 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3590 break; 3591 default: 3592 e1000_read_nvm(&adapter->hw, 3593 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3594 break; 3595 } 3596 if (eeprom_data & apme_mask) 3597 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3598 /* 3599 * We have the eeprom settings, now apply the special cases 3600 * where the eeprom may be wrong or the board won't support 3601 * wake on lan on a particular port 3602 */ 3603 device_id = pci_get_device(dev); 3604 switch (device_id) { 3605 case E1000_DEV_ID_82546GB_PCIE: 3606 adapter->wol = 0; 3607 break; 3608 case E1000_DEV_ID_82546EB_FIBER: 3609 case E1000_DEV_ID_82546GB_FIBER: 3610 /* Wake events only supported on port A for dual fiber 3611 * regardless of eeprom setting */ 3612 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3613 E1000_STATUS_FUNC_1) 3614 adapter->wol = 0; 3615 break; 3616 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3617 /* if quad port adapter, disable WoL on all but port A */ 3618 if (global_quad_port_a != 0) 3619 adapter->wol = 0; 3620 /* Reset for multiple quad port adapters */ 3621 if (++global_quad_port_a == 4) 3622 global_quad_port_a = 0; 3623 break; 3624 case E1000_DEV_ID_82571EB_FIBER: 3625 /* Wake events only supported on port A for dual fiber 3626 * regardless of eeprom setting */ 3627 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3628 E1000_STATUS_FUNC_1) 3629 adapter->wol = 0; 3630 break; 3631 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3632 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3633 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3634 /* if quad port adapter, disable WoL on all but port A */ 3635 if (global_quad_port_a != 0) 3636 adapter->wol = 0; 3637 /* Reset for multiple quad port adapters */ 3638 if (++global_quad_port_a == 4) 3639 global_quad_port_a = 0; 3640 break; 3641 } 3642 return; 3643 } 3644 3645 3646 /* 3647 * Enable PCI Wake On Lan capability 3648 */ 3649 static void 3650 em_enable_wakeup(if_ctx_t ctx) 3651 { 3652 struct adapter *adapter = iflib_get_softc(ctx); 3653 device_t dev = iflib_get_dev(ctx); 3654 if_t ifp = iflib_get_ifp(ctx); 3655 int error = 0; 3656 u32 pmc, ctrl, ctrl_ext, rctl; 3657 u16 status; 3658 3659 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3660 return; 3661 3662 /* 3663 * Determine type of Wakeup: note that wol 3664 * is set with all bits on by default. 3665 */ 3666 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3667 adapter->wol &= ~E1000_WUFC_MAG; 3668 3669 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3670 adapter->wol &= ~E1000_WUFC_EX; 3671 3672 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3673 adapter->wol &= ~E1000_WUFC_MC; 3674 else { 3675 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3676 rctl |= E1000_RCTL_MPE; 3677 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3678 } 3679 3680 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3681 goto pme; 3682 3683 /* Advertise the wakeup capability */ 3684 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3685 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3686 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3687 3688 /* Keep the laser running on Fiber adapters */ 3689 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3690 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3691 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3692 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3693 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3694 } 3695 3696 if ((adapter->hw.mac.type == e1000_ich8lan) || 3697 (adapter->hw.mac.type == e1000_pchlan) || 3698 (adapter->hw.mac.type == e1000_ich9lan) || 3699 (adapter->hw.mac.type == e1000_ich10lan)) 3700 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3701 3702 if ( adapter->hw.mac.type >= e1000_pchlan) { 3703 error = em_enable_phy_wakeup(adapter); 3704 if (error) 3705 goto pme; 3706 } else { 3707 /* Enable wakeup by the MAC */ 3708 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3709 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3710 } 3711 3712 if (adapter->hw.phy.type == e1000_phy_igp_3) 3713 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3714 3715 pme: 3716 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3717 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3718 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3719 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3720 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3721 3722 return; 3723 } 3724 3725 /* 3726 * WOL in the newer chipset interfaces (pchlan) 3727 * require thing to be copied into the phy 3728 */ 3729 static int 3730 em_enable_phy_wakeup(struct adapter *adapter) 3731 { 3732 struct e1000_hw *hw = &adapter->hw; 3733 u32 mreg, ret = 0; 3734 u16 preg; 3735 3736 /* copy MAC RARs to PHY RARs */ 3737 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3738 3739 /* copy MAC MTA to PHY MTA */ 3740 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3741 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3742 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3743 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3744 (u16)((mreg >> 16) & 0xFFFF)); 3745 } 3746 3747 /* configure PHY Rx Control register */ 3748 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3749 mreg = E1000_READ_REG(hw, E1000_RCTL); 3750 if (mreg & E1000_RCTL_UPE) 3751 preg |= BM_RCTL_UPE; 3752 if (mreg & E1000_RCTL_MPE) 3753 preg |= BM_RCTL_MPE; 3754 preg &= ~(BM_RCTL_MO_MASK); 3755 if (mreg & E1000_RCTL_MO_3) 3756 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3757 << BM_RCTL_MO_SHIFT); 3758 if (mreg & E1000_RCTL_BAM) 3759 preg |= BM_RCTL_BAM; 3760 if (mreg & E1000_RCTL_PMCF) 3761 preg |= BM_RCTL_PMCF; 3762 mreg = E1000_READ_REG(hw, E1000_CTRL); 3763 if (mreg & E1000_CTRL_RFCE) 3764 preg |= BM_RCTL_RFCE; 3765 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3766 3767 /* enable PHY wakeup in MAC register */ 3768 E1000_WRITE_REG(hw, E1000_WUC, 3769 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3770 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3771 3772 /* configure and enable PHY wakeup in PHY registers */ 3773 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3774 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3775 3776 /* activate PHY wakeup */ 3777 ret = hw->phy.ops.acquire(hw); 3778 if (ret) { 3779 printf("Could not acquire PHY\n"); 3780 return ret; 3781 } 3782 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3783 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3784 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3785 if (ret) { 3786 printf("Could not read PHY page 769\n"); 3787 goto out; 3788 } 3789 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3790 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3791 if (ret) 3792 printf("Could not set PHY Host Wakeup bit\n"); 3793 out: 3794 hw->phy.ops.release(hw); 3795 3796 return ret; 3797 } 3798 3799 static void 3800 em_if_led_func(if_ctx_t ctx, int onoff) 3801 { 3802 struct adapter *adapter = iflib_get_softc(ctx); 3803 3804 if (onoff) { 3805 e1000_setup_led(&adapter->hw); 3806 e1000_led_on(&adapter->hw); 3807 } else { 3808 e1000_led_off(&adapter->hw); 3809 e1000_cleanup_led(&adapter->hw); 3810 } 3811 } 3812 3813 /* 3814 * Disable the L0S and L1 LINK states 3815 */ 3816 static void 3817 em_disable_aspm(struct adapter *adapter) 3818 { 3819 int base, reg; 3820 u16 link_cap,link_ctrl; 3821 device_t dev = adapter->dev; 3822 3823 switch (adapter->hw.mac.type) { 3824 case e1000_82573: 3825 case e1000_82574: 3826 case e1000_82583: 3827 break; 3828 default: 3829 return; 3830 } 3831 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3832 return; 3833 reg = base + PCIER_LINK_CAP; 3834 link_cap = pci_read_config(dev, reg, 2); 3835 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3836 return; 3837 reg = base + PCIER_LINK_CTL; 3838 link_ctrl = pci_read_config(dev, reg, 2); 3839 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3840 pci_write_config(dev, reg, link_ctrl, 2); 3841 return; 3842 } 3843 3844 /********************************************************************** 3845 * 3846 * Update the board statistics counters. 3847 * 3848 **********************************************************************/ 3849 static void 3850 em_update_stats_counters(struct adapter *adapter) 3851 { 3852 3853 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3854 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3855 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3856 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3857 } 3858 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3859 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3860 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3861 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3862 3863 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3864 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3865 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3866 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3867 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3868 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3869 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3870 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3871 /* 3872 ** For watchdog management we need to know if we have been 3873 ** paused during the last interval, so capture that here. 3874 */ 3875 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3876 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3877 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3878 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3879 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3880 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3881 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3882 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3883 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3884 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3885 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3886 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3887 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3888 3889 /* For the 64-bit byte counters the low dword must be read first. */ 3890 /* Both registers clear on the read of the high dword */ 3891 3892 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3893 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3894 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3895 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3896 3897 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3898 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3899 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3900 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3901 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3902 3903 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3904 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3905 3906 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3907 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3908 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3909 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3910 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3911 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3912 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3913 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3914 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3915 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3916 3917 /* Interrupt Counts */ 3918 3919 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3920 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3921 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3922 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3923 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3924 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3925 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3926 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3927 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3928 3929 if (adapter->hw.mac.type >= e1000_82543) { 3930 adapter->stats.algnerrc += 3931 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3932 adapter->stats.rxerrc += 3933 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3934 adapter->stats.tncrs += 3935 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3936 adapter->stats.cexterr += 3937 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3938 adapter->stats.tsctc += 3939 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3940 adapter->stats.tsctfc += 3941 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3942 } 3943 } 3944 3945 static uint64_t 3946 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3947 { 3948 struct adapter *adapter = iflib_get_softc(ctx); 3949 struct ifnet *ifp = iflib_get_ifp(ctx); 3950 3951 switch (cnt) { 3952 case IFCOUNTER_COLLISIONS: 3953 return (adapter->stats.colc); 3954 case IFCOUNTER_IERRORS: 3955 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3956 adapter->stats.crcerrs + adapter->stats.algnerrc + 3957 adapter->stats.ruc + adapter->stats.roc + 3958 adapter->stats.mpc + adapter->stats.cexterr); 3959 case IFCOUNTER_OERRORS: 3960 return (adapter->stats.ecol + adapter->stats.latecol + 3961 adapter->watchdog_events); 3962 default: 3963 return (if_get_counter_default(ifp, cnt)); 3964 } 3965 } 3966 3967 /* Export a single 32-bit register via a read-only sysctl. */ 3968 static int 3969 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3970 { 3971 struct adapter *adapter; 3972 u_int val; 3973 3974 adapter = oidp->oid_arg1; 3975 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3976 return (sysctl_handle_int(oidp, &val, 0, req)); 3977 } 3978 3979 /* 3980 * Add sysctl variables, one per statistic, to the system. 3981 */ 3982 static void 3983 em_add_hw_stats(struct adapter *adapter) 3984 { 3985 device_t dev = iflib_get_dev(adapter->ctx); 3986 struct em_tx_queue *tx_que = adapter->tx_queues; 3987 struct em_rx_queue *rx_que = adapter->rx_queues; 3988 3989 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3990 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3991 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3992 struct e1000_hw_stats *stats = &adapter->stats; 3993 3994 struct sysctl_oid *stat_node, *queue_node, *int_node; 3995 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3996 3997 #define QUEUE_NAME_LEN 32 3998 char namebuf[QUEUE_NAME_LEN]; 3999 4000 /* Driver Statistics */ 4001 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4002 CTLFLAG_RD, &adapter->dropped_pkts, 4003 "Driver dropped packets"); 4004 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4005 CTLFLAG_RD, &adapter->link_irq, 4006 "Link MSIX IRQ Handled"); 4007 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4008 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4009 "Defragmenting mbuf chain failed"); 4010 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4011 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4012 "Driver tx dma failure in xmit"); 4013 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4014 CTLFLAG_RD, &adapter->rx_overruns, 4015 "RX overruns"); 4016 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4017 CTLFLAG_RD, &adapter->watchdog_events, 4018 "Watchdog timeouts"); 4019 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4020 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4021 em_sysctl_reg_handler, "IU", 4022 "Device Control Register"); 4023 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4024 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4025 em_sysctl_reg_handler, "IU", 4026 "Receiver Control Register"); 4027 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4028 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4029 "Flow Control High Watermark"); 4030 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4031 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4032 "Flow Control Low Watermark"); 4033 4034 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4035 struct tx_ring *txr = &tx_que->txr; 4036 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4037 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4038 CTLFLAG_RD, NULL, "TX Queue Name"); 4039 queue_list = SYSCTL_CHILDREN(queue_node); 4040 4041 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4042 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4043 E1000_TDH(txr->me), 4044 em_sysctl_reg_handler, "IU", 4045 "Transmit Descriptor Head"); 4046 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4047 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4048 E1000_TDT(txr->me), 4049 em_sysctl_reg_handler, "IU", 4050 "Transmit Descriptor Tail"); 4051 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4052 CTLFLAG_RD, &txr->tx_irq, 4053 "Queue MSI-X Transmit Interrupts"); 4054 } 4055 4056 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4057 struct rx_ring *rxr = &rx_que->rxr; 4058 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4059 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4060 CTLFLAG_RD, NULL, "RX Queue Name"); 4061 queue_list = SYSCTL_CHILDREN(queue_node); 4062 4063 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4064 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4065 E1000_RDH(rxr->me), 4066 em_sysctl_reg_handler, "IU", 4067 "Receive Descriptor Head"); 4068 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4069 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4070 E1000_RDT(rxr->me), 4071 em_sysctl_reg_handler, "IU", 4072 "Receive Descriptor Tail"); 4073 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4074 CTLFLAG_RD, &rxr->rx_irq, 4075 "Queue MSI-X Receive Interrupts"); 4076 } 4077 4078 /* MAC stats get their own sub node */ 4079 4080 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4081 CTLFLAG_RD, NULL, "Statistics"); 4082 stat_list = SYSCTL_CHILDREN(stat_node); 4083 4084 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4085 CTLFLAG_RD, &stats->ecol, 4086 "Excessive collisions"); 4087 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4088 CTLFLAG_RD, &stats->scc, 4089 "Single collisions"); 4090 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4091 CTLFLAG_RD, &stats->mcc, 4092 "Multiple collisions"); 4093 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4094 CTLFLAG_RD, &stats->latecol, 4095 "Late collisions"); 4096 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4097 CTLFLAG_RD, &stats->colc, 4098 "Collision Count"); 4099 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4100 CTLFLAG_RD, &adapter->stats.symerrs, 4101 "Symbol Errors"); 4102 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4103 CTLFLAG_RD, &adapter->stats.sec, 4104 "Sequence Errors"); 4105 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4106 CTLFLAG_RD, &adapter->stats.dc, 4107 "Defer Count"); 4108 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4109 CTLFLAG_RD, &adapter->stats.mpc, 4110 "Missed Packets"); 4111 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4112 CTLFLAG_RD, &adapter->stats.rnbc, 4113 "Receive No Buffers"); 4114 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4115 CTLFLAG_RD, &adapter->stats.ruc, 4116 "Receive Undersize"); 4117 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4118 CTLFLAG_RD, &adapter->stats.rfc, 4119 "Fragmented Packets Received "); 4120 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4121 CTLFLAG_RD, &adapter->stats.roc, 4122 "Oversized Packets Received"); 4123 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4124 CTLFLAG_RD, &adapter->stats.rjc, 4125 "Recevied Jabber"); 4126 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4127 CTLFLAG_RD, &adapter->stats.rxerrc, 4128 "Receive Errors"); 4129 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4130 CTLFLAG_RD, &adapter->stats.crcerrs, 4131 "CRC errors"); 4132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4133 CTLFLAG_RD, &adapter->stats.algnerrc, 4134 "Alignment Errors"); 4135 /* On 82575 these are collision counts */ 4136 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4137 CTLFLAG_RD, &adapter->stats.cexterr, 4138 "Collision/Carrier extension errors"); 4139 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4140 CTLFLAG_RD, &adapter->stats.xonrxc, 4141 "XON Received"); 4142 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4143 CTLFLAG_RD, &adapter->stats.xontxc, 4144 "XON Transmitted"); 4145 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4146 CTLFLAG_RD, &adapter->stats.xoffrxc, 4147 "XOFF Received"); 4148 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4149 CTLFLAG_RD, &adapter->stats.xofftxc, 4150 "XOFF Transmitted"); 4151 4152 /* Packet Reception Stats */ 4153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4154 CTLFLAG_RD, &adapter->stats.tpr, 4155 "Total Packets Received "); 4156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4157 CTLFLAG_RD, &adapter->stats.gprc, 4158 "Good Packets Received"); 4159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4160 CTLFLAG_RD, &adapter->stats.bprc, 4161 "Broadcast Packets Received"); 4162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4163 CTLFLAG_RD, &adapter->stats.mprc, 4164 "Multicast Packets Received"); 4165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4166 CTLFLAG_RD, &adapter->stats.prc64, 4167 "64 byte frames received "); 4168 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4169 CTLFLAG_RD, &adapter->stats.prc127, 4170 "65-127 byte frames received"); 4171 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4172 CTLFLAG_RD, &adapter->stats.prc255, 4173 "128-255 byte frames received"); 4174 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4175 CTLFLAG_RD, &adapter->stats.prc511, 4176 "256-511 byte frames received"); 4177 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4178 CTLFLAG_RD, &adapter->stats.prc1023, 4179 "512-1023 byte frames received"); 4180 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4181 CTLFLAG_RD, &adapter->stats.prc1522, 4182 "1023-1522 byte frames received"); 4183 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4184 CTLFLAG_RD, &adapter->stats.gorc, 4185 "Good Octets Received"); 4186 4187 /* Packet Transmission Stats */ 4188 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4189 CTLFLAG_RD, &adapter->stats.gotc, 4190 "Good Octets Transmitted"); 4191 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4192 CTLFLAG_RD, &adapter->stats.tpt, 4193 "Total Packets Transmitted"); 4194 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4195 CTLFLAG_RD, &adapter->stats.gptc, 4196 "Good Packets Transmitted"); 4197 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4198 CTLFLAG_RD, &adapter->stats.bptc, 4199 "Broadcast Packets Transmitted"); 4200 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4201 CTLFLAG_RD, &adapter->stats.mptc, 4202 "Multicast Packets Transmitted"); 4203 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4204 CTLFLAG_RD, &adapter->stats.ptc64, 4205 "64 byte frames transmitted "); 4206 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4207 CTLFLAG_RD, &adapter->stats.ptc127, 4208 "65-127 byte frames transmitted"); 4209 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4210 CTLFLAG_RD, &adapter->stats.ptc255, 4211 "128-255 byte frames transmitted"); 4212 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4213 CTLFLAG_RD, &adapter->stats.ptc511, 4214 "256-511 byte frames transmitted"); 4215 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4216 CTLFLAG_RD, &adapter->stats.ptc1023, 4217 "512-1023 byte frames transmitted"); 4218 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4219 CTLFLAG_RD, &adapter->stats.ptc1522, 4220 "1024-1522 byte frames transmitted"); 4221 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4222 CTLFLAG_RD, &adapter->stats.tsctc, 4223 "TSO Contexts Transmitted"); 4224 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4225 CTLFLAG_RD, &adapter->stats.tsctfc, 4226 "TSO Contexts Failed"); 4227 4228 4229 /* Interrupt Stats */ 4230 4231 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4232 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4233 int_list = SYSCTL_CHILDREN(int_node); 4234 4235 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4236 CTLFLAG_RD, &adapter->stats.iac, 4237 "Interrupt Assertion Count"); 4238 4239 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4240 CTLFLAG_RD, &adapter->stats.icrxptc, 4241 "Interrupt Cause Rx Pkt Timer Expire Count"); 4242 4243 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4244 CTLFLAG_RD, &adapter->stats.icrxatc, 4245 "Interrupt Cause Rx Abs Timer Expire Count"); 4246 4247 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4248 CTLFLAG_RD, &adapter->stats.ictxptc, 4249 "Interrupt Cause Tx Pkt Timer Expire Count"); 4250 4251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4252 CTLFLAG_RD, &adapter->stats.ictxatc, 4253 "Interrupt Cause Tx Abs Timer Expire Count"); 4254 4255 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4256 CTLFLAG_RD, &adapter->stats.ictxqec, 4257 "Interrupt Cause Tx Queue Empty Count"); 4258 4259 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4260 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4261 "Interrupt Cause Tx Queue Min Thresh Count"); 4262 4263 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4264 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4265 "Interrupt Cause Rx Desc Min Thresh Count"); 4266 4267 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4268 CTLFLAG_RD, &adapter->stats.icrxoc, 4269 "Interrupt Cause Receiver Overrun Count"); 4270 } 4271 4272 /********************************************************************** 4273 * 4274 * This routine provides a way to dump out the adapter eeprom, 4275 * often a useful debug/service tool. This only dumps the first 4276 * 32 words, stuff that matters is in that extent. 4277 * 4278 **********************************************************************/ 4279 static int 4280 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4281 { 4282 struct adapter *adapter = (struct adapter *)arg1; 4283 int error; 4284 int result; 4285 4286 result = -1; 4287 error = sysctl_handle_int(oidp, &result, 0, req); 4288 4289 if (error || !req->newptr) 4290 return (error); 4291 4292 /* 4293 * This value will cause a hex dump of the 4294 * first 32 16-bit words of the EEPROM to 4295 * the screen. 4296 */ 4297 if (result == 1) 4298 em_print_nvm_info(adapter); 4299 4300 return (error); 4301 } 4302 4303 static void 4304 em_print_nvm_info(struct adapter *adapter) 4305 { 4306 u16 eeprom_data; 4307 int i, j, row = 0; 4308 4309 /* Its a bit crude, but it gets the job done */ 4310 printf("\nInterface EEPROM Dump:\n"); 4311 printf("Offset\n0x0000 "); 4312 for (i = 0, j = 0; i < 32; i++, j++) { 4313 if (j == 8) { /* Make the offset block */ 4314 j = 0; ++row; 4315 printf("\n0x00%x0 ",row); 4316 } 4317 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4318 printf("%04x ", eeprom_data); 4319 } 4320 printf("\n"); 4321 } 4322 4323 static int 4324 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4325 { 4326 struct em_int_delay_info *info; 4327 struct adapter *adapter; 4328 u32 regval; 4329 int error, usecs, ticks; 4330 4331 info = (struct em_int_delay_info *) arg1; 4332 usecs = info->value; 4333 error = sysctl_handle_int(oidp, &usecs, 0, req); 4334 if (error != 0 || req->newptr == NULL) 4335 return (error); 4336 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4337 return (EINVAL); 4338 info->value = usecs; 4339 ticks = EM_USECS_TO_TICKS(usecs); 4340 if (info->offset == E1000_ITR) /* units are 256ns here */ 4341 ticks *= 4; 4342 4343 adapter = info->adapter; 4344 4345 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4346 regval = (regval & ~0xffff) | (ticks & 0xffff); 4347 /* Handle a few special cases. */ 4348 switch (info->offset) { 4349 case E1000_RDTR: 4350 break; 4351 case E1000_TIDV: 4352 if (ticks == 0) { 4353 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4354 /* Don't write 0 into the TIDV register. */ 4355 regval++; 4356 } else 4357 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4358 break; 4359 } 4360 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4361 return (0); 4362 } 4363 4364 static void 4365 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4366 const char *description, struct em_int_delay_info *info, 4367 int offset, int value) 4368 { 4369 info->adapter = adapter; 4370 info->offset = offset; 4371 info->value = value; 4372 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4373 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4374 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4375 info, 0, em_sysctl_int_delay, "I", description); 4376 } 4377 4378 /* 4379 * Set flow control using sysctl: 4380 * Flow control values: 4381 * 0 - off 4382 * 1 - rx pause 4383 * 2 - tx pause 4384 * 3 - full 4385 */ 4386 static int 4387 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4388 { 4389 int error; 4390 static int input = 3; /* default is full */ 4391 struct adapter *adapter = (struct adapter *) arg1; 4392 4393 error = sysctl_handle_int(oidp, &input, 0, req); 4394 4395 if ((error) || (req->newptr == NULL)) 4396 return (error); 4397 4398 if (input == adapter->fc) /* no change? */ 4399 return (error); 4400 4401 switch (input) { 4402 case e1000_fc_rx_pause: 4403 case e1000_fc_tx_pause: 4404 case e1000_fc_full: 4405 case e1000_fc_none: 4406 adapter->hw.fc.requested_mode = input; 4407 adapter->fc = input; 4408 break; 4409 default: 4410 /* Do nothing */ 4411 return (error); 4412 } 4413 4414 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4415 e1000_force_mac_fc(&adapter->hw); 4416 return (error); 4417 } 4418 4419 /* 4420 * Manage Energy Efficient Ethernet: 4421 * Control values: 4422 * 0/1 - enabled/disabled 4423 */ 4424 static int 4425 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4426 { 4427 struct adapter *adapter = (struct adapter *) arg1; 4428 int error, value; 4429 4430 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4431 error = sysctl_handle_int(oidp, &value, 0, req); 4432 if (error || req->newptr == NULL) 4433 return (error); 4434 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4435 em_if_init(adapter->ctx); 4436 4437 return (0); 4438 } 4439 4440 static int 4441 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4442 { 4443 struct adapter *adapter; 4444 int error; 4445 int result; 4446 4447 result = -1; 4448 error = sysctl_handle_int(oidp, &result, 0, req); 4449 4450 if (error || !req->newptr) 4451 return (error); 4452 4453 if (result == 1) { 4454 adapter = (struct adapter *) arg1; 4455 em_print_debug_info(adapter); 4456 } 4457 4458 return (error); 4459 } 4460 4461 static int 4462 em_get_rs(SYSCTL_HANDLER_ARGS) 4463 { 4464 struct adapter *adapter = (struct adapter *) arg1; 4465 int error; 4466 int result; 4467 4468 result = 0; 4469 error = sysctl_handle_int(oidp, &result, 0, req); 4470 4471 if (error || !req->newptr || result != 1) 4472 return (error); 4473 em_dump_rs(adapter); 4474 4475 return (error); 4476 } 4477 4478 static void 4479 em_if_debug(if_ctx_t ctx) 4480 { 4481 em_dump_rs(iflib_get_softc(ctx)); 4482 } 4483 4484 /* 4485 * This routine is meant to be fluid, add whatever is 4486 * needed for debugging a problem. -jfv 4487 */ 4488 static void 4489 em_print_debug_info(struct adapter *adapter) 4490 { 4491 device_t dev = iflib_get_dev(adapter->ctx); 4492 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4493 struct tx_ring *txr = &adapter->tx_queues->txr; 4494 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4495 4496 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4497 printf("Interface is RUNNING "); 4498 else 4499 printf("Interface is NOT RUNNING\n"); 4500 4501 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4502 printf("and INACTIVE\n"); 4503 else 4504 printf("and ACTIVE\n"); 4505 4506 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4507 device_printf(dev, "TX Queue %d ------\n", i); 4508 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4509 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4510 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4511 4512 } 4513 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4514 device_printf(dev, "RX Queue %d ------\n", j); 4515 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4516 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4517 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4518 } 4519 } 4520 4521 /* 4522 * 82574 only: 4523 * Write a new value to the EEPROM increasing the number of MSIX 4524 * vectors from 3 to 5, for proper multiqueue support. 4525 */ 4526 static void 4527 em_enable_vectors_82574(if_ctx_t ctx) 4528 { 4529 struct adapter *adapter = iflib_get_softc(ctx); 4530 struct e1000_hw *hw = &adapter->hw; 4531 device_t dev = iflib_get_dev(ctx); 4532 u16 edata; 4533 4534 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4535 printf("Current cap: %#06x\n", edata); 4536 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4537 device_printf(dev, "Writing to eeprom: increasing " 4538 "reported MSIX vectors from 3 to 5...\n"); 4539 edata &= ~(EM_NVM_MSIX_N_MASK); 4540 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4541 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4542 e1000_update_nvm_checksum(hw); 4543 device_printf(dev, "Writing to eeprom: done\n"); 4544 } 4545 } 4546