1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 167 /* required last entry */ 168 PVID_END 169 }; 170 171 static pci_vendor_info_t igb_vendor_info_array[] = 172 { 173 /* Intel(R) PRO/1000 Network Connection - igb */ 174 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 /********************************************************************* 218 * Function prototypes 219 *********************************************************************/ 220 static void *em_register(device_t dev); 221 static void *igb_register(device_t dev); 222 static int em_if_attach_pre(if_ctx_t ctx); 223 static int em_if_attach_post(if_ctx_t ctx); 224 static int em_if_detach(if_ctx_t ctx); 225 static int em_if_shutdown(if_ctx_t ctx); 226 static int em_if_suspend(if_ctx_t ctx); 227 static int em_if_resume(if_ctx_t ctx); 228 229 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 230 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 231 static void em_if_queues_free(if_ctx_t ctx); 232 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 234 static void em_if_init(if_ctx_t ctx); 235 static void em_if_stop(if_ctx_t ctx); 236 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 237 static int em_if_media_change(if_ctx_t ctx); 238 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 239 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 240 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 241 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 242 243 static void em_identify_hardware(if_ctx_t ctx); 244 static int em_allocate_pci_resources(if_ctx_t ctx); 245 static void em_free_pci_resources(if_ctx_t ctx); 246 static void em_reset(if_ctx_t ctx); 247 static int em_setup_interface(if_ctx_t ctx); 248 static int em_setup_msix(if_ctx_t ctx); 249 250 static void em_initialize_transmit_unit(if_ctx_t ctx); 251 static void em_initialize_receive_unit(if_ctx_t ctx); 252 253 static void em_if_enable_intr(if_ctx_t ctx); 254 static void em_if_disable_intr(if_ctx_t ctx); 255 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 256 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 257 static void em_if_multi_set(if_ctx_t ctx); 258 static void em_if_update_admin_status(if_ctx_t ctx); 259 static void em_if_debug(if_ctx_t ctx); 260 static void em_update_stats_counters(struct adapter *); 261 static void em_add_hw_stats(struct adapter *adapter); 262 static int em_if_set_promisc(if_ctx_t ctx, int flags); 263 static void em_setup_vlan_hw_support(struct adapter *); 264 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 265 static void em_print_nvm_info(struct adapter *); 266 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 267 static int em_get_rs(SYSCTL_HANDLER_ARGS); 268 static void em_print_debug_info(struct adapter *); 269 static int em_is_valid_ether_addr(u8 *); 270 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 271 static void em_add_int_delay_sysctl(struct adapter *, const char *, 272 const char *, struct em_int_delay_info *, int, int); 273 /* Management and WOL Support */ 274 static void em_init_manageability(struct adapter *); 275 static void em_release_manageability(struct adapter *); 276 static void em_get_hw_control(struct adapter *); 277 static void em_release_hw_control(struct adapter *); 278 static void em_get_wakeup(if_ctx_t ctx); 279 static void em_enable_wakeup(if_ctx_t ctx); 280 static int em_enable_phy_wakeup(struct adapter *); 281 static void em_disable_aspm(struct adapter *); 282 283 int em_intr(void *arg); 284 static void em_disable_promisc(if_ctx_t ctx); 285 286 /* MSIX handlers */ 287 static int em_if_msix_intr_assign(if_ctx_t, int); 288 static int em_msix_link(void *); 289 static void em_handle_link(void *context); 290 291 static void em_enable_vectors_82574(if_ctx_t); 292 293 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 294 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 295 static void em_if_led_func(if_ctx_t ctx, int onoff); 296 297 static int em_get_regs(SYSCTL_HANDLER_ARGS); 298 299 static void lem_smartspeed(struct adapter *adapter); 300 static void igb_configure_queues(struct adapter *adapter); 301 302 303 /********************************************************************* 304 * FreeBSD Device Interface Entry Points 305 *********************************************************************/ 306 static device_method_t em_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_register, em_register), 309 DEVMETHOD(device_probe, iflib_device_probe), 310 DEVMETHOD(device_attach, iflib_device_attach), 311 DEVMETHOD(device_detach, iflib_device_detach), 312 DEVMETHOD(device_shutdown, iflib_device_shutdown), 313 DEVMETHOD(device_suspend, iflib_device_suspend), 314 DEVMETHOD(device_resume, iflib_device_resume), 315 DEVMETHOD_END 316 }; 317 318 static device_method_t igb_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_register, igb_register), 321 DEVMETHOD(device_probe, iflib_device_probe), 322 DEVMETHOD(device_attach, iflib_device_attach), 323 DEVMETHOD(device_detach, iflib_device_detach), 324 DEVMETHOD(device_shutdown, iflib_device_shutdown), 325 DEVMETHOD(device_suspend, iflib_device_suspend), 326 DEVMETHOD(device_resume, iflib_device_resume), 327 DEVMETHOD_END 328 }; 329 330 331 static driver_t em_driver = { 332 "em", em_methods, sizeof(struct adapter), 333 }; 334 335 static devclass_t em_devclass; 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 337 338 MODULE_DEPEND(em, pci, 1, 1, 1); 339 MODULE_DEPEND(em, ether, 1, 1, 1); 340 MODULE_DEPEND(em, iflib, 1, 1, 1); 341 342 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 343 344 static driver_t igb_driver = { 345 "igb", igb_methods, sizeof(struct adapter), 346 }; 347 348 static devclass_t igb_devclass; 349 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 350 351 MODULE_DEPEND(igb, pci, 1, 1, 1); 352 MODULE_DEPEND(igb, ether, 1, 1, 1); 353 MODULE_DEPEND(igb, iflib, 1, 1, 1); 354 355 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 356 357 static device_method_t em_if_methods[] = { 358 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 359 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 360 DEVMETHOD(ifdi_detach, em_if_detach), 361 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 362 DEVMETHOD(ifdi_suspend, em_if_suspend), 363 DEVMETHOD(ifdi_resume, em_if_resume), 364 DEVMETHOD(ifdi_init, em_if_init), 365 DEVMETHOD(ifdi_stop, em_if_stop), 366 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 367 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 368 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 369 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 370 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 371 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 372 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 373 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 374 DEVMETHOD(ifdi_media_status, em_if_media_status), 375 DEVMETHOD(ifdi_media_change, em_if_media_change), 376 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 377 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 378 DEVMETHOD(ifdi_timer, em_if_timer), 379 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 380 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 381 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 382 DEVMETHOD(ifdi_led_func, em_if_led_func), 383 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 384 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 385 DEVMETHOD(ifdi_debug, em_if_debug), 386 DEVMETHOD_END 387 }; 388 389 /* 390 * note that if (adapter->msix_mem) is replaced by: 391 * if (adapter->intr_type == IFLIB_INTR_MSIX) 392 */ 393 static driver_t em_if_driver = { 394 "em_if", em_if_methods, sizeof(struct adapter) 395 }; 396 397 /********************************************************************* 398 * Tunable default values. 399 *********************************************************************/ 400 401 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 402 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 403 #define M_TSO_LEN 66 404 405 #define MAX_INTS_PER_SEC 8000 406 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 407 408 /* Allow common code without TSO */ 409 #ifndef CSUM_TSO 410 #define CSUM_TSO 0 411 #endif 412 413 #define TSO_WORKAROUND 4 414 415 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 416 417 static int em_disable_crc_stripping = 0; 418 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 419 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 420 421 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 422 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 423 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 424 0, "Default transmit interrupt delay in usecs"); 425 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 426 0, "Default receive interrupt delay in usecs"); 427 428 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 429 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 430 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 431 &em_tx_abs_int_delay_dflt, 0, 432 "Default transmit interrupt delay limit in usecs"); 433 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 434 &em_rx_abs_int_delay_dflt, 0, 435 "Default receive interrupt delay limit in usecs"); 436 437 static int em_smart_pwr_down = FALSE; 438 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 439 0, "Set to true to leave smart power down enabled on newer adapters"); 440 441 /* Controls whether promiscuous also shows bad packets */ 442 static int em_debug_sbp = TRUE; 443 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 444 "Show bad packets in promiscuous mode"); 445 446 /* How many packets rxeof tries to clean at a time */ 447 static int em_rx_process_limit = 100; 448 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 449 &em_rx_process_limit, 0, 450 "Maximum number of received packets to process " 451 "at a time, -1 means unlimited"); 452 453 /* Energy efficient ethernet - default to OFF */ 454 static int eee_setting = 1; 455 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 456 "Enable Energy Efficient Ethernet"); 457 458 /* 459 ** Tuneable Interrupt rate 460 */ 461 static int em_max_interrupt_rate = 8000; 462 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 463 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 464 465 466 467 /* Global used in WOL setup with multiport cards */ 468 static int global_quad_port_a = 0; 469 470 extern struct if_txrx igb_txrx; 471 extern struct if_txrx em_txrx; 472 extern struct if_txrx lem_txrx; 473 474 static struct if_shared_ctx em_sctx_init = { 475 .isc_magic = IFLIB_MAGIC, 476 .isc_q_align = PAGE_SIZE, 477 .isc_tx_maxsize = EM_TSO_SIZE, 478 .isc_tx_maxsegsize = PAGE_SIZE, 479 .isc_rx_maxsize = MJUM9BYTES, 480 .isc_rx_nsegments = 1, 481 .isc_rx_maxsegsize = MJUM9BYTES, 482 .isc_nfl = 1, 483 .isc_nrxqs = 1, 484 .isc_ntxqs = 1, 485 .isc_admin_intrcnt = 1, 486 .isc_vendor_info = em_vendor_info_array, 487 .isc_driver_version = em_driver_version, 488 .isc_driver = &em_if_driver, 489 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 490 491 .isc_nrxd_min = {EM_MIN_RXD}, 492 .isc_ntxd_min = {EM_MIN_TXD}, 493 .isc_nrxd_max = {EM_MAX_RXD}, 494 .isc_ntxd_max = {EM_MAX_TXD}, 495 .isc_nrxd_default = {EM_DEFAULT_RXD}, 496 .isc_ntxd_default = {EM_DEFAULT_TXD}, 497 }; 498 499 if_shared_ctx_t em_sctx = &em_sctx_init; 500 501 502 static struct if_shared_ctx igb_sctx_init = { 503 .isc_magic = IFLIB_MAGIC, 504 .isc_q_align = PAGE_SIZE, 505 .isc_tx_maxsize = EM_TSO_SIZE, 506 .isc_tx_maxsegsize = PAGE_SIZE, 507 .isc_rx_maxsize = MJUM9BYTES, 508 .isc_rx_nsegments = 1, 509 .isc_rx_maxsegsize = MJUM9BYTES, 510 .isc_nfl = 1, 511 .isc_nrxqs = 1, 512 .isc_ntxqs = 1, 513 .isc_admin_intrcnt = 1, 514 .isc_vendor_info = igb_vendor_info_array, 515 .isc_driver_version = em_driver_version, 516 .isc_driver = &em_if_driver, 517 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 518 519 .isc_nrxd_min = {EM_MIN_RXD}, 520 .isc_ntxd_min = {EM_MIN_TXD}, 521 .isc_nrxd_max = {IGB_MAX_RXD}, 522 .isc_ntxd_max = {IGB_MAX_TXD}, 523 .isc_nrxd_default = {EM_DEFAULT_RXD}, 524 .isc_ntxd_default = {EM_DEFAULT_TXD}, 525 }; 526 527 if_shared_ctx_t igb_sctx = &igb_sctx_init; 528 529 /***************************************************************** 530 * 531 * Dump Registers 532 * 533 ****************************************************************/ 534 #define IGB_REGS_LEN 739 535 536 static int em_get_regs(SYSCTL_HANDLER_ARGS) 537 { 538 struct adapter *adapter = (struct adapter *)arg1; 539 struct e1000_hw *hw = &adapter->hw; 540 struct sbuf *sb; 541 u32 *regs_buff; 542 int rc; 543 544 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 545 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 546 547 rc = sysctl_wire_old_buffer(req, 0); 548 MPASS(rc == 0); 549 if (rc != 0) { 550 free(regs_buff, M_DEVBUF); 551 return (rc); 552 } 553 554 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 555 MPASS(sb != NULL); 556 if (sb == NULL) { 557 free(regs_buff, M_DEVBUF); 558 return (ENOMEM); 559 } 560 561 /* General Registers */ 562 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 563 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 564 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 565 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 566 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 567 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 568 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 569 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 570 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 571 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 572 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 573 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 574 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 575 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 576 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 577 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 578 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 579 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 580 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 581 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 582 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 583 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 584 585 sbuf_printf(sb, "General Registers\n"); 586 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 587 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 588 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 589 590 sbuf_printf(sb, "Interrupt Registers\n"); 591 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 592 593 sbuf_printf(sb, "RX Registers\n"); 594 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 595 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 596 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 597 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 598 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 599 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 600 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 601 602 sbuf_printf(sb, "TX Registers\n"); 603 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 604 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 605 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 606 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 607 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 608 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 609 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 610 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 611 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 612 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 613 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 614 615 free(regs_buff, M_DEVBUF); 616 617 #ifdef DUMP_DESCS 618 { 619 if_softc_ctx_t scctx = adapter->shared; 620 struct rx_ring *rxr = &rx_que->rxr; 621 struct tx_ring *txr = &tx_que->txr; 622 int ntxd = scctx->isc_ntxd[0]; 623 int nrxd = scctx->isc_nrxd[0]; 624 int j; 625 626 for (j = 0; j < nrxd; j++) { 627 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 628 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 629 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 630 } 631 632 for (j = 0; j < min(ntxd, 256); j++) { 633 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 634 635 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 636 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 637 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 638 639 } 640 } 641 #endif 642 643 rc = sbuf_finish(sb); 644 sbuf_delete(sb); 645 return(rc); 646 } 647 648 static void * 649 em_register(device_t dev) 650 { 651 return (em_sctx); 652 } 653 654 static void * 655 igb_register(device_t dev) 656 { 657 return (igb_sctx); 658 } 659 660 static int 661 em_set_num_queues(if_ctx_t ctx) 662 { 663 struct adapter *adapter = iflib_get_softc(ctx); 664 int maxqueues; 665 666 /* Sanity check based on HW */ 667 switch (adapter->hw.mac.type) { 668 case e1000_82576: 669 case e1000_82580: 670 case e1000_i350: 671 case e1000_i354: 672 maxqueues = 8; 673 break; 674 case e1000_i210: 675 case e1000_82575: 676 maxqueues = 4; 677 break; 678 case e1000_i211: 679 case e1000_82574: 680 maxqueues = 2; 681 break; 682 default: 683 maxqueues = 1; 684 break; 685 } 686 687 return (maxqueues); 688 } 689 690 691 #define EM_CAPS \ 692 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 693 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 694 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 695 696 #define IGB_CAPS \ 697 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 698 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 699 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 700 701 /********************************************************************* 702 * Device initialization routine 703 * 704 * The attach entry point is called when the driver is being loaded. 705 * This routine identifies the type of hardware, allocates all resources 706 * and initializes the hardware. 707 * 708 * return 0 on success, positive on failure 709 *********************************************************************/ 710 711 static int 712 em_if_attach_pre(if_ctx_t ctx) 713 { 714 struct adapter *adapter; 715 if_softc_ctx_t scctx; 716 device_t dev; 717 struct e1000_hw *hw; 718 int error = 0; 719 720 INIT_DEBUGOUT("em_if_attach_pre begin"); 721 dev = iflib_get_dev(ctx); 722 adapter = iflib_get_softc(ctx); 723 724 if (resource_disabled("em", device_get_unit(dev))) { 725 device_printf(dev, "Disabled by device hint\n"); 726 return (ENXIO); 727 } 728 729 adapter->ctx = ctx; 730 adapter->dev = adapter->osdep.dev = dev; 731 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 732 adapter->media = iflib_get_media(ctx); 733 hw = &adapter->hw; 734 735 adapter->tx_process_limit = scctx->isc_ntxd[0]; 736 737 /* SYSCTL stuff */ 738 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 739 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 740 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 741 em_sysctl_nvm_info, "I", "NVM Information"); 742 743 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 744 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 745 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 746 em_sysctl_debug_info, "I", "Debug Information"); 747 748 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 749 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 750 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 751 em_set_flowcntl, "I", "Flow Control"); 752 753 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 754 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 755 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 756 em_get_regs, "A", "Dump Registers"); 757 758 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 759 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 760 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 761 em_get_rs, "I", "Dump RS indexes"); 762 763 /* Determine hardware and mac info */ 764 em_identify_hardware(ctx); 765 766 /* Set isc_msix_bar */ 767 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 768 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 769 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 770 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 771 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 772 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 773 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 774 775 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 776 777 778 if (adapter->hw.mac.type >= igb_mac_min) { 779 int try_second_bar; 780 781 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 782 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 783 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 784 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 785 scctx->isc_txrx = &igb_txrx; 786 scctx->isc_capenable = IGB_CAPS; 787 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 788 | CSUM_IP6_UDP | CSUM_IP6_TCP; 789 if (adapter->hw.mac.type != e1000_82575) 790 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 791 792 /* 793 ** Some new devices, as with ixgbe, now may 794 ** use a different BAR, so we need to keep 795 ** track of which is used. 796 */ 797 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 798 if (try_second_bar == 0) 799 scctx->isc_msix_bar += 4; 800 801 } else if (adapter->hw.mac.type >= em_mac_min) { 802 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 803 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 804 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 805 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 806 scctx->isc_txrx = &em_txrx; 807 scctx->isc_capenable = EM_CAPS; 808 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 809 } else { 810 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 811 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 812 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 813 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 814 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 815 scctx->isc_txrx = &lem_txrx; 816 scctx->isc_capenable = EM_CAPS; 817 if (adapter->hw.mac.type < e1000_82543) 818 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 819 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 820 scctx->isc_msix_bar = 0; 821 } 822 823 /* Setup PCI resources */ 824 if (em_allocate_pci_resources(ctx)) { 825 device_printf(dev, "Allocation of PCI resources failed\n"); 826 error = ENXIO; 827 goto err_pci; 828 } 829 830 /* 831 ** For ICH8 and family we need to 832 ** map the flash memory, and this 833 ** must happen after the MAC is 834 ** identified 835 */ 836 if ((hw->mac.type == e1000_ich8lan) || 837 (hw->mac.type == e1000_ich9lan) || 838 (hw->mac.type == e1000_ich10lan) || 839 (hw->mac.type == e1000_pchlan) || 840 (hw->mac.type == e1000_pch2lan) || 841 (hw->mac.type == e1000_pch_lpt)) { 842 int rid = EM_BAR_TYPE_FLASH; 843 adapter->flash = bus_alloc_resource_any(dev, 844 SYS_RES_MEMORY, &rid, RF_ACTIVE); 845 if (adapter->flash == NULL) { 846 device_printf(dev, "Mapping of Flash failed\n"); 847 error = ENXIO; 848 goto err_pci; 849 } 850 /* This is used in the shared code */ 851 hw->flash_address = (u8 *)adapter->flash; 852 adapter->osdep.flash_bus_space_tag = 853 rman_get_bustag(adapter->flash); 854 adapter->osdep.flash_bus_space_handle = 855 rman_get_bushandle(adapter->flash); 856 } 857 /* 858 ** In the new SPT device flash is not a 859 ** separate BAR, rather it is also in BAR0, 860 ** so use the same tag and an offset handle for the 861 ** FLASH read/write macros in the shared code. 862 */ 863 else if (hw->mac.type == e1000_pch_spt) { 864 adapter->osdep.flash_bus_space_tag = 865 adapter->osdep.mem_bus_space_tag; 866 adapter->osdep.flash_bus_space_handle = 867 adapter->osdep.mem_bus_space_handle 868 + E1000_FLASH_BASE_ADDR; 869 } 870 871 /* Do Shared Code initialization */ 872 error = e1000_setup_init_funcs(hw, TRUE); 873 if (error) { 874 device_printf(dev, "Setup of Shared code failed, error %d\n", 875 error); 876 error = ENXIO; 877 goto err_pci; 878 } 879 880 em_setup_msix(ctx); 881 e1000_get_bus_info(hw); 882 883 /* Set up some sysctls for the tunable interrupt delays */ 884 em_add_int_delay_sysctl(adapter, "rx_int_delay", 885 "receive interrupt delay in usecs", &adapter->rx_int_delay, 886 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 887 em_add_int_delay_sysctl(adapter, "tx_int_delay", 888 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 889 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 890 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 891 "receive interrupt delay limit in usecs", 892 &adapter->rx_abs_int_delay, 893 E1000_REGISTER(hw, E1000_RADV), 894 em_rx_abs_int_delay_dflt); 895 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 896 "transmit interrupt delay limit in usecs", 897 &adapter->tx_abs_int_delay, 898 E1000_REGISTER(hw, E1000_TADV), 899 em_tx_abs_int_delay_dflt); 900 em_add_int_delay_sysctl(adapter, "itr", 901 "interrupt delay limit in usecs/4", 902 &adapter->tx_itr, 903 E1000_REGISTER(hw, E1000_ITR), 904 DEFAULT_ITR); 905 906 hw->mac.autoneg = DO_AUTO_NEG; 907 hw->phy.autoneg_wait_to_complete = FALSE; 908 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 909 910 if (adapter->hw.mac.type < em_mac_min) { 911 e1000_init_script_state_82541(&adapter->hw, TRUE); 912 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 913 } 914 /* Copper options */ 915 if (hw->phy.media_type == e1000_media_type_copper) { 916 hw->phy.mdix = AUTO_ALL_MODES; 917 hw->phy.disable_polarity_correction = FALSE; 918 hw->phy.ms_type = EM_MASTER_SLAVE; 919 } 920 921 /* 922 * Set the frame limits assuming 923 * standard ethernet sized frames. 924 */ 925 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 926 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 927 928 /* 929 * This controls when hardware reports transmit completion 930 * status. 931 */ 932 hw->mac.report_tx_early = 1; 933 934 /* Allocate multicast array memory. */ 935 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 936 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 937 if (adapter->mta == NULL) { 938 device_printf(dev, "Can not allocate multicast setup array\n"); 939 error = ENOMEM; 940 goto err_late; 941 } 942 943 /* Check SOL/IDER usage */ 944 if (e1000_check_reset_block(hw)) 945 device_printf(dev, "PHY reset is blocked" 946 " due to SOL/IDER session.\n"); 947 948 /* Sysctl for setting Energy Efficient Ethernet */ 949 hw->dev_spec.ich8lan.eee_disable = eee_setting; 950 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 951 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 952 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 953 adapter, 0, em_sysctl_eee, "I", 954 "Disable Energy Efficient Ethernet"); 955 956 /* 957 ** Start from a known state, this is 958 ** important in reading the nvm and 959 ** mac from that. 960 */ 961 e1000_reset_hw(hw); 962 963 /* Make sure we have a good EEPROM before we read from it */ 964 if (e1000_validate_nvm_checksum(hw) < 0) { 965 /* 966 ** Some PCI-E parts fail the first check due to 967 ** the link being in sleep state, call it again, 968 ** if it fails a second time its a real issue. 969 */ 970 if (e1000_validate_nvm_checksum(hw) < 0) { 971 device_printf(dev, 972 "The EEPROM Checksum Is Not Valid\n"); 973 error = EIO; 974 goto err_late; 975 } 976 } 977 978 /* Copy the permanent MAC address out of the EEPROM */ 979 if (e1000_read_mac_addr(hw) < 0) { 980 device_printf(dev, "EEPROM read error while reading MAC" 981 " address\n"); 982 error = EIO; 983 goto err_late; 984 } 985 986 if (!em_is_valid_ether_addr(hw->mac.addr)) { 987 device_printf(dev, "Invalid MAC address\n"); 988 error = EIO; 989 goto err_late; 990 } 991 992 /* Disable ULP support */ 993 e1000_disable_ulp_lpt_lp(hw, TRUE); 994 995 /* 996 * Get Wake-on-Lan and Management info for later use 997 */ 998 em_get_wakeup(ctx); 999 1000 iflib_set_mac(ctx, hw->mac.addr); 1001 1002 return (0); 1003 1004 err_late: 1005 em_release_hw_control(adapter); 1006 err_pci: 1007 em_free_pci_resources(ctx); 1008 free(adapter->mta, M_DEVBUF); 1009 1010 return (error); 1011 } 1012 1013 static int 1014 em_if_attach_post(if_ctx_t ctx) 1015 { 1016 struct adapter *adapter = iflib_get_softc(ctx); 1017 struct e1000_hw *hw = &adapter->hw; 1018 int error = 0; 1019 1020 /* Setup OS specific network interface */ 1021 error = em_setup_interface(ctx); 1022 if (error != 0) { 1023 goto err_late; 1024 } 1025 1026 em_reset(ctx); 1027 1028 /* Initialize statistics */ 1029 em_update_stats_counters(adapter); 1030 hw->mac.get_link_status = 1; 1031 em_if_update_admin_status(ctx); 1032 em_add_hw_stats(adapter); 1033 1034 /* Non-AMT based hardware can now take control from firmware */ 1035 if (adapter->has_manage && !adapter->has_amt) 1036 em_get_hw_control(adapter); 1037 1038 INIT_DEBUGOUT("em_if_attach_post: end"); 1039 1040 return (error); 1041 1042 err_late: 1043 em_release_hw_control(adapter); 1044 em_free_pci_resources(ctx); 1045 em_if_queues_free(ctx); 1046 free(adapter->mta, M_DEVBUF); 1047 1048 return (error); 1049 } 1050 1051 /********************************************************************* 1052 * Device removal routine 1053 * 1054 * The detach entry point is called when the driver is being removed. 1055 * This routine stops the adapter and deallocates all the resources 1056 * that were allocated for driver operation. 1057 * 1058 * return 0 on success, positive on failure 1059 *********************************************************************/ 1060 1061 static int 1062 em_if_detach(if_ctx_t ctx) 1063 { 1064 struct adapter *adapter = iflib_get_softc(ctx); 1065 1066 INIT_DEBUGOUT("em_detach: begin"); 1067 1068 e1000_phy_hw_reset(&adapter->hw); 1069 1070 em_release_manageability(adapter); 1071 em_release_hw_control(adapter); 1072 em_free_pci_resources(ctx); 1073 1074 return (0); 1075 } 1076 1077 /********************************************************************* 1078 * 1079 * Shutdown entry point 1080 * 1081 **********************************************************************/ 1082 1083 static int 1084 em_if_shutdown(if_ctx_t ctx) 1085 { 1086 return em_if_suspend(ctx); 1087 } 1088 1089 /* 1090 * Suspend/resume device methods. 1091 */ 1092 static int 1093 em_if_suspend(if_ctx_t ctx) 1094 { 1095 struct adapter *adapter = iflib_get_softc(ctx); 1096 1097 em_release_manageability(adapter); 1098 em_release_hw_control(adapter); 1099 em_enable_wakeup(ctx); 1100 return (0); 1101 } 1102 1103 static int 1104 em_if_resume(if_ctx_t ctx) 1105 { 1106 struct adapter *adapter = iflib_get_softc(ctx); 1107 1108 if (adapter->hw.mac.type == e1000_pch2lan) 1109 e1000_resume_workarounds_pchlan(&adapter->hw); 1110 em_if_init(ctx); 1111 em_init_manageability(adapter); 1112 1113 return(0); 1114 } 1115 1116 static int 1117 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1118 { 1119 int max_frame_size; 1120 struct adapter *adapter = iflib_get_softc(ctx); 1121 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1122 1123 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1124 1125 switch (adapter->hw.mac.type) { 1126 case e1000_82571: 1127 case e1000_82572: 1128 case e1000_ich9lan: 1129 case e1000_ich10lan: 1130 case e1000_pch2lan: 1131 case e1000_pch_lpt: 1132 case e1000_pch_spt: 1133 case e1000_82574: 1134 case e1000_82583: 1135 case e1000_80003es2lan: 1136 /* 9K Jumbo Frame size */ 1137 max_frame_size = 9234; 1138 break; 1139 case e1000_pchlan: 1140 max_frame_size = 4096; 1141 break; 1142 case e1000_82542: 1143 case e1000_ich8lan: 1144 /* Adapters that do not support jumbo frames */ 1145 max_frame_size = ETHER_MAX_LEN; 1146 break; 1147 default: 1148 if (adapter->hw.mac.type >= igb_mac_min) 1149 max_frame_size = 9234; 1150 else /* lem */ 1151 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1152 } 1153 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1154 return (EINVAL); 1155 } 1156 1157 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1158 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1159 return (0); 1160 } 1161 1162 /********************************************************************* 1163 * Init entry point 1164 * 1165 * This routine is used in two ways. It is used by the stack as 1166 * init entry point in network interface structure. It is also used 1167 * by the driver as a hw/sw initialization routine to get to a 1168 * consistent state. 1169 * 1170 * return 0 on success, positive on failure 1171 **********************************************************************/ 1172 1173 static void 1174 em_if_init(if_ctx_t ctx) 1175 { 1176 struct adapter *adapter = iflib_get_softc(ctx); 1177 struct ifnet *ifp = iflib_get_ifp(ctx); 1178 struct em_tx_queue *tx_que; 1179 int i; 1180 INIT_DEBUGOUT("em_if_init: begin"); 1181 1182 /* Get the latest mac address, User can use a LAA */ 1183 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1184 ETHER_ADDR_LEN); 1185 1186 /* Put the address into the Receive Address Array */ 1187 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1188 1189 /* 1190 * With the 82571 adapter, RAR[0] may be overwritten 1191 * when the other port is reset, we make a duplicate 1192 * in RAR[14] for that eventuality, this assures 1193 * the interface continues to function. 1194 */ 1195 if (adapter->hw.mac.type == e1000_82571) { 1196 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1197 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1198 E1000_RAR_ENTRIES - 1); 1199 } 1200 1201 1202 /* Initialize the hardware */ 1203 em_reset(ctx); 1204 em_if_update_admin_status(ctx); 1205 1206 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1207 struct tx_ring *txr = &tx_que->txr; 1208 1209 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1210 } 1211 1212 /* Setup VLAN support, basic and offload if available */ 1213 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1214 1215 /* Clear bad data from Rx FIFOs */ 1216 if (adapter->hw.mac.type >= igb_mac_min) 1217 e1000_rx_fifo_flush_82575(&adapter->hw); 1218 1219 /* Configure for OS presence */ 1220 em_init_manageability(adapter); 1221 1222 /* Prepare transmit descriptors and buffers */ 1223 em_initialize_transmit_unit(ctx); 1224 1225 /* Setup Multicast table */ 1226 em_if_multi_set(ctx); 1227 1228 /* 1229 * Figure out the desired mbuf 1230 * pool for doing jumbos 1231 */ 1232 if (adapter->hw.mac.max_frame_size <= 2048) 1233 adapter->rx_mbuf_sz = MCLBYTES; 1234 #ifndef CONTIGMALLOC_WORKS 1235 else 1236 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1237 #else 1238 else if (adapter->hw.mac.max_frame_size <= 4096) 1239 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1240 else 1241 adapter->rx_mbuf_sz = MJUM9BYTES; 1242 #endif 1243 em_initialize_receive_unit(ctx); 1244 1245 /* Use real VLAN Filter support? */ 1246 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1247 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1248 /* Use real VLAN Filter support */ 1249 em_setup_vlan_hw_support(adapter); 1250 else { 1251 u32 ctrl; 1252 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1253 ctrl |= E1000_CTRL_VME; 1254 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1255 } 1256 } 1257 1258 /* Don't lose promiscuous settings */ 1259 em_if_set_promisc(ctx, IFF_PROMISC); 1260 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1261 1262 /* MSI/X configuration for 82574 */ 1263 if (adapter->hw.mac.type == e1000_82574) { 1264 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1265 1266 tmp |= E1000_CTRL_EXT_PBA_CLR; 1267 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1268 /* Set the IVAR - interrupt vector routing. */ 1269 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1270 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1271 igb_configure_queues(adapter); 1272 1273 /* this clears any pending interrupts */ 1274 E1000_READ_REG(&adapter->hw, E1000_ICR); 1275 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1276 1277 /* AMT based hardware can now take control from firmware */ 1278 if (adapter->has_manage && adapter->has_amt) 1279 em_get_hw_control(adapter); 1280 1281 /* Set Energy Efficient Ethernet */ 1282 if (adapter->hw.mac.type >= igb_mac_min && 1283 adapter->hw.phy.media_type == e1000_media_type_copper) { 1284 if (adapter->hw.mac.type == e1000_i354) 1285 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1286 else 1287 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1288 } 1289 } 1290 1291 /********************************************************************* 1292 * 1293 * Fast Legacy/MSI Combined Interrupt Service routine 1294 * 1295 *********************************************************************/ 1296 int 1297 em_intr(void *arg) 1298 { 1299 struct adapter *adapter = arg; 1300 if_ctx_t ctx = adapter->ctx; 1301 u32 reg_icr; 1302 1303 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1304 1305 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1306 goto skip_stray; 1307 /* Hot eject? */ 1308 if (reg_icr == 0xffffffff) 1309 return FILTER_STRAY; 1310 1311 /* Definitely not our interrupt. */ 1312 if (reg_icr == 0x0) 1313 return FILTER_STRAY; 1314 1315 /* 1316 * Starting with the 82571 chip, bit 31 should be used to 1317 * determine whether the interrupt belongs to us. 1318 */ 1319 if (adapter->hw.mac.type >= e1000_82571 && 1320 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1321 return FILTER_STRAY; 1322 1323 skip_stray: 1324 /* Link status change */ 1325 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1326 adapter->hw.mac.get_link_status = 1; 1327 iflib_admin_intr_deferred(ctx); 1328 } 1329 1330 if (reg_icr & E1000_ICR_RXO) 1331 adapter->rx_overruns++; 1332 1333 return (FILTER_SCHEDULE_THREAD); 1334 } 1335 1336 static void 1337 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1338 { 1339 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1340 } 1341 1342 static void 1343 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1344 { 1345 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1346 } 1347 1348 static void 1349 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1350 { 1351 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1352 } 1353 1354 static void 1355 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1356 { 1357 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1358 } 1359 1360 static int 1361 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1362 { 1363 struct adapter *adapter = iflib_get_softc(ctx); 1364 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1365 1366 if (adapter->hw.mac.type >= igb_mac_min) 1367 igb_rx_enable_queue(adapter, rxq); 1368 else 1369 em_rx_enable_queue(adapter, rxq); 1370 return (0); 1371 } 1372 1373 static int 1374 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1375 { 1376 struct adapter *adapter = iflib_get_softc(ctx); 1377 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1378 1379 if (adapter->hw.mac.type >= igb_mac_min) 1380 igb_tx_enable_queue(adapter, txq); 1381 else 1382 em_tx_enable_queue(adapter, txq); 1383 return (0); 1384 } 1385 1386 /********************************************************************* 1387 * 1388 * MSIX RX Interrupt Service routine 1389 * 1390 **********************************************************************/ 1391 static int 1392 em_msix_que(void *arg) 1393 { 1394 struct em_rx_queue *que = arg; 1395 1396 ++que->irqs; 1397 1398 return (FILTER_SCHEDULE_THREAD); 1399 } 1400 1401 /********************************************************************* 1402 * 1403 * MSIX Link Fast Interrupt Service routine 1404 * 1405 **********************************************************************/ 1406 static int 1407 em_msix_link(void *arg) 1408 { 1409 struct adapter *adapter = arg; 1410 u32 reg_icr; 1411 1412 ++adapter->link_irq; 1413 MPASS(adapter->hw.back != NULL); 1414 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1415 1416 if (reg_icr & E1000_ICR_RXO) 1417 adapter->rx_overruns++; 1418 1419 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1420 em_handle_link(adapter->ctx); 1421 } else { 1422 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1423 EM_MSIX_LINK | E1000_IMS_LSC); 1424 if (adapter->hw.mac.type >= igb_mac_min) 1425 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1426 } 1427 1428 /* 1429 * Because we must read the ICR for this interrupt 1430 * it may clear other causes using autoclear, for 1431 * this reason we simply create a soft interrupt 1432 * for all these vectors. 1433 */ 1434 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1435 E1000_WRITE_REG(&adapter->hw, 1436 E1000_ICS, adapter->ims); 1437 } 1438 1439 return (FILTER_HANDLED); 1440 } 1441 1442 static void 1443 em_handle_link(void *context) 1444 { 1445 if_ctx_t ctx = context; 1446 struct adapter *adapter = iflib_get_softc(ctx); 1447 1448 adapter->hw.mac.get_link_status = 1; 1449 iflib_admin_intr_deferred(ctx); 1450 } 1451 1452 1453 /********************************************************************* 1454 * 1455 * Media Ioctl callback 1456 * 1457 * This routine is called whenever the user queries the status of 1458 * the interface using ifconfig. 1459 * 1460 **********************************************************************/ 1461 static void 1462 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1463 { 1464 struct adapter *adapter = iflib_get_softc(ctx); 1465 u_char fiber_type = IFM_1000_SX; 1466 1467 INIT_DEBUGOUT("em_if_media_status: begin"); 1468 1469 iflib_admin_intr_deferred(ctx); 1470 1471 ifmr->ifm_status = IFM_AVALID; 1472 ifmr->ifm_active = IFM_ETHER; 1473 1474 if (!adapter->link_active) { 1475 return; 1476 } 1477 1478 ifmr->ifm_status |= IFM_ACTIVE; 1479 1480 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1481 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1482 if (adapter->hw.mac.type == e1000_82545) 1483 fiber_type = IFM_1000_LX; 1484 ifmr->ifm_active |= fiber_type | IFM_FDX; 1485 } else { 1486 switch (adapter->link_speed) { 1487 case 10: 1488 ifmr->ifm_active |= IFM_10_T; 1489 break; 1490 case 100: 1491 ifmr->ifm_active |= IFM_100_TX; 1492 break; 1493 case 1000: 1494 ifmr->ifm_active |= IFM_1000_T; 1495 break; 1496 } 1497 if (adapter->link_duplex == FULL_DUPLEX) 1498 ifmr->ifm_active |= IFM_FDX; 1499 else 1500 ifmr->ifm_active |= IFM_HDX; 1501 } 1502 } 1503 1504 /********************************************************************* 1505 * 1506 * Media Ioctl callback 1507 * 1508 * This routine is called when the user changes speed/duplex using 1509 * media/mediopt option with ifconfig. 1510 * 1511 **********************************************************************/ 1512 static int 1513 em_if_media_change(if_ctx_t ctx) 1514 { 1515 struct adapter *adapter = iflib_get_softc(ctx); 1516 struct ifmedia *ifm = iflib_get_media(ctx); 1517 1518 INIT_DEBUGOUT("em_if_media_change: begin"); 1519 1520 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1521 return (EINVAL); 1522 1523 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1524 case IFM_AUTO: 1525 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1526 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1527 break; 1528 case IFM_1000_LX: 1529 case IFM_1000_SX: 1530 case IFM_1000_T: 1531 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1532 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1533 break; 1534 case IFM_100_TX: 1535 adapter->hw.mac.autoneg = FALSE; 1536 adapter->hw.phy.autoneg_advertised = 0; 1537 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1538 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1539 else 1540 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1541 break; 1542 case IFM_10_T: 1543 adapter->hw.mac.autoneg = FALSE; 1544 adapter->hw.phy.autoneg_advertised = 0; 1545 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1546 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1547 else 1548 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1549 break; 1550 default: 1551 device_printf(adapter->dev, "Unsupported media type\n"); 1552 } 1553 1554 em_if_init(ctx); 1555 1556 return (0); 1557 } 1558 1559 static int 1560 em_if_set_promisc(if_ctx_t ctx, int flags) 1561 { 1562 struct adapter *adapter = iflib_get_softc(ctx); 1563 u32 reg_rctl; 1564 1565 em_disable_promisc(ctx); 1566 1567 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1568 1569 if (flags & IFF_PROMISC) { 1570 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1571 /* Turn this on if you want to see bad packets */ 1572 if (em_debug_sbp) 1573 reg_rctl |= E1000_RCTL_SBP; 1574 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1575 } else if (flags & IFF_ALLMULTI) { 1576 reg_rctl |= E1000_RCTL_MPE; 1577 reg_rctl &= ~E1000_RCTL_UPE; 1578 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1579 } 1580 return (0); 1581 } 1582 1583 static void 1584 em_disable_promisc(if_ctx_t ctx) 1585 { 1586 struct adapter *adapter = iflib_get_softc(ctx); 1587 struct ifnet *ifp = iflib_get_ifp(ctx); 1588 u32 reg_rctl; 1589 int mcnt = 0; 1590 1591 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1592 reg_rctl &= (~E1000_RCTL_UPE); 1593 if (if_getflags(ifp) & IFF_ALLMULTI) 1594 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1595 else 1596 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1597 /* Don't disable if in MAX groups */ 1598 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1599 reg_rctl &= (~E1000_RCTL_MPE); 1600 reg_rctl &= (~E1000_RCTL_SBP); 1601 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1602 } 1603 1604 1605 /********************************************************************* 1606 * Multicast Update 1607 * 1608 * This routine is called whenever multicast address list is updated. 1609 * 1610 **********************************************************************/ 1611 1612 static void 1613 em_if_multi_set(if_ctx_t ctx) 1614 { 1615 struct adapter *adapter = iflib_get_softc(ctx); 1616 struct ifnet *ifp = iflib_get_ifp(ctx); 1617 u32 reg_rctl = 0; 1618 u8 *mta; /* Multicast array memory */ 1619 int mcnt = 0; 1620 1621 IOCTL_DEBUGOUT("em_set_multi: begin"); 1622 1623 mta = adapter->mta; 1624 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1625 1626 if (adapter->hw.mac.type == e1000_82542 && 1627 adapter->hw.revision_id == E1000_REVISION_2) { 1628 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1629 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1630 e1000_pci_clear_mwi(&adapter->hw); 1631 reg_rctl |= E1000_RCTL_RST; 1632 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1633 msec_delay(5); 1634 } 1635 1636 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1637 1638 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1639 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1640 reg_rctl |= E1000_RCTL_MPE; 1641 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1642 } else 1643 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1644 1645 if (adapter->hw.mac.type == e1000_82542 && 1646 adapter->hw.revision_id == E1000_REVISION_2) { 1647 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1648 reg_rctl &= ~E1000_RCTL_RST; 1649 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1650 msec_delay(5); 1651 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1652 e1000_pci_set_mwi(&adapter->hw); 1653 } 1654 } 1655 1656 1657 /********************************************************************* 1658 * Timer routine 1659 * 1660 * This routine checks for link status and updates statistics. 1661 * 1662 **********************************************************************/ 1663 1664 static void 1665 em_if_timer(if_ctx_t ctx, uint16_t qid) 1666 { 1667 struct adapter *adapter = iflib_get_softc(ctx); 1668 struct em_rx_queue *que; 1669 int i; 1670 int trigger = 0; 1671 1672 if (qid != 0) 1673 return; 1674 1675 iflib_admin_intr_deferred(ctx); 1676 /* Reset LAA into RAR[0] on 82571 */ 1677 if ((adapter->hw.mac.type == e1000_82571) && 1678 e1000_get_laa_state_82571(&adapter->hw)) 1679 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1680 1681 if (adapter->hw.mac.type < em_mac_min) 1682 lem_smartspeed(adapter); 1683 1684 /* Mask to use in the irq trigger */ 1685 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1686 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1687 trigger |= que->eims; 1688 } else { 1689 trigger = E1000_ICS_RXDMT0; 1690 } 1691 } 1692 1693 1694 static void 1695 em_if_update_admin_status(if_ctx_t ctx) 1696 { 1697 struct adapter *adapter = iflib_get_softc(ctx); 1698 struct e1000_hw *hw = &adapter->hw; 1699 struct ifnet *ifp = iflib_get_ifp(ctx); 1700 device_t dev = iflib_get_dev(ctx); 1701 u32 link_check, thstat, ctrl; 1702 1703 link_check = thstat = ctrl = 0; 1704 /* Get the cached link value or read phy for real */ 1705 switch (hw->phy.media_type) { 1706 case e1000_media_type_copper: 1707 if (hw->mac.get_link_status) { 1708 if (hw->mac.type == e1000_pch_spt) 1709 msec_delay(50); 1710 /* Do the work to read phy */ 1711 e1000_check_for_link(hw); 1712 link_check = !hw->mac.get_link_status; 1713 if (link_check) /* ESB2 fix */ 1714 e1000_cfg_on_link_up(hw); 1715 } else { 1716 link_check = TRUE; 1717 } 1718 break; 1719 case e1000_media_type_fiber: 1720 e1000_check_for_link(hw); 1721 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1722 E1000_STATUS_LU); 1723 break; 1724 case e1000_media_type_internal_serdes: 1725 e1000_check_for_link(hw); 1726 link_check = adapter->hw.mac.serdes_has_link; 1727 break; 1728 /* VF device is type_unknown */ 1729 case e1000_media_type_unknown: 1730 e1000_check_for_link(hw); 1731 link_check = !hw->mac.get_link_status; 1732 /* FALLTHROUGH */ 1733 default: 1734 break; 1735 } 1736 1737 /* Check for thermal downshift or shutdown */ 1738 if (hw->mac.type == e1000_i350) { 1739 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1740 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1741 } 1742 1743 /* Now check for a transition */ 1744 if (link_check && (adapter->link_active == 0)) { 1745 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1746 &adapter->link_duplex); 1747 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1748 if ((adapter->link_speed != SPEED_1000) && 1749 ((hw->mac.type == e1000_82571) || 1750 (hw->mac.type == e1000_82572))) { 1751 int tarc0; 1752 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1753 tarc0 &= ~TARC_SPEED_MODE_BIT; 1754 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1755 } 1756 if (bootverbose) 1757 device_printf(dev, "Link is up %d Mbps %s\n", 1758 adapter->link_speed, 1759 ((adapter->link_duplex == FULL_DUPLEX) ? 1760 "Full Duplex" : "Half Duplex")); 1761 adapter->link_active = 1; 1762 adapter->smartspeed = 0; 1763 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1764 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && 1765 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1766 device_printf(dev, "Link: thermal downshift\n"); 1767 /* Delay Link Up for Phy update */ 1768 if (((hw->mac.type == e1000_i210) || 1769 (hw->mac.type == e1000_i211)) && 1770 (hw->phy.id == I210_I_PHY_ID)) 1771 msec_delay(I210_LINK_DELAY); 1772 /* Reset if the media type changed. */ 1773 if ((hw->dev_spec._82575.media_changed) && 1774 (adapter->hw.mac.type >= igb_mac_min)) { 1775 hw->dev_spec._82575.media_changed = false; 1776 adapter->flags |= IGB_MEDIA_RESET; 1777 em_reset(ctx); 1778 } 1779 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1780 printf("Link state changed to up\n"); 1781 } else if (!link_check && (adapter->link_active == 1)) { 1782 if_setbaudrate(ifp, 0); 1783 adapter->link_speed = 0; 1784 adapter->link_duplex = 0; 1785 if (bootverbose) 1786 device_printf(dev, "Link is Down\n"); 1787 adapter->link_active = 0; 1788 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1789 printf("link state changed to down\n"); 1790 } 1791 em_update_stats_counters(adapter); 1792 1793 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1794 } 1795 1796 /********************************************************************* 1797 * 1798 * This routine disables all traffic on the adapter by issuing a 1799 * global reset on the MAC and deallocates TX/RX buffers. 1800 * 1801 * This routine should always be called with BOTH the CORE 1802 * and TX locks. 1803 **********************************************************************/ 1804 1805 static void 1806 em_if_stop(if_ctx_t ctx) 1807 { 1808 struct adapter *adapter = iflib_get_softc(ctx); 1809 1810 INIT_DEBUGOUT("em_stop: begin"); 1811 1812 e1000_reset_hw(&adapter->hw); 1813 if (adapter->hw.mac.type >= e1000_82544) 1814 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1815 1816 e1000_led_off(&adapter->hw); 1817 e1000_cleanup_led(&adapter->hw); 1818 } 1819 1820 1821 /********************************************************************* 1822 * 1823 * Determine hardware revision. 1824 * 1825 **********************************************************************/ 1826 static void 1827 em_identify_hardware(if_ctx_t ctx) 1828 { 1829 device_t dev = iflib_get_dev(ctx); 1830 struct adapter *adapter = iflib_get_softc(ctx); 1831 1832 /* Make sure our PCI config space has the necessary stuff set */ 1833 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1834 1835 /* Save off the information about this board */ 1836 adapter->hw.vendor_id = pci_get_vendor(dev); 1837 adapter->hw.device_id = pci_get_device(dev); 1838 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1839 adapter->hw.subsystem_vendor_id = 1840 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1841 adapter->hw.subsystem_device_id = 1842 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1843 1844 /* Do Shared Code Init and Setup */ 1845 if (e1000_set_mac_type(&adapter->hw)) { 1846 device_printf(dev, "Setup init failure\n"); 1847 return; 1848 } 1849 } 1850 1851 static int 1852 em_allocate_pci_resources(if_ctx_t ctx) 1853 { 1854 struct adapter *adapter = iflib_get_softc(ctx); 1855 device_t dev = iflib_get_dev(ctx); 1856 int rid, val; 1857 1858 rid = PCIR_BAR(0); 1859 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1860 &rid, RF_ACTIVE); 1861 if (adapter->memory == NULL) { 1862 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1863 return (ENXIO); 1864 } 1865 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1866 adapter->osdep.mem_bus_space_handle = 1867 rman_get_bushandle(adapter->memory); 1868 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1869 1870 /* Only older adapters use IO mapping */ 1871 if (adapter->hw.mac.type < em_mac_min && 1872 adapter->hw.mac.type > e1000_82543) { 1873 /* Figure our where our IO BAR is ? */ 1874 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1875 val = pci_read_config(dev, rid, 4); 1876 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1877 adapter->io_rid = rid; 1878 break; 1879 } 1880 rid += 4; 1881 /* check for 64bit BAR */ 1882 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1883 rid += 4; 1884 } 1885 if (rid >= PCIR_CIS) { 1886 device_printf(dev, "Unable to locate IO BAR\n"); 1887 return (ENXIO); 1888 } 1889 adapter->ioport = bus_alloc_resource_any(dev, 1890 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1891 if (adapter->ioport == NULL) { 1892 device_printf(dev, "Unable to allocate bus resource: " 1893 "ioport\n"); 1894 return (ENXIO); 1895 } 1896 adapter->hw.io_base = 0; 1897 adapter->osdep.io_bus_space_tag = 1898 rman_get_bustag(adapter->ioport); 1899 adapter->osdep.io_bus_space_handle = 1900 rman_get_bushandle(adapter->ioport); 1901 } 1902 1903 adapter->hw.back = &adapter->osdep; 1904 1905 return (0); 1906 } 1907 1908 /********************************************************************* 1909 * 1910 * Setup the MSIX Interrupt handlers 1911 * 1912 **********************************************************************/ 1913 static int 1914 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1915 { 1916 struct adapter *adapter = iflib_get_softc(ctx); 1917 struct em_rx_queue *rx_que = adapter->rx_queues; 1918 struct em_tx_queue *tx_que = adapter->tx_queues; 1919 int error, rid, i, vector = 0, rx_vectors; 1920 char buf[16]; 1921 1922 /* First set up ring resources */ 1923 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1924 rid = vector + 1; 1925 snprintf(buf, sizeof(buf), "rxq%d", i); 1926 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1927 if (error) { 1928 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1929 adapter->rx_num_queues = i + 1; 1930 goto fail; 1931 } 1932 1933 rx_que->msix = vector; 1934 1935 /* 1936 * Set the bit to enable interrupt 1937 * in E1000_IMS -- bits 20 and 21 1938 * are for RX0 and RX1, note this has 1939 * NOTHING to do with the MSIX vector 1940 */ 1941 if (adapter->hw.mac.type == e1000_82574) { 1942 rx_que->eims = 1 << (20 + i); 1943 adapter->ims |= rx_que->eims; 1944 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1945 } else if (adapter->hw.mac.type == e1000_82575) 1946 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1947 else 1948 rx_que->eims = 1 << vector; 1949 } 1950 rx_vectors = vector; 1951 1952 vector = 0; 1953 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1954 rid = vector + 1; 1955 snprintf(buf, sizeof(buf), "txq%d", i); 1956 tx_que = &adapter->tx_queues[i]; 1957 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1958 1959 tx_que->msix = (vector % adapter->tx_num_queues); 1960 1961 /* 1962 * Set the bit to enable interrupt 1963 * in E1000_IMS -- bits 22 and 23 1964 * are for TX0 and TX1, note this has 1965 * NOTHING to do with the MSIX vector 1966 */ 1967 if (adapter->hw.mac.type == e1000_82574) { 1968 tx_que->eims = 1 << (22 + i); 1969 adapter->ims |= tx_que->eims; 1970 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1971 } else if (adapter->hw.mac.type == e1000_82575) { 1972 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1973 } else { 1974 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1975 } 1976 } 1977 1978 /* Link interrupt */ 1979 rid = rx_vectors + 1; 1980 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1981 1982 if (error) { 1983 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1984 goto fail; 1985 } 1986 adapter->linkvec = rx_vectors; 1987 if (adapter->hw.mac.type < igb_mac_min) { 1988 adapter->ivars |= (8 | rx_vectors) << 16; 1989 adapter->ivars |= 0x80000000; 1990 } 1991 return (0); 1992 fail: 1993 iflib_irq_free(ctx, &adapter->irq); 1994 rx_que = adapter->rx_queues; 1995 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1996 iflib_irq_free(ctx, &rx_que->que_irq); 1997 return (error); 1998 } 1999 2000 static void 2001 igb_configure_queues(struct adapter *adapter) 2002 { 2003 struct e1000_hw *hw = &adapter->hw; 2004 struct em_rx_queue *rx_que; 2005 struct em_tx_queue *tx_que; 2006 u32 tmp, ivar = 0, newitr = 0; 2007 2008 /* First turn on RSS capability */ 2009 if (adapter->hw.mac.type != e1000_82575) 2010 E1000_WRITE_REG(hw, E1000_GPIE, 2011 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2012 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2013 2014 /* Turn on MSIX */ 2015 switch (adapter->hw.mac.type) { 2016 case e1000_82580: 2017 case e1000_i350: 2018 case e1000_i354: 2019 case e1000_i210: 2020 case e1000_i211: 2021 case e1000_vfadapt: 2022 case e1000_vfadapt_i350: 2023 /* RX entries */ 2024 for (int i = 0; i < adapter->rx_num_queues; i++) { 2025 u32 index = i >> 1; 2026 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2027 rx_que = &adapter->rx_queues[i]; 2028 if (i & 1) { 2029 ivar &= 0xFF00FFFF; 2030 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2031 } else { 2032 ivar &= 0xFFFFFF00; 2033 ivar |= rx_que->msix | E1000_IVAR_VALID; 2034 } 2035 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2036 } 2037 /* TX entries */ 2038 for (int i = 0; i < adapter->tx_num_queues; i++) { 2039 u32 index = i >> 1; 2040 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2041 tx_que = &adapter->tx_queues[i]; 2042 if (i & 1) { 2043 ivar &= 0x00FFFFFF; 2044 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2045 } else { 2046 ivar &= 0xFFFF00FF; 2047 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2048 } 2049 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2050 adapter->que_mask |= tx_que->eims; 2051 } 2052 2053 /* And for the link interrupt */ 2054 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2055 adapter->link_mask = 1 << adapter->linkvec; 2056 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2057 break; 2058 case e1000_82576: 2059 /* RX entries */ 2060 for (int i = 0; i < adapter->rx_num_queues; i++) { 2061 u32 index = i & 0x7; /* Each IVAR has two entries */ 2062 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2063 rx_que = &adapter->rx_queues[i]; 2064 if (i < 8) { 2065 ivar &= 0xFFFFFF00; 2066 ivar |= rx_que->msix | E1000_IVAR_VALID; 2067 } else { 2068 ivar &= 0xFF00FFFF; 2069 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2070 } 2071 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2072 adapter->que_mask |= rx_que->eims; 2073 } 2074 /* TX entries */ 2075 for (int i = 0; i < adapter->tx_num_queues; i++) { 2076 u32 index = i & 0x7; /* Each IVAR has two entries */ 2077 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2078 tx_que = &adapter->tx_queues[i]; 2079 if (i < 8) { 2080 ivar &= 0xFFFF00FF; 2081 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2082 } else { 2083 ivar &= 0x00FFFFFF; 2084 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2085 } 2086 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2087 adapter->que_mask |= tx_que->eims; 2088 } 2089 2090 /* And for the link interrupt */ 2091 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2092 adapter->link_mask = 1 << adapter->linkvec; 2093 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2094 break; 2095 2096 case e1000_82575: 2097 /* enable MSI-X support*/ 2098 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2099 tmp |= E1000_CTRL_EXT_PBA_CLR; 2100 /* Auto-Mask interrupts upon ICR read. */ 2101 tmp |= E1000_CTRL_EXT_EIAME; 2102 tmp |= E1000_CTRL_EXT_IRCA; 2103 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2104 2105 /* Queues */ 2106 for (int i = 0; i < adapter->rx_num_queues; i++) { 2107 rx_que = &adapter->rx_queues[i]; 2108 tmp = E1000_EICR_RX_QUEUE0 << i; 2109 tmp |= E1000_EICR_TX_QUEUE0 << i; 2110 rx_que->eims = tmp; 2111 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2112 i, rx_que->eims); 2113 adapter->que_mask |= rx_que->eims; 2114 } 2115 2116 /* Link */ 2117 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2118 E1000_EIMS_OTHER); 2119 adapter->link_mask |= E1000_EIMS_OTHER; 2120 default: 2121 break; 2122 } 2123 2124 /* Set the starting interrupt rate */ 2125 if (em_max_interrupt_rate > 0) 2126 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2127 2128 if (hw->mac.type == e1000_82575) 2129 newitr |= newitr << 16; 2130 else 2131 newitr |= E1000_EITR_CNT_IGNR; 2132 2133 for (int i = 0; i < adapter->rx_num_queues; i++) { 2134 rx_que = &adapter->rx_queues[i]; 2135 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2136 } 2137 2138 return; 2139 } 2140 2141 static void 2142 em_free_pci_resources(if_ctx_t ctx) 2143 { 2144 struct adapter *adapter = iflib_get_softc(ctx); 2145 struct em_rx_queue *que = adapter->rx_queues; 2146 device_t dev = iflib_get_dev(ctx); 2147 2148 /* Release all msix queue resources */ 2149 if (adapter->intr_type == IFLIB_INTR_MSIX) 2150 iflib_irq_free(ctx, &adapter->irq); 2151 2152 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2153 iflib_irq_free(ctx, &que->que_irq); 2154 } 2155 2156 /* First release all the interrupt resources */ 2157 if (adapter->memory != NULL) { 2158 bus_release_resource(dev, SYS_RES_MEMORY, 2159 PCIR_BAR(0), adapter->memory); 2160 adapter->memory = NULL; 2161 } 2162 2163 if (adapter->flash != NULL) { 2164 bus_release_resource(dev, SYS_RES_MEMORY, 2165 EM_FLASH, adapter->flash); 2166 adapter->flash = NULL; 2167 } 2168 if (adapter->ioport != NULL) 2169 bus_release_resource(dev, SYS_RES_IOPORT, 2170 adapter->io_rid, adapter->ioport); 2171 } 2172 2173 /* Setup MSI or MSI/X */ 2174 static int 2175 em_setup_msix(if_ctx_t ctx) 2176 { 2177 struct adapter *adapter = iflib_get_softc(ctx); 2178 2179 if (adapter->hw.mac.type == e1000_82574) { 2180 em_enable_vectors_82574(ctx); 2181 } 2182 return (0); 2183 } 2184 2185 /********************************************************************* 2186 * 2187 * Initialize the hardware to a configuration 2188 * as specified by the adapter structure. 2189 * 2190 **********************************************************************/ 2191 2192 static void 2193 lem_smartspeed(struct adapter *adapter) 2194 { 2195 u16 phy_tmp; 2196 2197 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2198 adapter->hw.mac.autoneg == 0 || 2199 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2200 return; 2201 2202 if (adapter->smartspeed == 0) { 2203 /* If Master/Slave config fault is asserted twice, 2204 * we assume back-to-back */ 2205 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2206 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2207 return; 2208 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2209 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2210 e1000_read_phy_reg(&adapter->hw, 2211 PHY_1000T_CTRL, &phy_tmp); 2212 if(phy_tmp & CR_1000T_MS_ENABLE) { 2213 phy_tmp &= ~CR_1000T_MS_ENABLE; 2214 e1000_write_phy_reg(&adapter->hw, 2215 PHY_1000T_CTRL, phy_tmp); 2216 adapter->smartspeed++; 2217 if(adapter->hw.mac.autoneg && 2218 !e1000_copper_link_autoneg(&adapter->hw) && 2219 !e1000_read_phy_reg(&adapter->hw, 2220 PHY_CONTROL, &phy_tmp)) { 2221 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2222 MII_CR_RESTART_AUTO_NEG); 2223 e1000_write_phy_reg(&adapter->hw, 2224 PHY_CONTROL, phy_tmp); 2225 } 2226 } 2227 } 2228 return; 2229 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2230 /* If still no link, perhaps using 2/3 pair cable */ 2231 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2232 phy_tmp |= CR_1000T_MS_ENABLE; 2233 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2234 if(adapter->hw.mac.autoneg && 2235 !e1000_copper_link_autoneg(&adapter->hw) && 2236 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2237 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2238 MII_CR_RESTART_AUTO_NEG); 2239 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2240 } 2241 } 2242 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2243 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2244 adapter->smartspeed = 0; 2245 } 2246 2247 /********************************************************************* 2248 * 2249 * Initialize the DMA Coalescing feature 2250 * 2251 **********************************************************************/ 2252 static void 2253 igb_init_dmac(struct adapter *adapter, u32 pba) 2254 { 2255 device_t dev = adapter->dev; 2256 struct e1000_hw *hw = &adapter->hw; 2257 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2258 u16 hwm; 2259 u16 max_frame_size; 2260 2261 if (hw->mac.type == e1000_i211) 2262 return; 2263 2264 max_frame_size = adapter->shared->isc_max_frame_size; 2265 if (hw->mac.type > e1000_82580) { 2266 2267 if (adapter->dmac == 0) { /* Disabling it */ 2268 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2269 return; 2270 } else 2271 device_printf(dev, "DMA Coalescing enabled\n"); 2272 2273 /* Set starting threshold */ 2274 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2275 2276 hwm = 64 * pba - max_frame_size / 16; 2277 if (hwm < 64 * (pba - 6)) 2278 hwm = 64 * (pba - 6); 2279 reg = E1000_READ_REG(hw, E1000_FCRTC); 2280 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2281 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2282 & E1000_FCRTC_RTH_COAL_MASK); 2283 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2284 2285 2286 dmac = pba - max_frame_size / 512; 2287 if (dmac < pba - 10) 2288 dmac = pba - 10; 2289 reg = E1000_READ_REG(hw, E1000_DMACR); 2290 reg &= ~E1000_DMACR_DMACTHR_MASK; 2291 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2292 & E1000_DMACR_DMACTHR_MASK); 2293 2294 /* transition to L0x or L1 if available..*/ 2295 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2296 2297 /* Check if status is 2.5Gb backplane connection 2298 * before configuration of watchdog timer, which is 2299 * in msec values in 12.8usec intervals 2300 * watchdog timer= msec values in 32usec intervals 2301 * for non 2.5Gb connection 2302 */ 2303 if (hw->mac.type == e1000_i354) { 2304 int status = E1000_READ_REG(hw, E1000_STATUS); 2305 if ((status & E1000_STATUS_2P5_SKU) && 2306 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2307 reg |= ((adapter->dmac * 5) >> 6); 2308 else 2309 reg |= (adapter->dmac >> 5); 2310 } else { 2311 reg |= (adapter->dmac >> 5); 2312 } 2313 2314 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2315 2316 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2317 2318 /* Set the interval before transition */ 2319 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2320 if (hw->mac.type == e1000_i350) 2321 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2322 /* 2323 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2324 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2325 */ 2326 if (hw->mac.type == e1000_i354) { 2327 int status = E1000_READ_REG(hw, E1000_STATUS); 2328 if ((status & E1000_STATUS_2P5_SKU) && 2329 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2330 reg |= 0xA; 2331 else 2332 reg |= 0x4; 2333 } else { 2334 reg |= 0x4; 2335 } 2336 2337 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2338 2339 /* free space in tx packet buffer to wake from DMA coal */ 2340 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2341 (2 * max_frame_size)) >> 6); 2342 2343 /* make low power state decision controlled by DMA coal */ 2344 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2345 reg &= ~E1000_PCIEMISC_LX_DECISION; 2346 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2347 2348 } else if (hw->mac.type == e1000_82580) { 2349 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2350 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2351 reg & ~E1000_PCIEMISC_LX_DECISION); 2352 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2353 } 2354 } 2355 2356 static void 2357 em_reset(if_ctx_t ctx) 2358 { 2359 device_t dev = iflib_get_dev(ctx); 2360 struct adapter *adapter = iflib_get_softc(ctx); 2361 struct ifnet *ifp = iflib_get_ifp(ctx); 2362 struct e1000_hw *hw = &adapter->hw; 2363 u16 rx_buffer_size; 2364 u32 pba; 2365 2366 INIT_DEBUGOUT("em_reset: begin"); 2367 /* Let the firmware know the OS is in control */ 2368 em_get_hw_control(adapter); 2369 2370 /* Set up smart power down as default off on newer adapters. */ 2371 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2372 hw->mac.type == e1000_82572)) { 2373 u16 phy_tmp = 0; 2374 2375 /* Speed up time to link by disabling smart power down. */ 2376 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2377 phy_tmp &= ~IGP02E1000_PM_SPD; 2378 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2379 } 2380 2381 /* 2382 * Packet Buffer Allocation (PBA) 2383 * Writing PBA sets the receive portion of the buffer 2384 * the remainder is used for the transmit buffer. 2385 */ 2386 switch (hw->mac.type) { 2387 /* Total Packet Buffer on these is 48K */ 2388 case e1000_82571: 2389 case e1000_82572: 2390 case e1000_80003es2lan: 2391 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2392 break; 2393 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2394 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2395 break; 2396 case e1000_82574: 2397 case e1000_82583: 2398 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2399 break; 2400 case e1000_ich8lan: 2401 pba = E1000_PBA_8K; 2402 break; 2403 case e1000_ich9lan: 2404 case e1000_ich10lan: 2405 /* Boost Receive side for jumbo frames */ 2406 if (adapter->hw.mac.max_frame_size > 4096) 2407 pba = E1000_PBA_14K; 2408 else 2409 pba = E1000_PBA_10K; 2410 break; 2411 case e1000_pchlan: 2412 case e1000_pch2lan: 2413 case e1000_pch_lpt: 2414 case e1000_pch_spt: 2415 pba = E1000_PBA_26K; 2416 break; 2417 case e1000_82575: 2418 pba = E1000_PBA_32K; 2419 break; 2420 case e1000_82576: 2421 case e1000_vfadapt: 2422 pba = E1000_READ_REG(hw, E1000_RXPBS); 2423 pba &= E1000_RXPBS_SIZE_MASK_82576; 2424 break; 2425 case e1000_82580: 2426 case e1000_i350: 2427 case e1000_i354: 2428 case e1000_vfadapt_i350: 2429 pba = E1000_READ_REG(hw, E1000_RXPBS); 2430 pba = e1000_rxpbs_adjust_82580(pba); 2431 break; 2432 case e1000_i210: 2433 case e1000_i211: 2434 pba = E1000_PBA_34K; 2435 break; 2436 default: 2437 if (adapter->hw.mac.max_frame_size > 8192) 2438 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2439 else 2440 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2441 } 2442 2443 /* Special needs in case of Jumbo frames */ 2444 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2445 u32 tx_space, min_tx, min_rx; 2446 pba = E1000_READ_REG(hw, E1000_PBA); 2447 tx_space = pba >> 16; 2448 pba &= 0xffff; 2449 min_tx = (adapter->hw.mac.max_frame_size + 2450 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2451 min_tx = roundup2(min_tx, 1024); 2452 min_tx >>= 10; 2453 min_rx = adapter->hw.mac.max_frame_size; 2454 min_rx = roundup2(min_rx, 1024); 2455 min_rx >>= 10; 2456 if (tx_space < min_tx && 2457 ((min_tx - tx_space) < pba)) { 2458 pba = pba - (min_tx - tx_space); 2459 /* 2460 * if short on rx space, rx wins 2461 * and must trump tx adjustment 2462 */ 2463 if (pba < min_rx) 2464 pba = min_rx; 2465 } 2466 E1000_WRITE_REG(hw, E1000_PBA, pba); 2467 } 2468 2469 if (hw->mac.type < igb_mac_min) 2470 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2471 2472 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2473 2474 /* 2475 * These parameters control the automatic generation (Tx) and 2476 * response (Rx) to Ethernet PAUSE frames. 2477 * - High water mark should allow for at least two frames to be 2478 * received after sending an XOFF. 2479 * - Low water mark works best when it is very near the high water mark. 2480 * This allows the receiver to restart by sending XON when it has 2481 * drained a bit. Here we use an arbitrary value of 1500 which will 2482 * restart after one full frame is pulled from the buffer. There 2483 * could be several smaller frames in the buffer and if so they will 2484 * not trigger the XON until their total number reduces the buffer 2485 * by 1500. 2486 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2487 */ 2488 rx_buffer_size = (pba & 0xffff) << 10; 2489 hw->fc.high_water = rx_buffer_size - 2490 roundup2(adapter->hw.mac.max_frame_size, 1024); 2491 hw->fc.low_water = hw->fc.high_water - 1500; 2492 2493 if (adapter->fc) /* locally set flow control value? */ 2494 hw->fc.requested_mode = adapter->fc; 2495 else 2496 hw->fc.requested_mode = e1000_fc_full; 2497 2498 if (hw->mac.type == e1000_80003es2lan) 2499 hw->fc.pause_time = 0xFFFF; 2500 else 2501 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2502 2503 hw->fc.send_xon = TRUE; 2504 2505 /* Device specific overrides/settings */ 2506 switch (hw->mac.type) { 2507 case e1000_pchlan: 2508 /* Workaround: no TX flow ctrl for PCH */ 2509 hw->fc.requested_mode = e1000_fc_rx_pause; 2510 hw->fc.pause_time = 0xFFFF; /* override */ 2511 if (if_getmtu(ifp) > ETHERMTU) { 2512 hw->fc.high_water = 0x3500; 2513 hw->fc.low_water = 0x1500; 2514 } else { 2515 hw->fc.high_water = 0x5000; 2516 hw->fc.low_water = 0x3000; 2517 } 2518 hw->fc.refresh_time = 0x1000; 2519 break; 2520 case e1000_pch2lan: 2521 case e1000_pch_lpt: 2522 case e1000_pch_spt: 2523 hw->fc.high_water = 0x5C20; 2524 hw->fc.low_water = 0x5048; 2525 hw->fc.pause_time = 0x0650; 2526 hw->fc.refresh_time = 0x0400; 2527 /* Jumbos need adjusted PBA */ 2528 if (if_getmtu(ifp) > ETHERMTU) 2529 E1000_WRITE_REG(hw, E1000_PBA, 12); 2530 else 2531 E1000_WRITE_REG(hw, E1000_PBA, 26); 2532 break; 2533 case e1000_82575: 2534 case e1000_82576: 2535 /* 8-byte granularity */ 2536 hw->fc.low_water = hw->fc.high_water - 8; 2537 break; 2538 case e1000_82580: 2539 case e1000_i350: 2540 case e1000_i354: 2541 case e1000_i210: 2542 case e1000_i211: 2543 case e1000_vfadapt: 2544 case e1000_vfadapt_i350: 2545 /* 16-byte granularity */ 2546 hw->fc.low_water = hw->fc.high_water - 16; 2547 break; 2548 case e1000_ich9lan: 2549 case e1000_ich10lan: 2550 if (if_getmtu(ifp) > ETHERMTU) { 2551 hw->fc.high_water = 0x2800; 2552 hw->fc.low_water = hw->fc.high_water - 8; 2553 break; 2554 } 2555 /* FALLTHROUGH */ 2556 default: 2557 if (hw->mac.type == e1000_80003es2lan) 2558 hw->fc.pause_time = 0xFFFF; 2559 break; 2560 } 2561 2562 /* Issue a global reset */ 2563 e1000_reset_hw(hw); 2564 if (adapter->hw.mac.type >= igb_mac_min) { 2565 E1000_WRITE_REG(hw, E1000_WUC, 0); 2566 } else { 2567 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2568 em_disable_aspm(adapter); 2569 } 2570 if (adapter->flags & IGB_MEDIA_RESET) { 2571 e1000_setup_init_funcs(hw, TRUE); 2572 e1000_get_bus_info(hw); 2573 adapter->flags &= ~IGB_MEDIA_RESET; 2574 } 2575 /* and a re-init */ 2576 if (e1000_init_hw(hw) < 0) { 2577 device_printf(dev, "Hardware Initialization Failed\n"); 2578 return; 2579 } 2580 if (adapter->hw.mac.type >= igb_mac_min) 2581 igb_init_dmac(adapter, pba); 2582 2583 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2584 e1000_get_phy_info(hw); 2585 e1000_check_for_link(hw); 2586 } 2587 2588 #define RSSKEYLEN 10 2589 static void 2590 em_initialize_rss_mapping(struct adapter *adapter) 2591 { 2592 uint8_t rss_key[4 * RSSKEYLEN]; 2593 uint32_t reta = 0; 2594 struct e1000_hw *hw = &adapter->hw; 2595 int i; 2596 2597 /* 2598 * Configure RSS key 2599 */ 2600 arc4rand(rss_key, sizeof(rss_key), 0); 2601 for (i = 0; i < RSSKEYLEN; ++i) { 2602 uint32_t rssrk = 0; 2603 2604 rssrk = EM_RSSRK_VAL(rss_key, i); 2605 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2606 } 2607 2608 /* 2609 * Configure RSS redirect table in following fashion: 2610 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2611 */ 2612 for (i = 0; i < sizeof(reta); ++i) { 2613 uint32_t q; 2614 2615 q = (i % adapter->rx_num_queues) << 7; 2616 reta |= q << (8 * i); 2617 } 2618 2619 for (i = 0; i < 32; ++i) 2620 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2621 2622 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2623 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2624 E1000_MRQC_RSS_FIELD_IPV4 | 2625 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2626 E1000_MRQC_RSS_FIELD_IPV6_EX | 2627 E1000_MRQC_RSS_FIELD_IPV6); 2628 2629 } 2630 2631 static void 2632 igb_initialize_rss_mapping(struct adapter *adapter) 2633 { 2634 struct e1000_hw *hw = &adapter->hw; 2635 int i; 2636 int queue_id; 2637 u32 reta; 2638 u32 rss_key[10], mrqc, shift = 0; 2639 2640 /* XXX? */ 2641 if (adapter->hw.mac.type == e1000_82575) 2642 shift = 6; 2643 2644 /* 2645 * The redirection table controls which destination 2646 * queue each bucket redirects traffic to. 2647 * Each DWORD represents four queues, with the LSB 2648 * being the first queue in the DWORD. 2649 * 2650 * This just allocates buckets to queues using round-robin 2651 * allocation. 2652 * 2653 * NOTE: It Just Happens to line up with the default 2654 * RSS allocation method. 2655 */ 2656 2657 /* Warning FM follows */ 2658 reta = 0; 2659 for (i = 0; i < 128; i++) { 2660 #ifdef RSS 2661 queue_id = rss_get_indirection_to_bucket(i); 2662 /* 2663 * If we have more queues than buckets, we'll 2664 * end up mapping buckets to a subset of the 2665 * queues. 2666 * 2667 * If we have more buckets than queues, we'll 2668 * end up instead assigning multiple buckets 2669 * to queues. 2670 * 2671 * Both are suboptimal, but we need to handle 2672 * the case so we don't go out of bounds 2673 * indexing arrays and such. 2674 */ 2675 queue_id = queue_id % adapter->rx_num_queues; 2676 #else 2677 queue_id = (i % adapter->rx_num_queues); 2678 #endif 2679 /* Adjust if required */ 2680 queue_id = queue_id << shift; 2681 2682 /* 2683 * The low 8 bits are for hash value (n+0); 2684 * The next 8 bits are for hash value (n+1), etc. 2685 */ 2686 reta = reta >> 8; 2687 reta = reta | ( ((uint32_t) queue_id) << 24); 2688 if ((i & 3) == 3) { 2689 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2690 reta = 0; 2691 } 2692 } 2693 2694 /* Now fill in hash table */ 2695 2696 /* 2697 * MRQC: Multiple Receive Queues Command 2698 * Set queuing to RSS control, number depends on the device. 2699 */ 2700 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2701 2702 #ifdef RSS 2703 /* XXX ew typecasting */ 2704 rss_getkey((uint8_t *) &rss_key); 2705 #else 2706 arc4rand(&rss_key, sizeof(rss_key), 0); 2707 #endif 2708 for (i = 0; i < 10; i++) 2709 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2710 2711 /* 2712 * Configure the RSS fields to hash upon. 2713 */ 2714 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2715 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2716 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2717 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2718 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2719 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2720 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2721 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2722 2723 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2724 } 2725 2726 /********************************************************************* 2727 * 2728 * Setup networking device structure and register an interface. 2729 * 2730 **********************************************************************/ 2731 static int 2732 em_setup_interface(if_ctx_t ctx) 2733 { 2734 struct ifnet *ifp = iflib_get_ifp(ctx); 2735 struct adapter *adapter = iflib_get_softc(ctx); 2736 if_softc_ctx_t scctx = adapter->shared; 2737 uint64_t cap = 0; 2738 2739 INIT_DEBUGOUT("em_setup_interface: begin"); 2740 2741 /* TSO parameters */ 2742 if_sethwtsomax(ifp, IP_MAXPACKET); 2743 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2744 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2745 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2746 2747 /* Single Queue */ 2748 if (adapter->tx_num_queues == 1) { 2749 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2750 if_setsendqready(ifp); 2751 } 2752 2753 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2754 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2755 2756 /* 2757 * Tell the upper layer(s) we 2758 * support full VLAN capability 2759 */ 2760 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2761 if_setcapabilitiesbit(ifp, cap, 0); 2762 2763 /* 2764 * Don't turn this on by default, if vlans are 2765 * created on another pseudo device (eg. lagg) 2766 * then vlan events are not passed thru, breaking 2767 * operation, but with HW FILTER off it works. If 2768 * using vlans directly on the em driver you can 2769 * enable this and get full hardware tag filtering. 2770 */ 2771 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2772 2773 /* Enable only WOL MAGIC by default */ 2774 if (adapter->wol) { 2775 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2776 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2777 } else { 2778 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2779 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2780 } 2781 2782 /* 2783 * Specify the media types supported by this adapter and register 2784 * callbacks to update media and link information 2785 */ 2786 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2787 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2788 u_char fiber_type = IFM_1000_SX; /* default type */ 2789 2790 if (adapter->hw.mac.type == e1000_82545) 2791 fiber_type = IFM_1000_LX; 2792 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2793 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2794 } else { 2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2796 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2797 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2798 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2799 if (adapter->hw.phy.type != e1000_phy_ife) { 2800 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2801 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2802 } 2803 } 2804 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2805 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2806 return (0); 2807 } 2808 2809 static int 2810 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2811 { 2812 struct adapter *adapter = iflib_get_softc(ctx); 2813 if_softc_ctx_t scctx = adapter->shared; 2814 int error = E1000_SUCCESS; 2815 struct em_tx_queue *que; 2816 int i, j; 2817 2818 MPASS(adapter->tx_num_queues > 0); 2819 MPASS(adapter->tx_num_queues == ntxqsets); 2820 2821 /* First allocate the top level queue structs */ 2822 if (!(adapter->tx_queues = 2823 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2824 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2825 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2826 return(ENOMEM); 2827 } 2828 2829 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2830 /* Set up some basics */ 2831 2832 struct tx_ring *txr = &que->txr; 2833 txr->adapter = que->adapter = adapter; 2834 que->me = txr->me = i; 2835 2836 /* Allocate report status array */ 2837 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2838 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2839 error = ENOMEM; 2840 goto fail; 2841 } 2842 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2843 txr->tx_rsq[j] = QIDX_INVALID; 2844 /* get the virtual and physical address of the hardware queues */ 2845 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2846 txr->tx_paddr = paddrs[i*ntxqs]; 2847 } 2848 2849 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2850 return (0); 2851 fail: 2852 em_if_queues_free(ctx); 2853 return (error); 2854 } 2855 2856 static int 2857 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2858 { 2859 struct adapter *adapter = iflib_get_softc(ctx); 2860 int error = E1000_SUCCESS; 2861 struct em_rx_queue *que; 2862 int i; 2863 2864 MPASS(adapter->rx_num_queues > 0); 2865 MPASS(adapter->rx_num_queues == nrxqsets); 2866 2867 /* First allocate the top level queue structs */ 2868 if (!(adapter->rx_queues = 2869 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2870 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2871 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2872 error = ENOMEM; 2873 goto fail; 2874 } 2875 2876 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2877 /* Set up some basics */ 2878 struct rx_ring *rxr = &que->rxr; 2879 rxr->adapter = que->adapter = adapter; 2880 rxr->que = que; 2881 que->me = rxr->me = i; 2882 2883 /* get the virtual and physical address of the hardware queues */ 2884 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2885 rxr->rx_paddr = paddrs[i*nrxqs]; 2886 } 2887 2888 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2889 2890 return (0); 2891 fail: 2892 em_if_queues_free(ctx); 2893 return (error); 2894 } 2895 2896 static void 2897 em_if_queues_free(if_ctx_t ctx) 2898 { 2899 struct adapter *adapter = iflib_get_softc(ctx); 2900 struct em_tx_queue *tx_que = adapter->tx_queues; 2901 struct em_rx_queue *rx_que = adapter->rx_queues; 2902 2903 if (tx_que != NULL) { 2904 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2905 struct tx_ring *txr = &tx_que->txr; 2906 if (txr->tx_rsq == NULL) 2907 break; 2908 2909 free(txr->tx_rsq, M_DEVBUF); 2910 txr->tx_rsq = NULL; 2911 } 2912 free(adapter->tx_queues, M_DEVBUF); 2913 adapter->tx_queues = NULL; 2914 } 2915 2916 if (rx_que != NULL) { 2917 free(adapter->rx_queues, M_DEVBUF); 2918 adapter->rx_queues = NULL; 2919 } 2920 2921 em_release_hw_control(adapter); 2922 2923 if (adapter->mta != NULL) { 2924 free(adapter->mta, M_DEVBUF); 2925 } 2926 } 2927 2928 /********************************************************************* 2929 * 2930 * Enable transmit unit. 2931 * 2932 **********************************************************************/ 2933 static void 2934 em_initialize_transmit_unit(if_ctx_t ctx) 2935 { 2936 struct adapter *adapter = iflib_get_softc(ctx); 2937 if_softc_ctx_t scctx = adapter->shared; 2938 struct em_tx_queue *que; 2939 struct tx_ring *txr; 2940 struct e1000_hw *hw = &adapter->hw; 2941 u32 tctl, txdctl = 0, tarc, tipg = 0; 2942 2943 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2944 2945 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2946 u64 bus_addr; 2947 caddr_t offp, endp; 2948 2949 que = &adapter->tx_queues[i]; 2950 txr = &que->txr; 2951 bus_addr = txr->tx_paddr; 2952 2953 /* Clear checksum offload context. */ 2954 offp = (caddr_t)&txr->csum_flags; 2955 endp = (caddr_t)(txr + 1); 2956 bzero(offp, endp - offp); 2957 2958 /* Base and Len of TX Ring */ 2959 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2960 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2961 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2962 (u32)(bus_addr >> 32)); 2963 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2964 (u32)bus_addr); 2965 /* Init the HEAD/TAIL indices */ 2966 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2967 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2968 2969 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2970 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2971 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2972 2973 txdctl = 0; /* clear txdctl */ 2974 txdctl |= 0x1f; /* PTHRESH */ 2975 txdctl |= 1 << 8; /* HTHRESH */ 2976 txdctl |= 1 << 16;/* WTHRESH */ 2977 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2978 txdctl |= E1000_TXDCTL_GRAN; 2979 txdctl |= 1 << 25; /* LWTHRESH */ 2980 2981 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2982 } 2983 2984 /* Set the default values for the Tx Inter Packet Gap timer */ 2985 switch (adapter->hw.mac.type) { 2986 case e1000_80003es2lan: 2987 tipg = DEFAULT_82543_TIPG_IPGR1; 2988 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2989 E1000_TIPG_IPGR2_SHIFT; 2990 break; 2991 case e1000_82542: 2992 tipg = DEFAULT_82542_TIPG_IPGT; 2993 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2994 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2995 break; 2996 default: 2997 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2998 (adapter->hw.phy.media_type == 2999 e1000_media_type_internal_serdes)) 3000 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3001 else 3002 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3003 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3004 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3005 } 3006 3007 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3008 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3009 3010 if(adapter->hw.mac.type >= e1000_82540) 3011 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3012 adapter->tx_abs_int_delay.value); 3013 3014 if ((adapter->hw.mac.type == e1000_82571) || 3015 (adapter->hw.mac.type == e1000_82572)) { 3016 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3017 tarc |= TARC_SPEED_MODE_BIT; 3018 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3019 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3020 /* errata: program both queues to unweighted RR */ 3021 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3022 tarc |= 1; 3023 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3024 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3025 tarc |= 1; 3026 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3027 } else if (adapter->hw.mac.type == e1000_82574) { 3028 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3029 tarc |= TARC_ERRATA_BIT; 3030 if ( adapter->tx_num_queues > 1) { 3031 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3032 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3033 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3034 } else 3035 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3036 } 3037 3038 if (adapter->tx_int_delay.value > 0) 3039 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3040 3041 /* Program the Transmit Control Register */ 3042 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3043 tctl &= ~E1000_TCTL_CT; 3044 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3045 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3046 3047 if (adapter->hw.mac.type >= e1000_82571) 3048 tctl |= E1000_TCTL_MULR; 3049 3050 /* This write will effectively turn on the transmit unit. */ 3051 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3052 3053 if (hw->mac.type == e1000_pch_spt) { 3054 u32 reg; 3055 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3056 reg |= E1000_RCTL_RDMTS_HEX; 3057 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3058 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3059 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 3060 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3061 } 3062 } 3063 3064 /********************************************************************* 3065 * 3066 * Enable receive unit. 3067 * 3068 **********************************************************************/ 3069 3070 static void 3071 em_initialize_receive_unit(if_ctx_t ctx) 3072 { 3073 struct adapter *adapter = iflib_get_softc(ctx); 3074 if_softc_ctx_t scctx = adapter->shared; 3075 struct ifnet *ifp = iflib_get_ifp(ctx); 3076 struct e1000_hw *hw = &adapter->hw; 3077 struct em_rx_queue *que; 3078 int i; 3079 u32 rctl, rxcsum, rfctl; 3080 3081 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3082 3083 /* 3084 * Make sure receives are disabled while setting 3085 * up the descriptor ring 3086 */ 3087 rctl = E1000_READ_REG(hw, E1000_RCTL); 3088 /* Do not disable if ever enabled on this hardware */ 3089 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3090 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3091 3092 /* Setup the Receive Control Register */ 3093 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3094 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3095 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3096 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3097 3098 /* Do not store bad packets */ 3099 rctl &= ~E1000_RCTL_SBP; 3100 3101 /* Enable Long Packet receive */ 3102 if (if_getmtu(ifp) > ETHERMTU) 3103 rctl |= E1000_RCTL_LPE; 3104 else 3105 rctl &= ~E1000_RCTL_LPE; 3106 3107 /* Strip the CRC */ 3108 if (!em_disable_crc_stripping) 3109 rctl |= E1000_RCTL_SECRC; 3110 3111 if (adapter->hw.mac.type >= e1000_82540) { 3112 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3113 adapter->rx_abs_int_delay.value); 3114 3115 /* 3116 * Set the interrupt throttling rate. Value is calculated 3117 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3118 */ 3119 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3120 } 3121 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3122 adapter->rx_int_delay.value); 3123 3124 /* Use extended rx descriptor formats */ 3125 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3126 rfctl |= E1000_RFCTL_EXTEN; 3127 /* 3128 * When using MSIX interrupts we need to throttle 3129 * using the EITR register (82574 only) 3130 */ 3131 if (hw->mac.type == e1000_82574) { 3132 for (int i = 0; i < 4; i++) 3133 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3134 DEFAULT_ITR); 3135 /* Disable accelerated acknowledge */ 3136 rfctl |= E1000_RFCTL_ACK_DIS; 3137 } 3138 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3139 3140 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3141 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3142 adapter->hw.mac.type >= e1000_82543) { 3143 if (adapter->tx_num_queues > 1) { 3144 if (adapter->hw.mac.type >= igb_mac_min) { 3145 rxcsum |= E1000_RXCSUM_PCSD; 3146 if (hw->mac.type != e1000_82575) 3147 rxcsum |= E1000_RXCSUM_CRCOFL; 3148 } else 3149 rxcsum |= E1000_RXCSUM_TUOFL | 3150 E1000_RXCSUM_IPOFL | 3151 E1000_RXCSUM_PCSD; 3152 } else { 3153 if (adapter->hw.mac.type >= igb_mac_min) 3154 rxcsum |= E1000_RXCSUM_IPPCSE; 3155 else 3156 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3157 if (adapter->hw.mac.type > e1000_82575) 3158 rxcsum |= E1000_RXCSUM_CRCOFL; 3159 } 3160 } else 3161 rxcsum &= ~E1000_RXCSUM_TUOFL; 3162 3163 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3164 3165 if (adapter->rx_num_queues > 1) { 3166 if (adapter->hw.mac.type >= igb_mac_min) 3167 igb_initialize_rss_mapping(adapter); 3168 else 3169 em_initialize_rss_mapping(adapter); 3170 } 3171 3172 /* 3173 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3174 * long latencies are observed, like Lenovo X60. This 3175 * change eliminates the problem, but since having positive 3176 * values in RDTR is a known source of problems on other 3177 * platforms another solution is being sought. 3178 */ 3179 if (hw->mac.type == e1000_82573) 3180 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3181 3182 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3183 struct rx_ring *rxr = &que->rxr; 3184 /* Setup the Base and Length of the Rx Descriptor Ring */ 3185 u64 bus_addr = rxr->rx_paddr; 3186 #if 0 3187 u32 rdt = adapter->rx_num_queues -1; /* default */ 3188 #endif 3189 3190 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3191 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3192 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3193 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3194 /* Setup the Head and Tail Descriptor Pointers */ 3195 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3196 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3197 } 3198 3199 /* 3200 * Set PTHRESH for improved jumbo performance 3201 * According to 10.2.5.11 of Intel 82574 Datasheet, 3202 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3203 * Only write to RXDCTL(1) if there is a need for different 3204 * settings. 3205 */ 3206 3207 if (((adapter->hw.mac.type == e1000_ich9lan) || 3208 (adapter->hw.mac.type == e1000_pch2lan) || 3209 (adapter->hw.mac.type == e1000_ich10lan)) && 3210 (if_getmtu(ifp) > ETHERMTU)) { 3211 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3212 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3213 } else if (adapter->hw.mac.type == e1000_82574) { 3214 for (int i = 0; i < adapter->rx_num_queues; i++) { 3215 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3216 rxdctl |= 0x20; /* PTHRESH */ 3217 rxdctl |= 4 << 8; /* HTHRESH */ 3218 rxdctl |= 4 << 16;/* WTHRESH */ 3219 rxdctl |= 1 << 24; /* Switch to granularity */ 3220 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3221 } 3222 } else if (adapter->hw.mac.type >= igb_mac_min) { 3223 u32 psize, srrctl = 0; 3224 3225 if (if_getmtu(ifp) > ETHERMTU) { 3226 /* Set maximum packet len */ 3227 if (adapter->rx_mbuf_sz <= 4096) { 3228 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3229 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3230 } else if (adapter->rx_mbuf_sz > 4096) { 3231 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3232 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3233 } 3234 psize = scctx->isc_max_frame_size; 3235 /* are we on a vlan? */ 3236 if (ifp->if_vlantrunk != NULL) 3237 psize += VLAN_TAG_SIZE; 3238 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3239 } else { 3240 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3241 rctl |= E1000_RCTL_SZ_2048; 3242 } 3243 3244 /* 3245 * If TX flow control is disabled and there's >1 queue defined, 3246 * enable DROP. 3247 * 3248 * This drops frames rather than hanging the RX MAC for all queues. 3249 */ 3250 if ((adapter->rx_num_queues > 1) && 3251 (adapter->fc == e1000_fc_none || 3252 adapter->fc == e1000_fc_rx_pause)) { 3253 srrctl |= E1000_SRRCTL_DROP_EN; 3254 } 3255 /* Setup the Base and Length of the Rx Descriptor Rings */ 3256 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3257 struct rx_ring *rxr = &que->rxr; 3258 u64 bus_addr = rxr->rx_paddr; 3259 u32 rxdctl; 3260 3261 #ifdef notyet 3262 /* Configure for header split? -- ignore for now */ 3263 rxr->hdr_split = igb_header_split; 3264 #else 3265 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3266 #endif 3267 3268 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3269 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3270 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3271 (uint32_t)(bus_addr >> 32)); 3272 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3273 (uint32_t)bus_addr); 3274 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3275 /* Enable this Queue */ 3276 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3277 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3278 rxdctl &= 0xFFF00000; 3279 rxdctl |= IGB_RX_PTHRESH; 3280 rxdctl |= IGB_RX_HTHRESH << 8; 3281 rxdctl |= IGB_RX_WTHRESH << 16; 3282 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3283 } 3284 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3285 if (if_getmtu(ifp) > ETHERMTU) 3286 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3287 else 3288 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3289 } 3290 3291 /* Make sure VLAN Filters are off */ 3292 rctl &= ~E1000_RCTL_VFE; 3293 3294 if (adapter->hw.mac.type < igb_mac_min) { 3295 if (adapter->rx_mbuf_sz == MCLBYTES) 3296 rctl |= E1000_RCTL_SZ_2048; 3297 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3298 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3299 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3300 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3301 3302 /* ensure we clear use DTYPE of 00 here */ 3303 rctl &= ~0x00000C00; 3304 } 3305 3306 /* Write out the settings */ 3307 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3308 3309 return; 3310 } 3311 3312 static void 3313 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3314 { 3315 struct adapter *adapter = iflib_get_softc(ctx); 3316 u32 index, bit; 3317 3318 index = (vtag >> 5) & 0x7F; 3319 bit = vtag & 0x1F; 3320 adapter->shadow_vfta[index] |= (1 << bit); 3321 ++adapter->num_vlans; 3322 } 3323 3324 static void 3325 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3326 { 3327 struct adapter *adapter = iflib_get_softc(ctx); 3328 u32 index, bit; 3329 3330 index = (vtag >> 5) & 0x7F; 3331 bit = vtag & 0x1F; 3332 adapter->shadow_vfta[index] &= ~(1 << bit); 3333 --adapter->num_vlans; 3334 } 3335 3336 static void 3337 em_setup_vlan_hw_support(struct adapter *adapter) 3338 { 3339 struct e1000_hw *hw = &adapter->hw; 3340 u32 reg; 3341 3342 /* 3343 * We get here thru init_locked, meaning 3344 * a soft reset, this has already cleared 3345 * the VFTA and other state, so if there 3346 * have been no vlan's registered do nothing. 3347 */ 3348 if (adapter->num_vlans == 0) 3349 return; 3350 3351 /* 3352 * A soft reset zero's out the VFTA, so 3353 * we need to repopulate it now. 3354 */ 3355 for (int i = 0; i < EM_VFTA_SIZE; i++) 3356 if (adapter->shadow_vfta[i] != 0) 3357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3358 i, adapter->shadow_vfta[i]); 3359 3360 reg = E1000_READ_REG(hw, E1000_CTRL); 3361 reg |= E1000_CTRL_VME; 3362 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3363 3364 /* Enable the Filter Table */ 3365 reg = E1000_READ_REG(hw, E1000_RCTL); 3366 reg &= ~E1000_RCTL_CFIEN; 3367 reg |= E1000_RCTL_VFE; 3368 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3369 } 3370 3371 static void 3372 em_if_enable_intr(if_ctx_t ctx) 3373 { 3374 struct adapter *adapter = iflib_get_softc(ctx); 3375 struct e1000_hw *hw = &adapter->hw; 3376 u32 ims_mask = IMS_ENABLE_MASK; 3377 3378 if (hw->mac.type == e1000_82574) { 3379 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3380 ims_mask |= adapter->ims; 3381 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3382 u32 mask = (adapter->que_mask | adapter->link_mask); 3383 3384 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3385 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3386 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3387 ims_mask = E1000_IMS_LSC; 3388 } 3389 3390 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3391 } 3392 3393 static void 3394 em_if_disable_intr(if_ctx_t ctx) 3395 { 3396 struct adapter *adapter = iflib_get_softc(ctx); 3397 struct e1000_hw *hw = &adapter->hw; 3398 3399 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3400 if (hw->mac.type >= igb_mac_min) 3401 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3402 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3403 } 3404 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3405 } 3406 3407 /* 3408 * Bit of a misnomer, what this really means is 3409 * to enable OS management of the system... aka 3410 * to disable special hardware management features 3411 */ 3412 static void 3413 em_init_manageability(struct adapter *adapter) 3414 { 3415 /* A shared code workaround */ 3416 #define E1000_82542_MANC2H E1000_MANC2H 3417 if (adapter->has_manage) { 3418 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3419 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3420 3421 /* disable hardware interception of ARP */ 3422 manc &= ~(E1000_MANC_ARP_EN); 3423 3424 /* enable receiving management packets to the host */ 3425 manc |= E1000_MANC_EN_MNG2HOST; 3426 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3427 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3428 manc2h |= E1000_MNG2HOST_PORT_623; 3429 manc2h |= E1000_MNG2HOST_PORT_664; 3430 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3431 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3432 } 3433 } 3434 3435 /* 3436 * Give control back to hardware management 3437 * controller if there is one. 3438 */ 3439 static void 3440 em_release_manageability(struct adapter *adapter) 3441 { 3442 if (adapter->has_manage) { 3443 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3444 3445 /* re-enable hardware interception of ARP */ 3446 manc |= E1000_MANC_ARP_EN; 3447 manc &= ~E1000_MANC_EN_MNG2HOST; 3448 3449 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3450 } 3451 } 3452 3453 /* 3454 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3455 * For ASF and Pass Through versions of f/w this means 3456 * that the driver is loaded. For AMT version type f/w 3457 * this means that the network i/f is open. 3458 */ 3459 static void 3460 em_get_hw_control(struct adapter *adapter) 3461 { 3462 u32 ctrl_ext, swsm; 3463 3464 if (adapter->vf_ifp) 3465 return; 3466 3467 if (adapter->hw.mac.type == e1000_82573) { 3468 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3469 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3470 swsm | E1000_SWSM_DRV_LOAD); 3471 return; 3472 } 3473 /* else */ 3474 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3475 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3476 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3477 } 3478 3479 /* 3480 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3481 * For ASF and Pass Through versions of f/w this means that 3482 * the driver is no longer loaded. For AMT versions of the 3483 * f/w this means that the network i/f is closed. 3484 */ 3485 static void 3486 em_release_hw_control(struct adapter *adapter) 3487 { 3488 u32 ctrl_ext, swsm; 3489 3490 if (!adapter->has_manage) 3491 return; 3492 3493 if (adapter->hw.mac.type == e1000_82573) { 3494 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3495 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3496 swsm & ~E1000_SWSM_DRV_LOAD); 3497 return; 3498 } 3499 /* else */ 3500 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3501 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3502 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3503 return; 3504 } 3505 3506 static int 3507 em_is_valid_ether_addr(u8 *addr) 3508 { 3509 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3510 3511 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3512 return (FALSE); 3513 } 3514 3515 return (TRUE); 3516 } 3517 3518 /* 3519 ** Parse the interface capabilities with regard 3520 ** to both system management and wake-on-lan for 3521 ** later use. 3522 */ 3523 static void 3524 em_get_wakeup(if_ctx_t ctx) 3525 { 3526 struct adapter *adapter = iflib_get_softc(ctx); 3527 device_t dev = iflib_get_dev(ctx); 3528 u16 eeprom_data = 0, device_id, apme_mask; 3529 3530 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3531 apme_mask = EM_EEPROM_APME; 3532 3533 switch (adapter->hw.mac.type) { 3534 case e1000_82542: 3535 case e1000_82543: 3536 break; 3537 case e1000_82544: 3538 e1000_read_nvm(&adapter->hw, 3539 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3540 apme_mask = EM_82544_APME; 3541 break; 3542 case e1000_82546: 3543 case e1000_82546_rev_3: 3544 if (adapter->hw.bus.func == 1) { 3545 e1000_read_nvm(&adapter->hw, 3546 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3547 break; 3548 } else 3549 e1000_read_nvm(&adapter->hw, 3550 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3551 break; 3552 case e1000_82573: 3553 case e1000_82583: 3554 adapter->has_amt = TRUE; 3555 /* FALLTHROUGH */ 3556 case e1000_82571: 3557 case e1000_82572: 3558 case e1000_80003es2lan: 3559 if (adapter->hw.bus.func == 1) { 3560 e1000_read_nvm(&adapter->hw, 3561 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3562 break; 3563 } else 3564 e1000_read_nvm(&adapter->hw, 3565 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3566 break; 3567 case e1000_ich8lan: 3568 case e1000_ich9lan: 3569 case e1000_ich10lan: 3570 case e1000_pchlan: 3571 case e1000_pch2lan: 3572 case e1000_pch_lpt: 3573 case e1000_pch_spt: 3574 case e1000_82575: /* listing all igb devices */ 3575 case e1000_82576: 3576 case e1000_82580: 3577 case e1000_i350: 3578 case e1000_i354: 3579 case e1000_i210: 3580 case e1000_i211: 3581 case e1000_vfadapt: 3582 case e1000_vfadapt_i350: 3583 apme_mask = E1000_WUC_APME; 3584 adapter->has_amt = TRUE; 3585 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3586 break; 3587 default: 3588 e1000_read_nvm(&adapter->hw, 3589 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3590 break; 3591 } 3592 if (eeprom_data & apme_mask) 3593 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3594 /* 3595 * We have the eeprom settings, now apply the special cases 3596 * where the eeprom may be wrong or the board won't support 3597 * wake on lan on a particular port 3598 */ 3599 device_id = pci_get_device(dev); 3600 switch (device_id) { 3601 case E1000_DEV_ID_82546GB_PCIE: 3602 adapter->wol = 0; 3603 break; 3604 case E1000_DEV_ID_82546EB_FIBER: 3605 case E1000_DEV_ID_82546GB_FIBER: 3606 /* Wake events only supported on port A for dual fiber 3607 * regardless of eeprom setting */ 3608 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3609 E1000_STATUS_FUNC_1) 3610 adapter->wol = 0; 3611 break; 3612 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3613 /* if quad port adapter, disable WoL on all but port A */ 3614 if (global_quad_port_a != 0) 3615 adapter->wol = 0; 3616 /* Reset for multiple quad port adapters */ 3617 if (++global_quad_port_a == 4) 3618 global_quad_port_a = 0; 3619 break; 3620 case E1000_DEV_ID_82571EB_FIBER: 3621 /* Wake events only supported on port A for dual fiber 3622 * regardless of eeprom setting */ 3623 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3624 E1000_STATUS_FUNC_1) 3625 adapter->wol = 0; 3626 break; 3627 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3628 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3629 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3630 /* if quad port adapter, disable WoL on all but port A */ 3631 if (global_quad_port_a != 0) 3632 adapter->wol = 0; 3633 /* Reset for multiple quad port adapters */ 3634 if (++global_quad_port_a == 4) 3635 global_quad_port_a = 0; 3636 break; 3637 } 3638 return; 3639 } 3640 3641 3642 /* 3643 * Enable PCI Wake On Lan capability 3644 */ 3645 static void 3646 em_enable_wakeup(if_ctx_t ctx) 3647 { 3648 struct adapter *adapter = iflib_get_softc(ctx); 3649 device_t dev = iflib_get_dev(ctx); 3650 if_t ifp = iflib_get_ifp(ctx); 3651 int error = 0; 3652 u32 pmc, ctrl, ctrl_ext, rctl; 3653 u16 status; 3654 3655 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3656 return; 3657 3658 /* 3659 * Determine type of Wakeup: note that wol 3660 * is set with all bits on by default. 3661 */ 3662 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3663 adapter->wol &= ~E1000_WUFC_MAG; 3664 3665 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3666 adapter->wol &= ~E1000_WUFC_EX; 3667 3668 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3669 adapter->wol &= ~E1000_WUFC_MC; 3670 else { 3671 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3672 rctl |= E1000_RCTL_MPE; 3673 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3674 } 3675 3676 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3677 goto pme; 3678 3679 /* Advertise the wakeup capability */ 3680 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3681 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3682 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3683 3684 /* Keep the laser running on Fiber adapters */ 3685 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3686 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3687 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3688 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3689 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3690 } 3691 3692 if ((adapter->hw.mac.type == e1000_ich8lan) || 3693 (adapter->hw.mac.type == e1000_pchlan) || 3694 (adapter->hw.mac.type == e1000_ich9lan) || 3695 (adapter->hw.mac.type == e1000_ich10lan)) 3696 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3697 3698 if ( adapter->hw.mac.type >= e1000_pchlan) { 3699 error = em_enable_phy_wakeup(adapter); 3700 if (error) 3701 goto pme; 3702 } else { 3703 /* Enable wakeup by the MAC */ 3704 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3705 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3706 } 3707 3708 if (adapter->hw.phy.type == e1000_phy_igp_3) 3709 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3710 3711 pme: 3712 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3713 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3714 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3715 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3716 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3717 3718 return; 3719 } 3720 3721 /* 3722 * WOL in the newer chipset interfaces (pchlan) 3723 * require thing to be copied into the phy 3724 */ 3725 static int 3726 em_enable_phy_wakeup(struct adapter *adapter) 3727 { 3728 struct e1000_hw *hw = &adapter->hw; 3729 u32 mreg, ret = 0; 3730 u16 preg; 3731 3732 /* copy MAC RARs to PHY RARs */ 3733 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3734 3735 /* copy MAC MTA to PHY MTA */ 3736 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3737 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3738 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3739 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3740 (u16)((mreg >> 16) & 0xFFFF)); 3741 } 3742 3743 /* configure PHY Rx Control register */ 3744 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3745 mreg = E1000_READ_REG(hw, E1000_RCTL); 3746 if (mreg & E1000_RCTL_UPE) 3747 preg |= BM_RCTL_UPE; 3748 if (mreg & E1000_RCTL_MPE) 3749 preg |= BM_RCTL_MPE; 3750 preg &= ~(BM_RCTL_MO_MASK); 3751 if (mreg & E1000_RCTL_MO_3) 3752 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3753 << BM_RCTL_MO_SHIFT); 3754 if (mreg & E1000_RCTL_BAM) 3755 preg |= BM_RCTL_BAM; 3756 if (mreg & E1000_RCTL_PMCF) 3757 preg |= BM_RCTL_PMCF; 3758 mreg = E1000_READ_REG(hw, E1000_CTRL); 3759 if (mreg & E1000_CTRL_RFCE) 3760 preg |= BM_RCTL_RFCE; 3761 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3762 3763 /* enable PHY wakeup in MAC register */ 3764 E1000_WRITE_REG(hw, E1000_WUC, 3765 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3766 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3767 3768 /* configure and enable PHY wakeup in PHY registers */ 3769 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3770 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3771 3772 /* activate PHY wakeup */ 3773 ret = hw->phy.ops.acquire(hw); 3774 if (ret) { 3775 printf("Could not acquire PHY\n"); 3776 return ret; 3777 } 3778 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3779 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3780 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3781 if (ret) { 3782 printf("Could not read PHY page 769\n"); 3783 goto out; 3784 } 3785 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3786 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3787 if (ret) 3788 printf("Could not set PHY Host Wakeup bit\n"); 3789 out: 3790 hw->phy.ops.release(hw); 3791 3792 return ret; 3793 } 3794 3795 static void 3796 em_if_led_func(if_ctx_t ctx, int onoff) 3797 { 3798 struct adapter *adapter = iflib_get_softc(ctx); 3799 3800 if (onoff) { 3801 e1000_setup_led(&adapter->hw); 3802 e1000_led_on(&adapter->hw); 3803 } else { 3804 e1000_led_off(&adapter->hw); 3805 e1000_cleanup_led(&adapter->hw); 3806 } 3807 } 3808 3809 /* 3810 * Disable the L0S and L1 LINK states 3811 */ 3812 static void 3813 em_disable_aspm(struct adapter *adapter) 3814 { 3815 int base, reg; 3816 u16 link_cap,link_ctrl; 3817 device_t dev = adapter->dev; 3818 3819 switch (adapter->hw.mac.type) { 3820 case e1000_82573: 3821 case e1000_82574: 3822 case e1000_82583: 3823 break; 3824 default: 3825 return; 3826 } 3827 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3828 return; 3829 reg = base + PCIER_LINK_CAP; 3830 link_cap = pci_read_config(dev, reg, 2); 3831 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3832 return; 3833 reg = base + PCIER_LINK_CTL; 3834 link_ctrl = pci_read_config(dev, reg, 2); 3835 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3836 pci_write_config(dev, reg, link_ctrl, 2); 3837 return; 3838 } 3839 3840 /********************************************************************** 3841 * 3842 * Update the board statistics counters. 3843 * 3844 **********************************************************************/ 3845 static void 3846 em_update_stats_counters(struct adapter *adapter) 3847 { 3848 3849 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3850 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3851 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3852 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3853 } 3854 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3855 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3856 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3857 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3858 3859 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3860 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3861 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3862 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3863 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3864 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3865 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3866 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3867 /* 3868 ** For watchdog management we need to know if we have been 3869 ** paused during the last interval, so capture that here. 3870 */ 3871 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3872 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3873 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3874 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3875 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3876 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3877 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3878 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3879 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3880 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3881 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3882 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3883 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3884 3885 /* For the 64-bit byte counters the low dword must be read first. */ 3886 /* Both registers clear on the read of the high dword */ 3887 3888 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3889 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3890 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3891 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3892 3893 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3894 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3895 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3896 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3897 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3898 3899 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3900 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3901 3902 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3903 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3904 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3905 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3906 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3907 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3908 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3909 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3910 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3911 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3912 3913 /* Interrupt Counts */ 3914 3915 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3916 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3917 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3918 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3919 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3920 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3921 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3922 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3923 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3924 3925 if (adapter->hw.mac.type >= e1000_82543) { 3926 adapter->stats.algnerrc += 3927 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3928 adapter->stats.rxerrc += 3929 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3930 adapter->stats.tncrs += 3931 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3932 adapter->stats.cexterr += 3933 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3934 adapter->stats.tsctc += 3935 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3936 adapter->stats.tsctfc += 3937 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3938 } 3939 } 3940 3941 static uint64_t 3942 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3943 { 3944 struct adapter *adapter = iflib_get_softc(ctx); 3945 struct ifnet *ifp = iflib_get_ifp(ctx); 3946 3947 switch (cnt) { 3948 case IFCOUNTER_COLLISIONS: 3949 return (adapter->stats.colc); 3950 case IFCOUNTER_IERRORS: 3951 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3952 adapter->stats.crcerrs + adapter->stats.algnerrc + 3953 adapter->stats.ruc + adapter->stats.roc + 3954 adapter->stats.mpc + adapter->stats.cexterr); 3955 case IFCOUNTER_OERRORS: 3956 return (adapter->stats.ecol + adapter->stats.latecol + 3957 adapter->watchdog_events); 3958 default: 3959 return (if_get_counter_default(ifp, cnt)); 3960 } 3961 } 3962 3963 /* Export a single 32-bit register via a read-only sysctl. */ 3964 static int 3965 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3966 { 3967 struct adapter *adapter; 3968 u_int val; 3969 3970 adapter = oidp->oid_arg1; 3971 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3972 return (sysctl_handle_int(oidp, &val, 0, req)); 3973 } 3974 3975 /* 3976 * Add sysctl variables, one per statistic, to the system. 3977 */ 3978 static void 3979 em_add_hw_stats(struct adapter *adapter) 3980 { 3981 device_t dev = iflib_get_dev(adapter->ctx); 3982 struct em_tx_queue *tx_que = adapter->tx_queues; 3983 struct em_rx_queue *rx_que = adapter->rx_queues; 3984 3985 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3986 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3987 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3988 struct e1000_hw_stats *stats = &adapter->stats; 3989 3990 struct sysctl_oid *stat_node, *queue_node, *int_node; 3991 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3992 3993 #define QUEUE_NAME_LEN 32 3994 char namebuf[QUEUE_NAME_LEN]; 3995 3996 /* Driver Statistics */ 3997 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3998 CTLFLAG_RD, &adapter->dropped_pkts, 3999 "Driver dropped packets"); 4000 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4001 CTLFLAG_RD, &adapter->link_irq, 4002 "Link MSIX IRQ Handled"); 4003 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4004 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4005 "Defragmenting mbuf chain failed"); 4006 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4007 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4008 "Driver tx dma failure in xmit"); 4009 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4010 CTLFLAG_RD, &adapter->rx_overruns, 4011 "RX overruns"); 4012 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4013 CTLFLAG_RD, &adapter->watchdog_events, 4014 "Watchdog timeouts"); 4015 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4016 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4017 em_sysctl_reg_handler, "IU", 4018 "Device Control Register"); 4019 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4020 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4021 em_sysctl_reg_handler, "IU", 4022 "Receiver Control Register"); 4023 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4024 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4025 "Flow Control High Watermark"); 4026 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4027 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4028 "Flow Control Low Watermark"); 4029 4030 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4031 struct tx_ring *txr = &tx_que->txr; 4032 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4033 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4034 CTLFLAG_RD, NULL, "TX Queue Name"); 4035 queue_list = SYSCTL_CHILDREN(queue_node); 4036 4037 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4038 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4039 E1000_TDH(txr->me), 4040 em_sysctl_reg_handler, "IU", 4041 "Transmit Descriptor Head"); 4042 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4043 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4044 E1000_TDT(txr->me), 4045 em_sysctl_reg_handler, "IU", 4046 "Transmit Descriptor Tail"); 4047 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4048 CTLFLAG_RD, &txr->tx_irq, 4049 "Queue MSI-X Transmit Interrupts"); 4050 } 4051 4052 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4053 struct rx_ring *rxr = &rx_que->rxr; 4054 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4055 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4056 CTLFLAG_RD, NULL, "RX Queue Name"); 4057 queue_list = SYSCTL_CHILDREN(queue_node); 4058 4059 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4060 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4061 E1000_RDH(rxr->me), 4062 em_sysctl_reg_handler, "IU", 4063 "Receive Descriptor Head"); 4064 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4065 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4066 E1000_RDT(rxr->me), 4067 em_sysctl_reg_handler, "IU", 4068 "Receive Descriptor Tail"); 4069 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4070 CTLFLAG_RD, &rxr->rx_irq, 4071 "Queue MSI-X Receive Interrupts"); 4072 } 4073 4074 /* MAC stats get their own sub node */ 4075 4076 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4077 CTLFLAG_RD, NULL, "Statistics"); 4078 stat_list = SYSCTL_CHILDREN(stat_node); 4079 4080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4081 CTLFLAG_RD, &stats->ecol, 4082 "Excessive collisions"); 4083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4084 CTLFLAG_RD, &stats->scc, 4085 "Single collisions"); 4086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4087 CTLFLAG_RD, &stats->mcc, 4088 "Multiple collisions"); 4089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4090 CTLFLAG_RD, &stats->latecol, 4091 "Late collisions"); 4092 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4093 CTLFLAG_RD, &stats->colc, 4094 "Collision Count"); 4095 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4096 CTLFLAG_RD, &adapter->stats.symerrs, 4097 "Symbol Errors"); 4098 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4099 CTLFLAG_RD, &adapter->stats.sec, 4100 "Sequence Errors"); 4101 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4102 CTLFLAG_RD, &adapter->stats.dc, 4103 "Defer Count"); 4104 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4105 CTLFLAG_RD, &adapter->stats.mpc, 4106 "Missed Packets"); 4107 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4108 CTLFLAG_RD, &adapter->stats.rnbc, 4109 "Receive No Buffers"); 4110 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4111 CTLFLAG_RD, &adapter->stats.ruc, 4112 "Receive Undersize"); 4113 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4114 CTLFLAG_RD, &adapter->stats.rfc, 4115 "Fragmented Packets Received "); 4116 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4117 CTLFLAG_RD, &adapter->stats.roc, 4118 "Oversized Packets Received"); 4119 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4120 CTLFLAG_RD, &adapter->stats.rjc, 4121 "Recevied Jabber"); 4122 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4123 CTLFLAG_RD, &adapter->stats.rxerrc, 4124 "Receive Errors"); 4125 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4126 CTLFLAG_RD, &adapter->stats.crcerrs, 4127 "CRC errors"); 4128 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4129 CTLFLAG_RD, &adapter->stats.algnerrc, 4130 "Alignment Errors"); 4131 /* On 82575 these are collision counts */ 4132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4133 CTLFLAG_RD, &adapter->stats.cexterr, 4134 "Collision/Carrier extension errors"); 4135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4136 CTLFLAG_RD, &adapter->stats.xonrxc, 4137 "XON Received"); 4138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4139 CTLFLAG_RD, &adapter->stats.xontxc, 4140 "XON Transmitted"); 4141 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4142 CTLFLAG_RD, &adapter->stats.xoffrxc, 4143 "XOFF Received"); 4144 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4145 CTLFLAG_RD, &adapter->stats.xofftxc, 4146 "XOFF Transmitted"); 4147 4148 /* Packet Reception Stats */ 4149 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4150 CTLFLAG_RD, &adapter->stats.tpr, 4151 "Total Packets Received "); 4152 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4153 CTLFLAG_RD, &adapter->stats.gprc, 4154 "Good Packets Received"); 4155 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4156 CTLFLAG_RD, &adapter->stats.bprc, 4157 "Broadcast Packets Received"); 4158 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4159 CTLFLAG_RD, &adapter->stats.mprc, 4160 "Multicast Packets Received"); 4161 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4162 CTLFLAG_RD, &adapter->stats.prc64, 4163 "64 byte frames received "); 4164 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4165 CTLFLAG_RD, &adapter->stats.prc127, 4166 "65-127 byte frames received"); 4167 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4168 CTLFLAG_RD, &adapter->stats.prc255, 4169 "128-255 byte frames received"); 4170 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4171 CTLFLAG_RD, &adapter->stats.prc511, 4172 "256-511 byte frames received"); 4173 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4174 CTLFLAG_RD, &adapter->stats.prc1023, 4175 "512-1023 byte frames received"); 4176 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4177 CTLFLAG_RD, &adapter->stats.prc1522, 4178 "1023-1522 byte frames received"); 4179 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4180 CTLFLAG_RD, &adapter->stats.gorc, 4181 "Good Octets Received"); 4182 4183 /* Packet Transmission Stats */ 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4185 CTLFLAG_RD, &adapter->stats.gotc, 4186 "Good Octets Transmitted"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4188 CTLFLAG_RD, &adapter->stats.tpt, 4189 "Total Packets Transmitted"); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4191 CTLFLAG_RD, &adapter->stats.gptc, 4192 "Good Packets Transmitted"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4194 CTLFLAG_RD, &adapter->stats.bptc, 4195 "Broadcast Packets Transmitted"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4197 CTLFLAG_RD, &adapter->stats.mptc, 4198 "Multicast Packets Transmitted"); 4199 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4200 CTLFLAG_RD, &adapter->stats.ptc64, 4201 "64 byte frames transmitted "); 4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4203 CTLFLAG_RD, &adapter->stats.ptc127, 4204 "65-127 byte frames transmitted"); 4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4206 CTLFLAG_RD, &adapter->stats.ptc255, 4207 "128-255 byte frames transmitted"); 4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4209 CTLFLAG_RD, &adapter->stats.ptc511, 4210 "256-511 byte frames transmitted"); 4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4212 CTLFLAG_RD, &adapter->stats.ptc1023, 4213 "512-1023 byte frames transmitted"); 4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4215 CTLFLAG_RD, &adapter->stats.ptc1522, 4216 "1024-1522 byte frames transmitted"); 4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4218 CTLFLAG_RD, &adapter->stats.tsctc, 4219 "TSO Contexts Transmitted"); 4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4221 CTLFLAG_RD, &adapter->stats.tsctfc, 4222 "TSO Contexts Failed"); 4223 4224 4225 /* Interrupt Stats */ 4226 4227 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4228 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4229 int_list = SYSCTL_CHILDREN(int_node); 4230 4231 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4232 CTLFLAG_RD, &adapter->stats.iac, 4233 "Interrupt Assertion Count"); 4234 4235 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4236 CTLFLAG_RD, &adapter->stats.icrxptc, 4237 "Interrupt Cause Rx Pkt Timer Expire Count"); 4238 4239 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4240 CTLFLAG_RD, &adapter->stats.icrxatc, 4241 "Interrupt Cause Rx Abs Timer Expire Count"); 4242 4243 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4244 CTLFLAG_RD, &adapter->stats.ictxptc, 4245 "Interrupt Cause Tx Pkt Timer Expire Count"); 4246 4247 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4248 CTLFLAG_RD, &adapter->stats.ictxatc, 4249 "Interrupt Cause Tx Abs Timer Expire Count"); 4250 4251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4252 CTLFLAG_RD, &adapter->stats.ictxqec, 4253 "Interrupt Cause Tx Queue Empty Count"); 4254 4255 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4256 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4257 "Interrupt Cause Tx Queue Min Thresh Count"); 4258 4259 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4260 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4261 "Interrupt Cause Rx Desc Min Thresh Count"); 4262 4263 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4264 CTLFLAG_RD, &adapter->stats.icrxoc, 4265 "Interrupt Cause Receiver Overrun Count"); 4266 } 4267 4268 /********************************************************************** 4269 * 4270 * This routine provides a way to dump out the adapter eeprom, 4271 * often a useful debug/service tool. This only dumps the first 4272 * 32 words, stuff that matters is in that extent. 4273 * 4274 **********************************************************************/ 4275 static int 4276 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4277 { 4278 struct adapter *adapter = (struct adapter *)arg1; 4279 int error; 4280 int result; 4281 4282 result = -1; 4283 error = sysctl_handle_int(oidp, &result, 0, req); 4284 4285 if (error || !req->newptr) 4286 return (error); 4287 4288 /* 4289 * This value will cause a hex dump of the 4290 * first 32 16-bit words of the EEPROM to 4291 * the screen. 4292 */ 4293 if (result == 1) 4294 em_print_nvm_info(adapter); 4295 4296 return (error); 4297 } 4298 4299 static void 4300 em_print_nvm_info(struct adapter *adapter) 4301 { 4302 u16 eeprom_data; 4303 int i, j, row = 0; 4304 4305 /* Its a bit crude, but it gets the job done */ 4306 printf("\nInterface EEPROM Dump:\n"); 4307 printf("Offset\n0x0000 "); 4308 for (i = 0, j = 0; i < 32; i++, j++) { 4309 if (j == 8) { /* Make the offset block */ 4310 j = 0; ++row; 4311 printf("\n0x00%x0 ",row); 4312 } 4313 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4314 printf("%04x ", eeprom_data); 4315 } 4316 printf("\n"); 4317 } 4318 4319 static int 4320 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4321 { 4322 struct em_int_delay_info *info; 4323 struct adapter *adapter; 4324 u32 regval; 4325 int error, usecs, ticks; 4326 4327 info = (struct em_int_delay_info *) arg1; 4328 usecs = info->value; 4329 error = sysctl_handle_int(oidp, &usecs, 0, req); 4330 if (error != 0 || req->newptr == NULL) 4331 return (error); 4332 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4333 return (EINVAL); 4334 info->value = usecs; 4335 ticks = EM_USECS_TO_TICKS(usecs); 4336 if (info->offset == E1000_ITR) /* units are 256ns here */ 4337 ticks *= 4; 4338 4339 adapter = info->adapter; 4340 4341 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4342 regval = (regval & ~0xffff) | (ticks & 0xffff); 4343 /* Handle a few special cases. */ 4344 switch (info->offset) { 4345 case E1000_RDTR: 4346 break; 4347 case E1000_TIDV: 4348 if (ticks == 0) { 4349 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4350 /* Don't write 0 into the TIDV register. */ 4351 regval++; 4352 } else 4353 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4354 break; 4355 } 4356 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4357 return (0); 4358 } 4359 4360 static void 4361 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4362 const char *description, struct em_int_delay_info *info, 4363 int offset, int value) 4364 { 4365 info->adapter = adapter; 4366 info->offset = offset; 4367 info->value = value; 4368 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4369 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4370 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4371 info, 0, em_sysctl_int_delay, "I", description); 4372 } 4373 4374 /* 4375 * Set flow control using sysctl: 4376 * Flow control values: 4377 * 0 - off 4378 * 1 - rx pause 4379 * 2 - tx pause 4380 * 3 - full 4381 */ 4382 static int 4383 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4384 { 4385 int error; 4386 static int input = 3; /* default is full */ 4387 struct adapter *adapter = (struct adapter *) arg1; 4388 4389 error = sysctl_handle_int(oidp, &input, 0, req); 4390 4391 if ((error) || (req->newptr == NULL)) 4392 return (error); 4393 4394 if (input == adapter->fc) /* no change? */ 4395 return (error); 4396 4397 switch (input) { 4398 case e1000_fc_rx_pause: 4399 case e1000_fc_tx_pause: 4400 case e1000_fc_full: 4401 case e1000_fc_none: 4402 adapter->hw.fc.requested_mode = input; 4403 adapter->fc = input; 4404 break; 4405 default: 4406 /* Do nothing */ 4407 return (error); 4408 } 4409 4410 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4411 e1000_force_mac_fc(&adapter->hw); 4412 return (error); 4413 } 4414 4415 /* 4416 * Manage Energy Efficient Ethernet: 4417 * Control values: 4418 * 0/1 - enabled/disabled 4419 */ 4420 static int 4421 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4422 { 4423 struct adapter *adapter = (struct adapter *) arg1; 4424 int error, value; 4425 4426 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4427 error = sysctl_handle_int(oidp, &value, 0, req); 4428 if (error || req->newptr == NULL) 4429 return (error); 4430 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4431 em_if_init(adapter->ctx); 4432 4433 return (0); 4434 } 4435 4436 static int 4437 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4438 { 4439 struct adapter *adapter; 4440 int error; 4441 int result; 4442 4443 result = -1; 4444 error = sysctl_handle_int(oidp, &result, 0, req); 4445 4446 if (error || !req->newptr) 4447 return (error); 4448 4449 if (result == 1) { 4450 adapter = (struct adapter *) arg1; 4451 em_print_debug_info(adapter); 4452 } 4453 4454 return (error); 4455 } 4456 4457 static int 4458 em_get_rs(SYSCTL_HANDLER_ARGS) 4459 { 4460 struct adapter *adapter = (struct adapter *) arg1; 4461 int error; 4462 int result; 4463 4464 result = 0; 4465 error = sysctl_handle_int(oidp, &result, 0, req); 4466 4467 if (error || !req->newptr || result != 1) 4468 return (error); 4469 em_dump_rs(adapter); 4470 4471 return (error); 4472 } 4473 4474 static void 4475 em_if_debug(if_ctx_t ctx) 4476 { 4477 em_dump_rs(iflib_get_softc(ctx)); 4478 } 4479 4480 /* 4481 * This routine is meant to be fluid, add whatever is 4482 * needed for debugging a problem. -jfv 4483 */ 4484 static void 4485 em_print_debug_info(struct adapter *adapter) 4486 { 4487 device_t dev = iflib_get_dev(adapter->ctx); 4488 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4489 struct tx_ring *txr = &adapter->tx_queues->txr; 4490 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4491 4492 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4493 printf("Interface is RUNNING "); 4494 else 4495 printf("Interface is NOT RUNNING\n"); 4496 4497 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4498 printf("and INACTIVE\n"); 4499 else 4500 printf("and ACTIVE\n"); 4501 4502 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4503 device_printf(dev, "TX Queue %d ------\n", i); 4504 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4505 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4506 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4507 4508 } 4509 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4510 device_printf(dev, "RX Queue %d ------\n", j); 4511 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4512 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4513 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4514 } 4515 } 4516 4517 /* 4518 * 82574 only: 4519 * Write a new value to the EEPROM increasing the number of MSIX 4520 * vectors from 3 to 5, for proper multiqueue support. 4521 */ 4522 static void 4523 em_enable_vectors_82574(if_ctx_t ctx) 4524 { 4525 struct adapter *adapter = iflib_get_softc(ctx); 4526 struct e1000_hw *hw = &adapter->hw; 4527 device_t dev = iflib_get_dev(ctx); 4528 u16 edata; 4529 4530 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4531 printf("Current cap: %#06x\n", edata); 4532 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4533 device_printf(dev, "Writing to eeprom: increasing " 4534 "reported MSIX vectors from 3 to 5...\n"); 4535 edata &= ~(EM_NVM_MSIX_N_MASK); 4536 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4537 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4538 e1000_update_nvm_checksum(hw); 4539 device_printf(dev, "Writing to eeprom: done\n"); 4540 } 4541 } 4542