1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "if_em.h" 30 #include <sys/sbuf.h> 31 #include <machine/_inttypes.h> 32 33 #define em_mac_min e1000_82571 34 #define igb_mac_min e1000_82575 35 36 /********************************************************************* 37 * Driver version: 38 *********************************************************************/ 39 static const char em_driver_version[] = "7.7.8-fbsd"; 40 static const char igb_driver_version[] = "2.5.28-fbsd"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static const pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 static const pci_vendor_info_t igb_vendor_info_array[] = 218 { 219 /* Intel(R) - igb-class devices */ 220 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 222 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 223 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 224 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 226 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 227 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 232 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 234 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 236 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 237 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 243 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 244 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 246 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 247 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 251 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 253 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 254 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 256 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 257 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 260 /* required last entry */ 261 PVID_END 262 }; 263 264 /********************************************************************* 265 * Function prototypes 266 *********************************************************************/ 267 static void *em_register(device_t); 268 static void *igb_register(device_t); 269 static int em_if_attach_pre(if_ctx_t); 270 static int em_if_attach_post(if_ctx_t); 271 static int em_if_detach(if_ctx_t); 272 static int em_if_shutdown(if_ctx_t); 273 static int em_if_suspend(if_ctx_t); 274 static int em_if_resume(if_ctx_t); 275 276 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 277 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static void em_if_queues_free(if_ctx_t); 279 280 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 281 static void em_if_init(if_ctx_t); 282 static void em_if_stop(if_ctx_t); 283 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 284 static int em_if_media_change(if_ctx_t); 285 static int em_if_mtu_set(if_ctx_t, uint32_t); 286 static void em_if_timer(if_ctx_t, uint16_t); 287 static void em_if_vlan_register(if_ctx_t, u16); 288 static void em_if_vlan_unregister(if_ctx_t, u16); 289 static void em_if_watchdog_reset(if_ctx_t); 290 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 291 292 static void em_identify_hardware(if_ctx_t); 293 static int em_allocate_pci_resources(if_ctx_t); 294 static void em_free_pci_resources(if_ctx_t); 295 static void em_reset(if_ctx_t); 296 static int em_setup_interface(if_ctx_t); 297 static int em_setup_msix(if_ctx_t); 298 299 static void em_initialize_transmit_unit(if_ctx_t); 300 static void em_initialize_receive_unit(if_ctx_t); 301 302 static void em_if_intr_enable(if_ctx_t); 303 static void em_if_intr_disable(if_ctx_t); 304 static void igb_if_intr_enable(if_ctx_t); 305 static void igb_if_intr_disable(if_ctx_t); 306 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 307 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 310 static void em_if_multi_set(if_ctx_t); 311 static void em_if_update_admin_status(if_ctx_t); 312 static void em_if_debug(if_ctx_t); 313 static void em_update_stats_counters(struct e1000_softc *); 314 static void em_add_hw_stats(struct e1000_softc *); 315 static int em_if_set_promisc(if_ctx_t, int); 316 static bool em_if_vlan_filter_capable(if_ctx_t); 317 static bool em_if_vlan_filter_used(if_ctx_t); 318 static void em_if_vlan_filter_enable(struct e1000_softc *); 319 static void em_if_vlan_filter_disable(struct e1000_softc *); 320 static void em_if_vlan_filter_write(struct e1000_softc *); 321 static void em_setup_vlan_hw_support(if_ctx_t ctx); 322 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 323 static void em_print_nvm_info(struct e1000_softc *); 324 static void em_fw_version_locked(if_ctx_t); 325 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 326 static void em_print_fw_version(struct e1000_softc *); 327 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 328 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 329 static int em_get_rs(SYSCTL_HANDLER_ARGS); 330 static void em_print_debug_info(struct e1000_softc *); 331 static int em_is_valid_ether_addr(u8 *); 332 static bool em_automask_tso(if_ctx_t); 333 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 334 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 335 const char *, struct em_int_delay_info *, int, int); 336 /* Management and WOL Support */ 337 static void em_init_manageability(struct e1000_softc *); 338 static void em_release_manageability(struct e1000_softc *); 339 static void em_get_hw_control(struct e1000_softc *); 340 static void em_release_hw_control(struct e1000_softc *); 341 static void em_get_wakeup(if_ctx_t); 342 static void em_enable_wakeup(if_ctx_t); 343 static int em_enable_phy_wakeup(struct e1000_softc *); 344 static void em_disable_aspm(struct e1000_softc *); 345 346 int em_intr(void *); 347 348 /* MSI-X handlers */ 349 static int em_if_msix_intr_assign(if_ctx_t, int); 350 static int em_msix_link(void *); 351 static void em_handle_link(void *); 352 353 static void em_enable_vectors_82574(if_ctx_t); 354 355 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 356 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 357 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 358 static void em_if_led_func(if_ctx_t, int); 359 360 static int em_get_regs(SYSCTL_HANDLER_ARGS); 361 362 static void lem_smartspeed(struct e1000_softc *); 363 static void igb_configure_queues(struct e1000_softc *); 364 static void em_flush_desc_rings(struct e1000_softc *); 365 366 367 /********************************************************************* 368 * FreeBSD Device Interface Entry Points 369 *********************************************************************/ 370 static device_method_t em_methods[] = { 371 /* Device interface */ 372 DEVMETHOD(device_register, em_register), 373 DEVMETHOD(device_probe, iflib_device_probe), 374 DEVMETHOD(device_attach, iflib_device_attach), 375 DEVMETHOD(device_detach, iflib_device_detach), 376 DEVMETHOD(device_shutdown, iflib_device_shutdown), 377 DEVMETHOD(device_suspend, iflib_device_suspend), 378 DEVMETHOD(device_resume, iflib_device_resume), 379 DEVMETHOD_END 380 }; 381 382 static device_method_t igb_methods[] = { 383 /* Device interface */ 384 DEVMETHOD(device_register, igb_register), 385 DEVMETHOD(device_probe, iflib_device_probe), 386 DEVMETHOD(device_attach, iflib_device_attach), 387 DEVMETHOD(device_detach, iflib_device_detach), 388 DEVMETHOD(device_shutdown, iflib_device_shutdown), 389 DEVMETHOD(device_suspend, iflib_device_suspend), 390 DEVMETHOD(device_resume, iflib_device_resume), 391 DEVMETHOD_END 392 }; 393 394 395 static driver_t em_driver = { 396 "em", em_methods, sizeof(struct e1000_softc), 397 }; 398 399 DRIVER_MODULE(em, pci, em_driver, 0, 0); 400 401 MODULE_DEPEND(em, pci, 1, 1, 1); 402 MODULE_DEPEND(em, ether, 1, 1, 1); 403 MODULE_DEPEND(em, iflib, 1, 1, 1); 404 405 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 406 407 static driver_t igb_driver = { 408 "igb", igb_methods, sizeof(struct e1000_softc), 409 }; 410 411 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 412 413 MODULE_DEPEND(igb, pci, 1, 1, 1); 414 MODULE_DEPEND(igb, ether, 1, 1, 1); 415 MODULE_DEPEND(igb, iflib, 1, 1, 1); 416 417 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 418 419 static device_method_t em_if_methods[] = { 420 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 421 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 422 DEVMETHOD(ifdi_detach, em_if_detach), 423 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 424 DEVMETHOD(ifdi_suspend, em_if_suspend), 425 DEVMETHOD(ifdi_resume, em_if_resume), 426 DEVMETHOD(ifdi_init, em_if_init), 427 DEVMETHOD(ifdi_stop, em_if_stop), 428 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 429 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 430 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 431 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 432 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 433 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 434 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 435 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 436 DEVMETHOD(ifdi_media_status, em_if_media_status), 437 DEVMETHOD(ifdi_media_change, em_if_media_change), 438 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 439 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 440 DEVMETHOD(ifdi_timer, em_if_timer), 441 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 442 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 443 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 444 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 445 DEVMETHOD(ifdi_led_func, em_if_led_func), 446 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 447 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 448 DEVMETHOD(ifdi_debug, em_if_debug), 449 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 450 DEVMETHOD_END 451 }; 452 453 static driver_t em_if_driver = { 454 "em_if", em_if_methods, sizeof(struct e1000_softc) 455 }; 456 457 static device_method_t igb_if_methods[] = { 458 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 459 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 460 DEVMETHOD(ifdi_detach, em_if_detach), 461 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 462 DEVMETHOD(ifdi_suspend, em_if_suspend), 463 DEVMETHOD(ifdi_resume, em_if_resume), 464 DEVMETHOD(ifdi_init, em_if_init), 465 DEVMETHOD(ifdi_stop, em_if_stop), 466 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 467 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 468 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 469 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 470 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 471 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 472 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 473 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 474 DEVMETHOD(ifdi_media_status, em_if_media_status), 475 DEVMETHOD(ifdi_media_change, em_if_media_change), 476 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 477 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 478 DEVMETHOD(ifdi_timer, em_if_timer), 479 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 480 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 481 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 482 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 483 DEVMETHOD(ifdi_led_func, em_if_led_func), 484 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 485 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 486 DEVMETHOD(ifdi_debug, em_if_debug), 487 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 488 DEVMETHOD_END 489 }; 490 491 static driver_t igb_if_driver = { 492 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 493 }; 494 495 /********************************************************************* 496 * Tunable default values. 497 *********************************************************************/ 498 499 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 500 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 501 502 /* Allow common code without TSO */ 503 #ifndef CSUM_TSO 504 #define CSUM_TSO 0 505 #endif 506 507 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 508 "EM driver parameters"); 509 510 static int em_disable_crc_stripping = 0; 511 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 512 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 513 514 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 515 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 516 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 517 0, "Default transmit interrupt delay in usecs"); 518 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 519 0, "Default receive interrupt delay in usecs"); 520 521 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 522 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 523 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 524 &em_tx_abs_int_delay_dflt, 0, 525 "Default transmit interrupt delay limit in usecs"); 526 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 527 &em_rx_abs_int_delay_dflt, 0, 528 "Default receive interrupt delay limit in usecs"); 529 530 static int em_smart_pwr_down = false; 531 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 532 0, "Set to true to leave smart power down enabled on newer adapters"); 533 534 static bool em_unsupported_tso = false; 535 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 536 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 537 538 /* Controls whether promiscuous also shows bad packets */ 539 static int em_debug_sbp = false; 540 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 541 "Show bad packets in promiscuous mode"); 542 543 /* Energy efficient ethernet - default to OFF */ 544 static int eee_setting = 1; 545 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 546 "Enable Energy Efficient Ethernet"); 547 548 /* 549 ** Tuneable Interrupt rate 550 */ 551 static int em_max_interrupt_rate = EM_INTS_PER_SEC; 552 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 553 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 554 555 /* Global used in WOL setup with multiport cards */ 556 static int global_quad_port_a = 0; 557 558 extern struct if_txrx igb_txrx; 559 extern struct if_txrx em_txrx; 560 extern struct if_txrx lem_txrx; 561 562 static struct if_shared_ctx em_sctx_init = { 563 .isc_magic = IFLIB_MAGIC, 564 .isc_q_align = PAGE_SIZE, 565 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 566 .isc_tx_maxsegsize = PAGE_SIZE, 567 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 568 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 569 .isc_rx_maxsize = MJUM9BYTES, 570 .isc_rx_nsegments = 1, 571 .isc_rx_maxsegsize = MJUM9BYTES, 572 .isc_nfl = 1, 573 .isc_nrxqs = 1, 574 .isc_ntxqs = 1, 575 .isc_admin_intrcnt = 1, 576 .isc_vendor_info = em_vendor_info_array, 577 .isc_driver_version = em_driver_version, 578 .isc_driver = &em_if_driver, 579 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 580 581 .isc_nrxd_min = {EM_MIN_RXD}, 582 .isc_ntxd_min = {EM_MIN_TXD}, 583 .isc_nrxd_max = {EM_MAX_RXD}, 584 .isc_ntxd_max = {EM_MAX_TXD}, 585 .isc_nrxd_default = {EM_DEFAULT_RXD}, 586 .isc_ntxd_default = {EM_DEFAULT_TXD}, 587 }; 588 589 static struct if_shared_ctx igb_sctx_init = { 590 .isc_magic = IFLIB_MAGIC, 591 .isc_q_align = PAGE_SIZE, 592 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 593 .isc_tx_maxsegsize = PAGE_SIZE, 594 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 595 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 596 .isc_rx_maxsize = MJUM9BYTES, 597 .isc_rx_nsegments = 1, 598 .isc_rx_maxsegsize = MJUM9BYTES, 599 .isc_nfl = 1, 600 .isc_nrxqs = 1, 601 .isc_ntxqs = 1, 602 .isc_admin_intrcnt = 1, 603 .isc_vendor_info = igb_vendor_info_array, 604 .isc_driver_version = igb_driver_version, 605 .isc_driver = &igb_if_driver, 606 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 607 608 .isc_nrxd_min = {EM_MIN_RXD}, 609 .isc_ntxd_min = {EM_MIN_TXD}, 610 .isc_nrxd_max = {IGB_MAX_RXD}, 611 .isc_ntxd_max = {IGB_MAX_TXD}, 612 .isc_nrxd_default = {EM_DEFAULT_RXD}, 613 .isc_ntxd_default = {EM_DEFAULT_TXD}, 614 }; 615 616 /***************************************************************** 617 * 618 * Dump Registers 619 * 620 ****************************************************************/ 621 #define IGB_REGS_LEN 739 622 623 static int em_get_regs(SYSCTL_HANDLER_ARGS) 624 { 625 struct e1000_softc *sc = (struct e1000_softc *)arg1; 626 struct e1000_hw *hw = &sc->hw; 627 struct sbuf *sb; 628 u32 *regs_buff; 629 int rc; 630 631 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 632 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 633 634 rc = sysctl_wire_old_buffer(req, 0); 635 MPASS(rc == 0); 636 if (rc != 0) { 637 free(regs_buff, M_DEVBUF); 638 return (rc); 639 } 640 641 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 642 MPASS(sb != NULL); 643 if (sb == NULL) { 644 free(regs_buff, M_DEVBUF); 645 return (ENOMEM); 646 } 647 648 /* General Registers */ 649 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 650 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 651 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 652 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 653 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 654 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 655 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 656 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 657 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 658 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 659 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 660 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 661 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 662 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 663 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 664 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 665 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 666 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 667 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 668 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 669 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 670 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 671 672 sbuf_printf(sb, "General Registers\n"); 673 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 674 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 675 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 676 677 sbuf_printf(sb, "Interrupt Registers\n"); 678 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 679 680 sbuf_printf(sb, "RX Registers\n"); 681 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 682 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 683 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 684 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 685 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 686 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 687 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 688 689 sbuf_printf(sb, "TX Registers\n"); 690 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 691 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 692 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 693 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 694 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 695 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 696 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 697 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 698 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 699 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 700 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 701 702 free(regs_buff, M_DEVBUF); 703 704 #ifdef DUMP_DESCS 705 { 706 if_softc_ctx_t scctx = sc->shared; 707 struct rx_ring *rxr = &rx_que->rxr; 708 struct tx_ring *txr = &tx_que->txr; 709 int ntxd = scctx->isc_ntxd[0]; 710 int nrxd = scctx->isc_nrxd[0]; 711 int j; 712 713 for (j = 0; j < nrxd; j++) { 714 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 715 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 716 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 717 } 718 719 for (j = 0; j < min(ntxd, 256); j++) { 720 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 721 722 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 723 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 724 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 725 726 } 727 } 728 #endif 729 730 rc = sbuf_finish(sb); 731 sbuf_delete(sb); 732 return(rc); 733 } 734 735 static void * 736 em_register(device_t dev) 737 { 738 return (&em_sctx_init); 739 } 740 741 static void * 742 igb_register(device_t dev) 743 { 744 return (&igb_sctx_init); 745 } 746 747 static int 748 em_set_num_queues(if_ctx_t ctx) 749 { 750 struct e1000_softc *sc = iflib_get_softc(ctx); 751 int maxqueues; 752 753 /* Sanity check based on HW */ 754 switch (sc->hw.mac.type) { 755 case e1000_82576: 756 case e1000_82580: 757 case e1000_i350: 758 case e1000_i354: 759 maxqueues = 8; 760 break; 761 case e1000_i210: 762 case e1000_82575: 763 maxqueues = 4; 764 break; 765 case e1000_i211: 766 case e1000_82574: 767 maxqueues = 2; 768 break; 769 default: 770 maxqueues = 1; 771 break; 772 } 773 774 return (maxqueues); 775 } 776 777 #define LEM_CAPS \ 778 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 779 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 780 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 781 782 #define EM_CAPS \ 783 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 784 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 785 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 786 IFCAP_TSO6 787 788 #define IGB_CAPS \ 789 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 790 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 791 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 792 IFCAP_TSO6 793 794 /********************************************************************* 795 * Device initialization routine 796 * 797 * The attach entry point is called when the driver is being loaded. 798 * This routine identifies the type of hardware, allocates all resources 799 * and initializes the hardware. 800 * 801 * return 0 on success, positive on failure 802 *********************************************************************/ 803 static int 804 em_if_attach_pre(if_ctx_t ctx) 805 { 806 struct e1000_softc *sc; 807 if_softc_ctx_t scctx; 808 device_t dev; 809 struct e1000_hw *hw; 810 struct sysctl_oid_list *child; 811 struct sysctl_ctx_list *ctx_list; 812 int error = 0; 813 814 INIT_DEBUGOUT("em_if_attach_pre: begin"); 815 dev = iflib_get_dev(ctx); 816 sc = iflib_get_softc(ctx); 817 818 sc->ctx = sc->osdep.ctx = ctx; 819 sc->dev = sc->osdep.dev = dev; 820 scctx = sc->shared = iflib_get_softc_ctx(ctx); 821 sc->media = iflib_get_media(ctx); 822 hw = &sc->hw; 823 824 /* Determine hardware and mac info */ 825 em_identify_hardware(ctx); 826 827 /* SYSCTL stuff */ 828 ctx_list = device_get_sysctl_ctx(dev); 829 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 830 831 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 832 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 833 em_sysctl_nvm_info, "I", "NVM Information"); 834 835 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 836 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 837 em_sysctl_print_fw_version, "A", 838 "Prints FW/NVM Versions"); 839 840 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 841 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 842 em_sysctl_debug_info, "I", "Debug Information"); 843 844 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 845 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 846 em_set_flowcntl, "I", "Flow Control"); 847 848 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 849 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 850 em_get_regs, "A", "Dump Registers"); 851 852 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 853 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 854 em_get_rs, "I", "Dump RS indexes"); 855 856 if (hw->mac.type >= e1000_i350) { 857 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 858 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 859 igb_sysctl_dmac, "I", "DMA Coalesce"); 860 } 861 862 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 863 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 864 if (bootverbose) 865 device_printf(dev, "attach_pre capping queues at %d\n", 866 scctx->isc_ntxqsets_max); 867 868 if (hw->mac.type >= igb_mac_min) { 869 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 870 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 871 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 872 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 873 scctx->isc_txrx = &igb_txrx; 874 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 875 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 876 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 877 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 878 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 879 CSUM_IP6_TCP | CSUM_IP6_UDP; 880 if (hw->mac.type != e1000_82575) 881 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 882 /* 883 ** Some new devices, as with ixgbe, now may 884 ** use a different BAR, so we need to keep 885 ** track of which is used. 886 */ 887 scctx->isc_msix_bar = pci_msix_table_bar(dev); 888 } else if (hw->mac.type >= em_mac_min) { 889 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 890 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 891 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 892 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 893 scctx->isc_txrx = &em_txrx; 894 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 895 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 896 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 897 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 898 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 899 CSUM_IP6_TCP | CSUM_IP6_UDP; 900 901 /* Disable TSO on all em(4) until ring stalls can be debugged */ 902 scctx->isc_capenable &= ~IFCAP_TSO; 903 904 /* 905 * Disable TSO on SPT due to errata that downclocks DMA performance 906 * i218-i219 Specification Update 1.5.4.5 907 */ 908 if (hw->mac.type == e1000_pch_spt) 909 scctx->isc_capenable &= ~IFCAP_TSO; 910 911 /* 912 * We support MSI-X with 82574 only, but indicate to iflib(4) 913 * that it shall give MSI at least a try with other devices. 914 */ 915 if (hw->mac.type == e1000_82574) { 916 scctx->isc_msix_bar = pci_msix_table_bar(dev); 917 } else { 918 scctx->isc_msix_bar = -1; 919 scctx->isc_disable_msix = 1; 920 } 921 } else { 922 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 923 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 924 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 925 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 926 scctx->isc_txrx = &lem_txrx; 927 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 928 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 929 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 930 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 931 if (em_unsupported_tso) 932 scctx->isc_capabilities |= IFCAP_TSO6; 933 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 934 CSUM_IP6_TCP | CSUM_IP6_UDP; 935 936 /* Disable TSO on all lem(4) until ring stalls can be debugged */ 937 scctx->isc_capenable &= ~IFCAP_TSO; 938 939 /* 82541ER doesn't do HW tagging */ 940 if (hw->device_id == E1000_DEV_ID_82541ER || 941 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 942 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 943 scctx->isc_capenable = scctx->isc_capabilities; 944 } 945 /* This is the first e1000 chip and it does not do offloads */ 946 if (hw->mac.type == e1000_82542) { 947 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 948 IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING | 949 IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO); 950 scctx->isc_capenable = scctx->isc_capabilities; 951 } 952 /* These can't do TSO for various reasons */ 953 if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 || 954 hw->mac.type == e1000_82547_rev_2) { 955 scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 956 scctx->isc_capenable = scctx->isc_capabilities; 957 } 958 /* XXXKB: No IPv6 before this? */ 959 if (hw->mac.type < e1000_82545){ 960 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 961 scctx->isc_capenable = scctx->isc_capabilities; 962 } 963 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 964 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 965 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 966 IFCAP_HWCSUM_IPV6); 967 968 /* INTx only */ 969 scctx->isc_msix_bar = 0; 970 } 971 972 /* Setup PCI resources */ 973 if (em_allocate_pci_resources(ctx)) { 974 device_printf(dev, "Allocation of PCI resources failed\n"); 975 error = ENXIO; 976 goto err_pci; 977 } 978 979 /* 980 ** For ICH8 and family we need to 981 ** map the flash memory, and this 982 ** must happen after the MAC is 983 ** identified 984 */ 985 if ((hw->mac.type == e1000_ich8lan) || 986 (hw->mac.type == e1000_ich9lan) || 987 (hw->mac.type == e1000_ich10lan) || 988 (hw->mac.type == e1000_pchlan) || 989 (hw->mac.type == e1000_pch2lan) || 990 (hw->mac.type == e1000_pch_lpt)) { 991 int rid = EM_BAR_TYPE_FLASH; 992 sc->flash = bus_alloc_resource_any(dev, 993 SYS_RES_MEMORY, &rid, RF_ACTIVE); 994 if (sc->flash == NULL) { 995 device_printf(dev, "Mapping of Flash failed\n"); 996 error = ENXIO; 997 goto err_pci; 998 } 999 /* This is used in the shared code */ 1000 hw->flash_address = (u8 *)sc->flash; 1001 sc->osdep.flash_bus_space_tag = 1002 rman_get_bustag(sc->flash); 1003 sc->osdep.flash_bus_space_handle = 1004 rman_get_bushandle(sc->flash); 1005 } 1006 /* 1007 ** In the new SPT device flash is not a 1008 ** separate BAR, rather it is also in BAR0, 1009 ** so use the same tag and an offset handle for the 1010 ** FLASH read/write macros in the shared code. 1011 */ 1012 else if (hw->mac.type >= e1000_pch_spt) { 1013 sc->osdep.flash_bus_space_tag = 1014 sc->osdep.mem_bus_space_tag; 1015 sc->osdep.flash_bus_space_handle = 1016 sc->osdep.mem_bus_space_handle 1017 + E1000_FLASH_BASE_ADDR; 1018 } 1019 1020 /* Do Shared Code initialization */ 1021 error = e1000_setup_init_funcs(hw, true); 1022 if (error) { 1023 device_printf(dev, "Setup of Shared code failed, error %d\n", 1024 error); 1025 error = ENXIO; 1026 goto err_pci; 1027 } 1028 1029 em_setup_msix(ctx); 1030 e1000_get_bus_info(hw); 1031 1032 /* Set up some sysctls for the tunable interrupt delays */ 1033 if (hw->mac.type < igb_mac_min) { 1034 em_add_int_delay_sysctl(sc, "rx_int_delay", 1035 "receive interrupt delay in usecs", &sc->rx_int_delay, 1036 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1037 em_add_int_delay_sysctl(sc, "tx_int_delay", 1038 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1039 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1040 } 1041 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1042 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1043 "receive interrupt delay limit in usecs", &sc->rx_abs_int_delay, 1044 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1045 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1046 "transmit interrupt delay limit in usecs", &sc->tx_abs_int_delay, 1047 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1048 em_add_int_delay_sysctl(sc, "itr", 1049 "interrupt delay limit in usecs/4", &sc->tx_itr, 1050 E1000_REGISTER(hw, E1000_ITR), 1051 EM_INTS_TO_ITR(em_max_interrupt_rate)); 1052 } 1053 1054 hw->mac.autoneg = DO_AUTO_NEG; 1055 hw->phy.autoneg_wait_to_complete = false; 1056 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1057 1058 if (hw->mac.type < em_mac_min) { 1059 e1000_init_script_state_82541(hw, true); 1060 e1000_set_tbi_compatibility_82543(hw, true); 1061 } 1062 /* Copper options */ 1063 if (hw->phy.media_type == e1000_media_type_copper) { 1064 hw->phy.mdix = AUTO_ALL_MODES; 1065 hw->phy.disable_polarity_correction = false; 1066 hw->phy.ms_type = EM_MASTER_SLAVE; 1067 } 1068 1069 /* 1070 * Set the frame limits assuming 1071 * standard ethernet sized frames. 1072 */ 1073 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1074 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1075 1076 /* 1077 * This controls when hardware reports transmit completion 1078 * status. 1079 */ 1080 hw->mac.report_tx_early = 1; 1081 1082 /* Allocate multicast array memory. */ 1083 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1084 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1085 if (sc->mta == NULL) { 1086 device_printf(dev, "Can not allocate multicast setup array\n"); 1087 error = ENOMEM; 1088 goto err_late; 1089 } 1090 1091 /* Clear the IFCAP_TSO auto mask */ 1092 sc->tso_automasked = 0; 1093 1094 /* Check SOL/IDER usage */ 1095 if (e1000_check_reset_block(hw)) 1096 device_printf(dev, "PHY reset is blocked" 1097 " due to SOL/IDER session.\n"); 1098 1099 /* Sysctl for setting Energy Efficient Ethernet */ 1100 if (hw->mac.type < igb_mac_min) 1101 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1102 else 1103 hw->dev_spec._82575.eee_disable = eee_setting; 1104 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1105 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1106 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1107 1108 /* 1109 ** Start from a known state, this is 1110 ** important in reading the nvm and 1111 ** mac from that. 1112 */ 1113 e1000_reset_hw(hw); 1114 1115 /* Make sure we have a good EEPROM before we read from it */ 1116 if (e1000_validate_nvm_checksum(hw) < 0) { 1117 /* 1118 ** Some PCI-E parts fail the first check due to 1119 ** the link being in sleep state, call it again, 1120 ** if it fails a second time its a real issue. 1121 */ 1122 if (e1000_validate_nvm_checksum(hw) < 0) { 1123 device_printf(dev, 1124 "The EEPROM Checksum Is Not Valid\n"); 1125 error = EIO; 1126 goto err_late; 1127 } 1128 } 1129 1130 /* Copy the permanent MAC address out of the EEPROM */ 1131 if (e1000_read_mac_addr(hw) < 0) { 1132 device_printf(dev, "EEPROM read error while reading MAC" 1133 " address\n"); 1134 error = EIO; 1135 goto err_late; 1136 } 1137 1138 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1139 if (sc->vf_ifp) { 1140 ether_gen_addr(iflib_get_ifp(ctx), 1141 (struct ether_addr *)hw->mac.addr); 1142 } else { 1143 device_printf(dev, "Invalid MAC address\n"); 1144 error = EIO; 1145 goto err_late; 1146 } 1147 } 1148 1149 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1150 em_fw_version_locked(ctx); 1151 1152 em_print_fw_version(sc); 1153 1154 /* 1155 * Get Wake-on-Lan and Management info for later use 1156 */ 1157 em_get_wakeup(ctx); 1158 1159 /* Enable only WOL MAGIC by default */ 1160 scctx->isc_capenable &= ~IFCAP_WOL; 1161 if (sc->wol != 0) 1162 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1163 1164 iflib_set_mac(ctx, hw->mac.addr); 1165 1166 return (0); 1167 1168 err_late: 1169 em_release_hw_control(sc); 1170 err_pci: 1171 em_free_pci_resources(ctx); 1172 free(sc->mta, M_DEVBUF); 1173 1174 return (error); 1175 } 1176 1177 static int 1178 em_if_attach_post(if_ctx_t ctx) 1179 { 1180 struct e1000_softc *sc = iflib_get_softc(ctx); 1181 struct e1000_hw *hw = &sc->hw; 1182 int error = 0; 1183 1184 /* Setup OS specific network interface */ 1185 error = em_setup_interface(ctx); 1186 if (error != 0) { 1187 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1188 goto err_late; 1189 } 1190 1191 em_reset(ctx); 1192 1193 /* Initialize statistics */ 1194 em_update_stats_counters(sc); 1195 hw->mac.get_link_status = 1; 1196 em_if_update_admin_status(ctx); 1197 em_add_hw_stats(sc); 1198 1199 /* Non-AMT based hardware can now take control from firmware */ 1200 if (sc->has_manage && !sc->has_amt) 1201 em_get_hw_control(sc); 1202 1203 INIT_DEBUGOUT("em_if_attach_post: end"); 1204 1205 return (0); 1206 1207 err_late: 1208 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1209 return (error); 1210 } 1211 1212 /********************************************************************* 1213 * Device removal routine 1214 * 1215 * The detach entry point is called when the driver is being removed. 1216 * This routine stops the adapter and deallocates all the resources 1217 * that were allocated for driver operation. 1218 * 1219 * return 0 on success, positive on failure 1220 *********************************************************************/ 1221 static int 1222 em_if_detach(if_ctx_t ctx) 1223 { 1224 struct e1000_softc *sc = iflib_get_softc(ctx); 1225 1226 INIT_DEBUGOUT("em_if_detach: begin"); 1227 1228 e1000_phy_hw_reset(&sc->hw); 1229 1230 em_release_manageability(sc); 1231 em_release_hw_control(sc); 1232 em_free_pci_resources(ctx); 1233 free(sc->mta, M_DEVBUF); 1234 sc->mta = NULL; 1235 1236 return (0); 1237 } 1238 1239 /********************************************************************* 1240 * 1241 * Shutdown entry point 1242 * 1243 **********************************************************************/ 1244 1245 static int 1246 em_if_shutdown(if_ctx_t ctx) 1247 { 1248 return em_if_suspend(ctx); 1249 } 1250 1251 /* 1252 * Suspend/resume device methods. 1253 */ 1254 static int 1255 em_if_suspend(if_ctx_t ctx) 1256 { 1257 struct e1000_softc *sc = iflib_get_softc(ctx); 1258 1259 em_release_manageability(sc); 1260 em_release_hw_control(sc); 1261 em_enable_wakeup(ctx); 1262 return (0); 1263 } 1264 1265 static int 1266 em_if_resume(if_ctx_t ctx) 1267 { 1268 struct e1000_softc *sc = iflib_get_softc(ctx); 1269 1270 if (sc->hw.mac.type == e1000_pch2lan) 1271 e1000_resume_workarounds_pchlan(&sc->hw); 1272 em_if_init(ctx); 1273 em_init_manageability(sc); 1274 1275 return(0); 1276 } 1277 1278 static int 1279 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1280 { 1281 int max_frame_size; 1282 struct e1000_softc *sc = iflib_get_softc(ctx); 1283 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1284 1285 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1286 1287 switch (sc->hw.mac.type) { 1288 case e1000_82571: 1289 case e1000_82572: 1290 case e1000_ich9lan: 1291 case e1000_ich10lan: 1292 case e1000_pch2lan: 1293 case e1000_pch_lpt: 1294 case e1000_pch_spt: 1295 case e1000_pch_cnp: 1296 case e1000_pch_tgp: 1297 case e1000_pch_adp: 1298 case e1000_pch_mtp: 1299 case e1000_pch_ptp: 1300 case e1000_82574: 1301 case e1000_82583: 1302 case e1000_80003es2lan: 1303 /* 9K Jumbo Frame size */ 1304 max_frame_size = 9234; 1305 break; 1306 case e1000_pchlan: 1307 max_frame_size = 4096; 1308 break; 1309 case e1000_82542: 1310 case e1000_ich8lan: 1311 /* Adapters that do not support jumbo frames */ 1312 max_frame_size = ETHER_MAX_LEN; 1313 break; 1314 default: 1315 if (sc->hw.mac.type >= igb_mac_min) 1316 max_frame_size = 9234; 1317 else /* lem */ 1318 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1319 } 1320 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1321 return (EINVAL); 1322 } 1323 1324 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1325 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1326 return (0); 1327 } 1328 1329 /********************************************************************* 1330 * Init entry point 1331 * 1332 * This routine is used in two ways. It is used by the stack as 1333 * init entry point in network interface structure. It is also used 1334 * by the driver as a hw/sw initialization routine to get to a 1335 * consistent state. 1336 * 1337 **********************************************************************/ 1338 static void 1339 em_if_init(if_ctx_t ctx) 1340 { 1341 struct e1000_softc *sc = iflib_get_softc(ctx); 1342 if_softc_ctx_t scctx = sc->shared; 1343 if_t ifp = iflib_get_ifp(ctx); 1344 struct em_tx_queue *tx_que; 1345 int i; 1346 1347 INIT_DEBUGOUT("em_if_init: begin"); 1348 1349 /* Get the latest mac address, User can use a LAA */ 1350 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1351 ETHER_ADDR_LEN); 1352 1353 /* Put the address into the Receive Address Array */ 1354 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1355 1356 /* 1357 * With the 82571 adapter, RAR[0] may be overwritten 1358 * when the other port is reset, we make a duplicate 1359 * in RAR[14] for that eventuality, this assures 1360 * the interface continues to function. 1361 */ 1362 if (sc->hw.mac.type == e1000_82571) { 1363 e1000_set_laa_state_82571(&sc->hw, true); 1364 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1365 E1000_RAR_ENTRIES - 1); 1366 } 1367 1368 /* Initialize the hardware */ 1369 em_reset(ctx); 1370 em_if_update_admin_status(ctx); 1371 1372 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1373 struct tx_ring *txr = &tx_que->txr; 1374 1375 txr->tx_rs_cidx = txr->tx_rs_pidx; 1376 1377 /* Initialize the last processed descriptor to be the end of 1378 * the ring, rather than the start, so that we avoid an 1379 * off-by-one error when calculating how many descriptors are 1380 * done in the credits_update function. 1381 */ 1382 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1383 } 1384 1385 /* Setup VLAN support, basic and offload if available */ 1386 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1387 1388 /* Clear bad data from Rx FIFOs */ 1389 if (sc->hw.mac.type >= igb_mac_min) 1390 e1000_rx_fifo_flush_base(&sc->hw); 1391 1392 /* Configure for OS presence */ 1393 em_init_manageability(sc); 1394 1395 /* Prepare transmit descriptors and buffers */ 1396 em_initialize_transmit_unit(ctx); 1397 1398 /* Setup Multicast table */ 1399 em_if_multi_set(ctx); 1400 1401 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1402 em_initialize_receive_unit(ctx); 1403 1404 /* Set up VLAN support and filter */ 1405 em_setup_vlan_hw_support(ctx); 1406 1407 /* Don't lose promiscuous settings */ 1408 em_if_set_promisc(ctx, if_getflags(ifp)); 1409 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1410 1411 /* MSI-X configuration for 82574 */ 1412 if (sc->hw.mac.type == e1000_82574) { 1413 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1414 1415 tmp |= E1000_CTRL_EXT_PBA_CLR; 1416 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1417 /* Set the IVAR - interrupt vector routing. */ 1418 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1419 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1420 igb_configure_queues(sc); 1421 1422 /* this clears any pending interrupts */ 1423 E1000_READ_REG(&sc->hw, E1000_ICR); 1424 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1425 1426 /* AMT based hardware can now take control from firmware */ 1427 if (sc->has_manage && sc->has_amt) 1428 em_get_hw_control(sc); 1429 1430 /* Set Energy Efficient Ethernet */ 1431 if (sc->hw.mac.type >= igb_mac_min && 1432 sc->hw.phy.media_type == e1000_media_type_copper) { 1433 if (sc->hw.mac.type == e1000_i354) 1434 e1000_set_eee_i354(&sc->hw, true, true); 1435 else 1436 e1000_set_eee_i350(&sc->hw, true, true); 1437 } 1438 } 1439 1440 /********************************************************************* 1441 * 1442 * Fast Legacy/MSI Combined Interrupt Service routine 1443 * 1444 *********************************************************************/ 1445 int 1446 em_intr(void *arg) 1447 { 1448 struct e1000_softc *sc = arg; 1449 if_ctx_t ctx = sc->ctx; 1450 u32 reg_icr; 1451 1452 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1453 1454 /* Hot eject? */ 1455 if (reg_icr == 0xffffffff) 1456 return FILTER_STRAY; 1457 1458 /* Definitely not our interrupt. */ 1459 if (reg_icr == 0x0) 1460 return FILTER_STRAY; 1461 1462 /* 1463 * Starting with the 82571 chip, bit 31 should be used to 1464 * determine whether the interrupt belongs to us. 1465 */ 1466 if (sc->hw.mac.type >= e1000_82571 && 1467 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1468 return FILTER_STRAY; 1469 1470 /* 1471 * Only MSI-X interrupts have one-shot behavior by taking advantage 1472 * of the EIAC register. Thus, explicitly disable interrupts. This 1473 * also works around the MSI message reordering errata on certain 1474 * systems. 1475 */ 1476 IFDI_INTR_DISABLE(ctx); 1477 1478 /* Link status change */ 1479 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1480 em_handle_link(ctx); 1481 1482 if (reg_icr & E1000_ICR_RXO) 1483 sc->rx_overruns++; 1484 1485 return (FILTER_SCHEDULE_THREAD); 1486 } 1487 1488 static int 1489 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1490 { 1491 struct e1000_softc *sc = iflib_get_softc(ctx); 1492 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1493 1494 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1495 return (0); 1496 } 1497 1498 static int 1499 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1500 { 1501 struct e1000_softc *sc = iflib_get_softc(ctx); 1502 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1503 1504 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1505 return (0); 1506 } 1507 1508 static int 1509 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1510 { 1511 struct e1000_softc *sc = iflib_get_softc(ctx); 1512 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1513 1514 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1515 return (0); 1516 } 1517 1518 static int 1519 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1520 { 1521 struct e1000_softc *sc = iflib_get_softc(ctx); 1522 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1523 1524 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1525 return (0); 1526 } 1527 1528 /********************************************************************* 1529 * 1530 * MSI-X RX Interrupt Service routine 1531 * 1532 **********************************************************************/ 1533 static int 1534 em_msix_que(void *arg) 1535 { 1536 struct em_rx_queue *que = arg; 1537 1538 ++que->irqs; 1539 1540 return (FILTER_SCHEDULE_THREAD); 1541 } 1542 1543 /********************************************************************* 1544 * 1545 * MSI-X Link Fast Interrupt Service routine 1546 * 1547 **********************************************************************/ 1548 static int 1549 em_msix_link(void *arg) 1550 { 1551 struct e1000_softc *sc = arg; 1552 u32 reg_icr; 1553 1554 ++sc->link_irq; 1555 MPASS(sc->hw.back != NULL); 1556 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1557 1558 if (reg_icr & E1000_ICR_RXO) 1559 sc->rx_overruns++; 1560 1561 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1562 em_handle_link(sc->ctx); 1563 1564 /* Re-arm unconditionally */ 1565 if (sc->hw.mac.type >= igb_mac_min) { 1566 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1567 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1568 } else if (sc->hw.mac.type == e1000_82574) { 1569 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1570 E1000_IMS_OTHER); 1571 /* 1572 * Because we must read the ICR for this interrupt it may 1573 * clear other causes using autoclear, for this reason we 1574 * simply create a soft interrupt for all these vectors. 1575 */ 1576 if (reg_icr) 1577 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1578 } else 1579 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1580 1581 return (FILTER_HANDLED); 1582 } 1583 1584 static void 1585 em_handle_link(void *context) 1586 { 1587 if_ctx_t ctx = context; 1588 struct e1000_softc *sc = iflib_get_softc(ctx); 1589 1590 sc->hw.mac.get_link_status = 1; 1591 iflib_admin_intr_deferred(ctx); 1592 } 1593 1594 /********************************************************************* 1595 * 1596 * Media Ioctl callback 1597 * 1598 * This routine is called whenever the user queries the status of 1599 * the interface using ifconfig. 1600 * 1601 **********************************************************************/ 1602 static void 1603 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1604 { 1605 struct e1000_softc *sc = iflib_get_softc(ctx); 1606 u_char fiber_type = IFM_1000_SX; 1607 1608 INIT_DEBUGOUT("em_if_media_status: begin"); 1609 1610 iflib_admin_intr_deferred(ctx); 1611 1612 ifmr->ifm_status = IFM_AVALID; 1613 ifmr->ifm_active = IFM_ETHER; 1614 1615 if (!sc->link_active) { 1616 return; 1617 } 1618 1619 ifmr->ifm_status |= IFM_ACTIVE; 1620 1621 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1622 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1623 if (sc->hw.mac.type == e1000_82545) 1624 fiber_type = IFM_1000_LX; 1625 ifmr->ifm_active |= fiber_type | IFM_FDX; 1626 } else { 1627 switch (sc->link_speed) { 1628 case 10: 1629 ifmr->ifm_active |= IFM_10_T; 1630 break; 1631 case 100: 1632 ifmr->ifm_active |= IFM_100_TX; 1633 break; 1634 case 1000: 1635 ifmr->ifm_active |= IFM_1000_T; 1636 break; 1637 } 1638 if (sc->link_duplex == FULL_DUPLEX) 1639 ifmr->ifm_active |= IFM_FDX; 1640 else 1641 ifmr->ifm_active |= IFM_HDX; 1642 } 1643 } 1644 1645 /********************************************************************* 1646 * 1647 * Media Ioctl callback 1648 * 1649 * This routine is called when the user changes speed/duplex using 1650 * media/mediopt option with ifconfig. 1651 * 1652 **********************************************************************/ 1653 static int 1654 em_if_media_change(if_ctx_t ctx) 1655 { 1656 struct e1000_softc *sc = iflib_get_softc(ctx); 1657 struct ifmedia *ifm = iflib_get_media(ctx); 1658 1659 INIT_DEBUGOUT("em_if_media_change: begin"); 1660 1661 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1662 return (EINVAL); 1663 1664 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1665 case IFM_AUTO: 1666 sc->hw.mac.autoneg = DO_AUTO_NEG; 1667 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1668 break; 1669 case IFM_1000_LX: 1670 case IFM_1000_SX: 1671 case IFM_1000_T: 1672 sc->hw.mac.autoneg = DO_AUTO_NEG; 1673 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1674 break; 1675 case IFM_100_TX: 1676 sc->hw.mac.autoneg = false; 1677 sc->hw.phy.autoneg_advertised = 0; 1678 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1679 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1680 else 1681 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1682 break; 1683 case IFM_10_T: 1684 sc->hw.mac.autoneg = false; 1685 sc->hw.phy.autoneg_advertised = 0; 1686 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1687 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1688 else 1689 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1690 break; 1691 default: 1692 device_printf(sc->dev, "Unsupported media type\n"); 1693 } 1694 1695 em_if_init(ctx); 1696 1697 return (0); 1698 } 1699 1700 static int 1701 em_if_set_promisc(if_ctx_t ctx, int flags) 1702 { 1703 struct e1000_softc *sc = iflib_get_softc(ctx); 1704 if_t ifp = iflib_get_ifp(ctx); 1705 u32 reg_rctl; 1706 int mcnt = 0; 1707 1708 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1709 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1710 if (flags & IFF_ALLMULTI) 1711 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1712 else 1713 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1714 1715 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1716 reg_rctl &= (~E1000_RCTL_MPE); 1717 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1718 1719 if (flags & IFF_PROMISC) { 1720 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1721 em_if_vlan_filter_disable(sc); 1722 /* Turn this on if you want to see bad packets */ 1723 if (em_debug_sbp) 1724 reg_rctl |= E1000_RCTL_SBP; 1725 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1726 } else { 1727 if (flags & IFF_ALLMULTI) { 1728 reg_rctl |= E1000_RCTL_MPE; 1729 reg_rctl &= ~E1000_RCTL_UPE; 1730 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1731 } 1732 if (em_if_vlan_filter_used(ctx)) 1733 em_if_vlan_filter_enable(sc); 1734 } 1735 return (0); 1736 } 1737 1738 static u_int 1739 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1740 { 1741 u8 *mta = arg; 1742 1743 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1744 return (0); 1745 1746 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1747 1748 return (1); 1749 } 1750 1751 /********************************************************************* 1752 * Multicast Update 1753 * 1754 * This routine is called whenever multicast address list is updated. 1755 * 1756 **********************************************************************/ 1757 static void 1758 em_if_multi_set(if_ctx_t ctx) 1759 { 1760 struct e1000_softc *sc = iflib_get_softc(ctx); 1761 if_t ifp = iflib_get_ifp(ctx); 1762 u8 *mta; /* Multicast array memory */ 1763 u32 reg_rctl = 0; 1764 int mcnt = 0; 1765 1766 IOCTL_DEBUGOUT("em_set_multi: begin"); 1767 1768 mta = sc->mta; 1769 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1770 1771 if (sc->hw.mac.type == e1000_82542 && 1772 sc->hw.revision_id == E1000_REVISION_2) { 1773 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1774 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1775 e1000_pci_clear_mwi(&sc->hw); 1776 reg_rctl |= E1000_RCTL_RST; 1777 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1778 msec_delay(5); 1779 } 1780 1781 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1782 1783 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1784 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1785 1786 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1787 1788 if (if_getflags(ifp) & IFF_PROMISC) 1789 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1790 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1791 if_getflags(ifp) & IFF_ALLMULTI) { 1792 reg_rctl |= E1000_RCTL_MPE; 1793 reg_rctl &= ~E1000_RCTL_UPE; 1794 } else 1795 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1796 1797 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1798 1799 if (sc->hw.mac.type == e1000_82542 && 1800 sc->hw.revision_id == E1000_REVISION_2) { 1801 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1802 reg_rctl &= ~E1000_RCTL_RST; 1803 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1804 msec_delay(5); 1805 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1806 e1000_pci_set_mwi(&sc->hw); 1807 } 1808 } 1809 1810 /********************************************************************* 1811 * Timer routine 1812 * 1813 * This routine schedules em_if_update_admin_status() to check for 1814 * link status and to gather statistics as well as to perform some 1815 * controller-specific hardware patting. 1816 * 1817 **********************************************************************/ 1818 static void 1819 em_if_timer(if_ctx_t ctx, uint16_t qid) 1820 { 1821 1822 if (qid != 0) 1823 return; 1824 1825 iflib_admin_intr_deferred(ctx); 1826 } 1827 1828 static void 1829 em_if_update_admin_status(if_ctx_t ctx) 1830 { 1831 struct e1000_softc *sc = iflib_get_softc(ctx); 1832 struct e1000_hw *hw = &sc->hw; 1833 device_t dev = iflib_get_dev(ctx); 1834 u32 link_check, thstat, ctrl; 1835 bool automasked = false; 1836 1837 link_check = thstat = ctrl = 0; 1838 /* Get the cached link value or read phy for real */ 1839 switch (hw->phy.media_type) { 1840 case e1000_media_type_copper: 1841 if (hw->mac.get_link_status) { 1842 if (hw->mac.type == e1000_pch_spt) 1843 msec_delay(50); 1844 /* Do the work to read phy */ 1845 e1000_check_for_link(hw); 1846 link_check = !hw->mac.get_link_status; 1847 if (link_check) /* ESB2 fix */ 1848 e1000_cfg_on_link_up(hw); 1849 } else { 1850 link_check = true; 1851 } 1852 break; 1853 case e1000_media_type_fiber: 1854 e1000_check_for_link(hw); 1855 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1856 E1000_STATUS_LU); 1857 break; 1858 case e1000_media_type_internal_serdes: 1859 e1000_check_for_link(hw); 1860 link_check = hw->mac.serdes_has_link; 1861 break; 1862 /* VF device is type_unknown */ 1863 case e1000_media_type_unknown: 1864 e1000_check_for_link(hw); 1865 link_check = !hw->mac.get_link_status; 1866 /* FALLTHROUGH */ 1867 default: 1868 break; 1869 } 1870 1871 /* Check for thermal downshift or shutdown */ 1872 if (hw->mac.type == e1000_i350) { 1873 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1874 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1875 } 1876 1877 /* Now check for a transition */ 1878 if (link_check && (sc->link_active == 0)) { 1879 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1880 &sc->link_duplex); 1881 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1882 if ((sc->link_speed != SPEED_1000) && 1883 ((hw->mac.type == e1000_82571) || 1884 (hw->mac.type == e1000_82572))) { 1885 int tarc0; 1886 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1887 tarc0 &= ~TARC_SPEED_MODE_BIT; 1888 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1889 } 1890 if (bootverbose) 1891 device_printf(dev, "Link is up %d Mbps %s\n", 1892 sc->link_speed, 1893 ((sc->link_duplex == FULL_DUPLEX) ? 1894 "Full Duplex" : "Half Duplex")); 1895 sc->link_active = 1; 1896 sc->smartspeed = 0; 1897 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1898 E1000_CTRL_EXT_LINK_MODE_GMII && 1899 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1900 device_printf(dev, "Link: thermal downshift\n"); 1901 /* Delay Link Up for Phy update */ 1902 if (((hw->mac.type == e1000_i210) || 1903 (hw->mac.type == e1000_i211)) && 1904 (hw->phy.id == I210_I_PHY_ID)) 1905 msec_delay(I210_LINK_DELAY); 1906 /* Reset if the media type changed. */ 1907 if (hw->dev_spec._82575.media_changed && 1908 hw->mac.type >= igb_mac_min) { 1909 hw->dev_spec._82575.media_changed = false; 1910 sc->flags |= IGB_MEDIA_RESET; 1911 em_reset(ctx); 1912 } 1913 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 1914 if (hw->mac.type < igb_mac_min) 1915 automasked = em_automask_tso(ctx); 1916 1917 /* Automasking resets the interface, so don't mark it up yet */ 1918 if (!automasked) 1919 iflib_link_state_change(ctx, LINK_STATE_UP, 1920 IF_Mbps(sc->link_speed)); 1921 } else if (!link_check && (sc->link_active == 1)) { 1922 sc->link_speed = 0; 1923 sc->link_duplex = 0; 1924 sc->link_active = 0; 1925 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1926 } 1927 em_update_stats_counters(sc); 1928 1929 /* Reset LAA into RAR[0] on 82571 */ 1930 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1931 e1000_rar_set(hw, hw->mac.addr, 0); 1932 1933 if (hw->mac.type < em_mac_min) 1934 lem_smartspeed(sc); 1935 } 1936 1937 static void 1938 em_if_watchdog_reset(if_ctx_t ctx) 1939 { 1940 struct e1000_softc *sc = iflib_get_softc(ctx); 1941 1942 /* 1943 * Just count the event; iflib(4) will already trigger a 1944 * sufficient reset of the controller. 1945 */ 1946 sc->watchdog_events++; 1947 } 1948 1949 /********************************************************************* 1950 * 1951 * This routine disables all traffic on the adapter by issuing a 1952 * global reset on the MAC. 1953 * 1954 **********************************************************************/ 1955 static void 1956 em_if_stop(if_ctx_t ctx) 1957 { 1958 struct e1000_softc *sc = iflib_get_softc(ctx); 1959 1960 INIT_DEBUGOUT("em_if_stop: begin"); 1961 1962 /* I219 needs special flushing to avoid hangs */ 1963 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1964 em_flush_desc_rings(sc); 1965 1966 e1000_reset_hw(&sc->hw); 1967 if (sc->hw.mac.type >= e1000_82544) 1968 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1969 1970 e1000_led_off(&sc->hw); 1971 e1000_cleanup_led(&sc->hw); 1972 } 1973 1974 /********************************************************************* 1975 * 1976 * Determine hardware revision. 1977 * 1978 **********************************************************************/ 1979 static void 1980 em_identify_hardware(if_ctx_t ctx) 1981 { 1982 device_t dev = iflib_get_dev(ctx); 1983 struct e1000_softc *sc = iflib_get_softc(ctx); 1984 1985 /* Make sure our PCI config space has the necessary stuff set */ 1986 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1987 1988 /* Save off the information about this board */ 1989 sc->hw.vendor_id = pci_get_vendor(dev); 1990 sc->hw.device_id = pci_get_device(dev); 1991 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1992 sc->hw.subsystem_vendor_id = 1993 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1994 sc->hw.subsystem_device_id = 1995 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1996 1997 /* Do Shared Code Init and Setup */ 1998 if (e1000_set_mac_type(&sc->hw)) { 1999 device_printf(dev, "Setup init failure\n"); 2000 return; 2001 } 2002 2003 /* Are we a VF device? */ 2004 if ((sc->hw.mac.type == e1000_vfadapt) || 2005 (sc->hw.mac.type == e1000_vfadapt_i350)) 2006 sc->vf_ifp = 1; 2007 else 2008 sc->vf_ifp = 0; 2009 } 2010 2011 static int 2012 em_allocate_pci_resources(if_ctx_t ctx) 2013 { 2014 struct e1000_softc *sc = iflib_get_softc(ctx); 2015 device_t dev = iflib_get_dev(ctx); 2016 int rid, val; 2017 2018 rid = PCIR_BAR(0); 2019 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2020 &rid, RF_ACTIVE); 2021 if (sc->memory == NULL) { 2022 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2023 return (ENXIO); 2024 } 2025 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2026 sc->osdep.mem_bus_space_handle = 2027 rman_get_bushandle(sc->memory); 2028 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2029 2030 /* Only older adapters use IO mapping */ 2031 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2032 /* Figure our where our IO BAR is ? */ 2033 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2034 val = pci_read_config(dev, rid, 4); 2035 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2036 break; 2037 } 2038 rid += 4; 2039 /* check for 64bit BAR */ 2040 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2041 rid += 4; 2042 } 2043 if (rid >= PCIR_CIS) { 2044 device_printf(dev, "Unable to locate IO BAR\n"); 2045 return (ENXIO); 2046 } 2047 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2048 &rid, RF_ACTIVE); 2049 if (sc->ioport == NULL) { 2050 device_printf(dev, "Unable to allocate bus resource: " 2051 "ioport\n"); 2052 return (ENXIO); 2053 } 2054 sc->hw.io_base = 0; 2055 sc->osdep.io_bus_space_tag = 2056 rman_get_bustag(sc->ioport); 2057 sc->osdep.io_bus_space_handle = 2058 rman_get_bushandle(sc->ioport); 2059 } 2060 2061 sc->hw.back = &sc->osdep; 2062 2063 return (0); 2064 } 2065 2066 /********************************************************************* 2067 * 2068 * Set up the MSI-X Interrupt handlers 2069 * 2070 **********************************************************************/ 2071 static int 2072 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2073 { 2074 struct e1000_softc *sc = iflib_get_softc(ctx); 2075 struct em_rx_queue *rx_que = sc->rx_queues; 2076 struct em_tx_queue *tx_que = sc->tx_queues; 2077 int error, rid, i, vector = 0, rx_vectors; 2078 char buf[16]; 2079 2080 /* First set up ring resources */ 2081 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2082 rid = vector + 1; 2083 snprintf(buf, sizeof(buf), "rxq%d", i); 2084 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2085 if (error) { 2086 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2087 sc->rx_num_queues = i + 1; 2088 goto fail; 2089 } 2090 2091 rx_que->msix = vector; 2092 2093 /* 2094 * Set the bit to enable interrupt 2095 * in E1000_IMS -- bits 20 and 21 2096 * are for RX0 and RX1, note this has 2097 * NOTHING to do with the MSI-X vector 2098 */ 2099 if (sc->hw.mac.type == e1000_82574) { 2100 rx_que->eims = 1 << (20 + i); 2101 sc->ims |= rx_que->eims; 2102 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2103 } else if (sc->hw.mac.type == e1000_82575) 2104 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2105 else 2106 rx_que->eims = 1 << vector; 2107 } 2108 rx_vectors = vector; 2109 2110 vector = 0; 2111 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2112 snprintf(buf, sizeof(buf), "txq%d", i); 2113 tx_que = &sc->tx_queues[i]; 2114 iflib_softirq_alloc_generic(ctx, 2115 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2116 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2117 2118 tx_que->msix = (vector % sc->rx_num_queues); 2119 2120 /* 2121 * Set the bit to enable interrupt 2122 * in E1000_IMS -- bits 22 and 23 2123 * are for TX0 and TX1, note this has 2124 * NOTHING to do with the MSI-X vector 2125 */ 2126 if (sc->hw.mac.type == e1000_82574) { 2127 tx_que->eims = 1 << (22 + i); 2128 sc->ims |= tx_que->eims; 2129 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2130 } else if (sc->hw.mac.type == e1000_82575) { 2131 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2132 } else { 2133 tx_que->eims = 1 << i; 2134 } 2135 } 2136 2137 /* Link interrupt */ 2138 rid = rx_vectors + 1; 2139 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2140 2141 if (error) { 2142 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2143 goto fail; 2144 } 2145 sc->linkvec = rx_vectors; 2146 if (sc->hw.mac.type < igb_mac_min) { 2147 sc->ivars |= (8 | rx_vectors) << 16; 2148 sc->ivars |= 0x80000000; 2149 /* Enable the "Other" interrupt type for link status change */ 2150 sc->ims |= E1000_IMS_OTHER; 2151 } 2152 2153 return (0); 2154 fail: 2155 iflib_irq_free(ctx, &sc->irq); 2156 rx_que = sc->rx_queues; 2157 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2158 iflib_irq_free(ctx, &rx_que->que_irq); 2159 return (error); 2160 } 2161 2162 static void 2163 igb_configure_queues(struct e1000_softc *sc) 2164 { 2165 struct e1000_hw *hw = &sc->hw; 2166 struct em_rx_queue *rx_que; 2167 struct em_tx_queue *tx_que; 2168 u32 tmp, ivar = 0, newitr = 0; 2169 2170 /* First turn on RSS capability */ 2171 if (hw->mac.type != e1000_82575) 2172 E1000_WRITE_REG(hw, E1000_GPIE, 2173 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2174 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2175 2176 /* Turn on MSI-X */ 2177 switch (hw->mac.type) { 2178 case e1000_82580: 2179 case e1000_i350: 2180 case e1000_i354: 2181 case e1000_i210: 2182 case e1000_i211: 2183 case e1000_vfadapt: 2184 case e1000_vfadapt_i350: 2185 /* RX entries */ 2186 for (int i = 0; i < sc->rx_num_queues; i++) { 2187 u32 index = i >> 1; 2188 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2189 rx_que = &sc->rx_queues[i]; 2190 if (i & 1) { 2191 ivar &= 0xFF00FFFF; 2192 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2193 } else { 2194 ivar &= 0xFFFFFF00; 2195 ivar |= rx_que->msix | E1000_IVAR_VALID; 2196 } 2197 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2198 } 2199 /* TX entries */ 2200 for (int i = 0; i < sc->tx_num_queues; i++) { 2201 u32 index = i >> 1; 2202 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2203 tx_que = &sc->tx_queues[i]; 2204 if (i & 1) { 2205 ivar &= 0x00FFFFFF; 2206 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2207 } else { 2208 ivar &= 0xFFFF00FF; 2209 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2210 } 2211 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2212 sc->que_mask |= tx_que->eims; 2213 } 2214 2215 /* And for the link interrupt */ 2216 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2217 sc->link_mask = 1 << sc->linkvec; 2218 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2219 break; 2220 case e1000_82576: 2221 /* RX entries */ 2222 for (int i = 0; i < sc->rx_num_queues; i++) { 2223 u32 index = i & 0x7; /* Each IVAR has two entries */ 2224 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2225 rx_que = &sc->rx_queues[i]; 2226 if (i < 8) { 2227 ivar &= 0xFFFFFF00; 2228 ivar |= rx_que->msix | E1000_IVAR_VALID; 2229 } else { 2230 ivar &= 0xFF00FFFF; 2231 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2232 } 2233 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2234 sc->que_mask |= rx_que->eims; 2235 } 2236 /* TX entries */ 2237 for (int i = 0; i < sc->tx_num_queues; i++) { 2238 u32 index = i & 0x7; /* Each IVAR has two entries */ 2239 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2240 tx_que = &sc->tx_queues[i]; 2241 if (i < 8) { 2242 ivar &= 0xFFFF00FF; 2243 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2244 } else { 2245 ivar &= 0x00FFFFFF; 2246 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2247 } 2248 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2249 sc->que_mask |= tx_que->eims; 2250 } 2251 2252 /* And for the link interrupt */ 2253 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2254 sc->link_mask = 1 << sc->linkvec; 2255 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2256 break; 2257 2258 case e1000_82575: 2259 /* enable MSI-X support*/ 2260 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2261 tmp |= E1000_CTRL_EXT_PBA_CLR; 2262 /* Auto-Mask interrupts upon ICR read. */ 2263 tmp |= E1000_CTRL_EXT_EIAME; 2264 tmp |= E1000_CTRL_EXT_IRCA; 2265 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2266 2267 /* Queues */ 2268 for (int i = 0; i < sc->rx_num_queues; i++) { 2269 rx_que = &sc->rx_queues[i]; 2270 tmp = E1000_EICR_RX_QUEUE0 << i; 2271 tmp |= E1000_EICR_TX_QUEUE0 << i; 2272 rx_que->eims = tmp; 2273 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2274 i, rx_que->eims); 2275 sc->que_mask |= rx_que->eims; 2276 } 2277 2278 /* Link */ 2279 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2280 E1000_EIMS_OTHER); 2281 sc->link_mask |= E1000_EIMS_OTHER; 2282 default: 2283 break; 2284 } 2285 2286 /* Set the igb starting interrupt rate */ 2287 if (em_max_interrupt_rate > 0) { 2288 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2289 2290 if (hw->mac.type == e1000_82575) 2291 newitr |= newitr << 16; 2292 else 2293 newitr |= E1000_EITR_CNT_IGNR; 2294 2295 for (int i = 0; i < sc->rx_num_queues; i++) { 2296 rx_que = &sc->rx_queues[i]; 2297 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2298 } 2299 } 2300 2301 return; 2302 } 2303 2304 static void 2305 em_free_pci_resources(if_ctx_t ctx) 2306 { 2307 struct e1000_softc *sc = iflib_get_softc(ctx); 2308 struct em_rx_queue *que = sc->rx_queues; 2309 device_t dev = iflib_get_dev(ctx); 2310 2311 /* Release all MSI-X queue resources */ 2312 if (sc->intr_type == IFLIB_INTR_MSIX) 2313 iflib_irq_free(ctx, &sc->irq); 2314 2315 if (que != NULL) { 2316 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2317 iflib_irq_free(ctx, &que->que_irq); 2318 } 2319 } 2320 2321 if (sc->memory != NULL) { 2322 bus_release_resource(dev, SYS_RES_MEMORY, 2323 rman_get_rid(sc->memory), sc->memory); 2324 sc->memory = NULL; 2325 } 2326 2327 if (sc->flash != NULL) { 2328 bus_release_resource(dev, SYS_RES_MEMORY, 2329 rman_get_rid(sc->flash), sc->flash); 2330 sc->flash = NULL; 2331 } 2332 2333 if (sc->ioport != NULL) { 2334 bus_release_resource(dev, SYS_RES_IOPORT, 2335 rman_get_rid(sc->ioport), sc->ioport); 2336 sc->ioport = NULL; 2337 } 2338 } 2339 2340 /* Set up MSI or MSI-X */ 2341 static int 2342 em_setup_msix(if_ctx_t ctx) 2343 { 2344 struct e1000_softc *sc = iflib_get_softc(ctx); 2345 2346 if (sc->hw.mac.type == e1000_82574) { 2347 em_enable_vectors_82574(ctx); 2348 } 2349 return (0); 2350 } 2351 2352 /********************************************************************* 2353 * 2354 * Workaround for SmartSpeed on 82541 and 82547 controllers 2355 * 2356 **********************************************************************/ 2357 static void 2358 lem_smartspeed(struct e1000_softc *sc) 2359 { 2360 u16 phy_tmp; 2361 2362 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2363 sc->hw.mac.autoneg == 0 || 2364 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2365 return; 2366 2367 if (sc->smartspeed == 0) { 2368 /* If Master/Slave config fault is asserted twice, 2369 * we assume back-to-back */ 2370 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2371 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2372 return; 2373 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2374 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2375 e1000_read_phy_reg(&sc->hw, 2376 PHY_1000T_CTRL, &phy_tmp); 2377 if(phy_tmp & CR_1000T_MS_ENABLE) { 2378 phy_tmp &= ~CR_1000T_MS_ENABLE; 2379 e1000_write_phy_reg(&sc->hw, 2380 PHY_1000T_CTRL, phy_tmp); 2381 sc->smartspeed++; 2382 if(sc->hw.mac.autoneg && 2383 !e1000_copper_link_autoneg(&sc->hw) && 2384 !e1000_read_phy_reg(&sc->hw, 2385 PHY_CONTROL, &phy_tmp)) { 2386 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2387 MII_CR_RESTART_AUTO_NEG); 2388 e1000_write_phy_reg(&sc->hw, 2389 PHY_CONTROL, phy_tmp); 2390 } 2391 } 2392 } 2393 return; 2394 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2395 /* If still no link, perhaps using 2/3 pair cable */ 2396 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2397 phy_tmp |= CR_1000T_MS_ENABLE; 2398 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2399 if(sc->hw.mac.autoneg && 2400 !e1000_copper_link_autoneg(&sc->hw) && 2401 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2402 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2403 MII_CR_RESTART_AUTO_NEG); 2404 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2405 } 2406 } 2407 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2408 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2409 sc->smartspeed = 0; 2410 } 2411 2412 /********************************************************************* 2413 * 2414 * Initialize the DMA Coalescing feature 2415 * 2416 **********************************************************************/ 2417 static void 2418 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2419 { 2420 device_t dev = sc->dev; 2421 struct e1000_hw *hw = &sc->hw; 2422 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2423 u16 hwm; 2424 u16 max_frame_size; 2425 2426 if (hw->mac.type == e1000_i211) 2427 return; 2428 2429 max_frame_size = sc->shared->isc_max_frame_size; 2430 if (hw->mac.type > e1000_82580) { 2431 2432 if (sc->dmac == 0) { /* Disabling it */ 2433 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2434 return; 2435 } else 2436 device_printf(dev, "DMA Coalescing enabled\n"); 2437 2438 /* Set starting threshold */ 2439 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2440 2441 hwm = 64 * pba - max_frame_size / 16; 2442 if (hwm < 64 * (pba - 6)) 2443 hwm = 64 * (pba - 6); 2444 reg = E1000_READ_REG(hw, E1000_FCRTC); 2445 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2446 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2447 & E1000_FCRTC_RTH_COAL_MASK); 2448 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2449 2450 2451 dmac = pba - max_frame_size / 512; 2452 if (dmac < pba - 10) 2453 dmac = pba - 10; 2454 reg = E1000_READ_REG(hw, E1000_DMACR); 2455 reg &= ~E1000_DMACR_DMACTHR_MASK; 2456 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2457 & E1000_DMACR_DMACTHR_MASK); 2458 2459 /* transition to L0x or L1 if available..*/ 2460 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2461 2462 /* Check if status is 2.5Gb backplane connection 2463 * before configuration of watchdog timer, which is 2464 * in msec values in 12.8usec intervals 2465 * watchdog timer= msec values in 32usec intervals 2466 * for non 2.5Gb connection 2467 */ 2468 if (hw->mac.type == e1000_i354) { 2469 int status = E1000_READ_REG(hw, E1000_STATUS); 2470 if ((status & E1000_STATUS_2P5_SKU) && 2471 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2472 reg |= ((sc->dmac * 5) >> 6); 2473 else 2474 reg |= (sc->dmac >> 5); 2475 } else { 2476 reg |= (sc->dmac >> 5); 2477 } 2478 2479 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2480 2481 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2482 2483 /* Set the interval before transition */ 2484 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2485 if (hw->mac.type == e1000_i350) 2486 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2487 /* 2488 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2489 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2490 */ 2491 if (hw->mac.type == e1000_i354) { 2492 int status = E1000_READ_REG(hw, E1000_STATUS); 2493 if ((status & E1000_STATUS_2P5_SKU) && 2494 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2495 reg |= 0xA; 2496 else 2497 reg |= 0x4; 2498 } else { 2499 reg |= 0x4; 2500 } 2501 2502 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2503 2504 /* free space in tx packet buffer to wake from DMA coal */ 2505 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2506 (2 * max_frame_size)) >> 6); 2507 2508 /* make low power state decision controlled by DMA coal */ 2509 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2510 reg &= ~E1000_PCIEMISC_LX_DECISION; 2511 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2512 2513 } else if (hw->mac.type == e1000_82580) { 2514 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2515 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2516 reg & ~E1000_PCIEMISC_LX_DECISION); 2517 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2518 } 2519 } 2520 /********************************************************************* 2521 * The 3 following flush routines are used as a workaround in the 2522 * I219 client parts and only for them. 2523 * 2524 * em_flush_tx_ring - remove all descriptors from the tx_ring 2525 * 2526 * We want to clear all pending descriptors from the TX ring. 2527 * zeroing happens when the HW reads the regs. We assign the ring itself as 2528 * the data of the next descriptor. We don't care about the data we are about 2529 * to reset the HW. 2530 **********************************************************************/ 2531 static void 2532 em_flush_tx_ring(struct e1000_softc *sc) 2533 { 2534 struct e1000_hw *hw = &sc->hw; 2535 struct tx_ring *txr = &sc->tx_queues->txr; 2536 struct e1000_tx_desc *txd; 2537 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2538 u16 size = 512; 2539 2540 tctl = E1000_READ_REG(hw, E1000_TCTL); 2541 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2542 2543 txd = &txr->tx_base[txr->tx_cidx_processed]; 2544 2545 /* Just use the ring as a dummy buffer addr */ 2546 txd->buffer_addr = txr->tx_paddr; 2547 txd->lower.data = htole32(txd_lower | size); 2548 txd->upper.data = 0; 2549 2550 /* flush descriptors to memory before notifying the HW */ 2551 wmb(); 2552 2553 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2554 mb(); 2555 usec_delay(250); 2556 } 2557 2558 /********************************************************************* 2559 * em_flush_rx_ring - remove all descriptors from the rx_ring 2560 * 2561 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2562 **********************************************************************/ 2563 static void 2564 em_flush_rx_ring(struct e1000_softc *sc) 2565 { 2566 struct e1000_hw *hw = &sc->hw; 2567 u32 rctl, rxdctl; 2568 2569 rctl = E1000_READ_REG(hw, E1000_RCTL); 2570 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2571 E1000_WRITE_FLUSH(hw); 2572 usec_delay(150); 2573 2574 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2575 /* zero the lower 14 bits (prefetch and host thresholds) */ 2576 rxdctl &= 0xffffc000; 2577 /* 2578 * update thresholds: prefetch threshold to 31, host threshold to 1 2579 * and make sure the granularity is "descriptors" and not "cache lines" 2580 */ 2581 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2582 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2583 2584 /* momentarily enable the RX ring for the changes to take effect */ 2585 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2586 E1000_WRITE_FLUSH(hw); 2587 usec_delay(150); 2588 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2589 } 2590 2591 /********************************************************************* 2592 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2593 * 2594 * In I219, the descriptor rings must be emptied before resetting the HW 2595 * or before changing the device state to D3 during runtime (runtime PM). 2596 * 2597 * Failure to do this will cause the HW to enter a unit hang state which can 2598 * only be released by PCI reset on the device 2599 * 2600 **********************************************************************/ 2601 static void 2602 em_flush_desc_rings(struct e1000_softc *sc) 2603 { 2604 struct e1000_hw *hw = &sc->hw; 2605 device_t dev = sc->dev; 2606 u16 hang_state; 2607 u32 fext_nvm11, tdlen; 2608 2609 /* First, disable MULR fix in FEXTNVM11 */ 2610 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2611 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2612 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2613 2614 /* do nothing if we're not in faulty state, or if the queue is empty */ 2615 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2616 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2617 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2618 return; 2619 em_flush_tx_ring(sc); 2620 2621 /* recheck, maybe the fault is caused by the rx ring */ 2622 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2623 if (hang_state & FLUSH_DESC_REQUIRED) 2624 em_flush_rx_ring(sc); 2625 } 2626 2627 2628 /********************************************************************* 2629 * 2630 * Initialize the hardware to a configuration as specified by the 2631 * sc structure. 2632 * 2633 **********************************************************************/ 2634 static void 2635 em_reset(if_ctx_t ctx) 2636 { 2637 device_t dev = iflib_get_dev(ctx); 2638 struct e1000_softc *sc = iflib_get_softc(ctx); 2639 if_t ifp = iflib_get_ifp(ctx); 2640 struct e1000_hw *hw = &sc->hw; 2641 u32 rx_buffer_size; 2642 u32 pba; 2643 2644 INIT_DEBUGOUT("em_reset: begin"); 2645 /* Let the firmware know the OS is in control */ 2646 em_get_hw_control(sc); 2647 2648 /* Set up smart power down as default off on newer adapters. */ 2649 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2650 hw->mac.type == e1000_82572)) { 2651 u16 phy_tmp = 0; 2652 2653 /* Speed up time to link by disabling smart power down. */ 2654 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2655 phy_tmp &= ~IGP02E1000_PM_SPD; 2656 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2657 } 2658 2659 /* 2660 * Packet Buffer Allocation (PBA) 2661 * Writing PBA sets the receive portion of the buffer 2662 * the remainder is used for the transmit buffer. 2663 */ 2664 switch (hw->mac.type) { 2665 /* 82547: Total Packet Buffer is 40K */ 2666 case e1000_82547: 2667 case e1000_82547_rev_2: 2668 if (hw->mac.max_frame_size > 8192) 2669 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2670 else 2671 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2672 break; 2673 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2674 case e1000_82571: 2675 case e1000_82572: 2676 case e1000_80003es2lan: 2677 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2678 break; 2679 /* 82573: Total Packet Buffer is 32K */ 2680 case e1000_82573: 2681 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2682 break; 2683 case e1000_82574: 2684 case e1000_82583: 2685 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2686 break; 2687 case e1000_ich8lan: 2688 pba = E1000_PBA_8K; 2689 break; 2690 case e1000_ich9lan: 2691 case e1000_ich10lan: 2692 /* Boost Receive side for jumbo frames */ 2693 if (hw->mac.max_frame_size > 4096) 2694 pba = E1000_PBA_14K; 2695 else 2696 pba = E1000_PBA_10K; 2697 break; 2698 case e1000_pchlan: 2699 case e1000_pch2lan: 2700 case e1000_pch_lpt: 2701 case e1000_pch_spt: 2702 case e1000_pch_cnp: 2703 case e1000_pch_tgp: 2704 case e1000_pch_adp: 2705 case e1000_pch_mtp: 2706 case e1000_pch_ptp: 2707 pba = E1000_PBA_26K; 2708 break; 2709 case e1000_82575: 2710 pba = E1000_PBA_32K; 2711 break; 2712 case e1000_82576: 2713 case e1000_vfadapt: 2714 pba = E1000_READ_REG(hw, E1000_RXPBS); 2715 pba &= E1000_RXPBS_SIZE_MASK_82576; 2716 break; 2717 case e1000_82580: 2718 case e1000_i350: 2719 case e1000_i354: 2720 case e1000_vfadapt_i350: 2721 pba = E1000_READ_REG(hw, E1000_RXPBS); 2722 pba = e1000_rxpbs_adjust_82580(pba); 2723 break; 2724 case e1000_i210: 2725 case e1000_i211: 2726 pba = E1000_PBA_34K; 2727 break; 2728 default: 2729 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2730 if (hw->mac.max_frame_size > 8192) 2731 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2732 else 2733 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2734 } 2735 2736 /* Special needs in case of Jumbo frames */ 2737 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2738 u32 tx_space, min_tx, min_rx; 2739 pba = E1000_READ_REG(hw, E1000_PBA); 2740 tx_space = pba >> 16; 2741 pba &= 0xffff; 2742 min_tx = (hw->mac.max_frame_size + 2743 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2744 min_tx = roundup2(min_tx, 1024); 2745 min_tx >>= 10; 2746 min_rx = hw->mac.max_frame_size; 2747 min_rx = roundup2(min_rx, 1024); 2748 min_rx >>= 10; 2749 if (tx_space < min_tx && 2750 ((min_tx - tx_space) < pba)) { 2751 pba = pba - (min_tx - tx_space); 2752 /* 2753 * if short on rx space, rx wins 2754 * and must trump tx adjustment 2755 */ 2756 if (pba < min_rx) 2757 pba = min_rx; 2758 } 2759 E1000_WRITE_REG(hw, E1000_PBA, pba); 2760 } 2761 2762 if (hw->mac.type < igb_mac_min) 2763 E1000_WRITE_REG(hw, E1000_PBA, pba); 2764 2765 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2766 2767 /* 2768 * These parameters control the automatic generation (Tx) and 2769 * response (Rx) to Ethernet PAUSE frames. 2770 * - High water mark should allow for at least two frames to be 2771 * received after sending an XOFF. 2772 * - Low water mark works best when it is very near the high water mark. 2773 * This allows the receiver to restart by sending XON when it has 2774 * drained a bit. Here we use an arbitrary value of 1500 which will 2775 * restart after one full frame is pulled from the buffer. There 2776 * could be several smaller frames in the buffer and if so they will 2777 * not trigger the XON until their total number reduces the buffer 2778 * by 1500. 2779 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2780 */ 2781 rx_buffer_size = (pba & 0xffff) << 10; 2782 hw->fc.high_water = rx_buffer_size - 2783 roundup2(hw->mac.max_frame_size, 1024); 2784 hw->fc.low_water = hw->fc.high_water - 1500; 2785 2786 if (sc->fc) /* locally set flow control value? */ 2787 hw->fc.requested_mode = sc->fc; 2788 else 2789 hw->fc.requested_mode = e1000_fc_full; 2790 2791 if (hw->mac.type == e1000_80003es2lan) 2792 hw->fc.pause_time = 0xFFFF; 2793 else 2794 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2795 2796 hw->fc.send_xon = true; 2797 2798 /* Device specific overrides/settings */ 2799 switch (hw->mac.type) { 2800 case e1000_pchlan: 2801 /* Workaround: no TX flow ctrl for PCH */ 2802 hw->fc.requested_mode = e1000_fc_rx_pause; 2803 hw->fc.pause_time = 0xFFFF; /* override */ 2804 if (if_getmtu(ifp) > ETHERMTU) { 2805 hw->fc.high_water = 0x3500; 2806 hw->fc.low_water = 0x1500; 2807 } else { 2808 hw->fc.high_water = 0x5000; 2809 hw->fc.low_water = 0x3000; 2810 } 2811 hw->fc.refresh_time = 0x1000; 2812 break; 2813 case e1000_pch2lan: 2814 case e1000_pch_lpt: 2815 case e1000_pch_spt: 2816 case e1000_pch_cnp: 2817 case e1000_pch_tgp: 2818 case e1000_pch_adp: 2819 case e1000_pch_mtp: 2820 case e1000_pch_ptp: 2821 hw->fc.high_water = 0x5C20; 2822 hw->fc.low_water = 0x5048; 2823 hw->fc.pause_time = 0x0650; 2824 hw->fc.refresh_time = 0x0400; 2825 /* Jumbos need adjusted PBA */ 2826 if (if_getmtu(ifp) > ETHERMTU) 2827 E1000_WRITE_REG(hw, E1000_PBA, 12); 2828 else 2829 E1000_WRITE_REG(hw, E1000_PBA, 26); 2830 break; 2831 case e1000_82575: 2832 case e1000_82576: 2833 /* 8-byte granularity */ 2834 hw->fc.low_water = hw->fc.high_water - 8; 2835 break; 2836 case e1000_82580: 2837 case e1000_i350: 2838 case e1000_i354: 2839 case e1000_i210: 2840 case e1000_i211: 2841 case e1000_vfadapt: 2842 case e1000_vfadapt_i350: 2843 /* 16-byte granularity */ 2844 hw->fc.low_water = hw->fc.high_water - 16; 2845 break; 2846 case e1000_ich9lan: 2847 case e1000_ich10lan: 2848 if (if_getmtu(ifp) > ETHERMTU) { 2849 hw->fc.high_water = 0x2800; 2850 hw->fc.low_water = hw->fc.high_water - 8; 2851 break; 2852 } 2853 /* FALLTHROUGH */ 2854 default: 2855 if (hw->mac.type == e1000_80003es2lan) 2856 hw->fc.pause_time = 0xFFFF; 2857 break; 2858 } 2859 2860 /* I219 needs some special flushing to avoid hangs */ 2861 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2862 em_flush_desc_rings(sc); 2863 2864 /* Issue a global reset */ 2865 e1000_reset_hw(hw); 2866 if (hw->mac.type >= igb_mac_min) { 2867 E1000_WRITE_REG(hw, E1000_WUC, 0); 2868 } else { 2869 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2870 em_disable_aspm(sc); 2871 } 2872 if (sc->flags & IGB_MEDIA_RESET) { 2873 e1000_setup_init_funcs(hw, true); 2874 e1000_get_bus_info(hw); 2875 sc->flags &= ~IGB_MEDIA_RESET; 2876 } 2877 /* and a re-init */ 2878 if (e1000_init_hw(hw) < 0) { 2879 device_printf(dev, "Hardware Initialization Failed\n"); 2880 return; 2881 } 2882 if (hw->mac.type >= igb_mac_min) 2883 igb_init_dmac(sc, pba); 2884 2885 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2886 e1000_get_phy_info(hw); 2887 e1000_check_for_link(hw); 2888 } 2889 2890 /* 2891 * Initialise the RSS mapping for NICs that support multiple transmit/ 2892 * receive rings. 2893 */ 2894 2895 #define RSSKEYLEN 10 2896 static void 2897 em_initialize_rss_mapping(struct e1000_softc *sc) 2898 { 2899 uint8_t rss_key[4 * RSSKEYLEN]; 2900 uint32_t reta = 0; 2901 struct e1000_hw *hw = &sc->hw; 2902 int i; 2903 2904 /* 2905 * Configure RSS key 2906 */ 2907 arc4rand(rss_key, sizeof(rss_key), 0); 2908 for (i = 0; i < RSSKEYLEN; ++i) { 2909 uint32_t rssrk = 0; 2910 2911 rssrk = EM_RSSRK_VAL(rss_key, i); 2912 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2913 } 2914 2915 /* 2916 * Configure RSS redirect table in following fashion: 2917 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2918 */ 2919 for (i = 0; i < sizeof(reta); ++i) { 2920 uint32_t q; 2921 2922 q = (i % sc->rx_num_queues) << 7; 2923 reta |= q << (8 * i); 2924 } 2925 2926 for (i = 0; i < 32; ++i) 2927 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2928 2929 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2930 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2931 E1000_MRQC_RSS_FIELD_IPV4 | 2932 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2933 E1000_MRQC_RSS_FIELD_IPV6_EX | 2934 E1000_MRQC_RSS_FIELD_IPV6); 2935 } 2936 2937 static void 2938 igb_initialize_rss_mapping(struct e1000_softc *sc) 2939 { 2940 struct e1000_hw *hw = &sc->hw; 2941 int i; 2942 int queue_id; 2943 u32 reta; 2944 u32 rss_key[10], mrqc, shift = 0; 2945 2946 /* XXX? */ 2947 if (hw->mac.type == e1000_82575) 2948 shift = 6; 2949 2950 /* 2951 * The redirection table controls which destination 2952 * queue each bucket redirects traffic to. 2953 * Each DWORD represents four queues, with the LSB 2954 * being the first queue in the DWORD. 2955 * 2956 * This just allocates buckets to queues using round-robin 2957 * allocation. 2958 * 2959 * NOTE: It Just Happens to line up with the default 2960 * RSS allocation method. 2961 */ 2962 2963 /* Warning FM follows */ 2964 reta = 0; 2965 for (i = 0; i < 128; i++) { 2966 #ifdef RSS 2967 queue_id = rss_get_indirection_to_bucket(i); 2968 /* 2969 * If we have more queues than buckets, we'll 2970 * end up mapping buckets to a subset of the 2971 * queues. 2972 * 2973 * If we have more buckets than queues, we'll 2974 * end up instead assigning multiple buckets 2975 * to queues. 2976 * 2977 * Both are suboptimal, but we need to handle 2978 * the case so we don't go out of bounds 2979 * indexing arrays and such. 2980 */ 2981 queue_id = queue_id % sc->rx_num_queues; 2982 #else 2983 queue_id = (i % sc->rx_num_queues); 2984 #endif 2985 /* Adjust if required */ 2986 queue_id = queue_id << shift; 2987 2988 /* 2989 * The low 8 bits are for hash value (n+0); 2990 * The next 8 bits are for hash value (n+1), etc. 2991 */ 2992 reta = reta >> 8; 2993 reta = reta | ( ((uint32_t) queue_id) << 24); 2994 if ((i & 3) == 3) { 2995 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2996 reta = 0; 2997 } 2998 } 2999 3000 /* Now fill in hash table */ 3001 3002 /* 3003 * MRQC: Multiple Receive Queues Command 3004 * Set queuing to RSS control, number depends on the device. 3005 */ 3006 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3007 3008 #ifdef RSS 3009 /* XXX ew typecasting */ 3010 rss_getkey((uint8_t *) &rss_key); 3011 #else 3012 arc4rand(&rss_key, sizeof(rss_key), 0); 3013 #endif 3014 for (i = 0; i < 10; i++) 3015 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3016 3017 /* 3018 * Configure the RSS fields to hash upon. 3019 */ 3020 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3021 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3022 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3023 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3024 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3025 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3026 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3027 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3028 3029 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3030 } 3031 3032 /********************************************************************* 3033 * 3034 * Setup networking device structure and register interface media. 3035 * 3036 **********************************************************************/ 3037 static int 3038 em_setup_interface(if_ctx_t ctx) 3039 { 3040 if_t ifp = iflib_get_ifp(ctx); 3041 struct e1000_softc *sc = iflib_get_softc(ctx); 3042 if_softc_ctx_t scctx = sc->shared; 3043 3044 INIT_DEBUGOUT("em_setup_interface: begin"); 3045 3046 /* Single Queue */ 3047 if (sc->tx_num_queues == 1) { 3048 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3049 if_setsendqready(ifp); 3050 } 3051 3052 /* 3053 * Specify the media types supported by this adapter and register 3054 * callbacks to update media and link information 3055 */ 3056 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3057 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3058 u_char fiber_type = IFM_1000_SX; /* default type */ 3059 3060 if (sc->hw.mac.type == e1000_82545) 3061 fiber_type = IFM_1000_LX; 3062 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3063 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3064 } else { 3065 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3066 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3067 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3068 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3069 if (sc->hw.phy.type != e1000_phy_ife) { 3070 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3071 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3072 } 3073 } 3074 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3075 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3076 return (0); 3077 } 3078 3079 static int 3080 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3081 { 3082 struct e1000_softc *sc = iflib_get_softc(ctx); 3083 if_softc_ctx_t scctx = sc->shared; 3084 int error = E1000_SUCCESS; 3085 struct em_tx_queue *que; 3086 int i, j; 3087 3088 MPASS(sc->tx_num_queues > 0); 3089 MPASS(sc->tx_num_queues == ntxqsets); 3090 3091 /* First allocate the top level queue structs */ 3092 if (!(sc->tx_queues = 3093 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3094 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3095 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3096 return(ENOMEM); 3097 } 3098 3099 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3100 /* Set up some basics */ 3101 3102 struct tx_ring *txr = &que->txr; 3103 txr->sc = que->sc = sc; 3104 que->me = txr->me = i; 3105 3106 /* Allocate report status array */ 3107 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3108 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3109 error = ENOMEM; 3110 goto fail; 3111 } 3112 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3113 txr->tx_rsq[j] = QIDX_INVALID; 3114 /* get the virtual and physical address of the hardware queues */ 3115 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3116 txr->tx_paddr = paddrs[i*ntxqs]; 3117 } 3118 3119 if (bootverbose) 3120 device_printf(iflib_get_dev(ctx), 3121 "allocated for %d tx_queues\n", sc->tx_num_queues); 3122 return (0); 3123 fail: 3124 em_if_queues_free(ctx); 3125 return (error); 3126 } 3127 3128 static int 3129 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3130 { 3131 struct e1000_softc *sc = iflib_get_softc(ctx); 3132 int error = E1000_SUCCESS; 3133 struct em_rx_queue *que; 3134 int i; 3135 3136 MPASS(sc->rx_num_queues > 0); 3137 MPASS(sc->rx_num_queues == nrxqsets); 3138 3139 /* First allocate the top level queue structs */ 3140 if (!(sc->rx_queues = 3141 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3142 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3143 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3144 error = ENOMEM; 3145 goto fail; 3146 } 3147 3148 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3149 /* Set up some basics */ 3150 struct rx_ring *rxr = &que->rxr; 3151 rxr->sc = que->sc = sc; 3152 rxr->que = que; 3153 que->me = rxr->me = i; 3154 3155 /* get the virtual and physical address of the hardware queues */ 3156 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3157 rxr->rx_paddr = paddrs[i*nrxqs]; 3158 } 3159 3160 if (bootverbose) 3161 device_printf(iflib_get_dev(ctx), 3162 "allocated for %d rx_queues\n", sc->rx_num_queues); 3163 3164 return (0); 3165 fail: 3166 em_if_queues_free(ctx); 3167 return (error); 3168 } 3169 3170 static void 3171 em_if_queues_free(if_ctx_t ctx) 3172 { 3173 struct e1000_softc *sc = iflib_get_softc(ctx); 3174 struct em_tx_queue *tx_que = sc->tx_queues; 3175 struct em_rx_queue *rx_que = sc->rx_queues; 3176 3177 if (tx_que != NULL) { 3178 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3179 struct tx_ring *txr = &tx_que->txr; 3180 if (txr->tx_rsq == NULL) 3181 break; 3182 3183 free(txr->tx_rsq, M_DEVBUF); 3184 txr->tx_rsq = NULL; 3185 } 3186 free(sc->tx_queues, M_DEVBUF); 3187 sc->tx_queues = NULL; 3188 } 3189 3190 if (rx_que != NULL) { 3191 free(sc->rx_queues, M_DEVBUF); 3192 sc->rx_queues = NULL; 3193 } 3194 } 3195 3196 /********************************************************************* 3197 * 3198 * Enable transmit unit. 3199 * 3200 **********************************************************************/ 3201 static void 3202 em_initialize_transmit_unit(if_ctx_t ctx) 3203 { 3204 struct e1000_softc *sc = iflib_get_softc(ctx); 3205 if_softc_ctx_t scctx = sc->shared; 3206 struct em_tx_queue *que; 3207 struct tx_ring *txr; 3208 struct e1000_hw *hw = &sc->hw; 3209 u32 tctl, txdctl = 0, tarc, tipg = 0; 3210 3211 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3212 3213 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3214 u64 bus_addr; 3215 caddr_t offp, endp; 3216 3217 que = &sc->tx_queues[i]; 3218 txr = &que->txr; 3219 bus_addr = txr->tx_paddr; 3220 3221 /* Clear checksum offload context. */ 3222 offp = (caddr_t)&txr->csum_flags; 3223 endp = (caddr_t)(txr + 1); 3224 bzero(offp, endp - offp); 3225 3226 /* Base and Len of TX Ring */ 3227 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3228 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3229 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3230 (u32)(bus_addr >> 32)); 3231 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3232 (u32)bus_addr); 3233 /* Init the HEAD/TAIL indices */ 3234 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3235 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3236 3237 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3238 E1000_READ_REG(hw, E1000_TDBAL(i)), 3239 E1000_READ_REG(hw, E1000_TDLEN(i))); 3240 3241 txdctl = 0; /* clear txdctl */ 3242 txdctl |= 0x1f; /* PTHRESH */ 3243 txdctl |= 1 << 8; /* HTHRESH */ 3244 txdctl |= 1 << 16;/* WTHRESH */ 3245 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3246 txdctl |= E1000_TXDCTL_GRAN; 3247 txdctl |= 1 << 25; /* LWTHRESH */ 3248 3249 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3250 } 3251 3252 /* Set the default values for the Tx Inter Packet Gap timer */ 3253 switch (hw->mac.type) { 3254 case e1000_80003es2lan: 3255 tipg = DEFAULT_82543_TIPG_IPGR1; 3256 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3257 E1000_TIPG_IPGR2_SHIFT; 3258 break; 3259 case e1000_82542: 3260 tipg = DEFAULT_82542_TIPG_IPGT; 3261 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3262 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3263 break; 3264 default: 3265 if (hw->phy.media_type == e1000_media_type_fiber || 3266 hw->phy.media_type == e1000_media_type_internal_serdes) 3267 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3268 else 3269 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3270 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3271 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3272 } 3273 3274 if (hw->mac.type < igb_mac_min) { 3275 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3276 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3277 3278 if (sc->tx_int_delay.value > 0) 3279 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3280 } 3281 3282 if (hw->mac.type >= e1000_82540) 3283 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3284 3285 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3286 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3287 tarc |= TARC_SPEED_MODE_BIT; 3288 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3289 } else if (hw->mac.type == e1000_80003es2lan) { 3290 /* errata: program both queues to unweighted RR */ 3291 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3292 tarc |= 1; 3293 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3294 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3295 tarc |= 1; 3296 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3297 } else if (hw->mac.type == e1000_82574) { 3298 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3299 tarc |= TARC_ERRATA_BIT; 3300 if ( sc->tx_num_queues > 1) { 3301 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3302 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3303 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3304 } else 3305 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3306 } 3307 3308 /* Program the Transmit Control Register */ 3309 tctl = E1000_READ_REG(hw, E1000_TCTL); 3310 tctl &= ~E1000_TCTL_CT; 3311 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3312 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3313 3314 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3315 tctl |= E1000_TCTL_MULR; 3316 3317 /* This write will effectively turn on the transmit unit. */ 3318 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3319 3320 /* SPT and KBL errata workarounds */ 3321 if (hw->mac.type == e1000_pch_spt) { 3322 u32 reg; 3323 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3324 reg |= E1000_RCTL_RDMTS_HEX; 3325 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3326 /* i218-i219 Specification Update 1.5.4.5 */ 3327 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3328 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3329 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3330 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3331 } 3332 } 3333 3334 /********************************************************************* 3335 * 3336 * Enable receive unit. 3337 * 3338 **********************************************************************/ 3339 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3340 3341 static void 3342 em_initialize_receive_unit(if_ctx_t ctx) 3343 { 3344 struct e1000_softc *sc = iflib_get_softc(ctx); 3345 if_softc_ctx_t scctx = sc->shared; 3346 if_t ifp = iflib_get_ifp(ctx); 3347 struct e1000_hw *hw = &sc->hw; 3348 struct em_rx_queue *que; 3349 int i; 3350 uint32_t rctl, rxcsum; 3351 3352 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3353 3354 /* 3355 * Make sure receives are disabled while setting 3356 * up the descriptor ring 3357 */ 3358 rctl = E1000_READ_REG(hw, E1000_RCTL); 3359 /* Do not disable if ever enabled on this hardware */ 3360 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3361 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3362 3363 /* Setup the Receive Control Register */ 3364 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3365 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3366 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3367 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3368 3369 /* Do not store bad packets */ 3370 rctl &= ~E1000_RCTL_SBP; 3371 3372 /* Enable Long Packet receive */ 3373 if (if_getmtu(ifp) > ETHERMTU) 3374 rctl |= E1000_RCTL_LPE; 3375 else 3376 rctl &= ~E1000_RCTL_LPE; 3377 3378 /* Strip the CRC */ 3379 if (!em_disable_crc_stripping) 3380 rctl |= E1000_RCTL_SECRC; 3381 3382 /* lem/em default interrupt moderation */ 3383 if (hw->mac.type < igb_mac_min) { 3384 if (hw->mac.type >= e1000_82540) { 3385 E1000_WRITE_REG(hw, E1000_RADV, sc->rx_abs_int_delay.value); 3386 3387 /* Set the default interrupt throttling rate */ 3388 E1000_WRITE_REG(hw, E1000_ITR, 3389 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3390 } 3391 3392 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3393 * long latencies are observed, like Lenovo X60. This 3394 * change eliminates the problem, but since having positive 3395 * values in RDTR is a known source of problems on other 3396 * platforms another solution is being sought. 3397 */ 3398 if (hw->mac.type == e1000_82573) 3399 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3400 else 3401 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3402 } 3403 3404 if (hw->mac.type >= em_mac_min) { 3405 uint32_t rfctl; 3406 /* Use extended rx descriptor formats */ 3407 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3408 rfctl |= E1000_RFCTL_EXTEN; 3409 3410 /* 3411 * When using MSI-X interrupts we need to throttle 3412 * using the EITR register (82574 only) 3413 */ 3414 if (hw->mac.type == e1000_82574) { 3415 for (int i = 0; i < 4; i++) 3416 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3417 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3418 /* Disable accelerated acknowledge */ 3419 rfctl |= E1000_RFCTL_ACK_DIS; 3420 } 3421 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3422 } 3423 3424 /* Set up L3 and L4 csum Rx descriptor offloads */ 3425 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3426 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3427 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3428 if (hw->mac.type > e1000_82575) 3429 rxcsum |= E1000_RXCSUM_CRCOFL; 3430 else if (hw->mac.type < em_mac_min && 3431 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3432 rxcsum |= E1000_RXCSUM_IPV6OFL; 3433 } else { 3434 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3435 if (hw->mac.type > e1000_82575) 3436 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3437 else if (hw->mac.type < em_mac_min) 3438 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3439 } 3440 3441 if (sc->rx_num_queues > 1) { 3442 /* RSS hash needed in the Rx descriptor */ 3443 rxcsum |= E1000_RXCSUM_PCSD; 3444 3445 if (hw->mac.type >= igb_mac_min) 3446 igb_initialize_rss_mapping(sc); 3447 else 3448 em_initialize_rss_mapping(sc); 3449 } 3450 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3451 3452 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3453 struct rx_ring *rxr = &que->rxr; 3454 /* Setup the Base and Length of the Rx Descriptor Ring */ 3455 u64 bus_addr = rxr->rx_paddr; 3456 #if 0 3457 u32 rdt = sc->rx_num_queues -1; /* default */ 3458 #endif 3459 3460 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3461 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3462 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3463 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3464 /* Setup the Head and Tail Descriptor Pointers */ 3465 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3466 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3467 } 3468 3469 /* 3470 * Set PTHRESH for improved jumbo performance 3471 * According to 10.2.5.11 of Intel 82574 Datasheet, 3472 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3473 * Only write to RXDCTL(1) if there is a need for different 3474 * settings. 3475 */ 3476 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3477 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3478 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3479 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3480 } else if (hw->mac.type == e1000_82574) { 3481 for (int i = 0; i < sc->rx_num_queues; i++) { 3482 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3483 rxdctl |= 0x20; /* PTHRESH */ 3484 rxdctl |= 4 << 8; /* HTHRESH */ 3485 rxdctl |= 4 << 16;/* WTHRESH */ 3486 rxdctl |= 1 << 24; /* Switch to granularity */ 3487 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3488 } 3489 } else if (hw->mac.type >= igb_mac_min) { 3490 u32 psize, srrctl = 0; 3491 3492 if (if_getmtu(ifp) > ETHERMTU) { 3493 psize = scctx->isc_max_frame_size; 3494 /* are we on a vlan? */ 3495 if (if_vlantrunkinuse(ifp)) 3496 psize += VLAN_TAG_SIZE; 3497 3498 if (sc->vf_ifp) 3499 e1000_rlpml_set_vf(hw, psize); 3500 else 3501 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3502 } 3503 3504 /* Set maximum packet buffer len */ 3505 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3506 E1000_SRRCTL_BSIZEPKT_SHIFT; 3507 3508 /* 3509 * If TX flow control is disabled and there's >1 queue defined, 3510 * enable DROP. 3511 * 3512 * This drops frames rather than hanging the RX MAC for all queues. 3513 */ 3514 if ((sc->rx_num_queues > 1) && 3515 (sc->fc == e1000_fc_none || 3516 sc->fc == e1000_fc_rx_pause)) { 3517 srrctl |= E1000_SRRCTL_DROP_EN; 3518 } 3519 /* Setup the Base and Length of the Rx Descriptor Rings */ 3520 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3521 struct rx_ring *rxr = &que->rxr; 3522 u64 bus_addr = rxr->rx_paddr; 3523 u32 rxdctl; 3524 3525 #ifdef notyet 3526 /* Configure for header split? -- ignore for now */ 3527 rxr->hdr_split = igb_header_split; 3528 #else 3529 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3530 #endif 3531 3532 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3533 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3534 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3535 (uint32_t)(bus_addr >> 32)); 3536 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3537 (uint32_t)bus_addr); 3538 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3539 /* Enable this Queue */ 3540 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3541 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3542 rxdctl &= 0xFFF00000; 3543 rxdctl |= IGB_RX_PTHRESH; 3544 rxdctl |= IGB_RX_HTHRESH << 8; 3545 rxdctl |= IGB_RX_WTHRESH << 16; 3546 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3547 } 3548 } else if (hw->mac.type >= e1000_pch2lan) { 3549 if (if_getmtu(ifp) > ETHERMTU) 3550 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3551 else 3552 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3553 } 3554 3555 /* Make sure VLAN Filters are off */ 3556 rctl &= ~E1000_RCTL_VFE; 3557 3558 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3559 if (hw->mac.type < igb_mac_min) { 3560 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3561 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3562 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3563 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3564 else if (sc->rx_mbuf_sz > 8192) 3565 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3566 else { 3567 rctl |= E1000_RCTL_SZ_2048; 3568 rctl &= ~E1000_RCTL_BSEX; 3569 } 3570 } else 3571 rctl |= E1000_RCTL_SZ_2048; 3572 3573 /* 3574 * rctl bits 11:10 are as follows 3575 * lem: reserved 3576 * em: DTYPE 3577 * igb: reserved 3578 * and should be 00 on all of the above 3579 */ 3580 rctl &= ~0x00000C00; 3581 3582 /* Write out the settings */ 3583 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3584 3585 return; 3586 } 3587 3588 static void 3589 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3590 { 3591 struct e1000_softc *sc = iflib_get_softc(ctx); 3592 u32 index, bit; 3593 3594 index = (vtag >> 5) & 0x7F; 3595 bit = vtag & 0x1F; 3596 sc->shadow_vfta[index] |= (1 << bit); 3597 ++sc->num_vlans; 3598 em_if_vlan_filter_write(sc); 3599 } 3600 3601 static void 3602 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3603 { 3604 struct e1000_softc *sc = iflib_get_softc(ctx); 3605 u32 index, bit; 3606 3607 index = (vtag >> 5) & 0x7F; 3608 bit = vtag & 0x1F; 3609 sc->shadow_vfta[index] &= ~(1 << bit); 3610 --sc->num_vlans; 3611 em_if_vlan_filter_write(sc); 3612 } 3613 3614 static bool 3615 em_if_vlan_filter_capable(if_ctx_t ctx) 3616 { 3617 if_t ifp = iflib_get_ifp(ctx); 3618 3619 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3620 !em_disable_crc_stripping) 3621 return (true); 3622 3623 return (false); 3624 } 3625 3626 static bool 3627 em_if_vlan_filter_used(if_ctx_t ctx) 3628 { 3629 struct e1000_softc *sc = iflib_get_softc(ctx); 3630 3631 if (!em_if_vlan_filter_capable(ctx)) 3632 return (false); 3633 3634 for (int i = 0; i < EM_VFTA_SIZE; i++) 3635 if (sc->shadow_vfta[i] != 0) 3636 return (true); 3637 3638 return (false); 3639 } 3640 3641 static void 3642 em_if_vlan_filter_enable(struct e1000_softc *sc) 3643 { 3644 struct e1000_hw *hw = &sc->hw; 3645 u32 reg; 3646 3647 reg = E1000_READ_REG(hw, E1000_RCTL); 3648 reg &= ~E1000_RCTL_CFIEN; 3649 reg |= E1000_RCTL_VFE; 3650 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3651 } 3652 3653 static void 3654 em_if_vlan_filter_disable(struct e1000_softc *sc) 3655 { 3656 struct e1000_hw *hw = &sc->hw; 3657 u32 reg; 3658 3659 reg = E1000_READ_REG(hw, E1000_RCTL); 3660 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3661 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3662 } 3663 3664 static void 3665 em_if_vlan_filter_write(struct e1000_softc *sc) 3666 { 3667 struct e1000_hw *hw = &sc->hw; 3668 3669 if (sc->vf_ifp) 3670 return; 3671 3672 /* Disable interrupts for lem-class devices during the filter change */ 3673 if (hw->mac.type < em_mac_min) 3674 em_if_intr_disable(sc->ctx); 3675 3676 for (int i = 0; i < EM_VFTA_SIZE; i++) 3677 if (sc->shadow_vfta[i] != 0) { 3678 /* XXXKB: incomplete VF support, we return early above */ 3679 if (sc->vf_ifp) 3680 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3681 else 3682 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3683 } 3684 3685 /* Re-enable interrupts for lem-class devices */ 3686 if (hw->mac.type < em_mac_min) 3687 em_if_intr_enable(sc->ctx); 3688 } 3689 3690 static void 3691 em_setup_vlan_hw_support(if_ctx_t ctx) 3692 { 3693 struct e1000_softc *sc = iflib_get_softc(ctx); 3694 struct e1000_hw *hw = &sc->hw; 3695 if_t ifp = iflib_get_ifp(ctx); 3696 u32 reg; 3697 3698 /* XXXKB: Return early if we are a VF until VF decap and filter management 3699 * is ready and tested. 3700 */ 3701 if (sc->vf_ifp) 3702 return; 3703 3704 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3705 !em_disable_crc_stripping) { 3706 reg = E1000_READ_REG(hw, E1000_CTRL); 3707 reg |= E1000_CTRL_VME; 3708 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3709 } else { 3710 reg = E1000_READ_REG(hw, E1000_CTRL); 3711 reg &= ~E1000_CTRL_VME; 3712 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3713 } 3714 3715 /* If we aren't doing HW filtering, we're done */ 3716 if (!em_if_vlan_filter_capable(ctx)) { 3717 em_if_vlan_filter_disable(sc); 3718 return; 3719 } 3720 3721 /* 3722 * A soft reset zero's out the VFTA, so 3723 * we need to repopulate it now. 3724 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3725 * traffic through. This will write the entire table. 3726 */ 3727 em_if_vlan_register(ctx, 0); 3728 3729 /* Enable the Filter Table */ 3730 em_if_vlan_filter_enable(sc); 3731 } 3732 3733 static void 3734 em_if_intr_enable(if_ctx_t ctx) 3735 { 3736 struct e1000_softc *sc = iflib_get_softc(ctx); 3737 struct e1000_hw *hw = &sc->hw; 3738 u32 ims_mask = IMS_ENABLE_MASK; 3739 3740 if (sc->intr_type == IFLIB_INTR_MSIX) { 3741 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3742 ims_mask |= sc->ims; 3743 } 3744 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3745 E1000_WRITE_FLUSH(hw); 3746 } 3747 3748 static void 3749 em_if_intr_disable(if_ctx_t ctx) 3750 { 3751 struct e1000_softc *sc = iflib_get_softc(ctx); 3752 struct e1000_hw *hw = &sc->hw; 3753 3754 if (sc->intr_type == IFLIB_INTR_MSIX) 3755 E1000_WRITE_REG(hw, EM_EIAC, 0); 3756 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3757 E1000_WRITE_FLUSH(hw); 3758 } 3759 3760 static void 3761 igb_if_intr_enable(if_ctx_t ctx) 3762 { 3763 struct e1000_softc *sc = iflib_get_softc(ctx); 3764 struct e1000_hw *hw = &sc->hw; 3765 u32 mask; 3766 3767 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3768 mask = (sc->que_mask | sc->link_mask); 3769 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3770 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3771 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3772 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3773 } else 3774 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3775 E1000_WRITE_FLUSH(hw); 3776 } 3777 3778 static void 3779 igb_if_intr_disable(if_ctx_t ctx) 3780 { 3781 struct e1000_softc *sc = iflib_get_softc(ctx); 3782 struct e1000_hw *hw = &sc->hw; 3783 3784 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3785 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3786 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3787 } 3788 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3789 E1000_WRITE_FLUSH(hw); 3790 } 3791 3792 /* 3793 * Bit of a misnomer, what this really means is 3794 * to enable OS management of the system... aka 3795 * to disable special hardware management features 3796 */ 3797 static void 3798 em_init_manageability(struct e1000_softc *sc) 3799 { 3800 /* A shared code workaround */ 3801 #define E1000_82542_MANC2H E1000_MANC2H 3802 if (sc->has_manage) { 3803 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3804 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3805 3806 /* disable hardware interception of ARP */ 3807 manc &= ~(E1000_MANC_ARP_EN); 3808 3809 /* enable receiving management packets to the host */ 3810 manc |= E1000_MANC_EN_MNG2HOST; 3811 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3812 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3813 manc2h |= E1000_MNG2HOST_PORT_623; 3814 manc2h |= E1000_MNG2HOST_PORT_664; 3815 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3816 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3817 } 3818 } 3819 3820 /* 3821 * Give control back to hardware management 3822 * controller if there is one. 3823 */ 3824 static void 3825 em_release_manageability(struct e1000_softc *sc) 3826 { 3827 if (sc->has_manage) { 3828 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3829 3830 /* re-enable hardware interception of ARP */ 3831 manc |= E1000_MANC_ARP_EN; 3832 manc &= ~E1000_MANC_EN_MNG2HOST; 3833 3834 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3835 } 3836 } 3837 3838 /* 3839 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3840 * For ASF and Pass Through versions of f/w this means 3841 * that the driver is loaded. For AMT version type f/w 3842 * this means that the network i/f is open. 3843 */ 3844 static void 3845 em_get_hw_control(struct e1000_softc *sc) 3846 { 3847 u32 ctrl_ext, swsm; 3848 3849 if (sc->vf_ifp) 3850 return; 3851 3852 if (sc->hw.mac.type == e1000_82573) { 3853 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3854 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3855 swsm | E1000_SWSM_DRV_LOAD); 3856 return; 3857 } 3858 /* else */ 3859 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3860 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3861 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3862 } 3863 3864 /* 3865 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3866 * For ASF and Pass Through versions of f/w this means that 3867 * the driver is no longer loaded. For AMT versions of the 3868 * f/w this means that the network i/f is closed. 3869 */ 3870 static void 3871 em_release_hw_control(struct e1000_softc *sc) 3872 { 3873 u32 ctrl_ext, swsm; 3874 3875 if (!sc->has_manage) 3876 return; 3877 3878 if (sc->hw.mac.type == e1000_82573) { 3879 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3880 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3881 swsm & ~E1000_SWSM_DRV_LOAD); 3882 return; 3883 } 3884 /* else */ 3885 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3886 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3887 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3888 return; 3889 } 3890 3891 static int 3892 em_is_valid_ether_addr(u8 *addr) 3893 { 3894 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3895 3896 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3897 return (false); 3898 } 3899 3900 return (true); 3901 } 3902 3903 static bool 3904 em_automask_tso(if_ctx_t ctx) 3905 { 3906 struct e1000_softc *sc = iflib_get_softc(ctx); 3907 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 3908 if_t ifp = iflib_get_ifp(ctx); 3909 3910 if (!em_unsupported_tso && sc->link_speed && 3911 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 3912 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 3913 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 3914 scctx->isc_capenable &= ~IFCAP_TSO; 3915 if_setcapenablebit(ifp, 0, IFCAP_TSO); 3916 /* iflib_init_locked handles ifnet hwassistbits */ 3917 iflib_request_reset(ctx); 3918 return true; 3919 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 3920 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 3921 scctx->isc_capenable |= sc->tso_automasked; 3922 if_setcapenablebit(ifp, sc->tso_automasked, 0); 3923 sc->tso_automasked = 0; 3924 /* iflib_init_locked handles ifnet hwassistbits */ 3925 iflib_request_reset(ctx); 3926 return true; 3927 } 3928 3929 return false; 3930 } 3931 3932 /* 3933 ** Parse the interface capabilities with regard 3934 ** to both system management and wake-on-lan for 3935 ** later use. 3936 */ 3937 static void 3938 em_get_wakeup(if_ctx_t ctx) 3939 { 3940 struct e1000_softc *sc = iflib_get_softc(ctx); 3941 device_t dev = iflib_get_dev(ctx); 3942 u16 eeprom_data = 0, device_id, apme_mask; 3943 3944 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3945 apme_mask = EM_EEPROM_APME; 3946 3947 switch (sc->hw.mac.type) { 3948 case e1000_82542: 3949 case e1000_82543: 3950 break; 3951 case e1000_82544: 3952 e1000_read_nvm(&sc->hw, 3953 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3954 apme_mask = EM_82544_APME; 3955 break; 3956 case e1000_82546: 3957 case e1000_82546_rev_3: 3958 if (sc->hw.bus.func == 1) { 3959 e1000_read_nvm(&sc->hw, 3960 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3961 break; 3962 } else 3963 e1000_read_nvm(&sc->hw, 3964 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3965 break; 3966 case e1000_82573: 3967 case e1000_82583: 3968 sc->has_amt = true; 3969 /* FALLTHROUGH */ 3970 case e1000_82571: 3971 case e1000_82572: 3972 case e1000_80003es2lan: 3973 if (sc->hw.bus.func == 1) { 3974 e1000_read_nvm(&sc->hw, 3975 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3976 break; 3977 } else 3978 e1000_read_nvm(&sc->hw, 3979 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3980 break; 3981 case e1000_ich8lan: 3982 case e1000_ich9lan: 3983 case e1000_ich10lan: 3984 case e1000_pchlan: 3985 case e1000_pch2lan: 3986 case e1000_pch_lpt: 3987 case e1000_pch_spt: 3988 case e1000_82575: /* listing all igb devices */ 3989 case e1000_82576: 3990 case e1000_82580: 3991 case e1000_i350: 3992 case e1000_i354: 3993 case e1000_i210: 3994 case e1000_i211: 3995 case e1000_vfadapt: 3996 case e1000_vfadapt_i350: 3997 apme_mask = E1000_WUC_APME; 3998 sc->has_amt = true; 3999 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4000 break; 4001 default: 4002 e1000_read_nvm(&sc->hw, 4003 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4004 break; 4005 } 4006 if (eeprom_data & apme_mask) 4007 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4008 /* 4009 * We have the eeprom settings, now apply the special cases 4010 * where the eeprom may be wrong or the board won't support 4011 * wake on lan on a particular port 4012 */ 4013 device_id = pci_get_device(dev); 4014 switch (device_id) { 4015 case E1000_DEV_ID_82546GB_PCIE: 4016 sc->wol = 0; 4017 break; 4018 case E1000_DEV_ID_82546EB_FIBER: 4019 case E1000_DEV_ID_82546GB_FIBER: 4020 /* Wake events only supported on port A for dual fiber 4021 * regardless of eeprom setting */ 4022 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4023 E1000_STATUS_FUNC_1) 4024 sc->wol = 0; 4025 break; 4026 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4027 /* if quad port adapter, disable WoL on all but port A */ 4028 if (global_quad_port_a != 0) 4029 sc->wol = 0; 4030 /* Reset for multiple quad port adapters */ 4031 if (++global_quad_port_a == 4) 4032 global_quad_port_a = 0; 4033 break; 4034 case E1000_DEV_ID_82571EB_FIBER: 4035 /* Wake events only supported on port A for dual fiber 4036 * regardless of eeprom setting */ 4037 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4038 E1000_STATUS_FUNC_1) 4039 sc->wol = 0; 4040 break; 4041 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4042 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4043 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4044 /* if quad port adapter, disable WoL on all but port A */ 4045 if (global_quad_port_a != 0) 4046 sc->wol = 0; 4047 /* Reset for multiple quad port adapters */ 4048 if (++global_quad_port_a == 4) 4049 global_quad_port_a = 0; 4050 break; 4051 } 4052 return; 4053 } 4054 4055 4056 /* 4057 * Enable PCI Wake On Lan capability 4058 */ 4059 static void 4060 em_enable_wakeup(if_ctx_t ctx) 4061 { 4062 struct e1000_softc *sc = iflib_get_softc(ctx); 4063 device_t dev = iflib_get_dev(ctx); 4064 if_t ifp = iflib_get_ifp(ctx); 4065 int error = 0; 4066 u32 pmc, ctrl, ctrl_ext, rctl; 4067 u16 status; 4068 4069 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4070 return; 4071 4072 /* 4073 * Determine type of Wakeup: note that wol 4074 * is set with all bits on by default. 4075 */ 4076 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4077 sc->wol &= ~E1000_WUFC_MAG; 4078 4079 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4080 sc->wol &= ~E1000_WUFC_EX; 4081 4082 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4083 sc->wol &= ~E1000_WUFC_MC; 4084 else { 4085 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4086 rctl |= E1000_RCTL_MPE; 4087 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4088 } 4089 4090 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4091 goto pme; 4092 4093 /* Advertise the wakeup capability */ 4094 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4095 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4096 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4097 4098 /* Keep the laser running on Fiber adapters */ 4099 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4100 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4101 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4102 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4103 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4104 } 4105 4106 if ((sc->hw.mac.type == e1000_ich8lan) || 4107 (sc->hw.mac.type == e1000_pchlan) || 4108 (sc->hw.mac.type == e1000_ich9lan) || 4109 (sc->hw.mac.type == e1000_ich10lan)) 4110 e1000_suspend_workarounds_ich8lan(&sc->hw); 4111 4112 if ( sc->hw.mac.type >= e1000_pchlan) { 4113 error = em_enable_phy_wakeup(sc); 4114 if (error) 4115 goto pme; 4116 } else { 4117 /* Enable wakeup by the MAC */ 4118 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4119 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4120 } 4121 4122 if (sc->hw.phy.type == e1000_phy_igp_3) 4123 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4124 4125 pme: 4126 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4127 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4128 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4129 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4130 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4131 4132 return; 4133 } 4134 4135 /* 4136 * WOL in the newer chipset interfaces (pchlan) 4137 * require thing to be copied into the phy 4138 */ 4139 static int 4140 em_enable_phy_wakeup(struct e1000_softc *sc) 4141 { 4142 struct e1000_hw *hw = &sc->hw; 4143 u32 mreg, ret = 0; 4144 u16 preg; 4145 4146 /* copy MAC RARs to PHY RARs */ 4147 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4148 4149 /* copy MAC MTA to PHY MTA */ 4150 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4151 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4152 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4153 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4154 (u16)((mreg >> 16) & 0xFFFF)); 4155 } 4156 4157 /* configure PHY Rx Control register */ 4158 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4159 mreg = E1000_READ_REG(hw, E1000_RCTL); 4160 if (mreg & E1000_RCTL_UPE) 4161 preg |= BM_RCTL_UPE; 4162 if (mreg & E1000_RCTL_MPE) 4163 preg |= BM_RCTL_MPE; 4164 preg &= ~(BM_RCTL_MO_MASK); 4165 if (mreg & E1000_RCTL_MO_3) 4166 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4167 << BM_RCTL_MO_SHIFT); 4168 if (mreg & E1000_RCTL_BAM) 4169 preg |= BM_RCTL_BAM; 4170 if (mreg & E1000_RCTL_PMCF) 4171 preg |= BM_RCTL_PMCF; 4172 mreg = E1000_READ_REG(hw, E1000_CTRL); 4173 if (mreg & E1000_CTRL_RFCE) 4174 preg |= BM_RCTL_RFCE; 4175 e1000_write_phy_reg(hw, BM_RCTL, preg); 4176 4177 /* enable PHY wakeup in MAC register */ 4178 E1000_WRITE_REG(hw, E1000_WUC, 4179 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4180 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4181 4182 /* configure and enable PHY wakeup in PHY registers */ 4183 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4184 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4185 4186 /* activate PHY wakeup */ 4187 ret = hw->phy.ops.acquire(hw); 4188 if (ret) { 4189 printf("Could not acquire PHY\n"); 4190 return ret; 4191 } 4192 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4193 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4194 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4195 if (ret) { 4196 printf("Could not read PHY page 769\n"); 4197 goto out; 4198 } 4199 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4200 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4201 if (ret) 4202 printf("Could not set PHY Host Wakeup bit\n"); 4203 out: 4204 hw->phy.ops.release(hw); 4205 4206 return ret; 4207 } 4208 4209 static void 4210 em_if_led_func(if_ctx_t ctx, int onoff) 4211 { 4212 struct e1000_softc *sc = iflib_get_softc(ctx); 4213 4214 if (onoff) { 4215 e1000_setup_led(&sc->hw); 4216 e1000_led_on(&sc->hw); 4217 } else { 4218 e1000_led_off(&sc->hw); 4219 e1000_cleanup_led(&sc->hw); 4220 } 4221 } 4222 4223 /* 4224 * Disable the L0S and L1 LINK states 4225 */ 4226 static void 4227 em_disable_aspm(struct e1000_softc *sc) 4228 { 4229 int base, reg; 4230 u16 link_cap,link_ctrl; 4231 device_t dev = sc->dev; 4232 4233 switch (sc->hw.mac.type) { 4234 case e1000_82573: 4235 case e1000_82574: 4236 case e1000_82583: 4237 break; 4238 default: 4239 return; 4240 } 4241 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4242 return; 4243 reg = base + PCIER_LINK_CAP; 4244 link_cap = pci_read_config(dev, reg, 2); 4245 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4246 return; 4247 reg = base + PCIER_LINK_CTL; 4248 link_ctrl = pci_read_config(dev, reg, 2); 4249 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4250 pci_write_config(dev, reg, link_ctrl, 2); 4251 return; 4252 } 4253 4254 /********************************************************************** 4255 * 4256 * Update the board statistics counters. 4257 * 4258 **********************************************************************/ 4259 static void 4260 em_update_stats_counters(struct e1000_softc *sc) 4261 { 4262 u64 prev_xoffrxc = sc->stats.xoffrxc; 4263 4264 if(sc->hw.phy.media_type == e1000_media_type_copper || 4265 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4266 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4267 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4268 } 4269 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4270 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4271 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4272 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4273 4274 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4275 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4276 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4277 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4278 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4279 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4280 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4281 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4282 /* 4283 ** For watchdog management we need to know if we have been 4284 ** paused during the last interval, so capture that here. 4285 */ 4286 if (sc->stats.xoffrxc != prev_xoffrxc) 4287 sc->shared->isc_pause_frames = 1; 4288 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4289 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4290 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4291 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4292 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4293 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4294 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4295 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4296 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4297 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4298 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4299 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4300 4301 /* For the 64-bit byte counters the low dword must be read first. */ 4302 /* Both registers clear on the read of the high dword */ 4303 4304 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4305 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4306 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4307 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4308 4309 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4310 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4311 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4312 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4313 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4314 4315 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4316 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4317 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4318 4319 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4320 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4321 4322 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4323 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4324 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4325 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4326 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4327 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4328 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4329 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4330 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4331 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4332 4333 /* Interrupt Counts */ 4334 4335 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4336 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4337 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4338 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4339 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4340 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4341 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4342 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4343 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4344 4345 if (sc->hw.mac.type >= e1000_82543) { 4346 sc->stats.algnerrc += 4347 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4348 sc->stats.rxerrc += 4349 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4350 sc->stats.tncrs += 4351 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4352 sc->stats.cexterr += 4353 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4354 sc->stats.tsctc += 4355 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4356 sc->stats.tsctfc += 4357 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4358 } 4359 } 4360 4361 static uint64_t 4362 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4363 { 4364 struct e1000_softc *sc = iflib_get_softc(ctx); 4365 if_t ifp = iflib_get_ifp(ctx); 4366 4367 switch (cnt) { 4368 case IFCOUNTER_COLLISIONS: 4369 return (sc->stats.colc); 4370 case IFCOUNTER_IERRORS: 4371 return (sc->dropped_pkts + sc->stats.rxerrc + 4372 sc->stats.crcerrs + sc->stats.algnerrc + 4373 sc->stats.ruc + sc->stats.roc + 4374 sc->stats.mpc + sc->stats.cexterr); 4375 case IFCOUNTER_OERRORS: 4376 return (sc->stats.ecol + sc->stats.latecol + 4377 sc->watchdog_events); 4378 default: 4379 return (if_get_counter_default(ifp, cnt)); 4380 } 4381 } 4382 4383 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4384 * @ctx: iflib context 4385 * @event: event code to check 4386 * 4387 * Defaults to returning false for unknown events. 4388 * 4389 * @returns true if iflib needs to reinit the interface 4390 */ 4391 static bool 4392 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4393 { 4394 switch (event) { 4395 case IFLIB_RESTART_VLAN_CONFIG: 4396 default: 4397 return (false); 4398 } 4399 } 4400 4401 /* Export a single 32-bit register via a read-only sysctl. */ 4402 static int 4403 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4404 { 4405 struct e1000_softc *sc; 4406 u_int val; 4407 4408 sc = oidp->oid_arg1; 4409 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4410 return (sysctl_handle_int(oidp, &val, 0, req)); 4411 } 4412 4413 /* 4414 * Add sysctl variables, one per statistic, to the system. 4415 */ 4416 static void 4417 em_add_hw_stats(struct e1000_softc *sc) 4418 { 4419 device_t dev = iflib_get_dev(sc->ctx); 4420 struct em_tx_queue *tx_que = sc->tx_queues; 4421 struct em_rx_queue *rx_que = sc->rx_queues; 4422 4423 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4424 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4425 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4426 struct e1000_hw_stats *stats = &sc->stats; 4427 4428 struct sysctl_oid *stat_node, *queue_node, *int_node; 4429 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4430 4431 #define QUEUE_NAME_LEN 32 4432 char namebuf[QUEUE_NAME_LEN]; 4433 4434 /* Driver Statistics */ 4435 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4436 CTLFLAG_RD, &sc->dropped_pkts, 4437 "Driver dropped packets"); 4438 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4439 CTLFLAG_RD, &sc->link_irq, 4440 "Link MSI-X IRQ Handled"); 4441 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4442 CTLFLAG_RD, &sc->rx_overruns, 4443 "RX overruns"); 4444 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4445 CTLFLAG_RD, &sc->watchdog_events, 4446 "Watchdog timeouts"); 4447 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4448 CTLTYPE_UINT | CTLFLAG_RD, 4449 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4450 "Device Control Register"); 4451 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4452 CTLTYPE_UINT | CTLFLAG_RD, 4453 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4454 "Receiver Control Register"); 4455 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4456 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4457 "Flow Control High Watermark"); 4458 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4459 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4460 "Flow Control Low Watermark"); 4461 4462 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4463 struct tx_ring *txr = &tx_que->txr; 4464 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4465 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4466 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4467 queue_list = SYSCTL_CHILDREN(queue_node); 4468 4469 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4470 CTLTYPE_UINT | CTLFLAG_RD, sc, 4471 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4472 "Transmit Descriptor Head"); 4473 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4474 CTLTYPE_UINT | CTLFLAG_RD, sc, 4475 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4476 "Transmit Descriptor Tail"); 4477 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4478 CTLFLAG_RD, &txr->tx_irq, 4479 "Queue MSI-X Transmit Interrupts"); 4480 } 4481 4482 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4483 struct rx_ring *rxr = &rx_que->rxr; 4484 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4485 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4486 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4487 queue_list = SYSCTL_CHILDREN(queue_node); 4488 4489 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4490 CTLTYPE_UINT | CTLFLAG_RD, sc, 4491 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4492 "Receive Descriptor Head"); 4493 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4494 CTLTYPE_UINT | CTLFLAG_RD, sc, 4495 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4496 "Receive Descriptor Tail"); 4497 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4498 CTLFLAG_RD, &rxr->rx_irq, 4499 "Queue MSI-X Receive Interrupts"); 4500 } 4501 4502 /* MAC stats get their own sub node */ 4503 4504 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4505 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4506 stat_list = SYSCTL_CHILDREN(stat_node); 4507 4508 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4509 CTLFLAG_RD, &stats->ecol, 4510 "Excessive collisions"); 4511 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4512 CTLFLAG_RD, &stats->scc, 4513 "Single collisions"); 4514 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4515 CTLFLAG_RD, &stats->mcc, 4516 "Multiple collisions"); 4517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4518 CTLFLAG_RD, &stats->latecol, 4519 "Late collisions"); 4520 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4521 CTLFLAG_RD, &stats->colc, 4522 "Collision Count"); 4523 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4524 CTLFLAG_RD, &sc->stats.symerrs, 4525 "Symbol Errors"); 4526 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4527 CTLFLAG_RD, &sc->stats.sec, 4528 "Sequence Errors"); 4529 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4530 CTLFLAG_RD, &sc->stats.dc, 4531 "Defer Count"); 4532 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4533 CTLFLAG_RD, &sc->stats.mpc, 4534 "Missed Packets"); 4535 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 4536 CTLFLAG_RD, &sc->stats.rlec, 4537 "Receive Length Errors"); 4538 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4539 CTLFLAG_RD, &sc->stats.rnbc, 4540 "Receive No Buffers"); 4541 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4542 CTLFLAG_RD, &sc->stats.ruc, 4543 "Receive Undersize"); 4544 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4545 CTLFLAG_RD, &sc->stats.rfc, 4546 "Fragmented Packets Received "); 4547 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4548 CTLFLAG_RD, &sc->stats.roc, 4549 "Oversized Packets Received"); 4550 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4551 CTLFLAG_RD, &sc->stats.rjc, 4552 "Recevied Jabber"); 4553 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4554 CTLFLAG_RD, &sc->stats.rxerrc, 4555 "Receive Errors"); 4556 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4557 CTLFLAG_RD, &sc->stats.crcerrs, 4558 "CRC errors"); 4559 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4560 CTLFLAG_RD, &sc->stats.algnerrc, 4561 "Alignment Errors"); 4562 /* On 82575 these are collision counts */ 4563 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4564 CTLFLAG_RD, &sc->stats.cexterr, 4565 "Collision/Carrier extension errors"); 4566 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4567 CTLFLAG_RD, &sc->stats.xonrxc, 4568 "XON Received"); 4569 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4570 CTLFLAG_RD, &sc->stats.xontxc, 4571 "XON Transmitted"); 4572 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4573 CTLFLAG_RD, &sc->stats.xoffrxc, 4574 "XOFF Received"); 4575 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4576 CTLFLAG_RD, &sc->stats.xofftxc, 4577 "XOFF Transmitted"); 4578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 4579 CTLFLAG_RD, &sc->stats.fcruc, 4580 "Unsupported Flow Control Received"); 4581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 4582 CTLFLAG_RD, &sc->stats.mgprc, 4583 "Management Packets Received"); 4584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 4585 CTLFLAG_RD, &sc->stats.mgpdc, 4586 "Management Packets Dropped"); 4587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 4588 CTLFLAG_RD, &sc->stats.mgptc, 4589 "Management Packets Transmitted"); 4590 4591 /* Packet Reception Stats */ 4592 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4593 CTLFLAG_RD, &sc->stats.tpr, 4594 "Total Packets Received "); 4595 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4596 CTLFLAG_RD, &sc->stats.gprc, 4597 "Good Packets Received"); 4598 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4599 CTLFLAG_RD, &sc->stats.bprc, 4600 "Broadcast Packets Received"); 4601 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4602 CTLFLAG_RD, &sc->stats.mprc, 4603 "Multicast Packets Received"); 4604 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4605 CTLFLAG_RD, &sc->stats.prc64, 4606 "64 byte frames received "); 4607 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4608 CTLFLAG_RD, &sc->stats.prc127, 4609 "65-127 byte frames received"); 4610 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4611 CTLFLAG_RD, &sc->stats.prc255, 4612 "128-255 byte frames received"); 4613 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4614 CTLFLAG_RD, &sc->stats.prc511, 4615 "256-511 byte frames received"); 4616 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4617 CTLFLAG_RD, &sc->stats.prc1023, 4618 "512-1023 byte frames received"); 4619 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4620 CTLFLAG_RD, &sc->stats.prc1522, 4621 "1023-1522 byte frames received"); 4622 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4623 CTLFLAG_RD, &sc->stats.gorc, 4624 "Good Octets Received"); 4625 4626 /* Packet Transmission Stats */ 4627 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4628 CTLFLAG_RD, &sc->stats.gotc, 4629 "Good Octets Transmitted"); 4630 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4631 CTLFLAG_RD, &sc->stats.tpt, 4632 "Total Packets Transmitted"); 4633 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4634 CTLFLAG_RD, &sc->stats.gptc, 4635 "Good Packets Transmitted"); 4636 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4637 CTLFLAG_RD, &sc->stats.bptc, 4638 "Broadcast Packets Transmitted"); 4639 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4640 CTLFLAG_RD, &sc->stats.mptc, 4641 "Multicast Packets Transmitted"); 4642 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4643 CTLFLAG_RD, &sc->stats.ptc64, 4644 "64 byte frames transmitted "); 4645 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4646 CTLFLAG_RD, &sc->stats.ptc127, 4647 "65-127 byte frames transmitted"); 4648 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4649 CTLFLAG_RD, &sc->stats.ptc255, 4650 "128-255 byte frames transmitted"); 4651 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4652 CTLFLAG_RD, &sc->stats.ptc511, 4653 "256-511 byte frames transmitted"); 4654 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4655 CTLFLAG_RD, &sc->stats.ptc1023, 4656 "512-1023 byte frames transmitted"); 4657 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4658 CTLFLAG_RD, &sc->stats.ptc1522, 4659 "1024-1522 byte frames transmitted"); 4660 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4661 CTLFLAG_RD, &sc->stats.tsctc, 4662 "TSO Contexts Transmitted"); 4663 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4664 CTLFLAG_RD, &sc->stats.tsctfc, 4665 "TSO Contexts Failed"); 4666 4667 4668 /* Interrupt Stats */ 4669 4670 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4671 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4672 int_list = SYSCTL_CHILDREN(int_node); 4673 4674 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4675 CTLFLAG_RD, &sc->stats.iac, 4676 "Interrupt Assertion Count"); 4677 4678 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4679 CTLFLAG_RD, &sc->stats.icrxptc, 4680 "Interrupt Cause Rx Pkt Timer Expire Count"); 4681 4682 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4683 CTLFLAG_RD, &sc->stats.icrxatc, 4684 "Interrupt Cause Rx Abs Timer Expire Count"); 4685 4686 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4687 CTLFLAG_RD, &sc->stats.ictxptc, 4688 "Interrupt Cause Tx Pkt Timer Expire Count"); 4689 4690 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4691 CTLFLAG_RD, &sc->stats.ictxatc, 4692 "Interrupt Cause Tx Abs Timer Expire Count"); 4693 4694 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4695 CTLFLAG_RD, &sc->stats.ictxqec, 4696 "Interrupt Cause Tx Queue Empty Count"); 4697 4698 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4699 CTLFLAG_RD, &sc->stats.ictxqmtc, 4700 "Interrupt Cause Tx Queue Min Thresh Count"); 4701 4702 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4703 CTLFLAG_RD, &sc->stats.icrxdmtc, 4704 "Interrupt Cause Rx Desc Min Thresh Count"); 4705 4706 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4707 CTLFLAG_RD, &sc->stats.icrxoc, 4708 "Interrupt Cause Receiver Overrun Count"); 4709 } 4710 4711 static void 4712 em_fw_version_locked(if_ctx_t ctx) 4713 { 4714 struct e1000_softc *sc = iflib_get_softc(ctx); 4715 struct e1000_hw *hw = &sc->hw; 4716 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4717 uint16_t eep = 0; 4718 4719 /* 4720 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4721 * NVM locking model, so we do it in em_if_attach_pre() and store the 4722 * info in the softc 4723 */ 4724 ASSERT_CTX_LOCK_HELD(hw); 4725 4726 *fw_ver = (struct e1000_fw_version){0}; 4727 4728 if (hw->mac.type >= igb_mac_min) { 4729 /* 4730 * Use the Shared Code for igb(4) 4731 */ 4732 e1000_get_fw_version(hw, fw_ver); 4733 } else { 4734 /* 4735 * Otherwise, EEPROM version should be present on (almost?) all 4736 * devices here 4737 */ 4738 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4739 INIT_DEBUGOUT("can't get EEPROM version"); 4740 return; 4741 } 4742 4743 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4744 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4745 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4746 } 4747 } 4748 4749 static void 4750 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4751 { 4752 const char *space = ""; 4753 4754 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4755 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4756 fw_ver->eep_minor, fw_ver->eep_build); 4757 space = " "; 4758 } 4759 4760 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4761 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4762 space, fw_ver->invm_major, fw_ver->invm_minor, 4763 fw_ver->invm_img_type); 4764 space = " "; 4765 } 4766 4767 if (fw_ver->or_valid) { 4768 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4769 space, fw_ver->or_major, fw_ver->or_build, 4770 fw_ver->or_patch); 4771 space = " "; 4772 } 4773 4774 if (fw_ver->etrack_id) 4775 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4776 } 4777 4778 static void 4779 em_print_fw_version(struct e1000_softc *sc ) 4780 { 4781 device_t dev = sc->dev; 4782 struct sbuf *buf; 4783 int error = 0; 4784 4785 buf = sbuf_new_auto(); 4786 if (!buf) { 4787 device_printf(dev, "Could not allocate sbuf for output.\n"); 4788 return; 4789 } 4790 4791 em_sbuf_fw_version(&sc->fw_ver, buf); 4792 4793 error = sbuf_finish(buf); 4794 if (error) 4795 device_printf(dev, "Error finishing sbuf: %d\n", error); 4796 else if (sbuf_len(buf)) 4797 device_printf(dev, "%s\n", sbuf_data(buf)); 4798 4799 sbuf_delete(buf); 4800 } 4801 4802 static int 4803 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4804 { 4805 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4806 device_t dev = sc->dev; 4807 struct sbuf *buf; 4808 int error = 0; 4809 4810 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4811 if (!buf) { 4812 device_printf(dev, "Could not allocate sbuf for output.\n"); 4813 return (ENOMEM); 4814 } 4815 4816 em_sbuf_fw_version(&sc->fw_ver, buf); 4817 4818 error = sbuf_finish(buf); 4819 if (error) 4820 device_printf(dev, "Error finishing sbuf: %d\n", error); 4821 4822 sbuf_delete(buf); 4823 4824 return (0); 4825 } 4826 4827 /********************************************************************** 4828 * 4829 * This routine provides a way to dump out the adapter eeprom, 4830 * often a useful debug/service tool. This only dumps the first 4831 * 32 words, stuff that matters is in that extent. 4832 * 4833 **********************************************************************/ 4834 static int 4835 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4836 { 4837 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4838 int error; 4839 int result; 4840 4841 result = -1; 4842 error = sysctl_handle_int(oidp, &result, 0, req); 4843 4844 if (error || !req->newptr) 4845 return (error); 4846 4847 /* 4848 * This value will cause a hex dump of the 4849 * first 32 16-bit words of the EEPROM to 4850 * the screen. 4851 */ 4852 if (result == 1) 4853 em_print_nvm_info(sc); 4854 4855 return (error); 4856 } 4857 4858 static void 4859 em_print_nvm_info(struct e1000_softc *sc) 4860 { 4861 struct e1000_hw *hw = &sc->hw; 4862 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4863 u16 eeprom_data; 4864 int i, j, row = 0; 4865 4866 /* Its a bit crude, but it gets the job done */ 4867 printf("\nInterface EEPROM Dump:\n"); 4868 printf("Offset\n0x0000 "); 4869 4870 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4871 sx_xlock(iflib_ctx_lock); 4872 ASSERT_CTX_LOCK_HELD(hw); 4873 for (i = 0, j = 0; i < 32; i++, j++) { 4874 if (j == 8) { /* Make the offset block */ 4875 j = 0; ++row; 4876 printf("\n0x00%x0 ",row); 4877 } 4878 e1000_read_nvm(hw, i, 1, &eeprom_data); 4879 printf("%04x ", eeprom_data); 4880 } 4881 sx_xunlock(iflib_ctx_lock); 4882 printf("\n"); 4883 } 4884 4885 static int 4886 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4887 { 4888 struct em_int_delay_info *info; 4889 struct e1000_softc *sc; 4890 u32 regval; 4891 int error, usecs, ticks; 4892 4893 info = (struct em_int_delay_info *) arg1; 4894 usecs = info->value; 4895 error = sysctl_handle_int(oidp, &usecs, 0, req); 4896 if (error != 0 || req->newptr == NULL) 4897 return (error); 4898 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4899 return (EINVAL); 4900 info->value = usecs; 4901 ticks = EM_USECS_TO_TICKS(usecs); 4902 if (info->offset == E1000_ITR) /* units are 256ns here */ 4903 ticks *= 4; 4904 4905 sc = info->sc; 4906 4907 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4908 regval = (regval & ~0xffff) | (ticks & 0xffff); 4909 /* Handle a few special cases. */ 4910 switch (info->offset) { 4911 case E1000_RDTR: 4912 break; 4913 case E1000_TIDV: 4914 if (ticks == 0) { 4915 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4916 /* Don't write 0 into the TIDV register. */ 4917 regval++; 4918 } else 4919 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4920 break; 4921 } 4922 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4923 return (0); 4924 } 4925 4926 static void 4927 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4928 const char *description, struct em_int_delay_info *info, 4929 int offset, int value) 4930 { 4931 info->sc = sc; 4932 info->offset = offset; 4933 info->value = value; 4934 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4935 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4936 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4937 info, 0, em_sysctl_int_delay, "I", description); 4938 } 4939 4940 /* 4941 * Set flow control using sysctl: 4942 * Flow control values: 4943 * 0 - off 4944 * 1 - rx pause 4945 * 2 - tx pause 4946 * 3 - full 4947 */ 4948 static int 4949 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4950 { 4951 int error; 4952 static int input = 3; /* default is full */ 4953 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4954 4955 error = sysctl_handle_int(oidp, &input, 0, req); 4956 4957 if ((error) || (req->newptr == NULL)) 4958 return (error); 4959 4960 if (input == sc->fc) /* no change? */ 4961 return (error); 4962 4963 switch (input) { 4964 case e1000_fc_rx_pause: 4965 case e1000_fc_tx_pause: 4966 case e1000_fc_full: 4967 case e1000_fc_none: 4968 sc->hw.fc.requested_mode = input; 4969 sc->fc = input; 4970 break; 4971 default: 4972 /* Do nothing */ 4973 return (error); 4974 } 4975 4976 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4977 e1000_force_mac_fc(&sc->hw); 4978 return (error); 4979 } 4980 4981 /* 4982 * Manage DMA Coalesce: 4983 * Control values: 4984 * 0/1 - off/on 4985 * Legal timer values are: 4986 * 250,500,1000-10000 in thousands 4987 */ 4988 static int 4989 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 4990 { 4991 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4992 int error; 4993 4994 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 4995 4996 if ((error) || (req->newptr == NULL)) 4997 return (error); 4998 4999 switch (sc->dmac) { 5000 case 0: 5001 /* Disabling */ 5002 break; 5003 case 1: /* Just enable and use default */ 5004 sc->dmac = 1000; 5005 break; 5006 case 250: 5007 case 500: 5008 case 1000: 5009 case 2000: 5010 case 3000: 5011 case 4000: 5012 case 5000: 5013 case 6000: 5014 case 7000: 5015 case 8000: 5016 case 9000: 5017 case 10000: 5018 /* Legal values - allow */ 5019 break; 5020 default: 5021 /* Do nothing, illegal value */ 5022 sc->dmac = 0; 5023 return (EINVAL); 5024 } 5025 /* Reinit the interface */ 5026 em_if_init(sc->ctx); 5027 return (error); 5028 } 5029 5030 /* 5031 * Manage Energy Efficient Ethernet: 5032 * Control values: 5033 * 0/1 - enabled/disabled 5034 */ 5035 static int 5036 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5037 { 5038 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5039 int error, value; 5040 5041 if (sc->hw.mac.type < igb_mac_min) 5042 value = sc->hw.dev_spec.ich8lan.eee_disable; 5043 else 5044 value = sc->hw.dev_spec._82575.eee_disable; 5045 error = sysctl_handle_int(oidp, &value, 0, req); 5046 if (error || req->newptr == NULL) 5047 return (error); 5048 if (sc->hw.mac.type < igb_mac_min) 5049 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5050 else 5051 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5052 em_if_init(sc->ctx); 5053 5054 return (0); 5055 } 5056 5057 static int 5058 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5059 { 5060 struct e1000_softc *sc; 5061 int error; 5062 int result; 5063 5064 result = -1; 5065 error = sysctl_handle_int(oidp, &result, 0, req); 5066 5067 if (error || !req->newptr) 5068 return (error); 5069 5070 if (result == 1) { 5071 sc = (struct e1000_softc *) arg1; 5072 em_print_debug_info(sc); 5073 } 5074 5075 return (error); 5076 } 5077 5078 static int 5079 em_get_rs(SYSCTL_HANDLER_ARGS) 5080 { 5081 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5082 int error; 5083 int result; 5084 5085 result = 0; 5086 error = sysctl_handle_int(oidp, &result, 0, req); 5087 5088 if (error || !req->newptr || result != 1) 5089 return (error); 5090 em_dump_rs(sc); 5091 5092 return (error); 5093 } 5094 5095 static void 5096 em_if_debug(if_ctx_t ctx) 5097 { 5098 em_dump_rs(iflib_get_softc(ctx)); 5099 } 5100 5101 /* 5102 * This routine is meant to be fluid, add whatever is 5103 * needed for debugging a problem. -jfv 5104 */ 5105 static void 5106 em_print_debug_info(struct e1000_softc *sc) 5107 { 5108 device_t dev = iflib_get_dev(sc->ctx); 5109 if_t ifp = iflib_get_ifp(sc->ctx); 5110 struct tx_ring *txr = &sc->tx_queues->txr; 5111 struct rx_ring *rxr = &sc->rx_queues->rxr; 5112 5113 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5114 printf("Interface is RUNNING "); 5115 else 5116 printf("Interface is NOT RUNNING\n"); 5117 5118 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5119 printf("and INACTIVE\n"); 5120 else 5121 printf("and ACTIVE\n"); 5122 5123 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5124 device_printf(dev, "TX Queue %d ------\n", i); 5125 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5126 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5127 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5128 5129 } 5130 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5131 device_printf(dev, "RX Queue %d ------\n", j); 5132 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5133 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5134 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5135 } 5136 } 5137 5138 /* 5139 * 82574 only: 5140 * Write a new value to the EEPROM increasing the number of MSI-X 5141 * vectors from 3 to 5, for proper multiqueue support. 5142 */ 5143 static void 5144 em_enable_vectors_82574(if_ctx_t ctx) 5145 { 5146 struct e1000_softc *sc = iflib_get_softc(ctx); 5147 struct e1000_hw *hw = &sc->hw; 5148 device_t dev = iflib_get_dev(ctx); 5149 u16 edata; 5150 5151 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5152 if (bootverbose) 5153 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5154 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5155 device_printf(dev, "Writing to eeprom: increasing " 5156 "reported MSI-X vectors from 3 to 5...\n"); 5157 edata &= ~(EM_NVM_MSIX_N_MASK); 5158 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5159 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5160 e1000_update_nvm_checksum(hw); 5161 device_printf(dev, "Writing to eeprom: done\n"); 5162 } 5163 } 5164