1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 /* required last entry */ 178 PVID_END 179 }; 180 181 static pci_vendor_info_t igb_vendor_info_array[] = 182 { 183 /* Intel(R) PRO/1000 Network Connection - igb */ 184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 /* required last entry */ 224 PVID_END 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 static void *em_register(device_t dev); 231 static void *igb_register(device_t dev); 232 static int em_if_attach_pre(if_ctx_t ctx); 233 static int em_if_attach_post(if_ctx_t ctx); 234 static int em_if_detach(if_ctx_t ctx); 235 static int em_if_shutdown(if_ctx_t ctx); 236 static int em_if_suspend(if_ctx_t ctx); 237 static int em_if_resume(if_ctx_t ctx); 238 239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 241 static void em_if_queues_free(if_ctx_t ctx); 242 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 244 static void em_if_init(if_ctx_t ctx); 245 static void em_if_stop(if_ctx_t ctx); 246 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 247 static int em_if_media_change(if_ctx_t ctx); 248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 249 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 252 253 static void em_identify_hardware(if_ctx_t ctx); 254 static int em_allocate_pci_resources(if_ctx_t ctx); 255 static void em_free_pci_resources(if_ctx_t ctx); 256 static void em_reset(if_ctx_t ctx); 257 static int em_setup_interface(if_ctx_t ctx); 258 static int em_setup_msix(if_ctx_t ctx); 259 260 static void em_initialize_transmit_unit(if_ctx_t ctx); 261 static void em_initialize_receive_unit(if_ctx_t ctx); 262 263 static void em_if_enable_intr(if_ctx_t ctx); 264 static void em_if_disable_intr(if_ctx_t ctx); 265 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 266 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 267 static void em_if_multi_set(if_ctx_t ctx); 268 static void em_if_update_admin_status(if_ctx_t ctx); 269 static void em_if_debug(if_ctx_t ctx); 270 static void em_update_stats_counters(struct adapter *); 271 static void em_add_hw_stats(struct adapter *adapter); 272 static int em_if_set_promisc(if_ctx_t ctx, int flags); 273 static void em_setup_vlan_hw_support(struct adapter *); 274 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 275 static void em_print_nvm_info(struct adapter *); 276 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 277 static int em_get_rs(SYSCTL_HANDLER_ARGS); 278 static void em_print_debug_info(struct adapter *); 279 static int em_is_valid_ether_addr(u8 *); 280 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 281 static void em_add_int_delay_sysctl(struct adapter *, const char *, 282 const char *, struct em_int_delay_info *, int, int); 283 /* Management and WOL Support */ 284 static void em_init_manageability(struct adapter *); 285 static void em_release_manageability(struct adapter *); 286 static void em_get_hw_control(struct adapter *); 287 static void em_release_hw_control(struct adapter *); 288 static void em_get_wakeup(if_ctx_t ctx); 289 static void em_enable_wakeup(if_ctx_t ctx); 290 static int em_enable_phy_wakeup(struct adapter *); 291 static void em_disable_aspm(struct adapter *); 292 293 int em_intr(void *arg); 294 static void em_disable_promisc(if_ctx_t ctx); 295 296 /* MSIX handlers */ 297 static int em_if_msix_intr_assign(if_ctx_t, int); 298 static int em_msix_link(void *); 299 static void em_handle_link(void *context); 300 301 static void em_enable_vectors_82574(if_ctx_t); 302 303 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 304 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 305 static void em_if_led_func(if_ctx_t ctx, int onoff); 306 307 static int em_get_regs(SYSCTL_HANDLER_ARGS); 308 309 static void lem_smartspeed(struct adapter *adapter); 310 static void igb_configure_queues(struct adapter *adapter); 311 312 313 /********************************************************************* 314 * FreeBSD Device Interface Entry Points 315 *********************************************************************/ 316 static device_method_t em_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_register, em_register), 319 DEVMETHOD(device_probe, iflib_device_probe), 320 DEVMETHOD(device_attach, iflib_device_attach), 321 DEVMETHOD(device_detach, iflib_device_detach), 322 DEVMETHOD(device_shutdown, iflib_device_shutdown), 323 DEVMETHOD(device_suspend, iflib_device_suspend), 324 DEVMETHOD(device_resume, iflib_device_resume), 325 DEVMETHOD_END 326 }; 327 328 static device_method_t igb_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, igb_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 341 static driver_t em_driver = { 342 "em", em_methods, sizeof(struct adapter), 343 }; 344 345 static devclass_t em_devclass; 346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 347 348 MODULE_DEPEND(em, pci, 1, 1, 1); 349 MODULE_DEPEND(em, ether, 1, 1, 1); 350 MODULE_DEPEND(em, iflib, 1, 1, 1); 351 352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 353 354 static driver_t igb_driver = { 355 "igb", igb_methods, sizeof(struct adapter), 356 }; 357 358 static devclass_t igb_devclass; 359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 360 361 MODULE_DEPEND(igb, pci, 1, 1, 1); 362 MODULE_DEPEND(igb, ether, 1, 1, 1); 363 MODULE_DEPEND(igb, iflib, 1, 1, 1); 364 365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 366 367 static device_method_t em_if_methods[] = { 368 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 369 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 370 DEVMETHOD(ifdi_detach, em_if_detach), 371 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 372 DEVMETHOD(ifdi_suspend, em_if_suspend), 373 DEVMETHOD(ifdi_resume, em_if_resume), 374 DEVMETHOD(ifdi_init, em_if_init), 375 DEVMETHOD(ifdi_stop, em_if_stop), 376 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 377 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 378 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 379 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 380 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 381 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 382 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 383 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 384 DEVMETHOD(ifdi_media_status, em_if_media_status), 385 DEVMETHOD(ifdi_media_change, em_if_media_change), 386 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 387 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 388 DEVMETHOD(ifdi_timer, em_if_timer), 389 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 390 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 391 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 392 DEVMETHOD(ifdi_led_func, em_if_led_func), 393 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 394 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 395 DEVMETHOD(ifdi_debug, em_if_debug), 396 DEVMETHOD_END 397 }; 398 399 /* 400 * note that if (adapter->msix_mem) is replaced by: 401 * if (adapter->intr_type == IFLIB_INTR_MSIX) 402 */ 403 static driver_t em_if_driver = { 404 "em_if", em_if_methods, sizeof(struct adapter) 405 }; 406 407 /********************************************************************* 408 * Tunable default values. 409 *********************************************************************/ 410 411 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 412 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 413 #define M_TSO_LEN 66 414 415 #define MAX_INTS_PER_SEC 8000 416 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 417 418 /* Allow common code without TSO */ 419 #ifndef CSUM_TSO 420 #define CSUM_TSO 0 421 #endif 422 423 #define TSO_WORKAROUND 4 424 425 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 426 427 static int em_disable_crc_stripping = 0; 428 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 429 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 430 431 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 432 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 433 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 434 0, "Default transmit interrupt delay in usecs"); 435 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 436 0, "Default receive interrupt delay in usecs"); 437 438 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 439 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 440 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 441 &em_tx_abs_int_delay_dflt, 0, 442 "Default transmit interrupt delay limit in usecs"); 443 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 444 &em_rx_abs_int_delay_dflt, 0, 445 "Default receive interrupt delay limit in usecs"); 446 447 static int em_smart_pwr_down = FALSE; 448 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 449 0, "Set to true to leave smart power down enabled on newer adapters"); 450 451 /* Controls whether promiscuous also shows bad packets */ 452 static int em_debug_sbp = TRUE; 453 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 454 "Show bad packets in promiscuous mode"); 455 456 /* How many packets rxeof tries to clean at a time */ 457 static int em_rx_process_limit = 100; 458 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 459 &em_rx_process_limit, 0, 460 "Maximum number of received packets to process " 461 "at a time, -1 means unlimited"); 462 463 /* Energy efficient ethernet - default to OFF */ 464 static int eee_setting = 1; 465 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 466 "Enable Energy Efficient Ethernet"); 467 468 /* 469 ** Tuneable Interrupt rate 470 */ 471 static int em_max_interrupt_rate = 8000; 472 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 473 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 474 475 476 477 /* Global used in WOL setup with multiport cards */ 478 static int global_quad_port_a = 0; 479 480 extern struct if_txrx igb_txrx; 481 extern struct if_txrx em_txrx; 482 extern struct if_txrx lem_txrx; 483 484 static struct if_shared_ctx em_sctx_init = { 485 .isc_magic = IFLIB_MAGIC, 486 .isc_q_align = PAGE_SIZE, 487 .isc_tx_maxsize = EM_TSO_SIZE, 488 .isc_tx_maxsegsize = PAGE_SIZE, 489 .isc_rx_maxsize = MJUM9BYTES, 490 .isc_rx_nsegments = 1, 491 .isc_rx_maxsegsize = MJUM9BYTES, 492 .isc_nfl = 1, 493 .isc_nrxqs = 1, 494 .isc_ntxqs = 1, 495 .isc_admin_intrcnt = 1, 496 .isc_vendor_info = em_vendor_info_array, 497 .isc_driver_version = em_driver_version, 498 .isc_driver = &em_if_driver, 499 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 500 501 .isc_nrxd_min = {EM_MIN_RXD}, 502 .isc_ntxd_min = {EM_MIN_TXD}, 503 .isc_nrxd_max = {EM_MAX_RXD}, 504 .isc_ntxd_max = {EM_MAX_TXD}, 505 .isc_nrxd_default = {EM_DEFAULT_RXD}, 506 .isc_ntxd_default = {EM_DEFAULT_TXD}, 507 }; 508 509 if_shared_ctx_t em_sctx = &em_sctx_init; 510 511 512 static struct if_shared_ctx igb_sctx_init = { 513 .isc_magic = IFLIB_MAGIC, 514 .isc_q_align = PAGE_SIZE, 515 .isc_tx_maxsize = EM_TSO_SIZE, 516 .isc_tx_maxsegsize = PAGE_SIZE, 517 .isc_rx_maxsize = MJUM9BYTES, 518 .isc_rx_nsegments = 1, 519 .isc_rx_maxsegsize = MJUM9BYTES, 520 .isc_nfl = 1, 521 .isc_nrxqs = 1, 522 .isc_ntxqs = 1, 523 .isc_admin_intrcnt = 1, 524 .isc_vendor_info = igb_vendor_info_array, 525 .isc_driver_version = em_driver_version, 526 .isc_driver = &em_if_driver, 527 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 528 529 .isc_nrxd_min = {EM_MIN_RXD}, 530 .isc_ntxd_min = {EM_MIN_TXD}, 531 .isc_nrxd_max = {IGB_MAX_RXD}, 532 .isc_ntxd_max = {IGB_MAX_TXD}, 533 .isc_nrxd_default = {EM_DEFAULT_RXD}, 534 .isc_ntxd_default = {EM_DEFAULT_TXD}, 535 }; 536 537 if_shared_ctx_t igb_sctx = &igb_sctx_init; 538 539 /***************************************************************** 540 * 541 * Dump Registers 542 * 543 ****************************************************************/ 544 #define IGB_REGS_LEN 739 545 546 static int em_get_regs(SYSCTL_HANDLER_ARGS) 547 { 548 struct adapter *adapter = (struct adapter *)arg1; 549 struct e1000_hw *hw = &adapter->hw; 550 struct sbuf *sb; 551 u32 *regs_buff; 552 int rc; 553 554 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 555 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 556 557 rc = sysctl_wire_old_buffer(req, 0); 558 MPASS(rc == 0); 559 if (rc != 0) { 560 free(regs_buff, M_DEVBUF); 561 return (rc); 562 } 563 564 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 565 MPASS(sb != NULL); 566 if (sb == NULL) { 567 free(regs_buff, M_DEVBUF); 568 return (ENOMEM); 569 } 570 571 /* General Registers */ 572 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 573 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 574 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 575 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 576 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 577 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 578 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 579 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 580 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 581 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 582 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 583 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 584 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 585 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 586 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 587 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 588 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 589 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 590 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 591 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 592 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 593 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 594 595 sbuf_printf(sb, "General Registers\n"); 596 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 597 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 598 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 599 600 sbuf_printf(sb, "Interrupt Registers\n"); 601 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 602 603 sbuf_printf(sb, "RX Registers\n"); 604 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 605 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 606 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 607 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 608 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 609 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 610 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 611 612 sbuf_printf(sb, "TX Registers\n"); 613 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 614 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 615 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 616 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 617 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 618 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 619 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 620 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 621 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 622 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 623 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 624 625 free(regs_buff, M_DEVBUF); 626 627 #ifdef DUMP_DESCS 628 { 629 if_softc_ctx_t scctx = adapter->shared; 630 struct rx_ring *rxr = &rx_que->rxr; 631 struct tx_ring *txr = &tx_que->txr; 632 int ntxd = scctx->isc_ntxd[0]; 633 int nrxd = scctx->isc_nrxd[0]; 634 int j; 635 636 for (j = 0; j < nrxd; j++) { 637 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 638 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 639 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 640 } 641 642 for (j = 0; j < min(ntxd, 256); j++) { 643 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 644 645 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 646 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 647 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 648 649 } 650 } 651 #endif 652 653 rc = sbuf_finish(sb); 654 sbuf_delete(sb); 655 return(rc); 656 } 657 658 static void * 659 em_register(device_t dev) 660 { 661 return (em_sctx); 662 } 663 664 static void * 665 igb_register(device_t dev) 666 { 667 return (igb_sctx); 668 } 669 670 static int 671 em_set_num_queues(if_ctx_t ctx) 672 { 673 struct adapter *adapter = iflib_get_softc(ctx); 674 int maxqueues; 675 676 /* Sanity check based on HW */ 677 switch (adapter->hw.mac.type) { 678 case e1000_82576: 679 case e1000_82580: 680 case e1000_i350: 681 case e1000_i354: 682 maxqueues = 8; 683 break; 684 case e1000_i210: 685 case e1000_82575: 686 maxqueues = 4; 687 break; 688 case e1000_i211: 689 case e1000_82574: 690 maxqueues = 2; 691 break; 692 default: 693 maxqueues = 1; 694 break; 695 } 696 697 return (maxqueues); 698 } 699 700 701 #define EM_CAPS \ 702 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 703 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 704 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 705 706 #define IGB_CAPS \ 707 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 708 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 709 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 710 711 /********************************************************************* 712 * Device initialization routine 713 * 714 * The attach entry point is called when the driver is being loaded. 715 * This routine identifies the type of hardware, allocates all resources 716 * and initializes the hardware. 717 * 718 * return 0 on success, positive on failure 719 *********************************************************************/ 720 721 static int 722 em_if_attach_pre(if_ctx_t ctx) 723 { 724 struct adapter *adapter; 725 if_softc_ctx_t scctx; 726 device_t dev; 727 struct e1000_hw *hw; 728 int error = 0; 729 730 INIT_DEBUGOUT("em_if_attach_pre begin"); 731 dev = iflib_get_dev(ctx); 732 adapter = iflib_get_softc(ctx); 733 734 if (resource_disabled("em", device_get_unit(dev))) { 735 device_printf(dev, "Disabled by device hint\n"); 736 return (ENXIO); 737 } 738 739 adapter->ctx = ctx; 740 adapter->dev = adapter->osdep.dev = dev; 741 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 742 adapter->media = iflib_get_media(ctx); 743 hw = &adapter->hw; 744 745 adapter->tx_process_limit = scctx->isc_ntxd[0]; 746 747 /* SYSCTL stuff */ 748 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 749 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 750 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 751 em_sysctl_nvm_info, "I", "NVM Information"); 752 753 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 754 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 755 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 756 em_sysctl_debug_info, "I", "Debug Information"); 757 758 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 759 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 760 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 761 em_set_flowcntl, "I", "Flow Control"); 762 763 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 764 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 765 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 766 em_get_regs, "A", "Dump Registers"); 767 768 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 769 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 770 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 771 em_get_rs, "I", "Dump RS indexes"); 772 773 /* Determine hardware and mac info */ 774 em_identify_hardware(ctx); 775 776 /* Set isc_msix_bar */ 777 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 778 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 779 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 780 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 781 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 782 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 783 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 784 785 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 786 787 788 if (adapter->hw.mac.type >= igb_mac_min) { 789 int try_second_bar; 790 791 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 792 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 793 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 794 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 795 scctx->isc_txrx = &igb_txrx; 796 scctx->isc_capenable = IGB_CAPS; 797 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 798 | CSUM_IP6_UDP | CSUM_IP6_TCP; 799 if (adapter->hw.mac.type != e1000_82575) 800 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 801 802 /* 803 ** Some new devices, as with ixgbe, now may 804 ** use a different BAR, so we need to keep 805 ** track of which is used. 806 */ 807 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 808 if (try_second_bar == 0) 809 scctx->isc_msix_bar += 4; 810 811 } else if (adapter->hw.mac.type >= em_mac_min) { 812 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 813 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 814 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 815 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 816 scctx->isc_txrx = &em_txrx; 817 scctx->isc_capenable = EM_CAPS; 818 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 819 } else { 820 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 821 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 822 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 823 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 824 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 825 scctx->isc_txrx = &lem_txrx; 826 scctx->isc_capenable = EM_CAPS; 827 if (adapter->hw.mac.type < e1000_82543) 828 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 829 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 830 scctx->isc_msix_bar = 0; 831 } 832 833 /* Setup PCI resources */ 834 if (em_allocate_pci_resources(ctx)) { 835 device_printf(dev, "Allocation of PCI resources failed\n"); 836 error = ENXIO; 837 goto err_pci; 838 } 839 840 /* 841 ** For ICH8 and family we need to 842 ** map the flash memory, and this 843 ** must happen after the MAC is 844 ** identified 845 */ 846 if ((hw->mac.type == e1000_ich8lan) || 847 (hw->mac.type == e1000_ich9lan) || 848 (hw->mac.type == e1000_ich10lan) || 849 (hw->mac.type == e1000_pchlan) || 850 (hw->mac.type == e1000_pch2lan) || 851 (hw->mac.type == e1000_pch_lpt)) { 852 int rid = EM_BAR_TYPE_FLASH; 853 adapter->flash = bus_alloc_resource_any(dev, 854 SYS_RES_MEMORY, &rid, RF_ACTIVE); 855 if (adapter->flash == NULL) { 856 device_printf(dev, "Mapping of Flash failed\n"); 857 error = ENXIO; 858 goto err_pci; 859 } 860 /* This is used in the shared code */ 861 hw->flash_address = (u8 *)adapter->flash; 862 adapter->osdep.flash_bus_space_tag = 863 rman_get_bustag(adapter->flash); 864 adapter->osdep.flash_bus_space_handle = 865 rman_get_bushandle(adapter->flash); 866 } 867 /* 868 ** In the new SPT device flash is not a 869 ** separate BAR, rather it is also in BAR0, 870 ** so use the same tag and an offset handle for the 871 ** FLASH read/write macros in the shared code. 872 */ 873 else if (hw->mac.type >= e1000_pch_spt) { 874 adapter->osdep.flash_bus_space_tag = 875 adapter->osdep.mem_bus_space_tag; 876 adapter->osdep.flash_bus_space_handle = 877 adapter->osdep.mem_bus_space_handle 878 + E1000_FLASH_BASE_ADDR; 879 } 880 881 /* Do Shared Code initialization */ 882 error = e1000_setup_init_funcs(hw, TRUE); 883 if (error) { 884 device_printf(dev, "Setup of Shared code failed, error %d\n", 885 error); 886 error = ENXIO; 887 goto err_pci; 888 } 889 890 em_setup_msix(ctx); 891 e1000_get_bus_info(hw); 892 893 /* Set up some sysctls for the tunable interrupt delays */ 894 em_add_int_delay_sysctl(adapter, "rx_int_delay", 895 "receive interrupt delay in usecs", &adapter->rx_int_delay, 896 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 897 em_add_int_delay_sysctl(adapter, "tx_int_delay", 898 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 899 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 900 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 901 "receive interrupt delay limit in usecs", 902 &adapter->rx_abs_int_delay, 903 E1000_REGISTER(hw, E1000_RADV), 904 em_rx_abs_int_delay_dflt); 905 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 906 "transmit interrupt delay limit in usecs", 907 &adapter->tx_abs_int_delay, 908 E1000_REGISTER(hw, E1000_TADV), 909 em_tx_abs_int_delay_dflt); 910 em_add_int_delay_sysctl(adapter, "itr", 911 "interrupt delay limit in usecs/4", 912 &adapter->tx_itr, 913 E1000_REGISTER(hw, E1000_ITR), 914 DEFAULT_ITR); 915 916 hw->mac.autoneg = DO_AUTO_NEG; 917 hw->phy.autoneg_wait_to_complete = FALSE; 918 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 919 920 if (adapter->hw.mac.type < em_mac_min) { 921 e1000_init_script_state_82541(&adapter->hw, TRUE); 922 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 923 } 924 /* Copper options */ 925 if (hw->phy.media_type == e1000_media_type_copper) { 926 hw->phy.mdix = AUTO_ALL_MODES; 927 hw->phy.disable_polarity_correction = FALSE; 928 hw->phy.ms_type = EM_MASTER_SLAVE; 929 } 930 931 /* 932 * Set the frame limits assuming 933 * standard ethernet sized frames. 934 */ 935 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 936 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 937 938 /* 939 * This controls when hardware reports transmit completion 940 * status. 941 */ 942 hw->mac.report_tx_early = 1; 943 944 /* Allocate multicast array memory. */ 945 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 946 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 947 if (adapter->mta == NULL) { 948 device_printf(dev, "Can not allocate multicast setup array\n"); 949 error = ENOMEM; 950 goto err_late; 951 } 952 953 /* Check SOL/IDER usage */ 954 if (e1000_check_reset_block(hw)) 955 device_printf(dev, "PHY reset is blocked" 956 " due to SOL/IDER session.\n"); 957 958 /* Sysctl for setting Energy Efficient Ethernet */ 959 hw->dev_spec.ich8lan.eee_disable = eee_setting; 960 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 961 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 962 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 963 adapter, 0, em_sysctl_eee, "I", 964 "Disable Energy Efficient Ethernet"); 965 966 /* 967 ** Start from a known state, this is 968 ** important in reading the nvm and 969 ** mac from that. 970 */ 971 e1000_reset_hw(hw); 972 973 /* Make sure we have a good EEPROM before we read from it */ 974 if (e1000_validate_nvm_checksum(hw) < 0) { 975 /* 976 ** Some PCI-E parts fail the first check due to 977 ** the link being in sleep state, call it again, 978 ** if it fails a second time its a real issue. 979 */ 980 if (e1000_validate_nvm_checksum(hw) < 0) { 981 device_printf(dev, 982 "The EEPROM Checksum Is Not Valid\n"); 983 error = EIO; 984 goto err_late; 985 } 986 } 987 988 /* Copy the permanent MAC address out of the EEPROM */ 989 if (e1000_read_mac_addr(hw) < 0) { 990 device_printf(dev, "EEPROM read error while reading MAC" 991 " address\n"); 992 error = EIO; 993 goto err_late; 994 } 995 996 if (!em_is_valid_ether_addr(hw->mac.addr)) { 997 device_printf(dev, "Invalid MAC address\n"); 998 error = EIO; 999 goto err_late; 1000 } 1001 1002 /* Disable ULP support */ 1003 e1000_disable_ulp_lpt_lp(hw, TRUE); 1004 1005 /* 1006 * Get Wake-on-Lan and Management info for later use 1007 */ 1008 em_get_wakeup(ctx); 1009 1010 iflib_set_mac(ctx, hw->mac.addr); 1011 1012 return (0); 1013 1014 err_late: 1015 em_release_hw_control(adapter); 1016 err_pci: 1017 em_free_pci_resources(ctx); 1018 free(adapter->mta, M_DEVBUF); 1019 1020 return (error); 1021 } 1022 1023 static int 1024 em_if_attach_post(if_ctx_t ctx) 1025 { 1026 struct adapter *adapter = iflib_get_softc(ctx); 1027 struct e1000_hw *hw = &adapter->hw; 1028 int error = 0; 1029 1030 /* Setup OS specific network interface */ 1031 error = em_setup_interface(ctx); 1032 if (error != 0) { 1033 goto err_late; 1034 } 1035 1036 em_reset(ctx); 1037 1038 /* Initialize statistics */ 1039 em_update_stats_counters(adapter); 1040 hw->mac.get_link_status = 1; 1041 em_if_update_admin_status(ctx); 1042 em_add_hw_stats(adapter); 1043 1044 /* Non-AMT based hardware can now take control from firmware */ 1045 if (adapter->has_manage && !adapter->has_amt) 1046 em_get_hw_control(adapter); 1047 1048 INIT_DEBUGOUT("em_if_attach_post: end"); 1049 1050 return (error); 1051 1052 err_late: 1053 em_release_hw_control(adapter); 1054 em_free_pci_resources(ctx); 1055 em_if_queues_free(ctx); 1056 free(adapter->mta, M_DEVBUF); 1057 1058 return (error); 1059 } 1060 1061 /********************************************************************* 1062 * Device removal routine 1063 * 1064 * The detach entry point is called when the driver is being removed. 1065 * This routine stops the adapter and deallocates all the resources 1066 * that were allocated for driver operation. 1067 * 1068 * return 0 on success, positive on failure 1069 *********************************************************************/ 1070 1071 static int 1072 em_if_detach(if_ctx_t ctx) 1073 { 1074 struct adapter *adapter = iflib_get_softc(ctx); 1075 1076 INIT_DEBUGOUT("em_detach: begin"); 1077 1078 e1000_phy_hw_reset(&adapter->hw); 1079 1080 em_release_manageability(adapter); 1081 em_release_hw_control(adapter); 1082 em_free_pci_resources(ctx); 1083 1084 return (0); 1085 } 1086 1087 /********************************************************************* 1088 * 1089 * Shutdown entry point 1090 * 1091 **********************************************************************/ 1092 1093 static int 1094 em_if_shutdown(if_ctx_t ctx) 1095 { 1096 return em_if_suspend(ctx); 1097 } 1098 1099 /* 1100 * Suspend/resume device methods. 1101 */ 1102 static int 1103 em_if_suspend(if_ctx_t ctx) 1104 { 1105 struct adapter *adapter = iflib_get_softc(ctx); 1106 1107 em_release_manageability(adapter); 1108 em_release_hw_control(adapter); 1109 em_enable_wakeup(ctx); 1110 return (0); 1111 } 1112 1113 static int 1114 em_if_resume(if_ctx_t ctx) 1115 { 1116 struct adapter *adapter = iflib_get_softc(ctx); 1117 1118 if (adapter->hw.mac.type == e1000_pch2lan) 1119 e1000_resume_workarounds_pchlan(&adapter->hw); 1120 em_if_init(ctx); 1121 em_init_manageability(adapter); 1122 1123 return(0); 1124 } 1125 1126 static int 1127 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1128 { 1129 int max_frame_size; 1130 struct adapter *adapter = iflib_get_softc(ctx); 1131 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1132 1133 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1134 1135 switch (adapter->hw.mac.type) { 1136 case e1000_82571: 1137 case e1000_82572: 1138 case e1000_ich9lan: 1139 case e1000_ich10lan: 1140 case e1000_pch2lan: 1141 case e1000_pch_lpt: 1142 case e1000_pch_spt: 1143 case e1000_pch_cnp: 1144 case e1000_82574: 1145 case e1000_82583: 1146 case e1000_80003es2lan: 1147 /* 9K Jumbo Frame size */ 1148 max_frame_size = 9234; 1149 break; 1150 case e1000_pchlan: 1151 max_frame_size = 4096; 1152 break; 1153 case e1000_82542: 1154 case e1000_ich8lan: 1155 /* Adapters that do not support jumbo frames */ 1156 max_frame_size = ETHER_MAX_LEN; 1157 break; 1158 default: 1159 if (adapter->hw.mac.type >= igb_mac_min) 1160 max_frame_size = 9234; 1161 else /* lem */ 1162 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1163 } 1164 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1165 return (EINVAL); 1166 } 1167 1168 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1169 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1170 return (0); 1171 } 1172 1173 /********************************************************************* 1174 * Init entry point 1175 * 1176 * This routine is used in two ways. It is used by the stack as 1177 * init entry point in network interface structure. It is also used 1178 * by the driver as a hw/sw initialization routine to get to a 1179 * consistent state. 1180 * 1181 * return 0 on success, positive on failure 1182 **********************************************************************/ 1183 1184 static void 1185 em_if_init(if_ctx_t ctx) 1186 { 1187 struct adapter *adapter = iflib_get_softc(ctx); 1188 struct ifnet *ifp = iflib_get_ifp(ctx); 1189 struct em_tx_queue *tx_que; 1190 int i; 1191 INIT_DEBUGOUT("em_if_init: begin"); 1192 1193 /* Get the latest mac address, User can use a LAA */ 1194 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1195 ETHER_ADDR_LEN); 1196 1197 /* Put the address into the Receive Address Array */ 1198 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1199 1200 /* 1201 * With the 82571 adapter, RAR[0] may be overwritten 1202 * when the other port is reset, we make a duplicate 1203 * in RAR[14] for that eventuality, this assures 1204 * the interface continues to function. 1205 */ 1206 if (adapter->hw.mac.type == e1000_82571) { 1207 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1208 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1209 E1000_RAR_ENTRIES - 1); 1210 } 1211 1212 1213 /* Initialize the hardware */ 1214 em_reset(ctx); 1215 em_if_update_admin_status(ctx); 1216 1217 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1218 struct tx_ring *txr = &tx_que->txr; 1219 1220 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1221 } 1222 1223 /* Setup VLAN support, basic and offload if available */ 1224 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1225 1226 /* Clear bad data from Rx FIFOs */ 1227 if (adapter->hw.mac.type >= igb_mac_min) 1228 e1000_rx_fifo_flush_82575(&adapter->hw); 1229 1230 /* Configure for OS presence */ 1231 em_init_manageability(adapter); 1232 1233 /* Prepare transmit descriptors and buffers */ 1234 em_initialize_transmit_unit(ctx); 1235 1236 /* Setup Multicast table */ 1237 em_if_multi_set(ctx); 1238 1239 /* 1240 * Figure out the desired mbuf 1241 * pool for doing jumbos 1242 */ 1243 if (adapter->hw.mac.max_frame_size <= 2048) 1244 adapter->rx_mbuf_sz = MCLBYTES; 1245 #ifndef CONTIGMALLOC_WORKS 1246 else 1247 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1248 #else 1249 else if (adapter->hw.mac.max_frame_size <= 4096) 1250 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1251 else 1252 adapter->rx_mbuf_sz = MJUM9BYTES; 1253 #endif 1254 em_initialize_receive_unit(ctx); 1255 1256 /* Use real VLAN Filter support? */ 1257 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1258 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1259 /* Use real VLAN Filter support */ 1260 em_setup_vlan_hw_support(adapter); 1261 else { 1262 u32 ctrl; 1263 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1264 ctrl |= E1000_CTRL_VME; 1265 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1266 } 1267 } 1268 1269 /* Don't lose promiscuous settings */ 1270 em_if_set_promisc(ctx, IFF_PROMISC); 1271 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1272 1273 /* MSI/X configuration for 82574 */ 1274 if (adapter->hw.mac.type == e1000_82574) { 1275 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1276 1277 tmp |= E1000_CTRL_EXT_PBA_CLR; 1278 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1279 /* Set the IVAR - interrupt vector routing. */ 1280 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1281 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1282 igb_configure_queues(adapter); 1283 1284 /* this clears any pending interrupts */ 1285 E1000_READ_REG(&adapter->hw, E1000_ICR); 1286 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1287 1288 /* AMT based hardware can now take control from firmware */ 1289 if (adapter->has_manage && adapter->has_amt) 1290 em_get_hw_control(adapter); 1291 1292 /* Set Energy Efficient Ethernet */ 1293 if (adapter->hw.mac.type >= igb_mac_min && 1294 adapter->hw.phy.media_type == e1000_media_type_copper) { 1295 if (adapter->hw.mac.type == e1000_i354) 1296 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1297 else 1298 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1299 } 1300 } 1301 1302 /********************************************************************* 1303 * 1304 * Fast Legacy/MSI Combined Interrupt Service routine 1305 * 1306 *********************************************************************/ 1307 int 1308 em_intr(void *arg) 1309 { 1310 struct adapter *adapter = arg; 1311 if_ctx_t ctx = adapter->ctx; 1312 u32 reg_icr; 1313 1314 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1315 1316 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1317 goto skip_stray; 1318 /* Hot eject? */ 1319 if (reg_icr == 0xffffffff) 1320 return FILTER_STRAY; 1321 1322 /* Definitely not our interrupt. */ 1323 if (reg_icr == 0x0) 1324 return FILTER_STRAY; 1325 1326 /* 1327 * Starting with the 82571 chip, bit 31 should be used to 1328 * determine whether the interrupt belongs to us. 1329 */ 1330 if (adapter->hw.mac.type >= e1000_82571 && 1331 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1332 return FILTER_STRAY; 1333 1334 skip_stray: 1335 /* Link status change */ 1336 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1337 adapter->hw.mac.get_link_status = 1; 1338 iflib_admin_intr_deferred(ctx); 1339 } 1340 1341 if (reg_icr & E1000_ICR_RXO) 1342 adapter->rx_overruns++; 1343 1344 return (FILTER_SCHEDULE_THREAD); 1345 } 1346 1347 static void 1348 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1349 { 1350 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1351 } 1352 1353 static void 1354 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1355 { 1356 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1357 } 1358 1359 static void 1360 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1361 { 1362 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1363 } 1364 1365 static void 1366 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1367 { 1368 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1369 } 1370 1371 static int 1372 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1373 { 1374 struct adapter *adapter = iflib_get_softc(ctx); 1375 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1376 1377 if (adapter->hw.mac.type >= igb_mac_min) 1378 igb_rx_enable_queue(adapter, rxq); 1379 else 1380 em_rx_enable_queue(adapter, rxq); 1381 return (0); 1382 } 1383 1384 static int 1385 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1386 { 1387 struct adapter *adapter = iflib_get_softc(ctx); 1388 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1389 1390 if (adapter->hw.mac.type >= igb_mac_min) 1391 igb_tx_enable_queue(adapter, txq); 1392 else 1393 em_tx_enable_queue(adapter, txq); 1394 return (0); 1395 } 1396 1397 /********************************************************************* 1398 * 1399 * MSIX RX Interrupt Service routine 1400 * 1401 **********************************************************************/ 1402 static int 1403 em_msix_que(void *arg) 1404 { 1405 struct em_rx_queue *que = arg; 1406 1407 ++que->irqs; 1408 1409 return (FILTER_SCHEDULE_THREAD); 1410 } 1411 1412 /********************************************************************* 1413 * 1414 * MSIX Link Fast Interrupt Service routine 1415 * 1416 **********************************************************************/ 1417 static int 1418 em_msix_link(void *arg) 1419 { 1420 struct adapter *adapter = arg; 1421 u32 reg_icr; 1422 1423 ++adapter->link_irq; 1424 MPASS(adapter->hw.back != NULL); 1425 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1426 1427 if (reg_icr & E1000_ICR_RXO) 1428 adapter->rx_overruns++; 1429 1430 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1431 em_handle_link(adapter->ctx); 1432 } else { 1433 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1434 EM_MSIX_LINK | E1000_IMS_LSC); 1435 if (adapter->hw.mac.type >= igb_mac_min) 1436 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1437 } 1438 1439 /* 1440 * Because we must read the ICR for this interrupt 1441 * it may clear other causes using autoclear, for 1442 * this reason we simply create a soft interrupt 1443 * for all these vectors. 1444 */ 1445 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1446 E1000_WRITE_REG(&adapter->hw, 1447 E1000_ICS, adapter->ims); 1448 } 1449 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static void 1454 em_handle_link(void *context) 1455 { 1456 if_ctx_t ctx = context; 1457 struct adapter *adapter = iflib_get_softc(ctx); 1458 1459 adapter->hw.mac.get_link_status = 1; 1460 iflib_admin_intr_deferred(ctx); 1461 } 1462 1463 1464 /********************************************************************* 1465 * 1466 * Media Ioctl callback 1467 * 1468 * This routine is called whenever the user queries the status of 1469 * the interface using ifconfig. 1470 * 1471 **********************************************************************/ 1472 static void 1473 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1474 { 1475 struct adapter *adapter = iflib_get_softc(ctx); 1476 u_char fiber_type = IFM_1000_SX; 1477 1478 INIT_DEBUGOUT("em_if_media_status: begin"); 1479 1480 iflib_admin_intr_deferred(ctx); 1481 1482 ifmr->ifm_status = IFM_AVALID; 1483 ifmr->ifm_active = IFM_ETHER; 1484 1485 if (!adapter->link_active) { 1486 return; 1487 } 1488 1489 ifmr->ifm_status |= IFM_ACTIVE; 1490 1491 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1492 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1493 if (adapter->hw.mac.type == e1000_82545) 1494 fiber_type = IFM_1000_LX; 1495 ifmr->ifm_active |= fiber_type | IFM_FDX; 1496 } else { 1497 switch (adapter->link_speed) { 1498 case 10: 1499 ifmr->ifm_active |= IFM_10_T; 1500 break; 1501 case 100: 1502 ifmr->ifm_active |= IFM_100_TX; 1503 break; 1504 case 1000: 1505 ifmr->ifm_active |= IFM_1000_T; 1506 break; 1507 } 1508 if (adapter->link_duplex == FULL_DUPLEX) 1509 ifmr->ifm_active |= IFM_FDX; 1510 else 1511 ifmr->ifm_active |= IFM_HDX; 1512 } 1513 } 1514 1515 /********************************************************************* 1516 * 1517 * Media Ioctl callback 1518 * 1519 * This routine is called when the user changes speed/duplex using 1520 * media/mediopt option with ifconfig. 1521 * 1522 **********************************************************************/ 1523 static int 1524 em_if_media_change(if_ctx_t ctx) 1525 { 1526 struct adapter *adapter = iflib_get_softc(ctx); 1527 struct ifmedia *ifm = iflib_get_media(ctx); 1528 1529 INIT_DEBUGOUT("em_if_media_change: begin"); 1530 1531 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1532 return (EINVAL); 1533 1534 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1535 case IFM_AUTO: 1536 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1537 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1538 break; 1539 case IFM_1000_LX: 1540 case IFM_1000_SX: 1541 case IFM_1000_T: 1542 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1543 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1544 break; 1545 case IFM_100_TX: 1546 adapter->hw.mac.autoneg = FALSE; 1547 adapter->hw.phy.autoneg_advertised = 0; 1548 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1549 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1550 else 1551 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1552 break; 1553 case IFM_10_T: 1554 adapter->hw.mac.autoneg = FALSE; 1555 adapter->hw.phy.autoneg_advertised = 0; 1556 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1557 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1558 else 1559 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1560 break; 1561 default: 1562 device_printf(adapter->dev, "Unsupported media type\n"); 1563 } 1564 1565 em_if_init(ctx); 1566 1567 return (0); 1568 } 1569 1570 static int 1571 em_if_set_promisc(if_ctx_t ctx, int flags) 1572 { 1573 struct adapter *adapter = iflib_get_softc(ctx); 1574 u32 reg_rctl; 1575 1576 em_disable_promisc(ctx); 1577 1578 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1579 1580 if (flags & IFF_PROMISC) { 1581 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1582 /* Turn this on if you want to see bad packets */ 1583 if (em_debug_sbp) 1584 reg_rctl |= E1000_RCTL_SBP; 1585 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1586 } else if (flags & IFF_ALLMULTI) { 1587 reg_rctl |= E1000_RCTL_MPE; 1588 reg_rctl &= ~E1000_RCTL_UPE; 1589 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1590 } 1591 return (0); 1592 } 1593 1594 static void 1595 em_disable_promisc(if_ctx_t ctx) 1596 { 1597 struct adapter *adapter = iflib_get_softc(ctx); 1598 struct ifnet *ifp = iflib_get_ifp(ctx); 1599 u32 reg_rctl; 1600 int mcnt = 0; 1601 1602 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1603 reg_rctl &= (~E1000_RCTL_UPE); 1604 if (if_getflags(ifp) & IFF_ALLMULTI) 1605 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1606 else 1607 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1608 /* Don't disable if in MAX groups */ 1609 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1610 reg_rctl &= (~E1000_RCTL_MPE); 1611 reg_rctl &= (~E1000_RCTL_SBP); 1612 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1613 } 1614 1615 1616 /********************************************************************* 1617 * Multicast Update 1618 * 1619 * This routine is called whenever multicast address list is updated. 1620 * 1621 **********************************************************************/ 1622 1623 static void 1624 em_if_multi_set(if_ctx_t ctx) 1625 { 1626 struct adapter *adapter = iflib_get_softc(ctx); 1627 struct ifnet *ifp = iflib_get_ifp(ctx); 1628 u32 reg_rctl = 0; 1629 u8 *mta; /* Multicast array memory */ 1630 int mcnt = 0; 1631 1632 IOCTL_DEBUGOUT("em_set_multi: begin"); 1633 1634 mta = adapter->mta; 1635 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1636 1637 if (adapter->hw.mac.type == e1000_82542 && 1638 adapter->hw.revision_id == E1000_REVISION_2) { 1639 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1640 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1641 e1000_pci_clear_mwi(&adapter->hw); 1642 reg_rctl |= E1000_RCTL_RST; 1643 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1644 msec_delay(5); 1645 } 1646 1647 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1648 1649 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1650 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1651 reg_rctl |= E1000_RCTL_MPE; 1652 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1653 } else 1654 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1655 1656 if (adapter->hw.mac.type == e1000_82542 && 1657 adapter->hw.revision_id == E1000_REVISION_2) { 1658 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1659 reg_rctl &= ~E1000_RCTL_RST; 1660 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1661 msec_delay(5); 1662 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1663 e1000_pci_set_mwi(&adapter->hw); 1664 } 1665 } 1666 1667 1668 /********************************************************************* 1669 * Timer routine 1670 * 1671 * This routine checks for link status and updates statistics. 1672 * 1673 **********************************************************************/ 1674 1675 static void 1676 em_if_timer(if_ctx_t ctx, uint16_t qid) 1677 { 1678 struct adapter *adapter = iflib_get_softc(ctx); 1679 struct em_rx_queue *que; 1680 int i; 1681 int trigger = 0; 1682 1683 if (qid != 0) 1684 return; 1685 1686 iflib_admin_intr_deferred(ctx); 1687 /* Reset LAA into RAR[0] on 82571 */ 1688 if ((adapter->hw.mac.type == e1000_82571) && 1689 e1000_get_laa_state_82571(&adapter->hw)) 1690 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1691 1692 if (adapter->hw.mac.type < em_mac_min) 1693 lem_smartspeed(adapter); 1694 1695 /* Mask to use in the irq trigger */ 1696 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1697 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1698 trigger |= que->eims; 1699 } else { 1700 trigger = E1000_ICS_RXDMT0; 1701 } 1702 } 1703 1704 1705 static void 1706 em_if_update_admin_status(if_ctx_t ctx) 1707 { 1708 struct adapter *adapter = iflib_get_softc(ctx); 1709 struct e1000_hw *hw = &adapter->hw; 1710 struct ifnet *ifp = iflib_get_ifp(ctx); 1711 device_t dev = iflib_get_dev(ctx); 1712 u32 link_check, thstat, ctrl; 1713 1714 link_check = thstat = ctrl = 0; 1715 /* Get the cached link value or read phy for real */ 1716 switch (hw->phy.media_type) { 1717 case e1000_media_type_copper: 1718 if (hw->mac.get_link_status) { 1719 if (hw->mac.type == e1000_pch_spt) 1720 msec_delay(50); 1721 /* Do the work to read phy */ 1722 e1000_check_for_link(hw); 1723 link_check = !hw->mac.get_link_status; 1724 if (link_check) /* ESB2 fix */ 1725 e1000_cfg_on_link_up(hw); 1726 } else { 1727 link_check = TRUE; 1728 } 1729 break; 1730 case e1000_media_type_fiber: 1731 e1000_check_for_link(hw); 1732 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1733 E1000_STATUS_LU); 1734 break; 1735 case e1000_media_type_internal_serdes: 1736 e1000_check_for_link(hw); 1737 link_check = adapter->hw.mac.serdes_has_link; 1738 break; 1739 /* VF device is type_unknown */ 1740 case e1000_media_type_unknown: 1741 e1000_check_for_link(hw); 1742 link_check = !hw->mac.get_link_status; 1743 /* FALLTHROUGH */ 1744 default: 1745 break; 1746 } 1747 1748 /* Check for thermal downshift or shutdown */ 1749 if (hw->mac.type == e1000_i350) { 1750 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1751 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1752 } 1753 1754 /* Now check for a transition */ 1755 if (link_check && (adapter->link_active == 0)) { 1756 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1757 &adapter->link_duplex); 1758 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1759 if ((adapter->link_speed != SPEED_1000) && 1760 ((hw->mac.type == e1000_82571) || 1761 (hw->mac.type == e1000_82572))) { 1762 int tarc0; 1763 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1764 tarc0 &= ~TARC_SPEED_MODE_BIT; 1765 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1766 } 1767 if (bootverbose) 1768 device_printf(dev, "Link is up %d Mbps %s\n", 1769 adapter->link_speed, 1770 ((adapter->link_duplex == FULL_DUPLEX) ? 1771 "Full Duplex" : "Half Duplex")); 1772 adapter->link_active = 1; 1773 adapter->smartspeed = 0; 1774 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1775 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && 1776 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1777 device_printf(dev, "Link: thermal downshift\n"); 1778 /* Delay Link Up for Phy update */ 1779 if (((hw->mac.type == e1000_i210) || 1780 (hw->mac.type == e1000_i211)) && 1781 (hw->phy.id == I210_I_PHY_ID)) 1782 msec_delay(I210_LINK_DELAY); 1783 /* Reset if the media type changed. */ 1784 if ((hw->dev_spec._82575.media_changed) && 1785 (adapter->hw.mac.type >= igb_mac_min)) { 1786 hw->dev_spec._82575.media_changed = false; 1787 adapter->flags |= IGB_MEDIA_RESET; 1788 em_reset(ctx); 1789 } 1790 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1791 printf("Link state changed to up\n"); 1792 } else if (!link_check && (adapter->link_active == 1)) { 1793 if_setbaudrate(ifp, 0); 1794 adapter->link_speed = 0; 1795 adapter->link_duplex = 0; 1796 if (bootverbose) 1797 device_printf(dev, "Link is Down\n"); 1798 adapter->link_active = 0; 1799 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1800 printf("link state changed to down\n"); 1801 } 1802 em_update_stats_counters(adapter); 1803 1804 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1805 } 1806 1807 /********************************************************************* 1808 * 1809 * This routine disables all traffic on the adapter by issuing a 1810 * global reset on the MAC and deallocates TX/RX buffers. 1811 * 1812 * This routine should always be called with BOTH the CORE 1813 * and TX locks. 1814 **********************************************************************/ 1815 1816 static void 1817 em_if_stop(if_ctx_t ctx) 1818 { 1819 struct adapter *adapter = iflib_get_softc(ctx); 1820 1821 INIT_DEBUGOUT("em_stop: begin"); 1822 1823 e1000_reset_hw(&adapter->hw); 1824 if (adapter->hw.mac.type >= e1000_82544) 1825 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1826 1827 e1000_led_off(&adapter->hw); 1828 e1000_cleanup_led(&adapter->hw); 1829 } 1830 1831 1832 /********************************************************************* 1833 * 1834 * Determine hardware revision. 1835 * 1836 **********************************************************************/ 1837 static void 1838 em_identify_hardware(if_ctx_t ctx) 1839 { 1840 device_t dev = iflib_get_dev(ctx); 1841 struct adapter *adapter = iflib_get_softc(ctx); 1842 1843 /* Make sure our PCI config space has the necessary stuff set */ 1844 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1845 1846 /* Save off the information about this board */ 1847 adapter->hw.vendor_id = pci_get_vendor(dev); 1848 adapter->hw.device_id = pci_get_device(dev); 1849 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1850 adapter->hw.subsystem_vendor_id = 1851 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1852 adapter->hw.subsystem_device_id = 1853 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1854 1855 /* Do Shared Code Init and Setup */ 1856 if (e1000_set_mac_type(&adapter->hw)) { 1857 device_printf(dev, "Setup init failure\n"); 1858 return; 1859 } 1860 } 1861 1862 static int 1863 em_allocate_pci_resources(if_ctx_t ctx) 1864 { 1865 struct adapter *adapter = iflib_get_softc(ctx); 1866 device_t dev = iflib_get_dev(ctx); 1867 int rid, val; 1868 1869 rid = PCIR_BAR(0); 1870 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1871 &rid, RF_ACTIVE); 1872 if (adapter->memory == NULL) { 1873 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1874 return (ENXIO); 1875 } 1876 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1877 adapter->osdep.mem_bus_space_handle = 1878 rman_get_bushandle(adapter->memory); 1879 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1880 1881 /* Only older adapters use IO mapping */ 1882 if (adapter->hw.mac.type < em_mac_min && 1883 adapter->hw.mac.type > e1000_82543) { 1884 /* Figure our where our IO BAR is ? */ 1885 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1886 val = pci_read_config(dev, rid, 4); 1887 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1888 adapter->io_rid = rid; 1889 break; 1890 } 1891 rid += 4; 1892 /* check for 64bit BAR */ 1893 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1894 rid += 4; 1895 } 1896 if (rid >= PCIR_CIS) { 1897 device_printf(dev, "Unable to locate IO BAR\n"); 1898 return (ENXIO); 1899 } 1900 adapter->ioport = bus_alloc_resource_any(dev, 1901 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1902 if (adapter->ioport == NULL) { 1903 device_printf(dev, "Unable to allocate bus resource: " 1904 "ioport\n"); 1905 return (ENXIO); 1906 } 1907 adapter->hw.io_base = 0; 1908 adapter->osdep.io_bus_space_tag = 1909 rman_get_bustag(adapter->ioport); 1910 adapter->osdep.io_bus_space_handle = 1911 rman_get_bushandle(adapter->ioport); 1912 } 1913 1914 adapter->hw.back = &adapter->osdep; 1915 1916 return (0); 1917 } 1918 1919 /********************************************************************* 1920 * 1921 * Setup the MSIX Interrupt handlers 1922 * 1923 **********************************************************************/ 1924 static int 1925 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1926 { 1927 struct adapter *adapter = iflib_get_softc(ctx); 1928 struct em_rx_queue *rx_que = adapter->rx_queues; 1929 struct em_tx_queue *tx_que = adapter->tx_queues; 1930 int error, rid, i, vector = 0, rx_vectors; 1931 char buf[16]; 1932 1933 /* First set up ring resources */ 1934 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1935 rid = vector + 1; 1936 snprintf(buf, sizeof(buf), "rxq%d", i); 1937 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1938 if (error) { 1939 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1940 adapter->rx_num_queues = i + 1; 1941 goto fail; 1942 } 1943 1944 rx_que->msix = vector; 1945 1946 /* 1947 * Set the bit to enable interrupt 1948 * in E1000_IMS -- bits 20 and 21 1949 * are for RX0 and RX1, note this has 1950 * NOTHING to do with the MSIX vector 1951 */ 1952 if (adapter->hw.mac.type == e1000_82574) { 1953 rx_que->eims = 1 << (20 + i); 1954 adapter->ims |= rx_que->eims; 1955 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1956 } else if (adapter->hw.mac.type == e1000_82575) 1957 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1958 else 1959 rx_que->eims = 1 << vector; 1960 } 1961 rx_vectors = vector; 1962 1963 vector = 0; 1964 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1965 rid = vector + 1; 1966 snprintf(buf, sizeof(buf), "txq%d", i); 1967 tx_que = &adapter->tx_queues[i]; 1968 iflib_softirq_alloc_generic(ctx, 1969 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1970 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1971 1972 tx_que->msix = (vector % adapter->tx_num_queues); 1973 1974 /* 1975 * Set the bit to enable interrupt 1976 * in E1000_IMS -- bits 22 and 23 1977 * are for TX0 and TX1, note this has 1978 * NOTHING to do with the MSIX vector 1979 */ 1980 if (adapter->hw.mac.type == e1000_82574) { 1981 tx_que->eims = 1 << (22 + i); 1982 adapter->ims |= tx_que->eims; 1983 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1984 } else if (adapter->hw.mac.type == e1000_82575) { 1985 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1986 } else { 1987 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1988 } 1989 } 1990 1991 /* Link interrupt */ 1992 rid = rx_vectors + 1; 1993 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1994 1995 if (error) { 1996 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1997 goto fail; 1998 } 1999 adapter->linkvec = rx_vectors; 2000 if (adapter->hw.mac.type < igb_mac_min) { 2001 adapter->ivars |= (8 | rx_vectors) << 16; 2002 adapter->ivars |= 0x80000000; 2003 } 2004 return (0); 2005 fail: 2006 iflib_irq_free(ctx, &adapter->irq); 2007 rx_que = adapter->rx_queues; 2008 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2009 iflib_irq_free(ctx, &rx_que->que_irq); 2010 return (error); 2011 } 2012 2013 static void 2014 igb_configure_queues(struct adapter *adapter) 2015 { 2016 struct e1000_hw *hw = &adapter->hw; 2017 struct em_rx_queue *rx_que; 2018 struct em_tx_queue *tx_que; 2019 u32 tmp, ivar = 0, newitr = 0; 2020 2021 /* First turn on RSS capability */ 2022 if (adapter->hw.mac.type != e1000_82575) 2023 E1000_WRITE_REG(hw, E1000_GPIE, 2024 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2025 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2026 2027 /* Turn on MSIX */ 2028 switch (adapter->hw.mac.type) { 2029 case e1000_82580: 2030 case e1000_i350: 2031 case e1000_i354: 2032 case e1000_i210: 2033 case e1000_i211: 2034 case e1000_vfadapt: 2035 case e1000_vfadapt_i350: 2036 /* RX entries */ 2037 for (int i = 0; i < adapter->rx_num_queues; i++) { 2038 u32 index = i >> 1; 2039 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2040 rx_que = &adapter->rx_queues[i]; 2041 if (i & 1) { 2042 ivar &= 0xFF00FFFF; 2043 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2044 } else { 2045 ivar &= 0xFFFFFF00; 2046 ivar |= rx_que->msix | E1000_IVAR_VALID; 2047 } 2048 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2049 } 2050 /* TX entries */ 2051 for (int i = 0; i < adapter->tx_num_queues; i++) { 2052 u32 index = i >> 1; 2053 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2054 tx_que = &adapter->tx_queues[i]; 2055 if (i & 1) { 2056 ivar &= 0x00FFFFFF; 2057 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2058 } else { 2059 ivar &= 0xFFFF00FF; 2060 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2061 } 2062 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2063 adapter->que_mask |= tx_que->eims; 2064 } 2065 2066 /* And for the link interrupt */ 2067 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2068 adapter->link_mask = 1 << adapter->linkvec; 2069 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2070 break; 2071 case e1000_82576: 2072 /* RX entries */ 2073 for (int i = 0; i < adapter->rx_num_queues; i++) { 2074 u32 index = i & 0x7; /* Each IVAR has two entries */ 2075 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2076 rx_que = &adapter->rx_queues[i]; 2077 if (i < 8) { 2078 ivar &= 0xFFFFFF00; 2079 ivar |= rx_que->msix | E1000_IVAR_VALID; 2080 } else { 2081 ivar &= 0xFF00FFFF; 2082 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2083 } 2084 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2085 adapter->que_mask |= rx_que->eims; 2086 } 2087 /* TX entries */ 2088 for (int i = 0; i < adapter->tx_num_queues; i++) { 2089 u32 index = i & 0x7; /* Each IVAR has two entries */ 2090 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2091 tx_que = &adapter->tx_queues[i]; 2092 if (i < 8) { 2093 ivar &= 0xFFFF00FF; 2094 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2095 } else { 2096 ivar &= 0x00FFFFFF; 2097 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2098 } 2099 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2100 adapter->que_mask |= tx_que->eims; 2101 } 2102 2103 /* And for the link interrupt */ 2104 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2105 adapter->link_mask = 1 << adapter->linkvec; 2106 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2107 break; 2108 2109 case e1000_82575: 2110 /* enable MSI-X support*/ 2111 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2112 tmp |= E1000_CTRL_EXT_PBA_CLR; 2113 /* Auto-Mask interrupts upon ICR read. */ 2114 tmp |= E1000_CTRL_EXT_EIAME; 2115 tmp |= E1000_CTRL_EXT_IRCA; 2116 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2117 2118 /* Queues */ 2119 for (int i = 0; i < adapter->rx_num_queues; i++) { 2120 rx_que = &adapter->rx_queues[i]; 2121 tmp = E1000_EICR_RX_QUEUE0 << i; 2122 tmp |= E1000_EICR_TX_QUEUE0 << i; 2123 rx_que->eims = tmp; 2124 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2125 i, rx_que->eims); 2126 adapter->que_mask |= rx_que->eims; 2127 } 2128 2129 /* Link */ 2130 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2131 E1000_EIMS_OTHER); 2132 adapter->link_mask |= E1000_EIMS_OTHER; 2133 default: 2134 break; 2135 } 2136 2137 /* Set the starting interrupt rate */ 2138 if (em_max_interrupt_rate > 0) 2139 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2140 2141 if (hw->mac.type == e1000_82575) 2142 newitr |= newitr << 16; 2143 else 2144 newitr |= E1000_EITR_CNT_IGNR; 2145 2146 for (int i = 0; i < adapter->rx_num_queues; i++) { 2147 rx_que = &adapter->rx_queues[i]; 2148 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2149 } 2150 2151 return; 2152 } 2153 2154 static void 2155 em_free_pci_resources(if_ctx_t ctx) 2156 { 2157 struct adapter *adapter = iflib_get_softc(ctx); 2158 struct em_rx_queue *que = adapter->rx_queues; 2159 device_t dev = iflib_get_dev(ctx); 2160 2161 /* Release all msix queue resources */ 2162 if (adapter->intr_type == IFLIB_INTR_MSIX) 2163 iflib_irq_free(ctx, &adapter->irq); 2164 2165 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2166 iflib_irq_free(ctx, &que->que_irq); 2167 } 2168 2169 /* First release all the interrupt resources */ 2170 if (adapter->memory != NULL) { 2171 bus_release_resource(dev, SYS_RES_MEMORY, 2172 PCIR_BAR(0), adapter->memory); 2173 adapter->memory = NULL; 2174 } 2175 2176 if (adapter->flash != NULL) { 2177 bus_release_resource(dev, SYS_RES_MEMORY, 2178 EM_FLASH, adapter->flash); 2179 adapter->flash = NULL; 2180 } 2181 if (adapter->ioport != NULL) 2182 bus_release_resource(dev, SYS_RES_IOPORT, 2183 adapter->io_rid, adapter->ioport); 2184 } 2185 2186 /* Setup MSI or MSI/X */ 2187 static int 2188 em_setup_msix(if_ctx_t ctx) 2189 { 2190 struct adapter *adapter = iflib_get_softc(ctx); 2191 2192 if (adapter->hw.mac.type == e1000_82574) { 2193 em_enable_vectors_82574(ctx); 2194 } 2195 return (0); 2196 } 2197 2198 /********************************************************************* 2199 * 2200 * Initialize the hardware to a configuration 2201 * as specified by the adapter structure. 2202 * 2203 **********************************************************************/ 2204 2205 static void 2206 lem_smartspeed(struct adapter *adapter) 2207 { 2208 u16 phy_tmp; 2209 2210 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2211 adapter->hw.mac.autoneg == 0 || 2212 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2213 return; 2214 2215 if (adapter->smartspeed == 0) { 2216 /* If Master/Slave config fault is asserted twice, 2217 * we assume back-to-back */ 2218 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2219 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2220 return; 2221 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2222 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2223 e1000_read_phy_reg(&adapter->hw, 2224 PHY_1000T_CTRL, &phy_tmp); 2225 if(phy_tmp & CR_1000T_MS_ENABLE) { 2226 phy_tmp &= ~CR_1000T_MS_ENABLE; 2227 e1000_write_phy_reg(&adapter->hw, 2228 PHY_1000T_CTRL, phy_tmp); 2229 adapter->smartspeed++; 2230 if(adapter->hw.mac.autoneg && 2231 !e1000_copper_link_autoneg(&adapter->hw) && 2232 !e1000_read_phy_reg(&adapter->hw, 2233 PHY_CONTROL, &phy_tmp)) { 2234 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2235 MII_CR_RESTART_AUTO_NEG); 2236 e1000_write_phy_reg(&adapter->hw, 2237 PHY_CONTROL, phy_tmp); 2238 } 2239 } 2240 } 2241 return; 2242 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2243 /* If still no link, perhaps using 2/3 pair cable */ 2244 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2245 phy_tmp |= CR_1000T_MS_ENABLE; 2246 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2247 if(adapter->hw.mac.autoneg && 2248 !e1000_copper_link_autoneg(&adapter->hw) && 2249 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2250 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2251 MII_CR_RESTART_AUTO_NEG); 2252 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2253 } 2254 } 2255 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2256 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2257 adapter->smartspeed = 0; 2258 } 2259 2260 /********************************************************************* 2261 * 2262 * Initialize the DMA Coalescing feature 2263 * 2264 **********************************************************************/ 2265 static void 2266 igb_init_dmac(struct adapter *adapter, u32 pba) 2267 { 2268 device_t dev = adapter->dev; 2269 struct e1000_hw *hw = &adapter->hw; 2270 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2271 u16 hwm; 2272 u16 max_frame_size; 2273 2274 if (hw->mac.type == e1000_i211) 2275 return; 2276 2277 max_frame_size = adapter->shared->isc_max_frame_size; 2278 if (hw->mac.type > e1000_82580) { 2279 2280 if (adapter->dmac == 0) { /* Disabling it */ 2281 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2282 return; 2283 } else 2284 device_printf(dev, "DMA Coalescing enabled\n"); 2285 2286 /* Set starting threshold */ 2287 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2288 2289 hwm = 64 * pba - max_frame_size / 16; 2290 if (hwm < 64 * (pba - 6)) 2291 hwm = 64 * (pba - 6); 2292 reg = E1000_READ_REG(hw, E1000_FCRTC); 2293 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2294 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2295 & E1000_FCRTC_RTH_COAL_MASK); 2296 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2297 2298 2299 dmac = pba - max_frame_size / 512; 2300 if (dmac < pba - 10) 2301 dmac = pba - 10; 2302 reg = E1000_READ_REG(hw, E1000_DMACR); 2303 reg &= ~E1000_DMACR_DMACTHR_MASK; 2304 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2305 & E1000_DMACR_DMACTHR_MASK); 2306 2307 /* transition to L0x or L1 if available..*/ 2308 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2309 2310 /* Check if status is 2.5Gb backplane connection 2311 * before configuration of watchdog timer, which is 2312 * in msec values in 12.8usec intervals 2313 * watchdog timer= msec values in 32usec intervals 2314 * for non 2.5Gb connection 2315 */ 2316 if (hw->mac.type == e1000_i354) { 2317 int status = E1000_READ_REG(hw, E1000_STATUS); 2318 if ((status & E1000_STATUS_2P5_SKU) && 2319 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2320 reg |= ((adapter->dmac * 5) >> 6); 2321 else 2322 reg |= (adapter->dmac >> 5); 2323 } else { 2324 reg |= (adapter->dmac >> 5); 2325 } 2326 2327 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2328 2329 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2330 2331 /* Set the interval before transition */ 2332 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2333 if (hw->mac.type == e1000_i350) 2334 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2335 /* 2336 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2337 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2338 */ 2339 if (hw->mac.type == e1000_i354) { 2340 int status = E1000_READ_REG(hw, E1000_STATUS); 2341 if ((status & E1000_STATUS_2P5_SKU) && 2342 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2343 reg |= 0xA; 2344 else 2345 reg |= 0x4; 2346 } else { 2347 reg |= 0x4; 2348 } 2349 2350 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2351 2352 /* free space in tx packet buffer to wake from DMA coal */ 2353 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2354 (2 * max_frame_size)) >> 6); 2355 2356 /* make low power state decision controlled by DMA coal */ 2357 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2358 reg &= ~E1000_PCIEMISC_LX_DECISION; 2359 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2360 2361 } else if (hw->mac.type == e1000_82580) { 2362 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2363 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2364 reg & ~E1000_PCIEMISC_LX_DECISION); 2365 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2366 } 2367 } 2368 2369 static void 2370 em_reset(if_ctx_t ctx) 2371 { 2372 device_t dev = iflib_get_dev(ctx); 2373 struct adapter *adapter = iflib_get_softc(ctx); 2374 struct ifnet *ifp = iflib_get_ifp(ctx); 2375 struct e1000_hw *hw = &adapter->hw; 2376 u16 rx_buffer_size; 2377 u32 pba; 2378 2379 INIT_DEBUGOUT("em_reset: begin"); 2380 /* Let the firmware know the OS is in control */ 2381 em_get_hw_control(adapter); 2382 2383 /* Set up smart power down as default off on newer adapters. */ 2384 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2385 hw->mac.type == e1000_82572)) { 2386 u16 phy_tmp = 0; 2387 2388 /* Speed up time to link by disabling smart power down. */ 2389 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2390 phy_tmp &= ~IGP02E1000_PM_SPD; 2391 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2392 } 2393 2394 /* 2395 * Packet Buffer Allocation (PBA) 2396 * Writing PBA sets the receive portion of the buffer 2397 * the remainder is used for the transmit buffer. 2398 */ 2399 switch (hw->mac.type) { 2400 /* Total Packet Buffer on these is 48K */ 2401 case e1000_82571: 2402 case e1000_82572: 2403 case e1000_80003es2lan: 2404 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2405 break; 2406 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2407 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2408 break; 2409 case e1000_82574: 2410 case e1000_82583: 2411 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2412 break; 2413 case e1000_ich8lan: 2414 pba = E1000_PBA_8K; 2415 break; 2416 case e1000_ich9lan: 2417 case e1000_ich10lan: 2418 /* Boost Receive side for jumbo frames */ 2419 if (adapter->hw.mac.max_frame_size > 4096) 2420 pba = E1000_PBA_14K; 2421 else 2422 pba = E1000_PBA_10K; 2423 break; 2424 case e1000_pchlan: 2425 case e1000_pch2lan: 2426 case e1000_pch_lpt: 2427 case e1000_pch_spt: 2428 case e1000_pch_cnp: 2429 pba = E1000_PBA_26K; 2430 break; 2431 case e1000_82575: 2432 pba = E1000_PBA_32K; 2433 break; 2434 case e1000_82576: 2435 case e1000_vfadapt: 2436 pba = E1000_READ_REG(hw, E1000_RXPBS); 2437 pba &= E1000_RXPBS_SIZE_MASK_82576; 2438 break; 2439 case e1000_82580: 2440 case e1000_i350: 2441 case e1000_i354: 2442 case e1000_vfadapt_i350: 2443 pba = E1000_READ_REG(hw, E1000_RXPBS); 2444 pba = e1000_rxpbs_adjust_82580(pba); 2445 break; 2446 case e1000_i210: 2447 case e1000_i211: 2448 pba = E1000_PBA_34K; 2449 break; 2450 default: 2451 if (adapter->hw.mac.max_frame_size > 8192) 2452 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2453 else 2454 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2455 } 2456 2457 /* Special needs in case of Jumbo frames */ 2458 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2459 u32 tx_space, min_tx, min_rx; 2460 pba = E1000_READ_REG(hw, E1000_PBA); 2461 tx_space = pba >> 16; 2462 pba &= 0xffff; 2463 min_tx = (adapter->hw.mac.max_frame_size + 2464 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2465 min_tx = roundup2(min_tx, 1024); 2466 min_tx >>= 10; 2467 min_rx = adapter->hw.mac.max_frame_size; 2468 min_rx = roundup2(min_rx, 1024); 2469 min_rx >>= 10; 2470 if (tx_space < min_tx && 2471 ((min_tx - tx_space) < pba)) { 2472 pba = pba - (min_tx - tx_space); 2473 /* 2474 * if short on rx space, rx wins 2475 * and must trump tx adjustment 2476 */ 2477 if (pba < min_rx) 2478 pba = min_rx; 2479 } 2480 E1000_WRITE_REG(hw, E1000_PBA, pba); 2481 } 2482 2483 if (hw->mac.type < igb_mac_min) 2484 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2485 2486 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2487 2488 /* 2489 * These parameters control the automatic generation (Tx) and 2490 * response (Rx) to Ethernet PAUSE frames. 2491 * - High water mark should allow for at least two frames to be 2492 * received after sending an XOFF. 2493 * - Low water mark works best when it is very near the high water mark. 2494 * This allows the receiver to restart by sending XON when it has 2495 * drained a bit. Here we use an arbitrary value of 1500 which will 2496 * restart after one full frame is pulled from the buffer. There 2497 * could be several smaller frames in the buffer and if so they will 2498 * not trigger the XON until their total number reduces the buffer 2499 * by 1500. 2500 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2501 */ 2502 rx_buffer_size = (pba & 0xffff) << 10; 2503 hw->fc.high_water = rx_buffer_size - 2504 roundup2(adapter->hw.mac.max_frame_size, 1024); 2505 hw->fc.low_water = hw->fc.high_water - 1500; 2506 2507 if (adapter->fc) /* locally set flow control value? */ 2508 hw->fc.requested_mode = adapter->fc; 2509 else 2510 hw->fc.requested_mode = e1000_fc_full; 2511 2512 if (hw->mac.type == e1000_80003es2lan) 2513 hw->fc.pause_time = 0xFFFF; 2514 else 2515 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2516 2517 hw->fc.send_xon = TRUE; 2518 2519 /* Device specific overrides/settings */ 2520 switch (hw->mac.type) { 2521 case e1000_pchlan: 2522 /* Workaround: no TX flow ctrl for PCH */ 2523 hw->fc.requested_mode = e1000_fc_rx_pause; 2524 hw->fc.pause_time = 0xFFFF; /* override */ 2525 if (if_getmtu(ifp) > ETHERMTU) { 2526 hw->fc.high_water = 0x3500; 2527 hw->fc.low_water = 0x1500; 2528 } else { 2529 hw->fc.high_water = 0x5000; 2530 hw->fc.low_water = 0x3000; 2531 } 2532 hw->fc.refresh_time = 0x1000; 2533 break; 2534 case e1000_pch2lan: 2535 case e1000_pch_lpt: 2536 case e1000_pch_spt: 2537 case e1000_pch_cnp: 2538 hw->fc.high_water = 0x5C20; 2539 hw->fc.low_water = 0x5048; 2540 hw->fc.pause_time = 0x0650; 2541 hw->fc.refresh_time = 0x0400; 2542 /* Jumbos need adjusted PBA */ 2543 if (if_getmtu(ifp) > ETHERMTU) 2544 E1000_WRITE_REG(hw, E1000_PBA, 12); 2545 else 2546 E1000_WRITE_REG(hw, E1000_PBA, 26); 2547 break; 2548 case e1000_82575: 2549 case e1000_82576: 2550 /* 8-byte granularity */ 2551 hw->fc.low_water = hw->fc.high_water - 8; 2552 break; 2553 case e1000_82580: 2554 case e1000_i350: 2555 case e1000_i354: 2556 case e1000_i210: 2557 case e1000_i211: 2558 case e1000_vfadapt: 2559 case e1000_vfadapt_i350: 2560 /* 16-byte granularity */ 2561 hw->fc.low_water = hw->fc.high_water - 16; 2562 break; 2563 case e1000_ich9lan: 2564 case e1000_ich10lan: 2565 if (if_getmtu(ifp) > ETHERMTU) { 2566 hw->fc.high_water = 0x2800; 2567 hw->fc.low_water = hw->fc.high_water - 8; 2568 break; 2569 } 2570 /* FALLTHROUGH */ 2571 default: 2572 if (hw->mac.type == e1000_80003es2lan) 2573 hw->fc.pause_time = 0xFFFF; 2574 break; 2575 } 2576 2577 /* Issue a global reset */ 2578 e1000_reset_hw(hw); 2579 if (adapter->hw.mac.type >= igb_mac_min) { 2580 E1000_WRITE_REG(hw, E1000_WUC, 0); 2581 } else { 2582 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2583 em_disable_aspm(adapter); 2584 } 2585 if (adapter->flags & IGB_MEDIA_RESET) { 2586 e1000_setup_init_funcs(hw, TRUE); 2587 e1000_get_bus_info(hw); 2588 adapter->flags &= ~IGB_MEDIA_RESET; 2589 } 2590 /* and a re-init */ 2591 if (e1000_init_hw(hw) < 0) { 2592 device_printf(dev, "Hardware Initialization Failed\n"); 2593 return; 2594 } 2595 if (adapter->hw.mac.type >= igb_mac_min) 2596 igb_init_dmac(adapter, pba); 2597 2598 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2599 e1000_get_phy_info(hw); 2600 e1000_check_for_link(hw); 2601 } 2602 2603 #define RSSKEYLEN 10 2604 static void 2605 em_initialize_rss_mapping(struct adapter *adapter) 2606 { 2607 uint8_t rss_key[4 * RSSKEYLEN]; 2608 uint32_t reta = 0; 2609 struct e1000_hw *hw = &adapter->hw; 2610 int i; 2611 2612 /* 2613 * Configure RSS key 2614 */ 2615 arc4rand(rss_key, sizeof(rss_key), 0); 2616 for (i = 0; i < RSSKEYLEN; ++i) { 2617 uint32_t rssrk = 0; 2618 2619 rssrk = EM_RSSRK_VAL(rss_key, i); 2620 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2621 } 2622 2623 /* 2624 * Configure RSS redirect table in following fashion: 2625 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2626 */ 2627 for (i = 0; i < sizeof(reta); ++i) { 2628 uint32_t q; 2629 2630 q = (i % adapter->rx_num_queues) << 7; 2631 reta |= q << (8 * i); 2632 } 2633 2634 for (i = 0; i < 32; ++i) 2635 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2636 2637 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2638 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2639 E1000_MRQC_RSS_FIELD_IPV4 | 2640 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2641 E1000_MRQC_RSS_FIELD_IPV6_EX | 2642 E1000_MRQC_RSS_FIELD_IPV6); 2643 2644 } 2645 2646 static void 2647 igb_initialize_rss_mapping(struct adapter *adapter) 2648 { 2649 struct e1000_hw *hw = &adapter->hw; 2650 int i; 2651 int queue_id; 2652 u32 reta; 2653 u32 rss_key[10], mrqc, shift = 0; 2654 2655 /* XXX? */ 2656 if (adapter->hw.mac.type == e1000_82575) 2657 shift = 6; 2658 2659 /* 2660 * The redirection table controls which destination 2661 * queue each bucket redirects traffic to. 2662 * Each DWORD represents four queues, with the LSB 2663 * being the first queue in the DWORD. 2664 * 2665 * This just allocates buckets to queues using round-robin 2666 * allocation. 2667 * 2668 * NOTE: It Just Happens to line up with the default 2669 * RSS allocation method. 2670 */ 2671 2672 /* Warning FM follows */ 2673 reta = 0; 2674 for (i = 0; i < 128; i++) { 2675 #ifdef RSS 2676 queue_id = rss_get_indirection_to_bucket(i); 2677 /* 2678 * If we have more queues than buckets, we'll 2679 * end up mapping buckets to a subset of the 2680 * queues. 2681 * 2682 * If we have more buckets than queues, we'll 2683 * end up instead assigning multiple buckets 2684 * to queues. 2685 * 2686 * Both are suboptimal, but we need to handle 2687 * the case so we don't go out of bounds 2688 * indexing arrays and such. 2689 */ 2690 queue_id = queue_id % adapter->rx_num_queues; 2691 #else 2692 queue_id = (i % adapter->rx_num_queues); 2693 #endif 2694 /* Adjust if required */ 2695 queue_id = queue_id << shift; 2696 2697 /* 2698 * The low 8 bits are for hash value (n+0); 2699 * The next 8 bits are for hash value (n+1), etc. 2700 */ 2701 reta = reta >> 8; 2702 reta = reta | ( ((uint32_t) queue_id) << 24); 2703 if ((i & 3) == 3) { 2704 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2705 reta = 0; 2706 } 2707 } 2708 2709 /* Now fill in hash table */ 2710 2711 /* 2712 * MRQC: Multiple Receive Queues Command 2713 * Set queuing to RSS control, number depends on the device. 2714 */ 2715 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2716 2717 #ifdef RSS 2718 /* XXX ew typecasting */ 2719 rss_getkey((uint8_t *) &rss_key); 2720 #else 2721 arc4rand(&rss_key, sizeof(rss_key), 0); 2722 #endif 2723 for (i = 0; i < 10; i++) 2724 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2725 2726 /* 2727 * Configure the RSS fields to hash upon. 2728 */ 2729 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2730 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2731 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2732 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2733 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2734 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2735 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2736 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2737 2738 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2739 } 2740 2741 /********************************************************************* 2742 * 2743 * Setup networking device structure and register an interface. 2744 * 2745 **********************************************************************/ 2746 static int 2747 em_setup_interface(if_ctx_t ctx) 2748 { 2749 struct ifnet *ifp = iflib_get_ifp(ctx); 2750 struct adapter *adapter = iflib_get_softc(ctx); 2751 if_softc_ctx_t scctx = adapter->shared; 2752 uint64_t cap = 0; 2753 2754 INIT_DEBUGOUT("em_setup_interface: begin"); 2755 2756 /* TSO parameters */ 2757 if_sethwtsomax(ifp, IP_MAXPACKET); 2758 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2759 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2760 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2761 2762 /* Single Queue */ 2763 if (adapter->tx_num_queues == 1) { 2764 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2765 if_setsendqready(ifp); 2766 } 2767 2768 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2769 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2770 2771 /* 2772 * Tell the upper layer(s) we 2773 * support full VLAN capability 2774 */ 2775 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2776 if_setcapabilitiesbit(ifp, cap, 0); 2777 2778 /* 2779 * Don't turn this on by default, if vlans are 2780 * created on another pseudo device (eg. lagg) 2781 * then vlan events are not passed thru, breaking 2782 * operation, but with HW FILTER off it works. If 2783 * using vlans directly on the em driver you can 2784 * enable this and get full hardware tag filtering. 2785 */ 2786 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2787 2788 /* Enable only WOL MAGIC by default */ 2789 if (adapter->wol) { 2790 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2791 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2792 } else { 2793 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2794 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2795 } 2796 2797 /* 2798 * Specify the media types supported by this adapter and register 2799 * callbacks to update media and link information 2800 */ 2801 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2802 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2803 u_char fiber_type = IFM_1000_SX; /* default type */ 2804 2805 if (adapter->hw.mac.type == e1000_82545) 2806 fiber_type = IFM_1000_LX; 2807 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2808 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2809 } else { 2810 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2811 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2812 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2813 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2814 if (adapter->hw.phy.type != e1000_phy_ife) { 2815 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2816 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2817 } 2818 } 2819 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2820 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2821 return (0); 2822 } 2823 2824 static int 2825 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2826 { 2827 struct adapter *adapter = iflib_get_softc(ctx); 2828 if_softc_ctx_t scctx = adapter->shared; 2829 int error = E1000_SUCCESS; 2830 struct em_tx_queue *que; 2831 int i, j; 2832 2833 MPASS(adapter->tx_num_queues > 0); 2834 MPASS(adapter->tx_num_queues == ntxqsets); 2835 2836 /* First allocate the top level queue structs */ 2837 if (!(adapter->tx_queues = 2838 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2839 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2840 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2841 return(ENOMEM); 2842 } 2843 2844 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2845 /* Set up some basics */ 2846 2847 struct tx_ring *txr = &que->txr; 2848 txr->adapter = que->adapter = adapter; 2849 que->me = txr->me = i; 2850 2851 /* Allocate report status array */ 2852 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2853 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2854 error = ENOMEM; 2855 goto fail; 2856 } 2857 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2858 txr->tx_rsq[j] = QIDX_INVALID; 2859 /* get the virtual and physical address of the hardware queues */ 2860 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2861 txr->tx_paddr = paddrs[i*ntxqs]; 2862 } 2863 2864 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2865 return (0); 2866 fail: 2867 em_if_queues_free(ctx); 2868 return (error); 2869 } 2870 2871 static int 2872 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2873 { 2874 struct adapter *adapter = iflib_get_softc(ctx); 2875 int error = E1000_SUCCESS; 2876 struct em_rx_queue *que; 2877 int i; 2878 2879 MPASS(adapter->rx_num_queues > 0); 2880 MPASS(adapter->rx_num_queues == nrxqsets); 2881 2882 /* First allocate the top level queue structs */ 2883 if (!(adapter->rx_queues = 2884 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2885 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2886 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2887 error = ENOMEM; 2888 goto fail; 2889 } 2890 2891 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2892 /* Set up some basics */ 2893 struct rx_ring *rxr = &que->rxr; 2894 rxr->adapter = que->adapter = adapter; 2895 rxr->que = que; 2896 que->me = rxr->me = i; 2897 2898 /* get the virtual and physical address of the hardware queues */ 2899 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2900 rxr->rx_paddr = paddrs[i*nrxqs]; 2901 } 2902 2903 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2904 2905 return (0); 2906 fail: 2907 em_if_queues_free(ctx); 2908 return (error); 2909 } 2910 2911 static void 2912 em_if_queues_free(if_ctx_t ctx) 2913 { 2914 struct adapter *adapter = iflib_get_softc(ctx); 2915 struct em_tx_queue *tx_que = adapter->tx_queues; 2916 struct em_rx_queue *rx_que = adapter->rx_queues; 2917 2918 if (tx_que != NULL) { 2919 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2920 struct tx_ring *txr = &tx_que->txr; 2921 if (txr->tx_rsq == NULL) 2922 break; 2923 2924 free(txr->tx_rsq, M_DEVBUF); 2925 txr->tx_rsq = NULL; 2926 } 2927 free(adapter->tx_queues, M_DEVBUF); 2928 adapter->tx_queues = NULL; 2929 } 2930 2931 if (rx_que != NULL) { 2932 free(adapter->rx_queues, M_DEVBUF); 2933 adapter->rx_queues = NULL; 2934 } 2935 2936 em_release_hw_control(adapter); 2937 2938 if (adapter->mta != NULL) { 2939 free(adapter->mta, M_DEVBUF); 2940 } 2941 } 2942 2943 /********************************************************************* 2944 * 2945 * Enable transmit unit. 2946 * 2947 **********************************************************************/ 2948 static void 2949 em_initialize_transmit_unit(if_ctx_t ctx) 2950 { 2951 struct adapter *adapter = iflib_get_softc(ctx); 2952 if_softc_ctx_t scctx = adapter->shared; 2953 struct em_tx_queue *que; 2954 struct tx_ring *txr; 2955 struct e1000_hw *hw = &adapter->hw; 2956 u32 tctl, txdctl = 0, tarc, tipg = 0; 2957 2958 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2959 2960 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2961 u64 bus_addr; 2962 caddr_t offp, endp; 2963 2964 que = &adapter->tx_queues[i]; 2965 txr = &que->txr; 2966 bus_addr = txr->tx_paddr; 2967 2968 /* Clear checksum offload context. */ 2969 offp = (caddr_t)&txr->csum_flags; 2970 endp = (caddr_t)(txr + 1); 2971 bzero(offp, endp - offp); 2972 2973 /* Base and Len of TX Ring */ 2974 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2975 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2976 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2977 (u32)(bus_addr >> 32)); 2978 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2979 (u32)bus_addr); 2980 /* Init the HEAD/TAIL indices */ 2981 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2982 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2983 2984 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2985 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2986 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2987 2988 txdctl = 0; /* clear txdctl */ 2989 txdctl |= 0x1f; /* PTHRESH */ 2990 txdctl |= 1 << 8; /* HTHRESH */ 2991 txdctl |= 1 << 16;/* WTHRESH */ 2992 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2993 txdctl |= E1000_TXDCTL_GRAN; 2994 txdctl |= 1 << 25; /* LWTHRESH */ 2995 2996 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2997 } 2998 2999 /* Set the default values for the Tx Inter Packet Gap timer */ 3000 switch (adapter->hw.mac.type) { 3001 case e1000_80003es2lan: 3002 tipg = DEFAULT_82543_TIPG_IPGR1; 3003 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3004 E1000_TIPG_IPGR2_SHIFT; 3005 break; 3006 case e1000_82542: 3007 tipg = DEFAULT_82542_TIPG_IPGT; 3008 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3009 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3010 break; 3011 default: 3012 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3013 (adapter->hw.phy.media_type == 3014 e1000_media_type_internal_serdes)) 3015 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3016 else 3017 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3018 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3019 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3020 } 3021 3022 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3023 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3024 3025 if(adapter->hw.mac.type >= e1000_82540) 3026 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3027 adapter->tx_abs_int_delay.value); 3028 3029 if ((adapter->hw.mac.type == e1000_82571) || 3030 (adapter->hw.mac.type == e1000_82572)) { 3031 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3032 tarc |= TARC_SPEED_MODE_BIT; 3033 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3034 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3035 /* errata: program both queues to unweighted RR */ 3036 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3037 tarc |= 1; 3038 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3039 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3040 tarc |= 1; 3041 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3042 } else if (adapter->hw.mac.type == e1000_82574) { 3043 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3044 tarc |= TARC_ERRATA_BIT; 3045 if ( adapter->tx_num_queues > 1) { 3046 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3047 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3048 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3049 } else 3050 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3051 } 3052 3053 if (adapter->tx_int_delay.value > 0) 3054 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3055 3056 /* Program the Transmit Control Register */ 3057 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3058 tctl &= ~E1000_TCTL_CT; 3059 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3060 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3061 3062 if (adapter->hw.mac.type >= e1000_82571) 3063 tctl |= E1000_TCTL_MULR; 3064 3065 /* This write will effectively turn on the transmit unit. */ 3066 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3067 3068 /* SPT and KBL errata workarounds */ 3069 if (hw->mac.type == e1000_pch_spt) { 3070 u32 reg; 3071 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3072 reg |= E1000_RCTL_RDMTS_HEX; 3073 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3074 /* i218-i219 Specification Update 1.5.4.5 */ 3075 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3076 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3077 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3078 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3079 } 3080 } 3081 3082 /********************************************************************* 3083 * 3084 * Enable receive unit. 3085 * 3086 **********************************************************************/ 3087 3088 static void 3089 em_initialize_receive_unit(if_ctx_t ctx) 3090 { 3091 struct adapter *adapter = iflib_get_softc(ctx); 3092 if_softc_ctx_t scctx = adapter->shared; 3093 struct ifnet *ifp = iflib_get_ifp(ctx); 3094 struct e1000_hw *hw = &adapter->hw; 3095 struct em_rx_queue *que; 3096 int i; 3097 u32 rctl, rxcsum, rfctl; 3098 3099 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3100 3101 /* 3102 * Make sure receives are disabled while setting 3103 * up the descriptor ring 3104 */ 3105 rctl = E1000_READ_REG(hw, E1000_RCTL); 3106 /* Do not disable if ever enabled on this hardware */ 3107 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3108 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3109 3110 /* Setup the Receive Control Register */ 3111 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3112 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3113 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3114 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3115 3116 /* Do not store bad packets */ 3117 rctl &= ~E1000_RCTL_SBP; 3118 3119 /* Enable Long Packet receive */ 3120 if (if_getmtu(ifp) > ETHERMTU) 3121 rctl |= E1000_RCTL_LPE; 3122 else 3123 rctl &= ~E1000_RCTL_LPE; 3124 3125 /* Strip the CRC */ 3126 if (!em_disable_crc_stripping) 3127 rctl |= E1000_RCTL_SECRC; 3128 3129 if (adapter->hw.mac.type >= e1000_82540) { 3130 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3131 adapter->rx_abs_int_delay.value); 3132 3133 /* 3134 * Set the interrupt throttling rate. Value is calculated 3135 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3136 */ 3137 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3138 } 3139 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3140 adapter->rx_int_delay.value); 3141 3142 /* Use extended rx descriptor formats */ 3143 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3144 rfctl |= E1000_RFCTL_EXTEN; 3145 /* 3146 * When using MSIX interrupts we need to throttle 3147 * using the EITR register (82574 only) 3148 */ 3149 if (hw->mac.type == e1000_82574) { 3150 for (int i = 0; i < 4; i++) 3151 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3152 DEFAULT_ITR); 3153 /* Disable accelerated acknowledge */ 3154 rfctl |= E1000_RFCTL_ACK_DIS; 3155 } 3156 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3157 3158 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3159 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3160 adapter->hw.mac.type >= e1000_82543) { 3161 if (adapter->tx_num_queues > 1) { 3162 if (adapter->hw.mac.type >= igb_mac_min) { 3163 rxcsum |= E1000_RXCSUM_PCSD; 3164 if (hw->mac.type != e1000_82575) 3165 rxcsum |= E1000_RXCSUM_CRCOFL; 3166 } else 3167 rxcsum |= E1000_RXCSUM_TUOFL | 3168 E1000_RXCSUM_IPOFL | 3169 E1000_RXCSUM_PCSD; 3170 } else { 3171 if (adapter->hw.mac.type >= igb_mac_min) 3172 rxcsum |= E1000_RXCSUM_IPPCSE; 3173 else 3174 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3175 if (adapter->hw.mac.type > e1000_82575) 3176 rxcsum |= E1000_RXCSUM_CRCOFL; 3177 } 3178 } else 3179 rxcsum &= ~E1000_RXCSUM_TUOFL; 3180 3181 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3182 3183 if (adapter->rx_num_queues > 1) { 3184 if (adapter->hw.mac.type >= igb_mac_min) 3185 igb_initialize_rss_mapping(adapter); 3186 else 3187 em_initialize_rss_mapping(adapter); 3188 } 3189 3190 /* 3191 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3192 * long latencies are observed, like Lenovo X60. This 3193 * change eliminates the problem, but since having positive 3194 * values in RDTR is a known source of problems on other 3195 * platforms another solution is being sought. 3196 */ 3197 if (hw->mac.type == e1000_82573) 3198 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3199 3200 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3201 struct rx_ring *rxr = &que->rxr; 3202 /* Setup the Base and Length of the Rx Descriptor Ring */ 3203 u64 bus_addr = rxr->rx_paddr; 3204 #if 0 3205 u32 rdt = adapter->rx_num_queues -1; /* default */ 3206 #endif 3207 3208 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3209 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3210 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3211 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3212 /* Setup the Head and Tail Descriptor Pointers */ 3213 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3214 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3215 } 3216 3217 /* 3218 * Set PTHRESH for improved jumbo performance 3219 * According to 10.2.5.11 of Intel 82574 Datasheet, 3220 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3221 * Only write to RXDCTL(1) if there is a need for different 3222 * settings. 3223 */ 3224 3225 if (((adapter->hw.mac.type == e1000_ich9lan) || 3226 (adapter->hw.mac.type == e1000_pch2lan) || 3227 (adapter->hw.mac.type == e1000_ich10lan)) && 3228 (if_getmtu(ifp) > ETHERMTU)) { 3229 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3230 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3231 } else if (adapter->hw.mac.type == e1000_82574) { 3232 for (int i = 0; i < adapter->rx_num_queues; i++) { 3233 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3234 rxdctl |= 0x20; /* PTHRESH */ 3235 rxdctl |= 4 << 8; /* HTHRESH */ 3236 rxdctl |= 4 << 16;/* WTHRESH */ 3237 rxdctl |= 1 << 24; /* Switch to granularity */ 3238 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3239 } 3240 } else if (adapter->hw.mac.type >= igb_mac_min) { 3241 u32 psize, srrctl = 0; 3242 3243 if (if_getmtu(ifp) > ETHERMTU) { 3244 /* Set maximum packet len */ 3245 if (adapter->rx_mbuf_sz <= 4096) { 3246 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3247 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3248 } else if (adapter->rx_mbuf_sz > 4096) { 3249 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3250 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3251 } 3252 psize = scctx->isc_max_frame_size; 3253 /* are we on a vlan? */ 3254 if (ifp->if_vlantrunk != NULL) 3255 psize += VLAN_TAG_SIZE; 3256 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3257 } else { 3258 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3259 rctl |= E1000_RCTL_SZ_2048; 3260 } 3261 3262 /* 3263 * If TX flow control is disabled and there's >1 queue defined, 3264 * enable DROP. 3265 * 3266 * This drops frames rather than hanging the RX MAC for all queues. 3267 */ 3268 if ((adapter->rx_num_queues > 1) && 3269 (adapter->fc == e1000_fc_none || 3270 adapter->fc == e1000_fc_rx_pause)) { 3271 srrctl |= E1000_SRRCTL_DROP_EN; 3272 } 3273 /* Setup the Base and Length of the Rx Descriptor Rings */ 3274 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3275 struct rx_ring *rxr = &que->rxr; 3276 u64 bus_addr = rxr->rx_paddr; 3277 u32 rxdctl; 3278 3279 #ifdef notyet 3280 /* Configure for header split? -- ignore for now */ 3281 rxr->hdr_split = igb_header_split; 3282 #else 3283 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3284 #endif 3285 3286 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3287 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3288 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3289 (uint32_t)(bus_addr >> 32)); 3290 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3291 (uint32_t)bus_addr); 3292 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3293 /* Enable this Queue */ 3294 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3295 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3296 rxdctl &= 0xFFF00000; 3297 rxdctl |= IGB_RX_PTHRESH; 3298 rxdctl |= IGB_RX_HTHRESH << 8; 3299 rxdctl |= IGB_RX_WTHRESH << 16; 3300 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3301 } 3302 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3303 if (if_getmtu(ifp) > ETHERMTU) 3304 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3305 else 3306 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3307 } 3308 3309 /* Make sure VLAN Filters are off */ 3310 rctl &= ~E1000_RCTL_VFE; 3311 3312 if (adapter->hw.mac.type < igb_mac_min) { 3313 if (adapter->rx_mbuf_sz == MCLBYTES) 3314 rctl |= E1000_RCTL_SZ_2048; 3315 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3316 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3317 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3318 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3319 3320 /* ensure we clear use DTYPE of 00 here */ 3321 rctl &= ~0x00000C00; 3322 } 3323 3324 /* Write out the settings */ 3325 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3326 3327 return; 3328 } 3329 3330 static void 3331 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3332 { 3333 struct adapter *adapter = iflib_get_softc(ctx); 3334 u32 index, bit; 3335 3336 index = (vtag >> 5) & 0x7F; 3337 bit = vtag & 0x1F; 3338 adapter->shadow_vfta[index] |= (1 << bit); 3339 ++adapter->num_vlans; 3340 } 3341 3342 static void 3343 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3344 { 3345 struct adapter *adapter = iflib_get_softc(ctx); 3346 u32 index, bit; 3347 3348 index = (vtag >> 5) & 0x7F; 3349 bit = vtag & 0x1F; 3350 adapter->shadow_vfta[index] &= ~(1 << bit); 3351 --adapter->num_vlans; 3352 } 3353 3354 static void 3355 em_setup_vlan_hw_support(struct adapter *adapter) 3356 { 3357 struct e1000_hw *hw = &adapter->hw; 3358 u32 reg; 3359 3360 /* 3361 * We get here thru init_locked, meaning 3362 * a soft reset, this has already cleared 3363 * the VFTA and other state, so if there 3364 * have been no vlan's registered do nothing. 3365 */ 3366 if (adapter->num_vlans == 0) 3367 return; 3368 3369 /* 3370 * A soft reset zero's out the VFTA, so 3371 * we need to repopulate it now. 3372 */ 3373 for (int i = 0; i < EM_VFTA_SIZE; i++) 3374 if (adapter->shadow_vfta[i] != 0) 3375 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3376 i, adapter->shadow_vfta[i]); 3377 3378 reg = E1000_READ_REG(hw, E1000_CTRL); 3379 reg |= E1000_CTRL_VME; 3380 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3381 3382 /* Enable the Filter Table */ 3383 reg = E1000_READ_REG(hw, E1000_RCTL); 3384 reg &= ~E1000_RCTL_CFIEN; 3385 reg |= E1000_RCTL_VFE; 3386 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3387 } 3388 3389 static void 3390 em_if_enable_intr(if_ctx_t ctx) 3391 { 3392 struct adapter *adapter = iflib_get_softc(ctx); 3393 struct e1000_hw *hw = &adapter->hw; 3394 u32 ims_mask = IMS_ENABLE_MASK; 3395 3396 if (hw->mac.type == e1000_82574) { 3397 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3398 ims_mask |= adapter->ims; 3399 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3400 u32 mask = (adapter->que_mask | adapter->link_mask); 3401 3402 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3403 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3404 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3405 ims_mask = E1000_IMS_LSC; 3406 } 3407 3408 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3409 } 3410 3411 static void 3412 em_if_disable_intr(if_ctx_t ctx) 3413 { 3414 struct adapter *adapter = iflib_get_softc(ctx); 3415 struct e1000_hw *hw = &adapter->hw; 3416 3417 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3418 if (hw->mac.type >= igb_mac_min) 3419 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3420 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3421 } 3422 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3423 } 3424 3425 /* 3426 * Bit of a misnomer, what this really means is 3427 * to enable OS management of the system... aka 3428 * to disable special hardware management features 3429 */ 3430 static void 3431 em_init_manageability(struct adapter *adapter) 3432 { 3433 /* A shared code workaround */ 3434 #define E1000_82542_MANC2H E1000_MANC2H 3435 if (adapter->has_manage) { 3436 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3437 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3438 3439 /* disable hardware interception of ARP */ 3440 manc &= ~(E1000_MANC_ARP_EN); 3441 3442 /* enable receiving management packets to the host */ 3443 manc |= E1000_MANC_EN_MNG2HOST; 3444 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3445 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3446 manc2h |= E1000_MNG2HOST_PORT_623; 3447 manc2h |= E1000_MNG2HOST_PORT_664; 3448 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3449 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3450 } 3451 } 3452 3453 /* 3454 * Give control back to hardware management 3455 * controller if there is one. 3456 */ 3457 static void 3458 em_release_manageability(struct adapter *adapter) 3459 { 3460 if (adapter->has_manage) { 3461 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3462 3463 /* re-enable hardware interception of ARP */ 3464 manc |= E1000_MANC_ARP_EN; 3465 manc &= ~E1000_MANC_EN_MNG2HOST; 3466 3467 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3468 } 3469 } 3470 3471 /* 3472 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3473 * For ASF and Pass Through versions of f/w this means 3474 * that the driver is loaded. For AMT version type f/w 3475 * this means that the network i/f is open. 3476 */ 3477 static void 3478 em_get_hw_control(struct adapter *adapter) 3479 { 3480 u32 ctrl_ext, swsm; 3481 3482 if (adapter->vf_ifp) 3483 return; 3484 3485 if (adapter->hw.mac.type == e1000_82573) { 3486 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3487 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3488 swsm | E1000_SWSM_DRV_LOAD); 3489 return; 3490 } 3491 /* else */ 3492 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3493 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3494 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3495 } 3496 3497 /* 3498 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3499 * For ASF and Pass Through versions of f/w this means that 3500 * the driver is no longer loaded. For AMT versions of the 3501 * f/w this means that the network i/f is closed. 3502 */ 3503 static void 3504 em_release_hw_control(struct adapter *adapter) 3505 { 3506 u32 ctrl_ext, swsm; 3507 3508 if (!adapter->has_manage) 3509 return; 3510 3511 if (adapter->hw.mac.type == e1000_82573) { 3512 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3513 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3514 swsm & ~E1000_SWSM_DRV_LOAD); 3515 return; 3516 } 3517 /* else */ 3518 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3519 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3520 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3521 return; 3522 } 3523 3524 static int 3525 em_is_valid_ether_addr(u8 *addr) 3526 { 3527 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3528 3529 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3530 return (FALSE); 3531 } 3532 3533 return (TRUE); 3534 } 3535 3536 /* 3537 ** Parse the interface capabilities with regard 3538 ** to both system management and wake-on-lan for 3539 ** later use. 3540 */ 3541 static void 3542 em_get_wakeup(if_ctx_t ctx) 3543 { 3544 struct adapter *adapter = iflib_get_softc(ctx); 3545 device_t dev = iflib_get_dev(ctx); 3546 u16 eeprom_data = 0, device_id, apme_mask; 3547 3548 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3549 apme_mask = EM_EEPROM_APME; 3550 3551 switch (adapter->hw.mac.type) { 3552 case e1000_82542: 3553 case e1000_82543: 3554 break; 3555 case e1000_82544: 3556 e1000_read_nvm(&adapter->hw, 3557 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3558 apme_mask = EM_82544_APME; 3559 break; 3560 case e1000_82546: 3561 case e1000_82546_rev_3: 3562 if (adapter->hw.bus.func == 1) { 3563 e1000_read_nvm(&adapter->hw, 3564 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3565 break; 3566 } else 3567 e1000_read_nvm(&adapter->hw, 3568 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3569 break; 3570 case e1000_82573: 3571 case e1000_82583: 3572 adapter->has_amt = TRUE; 3573 /* FALLTHROUGH */ 3574 case e1000_82571: 3575 case e1000_82572: 3576 case e1000_80003es2lan: 3577 if (adapter->hw.bus.func == 1) { 3578 e1000_read_nvm(&adapter->hw, 3579 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3580 break; 3581 } else 3582 e1000_read_nvm(&adapter->hw, 3583 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3584 break; 3585 case e1000_ich8lan: 3586 case e1000_ich9lan: 3587 case e1000_ich10lan: 3588 case e1000_pchlan: 3589 case e1000_pch2lan: 3590 case e1000_pch_lpt: 3591 case e1000_pch_spt: 3592 case e1000_82575: /* listing all igb devices */ 3593 case e1000_82576: 3594 case e1000_82580: 3595 case e1000_i350: 3596 case e1000_i354: 3597 case e1000_i210: 3598 case e1000_i211: 3599 case e1000_vfadapt: 3600 case e1000_vfadapt_i350: 3601 apme_mask = E1000_WUC_APME; 3602 adapter->has_amt = TRUE; 3603 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3604 break; 3605 default: 3606 e1000_read_nvm(&adapter->hw, 3607 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3608 break; 3609 } 3610 if (eeprom_data & apme_mask) 3611 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3612 /* 3613 * We have the eeprom settings, now apply the special cases 3614 * where the eeprom may be wrong or the board won't support 3615 * wake on lan on a particular port 3616 */ 3617 device_id = pci_get_device(dev); 3618 switch (device_id) { 3619 case E1000_DEV_ID_82546GB_PCIE: 3620 adapter->wol = 0; 3621 break; 3622 case E1000_DEV_ID_82546EB_FIBER: 3623 case E1000_DEV_ID_82546GB_FIBER: 3624 /* Wake events only supported on port A for dual fiber 3625 * regardless of eeprom setting */ 3626 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3627 E1000_STATUS_FUNC_1) 3628 adapter->wol = 0; 3629 break; 3630 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3631 /* if quad port adapter, disable WoL on all but port A */ 3632 if (global_quad_port_a != 0) 3633 adapter->wol = 0; 3634 /* Reset for multiple quad port adapters */ 3635 if (++global_quad_port_a == 4) 3636 global_quad_port_a = 0; 3637 break; 3638 case E1000_DEV_ID_82571EB_FIBER: 3639 /* Wake events only supported on port A for dual fiber 3640 * regardless of eeprom setting */ 3641 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3642 E1000_STATUS_FUNC_1) 3643 adapter->wol = 0; 3644 break; 3645 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3646 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3647 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3648 /* if quad port adapter, disable WoL on all but port A */ 3649 if (global_quad_port_a != 0) 3650 adapter->wol = 0; 3651 /* Reset for multiple quad port adapters */ 3652 if (++global_quad_port_a == 4) 3653 global_quad_port_a = 0; 3654 break; 3655 } 3656 return; 3657 } 3658 3659 3660 /* 3661 * Enable PCI Wake On Lan capability 3662 */ 3663 static void 3664 em_enable_wakeup(if_ctx_t ctx) 3665 { 3666 struct adapter *adapter = iflib_get_softc(ctx); 3667 device_t dev = iflib_get_dev(ctx); 3668 if_t ifp = iflib_get_ifp(ctx); 3669 int error = 0; 3670 u32 pmc, ctrl, ctrl_ext, rctl; 3671 u16 status; 3672 3673 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3674 return; 3675 3676 /* 3677 * Determine type of Wakeup: note that wol 3678 * is set with all bits on by default. 3679 */ 3680 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3681 adapter->wol &= ~E1000_WUFC_MAG; 3682 3683 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3684 adapter->wol &= ~E1000_WUFC_EX; 3685 3686 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3687 adapter->wol &= ~E1000_WUFC_MC; 3688 else { 3689 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3690 rctl |= E1000_RCTL_MPE; 3691 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3692 } 3693 3694 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3695 goto pme; 3696 3697 /* Advertise the wakeup capability */ 3698 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3699 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3700 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3701 3702 /* Keep the laser running on Fiber adapters */ 3703 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3704 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3705 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3706 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3707 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3708 } 3709 3710 if ((adapter->hw.mac.type == e1000_ich8lan) || 3711 (adapter->hw.mac.type == e1000_pchlan) || 3712 (adapter->hw.mac.type == e1000_ich9lan) || 3713 (adapter->hw.mac.type == e1000_ich10lan)) 3714 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3715 3716 if ( adapter->hw.mac.type >= e1000_pchlan) { 3717 error = em_enable_phy_wakeup(adapter); 3718 if (error) 3719 goto pme; 3720 } else { 3721 /* Enable wakeup by the MAC */ 3722 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3723 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3724 } 3725 3726 if (adapter->hw.phy.type == e1000_phy_igp_3) 3727 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3728 3729 pme: 3730 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3731 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3732 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3733 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3734 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3735 3736 return; 3737 } 3738 3739 /* 3740 * WOL in the newer chipset interfaces (pchlan) 3741 * require thing to be copied into the phy 3742 */ 3743 static int 3744 em_enable_phy_wakeup(struct adapter *adapter) 3745 { 3746 struct e1000_hw *hw = &adapter->hw; 3747 u32 mreg, ret = 0; 3748 u16 preg; 3749 3750 /* copy MAC RARs to PHY RARs */ 3751 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3752 3753 /* copy MAC MTA to PHY MTA */ 3754 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3755 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3756 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3757 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3758 (u16)((mreg >> 16) & 0xFFFF)); 3759 } 3760 3761 /* configure PHY Rx Control register */ 3762 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3763 mreg = E1000_READ_REG(hw, E1000_RCTL); 3764 if (mreg & E1000_RCTL_UPE) 3765 preg |= BM_RCTL_UPE; 3766 if (mreg & E1000_RCTL_MPE) 3767 preg |= BM_RCTL_MPE; 3768 preg &= ~(BM_RCTL_MO_MASK); 3769 if (mreg & E1000_RCTL_MO_3) 3770 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3771 << BM_RCTL_MO_SHIFT); 3772 if (mreg & E1000_RCTL_BAM) 3773 preg |= BM_RCTL_BAM; 3774 if (mreg & E1000_RCTL_PMCF) 3775 preg |= BM_RCTL_PMCF; 3776 mreg = E1000_READ_REG(hw, E1000_CTRL); 3777 if (mreg & E1000_CTRL_RFCE) 3778 preg |= BM_RCTL_RFCE; 3779 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3780 3781 /* enable PHY wakeup in MAC register */ 3782 E1000_WRITE_REG(hw, E1000_WUC, 3783 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3784 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3785 3786 /* configure and enable PHY wakeup in PHY registers */ 3787 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3788 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3789 3790 /* activate PHY wakeup */ 3791 ret = hw->phy.ops.acquire(hw); 3792 if (ret) { 3793 printf("Could not acquire PHY\n"); 3794 return ret; 3795 } 3796 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3797 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3798 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3799 if (ret) { 3800 printf("Could not read PHY page 769\n"); 3801 goto out; 3802 } 3803 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3804 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3805 if (ret) 3806 printf("Could not set PHY Host Wakeup bit\n"); 3807 out: 3808 hw->phy.ops.release(hw); 3809 3810 return ret; 3811 } 3812 3813 static void 3814 em_if_led_func(if_ctx_t ctx, int onoff) 3815 { 3816 struct adapter *adapter = iflib_get_softc(ctx); 3817 3818 if (onoff) { 3819 e1000_setup_led(&adapter->hw); 3820 e1000_led_on(&adapter->hw); 3821 } else { 3822 e1000_led_off(&adapter->hw); 3823 e1000_cleanup_led(&adapter->hw); 3824 } 3825 } 3826 3827 /* 3828 * Disable the L0S and L1 LINK states 3829 */ 3830 static void 3831 em_disable_aspm(struct adapter *adapter) 3832 { 3833 int base, reg; 3834 u16 link_cap,link_ctrl; 3835 device_t dev = adapter->dev; 3836 3837 switch (adapter->hw.mac.type) { 3838 case e1000_82573: 3839 case e1000_82574: 3840 case e1000_82583: 3841 break; 3842 default: 3843 return; 3844 } 3845 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3846 return; 3847 reg = base + PCIER_LINK_CAP; 3848 link_cap = pci_read_config(dev, reg, 2); 3849 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3850 return; 3851 reg = base + PCIER_LINK_CTL; 3852 link_ctrl = pci_read_config(dev, reg, 2); 3853 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3854 pci_write_config(dev, reg, link_ctrl, 2); 3855 return; 3856 } 3857 3858 /********************************************************************** 3859 * 3860 * Update the board statistics counters. 3861 * 3862 **********************************************************************/ 3863 static void 3864 em_update_stats_counters(struct adapter *adapter) 3865 { 3866 3867 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3868 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3869 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3870 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3871 } 3872 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3873 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3874 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3875 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3876 3877 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3878 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3879 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3880 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3881 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3882 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3883 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3884 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3885 /* 3886 ** For watchdog management we need to know if we have been 3887 ** paused during the last interval, so capture that here. 3888 */ 3889 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3890 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3891 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3892 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3893 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3894 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3895 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3896 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3897 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3898 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3899 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3900 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3901 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3902 3903 /* For the 64-bit byte counters the low dword must be read first. */ 3904 /* Both registers clear on the read of the high dword */ 3905 3906 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3907 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3908 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3909 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3910 3911 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3912 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3913 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3914 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3915 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3916 3917 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3918 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3919 3920 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3921 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3922 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3923 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3924 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3925 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3926 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3927 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3928 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3929 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3930 3931 /* Interrupt Counts */ 3932 3933 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3934 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3935 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3936 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3937 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3938 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3939 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3940 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3941 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3942 3943 if (adapter->hw.mac.type >= e1000_82543) { 3944 adapter->stats.algnerrc += 3945 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3946 adapter->stats.rxerrc += 3947 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3948 adapter->stats.tncrs += 3949 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3950 adapter->stats.cexterr += 3951 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3952 adapter->stats.tsctc += 3953 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3954 adapter->stats.tsctfc += 3955 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3956 } 3957 } 3958 3959 static uint64_t 3960 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3961 { 3962 struct adapter *adapter = iflib_get_softc(ctx); 3963 struct ifnet *ifp = iflib_get_ifp(ctx); 3964 3965 switch (cnt) { 3966 case IFCOUNTER_COLLISIONS: 3967 return (adapter->stats.colc); 3968 case IFCOUNTER_IERRORS: 3969 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3970 adapter->stats.crcerrs + adapter->stats.algnerrc + 3971 adapter->stats.ruc + adapter->stats.roc + 3972 adapter->stats.mpc + adapter->stats.cexterr); 3973 case IFCOUNTER_OERRORS: 3974 return (adapter->stats.ecol + adapter->stats.latecol + 3975 adapter->watchdog_events); 3976 default: 3977 return (if_get_counter_default(ifp, cnt)); 3978 } 3979 } 3980 3981 /* Export a single 32-bit register via a read-only sysctl. */ 3982 static int 3983 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3984 { 3985 struct adapter *adapter; 3986 u_int val; 3987 3988 adapter = oidp->oid_arg1; 3989 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3990 return (sysctl_handle_int(oidp, &val, 0, req)); 3991 } 3992 3993 /* 3994 * Add sysctl variables, one per statistic, to the system. 3995 */ 3996 static void 3997 em_add_hw_stats(struct adapter *adapter) 3998 { 3999 device_t dev = iflib_get_dev(adapter->ctx); 4000 struct em_tx_queue *tx_que = adapter->tx_queues; 4001 struct em_rx_queue *rx_que = adapter->rx_queues; 4002 4003 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4004 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4005 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4006 struct e1000_hw_stats *stats = &adapter->stats; 4007 4008 struct sysctl_oid *stat_node, *queue_node, *int_node; 4009 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4010 4011 #define QUEUE_NAME_LEN 32 4012 char namebuf[QUEUE_NAME_LEN]; 4013 4014 /* Driver Statistics */ 4015 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4016 CTLFLAG_RD, &adapter->dropped_pkts, 4017 "Driver dropped packets"); 4018 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4019 CTLFLAG_RD, &adapter->link_irq, 4020 "Link MSIX IRQ Handled"); 4021 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4022 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4023 "Defragmenting mbuf chain failed"); 4024 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4025 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4026 "Driver tx dma failure in xmit"); 4027 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4028 CTLFLAG_RD, &adapter->rx_overruns, 4029 "RX overruns"); 4030 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4031 CTLFLAG_RD, &adapter->watchdog_events, 4032 "Watchdog timeouts"); 4033 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4034 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4035 em_sysctl_reg_handler, "IU", 4036 "Device Control Register"); 4037 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4038 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4039 em_sysctl_reg_handler, "IU", 4040 "Receiver Control Register"); 4041 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4042 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4043 "Flow Control High Watermark"); 4044 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4045 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4046 "Flow Control Low Watermark"); 4047 4048 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4049 struct tx_ring *txr = &tx_que->txr; 4050 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4051 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4052 CTLFLAG_RD, NULL, "TX Queue Name"); 4053 queue_list = SYSCTL_CHILDREN(queue_node); 4054 4055 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4056 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4057 E1000_TDH(txr->me), 4058 em_sysctl_reg_handler, "IU", 4059 "Transmit Descriptor Head"); 4060 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4061 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4062 E1000_TDT(txr->me), 4063 em_sysctl_reg_handler, "IU", 4064 "Transmit Descriptor Tail"); 4065 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4066 CTLFLAG_RD, &txr->tx_irq, 4067 "Queue MSI-X Transmit Interrupts"); 4068 } 4069 4070 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4071 struct rx_ring *rxr = &rx_que->rxr; 4072 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4073 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4074 CTLFLAG_RD, NULL, "RX Queue Name"); 4075 queue_list = SYSCTL_CHILDREN(queue_node); 4076 4077 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4078 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4079 E1000_RDH(rxr->me), 4080 em_sysctl_reg_handler, "IU", 4081 "Receive Descriptor Head"); 4082 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4083 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4084 E1000_RDT(rxr->me), 4085 em_sysctl_reg_handler, "IU", 4086 "Receive Descriptor Tail"); 4087 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4088 CTLFLAG_RD, &rxr->rx_irq, 4089 "Queue MSI-X Receive Interrupts"); 4090 } 4091 4092 /* MAC stats get their own sub node */ 4093 4094 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4095 CTLFLAG_RD, NULL, "Statistics"); 4096 stat_list = SYSCTL_CHILDREN(stat_node); 4097 4098 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4099 CTLFLAG_RD, &stats->ecol, 4100 "Excessive collisions"); 4101 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4102 CTLFLAG_RD, &stats->scc, 4103 "Single collisions"); 4104 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4105 CTLFLAG_RD, &stats->mcc, 4106 "Multiple collisions"); 4107 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4108 CTLFLAG_RD, &stats->latecol, 4109 "Late collisions"); 4110 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4111 CTLFLAG_RD, &stats->colc, 4112 "Collision Count"); 4113 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4114 CTLFLAG_RD, &adapter->stats.symerrs, 4115 "Symbol Errors"); 4116 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4117 CTLFLAG_RD, &adapter->stats.sec, 4118 "Sequence Errors"); 4119 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4120 CTLFLAG_RD, &adapter->stats.dc, 4121 "Defer Count"); 4122 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4123 CTLFLAG_RD, &adapter->stats.mpc, 4124 "Missed Packets"); 4125 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4126 CTLFLAG_RD, &adapter->stats.rnbc, 4127 "Receive No Buffers"); 4128 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4129 CTLFLAG_RD, &adapter->stats.ruc, 4130 "Receive Undersize"); 4131 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4132 CTLFLAG_RD, &adapter->stats.rfc, 4133 "Fragmented Packets Received "); 4134 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4135 CTLFLAG_RD, &adapter->stats.roc, 4136 "Oversized Packets Received"); 4137 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4138 CTLFLAG_RD, &adapter->stats.rjc, 4139 "Recevied Jabber"); 4140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4141 CTLFLAG_RD, &adapter->stats.rxerrc, 4142 "Receive Errors"); 4143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4144 CTLFLAG_RD, &adapter->stats.crcerrs, 4145 "CRC errors"); 4146 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4147 CTLFLAG_RD, &adapter->stats.algnerrc, 4148 "Alignment Errors"); 4149 /* On 82575 these are collision counts */ 4150 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4151 CTLFLAG_RD, &adapter->stats.cexterr, 4152 "Collision/Carrier extension errors"); 4153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4154 CTLFLAG_RD, &adapter->stats.xonrxc, 4155 "XON Received"); 4156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4157 CTLFLAG_RD, &adapter->stats.xontxc, 4158 "XON Transmitted"); 4159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4160 CTLFLAG_RD, &adapter->stats.xoffrxc, 4161 "XOFF Received"); 4162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4163 CTLFLAG_RD, &adapter->stats.xofftxc, 4164 "XOFF Transmitted"); 4165 4166 /* Packet Reception Stats */ 4167 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4168 CTLFLAG_RD, &adapter->stats.tpr, 4169 "Total Packets Received "); 4170 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4171 CTLFLAG_RD, &adapter->stats.gprc, 4172 "Good Packets Received"); 4173 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4174 CTLFLAG_RD, &adapter->stats.bprc, 4175 "Broadcast Packets Received"); 4176 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4177 CTLFLAG_RD, &adapter->stats.mprc, 4178 "Multicast Packets Received"); 4179 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4180 CTLFLAG_RD, &adapter->stats.prc64, 4181 "64 byte frames received "); 4182 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4183 CTLFLAG_RD, &adapter->stats.prc127, 4184 "65-127 byte frames received"); 4185 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4186 CTLFLAG_RD, &adapter->stats.prc255, 4187 "128-255 byte frames received"); 4188 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4189 CTLFLAG_RD, &adapter->stats.prc511, 4190 "256-511 byte frames received"); 4191 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4192 CTLFLAG_RD, &adapter->stats.prc1023, 4193 "512-1023 byte frames received"); 4194 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4195 CTLFLAG_RD, &adapter->stats.prc1522, 4196 "1023-1522 byte frames received"); 4197 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4198 CTLFLAG_RD, &adapter->stats.gorc, 4199 "Good Octets Received"); 4200 4201 /* Packet Transmission Stats */ 4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4203 CTLFLAG_RD, &adapter->stats.gotc, 4204 "Good Octets Transmitted"); 4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4206 CTLFLAG_RD, &adapter->stats.tpt, 4207 "Total Packets Transmitted"); 4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4209 CTLFLAG_RD, &adapter->stats.gptc, 4210 "Good Packets Transmitted"); 4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4212 CTLFLAG_RD, &adapter->stats.bptc, 4213 "Broadcast Packets Transmitted"); 4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4215 CTLFLAG_RD, &adapter->stats.mptc, 4216 "Multicast Packets Transmitted"); 4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4218 CTLFLAG_RD, &adapter->stats.ptc64, 4219 "64 byte frames transmitted "); 4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4221 CTLFLAG_RD, &adapter->stats.ptc127, 4222 "65-127 byte frames transmitted"); 4223 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4224 CTLFLAG_RD, &adapter->stats.ptc255, 4225 "128-255 byte frames transmitted"); 4226 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4227 CTLFLAG_RD, &adapter->stats.ptc511, 4228 "256-511 byte frames transmitted"); 4229 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4230 CTLFLAG_RD, &adapter->stats.ptc1023, 4231 "512-1023 byte frames transmitted"); 4232 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4233 CTLFLAG_RD, &adapter->stats.ptc1522, 4234 "1024-1522 byte frames transmitted"); 4235 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4236 CTLFLAG_RD, &adapter->stats.tsctc, 4237 "TSO Contexts Transmitted"); 4238 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4239 CTLFLAG_RD, &adapter->stats.tsctfc, 4240 "TSO Contexts Failed"); 4241 4242 4243 /* Interrupt Stats */ 4244 4245 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4246 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4247 int_list = SYSCTL_CHILDREN(int_node); 4248 4249 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4250 CTLFLAG_RD, &adapter->stats.iac, 4251 "Interrupt Assertion Count"); 4252 4253 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4254 CTLFLAG_RD, &adapter->stats.icrxptc, 4255 "Interrupt Cause Rx Pkt Timer Expire Count"); 4256 4257 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4258 CTLFLAG_RD, &adapter->stats.icrxatc, 4259 "Interrupt Cause Rx Abs Timer Expire Count"); 4260 4261 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4262 CTLFLAG_RD, &adapter->stats.ictxptc, 4263 "Interrupt Cause Tx Pkt Timer Expire Count"); 4264 4265 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4266 CTLFLAG_RD, &adapter->stats.ictxatc, 4267 "Interrupt Cause Tx Abs Timer Expire Count"); 4268 4269 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4270 CTLFLAG_RD, &adapter->stats.ictxqec, 4271 "Interrupt Cause Tx Queue Empty Count"); 4272 4273 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4274 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4275 "Interrupt Cause Tx Queue Min Thresh Count"); 4276 4277 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4278 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4279 "Interrupt Cause Rx Desc Min Thresh Count"); 4280 4281 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4282 CTLFLAG_RD, &adapter->stats.icrxoc, 4283 "Interrupt Cause Receiver Overrun Count"); 4284 } 4285 4286 /********************************************************************** 4287 * 4288 * This routine provides a way to dump out the adapter eeprom, 4289 * often a useful debug/service tool. This only dumps the first 4290 * 32 words, stuff that matters is in that extent. 4291 * 4292 **********************************************************************/ 4293 static int 4294 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4295 { 4296 struct adapter *adapter = (struct adapter *)arg1; 4297 int error; 4298 int result; 4299 4300 result = -1; 4301 error = sysctl_handle_int(oidp, &result, 0, req); 4302 4303 if (error || !req->newptr) 4304 return (error); 4305 4306 /* 4307 * This value will cause a hex dump of the 4308 * first 32 16-bit words of the EEPROM to 4309 * the screen. 4310 */ 4311 if (result == 1) 4312 em_print_nvm_info(adapter); 4313 4314 return (error); 4315 } 4316 4317 static void 4318 em_print_nvm_info(struct adapter *adapter) 4319 { 4320 u16 eeprom_data; 4321 int i, j, row = 0; 4322 4323 /* Its a bit crude, but it gets the job done */ 4324 printf("\nInterface EEPROM Dump:\n"); 4325 printf("Offset\n0x0000 "); 4326 for (i = 0, j = 0; i < 32; i++, j++) { 4327 if (j == 8) { /* Make the offset block */ 4328 j = 0; ++row; 4329 printf("\n0x00%x0 ",row); 4330 } 4331 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4332 printf("%04x ", eeprom_data); 4333 } 4334 printf("\n"); 4335 } 4336 4337 static int 4338 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4339 { 4340 struct em_int_delay_info *info; 4341 struct adapter *adapter; 4342 u32 regval; 4343 int error, usecs, ticks; 4344 4345 info = (struct em_int_delay_info *) arg1; 4346 usecs = info->value; 4347 error = sysctl_handle_int(oidp, &usecs, 0, req); 4348 if (error != 0 || req->newptr == NULL) 4349 return (error); 4350 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4351 return (EINVAL); 4352 info->value = usecs; 4353 ticks = EM_USECS_TO_TICKS(usecs); 4354 if (info->offset == E1000_ITR) /* units are 256ns here */ 4355 ticks *= 4; 4356 4357 adapter = info->adapter; 4358 4359 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4360 regval = (regval & ~0xffff) | (ticks & 0xffff); 4361 /* Handle a few special cases. */ 4362 switch (info->offset) { 4363 case E1000_RDTR: 4364 break; 4365 case E1000_TIDV: 4366 if (ticks == 0) { 4367 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4368 /* Don't write 0 into the TIDV register. */ 4369 regval++; 4370 } else 4371 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4372 break; 4373 } 4374 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4375 return (0); 4376 } 4377 4378 static void 4379 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4380 const char *description, struct em_int_delay_info *info, 4381 int offset, int value) 4382 { 4383 info->adapter = adapter; 4384 info->offset = offset; 4385 info->value = value; 4386 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4387 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4388 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4389 info, 0, em_sysctl_int_delay, "I", description); 4390 } 4391 4392 /* 4393 * Set flow control using sysctl: 4394 * Flow control values: 4395 * 0 - off 4396 * 1 - rx pause 4397 * 2 - tx pause 4398 * 3 - full 4399 */ 4400 static int 4401 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4402 { 4403 int error; 4404 static int input = 3; /* default is full */ 4405 struct adapter *adapter = (struct adapter *) arg1; 4406 4407 error = sysctl_handle_int(oidp, &input, 0, req); 4408 4409 if ((error) || (req->newptr == NULL)) 4410 return (error); 4411 4412 if (input == adapter->fc) /* no change? */ 4413 return (error); 4414 4415 switch (input) { 4416 case e1000_fc_rx_pause: 4417 case e1000_fc_tx_pause: 4418 case e1000_fc_full: 4419 case e1000_fc_none: 4420 adapter->hw.fc.requested_mode = input; 4421 adapter->fc = input; 4422 break; 4423 default: 4424 /* Do nothing */ 4425 return (error); 4426 } 4427 4428 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4429 e1000_force_mac_fc(&adapter->hw); 4430 return (error); 4431 } 4432 4433 /* 4434 * Manage Energy Efficient Ethernet: 4435 * Control values: 4436 * 0/1 - enabled/disabled 4437 */ 4438 static int 4439 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4440 { 4441 struct adapter *adapter = (struct adapter *) arg1; 4442 int error, value; 4443 4444 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4445 error = sysctl_handle_int(oidp, &value, 0, req); 4446 if (error || req->newptr == NULL) 4447 return (error); 4448 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4449 em_if_init(adapter->ctx); 4450 4451 return (0); 4452 } 4453 4454 static int 4455 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4456 { 4457 struct adapter *adapter; 4458 int error; 4459 int result; 4460 4461 result = -1; 4462 error = sysctl_handle_int(oidp, &result, 0, req); 4463 4464 if (error || !req->newptr) 4465 return (error); 4466 4467 if (result == 1) { 4468 adapter = (struct adapter *) arg1; 4469 em_print_debug_info(adapter); 4470 } 4471 4472 return (error); 4473 } 4474 4475 static int 4476 em_get_rs(SYSCTL_HANDLER_ARGS) 4477 { 4478 struct adapter *adapter = (struct adapter *) arg1; 4479 int error; 4480 int result; 4481 4482 result = 0; 4483 error = sysctl_handle_int(oidp, &result, 0, req); 4484 4485 if (error || !req->newptr || result != 1) 4486 return (error); 4487 em_dump_rs(adapter); 4488 4489 return (error); 4490 } 4491 4492 static void 4493 em_if_debug(if_ctx_t ctx) 4494 { 4495 em_dump_rs(iflib_get_softc(ctx)); 4496 } 4497 4498 /* 4499 * This routine is meant to be fluid, add whatever is 4500 * needed for debugging a problem. -jfv 4501 */ 4502 static void 4503 em_print_debug_info(struct adapter *adapter) 4504 { 4505 device_t dev = iflib_get_dev(adapter->ctx); 4506 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4507 struct tx_ring *txr = &adapter->tx_queues->txr; 4508 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4509 4510 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4511 printf("Interface is RUNNING "); 4512 else 4513 printf("Interface is NOT RUNNING\n"); 4514 4515 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4516 printf("and INACTIVE\n"); 4517 else 4518 printf("and ACTIVE\n"); 4519 4520 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4521 device_printf(dev, "TX Queue %d ------\n", i); 4522 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4523 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4524 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4525 4526 } 4527 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4528 device_printf(dev, "RX Queue %d ------\n", j); 4529 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4530 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4531 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4532 } 4533 } 4534 4535 /* 4536 * 82574 only: 4537 * Write a new value to the EEPROM increasing the number of MSIX 4538 * vectors from 3 to 5, for proper multiqueue support. 4539 */ 4540 static void 4541 em_enable_vectors_82574(if_ctx_t ctx) 4542 { 4543 struct adapter *adapter = iflib_get_softc(ctx); 4544 struct e1000_hw *hw = &adapter->hw; 4545 device_t dev = iflib_get_dev(ctx); 4546 u16 edata; 4547 4548 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4549 printf("Current cap: %#06x\n", edata); 4550 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4551 device_printf(dev, "Writing to eeprom: increasing " 4552 "reported MSIX vectors from 3 to 5...\n"); 4553 edata &= ~(EM_NVM_MSIX_N_MASK); 4554 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4555 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4556 e1000_update_nvm_checksum(hw); 4557 device_printf(dev, "Writing to eeprom: done\n"); 4558 } 4559 } 4560