1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 237 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 239 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 240 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 243 /* required last entry */ 244 PVID_END 245 }; 246 247 /********************************************************************* 248 * Function prototypes 249 *********************************************************************/ 250 static void *em_register(device_t dev); 251 static void *igb_register(device_t dev); 252 static int em_if_attach_pre(if_ctx_t ctx); 253 static int em_if_attach_post(if_ctx_t ctx); 254 static int em_if_detach(if_ctx_t ctx); 255 static int em_if_shutdown(if_ctx_t ctx); 256 static int em_if_suspend(if_ctx_t ctx); 257 static int em_if_resume(if_ctx_t ctx); 258 259 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 260 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 261 static void em_if_queues_free(if_ctx_t ctx); 262 263 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 264 static void em_if_init(if_ctx_t ctx); 265 static void em_if_stop(if_ctx_t ctx); 266 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 267 static int em_if_media_change(if_ctx_t ctx); 268 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 269 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 270 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 271 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 272 static void em_if_watchdog_reset(if_ctx_t ctx); 273 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 274 275 static void em_identify_hardware(if_ctx_t ctx); 276 static int em_allocate_pci_resources(if_ctx_t ctx); 277 static void em_free_pci_resources(if_ctx_t ctx); 278 static void em_reset(if_ctx_t ctx); 279 static int em_setup_interface(if_ctx_t ctx); 280 static int em_setup_msix(if_ctx_t ctx); 281 282 static void em_initialize_transmit_unit(if_ctx_t ctx); 283 static void em_initialize_receive_unit(if_ctx_t ctx); 284 285 static void em_if_intr_enable(if_ctx_t ctx); 286 static void em_if_intr_disable(if_ctx_t ctx); 287 static void igb_if_intr_enable(if_ctx_t ctx); 288 static void igb_if_intr_disable(if_ctx_t ctx); 289 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 290 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 291 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 292 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 293 static void em_if_multi_set(if_ctx_t ctx); 294 static void em_if_update_admin_status(if_ctx_t ctx); 295 static void em_if_debug(if_ctx_t ctx); 296 static void em_update_stats_counters(struct adapter *); 297 static void em_add_hw_stats(struct adapter *adapter); 298 static int em_if_set_promisc(if_ctx_t ctx, int flags); 299 static void em_setup_vlan_hw_support(struct adapter *); 300 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 301 static void em_print_nvm_info(struct adapter *); 302 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 303 static int em_get_rs(SYSCTL_HANDLER_ARGS); 304 static void em_print_debug_info(struct adapter *); 305 static int em_is_valid_ether_addr(u8 *); 306 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 307 static void em_add_int_delay_sysctl(struct adapter *, const char *, 308 const char *, struct em_int_delay_info *, int, int); 309 /* Management and WOL Support */ 310 static void em_init_manageability(struct adapter *); 311 static void em_release_manageability(struct adapter *); 312 static void em_get_hw_control(struct adapter *); 313 static void em_release_hw_control(struct adapter *); 314 static void em_get_wakeup(if_ctx_t ctx); 315 static void em_enable_wakeup(if_ctx_t ctx); 316 static int em_enable_phy_wakeup(struct adapter *); 317 static void em_disable_aspm(struct adapter *); 318 319 int em_intr(void *arg); 320 321 /* MSI-X handlers */ 322 static int em_if_msix_intr_assign(if_ctx_t, int); 323 static int em_msix_link(void *); 324 static void em_handle_link(void *context); 325 326 static void em_enable_vectors_82574(if_ctx_t); 327 328 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 330 static void em_if_led_func(if_ctx_t ctx, int onoff); 331 332 static int em_get_regs(SYSCTL_HANDLER_ARGS); 333 334 static void lem_smartspeed(struct adapter *adapter); 335 static void igb_configure_queues(struct adapter *adapter); 336 337 338 /********************************************************************* 339 * FreeBSD Device Interface Entry Points 340 *********************************************************************/ 341 static device_method_t em_methods[] = { 342 /* Device interface */ 343 DEVMETHOD(device_register, em_register), 344 DEVMETHOD(device_probe, iflib_device_probe), 345 DEVMETHOD(device_attach, iflib_device_attach), 346 DEVMETHOD(device_detach, iflib_device_detach), 347 DEVMETHOD(device_shutdown, iflib_device_shutdown), 348 DEVMETHOD(device_suspend, iflib_device_suspend), 349 DEVMETHOD(device_resume, iflib_device_resume), 350 DEVMETHOD_END 351 }; 352 353 static device_method_t igb_methods[] = { 354 /* Device interface */ 355 DEVMETHOD(device_register, igb_register), 356 DEVMETHOD(device_probe, iflib_device_probe), 357 DEVMETHOD(device_attach, iflib_device_attach), 358 DEVMETHOD(device_detach, iflib_device_detach), 359 DEVMETHOD(device_shutdown, iflib_device_shutdown), 360 DEVMETHOD(device_suspend, iflib_device_suspend), 361 DEVMETHOD(device_resume, iflib_device_resume), 362 DEVMETHOD_END 363 }; 364 365 366 static driver_t em_driver = { 367 "em", em_methods, sizeof(struct adapter), 368 }; 369 370 static devclass_t em_devclass; 371 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 372 373 MODULE_DEPEND(em, pci, 1, 1, 1); 374 MODULE_DEPEND(em, ether, 1, 1, 1); 375 MODULE_DEPEND(em, iflib, 1, 1, 1); 376 377 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 378 379 static driver_t igb_driver = { 380 "igb", igb_methods, sizeof(struct adapter), 381 }; 382 383 static devclass_t igb_devclass; 384 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 385 386 MODULE_DEPEND(igb, pci, 1, 1, 1); 387 MODULE_DEPEND(igb, ether, 1, 1, 1); 388 MODULE_DEPEND(igb, iflib, 1, 1, 1); 389 390 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 391 392 static device_method_t em_if_methods[] = { 393 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 394 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 395 DEVMETHOD(ifdi_detach, em_if_detach), 396 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 397 DEVMETHOD(ifdi_suspend, em_if_suspend), 398 DEVMETHOD(ifdi_resume, em_if_resume), 399 DEVMETHOD(ifdi_init, em_if_init), 400 DEVMETHOD(ifdi_stop, em_if_stop), 401 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 402 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 403 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 404 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 405 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 406 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 407 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 408 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 409 DEVMETHOD(ifdi_media_status, em_if_media_status), 410 DEVMETHOD(ifdi_media_change, em_if_media_change), 411 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 412 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 413 DEVMETHOD(ifdi_timer, em_if_timer), 414 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 415 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 416 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 417 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 418 DEVMETHOD(ifdi_led_func, em_if_led_func), 419 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 420 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 421 DEVMETHOD(ifdi_debug, em_if_debug), 422 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 423 DEVMETHOD_END 424 }; 425 426 static driver_t em_if_driver = { 427 "em_if", em_if_methods, sizeof(struct adapter) 428 }; 429 430 static device_method_t igb_if_methods[] = { 431 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 432 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 433 DEVMETHOD(ifdi_detach, em_if_detach), 434 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 435 DEVMETHOD(ifdi_suspend, em_if_suspend), 436 DEVMETHOD(ifdi_resume, em_if_resume), 437 DEVMETHOD(ifdi_init, em_if_init), 438 DEVMETHOD(ifdi_stop, em_if_stop), 439 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 440 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 441 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 442 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 443 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 444 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 445 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 446 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 447 DEVMETHOD(ifdi_media_status, em_if_media_status), 448 DEVMETHOD(ifdi_media_change, em_if_media_change), 449 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 450 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 451 DEVMETHOD(ifdi_timer, em_if_timer), 452 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 453 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 454 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 455 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 456 DEVMETHOD(ifdi_led_func, em_if_led_func), 457 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 458 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 459 DEVMETHOD(ifdi_debug, em_if_debug), 460 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 461 DEVMETHOD_END 462 }; 463 464 static driver_t igb_if_driver = { 465 "igb_if", igb_if_methods, sizeof(struct adapter) 466 }; 467 468 /********************************************************************* 469 * Tunable default values. 470 *********************************************************************/ 471 472 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 473 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 474 475 #define MAX_INTS_PER_SEC 8000 476 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 477 478 /* Allow common code without TSO */ 479 #ifndef CSUM_TSO 480 #define CSUM_TSO 0 481 #endif 482 483 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 484 "EM driver parameters"); 485 486 static int em_disable_crc_stripping = 0; 487 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 488 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 489 490 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 491 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 492 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 493 0, "Default transmit interrupt delay in usecs"); 494 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 495 0, "Default receive interrupt delay in usecs"); 496 497 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 498 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 499 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 500 &em_tx_abs_int_delay_dflt, 0, 501 "Default transmit interrupt delay limit in usecs"); 502 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 503 &em_rx_abs_int_delay_dflt, 0, 504 "Default receive interrupt delay limit in usecs"); 505 506 static int em_smart_pwr_down = FALSE; 507 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 508 0, "Set to true to leave smart power down enabled on newer adapters"); 509 510 /* Controls whether promiscuous also shows bad packets */ 511 static int em_debug_sbp = FALSE; 512 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 513 "Show bad packets in promiscuous mode"); 514 515 /* How many packets rxeof tries to clean at a time */ 516 static int em_rx_process_limit = 100; 517 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 518 &em_rx_process_limit, 0, 519 "Maximum number of received packets to process " 520 "at a time, -1 means unlimited"); 521 522 /* Energy efficient ethernet - default to OFF */ 523 static int eee_setting = 1; 524 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 525 "Enable Energy Efficient Ethernet"); 526 527 /* 528 ** Tuneable Interrupt rate 529 */ 530 static int em_max_interrupt_rate = 8000; 531 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 532 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 533 534 535 536 /* Global used in WOL setup with multiport cards */ 537 static int global_quad_port_a = 0; 538 539 extern struct if_txrx igb_txrx; 540 extern struct if_txrx em_txrx; 541 extern struct if_txrx lem_txrx; 542 543 static struct if_shared_ctx em_sctx_init = { 544 .isc_magic = IFLIB_MAGIC, 545 .isc_q_align = PAGE_SIZE, 546 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 547 .isc_tx_maxsegsize = PAGE_SIZE, 548 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 549 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 550 .isc_rx_maxsize = MJUM9BYTES, 551 .isc_rx_nsegments = 1, 552 .isc_rx_maxsegsize = MJUM9BYTES, 553 .isc_nfl = 1, 554 .isc_nrxqs = 1, 555 .isc_ntxqs = 1, 556 .isc_admin_intrcnt = 1, 557 .isc_vendor_info = em_vendor_info_array, 558 .isc_driver_version = em_driver_version, 559 .isc_driver = &em_if_driver, 560 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 561 562 .isc_nrxd_min = {EM_MIN_RXD}, 563 .isc_ntxd_min = {EM_MIN_TXD}, 564 .isc_nrxd_max = {EM_MAX_RXD}, 565 .isc_ntxd_max = {EM_MAX_TXD}, 566 .isc_nrxd_default = {EM_DEFAULT_RXD}, 567 .isc_ntxd_default = {EM_DEFAULT_TXD}, 568 }; 569 570 static struct if_shared_ctx igb_sctx_init = { 571 .isc_magic = IFLIB_MAGIC, 572 .isc_q_align = PAGE_SIZE, 573 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 574 .isc_tx_maxsegsize = PAGE_SIZE, 575 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 576 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 577 .isc_rx_maxsize = MJUM9BYTES, 578 .isc_rx_nsegments = 1, 579 .isc_rx_maxsegsize = MJUM9BYTES, 580 .isc_nfl = 1, 581 .isc_nrxqs = 1, 582 .isc_ntxqs = 1, 583 .isc_admin_intrcnt = 1, 584 .isc_vendor_info = igb_vendor_info_array, 585 .isc_driver_version = em_driver_version, 586 .isc_driver = &igb_if_driver, 587 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 588 589 .isc_nrxd_min = {EM_MIN_RXD}, 590 .isc_ntxd_min = {EM_MIN_TXD}, 591 .isc_nrxd_max = {IGB_MAX_RXD}, 592 .isc_ntxd_max = {IGB_MAX_TXD}, 593 .isc_nrxd_default = {EM_DEFAULT_RXD}, 594 .isc_ntxd_default = {EM_DEFAULT_TXD}, 595 }; 596 597 /***************************************************************** 598 * 599 * Dump Registers 600 * 601 ****************************************************************/ 602 #define IGB_REGS_LEN 739 603 604 static int em_get_regs(SYSCTL_HANDLER_ARGS) 605 { 606 struct adapter *adapter = (struct adapter *)arg1; 607 struct e1000_hw *hw = &adapter->hw; 608 struct sbuf *sb; 609 u32 *regs_buff; 610 int rc; 611 612 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 613 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 614 615 rc = sysctl_wire_old_buffer(req, 0); 616 MPASS(rc == 0); 617 if (rc != 0) { 618 free(regs_buff, M_DEVBUF); 619 return (rc); 620 } 621 622 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 623 MPASS(sb != NULL); 624 if (sb == NULL) { 625 free(regs_buff, M_DEVBUF); 626 return (ENOMEM); 627 } 628 629 /* General Registers */ 630 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 631 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 632 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 633 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 634 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 635 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 636 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 637 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 638 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 639 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 640 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 641 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 642 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 643 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 644 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 645 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 646 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 647 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 648 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 649 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 650 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 651 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 652 653 sbuf_printf(sb, "General Registers\n"); 654 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 655 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 656 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 657 658 sbuf_printf(sb, "Interrupt Registers\n"); 659 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 660 661 sbuf_printf(sb, "RX Registers\n"); 662 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 663 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 664 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 665 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 666 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 667 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 668 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 669 670 sbuf_printf(sb, "TX Registers\n"); 671 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 672 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 673 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 674 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 675 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 676 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 677 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 678 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 679 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 680 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 681 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 682 683 free(regs_buff, M_DEVBUF); 684 685 #ifdef DUMP_DESCS 686 { 687 if_softc_ctx_t scctx = adapter->shared; 688 struct rx_ring *rxr = &rx_que->rxr; 689 struct tx_ring *txr = &tx_que->txr; 690 int ntxd = scctx->isc_ntxd[0]; 691 int nrxd = scctx->isc_nrxd[0]; 692 int j; 693 694 for (j = 0; j < nrxd; j++) { 695 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 696 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 697 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 698 } 699 700 for (j = 0; j < min(ntxd, 256); j++) { 701 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 702 703 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 704 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 705 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 706 707 } 708 } 709 #endif 710 711 rc = sbuf_finish(sb); 712 sbuf_delete(sb); 713 return(rc); 714 } 715 716 static void * 717 em_register(device_t dev) 718 { 719 return (&em_sctx_init); 720 } 721 722 static void * 723 igb_register(device_t dev) 724 { 725 return (&igb_sctx_init); 726 } 727 728 static int 729 em_set_num_queues(if_ctx_t ctx) 730 { 731 struct adapter *adapter = iflib_get_softc(ctx); 732 int maxqueues; 733 734 /* Sanity check based on HW */ 735 switch (adapter->hw.mac.type) { 736 case e1000_82576: 737 case e1000_82580: 738 case e1000_i350: 739 case e1000_i354: 740 maxqueues = 8; 741 break; 742 case e1000_i210: 743 case e1000_82575: 744 maxqueues = 4; 745 break; 746 case e1000_i211: 747 case e1000_82574: 748 maxqueues = 2; 749 break; 750 default: 751 maxqueues = 1; 752 break; 753 } 754 755 return (maxqueues); 756 } 757 758 #define LEM_CAPS \ 759 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 760 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 761 762 #define EM_CAPS \ 763 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 764 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 765 IFCAP_LRO | IFCAP_VLAN_HWTSO 766 767 #define IGB_CAPS \ 768 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 769 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 770 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 771 IFCAP_TSO6 772 773 /********************************************************************* 774 * Device initialization routine 775 * 776 * The attach entry point is called when the driver is being loaded. 777 * This routine identifies the type of hardware, allocates all resources 778 * and initializes the hardware. 779 * 780 * return 0 on success, positive on failure 781 *********************************************************************/ 782 static int 783 em_if_attach_pre(if_ctx_t ctx) 784 { 785 struct adapter *adapter; 786 if_softc_ctx_t scctx; 787 device_t dev; 788 struct e1000_hw *hw; 789 int error = 0; 790 791 INIT_DEBUGOUT("em_if_attach_pre: begin"); 792 dev = iflib_get_dev(ctx); 793 adapter = iflib_get_softc(ctx); 794 795 adapter->ctx = adapter->osdep.ctx = ctx; 796 adapter->dev = adapter->osdep.dev = dev; 797 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 798 adapter->media = iflib_get_media(ctx); 799 hw = &adapter->hw; 800 801 adapter->tx_process_limit = scctx->isc_ntxd[0]; 802 803 /* SYSCTL stuff */ 804 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 805 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 806 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 807 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 808 809 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 810 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 811 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 812 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 813 814 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 815 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 816 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 817 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 818 819 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 820 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 821 OID_AUTO, "reg_dump", 822 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 823 em_get_regs, "A", "Dump Registers"); 824 825 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 826 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 827 OID_AUTO, "rs_dump", 828 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 829 em_get_rs, "I", "Dump RS indexes"); 830 831 /* Determine hardware and mac info */ 832 em_identify_hardware(ctx); 833 834 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 835 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 836 if (bootverbose) 837 device_printf(dev, "attach_pre capping queues at %d\n", 838 scctx->isc_ntxqsets_max); 839 840 if (hw->mac.type >= igb_mac_min) { 841 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 842 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 843 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 844 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 845 scctx->isc_txrx = &igb_txrx; 846 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 847 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 848 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 849 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 850 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 851 CSUM_IP6_TCP | CSUM_IP6_UDP; 852 if (hw->mac.type != e1000_82575) 853 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 854 /* 855 ** Some new devices, as with ixgbe, now may 856 ** use a different BAR, so we need to keep 857 ** track of which is used. 858 */ 859 scctx->isc_msix_bar = pci_msix_table_bar(dev); 860 } else if (hw->mac.type >= em_mac_min) { 861 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 862 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 863 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 864 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 865 scctx->isc_txrx = &em_txrx; 866 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 867 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 868 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 869 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 870 /* 871 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 872 * by default as we don't have workarounds for all associated 873 * silicon errata. E. g., with several MACs such as 82573E, 874 * TSO only works at Gigabit speed and otherwise can cause the 875 * hardware to hang (which also would be next to impossible to 876 * work around given that already queued TSO-using descriptors 877 * would need to be flushed and vlan(4) reconfigured at runtime 878 * in case of a link speed change). Moreover, MACs like 82579 879 * still can hang at Gigabit even with all publicly documented 880 * TSO workarounds implemented. Generally, the penality of 881 * these workarounds is rather high and may involve copying 882 * mbuf data around so advantages of TSO lapse. Still, TSO may 883 * work for a few MACs of this class - at least when sticking 884 * with Gigabit - in which case users may enable TSO manually. 885 */ 886 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 887 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 888 /* 889 * We support MSI-X with 82574 only, but indicate to iflib(4) 890 * that it shall give MSI at least a try with other devices. 891 */ 892 if (hw->mac.type == e1000_82574) { 893 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 894 } else { 895 scctx->isc_msix_bar = -1; 896 scctx->isc_disable_msix = 1; 897 } 898 } else { 899 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 900 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 901 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 902 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 903 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 904 scctx->isc_txrx = &lem_txrx; 905 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 906 if (hw->mac.type < e1000_82543) 907 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 908 /* INTx only */ 909 scctx->isc_msix_bar = 0; 910 } 911 912 /* Setup PCI resources */ 913 if (em_allocate_pci_resources(ctx)) { 914 device_printf(dev, "Allocation of PCI resources failed\n"); 915 error = ENXIO; 916 goto err_pci; 917 } 918 919 /* 920 ** For ICH8 and family we need to 921 ** map the flash memory, and this 922 ** must happen after the MAC is 923 ** identified 924 */ 925 if ((hw->mac.type == e1000_ich8lan) || 926 (hw->mac.type == e1000_ich9lan) || 927 (hw->mac.type == e1000_ich10lan) || 928 (hw->mac.type == e1000_pchlan) || 929 (hw->mac.type == e1000_pch2lan) || 930 (hw->mac.type == e1000_pch_lpt)) { 931 int rid = EM_BAR_TYPE_FLASH; 932 adapter->flash = bus_alloc_resource_any(dev, 933 SYS_RES_MEMORY, &rid, RF_ACTIVE); 934 if (adapter->flash == NULL) { 935 device_printf(dev, "Mapping of Flash failed\n"); 936 error = ENXIO; 937 goto err_pci; 938 } 939 /* This is used in the shared code */ 940 hw->flash_address = (u8 *)adapter->flash; 941 adapter->osdep.flash_bus_space_tag = 942 rman_get_bustag(adapter->flash); 943 adapter->osdep.flash_bus_space_handle = 944 rman_get_bushandle(adapter->flash); 945 } 946 /* 947 ** In the new SPT device flash is not a 948 ** separate BAR, rather it is also in BAR0, 949 ** so use the same tag and an offset handle for the 950 ** FLASH read/write macros in the shared code. 951 */ 952 else if (hw->mac.type >= e1000_pch_spt) { 953 adapter->osdep.flash_bus_space_tag = 954 adapter->osdep.mem_bus_space_tag; 955 adapter->osdep.flash_bus_space_handle = 956 adapter->osdep.mem_bus_space_handle 957 + E1000_FLASH_BASE_ADDR; 958 } 959 960 /* Do Shared Code initialization */ 961 error = e1000_setup_init_funcs(hw, TRUE); 962 if (error) { 963 device_printf(dev, "Setup of Shared code failed, error %d\n", 964 error); 965 error = ENXIO; 966 goto err_pci; 967 } 968 969 em_setup_msix(ctx); 970 e1000_get_bus_info(hw); 971 972 /* Set up some sysctls for the tunable interrupt delays */ 973 em_add_int_delay_sysctl(adapter, "rx_int_delay", 974 "receive interrupt delay in usecs", &adapter->rx_int_delay, 975 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 976 em_add_int_delay_sysctl(adapter, "tx_int_delay", 977 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 978 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 979 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 980 "receive interrupt delay limit in usecs", 981 &adapter->rx_abs_int_delay, 982 E1000_REGISTER(hw, E1000_RADV), 983 em_rx_abs_int_delay_dflt); 984 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 985 "transmit interrupt delay limit in usecs", 986 &adapter->tx_abs_int_delay, 987 E1000_REGISTER(hw, E1000_TADV), 988 em_tx_abs_int_delay_dflt); 989 em_add_int_delay_sysctl(adapter, "itr", 990 "interrupt delay limit in usecs/4", 991 &adapter->tx_itr, 992 E1000_REGISTER(hw, E1000_ITR), 993 DEFAULT_ITR); 994 995 hw->mac.autoneg = DO_AUTO_NEG; 996 hw->phy.autoneg_wait_to_complete = FALSE; 997 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 998 999 if (hw->mac.type < em_mac_min) { 1000 e1000_init_script_state_82541(hw, TRUE); 1001 e1000_set_tbi_compatibility_82543(hw, TRUE); 1002 } 1003 /* Copper options */ 1004 if (hw->phy.media_type == e1000_media_type_copper) { 1005 hw->phy.mdix = AUTO_ALL_MODES; 1006 hw->phy.disable_polarity_correction = FALSE; 1007 hw->phy.ms_type = EM_MASTER_SLAVE; 1008 } 1009 1010 /* 1011 * Set the frame limits assuming 1012 * standard ethernet sized frames. 1013 */ 1014 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1015 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1016 1017 /* 1018 * This controls when hardware reports transmit completion 1019 * status. 1020 */ 1021 hw->mac.report_tx_early = 1; 1022 1023 /* Allocate multicast array memory. */ 1024 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1025 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1026 if (adapter->mta == NULL) { 1027 device_printf(dev, "Can not allocate multicast setup array\n"); 1028 error = ENOMEM; 1029 goto err_late; 1030 } 1031 1032 /* Check SOL/IDER usage */ 1033 if (e1000_check_reset_block(hw)) 1034 device_printf(dev, "PHY reset is blocked" 1035 " due to SOL/IDER session.\n"); 1036 1037 /* Sysctl for setting Energy Efficient Ethernet */ 1038 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1039 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1040 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1041 OID_AUTO, "eee_control", 1042 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1043 adapter, 0, em_sysctl_eee, "I", 1044 "Disable Energy Efficient Ethernet"); 1045 1046 /* 1047 ** Start from a known state, this is 1048 ** important in reading the nvm and 1049 ** mac from that. 1050 */ 1051 e1000_reset_hw(hw); 1052 1053 /* Make sure we have a good EEPROM before we read from it */ 1054 if (e1000_validate_nvm_checksum(hw) < 0) { 1055 /* 1056 ** Some PCI-E parts fail the first check due to 1057 ** the link being in sleep state, call it again, 1058 ** if it fails a second time its a real issue. 1059 */ 1060 if (e1000_validate_nvm_checksum(hw) < 0) { 1061 device_printf(dev, 1062 "The EEPROM Checksum Is Not Valid\n"); 1063 error = EIO; 1064 goto err_late; 1065 } 1066 } 1067 1068 /* Copy the permanent MAC address out of the EEPROM */ 1069 if (e1000_read_mac_addr(hw) < 0) { 1070 device_printf(dev, "EEPROM read error while reading MAC" 1071 " address\n"); 1072 error = EIO; 1073 goto err_late; 1074 } 1075 1076 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1077 if (adapter->vf_ifp) { 1078 u8 addr[ETHER_ADDR_LEN]; 1079 arc4rand(&addr, sizeof(addr), 0); 1080 addr[0] &= 0xFE; 1081 addr[0] |= 0x02; 1082 bcopy(addr, hw->mac.addr, sizeof(addr)); 1083 } else { 1084 device_printf(dev, "Invalid MAC address\n"); 1085 error = EIO; 1086 goto err_late; 1087 } 1088 } 1089 1090 /* Disable ULP support */ 1091 e1000_disable_ulp_lpt_lp(hw, TRUE); 1092 1093 /* 1094 * Get Wake-on-Lan and Management info for later use 1095 */ 1096 em_get_wakeup(ctx); 1097 1098 /* Enable only WOL MAGIC by default */ 1099 scctx->isc_capenable &= ~IFCAP_WOL; 1100 if (adapter->wol != 0) 1101 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1102 1103 iflib_set_mac(ctx, hw->mac.addr); 1104 1105 return (0); 1106 1107 err_late: 1108 em_release_hw_control(adapter); 1109 err_pci: 1110 em_free_pci_resources(ctx); 1111 free(adapter->mta, M_DEVBUF); 1112 1113 return (error); 1114 } 1115 1116 static int 1117 em_if_attach_post(if_ctx_t ctx) 1118 { 1119 struct adapter *adapter = iflib_get_softc(ctx); 1120 struct e1000_hw *hw = &adapter->hw; 1121 int error = 0; 1122 1123 /* Setup OS specific network interface */ 1124 error = em_setup_interface(ctx); 1125 if (error != 0) { 1126 device_printf(adapter->dev, "Interface setup failed: %d\n", error); 1127 goto err_late; 1128 } 1129 1130 em_reset(ctx); 1131 1132 /* Initialize statistics */ 1133 em_update_stats_counters(adapter); 1134 hw->mac.get_link_status = 1; 1135 em_if_update_admin_status(ctx); 1136 em_add_hw_stats(adapter); 1137 1138 /* Non-AMT based hardware can now take control from firmware */ 1139 if (adapter->has_manage && !adapter->has_amt) 1140 em_get_hw_control(adapter); 1141 1142 INIT_DEBUGOUT("em_if_attach_post: end"); 1143 1144 return (0); 1145 1146 err_late: 1147 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1148 return (error); 1149 } 1150 1151 /********************************************************************* 1152 * Device removal routine 1153 * 1154 * The detach entry point is called when the driver is being removed. 1155 * This routine stops the adapter and deallocates all the resources 1156 * that were allocated for driver operation. 1157 * 1158 * return 0 on success, positive on failure 1159 *********************************************************************/ 1160 static int 1161 em_if_detach(if_ctx_t ctx) 1162 { 1163 struct adapter *adapter = iflib_get_softc(ctx); 1164 1165 INIT_DEBUGOUT("em_if_detach: begin"); 1166 1167 e1000_phy_hw_reset(&adapter->hw); 1168 1169 em_release_manageability(adapter); 1170 em_release_hw_control(adapter); 1171 em_free_pci_resources(ctx); 1172 free(adapter->mta, M_DEVBUF); 1173 adapter->mta = NULL; 1174 1175 return (0); 1176 } 1177 1178 /********************************************************************* 1179 * 1180 * Shutdown entry point 1181 * 1182 **********************************************************************/ 1183 1184 static int 1185 em_if_shutdown(if_ctx_t ctx) 1186 { 1187 return em_if_suspend(ctx); 1188 } 1189 1190 /* 1191 * Suspend/resume device methods. 1192 */ 1193 static int 1194 em_if_suspend(if_ctx_t ctx) 1195 { 1196 struct adapter *adapter = iflib_get_softc(ctx); 1197 1198 em_release_manageability(adapter); 1199 em_release_hw_control(adapter); 1200 em_enable_wakeup(ctx); 1201 return (0); 1202 } 1203 1204 static int 1205 em_if_resume(if_ctx_t ctx) 1206 { 1207 struct adapter *adapter = iflib_get_softc(ctx); 1208 1209 if (adapter->hw.mac.type == e1000_pch2lan) 1210 e1000_resume_workarounds_pchlan(&adapter->hw); 1211 em_if_init(ctx); 1212 em_init_manageability(adapter); 1213 1214 return(0); 1215 } 1216 1217 static int 1218 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1219 { 1220 int max_frame_size; 1221 struct adapter *adapter = iflib_get_softc(ctx); 1222 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1223 1224 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1225 1226 switch (adapter->hw.mac.type) { 1227 case e1000_82571: 1228 case e1000_82572: 1229 case e1000_ich9lan: 1230 case e1000_ich10lan: 1231 case e1000_pch2lan: 1232 case e1000_pch_lpt: 1233 case e1000_pch_spt: 1234 case e1000_pch_cnp: 1235 case e1000_pch_tgp: 1236 case e1000_pch_adp: 1237 case e1000_pch_mtp: 1238 case e1000_82574: 1239 case e1000_82583: 1240 case e1000_80003es2lan: 1241 /* 9K Jumbo Frame size */ 1242 max_frame_size = 9234; 1243 break; 1244 case e1000_pchlan: 1245 max_frame_size = 4096; 1246 break; 1247 case e1000_82542: 1248 case e1000_ich8lan: 1249 /* Adapters that do not support jumbo frames */ 1250 max_frame_size = ETHER_MAX_LEN; 1251 break; 1252 default: 1253 if (adapter->hw.mac.type >= igb_mac_min) 1254 max_frame_size = 9234; 1255 else /* lem */ 1256 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1257 } 1258 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1259 return (EINVAL); 1260 } 1261 1262 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1263 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1264 return (0); 1265 } 1266 1267 /********************************************************************* 1268 * Init entry point 1269 * 1270 * This routine is used in two ways. It is used by the stack as 1271 * init entry point in network interface structure. It is also used 1272 * by the driver as a hw/sw initialization routine to get to a 1273 * consistent state. 1274 * 1275 **********************************************************************/ 1276 static void 1277 em_if_init(if_ctx_t ctx) 1278 { 1279 struct adapter *adapter = iflib_get_softc(ctx); 1280 if_softc_ctx_t scctx = adapter->shared; 1281 struct ifnet *ifp = iflib_get_ifp(ctx); 1282 struct em_tx_queue *tx_que; 1283 int i; 1284 1285 INIT_DEBUGOUT("em_if_init: begin"); 1286 1287 /* Get the latest mac address, User can use a LAA */ 1288 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1289 ETHER_ADDR_LEN); 1290 1291 /* Put the address into the Receive Address Array */ 1292 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1293 1294 /* 1295 * With the 82571 adapter, RAR[0] may be overwritten 1296 * when the other port is reset, we make a duplicate 1297 * in RAR[14] for that eventuality, this assures 1298 * the interface continues to function. 1299 */ 1300 if (adapter->hw.mac.type == e1000_82571) { 1301 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1302 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1303 E1000_RAR_ENTRIES - 1); 1304 } 1305 1306 1307 /* Initialize the hardware */ 1308 em_reset(ctx); 1309 em_if_update_admin_status(ctx); 1310 1311 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1312 struct tx_ring *txr = &tx_que->txr; 1313 1314 txr->tx_rs_cidx = txr->tx_rs_pidx; 1315 1316 /* Initialize the last processed descriptor to be the end of 1317 * the ring, rather than the start, so that we avoid an 1318 * off-by-one error when calculating how many descriptors are 1319 * done in the credits_update function. 1320 */ 1321 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1322 } 1323 1324 /* Setup VLAN support, basic and offload if available */ 1325 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1326 1327 /* Clear bad data from Rx FIFOs */ 1328 if (adapter->hw.mac.type >= igb_mac_min) 1329 e1000_rx_fifo_flush_82575(&adapter->hw); 1330 1331 /* Configure for OS presence */ 1332 em_init_manageability(adapter); 1333 1334 /* Prepare transmit descriptors and buffers */ 1335 em_initialize_transmit_unit(ctx); 1336 1337 /* Setup Multicast table */ 1338 em_if_multi_set(ctx); 1339 1340 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1341 em_initialize_receive_unit(ctx); 1342 1343 /* Use real VLAN Filter support? */ 1344 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1345 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1346 /* Use real VLAN Filter support */ 1347 em_setup_vlan_hw_support(adapter); 1348 else { 1349 u32 ctrl; 1350 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1351 ctrl |= E1000_CTRL_VME; 1352 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1353 } 1354 } else { 1355 u32 ctrl; 1356 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1357 ctrl &= ~E1000_CTRL_VME; 1358 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1359 } 1360 1361 /* Don't lose promiscuous settings */ 1362 em_if_set_promisc(ctx, if_getflags(ifp)); 1363 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1364 1365 /* MSI-X configuration for 82574 */ 1366 if (adapter->hw.mac.type == e1000_82574) { 1367 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1368 1369 tmp |= E1000_CTRL_EXT_PBA_CLR; 1370 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1371 /* Set the IVAR - interrupt vector routing. */ 1372 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1373 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1374 igb_configure_queues(adapter); 1375 1376 /* this clears any pending interrupts */ 1377 E1000_READ_REG(&adapter->hw, E1000_ICR); 1378 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1379 1380 /* AMT based hardware can now take control from firmware */ 1381 if (adapter->has_manage && adapter->has_amt) 1382 em_get_hw_control(adapter); 1383 1384 /* Set Energy Efficient Ethernet */ 1385 if (adapter->hw.mac.type >= igb_mac_min && 1386 adapter->hw.phy.media_type == e1000_media_type_copper) { 1387 if (adapter->hw.mac.type == e1000_i354) 1388 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1389 else 1390 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1391 } 1392 } 1393 1394 /********************************************************************* 1395 * 1396 * Fast Legacy/MSI Combined Interrupt Service routine 1397 * 1398 *********************************************************************/ 1399 int 1400 em_intr(void *arg) 1401 { 1402 struct adapter *adapter = arg; 1403 if_ctx_t ctx = adapter->ctx; 1404 u32 reg_icr; 1405 1406 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1407 1408 /* Hot eject? */ 1409 if (reg_icr == 0xffffffff) 1410 return FILTER_STRAY; 1411 1412 /* Definitely not our interrupt. */ 1413 if (reg_icr == 0x0) 1414 return FILTER_STRAY; 1415 1416 /* 1417 * Starting with the 82571 chip, bit 31 should be used to 1418 * determine whether the interrupt belongs to us. 1419 */ 1420 if (adapter->hw.mac.type >= e1000_82571 && 1421 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1422 return FILTER_STRAY; 1423 1424 /* 1425 * Only MSI-X interrupts have one-shot behavior by taking advantage 1426 * of the EIAC register. Thus, explicitly disable interrupts. This 1427 * also works around the MSI message reordering errata on certain 1428 * systems. 1429 */ 1430 IFDI_INTR_DISABLE(ctx); 1431 1432 /* Link status change */ 1433 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1434 em_handle_link(ctx); 1435 1436 if (reg_icr & E1000_ICR_RXO) 1437 adapter->rx_overruns++; 1438 1439 return (FILTER_SCHEDULE_THREAD); 1440 } 1441 1442 static int 1443 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1444 { 1445 struct adapter *adapter = iflib_get_softc(ctx); 1446 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1447 1448 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1449 return (0); 1450 } 1451 1452 static int 1453 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1454 { 1455 struct adapter *adapter = iflib_get_softc(ctx); 1456 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1457 1458 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1459 return (0); 1460 } 1461 1462 static int 1463 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1464 { 1465 struct adapter *adapter = iflib_get_softc(ctx); 1466 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1467 1468 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1469 return (0); 1470 } 1471 1472 static int 1473 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1474 { 1475 struct adapter *adapter = iflib_get_softc(ctx); 1476 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1477 1478 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1479 return (0); 1480 } 1481 1482 /********************************************************************* 1483 * 1484 * MSI-X RX Interrupt Service routine 1485 * 1486 **********************************************************************/ 1487 static int 1488 em_msix_que(void *arg) 1489 { 1490 struct em_rx_queue *que = arg; 1491 1492 ++que->irqs; 1493 1494 return (FILTER_SCHEDULE_THREAD); 1495 } 1496 1497 /********************************************************************* 1498 * 1499 * MSI-X Link Fast Interrupt Service routine 1500 * 1501 **********************************************************************/ 1502 static int 1503 em_msix_link(void *arg) 1504 { 1505 struct adapter *adapter = arg; 1506 u32 reg_icr; 1507 bool notlink = false; 1508 1509 ++adapter->link_irq; 1510 MPASS(adapter->hw.back != NULL); 1511 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1512 1513 if (reg_icr & E1000_ICR_RXO) 1514 adapter->rx_overruns++; 1515 1516 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1517 em_handle_link(adapter->ctx); 1518 else 1519 notlink = true; 1520 1521 /* Re-arm for other/spurious interrupts */ 1522 if (notlink && adapter->hw.mac.type >= igb_mac_min) { 1523 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1524 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1525 } else if (adapter->hw.mac.type == e1000_82574) { 1526 if (notlink) 1527 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC | 1528 E1000_IMS_OTHER); 1529 /* 1530 * Because we must read the ICR for this interrupt it may 1531 * clear other causes using autoclear, for this reason we 1532 * simply create a soft interrupt for all these vectors. 1533 */ 1534 if (reg_icr) 1535 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1536 } 1537 1538 return (FILTER_HANDLED); 1539 } 1540 1541 static void 1542 em_handle_link(void *context) 1543 { 1544 if_ctx_t ctx = context; 1545 struct adapter *adapter = iflib_get_softc(ctx); 1546 1547 adapter->hw.mac.get_link_status = 1; 1548 iflib_admin_intr_deferred(ctx); 1549 } 1550 1551 /********************************************************************* 1552 * 1553 * Media Ioctl callback 1554 * 1555 * This routine is called whenever the user queries the status of 1556 * the interface using ifconfig. 1557 * 1558 **********************************************************************/ 1559 static void 1560 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1561 { 1562 struct adapter *adapter = iflib_get_softc(ctx); 1563 u_char fiber_type = IFM_1000_SX; 1564 1565 INIT_DEBUGOUT("em_if_media_status: begin"); 1566 1567 iflib_admin_intr_deferred(ctx); 1568 1569 ifmr->ifm_status = IFM_AVALID; 1570 ifmr->ifm_active = IFM_ETHER; 1571 1572 if (!adapter->link_active) { 1573 return; 1574 } 1575 1576 ifmr->ifm_status |= IFM_ACTIVE; 1577 1578 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1579 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1580 if (adapter->hw.mac.type == e1000_82545) 1581 fiber_type = IFM_1000_LX; 1582 ifmr->ifm_active |= fiber_type | IFM_FDX; 1583 } else { 1584 switch (adapter->link_speed) { 1585 case 10: 1586 ifmr->ifm_active |= IFM_10_T; 1587 break; 1588 case 100: 1589 ifmr->ifm_active |= IFM_100_TX; 1590 break; 1591 case 1000: 1592 ifmr->ifm_active |= IFM_1000_T; 1593 break; 1594 } 1595 if (adapter->link_duplex == FULL_DUPLEX) 1596 ifmr->ifm_active |= IFM_FDX; 1597 else 1598 ifmr->ifm_active |= IFM_HDX; 1599 } 1600 } 1601 1602 /********************************************************************* 1603 * 1604 * Media Ioctl callback 1605 * 1606 * This routine is called when the user changes speed/duplex using 1607 * media/mediopt option with ifconfig. 1608 * 1609 **********************************************************************/ 1610 static int 1611 em_if_media_change(if_ctx_t ctx) 1612 { 1613 struct adapter *adapter = iflib_get_softc(ctx); 1614 struct ifmedia *ifm = iflib_get_media(ctx); 1615 1616 INIT_DEBUGOUT("em_if_media_change: begin"); 1617 1618 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1619 return (EINVAL); 1620 1621 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1622 case IFM_AUTO: 1623 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1624 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1625 break; 1626 case IFM_1000_LX: 1627 case IFM_1000_SX: 1628 case IFM_1000_T: 1629 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1630 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1631 break; 1632 case IFM_100_TX: 1633 adapter->hw.mac.autoneg = FALSE; 1634 adapter->hw.phy.autoneg_advertised = 0; 1635 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1636 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1637 else 1638 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1639 break; 1640 case IFM_10_T: 1641 adapter->hw.mac.autoneg = FALSE; 1642 adapter->hw.phy.autoneg_advertised = 0; 1643 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1644 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1645 else 1646 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1647 break; 1648 default: 1649 device_printf(adapter->dev, "Unsupported media type\n"); 1650 } 1651 1652 em_if_init(ctx); 1653 1654 return (0); 1655 } 1656 1657 static int 1658 em_if_set_promisc(if_ctx_t ctx, int flags) 1659 { 1660 struct adapter *adapter = iflib_get_softc(ctx); 1661 struct ifnet *ifp = iflib_get_ifp(ctx); 1662 u32 reg_rctl; 1663 int mcnt = 0; 1664 1665 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1666 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1667 if (flags & IFF_ALLMULTI) 1668 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1669 else 1670 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1671 1672 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1673 reg_rctl &= (~E1000_RCTL_MPE); 1674 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1675 1676 if (flags & IFF_PROMISC) { 1677 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1678 /* Turn this on if you want to see bad packets */ 1679 if (em_debug_sbp) 1680 reg_rctl |= E1000_RCTL_SBP; 1681 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1682 } else if (flags & IFF_ALLMULTI) { 1683 reg_rctl |= E1000_RCTL_MPE; 1684 reg_rctl &= ~E1000_RCTL_UPE; 1685 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1686 } 1687 return (0); 1688 } 1689 1690 static u_int 1691 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1692 { 1693 u8 *mta = arg; 1694 1695 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1696 return (0); 1697 1698 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1699 1700 return (1); 1701 } 1702 1703 /********************************************************************* 1704 * Multicast Update 1705 * 1706 * This routine is called whenever multicast address list is updated. 1707 * 1708 **********************************************************************/ 1709 static void 1710 em_if_multi_set(if_ctx_t ctx) 1711 { 1712 struct adapter *adapter = iflib_get_softc(ctx); 1713 struct ifnet *ifp = iflib_get_ifp(ctx); 1714 u8 *mta; /* Multicast array memory */ 1715 u32 reg_rctl = 0; 1716 int mcnt = 0; 1717 1718 IOCTL_DEBUGOUT("em_set_multi: begin"); 1719 1720 mta = adapter->mta; 1721 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1722 1723 if (adapter->hw.mac.type == e1000_82542 && 1724 adapter->hw.revision_id == E1000_REVISION_2) { 1725 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1726 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1727 e1000_pci_clear_mwi(&adapter->hw); 1728 reg_rctl |= E1000_RCTL_RST; 1729 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1730 msec_delay(5); 1731 } 1732 1733 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1734 1735 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1736 1737 if (if_getflags(ifp) & IFF_PROMISC) 1738 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1739 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1740 if_getflags(ifp) & IFF_ALLMULTI) { 1741 reg_rctl |= E1000_RCTL_MPE; 1742 reg_rctl &= ~E1000_RCTL_UPE; 1743 } else 1744 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1745 1746 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1747 1748 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1749 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1750 1751 if (adapter->hw.mac.type == e1000_82542 && 1752 adapter->hw.revision_id == E1000_REVISION_2) { 1753 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1754 reg_rctl &= ~E1000_RCTL_RST; 1755 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1756 msec_delay(5); 1757 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1758 e1000_pci_set_mwi(&adapter->hw); 1759 } 1760 } 1761 1762 /********************************************************************* 1763 * Timer routine 1764 * 1765 * This routine schedules em_if_update_admin_status() to check for 1766 * link status and to gather statistics as well as to perform some 1767 * controller-specific hardware patting. 1768 * 1769 **********************************************************************/ 1770 static void 1771 em_if_timer(if_ctx_t ctx, uint16_t qid) 1772 { 1773 1774 if (qid != 0) 1775 return; 1776 1777 iflib_admin_intr_deferred(ctx); 1778 } 1779 1780 static void 1781 em_if_update_admin_status(if_ctx_t ctx) 1782 { 1783 struct adapter *adapter = iflib_get_softc(ctx); 1784 struct e1000_hw *hw = &adapter->hw; 1785 device_t dev = iflib_get_dev(ctx); 1786 u32 link_check, thstat, ctrl; 1787 1788 link_check = thstat = ctrl = 0; 1789 /* Get the cached link value or read phy for real */ 1790 switch (hw->phy.media_type) { 1791 case e1000_media_type_copper: 1792 if (hw->mac.get_link_status) { 1793 if (hw->mac.type == e1000_pch_spt) 1794 msec_delay(50); 1795 /* Do the work to read phy */ 1796 e1000_check_for_link(hw); 1797 link_check = !hw->mac.get_link_status; 1798 if (link_check) /* ESB2 fix */ 1799 e1000_cfg_on_link_up(hw); 1800 } else { 1801 link_check = TRUE; 1802 } 1803 break; 1804 case e1000_media_type_fiber: 1805 e1000_check_for_link(hw); 1806 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1807 E1000_STATUS_LU); 1808 break; 1809 case e1000_media_type_internal_serdes: 1810 e1000_check_for_link(hw); 1811 link_check = hw->mac.serdes_has_link; 1812 break; 1813 /* VF device is type_unknown */ 1814 case e1000_media_type_unknown: 1815 e1000_check_for_link(hw); 1816 link_check = !hw->mac.get_link_status; 1817 /* FALLTHROUGH */ 1818 default: 1819 break; 1820 } 1821 1822 /* Check for thermal downshift or shutdown */ 1823 if (hw->mac.type == e1000_i350) { 1824 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1825 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1826 } 1827 1828 /* Now check for a transition */ 1829 if (link_check && (adapter->link_active == 0)) { 1830 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1831 &adapter->link_duplex); 1832 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1833 if ((adapter->link_speed != SPEED_1000) && 1834 ((hw->mac.type == e1000_82571) || 1835 (hw->mac.type == e1000_82572))) { 1836 int tarc0; 1837 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1838 tarc0 &= ~TARC_SPEED_MODE_BIT; 1839 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1840 } 1841 if (bootverbose) 1842 device_printf(dev, "Link is up %d Mbps %s\n", 1843 adapter->link_speed, 1844 ((adapter->link_duplex == FULL_DUPLEX) ? 1845 "Full Duplex" : "Half Duplex")); 1846 adapter->link_active = 1; 1847 adapter->smartspeed = 0; 1848 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1849 E1000_CTRL_EXT_LINK_MODE_GMII && 1850 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1851 device_printf(dev, "Link: thermal downshift\n"); 1852 /* Delay Link Up for Phy update */ 1853 if (((hw->mac.type == e1000_i210) || 1854 (hw->mac.type == e1000_i211)) && 1855 (hw->phy.id == I210_I_PHY_ID)) 1856 msec_delay(I210_LINK_DELAY); 1857 /* Reset if the media type changed. */ 1858 if (hw->dev_spec._82575.media_changed && 1859 hw->mac.type >= igb_mac_min) { 1860 hw->dev_spec._82575.media_changed = false; 1861 adapter->flags |= IGB_MEDIA_RESET; 1862 em_reset(ctx); 1863 } 1864 iflib_link_state_change(ctx, LINK_STATE_UP, 1865 IF_Mbps(adapter->link_speed)); 1866 } else if (!link_check && (adapter->link_active == 1)) { 1867 adapter->link_speed = 0; 1868 adapter->link_duplex = 0; 1869 adapter->link_active = 0; 1870 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1871 } 1872 em_update_stats_counters(adapter); 1873 1874 /* Reset LAA into RAR[0] on 82571 */ 1875 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1876 e1000_rar_set(hw, hw->mac.addr, 0); 1877 1878 if (hw->mac.type < em_mac_min) 1879 lem_smartspeed(adapter); 1880 else if (hw->mac.type >= igb_mac_min && 1881 adapter->intr_type == IFLIB_INTR_MSIX) { 1882 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1883 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1884 } else if (hw->mac.type == e1000_82574 && 1885 adapter->intr_type == IFLIB_INTR_MSIX) 1886 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1887 } 1888 1889 static void 1890 em_if_watchdog_reset(if_ctx_t ctx) 1891 { 1892 struct adapter *adapter = iflib_get_softc(ctx); 1893 1894 /* 1895 * Just count the event; iflib(4) will already trigger a 1896 * sufficient reset of the controller. 1897 */ 1898 adapter->watchdog_events++; 1899 } 1900 1901 /********************************************************************* 1902 * 1903 * This routine disables all traffic on the adapter by issuing a 1904 * global reset on the MAC. 1905 * 1906 **********************************************************************/ 1907 static void 1908 em_if_stop(if_ctx_t ctx) 1909 { 1910 struct adapter *adapter = iflib_get_softc(ctx); 1911 1912 INIT_DEBUGOUT("em_if_stop: begin"); 1913 1914 e1000_reset_hw(&adapter->hw); 1915 if (adapter->hw.mac.type >= e1000_82544) 1916 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1917 1918 e1000_led_off(&adapter->hw); 1919 e1000_cleanup_led(&adapter->hw); 1920 } 1921 1922 /********************************************************************* 1923 * 1924 * Determine hardware revision. 1925 * 1926 **********************************************************************/ 1927 static void 1928 em_identify_hardware(if_ctx_t ctx) 1929 { 1930 device_t dev = iflib_get_dev(ctx); 1931 struct adapter *adapter = iflib_get_softc(ctx); 1932 1933 /* Make sure our PCI config space has the necessary stuff set */ 1934 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1935 1936 /* Save off the information about this board */ 1937 adapter->hw.vendor_id = pci_get_vendor(dev); 1938 adapter->hw.device_id = pci_get_device(dev); 1939 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1940 adapter->hw.subsystem_vendor_id = 1941 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1942 adapter->hw.subsystem_device_id = 1943 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1944 1945 /* Do Shared Code Init and Setup */ 1946 if (e1000_set_mac_type(&adapter->hw)) { 1947 device_printf(dev, "Setup init failure\n"); 1948 return; 1949 } 1950 1951 /* Are we a VF device? */ 1952 if ((adapter->hw.mac.type == e1000_vfadapt) || 1953 (adapter->hw.mac.type == e1000_vfadapt_i350)) 1954 adapter->vf_ifp = 1; 1955 else 1956 adapter->vf_ifp = 0; 1957 } 1958 1959 static int 1960 em_allocate_pci_resources(if_ctx_t ctx) 1961 { 1962 struct adapter *adapter = iflib_get_softc(ctx); 1963 device_t dev = iflib_get_dev(ctx); 1964 int rid, val; 1965 1966 rid = PCIR_BAR(0); 1967 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1968 &rid, RF_ACTIVE); 1969 if (adapter->memory == NULL) { 1970 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1971 return (ENXIO); 1972 } 1973 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1974 adapter->osdep.mem_bus_space_handle = 1975 rman_get_bushandle(adapter->memory); 1976 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1977 1978 /* Only older adapters use IO mapping */ 1979 if (adapter->hw.mac.type < em_mac_min && 1980 adapter->hw.mac.type > e1000_82543) { 1981 /* Figure our where our IO BAR is ? */ 1982 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1983 val = pci_read_config(dev, rid, 4); 1984 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1985 break; 1986 } 1987 rid += 4; 1988 /* check for 64bit BAR */ 1989 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1990 rid += 4; 1991 } 1992 if (rid >= PCIR_CIS) { 1993 device_printf(dev, "Unable to locate IO BAR\n"); 1994 return (ENXIO); 1995 } 1996 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1997 &rid, RF_ACTIVE); 1998 if (adapter->ioport == NULL) { 1999 device_printf(dev, "Unable to allocate bus resource: " 2000 "ioport\n"); 2001 return (ENXIO); 2002 } 2003 adapter->hw.io_base = 0; 2004 adapter->osdep.io_bus_space_tag = 2005 rman_get_bustag(adapter->ioport); 2006 adapter->osdep.io_bus_space_handle = 2007 rman_get_bushandle(adapter->ioport); 2008 } 2009 2010 adapter->hw.back = &adapter->osdep; 2011 2012 return (0); 2013 } 2014 2015 /********************************************************************* 2016 * 2017 * Set up the MSI-X Interrupt handlers 2018 * 2019 **********************************************************************/ 2020 static int 2021 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2022 { 2023 struct adapter *adapter = iflib_get_softc(ctx); 2024 struct em_rx_queue *rx_que = adapter->rx_queues; 2025 struct em_tx_queue *tx_que = adapter->tx_queues; 2026 int error, rid, i, vector = 0, rx_vectors; 2027 char buf[16]; 2028 2029 /* First set up ring resources */ 2030 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2031 rid = vector + 1; 2032 snprintf(buf, sizeof(buf), "rxq%d", i); 2033 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2034 if (error) { 2035 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2036 adapter->rx_num_queues = i + 1; 2037 goto fail; 2038 } 2039 2040 rx_que->msix = vector; 2041 2042 /* 2043 * Set the bit to enable interrupt 2044 * in E1000_IMS -- bits 20 and 21 2045 * are for RX0 and RX1, note this has 2046 * NOTHING to do with the MSI-X vector 2047 */ 2048 if (adapter->hw.mac.type == e1000_82574) { 2049 rx_que->eims = 1 << (20 + i); 2050 adapter->ims |= rx_que->eims; 2051 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2052 } else if (adapter->hw.mac.type == e1000_82575) 2053 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2054 else 2055 rx_que->eims = 1 << vector; 2056 } 2057 rx_vectors = vector; 2058 2059 vector = 0; 2060 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2061 snprintf(buf, sizeof(buf), "txq%d", i); 2062 tx_que = &adapter->tx_queues[i]; 2063 iflib_softirq_alloc_generic(ctx, 2064 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2065 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2066 2067 tx_que->msix = (vector % adapter->rx_num_queues); 2068 2069 /* 2070 * Set the bit to enable interrupt 2071 * in E1000_IMS -- bits 22 and 23 2072 * are for TX0 and TX1, note this has 2073 * NOTHING to do with the MSI-X vector 2074 */ 2075 if (adapter->hw.mac.type == e1000_82574) { 2076 tx_que->eims = 1 << (22 + i); 2077 adapter->ims |= tx_que->eims; 2078 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2079 } else if (adapter->hw.mac.type == e1000_82575) { 2080 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2081 } else { 2082 tx_que->eims = 1 << i; 2083 } 2084 } 2085 2086 /* Link interrupt */ 2087 rid = rx_vectors + 1; 2088 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2089 2090 if (error) { 2091 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2092 goto fail; 2093 } 2094 adapter->linkvec = rx_vectors; 2095 if (adapter->hw.mac.type < igb_mac_min) { 2096 adapter->ivars |= (8 | rx_vectors) << 16; 2097 adapter->ivars |= 0x80000000; 2098 /* Enable the "Other" interrupt type for link status change */ 2099 adapter->ims |= E1000_IMS_OTHER; 2100 } 2101 2102 return (0); 2103 fail: 2104 iflib_irq_free(ctx, &adapter->irq); 2105 rx_que = adapter->rx_queues; 2106 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2107 iflib_irq_free(ctx, &rx_que->que_irq); 2108 return (error); 2109 } 2110 2111 static void 2112 igb_configure_queues(struct adapter *adapter) 2113 { 2114 struct e1000_hw *hw = &adapter->hw; 2115 struct em_rx_queue *rx_que; 2116 struct em_tx_queue *tx_que; 2117 u32 tmp, ivar = 0, newitr = 0; 2118 2119 /* First turn on RSS capability */ 2120 if (hw->mac.type != e1000_82575) 2121 E1000_WRITE_REG(hw, E1000_GPIE, 2122 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2123 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2124 2125 /* Turn on MSI-X */ 2126 switch (hw->mac.type) { 2127 case e1000_82580: 2128 case e1000_i350: 2129 case e1000_i354: 2130 case e1000_i210: 2131 case e1000_i211: 2132 case e1000_vfadapt: 2133 case e1000_vfadapt_i350: 2134 /* RX entries */ 2135 for (int i = 0; i < adapter->rx_num_queues; i++) { 2136 u32 index = i >> 1; 2137 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2138 rx_que = &adapter->rx_queues[i]; 2139 if (i & 1) { 2140 ivar &= 0xFF00FFFF; 2141 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2142 } else { 2143 ivar &= 0xFFFFFF00; 2144 ivar |= rx_que->msix | E1000_IVAR_VALID; 2145 } 2146 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2147 } 2148 /* TX entries */ 2149 for (int i = 0; i < adapter->tx_num_queues; i++) { 2150 u32 index = i >> 1; 2151 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2152 tx_que = &adapter->tx_queues[i]; 2153 if (i & 1) { 2154 ivar &= 0x00FFFFFF; 2155 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2156 } else { 2157 ivar &= 0xFFFF00FF; 2158 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2159 } 2160 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2161 adapter->que_mask |= tx_que->eims; 2162 } 2163 2164 /* And for the link interrupt */ 2165 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2166 adapter->link_mask = 1 << adapter->linkvec; 2167 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2168 break; 2169 case e1000_82576: 2170 /* RX entries */ 2171 for (int i = 0; i < adapter->rx_num_queues; i++) { 2172 u32 index = i & 0x7; /* Each IVAR has two entries */ 2173 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2174 rx_que = &adapter->rx_queues[i]; 2175 if (i < 8) { 2176 ivar &= 0xFFFFFF00; 2177 ivar |= rx_que->msix | E1000_IVAR_VALID; 2178 } else { 2179 ivar &= 0xFF00FFFF; 2180 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2181 } 2182 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2183 adapter->que_mask |= rx_que->eims; 2184 } 2185 /* TX entries */ 2186 for (int i = 0; i < adapter->tx_num_queues; i++) { 2187 u32 index = i & 0x7; /* Each IVAR has two entries */ 2188 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2189 tx_que = &adapter->tx_queues[i]; 2190 if (i < 8) { 2191 ivar &= 0xFFFF00FF; 2192 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2193 } else { 2194 ivar &= 0x00FFFFFF; 2195 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2196 } 2197 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2198 adapter->que_mask |= tx_que->eims; 2199 } 2200 2201 /* And for the link interrupt */ 2202 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2203 adapter->link_mask = 1 << adapter->linkvec; 2204 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2205 break; 2206 2207 case e1000_82575: 2208 /* enable MSI-X support*/ 2209 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2210 tmp |= E1000_CTRL_EXT_PBA_CLR; 2211 /* Auto-Mask interrupts upon ICR read. */ 2212 tmp |= E1000_CTRL_EXT_EIAME; 2213 tmp |= E1000_CTRL_EXT_IRCA; 2214 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2215 2216 /* Queues */ 2217 for (int i = 0; i < adapter->rx_num_queues; i++) { 2218 rx_que = &adapter->rx_queues[i]; 2219 tmp = E1000_EICR_RX_QUEUE0 << i; 2220 tmp |= E1000_EICR_TX_QUEUE0 << i; 2221 rx_que->eims = tmp; 2222 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2223 i, rx_que->eims); 2224 adapter->que_mask |= rx_que->eims; 2225 } 2226 2227 /* Link */ 2228 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2229 E1000_EIMS_OTHER); 2230 adapter->link_mask |= E1000_EIMS_OTHER; 2231 default: 2232 break; 2233 } 2234 2235 /* Set the starting interrupt rate */ 2236 if (em_max_interrupt_rate > 0) 2237 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2238 2239 if (hw->mac.type == e1000_82575) 2240 newitr |= newitr << 16; 2241 else 2242 newitr |= E1000_EITR_CNT_IGNR; 2243 2244 for (int i = 0; i < adapter->rx_num_queues; i++) { 2245 rx_que = &adapter->rx_queues[i]; 2246 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2247 } 2248 2249 return; 2250 } 2251 2252 static void 2253 em_free_pci_resources(if_ctx_t ctx) 2254 { 2255 struct adapter *adapter = iflib_get_softc(ctx); 2256 struct em_rx_queue *que = adapter->rx_queues; 2257 device_t dev = iflib_get_dev(ctx); 2258 2259 /* Release all MSI-X queue resources */ 2260 if (adapter->intr_type == IFLIB_INTR_MSIX) 2261 iflib_irq_free(ctx, &adapter->irq); 2262 2263 if (que != NULL) { 2264 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2265 iflib_irq_free(ctx, &que->que_irq); 2266 } 2267 } 2268 2269 if (adapter->memory != NULL) { 2270 bus_release_resource(dev, SYS_RES_MEMORY, 2271 rman_get_rid(adapter->memory), adapter->memory); 2272 adapter->memory = NULL; 2273 } 2274 2275 if (adapter->flash != NULL) { 2276 bus_release_resource(dev, SYS_RES_MEMORY, 2277 rman_get_rid(adapter->flash), adapter->flash); 2278 adapter->flash = NULL; 2279 } 2280 2281 if (adapter->ioport != NULL) { 2282 bus_release_resource(dev, SYS_RES_IOPORT, 2283 rman_get_rid(adapter->ioport), adapter->ioport); 2284 adapter->ioport = NULL; 2285 } 2286 } 2287 2288 /* Set up MSI or MSI-X */ 2289 static int 2290 em_setup_msix(if_ctx_t ctx) 2291 { 2292 struct adapter *adapter = iflib_get_softc(ctx); 2293 2294 if (adapter->hw.mac.type == e1000_82574) { 2295 em_enable_vectors_82574(ctx); 2296 } 2297 return (0); 2298 } 2299 2300 /********************************************************************* 2301 * 2302 * Workaround for SmartSpeed on 82541 and 82547 controllers 2303 * 2304 **********************************************************************/ 2305 static void 2306 lem_smartspeed(struct adapter *adapter) 2307 { 2308 u16 phy_tmp; 2309 2310 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2311 adapter->hw.mac.autoneg == 0 || 2312 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2313 return; 2314 2315 if (adapter->smartspeed == 0) { 2316 /* If Master/Slave config fault is asserted twice, 2317 * we assume back-to-back */ 2318 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2319 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2320 return; 2321 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2322 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2323 e1000_read_phy_reg(&adapter->hw, 2324 PHY_1000T_CTRL, &phy_tmp); 2325 if(phy_tmp & CR_1000T_MS_ENABLE) { 2326 phy_tmp &= ~CR_1000T_MS_ENABLE; 2327 e1000_write_phy_reg(&adapter->hw, 2328 PHY_1000T_CTRL, phy_tmp); 2329 adapter->smartspeed++; 2330 if(adapter->hw.mac.autoneg && 2331 !e1000_copper_link_autoneg(&adapter->hw) && 2332 !e1000_read_phy_reg(&adapter->hw, 2333 PHY_CONTROL, &phy_tmp)) { 2334 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2335 MII_CR_RESTART_AUTO_NEG); 2336 e1000_write_phy_reg(&adapter->hw, 2337 PHY_CONTROL, phy_tmp); 2338 } 2339 } 2340 } 2341 return; 2342 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2343 /* If still no link, perhaps using 2/3 pair cable */ 2344 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2345 phy_tmp |= CR_1000T_MS_ENABLE; 2346 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2347 if(adapter->hw.mac.autoneg && 2348 !e1000_copper_link_autoneg(&adapter->hw) && 2349 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2350 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2351 MII_CR_RESTART_AUTO_NEG); 2352 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2353 } 2354 } 2355 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2356 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2357 adapter->smartspeed = 0; 2358 } 2359 2360 /********************************************************************* 2361 * 2362 * Initialize the DMA Coalescing feature 2363 * 2364 **********************************************************************/ 2365 static void 2366 igb_init_dmac(struct adapter *adapter, u32 pba) 2367 { 2368 device_t dev = adapter->dev; 2369 struct e1000_hw *hw = &adapter->hw; 2370 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2371 u16 hwm; 2372 u16 max_frame_size; 2373 2374 if (hw->mac.type == e1000_i211) 2375 return; 2376 2377 max_frame_size = adapter->shared->isc_max_frame_size; 2378 if (hw->mac.type > e1000_82580) { 2379 2380 if (adapter->dmac == 0) { /* Disabling it */ 2381 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2382 return; 2383 } else 2384 device_printf(dev, "DMA Coalescing enabled\n"); 2385 2386 /* Set starting threshold */ 2387 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2388 2389 hwm = 64 * pba - max_frame_size / 16; 2390 if (hwm < 64 * (pba - 6)) 2391 hwm = 64 * (pba - 6); 2392 reg = E1000_READ_REG(hw, E1000_FCRTC); 2393 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2394 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2395 & E1000_FCRTC_RTH_COAL_MASK); 2396 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2397 2398 2399 dmac = pba - max_frame_size / 512; 2400 if (dmac < pba - 10) 2401 dmac = pba - 10; 2402 reg = E1000_READ_REG(hw, E1000_DMACR); 2403 reg &= ~E1000_DMACR_DMACTHR_MASK; 2404 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2405 & E1000_DMACR_DMACTHR_MASK); 2406 2407 /* transition to L0x or L1 if available..*/ 2408 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2409 2410 /* Check if status is 2.5Gb backplane connection 2411 * before configuration of watchdog timer, which is 2412 * in msec values in 12.8usec intervals 2413 * watchdog timer= msec values in 32usec intervals 2414 * for non 2.5Gb connection 2415 */ 2416 if (hw->mac.type == e1000_i354) { 2417 int status = E1000_READ_REG(hw, E1000_STATUS); 2418 if ((status & E1000_STATUS_2P5_SKU) && 2419 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2420 reg |= ((adapter->dmac * 5) >> 6); 2421 else 2422 reg |= (adapter->dmac >> 5); 2423 } else { 2424 reg |= (adapter->dmac >> 5); 2425 } 2426 2427 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2428 2429 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2430 2431 /* Set the interval before transition */ 2432 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2433 if (hw->mac.type == e1000_i350) 2434 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2435 /* 2436 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2437 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2438 */ 2439 if (hw->mac.type == e1000_i354) { 2440 int status = E1000_READ_REG(hw, E1000_STATUS); 2441 if ((status & E1000_STATUS_2P5_SKU) && 2442 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2443 reg |= 0xA; 2444 else 2445 reg |= 0x4; 2446 } else { 2447 reg |= 0x4; 2448 } 2449 2450 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2451 2452 /* free space in tx packet buffer to wake from DMA coal */ 2453 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2454 (2 * max_frame_size)) >> 6); 2455 2456 /* make low power state decision controlled by DMA coal */ 2457 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2458 reg &= ~E1000_PCIEMISC_LX_DECISION; 2459 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2460 2461 } else if (hw->mac.type == e1000_82580) { 2462 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2463 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2464 reg & ~E1000_PCIEMISC_LX_DECISION); 2465 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2466 } 2467 } 2468 2469 /********************************************************************* 2470 * 2471 * Initialize the hardware to a configuration as specified by the 2472 * adapter structure. 2473 * 2474 **********************************************************************/ 2475 static void 2476 em_reset(if_ctx_t ctx) 2477 { 2478 device_t dev = iflib_get_dev(ctx); 2479 struct adapter *adapter = iflib_get_softc(ctx); 2480 struct ifnet *ifp = iflib_get_ifp(ctx); 2481 struct e1000_hw *hw = &adapter->hw; 2482 u16 rx_buffer_size; 2483 u32 pba; 2484 2485 INIT_DEBUGOUT("em_reset: begin"); 2486 /* Let the firmware know the OS is in control */ 2487 em_get_hw_control(adapter); 2488 2489 /* Set up smart power down as default off on newer adapters. */ 2490 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2491 hw->mac.type == e1000_82572)) { 2492 u16 phy_tmp = 0; 2493 2494 /* Speed up time to link by disabling smart power down. */ 2495 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2496 phy_tmp &= ~IGP02E1000_PM_SPD; 2497 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2498 } 2499 2500 /* 2501 * Packet Buffer Allocation (PBA) 2502 * Writing PBA sets the receive portion of the buffer 2503 * the remainder is used for the transmit buffer. 2504 */ 2505 switch (hw->mac.type) { 2506 /* 82547: Total Packet Buffer is 40K */ 2507 case e1000_82547: 2508 case e1000_82547_rev_2: 2509 if (hw->mac.max_frame_size > 8192) 2510 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2511 else 2512 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2513 break; 2514 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2515 case e1000_82571: 2516 case e1000_82572: 2517 case e1000_80003es2lan: 2518 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2519 break; 2520 /* 82573: Total Packet Buffer is 32K */ 2521 case e1000_82573: 2522 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2523 break; 2524 case e1000_82574: 2525 case e1000_82583: 2526 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2527 break; 2528 case e1000_ich8lan: 2529 pba = E1000_PBA_8K; 2530 break; 2531 case e1000_ich9lan: 2532 case e1000_ich10lan: 2533 /* Boost Receive side for jumbo frames */ 2534 if (hw->mac.max_frame_size > 4096) 2535 pba = E1000_PBA_14K; 2536 else 2537 pba = E1000_PBA_10K; 2538 break; 2539 case e1000_pchlan: 2540 case e1000_pch2lan: 2541 case e1000_pch_lpt: 2542 case e1000_pch_spt: 2543 case e1000_pch_cnp: 2544 case e1000_pch_tgp: 2545 case e1000_pch_adp: 2546 case e1000_pch_mtp: 2547 pba = E1000_PBA_26K; 2548 break; 2549 case e1000_82575: 2550 pba = E1000_PBA_32K; 2551 break; 2552 case e1000_82576: 2553 case e1000_vfadapt: 2554 pba = E1000_READ_REG(hw, E1000_RXPBS); 2555 pba &= E1000_RXPBS_SIZE_MASK_82576; 2556 break; 2557 case e1000_82580: 2558 case e1000_i350: 2559 case e1000_i354: 2560 case e1000_vfadapt_i350: 2561 pba = E1000_READ_REG(hw, E1000_RXPBS); 2562 pba = e1000_rxpbs_adjust_82580(pba); 2563 break; 2564 case e1000_i210: 2565 case e1000_i211: 2566 pba = E1000_PBA_34K; 2567 break; 2568 default: 2569 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2570 if (hw->mac.max_frame_size > 8192) 2571 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2572 else 2573 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2574 } 2575 2576 /* Special needs in case of Jumbo frames */ 2577 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2578 u32 tx_space, min_tx, min_rx; 2579 pba = E1000_READ_REG(hw, E1000_PBA); 2580 tx_space = pba >> 16; 2581 pba &= 0xffff; 2582 min_tx = (hw->mac.max_frame_size + 2583 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2584 min_tx = roundup2(min_tx, 1024); 2585 min_tx >>= 10; 2586 min_rx = hw->mac.max_frame_size; 2587 min_rx = roundup2(min_rx, 1024); 2588 min_rx >>= 10; 2589 if (tx_space < min_tx && 2590 ((min_tx - tx_space) < pba)) { 2591 pba = pba - (min_tx - tx_space); 2592 /* 2593 * if short on rx space, rx wins 2594 * and must trump tx adjustment 2595 */ 2596 if (pba < min_rx) 2597 pba = min_rx; 2598 } 2599 E1000_WRITE_REG(hw, E1000_PBA, pba); 2600 } 2601 2602 if (hw->mac.type < igb_mac_min) 2603 E1000_WRITE_REG(hw, E1000_PBA, pba); 2604 2605 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2606 2607 /* 2608 * These parameters control the automatic generation (Tx) and 2609 * response (Rx) to Ethernet PAUSE frames. 2610 * - High water mark should allow for at least two frames to be 2611 * received after sending an XOFF. 2612 * - Low water mark works best when it is very near the high water mark. 2613 * This allows the receiver to restart by sending XON when it has 2614 * drained a bit. Here we use an arbitrary value of 1500 which will 2615 * restart after one full frame is pulled from the buffer. There 2616 * could be several smaller frames in the buffer and if so they will 2617 * not trigger the XON until their total number reduces the buffer 2618 * by 1500. 2619 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2620 */ 2621 rx_buffer_size = (pba & 0xffff) << 10; 2622 hw->fc.high_water = rx_buffer_size - 2623 roundup2(hw->mac.max_frame_size, 1024); 2624 hw->fc.low_water = hw->fc.high_water - 1500; 2625 2626 if (adapter->fc) /* locally set flow control value? */ 2627 hw->fc.requested_mode = adapter->fc; 2628 else 2629 hw->fc.requested_mode = e1000_fc_full; 2630 2631 if (hw->mac.type == e1000_80003es2lan) 2632 hw->fc.pause_time = 0xFFFF; 2633 else 2634 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2635 2636 hw->fc.send_xon = TRUE; 2637 2638 /* Device specific overrides/settings */ 2639 switch (hw->mac.type) { 2640 case e1000_pchlan: 2641 /* Workaround: no TX flow ctrl for PCH */ 2642 hw->fc.requested_mode = e1000_fc_rx_pause; 2643 hw->fc.pause_time = 0xFFFF; /* override */ 2644 if (if_getmtu(ifp) > ETHERMTU) { 2645 hw->fc.high_water = 0x3500; 2646 hw->fc.low_water = 0x1500; 2647 } else { 2648 hw->fc.high_water = 0x5000; 2649 hw->fc.low_water = 0x3000; 2650 } 2651 hw->fc.refresh_time = 0x1000; 2652 break; 2653 case e1000_pch2lan: 2654 case e1000_pch_lpt: 2655 case e1000_pch_spt: 2656 case e1000_pch_cnp: 2657 case e1000_pch_tgp: 2658 case e1000_pch_adp: 2659 case e1000_pch_mtp: 2660 hw->fc.high_water = 0x5C20; 2661 hw->fc.low_water = 0x5048; 2662 hw->fc.pause_time = 0x0650; 2663 hw->fc.refresh_time = 0x0400; 2664 /* Jumbos need adjusted PBA */ 2665 if (if_getmtu(ifp) > ETHERMTU) 2666 E1000_WRITE_REG(hw, E1000_PBA, 12); 2667 else 2668 E1000_WRITE_REG(hw, E1000_PBA, 26); 2669 break; 2670 case e1000_82575: 2671 case e1000_82576: 2672 /* 8-byte granularity */ 2673 hw->fc.low_water = hw->fc.high_water - 8; 2674 break; 2675 case e1000_82580: 2676 case e1000_i350: 2677 case e1000_i354: 2678 case e1000_i210: 2679 case e1000_i211: 2680 case e1000_vfadapt: 2681 case e1000_vfadapt_i350: 2682 /* 16-byte granularity */ 2683 hw->fc.low_water = hw->fc.high_water - 16; 2684 break; 2685 case e1000_ich9lan: 2686 case e1000_ich10lan: 2687 if (if_getmtu(ifp) > ETHERMTU) { 2688 hw->fc.high_water = 0x2800; 2689 hw->fc.low_water = hw->fc.high_water - 8; 2690 break; 2691 } 2692 /* FALLTHROUGH */ 2693 default: 2694 if (hw->mac.type == e1000_80003es2lan) 2695 hw->fc.pause_time = 0xFFFF; 2696 break; 2697 } 2698 2699 /* Issue a global reset */ 2700 e1000_reset_hw(hw); 2701 if (hw->mac.type >= igb_mac_min) { 2702 E1000_WRITE_REG(hw, E1000_WUC, 0); 2703 } else { 2704 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2705 em_disable_aspm(adapter); 2706 } 2707 if (adapter->flags & IGB_MEDIA_RESET) { 2708 e1000_setup_init_funcs(hw, TRUE); 2709 e1000_get_bus_info(hw); 2710 adapter->flags &= ~IGB_MEDIA_RESET; 2711 } 2712 /* and a re-init */ 2713 if (e1000_init_hw(hw) < 0) { 2714 device_printf(dev, "Hardware Initialization Failed\n"); 2715 return; 2716 } 2717 if (hw->mac.type >= igb_mac_min) 2718 igb_init_dmac(adapter, pba); 2719 2720 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2721 e1000_get_phy_info(hw); 2722 e1000_check_for_link(hw); 2723 } 2724 2725 /* 2726 * Initialise the RSS mapping for NICs that support multiple transmit/ 2727 * receive rings. 2728 */ 2729 2730 #define RSSKEYLEN 10 2731 static void 2732 em_initialize_rss_mapping(struct adapter *adapter) 2733 { 2734 uint8_t rss_key[4 * RSSKEYLEN]; 2735 uint32_t reta = 0; 2736 struct e1000_hw *hw = &adapter->hw; 2737 int i; 2738 2739 /* 2740 * Configure RSS key 2741 */ 2742 arc4rand(rss_key, sizeof(rss_key), 0); 2743 for (i = 0; i < RSSKEYLEN; ++i) { 2744 uint32_t rssrk = 0; 2745 2746 rssrk = EM_RSSRK_VAL(rss_key, i); 2747 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2748 } 2749 2750 /* 2751 * Configure RSS redirect table in following fashion: 2752 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2753 */ 2754 for (i = 0; i < sizeof(reta); ++i) { 2755 uint32_t q; 2756 2757 q = (i % adapter->rx_num_queues) << 7; 2758 reta |= q << (8 * i); 2759 } 2760 2761 for (i = 0; i < 32; ++i) 2762 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2763 2764 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2765 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2766 E1000_MRQC_RSS_FIELD_IPV4 | 2767 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2768 E1000_MRQC_RSS_FIELD_IPV6_EX | 2769 E1000_MRQC_RSS_FIELD_IPV6); 2770 } 2771 2772 static void 2773 igb_initialize_rss_mapping(struct adapter *adapter) 2774 { 2775 struct e1000_hw *hw = &adapter->hw; 2776 int i; 2777 int queue_id; 2778 u32 reta; 2779 u32 rss_key[10], mrqc, shift = 0; 2780 2781 /* XXX? */ 2782 if (hw->mac.type == e1000_82575) 2783 shift = 6; 2784 2785 /* 2786 * The redirection table controls which destination 2787 * queue each bucket redirects traffic to. 2788 * Each DWORD represents four queues, with the LSB 2789 * being the first queue in the DWORD. 2790 * 2791 * This just allocates buckets to queues using round-robin 2792 * allocation. 2793 * 2794 * NOTE: It Just Happens to line up with the default 2795 * RSS allocation method. 2796 */ 2797 2798 /* Warning FM follows */ 2799 reta = 0; 2800 for (i = 0; i < 128; i++) { 2801 #ifdef RSS 2802 queue_id = rss_get_indirection_to_bucket(i); 2803 /* 2804 * If we have more queues than buckets, we'll 2805 * end up mapping buckets to a subset of the 2806 * queues. 2807 * 2808 * If we have more buckets than queues, we'll 2809 * end up instead assigning multiple buckets 2810 * to queues. 2811 * 2812 * Both are suboptimal, but we need to handle 2813 * the case so we don't go out of bounds 2814 * indexing arrays and such. 2815 */ 2816 queue_id = queue_id % adapter->rx_num_queues; 2817 #else 2818 queue_id = (i % adapter->rx_num_queues); 2819 #endif 2820 /* Adjust if required */ 2821 queue_id = queue_id << shift; 2822 2823 /* 2824 * The low 8 bits are for hash value (n+0); 2825 * The next 8 bits are for hash value (n+1), etc. 2826 */ 2827 reta = reta >> 8; 2828 reta = reta | ( ((uint32_t) queue_id) << 24); 2829 if ((i & 3) == 3) { 2830 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2831 reta = 0; 2832 } 2833 } 2834 2835 /* Now fill in hash table */ 2836 2837 /* 2838 * MRQC: Multiple Receive Queues Command 2839 * Set queuing to RSS control, number depends on the device. 2840 */ 2841 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2842 2843 #ifdef RSS 2844 /* XXX ew typecasting */ 2845 rss_getkey((uint8_t *) &rss_key); 2846 #else 2847 arc4rand(&rss_key, sizeof(rss_key), 0); 2848 #endif 2849 for (i = 0; i < 10; i++) 2850 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2851 2852 /* 2853 * Configure the RSS fields to hash upon. 2854 */ 2855 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2856 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2857 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2858 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2859 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2860 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2861 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2862 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2863 2864 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2865 } 2866 2867 /********************************************************************* 2868 * 2869 * Setup networking device structure and register interface media. 2870 * 2871 **********************************************************************/ 2872 static int 2873 em_setup_interface(if_ctx_t ctx) 2874 { 2875 struct ifnet *ifp = iflib_get_ifp(ctx); 2876 struct adapter *adapter = iflib_get_softc(ctx); 2877 if_softc_ctx_t scctx = adapter->shared; 2878 2879 INIT_DEBUGOUT("em_setup_interface: begin"); 2880 2881 /* Single Queue */ 2882 if (adapter->tx_num_queues == 1) { 2883 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2884 if_setsendqready(ifp); 2885 } 2886 2887 /* 2888 * Specify the media types supported by this adapter and register 2889 * callbacks to update media and link information 2890 */ 2891 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2892 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2893 u_char fiber_type = IFM_1000_SX; /* default type */ 2894 2895 if (adapter->hw.mac.type == e1000_82545) 2896 fiber_type = IFM_1000_LX; 2897 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2898 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2899 } else { 2900 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2901 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2902 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2903 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2904 if (adapter->hw.phy.type != e1000_phy_ife) { 2905 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2906 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2907 } 2908 } 2909 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2910 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2911 return (0); 2912 } 2913 2914 static int 2915 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2916 { 2917 struct adapter *adapter = iflib_get_softc(ctx); 2918 if_softc_ctx_t scctx = adapter->shared; 2919 int error = E1000_SUCCESS; 2920 struct em_tx_queue *que; 2921 int i, j; 2922 2923 MPASS(adapter->tx_num_queues > 0); 2924 MPASS(adapter->tx_num_queues == ntxqsets); 2925 2926 /* First allocate the top level queue structs */ 2927 if (!(adapter->tx_queues = 2928 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2929 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2930 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2931 return(ENOMEM); 2932 } 2933 2934 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2935 /* Set up some basics */ 2936 2937 struct tx_ring *txr = &que->txr; 2938 txr->adapter = que->adapter = adapter; 2939 que->me = txr->me = i; 2940 2941 /* Allocate report status array */ 2942 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2943 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2944 error = ENOMEM; 2945 goto fail; 2946 } 2947 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2948 txr->tx_rsq[j] = QIDX_INVALID; 2949 /* get the virtual and physical address of the hardware queues */ 2950 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2951 txr->tx_paddr = paddrs[i*ntxqs]; 2952 } 2953 2954 if (bootverbose) 2955 device_printf(iflib_get_dev(ctx), 2956 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2957 return (0); 2958 fail: 2959 em_if_queues_free(ctx); 2960 return (error); 2961 } 2962 2963 static int 2964 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2965 { 2966 struct adapter *adapter = iflib_get_softc(ctx); 2967 int error = E1000_SUCCESS; 2968 struct em_rx_queue *que; 2969 int i; 2970 2971 MPASS(adapter->rx_num_queues > 0); 2972 MPASS(adapter->rx_num_queues == nrxqsets); 2973 2974 /* First allocate the top level queue structs */ 2975 if (!(adapter->rx_queues = 2976 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2977 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2978 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2979 error = ENOMEM; 2980 goto fail; 2981 } 2982 2983 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2984 /* Set up some basics */ 2985 struct rx_ring *rxr = &que->rxr; 2986 rxr->adapter = que->adapter = adapter; 2987 rxr->que = que; 2988 que->me = rxr->me = i; 2989 2990 /* get the virtual and physical address of the hardware queues */ 2991 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2992 rxr->rx_paddr = paddrs[i*nrxqs]; 2993 } 2994 2995 if (bootverbose) 2996 device_printf(iflib_get_dev(ctx), 2997 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2998 2999 return (0); 3000 fail: 3001 em_if_queues_free(ctx); 3002 return (error); 3003 } 3004 3005 static void 3006 em_if_queues_free(if_ctx_t ctx) 3007 { 3008 struct adapter *adapter = iflib_get_softc(ctx); 3009 struct em_tx_queue *tx_que = adapter->tx_queues; 3010 struct em_rx_queue *rx_que = adapter->rx_queues; 3011 3012 if (tx_que != NULL) { 3013 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3014 struct tx_ring *txr = &tx_que->txr; 3015 if (txr->tx_rsq == NULL) 3016 break; 3017 3018 free(txr->tx_rsq, M_DEVBUF); 3019 txr->tx_rsq = NULL; 3020 } 3021 free(adapter->tx_queues, M_DEVBUF); 3022 adapter->tx_queues = NULL; 3023 } 3024 3025 if (rx_que != NULL) { 3026 free(adapter->rx_queues, M_DEVBUF); 3027 adapter->rx_queues = NULL; 3028 } 3029 } 3030 3031 /********************************************************************* 3032 * 3033 * Enable transmit unit. 3034 * 3035 **********************************************************************/ 3036 static void 3037 em_initialize_transmit_unit(if_ctx_t ctx) 3038 { 3039 struct adapter *adapter = iflib_get_softc(ctx); 3040 if_softc_ctx_t scctx = adapter->shared; 3041 struct em_tx_queue *que; 3042 struct tx_ring *txr; 3043 struct e1000_hw *hw = &adapter->hw; 3044 u32 tctl, txdctl = 0, tarc, tipg = 0; 3045 3046 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3047 3048 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 3049 u64 bus_addr; 3050 caddr_t offp, endp; 3051 3052 que = &adapter->tx_queues[i]; 3053 txr = &que->txr; 3054 bus_addr = txr->tx_paddr; 3055 3056 /* Clear checksum offload context. */ 3057 offp = (caddr_t)&txr->csum_flags; 3058 endp = (caddr_t)(txr + 1); 3059 bzero(offp, endp - offp); 3060 3061 /* Base and Len of TX Ring */ 3062 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3063 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3064 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3065 (u32)(bus_addr >> 32)); 3066 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3067 (u32)bus_addr); 3068 /* Init the HEAD/TAIL indices */ 3069 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3070 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3071 3072 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3073 E1000_READ_REG(hw, E1000_TDBAL(i)), 3074 E1000_READ_REG(hw, E1000_TDLEN(i))); 3075 3076 txdctl = 0; /* clear txdctl */ 3077 txdctl |= 0x1f; /* PTHRESH */ 3078 txdctl |= 1 << 8; /* HTHRESH */ 3079 txdctl |= 1 << 16;/* WTHRESH */ 3080 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3081 txdctl |= E1000_TXDCTL_GRAN; 3082 txdctl |= 1 << 25; /* LWTHRESH */ 3083 3084 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3085 } 3086 3087 /* Set the default values for the Tx Inter Packet Gap timer */ 3088 switch (hw->mac.type) { 3089 case e1000_80003es2lan: 3090 tipg = DEFAULT_82543_TIPG_IPGR1; 3091 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3092 E1000_TIPG_IPGR2_SHIFT; 3093 break; 3094 case e1000_82542: 3095 tipg = DEFAULT_82542_TIPG_IPGT; 3096 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3097 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3098 break; 3099 default: 3100 if (hw->phy.media_type == e1000_media_type_fiber || 3101 hw->phy.media_type == e1000_media_type_internal_serdes) 3102 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3103 else 3104 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3105 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3106 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3107 } 3108 3109 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3110 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value); 3111 3112 if(hw->mac.type >= e1000_82540) 3113 E1000_WRITE_REG(hw, E1000_TADV, 3114 adapter->tx_abs_int_delay.value); 3115 3116 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3117 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3118 tarc |= TARC_SPEED_MODE_BIT; 3119 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3120 } else if (hw->mac.type == e1000_80003es2lan) { 3121 /* errata: program both queues to unweighted RR */ 3122 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3123 tarc |= 1; 3124 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3125 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3126 tarc |= 1; 3127 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3128 } else if (hw->mac.type == e1000_82574) { 3129 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3130 tarc |= TARC_ERRATA_BIT; 3131 if ( adapter->tx_num_queues > 1) { 3132 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3133 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3134 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3135 } else 3136 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3137 } 3138 3139 if (adapter->tx_int_delay.value > 0) 3140 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3141 3142 /* Program the Transmit Control Register */ 3143 tctl = E1000_READ_REG(hw, E1000_TCTL); 3144 tctl &= ~E1000_TCTL_CT; 3145 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3146 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3147 3148 if (hw->mac.type >= e1000_82571) 3149 tctl |= E1000_TCTL_MULR; 3150 3151 /* This write will effectively turn on the transmit unit. */ 3152 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3153 3154 /* SPT and KBL errata workarounds */ 3155 if (hw->mac.type == e1000_pch_spt) { 3156 u32 reg; 3157 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3158 reg |= E1000_RCTL_RDMTS_HEX; 3159 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3160 /* i218-i219 Specification Update 1.5.4.5 */ 3161 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3162 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3163 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3164 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3165 } 3166 } 3167 3168 /********************************************************************* 3169 * 3170 * Enable receive unit. 3171 * 3172 **********************************************************************/ 3173 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3174 3175 static void 3176 em_initialize_receive_unit(if_ctx_t ctx) 3177 { 3178 struct adapter *adapter = iflib_get_softc(ctx); 3179 if_softc_ctx_t scctx = adapter->shared; 3180 struct ifnet *ifp = iflib_get_ifp(ctx); 3181 struct e1000_hw *hw = &adapter->hw; 3182 struct em_rx_queue *que; 3183 int i; 3184 uint32_t rctl, rxcsum; 3185 3186 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3187 3188 /* 3189 * Make sure receives are disabled while setting 3190 * up the descriptor ring 3191 */ 3192 rctl = E1000_READ_REG(hw, E1000_RCTL); 3193 /* Do not disable if ever enabled on this hardware */ 3194 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3195 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3196 3197 /* Setup the Receive Control Register */ 3198 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3199 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3200 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3201 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3202 3203 /* Do not store bad packets */ 3204 rctl &= ~E1000_RCTL_SBP; 3205 3206 /* Enable Long Packet receive */ 3207 if (if_getmtu(ifp) > ETHERMTU) 3208 rctl |= E1000_RCTL_LPE; 3209 else 3210 rctl &= ~E1000_RCTL_LPE; 3211 3212 /* Strip the CRC */ 3213 if (!em_disable_crc_stripping) 3214 rctl |= E1000_RCTL_SECRC; 3215 3216 if (hw->mac.type >= e1000_82540) { 3217 E1000_WRITE_REG(hw, E1000_RADV, 3218 adapter->rx_abs_int_delay.value); 3219 3220 /* 3221 * Set the interrupt throttling rate. Value is calculated 3222 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3223 */ 3224 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3225 } 3226 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value); 3227 3228 if (hw->mac.type >= em_mac_min) { 3229 uint32_t rfctl; 3230 /* Use extended rx descriptor formats */ 3231 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3232 rfctl |= E1000_RFCTL_EXTEN; 3233 3234 /* 3235 * When using MSI-X interrupts we need to throttle 3236 * using the EITR register (82574 only) 3237 */ 3238 if (hw->mac.type == e1000_82574) { 3239 for (int i = 0; i < 4; i++) 3240 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3241 DEFAULT_ITR); 3242 /* Disable accelerated acknowledge */ 3243 rfctl |= E1000_RFCTL_ACK_DIS; 3244 } 3245 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3246 } 3247 3248 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3249 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3250 hw->mac.type >= e1000_82543) { 3251 if (adapter->tx_num_queues > 1) { 3252 if (hw->mac.type >= igb_mac_min) { 3253 rxcsum |= E1000_RXCSUM_PCSD; 3254 if (hw->mac.type != e1000_82575) 3255 rxcsum |= E1000_RXCSUM_CRCOFL; 3256 } else 3257 rxcsum |= E1000_RXCSUM_TUOFL | 3258 E1000_RXCSUM_IPOFL | 3259 E1000_RXCSUM_PCSD; 3260 } else { 3261 if (hw->mac.type >= igb_mac_min) 3262 rxcsum |= E1000_RXCSUM_IPPCSE; 3263 else 3264 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3265 if (hw->mac.type > e1000_82575) 3266 rxcsum |= E1000_RXCSUM_CRCOFL; 3267 } 3268 } else 3269 rxcsum &= ~E1000_RXCSUM_TUOFL; 3270 3271 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3272 3273 if (adapter->rx_num_queues > 1) { 3274 if (hw->mac.type >= igb_mac_min) 3275 igb_initialize_rss_mapping(adapter); 3276 else 3277 em_initialize_rss_mapping(adapter); 3278 } 3279 3280 /* 3281 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3282 * long latencies are observed, like Lenovo X60. This 3283 * change eliminates the problem, but since having positive 3284 * values in RDTR is a known source of problems on other 3285 * platforms another solution is being sought. 3286 */ 3287 if (hw->mac.type == e1000_82573) 3288 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3289 3290 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3291 struct rx_ring *rxr = &que->rxr; 3292 /* Setup the Base and Length of the Rx Descriptor Ring */ 3293 u64 bus_addr = rxr->rx_paddr; 3294 #if 0 3295 u32 rdt = adapter->rx_num_queues -1; /* default */ 3296 #endif 3297 3298 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3299 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3300 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3301 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3302 /* Setup the Head and Tail Descriptor Pointers */ 3303 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3304 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3305 } 3306 3307 /* 3308 * Set PTHRESH for improved jumbo performance 3309 * According to 10.2.5.11 of Intel 82574 Datasheet, 3310 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3311 * Only write to RXDCTL(1) if there is a need for different 3312 * settings. 3313 */ 3314 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3315 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3316 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3317 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3318 } else if (hw->mac.type == e1000_82574) { 3319 for (int i = 0; i < adapter->rx_num_queues; i++) { 3320 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3321 rxdctl |= 0x20; /* PTHRESH */ 3322 rxdctl |= 4 << 8; /* HTHRESH */ 3323 rxdctl |= 4 << 16;/* WTHRESH */ 3324 rxdctl |= 1 << 24; /* Switch to granularity */ 3325 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3326 } 3327 } else if (hw->mac.type >= igb_mac_min) { 3328 u32 psize, srrctl = 0; 3329 3330 if (if_getmtu(ifp) > ETHERMTU) { 3331 psize = scctx->isc_max_frame_size; 3332 /* are we on a vlan? */ 3333 if (ifp->if_vlantrunk != NULL) 3334 psize += VLAN_TAG_SIZE; 3335 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3336 } 3337 3338 /* Set maximum packet buffer len */ 3339 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3340 E1000_SRRCTL_BSIZEPKT_SHIFT; 3341 3342 /* 3343 * If TX flow control is disabled and there's >1 queue defined, 3344 * enable DROP. 3345 * 3346 * This drops frames rather than hanging the RX MAC for all queues. 3347 */ 3348 if ((adapter->rx_num_queues > 1) && 3349 (adapter->fc == e1000_fc_none || 3350 adapter->fc == e1000_fc_rx_pause)) { 3351 srrctl |= E1000_SRRCTL_DROP_EN; 3352 } 3353 /* Setup the Base and Length of the Rx Descriptor Rings */ 3354 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3355 struct rx_ring *rxr = &que->rxr; 3356 u64 bus_addr = rxr->rx_paddr; 3357 u32 rxdctl; 3358 3359 #ifdef notyet 3360 /* Configure for header split? -- ignore for now */ 3361 rxr->hdr_split = igb_header_split; 3362 #else 3363 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3364 #endif 3365 3366 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3367 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3368 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3369 (uint32_t)(bus_addr >> 32)); 3370 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3371 (uint32_t)bus_addr); 3372 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3373 /* Enable this Queue */ 3374 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3375 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3376 rxdctl &= 0xFFF00000; 3377 rxdctl |= IGB_RX_PTHRESH; 3378 rxdctl |= IGB_RX_HTHRESH << 8; 3379 rxdctl |= IGB_RX_WTHRESH << 16; 3380 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3381 } 3382 } else if (hw->mac.type >= e1000_pch2lan) { 3383 if (if_getmtu(ifp) > ETHERMTU) 3384 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3385 else 3386 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3387 } 3388 3389 /* Make sure VLAN Filters are off */ 3390 rctl &= ~E1000_RCTL_VFE; 3391 3392 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3393 if (hw->mac.type < igb_mac_min) { 3394 if (adapter->rx_mbuf_sz > 2048 && adapter->rx_mbuf_sz <= 4096) 3395 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3396 else if (adapter->rx_mbuf_sz > 4096 && adapter->rx_mbuf_sz <= 8192) 3397 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3398 else if (adapter->rx_mbuf_sz > 8192) 3399 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3400 else { 3401 rctl |= E1000_RCTL_SZ_2048; 3402 rctl &= ~E1000_RCTL_BSEX; 3403 } 3404 } else 3405 rctl |= E1000_RCTL_SZ_2048; 3406 3407 /* 3408 * rctl bits 11:10 are as follows 3409 * lem: reserved 3410 * em: DTYPE 3411 * igb: reserved 3412 * and should be 00 on all of the above 3413 */ 3414 rctl &= ~0x00000C00; 3415 3416 /* Write out the settings */ 3417 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3418 3419 return; 3420 } 3421 3422 static void 3423 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3424 { 3425 struct adapter *adapter = iflib_get_softc(ctx); 3426 u32 index, bit; 3427 3428 index = (vtag >> 5) & 0x7F; 3429 bit = vtag & 0x1F; 3430 adapter->shadow_vfta[index] |= (1 << bit); 3431 ++adapter->num_vlans; 3432 } 3433 3434 static void 3435 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3436 { 3437 struct adapter *adapter = iflib_get_softc(ctx); 3438 u32 index, bit; 3439 3440 index = (vtag >> 5) & 0x7F; 3441 bit = vtag & 0x1F; 3442 adapter->shadow_vfta[index] &= ~(1 << bit); 3443 --adapter->num_vlans; 3444 } 3445 3446 static void 3447 em_setup_vlan_hw_support(struct adapter *adapter) 3448 { 3449 struct e1000_hw *hw = &adapter->hw; 3450 u32 reg; 3451 3452 /* 3453 * We get here thru init_locked, meaning 3454 * a soft reset, this has already cleared 3455 * the VFTA and other state, so if there 3456 * have been no vlan's registered do nothing. 3457 */ 3458 if (adapter->num_vlans == 0) 3459 return; 3460 3461 /* 3462 * A soft reset zero's out the VFTA, so 3463 * we need to repopulate it now. 3464 */ 3465 for (int i = 0; i < EM_VFTA_SIZE; i++) 3466 if (adapter->shadow_vfta[i] != 0) 3467 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3468 i, adapter->shadow_vfta[i]); 3469 3470 reg = E1000_READ_REG(hw, E1000_CTRL); 3471 reg |= E1000_CTRL_VME; 3472 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3473 3474 /* Enable the Filter Table */ 3475 reg = E1000_READ_REG(hw, E1000_RCTL); 3476 reg &= ~E1000_RCTL_CFIEN; 3477 reg |= E1000_RCTL_VFE; 3478 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3479 } 3480 3481 static void 3482 em_if_intr_enable(if_ctx_t ctx) 3483 { 3484 struct adapter *adapter = iflib_get_softc(ctx); 3485 struct e1000_hw *hw = &adapter->hw; 3486 u32 ims_mask = IMS_ENABLE_MASK; 3487 3488 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3489 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); 3490 ims_mask |= adapter->ims; 3491 } 3492 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3493 } 3494 3495 static void 3496 em_if_intr_disable(if_ctx_t ctx) 3497 { 3498 struct adapter *adapter = iflib_get_softc(ctx); 3499 struct e1000_hw *hw = &adapter->hw; 3500 3501 if (adapter->intr_type == IFLIB_INTR_MSIX) 3502 E1000_WRITE_REG(hw, EM_EIAC, 0); 3503 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3504 } 3505 3506 static void 3507 igb_if_intr_enable(if_ctx_t ctx) 3508 { 3509 struct adapter *adapter = iflib_get_softc(ctx); 3510 struct e1000_hw *hw = &adapter->hw; 3511 u32 mask; 3512 3513 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3514 mask = (adapter->que_mask | adapter->link_mask); 3515 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3516 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3517 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3518 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3519 } else 3520 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3521 E1000_WRITE_FLUSH(hw); 3522 } 3523 3524 static void 3525 igb_if_intr_disable(if_ctx_t ctx) 3526 { 3527 struct adapter *adapter = iflib_get_softc(ctx); 3528 struct e1000_hw *hw = &adapter->hw; 3529 3530 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3531 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3532 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3533 } 3534 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3535 E1000_WRITE_FLUSH(hw); 3536 } 3537 3538 /* 3539 * Bit of a misnomer, what this really means is 3540 * to enable OS management of the system... aka 3541 * to disable special hardware management features 3542 */ 3543 static void 3544 em_init_manageability(struct adapter *adapter) 3545 { 3546 /* A shared code workaround */ 3547 #define E1000_82542_MANC2H E1000_MANC2H 3548 if (adapter->has_manage) { 3549 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3550 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3551 3552 /* disable hardware interception of ARP */ 3553 manc &= ~(E1000_MANC_ARP_EN); 3554 3555 /* enable receiving management packets to the host */ 3556 manc |= E1000_MANC_EN_MNG2HOST; 3557 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3558 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3559 manc2h |= E1000_MNG2HOST_PORT_623; 3560 manc2h |= E1000_MNG2HOST_PORT_664; 3561 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3562 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3563 } 3564 } 3565 3566 /* 3567 * Give control back to hardware management 3568 * controller if there is one. 3569 */ 3570 static void 3571 em_release_manageability(struct adapter *adapter) 3572 { 3573 if (adapter->has_manage) { 3574 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3575 3576 /* re-enable hardware interception of ARP */ 3577 manc |= E1000_MANC_ARP_EN; 3578 manc &= ~E1000_MANC_EN_MNG2HOST; 3579 3580 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3581 } 3582 } 3583 3584 /* 3585 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3586 * For ASF and Pass Through versions of f/w this means 3587 * that the driver is loaded. For AMT version type f/w 3588 * this means that the network i/f is open. 3589 */ 3590 static void 3591 em_get_hw_control(struct adapter *adapter) 3592 { 3593 u32 ctrl_ext, swsm; 3594 3595 if (adapter->vf_ifp) 3596 return; 3597 3598 if (adapter->hw.mac.type == e1000_82573) { 3599 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3600 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3601 swsm | E1000_SWSM_DRV_LOAD); 3602 return; 3603 } 3604 /* else */ 3605 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3606 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3607 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3608 } 3609 3610 /* 3611 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3612 * For ASF and Pass Through versions of f/w this means that 3613 * the driver is no longer loaded. For AMT versions of the 3614 * f/w this means that the network i/f is closed. 3615 */ 3616 static void 3617 em_release_hw_control(struct adapter *adapter) 3618 { 3619 u32 ctrl_ext, swsm; 3620 3621 if (!adapter->has_manage) 3622 return; 3623 3624 if (adapter->hw.mac.type == e1000_82573) { 3625 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3626 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3627 swsm & ~E1000_SWSM_DRV_LOAD); 3628 return; 3629 } 3630 /* else */ 3631 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3632 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3633 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3634 return; 3635 } 3636 3637 static int 3638 em_is_valid_ether_addr(u8 *addr) 3639 { 3640 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3641 3642 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3643 return (FALSE); 3644 } 3645 3646 return (TRUE); 3647 } 3648 3649 /* 3650 ** Parse the interface capabilities with regard 3651 ** to both system management and wake-on-lan for 3652 ** later use. 3653 */ 3654 static void 3655 em_get_wakeup(if_ctx_t ctx) 3656 { 3657 struct adapter *adapter = iflib_get_softc(ctx); 3658 device_t dev = iflib_get_dev(ctx); 3659 u16 eeprom_data = 0, device_id, apme_mask; 3660 3661 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3662 apme_mask = EM_EEPROM_APME; 3663 3664 switch (adapter->hw.mac.type) { 3665 case e1000_82542: 3666 case e1000_82543: 3667 break; 3668 case e1000_82544: 3669 e1000_read_nvm(&adapter->hw, 3670 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3671 apme_mask = EM_82544_APME; 3672 break; 3673 case e1000_82546: 3674 case e1000_82546_rev_3: 3675 if (adapter->hw.bus.func == 1) { 3676 e1000_read_nvm(&adapter->hw, 3677 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3678 break; 3679 } else 3680 e1000_read_nvm(&adapter->hw, 3681 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3682 break; 3683 case e1000_82573: 3684 case e1000_82583: 3685 adapter->has_amt = TRUE; 3686 /* FALLTHROUGH */ 3687 case e1000_82571: 3688 case e1000_82572: 3689 case e1000_80003es2lan: 3690 if (adapter->hw.bus.func == 1) { 3691 e1000_read_nvm(&adapter->hw, 3692 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3693 break; 3694 } else 3695 e1000_read_nvm(&adapter->hw, 3696 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3697 break; 3698 case e1000_ich8lan: 3699 case e1000_ich9lan: 3700 case e1000_ich10lan: 3701 case e1000_pchlan: 3702 case e1000_pch2lan: 3703 case e1000_pch_lpt: 3704 case e1000_pch_spt: 3705 case e1000_82575: /* listing all igb devices */ 3706 case e1000_82576: 3707 case e1000_82580: 3708 case e1000_i350: 3709 case e1000_i354: 3710 case e1000_i210: 3711 case e1000_i211: 3712 case e1000_vfadapt: 3713 case e1000_vfadapt_i350: 3714 apme_mask = E1000_WUC_APME; 3715 adapter->has_amt = TRUE; 3716 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3717 break; 3718 default: 3719 e1000_read_nvm(&adapter->hw, 3720 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3721 break; 3722 } 3723 if (eeprom_data & apme_mask) 3724 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3725 /* 3726 * We have the eeprom settings, now apply the special cases 3727 * where the eeprom may be wrong or the board won't support 3728 * wake on lan on a particular port 3729 */ 3730 device_id = pci_get_device(dev); 3731 switch (device_id) { 3732 case E1000_DEV_ID_82546GB_PCIE: 3733 adapter->wol = 0; 3734 break; 3735 case E1000_DEV_ID_82546EB_FIBER: 3736 case E1000_DEV_ID_82546GB_FIBER: 3737 /* Wake events only supported on port A for dual fiber 3738 * regardless of eeprom setting */ 3739 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3740 E1000_STATUS_FUNC_1) 3741 adapter->wol = 0; 3742 break; 3743 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3744 /* if quad port adapter, disable WoL on all but port A */ 3745 if (global_quad_port_a != 0) 3746 adapter->wol = 0; 3747 /* Reset for multiple quad port adapters */ 3748 if (++global_quad_port_a == 4) 3749 global_quad_port_a = 0; 3750 break; 3751 case E1000_DEV_ID_82571EB_FIBER: 3752 /* Wake events only supported on port A for dual fiber 3753 * regardless of eeprom setting */ 3754 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3755 E1000_STATUS_FUNC_1) 3756 adapter->wol = 0; 3757 break; 3758 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3759 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3760 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3761 /* if quad port adapter, disable WoL on all but port A */ 3762 if (global_quad_port_a != 0) 3763 adapter->wol = 0; 3764 /* Reset for multiple quad port adapters */ 3765 if (++global_quad_port_a == 4) 3766 global_quad_port_a = 0; 3767 break; 3768 } 3769 return; 3770 } 3771 3772 3773 /* 3774 * Enable PCI Wake On Lan capability 3775 */ 3776 static void 3777 em_enable_wakeup(if_ctx_t ctx) 3778 { 3779 struct adapter *adapter = iflib_get_softc(ctx); 3780 device_t dev = iflib_get_dev(ctx); 3781 if_t ifp = iflib_get_ifp(ctx); 3782 int error = 0; 3783 u32 pmc, ctrl, ctrl_ext, rctl; 3784 u16 status; 3785 3786 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3787 return; 3788 3789 /* 3790 * Determine type of Wakeup: note that wol 3791 * is set with all bits on by default. 3792 */ 3793 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3794 adapter->wol &= ~E1000_WUFC_MAG; 3795 3796 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3797 adapter->wol &= ~E1000_WUFC_EX; 3798 3799 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3800 adapter->wol &= ~E1000_WUFC_MC; 3801 else { 3802 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3803 rctl |= E1000_RCTL_MPE; 3804 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3805 } 3806 3807 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3808 goto pme; 3809 3810 /* Advertise the wakeup capability */ 3811 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3812 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3813 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3814 3815 /* Keep the laser running on Fiber adapters */ 3816 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3817 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3818 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3819 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3820 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3821 } 3822 3823 if ((adapter->hw.mac.type == e1000_ich8lan) || 3824 (adapter->hw.mac.type == e1000_pchlan) || 3825 (adapter->hw.mac.type == e1000_ich9lan) || 3826 (adapter->hw.mac.type == e1000_ich10lan)) 3827 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3828 3829 if ( adapter->hw.mac.type >= e1000_pchlan) { 3830 error = em_enable_phy_wakeup(adapter); 3831 if (error) 3832 goto pme; 3833 } else { 3834 /* Enable wakeup by the MAC */ 3835 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3836 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3837 } 3838 3839 if (adapter->hw.phy.type == e1000_phy_igp_3) 3840 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3841 3842 pme: 3843 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3844 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3845 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3846 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3847 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3848 3849 return; 3850 } 3851 3852 /* 3853 * WOL in the newer chipset interfaces (pchlan) 3854 * require thing to be copied into the phy 3855 */ 3856 static int 3857 em_enable_phy_wakeup(struct adapter *adapter) 3858 { 3859 struct e1000_hw *hw = &adapter->hw; 3860 u32 mreg, ret = 0; 3861 u16 preg; 3862 3863 /* copy MAC RARs to PHY RARs */ 3864 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3865 3866 /* copy MAC MTA to PHY MTA */ 3867 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3868 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3869 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3870 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3871 (u16)((mreg >> 16) & 0xFFFF)); 3872 } 3873 3874 /* configure PHY Rx Control register */ 3875 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3876 mreg = E1000_READ_REG(hw, E1000_RCTL); 3877 if (mreg & E1000_RCTL_UPE) 3878 preg |= BM_RCTL_UPE; 3879 if (mreg & E1000_RCTL_MPE) 3880 preg |= BM_RCTL_MPE; 3881 preg &= ~(BM_RCTL_MO_MASK); 3882 if (mreg & E1000_RCTL_MO_3) 3883 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3884 << BM_RCTL_MO_SHIFT); 3885 if (mreg & E1000_RCTL_BAM) 3886 preg |= BM_RCTL_BAM; 3887 if (mreg & E1000_RCTL_PMCF) 3888 preg |= BM_RCTL_PMCF; 3889 mreg = E1000_READ_REG(hw, E1000_CTRL); 3890 if (mreg & E1000_CTRL_RFCE) 3891 preg |= BM_RCTL_RFCE; 3892 e1000_write_phy_reg(hw, BM_RCTL, preg); 3893 3894 /* enable PHY wakeup in MAC register */ 3895 E1000_WRITE_REG(hw, E1000_WUC, 3896 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3897 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3898 3899 /* configure and enable PHY wakeup in PHY registers */ 3900 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol); 3901 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3902 3903 /* activate PHY wakeup */ 3904 ret = hw->phy.ops.acquire(hw); 3905 if (ret) { 3906 printf("Could not acquire PHY\n"); 3907 return ret; 3908 } 3909 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3910 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3911 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3912 if (ret) { 3913 printf("Could not read PHY page 769\n"); 3914 goto out; 3915 } 3916 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3917 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3918 if (ret) 3919 printf("Could not set PHY Host Wakeup bit\n"); 3920 out: 3921 hw->phy.ops.release(hw); 3922 3923 return ret; 3924 } 3925 3926 static void 3927 em_if_led_func(if_ctx_t ctx, int onoff) 3928 { 3929 struct adapter *adapter = iflib_get_softc(ctx); 3930 3931 if (onoff) { 3932 e1000_setup_led(&adapter->hw); 3933 e1000_led_on(&adapter->hw); 3934 } else { 3935 e1000_led_off(&adapter->hw); 3936 e1000_cleanup_led(&adapter->hw); 3937 } 3938 } 3939 3940 /* 3941 * Disable the L0S and L1 LINK states 3942 */ 3943 static void 3944 em_disable_aspm(struct adapter *adapter) 3945 { 3946 int base, reg; 3947 u16 link_cap,link_ctrl; 3948 device_t dev = adapter->dev; 3949 3950 switch (adapter->hw.mac.type) { 3951 case e1000_82573: 3952 case e1000_82574: 3953 case e1000_82583: 3954 break; 3955 default: 3956 return; 3957 } 3958 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3959 return; 3960 reg = base + PCIER_LINK_CAP; 3961 link_cap = pci_read_config(dev, reg, 2); 3962 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3963 return; 3964 reg = base + PCIER_LINK_CTL; 3965 link_ctrl = pci_read_config(dev, reg, 2); 3966 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3967 pci_write_config(dev, reg, link_ctrl, 2); 3968 return; 3969 } 3970 3971 /********************************************************************** 3972 * 3973 * Update the board statistics counters. 3974 * 3975 **********************************************************************/ 3976 static void 3977 em_update_stats_counters(struct adapter *adapter) 3978 { 3979 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3980 3981 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3982 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3983 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3984 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3985 } 3986 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3987 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3988 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3989 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3990 3991 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3992 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3993 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3994 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3995 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3996 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3997 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3998 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3999 /* 4000 ** For watchdog management we need to know if we have been 4001 ** paused during the last interval, so capture that here. 4002 */ 4003 if (adapter->stats.xoffrxc != prev_xoffrxc) 4004 adapter->shared->isc_pause_frames = 1; 4005 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4006 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4007 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4008 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4009 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4010 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4011 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4012 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4013 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4014 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4015 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4016 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4017 4018 /* For the 64-bit byte counters the low dword must be read first. */ 4019 /* Both registers clear on the read of the high dword */ 4020 4021 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 4022 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 4023 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 4024 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 4025 4026 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4027 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4028 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4029 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4030 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4031 4032 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4033 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4034 4035 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4036 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4037 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4038 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4039 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4040 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4041 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4042 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4043 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4044 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4045 4046 /* Interrupt Counts */ 4047 4048 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 4049 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 4050 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 4051 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 4052 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 4053 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 4054 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 4055 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 4056 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 4057 4058 if (adapter->hw.mac.type >= e1000_82543) { 4059 adapter->stats.algnerrc += 4060 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4061 adapter->stats.rxerrc += 4062 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4063 adapter->stats.tncrs += 4064 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4065 adapter->stats.cexterr += 4066 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4067 adapter->stats.tsctc += 4068 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4069 adapter->stats.tsctfc += 4070 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4071 } 4072 } 4073 4074 static uint64_t 4075 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4076 { 4077 struct adapter *adapter = iflib_get_softc(ctx); 4078 struct ifnet *ifp = iflib_get_ifp(ctx); 4079 4080 switch (cnt) { 4081 case IFCOUNTER_COLLISIONS: 4082 return (adapter->stats.colc); 4083 case IFCOUNTER_IERRORS: 4084 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4085 adapter->stats.crcerrs + adapter->stats.algnerrc + 4086 adapter->stats.ruc + adapter->stats.roc + 4087 adapter->stats.mpc + adapter->stats.cexterr); 4088 case IFCOUNTER_OERRORS: 4089 return (adapter->stats.ecol + adapter->stats.latecol + 4090 adapter->watchdog_events); 4091 default: 4092 return (if_get_counter_default(ifp, cnt)); 4093 } 4094 } 4095 4096 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4097 * @ctx: iflib context 4098 * @event: event code to check 4099 * 4100 * Defaults to returning true for unknown events. 4101 * 4102 * @returns true if iflib needs to reinit the interface 4103 */ 4104 static bool 4105 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4106 { 4107 switch (event) { 4108 case IFLIB_RESTART_VLAN_CONFIG: 4109 default: 4110 return (true); 4111 } 4112 } 4113 4114 /* Export a single 32-bit register via a read-only sysctl. */ 4115 static int 4116 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4117 { 4118 struct adapter *adapter; 4119 u_int val; 4120 4121 adapter = oidp->oid_arg1; 4122 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4123 return (sysctl_handle_int(oidp, &val, 0, req)); 4124 } 4125 4126 /* 4127 * Add sysctl variables, one per statistic, to the system. 4128 */ 4129 static void 4130 em_add_hw_stats(struct adapter *adapter) 4131 { 4132 device_t dev = iflib_get_dev(adapter->ctx); 4133 struct em_tx_queue *tx_que = adapter->tx_queues; 4134 struct em_rx_queue *rx_que = adapter->rx_queues; 4135 4136 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4137 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4138 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4139 struct e1000_hw_stats *stats = &adapter->stats; 4140 4141 struct sysctl_oid *stat_node, *queue_node, *int_node; 4142 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4143 4144 #define QUEUE_NAME_LEN 32 4145 char namebuf[QUEUE_NAME_LEN]; 4146 4147 /* Driver Statistics */ 4148 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4149 CTLFLAG_RD, &adapter->dropped_pkts, 4150 "Driver dropped packets"); 4151 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4152 CTLFLAG_RD, &adapter->link_irq, 4153 "Link MSI-X IRQ Handled"); 4154 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4155 CTLFLAG_RD, &adapter->rx_overruns, 4156 "RX overruns"); 4157 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4158 CTLFLAG_RD, &adapter->watchdog_events, 4159 "Watchdog timeouts"); 4160 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4161 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4162 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4163 "Device Control Register"); 4164 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4165 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4166 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4167 "Receiver Control Register"); 4168 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4169 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4170 "Flow Control High Watermark"); 4171 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4172 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4173 "Flow Control Low Watermark"); 4174 4175 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4176 struct tx_ring *txr = &tx_que->txr; 4177 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4178 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4179 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4180 queue_list = SYSCTL_CHILDREN(queue_node); 4181 4182 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4183 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4184 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4185 "Transmit Descriptor Head"); 4186 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4187 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4188 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4189 "Transmit Descriptor Tail"); 4190 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4191 CTLFLAG_RD, &txr->tx_irq, 4192 "Queue MSI-X Transmit Interrupts"); 4193 } 4194 4195 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4196 struct rx_ring *rxr = &rx_que->rxr; 4197 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4198 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4199 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4200 queue_list = SYSCTL_CHILDREN(queue_node); 4201 4202 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4203 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4204 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4205 "Receive Descriptor Head"); 4206 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4207 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4208 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4209 "Receive Descriptor Tail"); 4210 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4211 CTLFLAG_RD, &rxr->rx_irq, 4212 "Queue MSI-X Receive Interrupts"); 4213 } 4214 4215 /* MAC stats get their own sub node */ 4216 4217 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4218 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4219 stat_list = SYSCTL_CHILDREN(stat_node); 4220 4221 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4222 CTLFLAG_RD, &stats->ecol, 4223 "Excessive collisions"); 4224 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4225 CTLFLAG_RD, &stats->scc, 4226 "Single collisions"); 4227 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4228 CTLFLAG_RD, &stats->mcc, 4229 "Multiple collisions"); 4230 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4231 CTLFLAG_RD, &stats->latecol, 4232 "Late collisions"); 4233 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4234 CTLFLAG_RD, &stats->colc, 4235 "Collision Count"); 4236 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4237 CTLFLAG_RD, &adapter->stats.symerrs, 4238 "Symbol Errors"); 4239 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4240 CTLFLAG_RD, &adapter->stats.sec, 4241 "Sequence Errors"); 4242 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4243 CTLFLAG_RD, &adapter->stats.dc, 4244 "Defer Count"); 4245 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4246 CTLFLAG_RD, &adapter->stats.mpc, 4247 "Missed Packets"); 4248 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4249 CTLFLAG_RD, &adapter->stats.rnbc, 4250 "Receive No Buffers"); 4251 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4252 CTLFLAG_RD, &adapter->stats.ruc, 4253 "Receive Undersize"); 4254 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4255 CTLFLAG_RD, &adapter->stats.rfc, 4256 "Fragmented Packets Received "); 4257 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4258 CTLFLAG_RD, &adapter->stats.roc, 4259 "Oversized Packets Received"); 4260 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4261 CTLFLAG_RD, &adapter->stats.rjc, 4262 "Recevied Jabber"); 4263 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4264 CTLFLAG_RD, &adapter->stats.rxerrc, 4265 "Receive Errors"); 4266 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4267 CTLFLAG_RD, &adapter->stats.crcerrs, 4268 "CRC errors"); 4269 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4270 CTLFLAG_RD, &adapter->stats.algnerrc, 4271 "Alignment Errors"); 4272 /* On 82575 these are collision counts */ 4273 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4274 CTLFLAG_RD, &adapter->stats.cexterr, 4275 "Collision/Carrier extension errors"); 4276 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4277 CTLFLAG_RD, &adapter->stats.xonrxc, 4278 "XON Received"); 4279 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4280 CTLFLAG_RD, &adapter->stats.xontxc, 4281 "XON Transmitted"); 4282 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4283 CTLFLAG_RD, &adapter->stats.xoffrxc, 4284 "XOFF Received"); 4285 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4286 CTLFLAG_RD, &adapter->stats.xofftxc, 4287 "XOFF Transmitted"); 4288 4289 /* Packet Reception Stats */ 4290 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4291 CTLFLAG_RD, &adapter->stats.tpr, 4292 "Total Packets Received "); 4293 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4294 CTLFLAG_RD, &adapter->stats.gprc, 4295 "Good Packets Received"); 4296 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4297 CTLFLAG_RD, &adapter->stats.bprc, 4298 "Broadcast Packets Received"); 4299 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4300 CTLFLAG_RD, &adapter->stats.mprc, 4301 "Multicast Packets Received"); 4302 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4303 CTLFLAG_RD, &adapter->stats.prc64, 4304 "64 byte frames received "); 4305 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4306 CTLFLAG_RD, &adapter->stats.prc127, 4307 "65-127 byte frames received"); 4308 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4309 CTLFLAG_RD, &adapter->stats.prc255, 4310 "128-255 byte frames received"); 4311 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4312 CTLFLAG_RD, &adapter->stats.prc511, 4313 "256-511 byte frames received"); 4314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4315 CTLFLAG_RD, &adapter->stats.prc1023, 4316 "512-1023 byte frames received"); 4317 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4318 CTLFLAG_RD, &adapter->stats.prc1522, 4319 "1023-1522 byte frames received"); 4320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4321 CTLFLAG_RD, &adapter->stats.gorc, 4322 "Good Octets Received"); 4323 4324 /* Packet Transmission Stats */ 4325 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4326 CTLFLAG_RD, &adapter->stats.gotc, 4327 "Good Octets Transmitted"); 4328 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4329 CTLFLAG_RD, &adapter->stats.tpt, 4330 "Total Packets Transmitted"); 4331 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4332 CTLFLAG_RD, &adapter->stats.gptc, 4333 "Good Packets Transmitted"); 4334 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4335 CTLFLAG_RD, &adapter->stats.bptc, 4336 "Broadcast Packets Transmitted"); 4337 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4338 CTLFLAG_RD, &adapter->stats.mptc, 4339 "Multicast Packets Transmitted"); 4340 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4341 CTLFLAG_RD, &adapter->stats.ptc64, 4342 "64 byte frames transmitted "); 4343 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4344 CTLFLAG_RD, &adapter->stats.ptc127, 4345 "65-127 byte frames transmitted"); 4346 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4347 CTLFLAG_RD, &adapter->stats.ptc255, 4348 "128-255 byte frames transmitted"); 4349 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4350 CTLFLAG_RD, &adapter->stats.ptc511, 4351 "256-511 byte frames transmitted"); 4352 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4353 CTLFLAG_RD, &adapter->stats.ptc1023, 4354 "512-1023 byte frames transmitted"); 4355 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4356 CTLFLAG_RD, &adapter->stats.ptc1522, 4357 "1024-1522 byte frames transmitted"); 4358 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4359 CTLFLAG_RD, &adapter->stats.tsctc, 4360 "TSO Contexts Transmitted"); 4361 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4362 CTLFLAG_RD, &adapter->stats.tsctfc, 4363 "TSO Contexts Failed"); 4364 4365 4366 /* Interrupt Stats */ 4367 4368 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4369 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4370 int_list = SYSCTL_CHILDREN(int_node); 4371 4372 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4373 CTLFLAG_RD, &adapter->stats.iac, 4374 "Interrupt Assertion Count"); 4375 4376 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4377 CTLFLAG_RD, &adapter->stats.icrxptc, 4378 "Interrupt Cause Rx Pkt Timer Expire Count"); 4379 4380 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4381 CTLFLAG_RD, &adapter->stats.icrxatc, 4382 "Interrupt Cause Rx Abs Timer Expire Count"); 4383 4384 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4385 CTLFLAG_RD, &adapter->stats.ictxptc, 4386 "Interrupt Cause Tx Pkt Timer Expire Count"); 4387 4388 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4389 CTLFLAG_RD, &adapter->stats.ictxatc, 4390 "Interrupt Cause Tx Abs Timer Expire Count"); 4391 4392 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4393 CTLFLAG_RD, &adapter->stats.ictxqec, 4394 "Interrupt Cause Tx Queue Empty Count"); 4395 4396 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4397 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4398 "Interrupt Cause Tx Queue Min Thresh Count"); 4399 4400 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4401 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4402 "Interrupt Cause Rx Desc Min Thresh Count"); 4403 4404 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4405 CTLFLAG_RD, &adapter->stats.icrxoc, 4406 "Interrupt Cause Receiver Overrun Count"); 4407 } 4408 4409 /********************************************************************** 4410 * 4411 * This routine provides a way to dump out the adapter eeprom, 4412 * often a useful debug/service tool. This only dumps the first 4413 * 32 words, stuff that matters is in that extent. 4414 * 4415 **********************************************************************/ 4416 static int 4417 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4418 { 4419 struct adapter *adapter = (struct adapter *)arg1; 4420 int error; 4421 int result; 4422 4423 result = -1; 4424 error = sysctl_handle_int(oidp, &result, 0, req); 4425 4426 if (error || !req->newptr) 4427 return (error); 4428 4429 /* 4430 * This value will cause a hex dump of the 4431 * first 32 16-bit words of the EEPROM to 4432 * the screen. 4433 */ 4434 if (result == 1) 4435 em_print_nvm_info(adapter); 4436 4437 return (error); 4438 } 4439 4440 static void 4441 em_print_nvm_info(struct adapter *adapter) 4442 { 4443 u16 eeprom_data; 4444 int i, j, row = 0; 4445 4446 /* Its a bit crude, but it gets the job done */ 4447 printf("\nInterface EEPROM Dump:\n"); 4448 printf("Offset\n0x0000 "); 4449 for (i = 0, j = 0; i < 32; i++, j++) { 4450 if (j == 8) { /* Make the offset block */ 4451 j = 0; ++row; 4452 printf("\n0x00%x0 ",row); 4453 } 4454 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4455 printf("%04x ", eeprom_data); 4456 } 4457 printf("\n"); 4458 } 4459 4460 static int 4461 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4462 { 4463 struct em_int_delay_info *info; 4464 struct adapter *adapter; 4465 u32 regval; 4466 int error, usecs, ticks; 4467 4468 info = (struct em_int_delay_info *) arg1; 4469 usecs = info->value; 4470 error = sysctl_handle_int(oidp, &usecs, 0, req); 4471 if (error != 0 || req->newptr == NULL) 4472 return (error); 4473 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4474 return (EINVAL); 4475 info->value = usecs; 4476 ticks = EM_USECS_TO_TICKS(usecs); 4477 if (info->offset == E1000_ITR) /* units are 256ns here */ 4478 ticks *= 4; 4479 4480 adapter = info->adapter; 4481 4482 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4483 regval = (regval & ~0xffff) | (ticks & 0xffff); 4484 /* Handle a few special cases. */ 4485 switch (info->offset) { 4486 case E1000_RDTR: 4487 break; 4488 case E1000_TIDV: 4489 if (ticks == 0) { 4490 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4491 /* Don't write 0 into the TIDV register. */ 4492 regval++; 4493 } else 4494 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4495 break; 4496 } 4497 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4498 return (0); 4499 } 4500 4501 static void 4502 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4503 const char *description, struct em_int_delay_info *info, 4504 int offset, int value) 4505 { 4506 info->adapter = adapter; 4507 info->offset = offset; 4508 info->value = value; 4509 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4510 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4511 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4512 info, 0, em_sysctl_int_delay, "I", description); 4513 } 4514 4515 /* 4516 * Set flow control using sysctl: 4517 * Flow control values: 4518 * 0 - off 4519 * 1 - rx pause 4520 * 2 - tx pause 4521 * 3 - full 4522 */ 4523 static int 4524 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4525 { 4526 int error; 4527 static int input = 3; /* default is full */ 4528 struct adapter *adapter = (struct adapter *) arg1; 4529 4530 error = sysctl_handle_int(oidp, &input, 0, req); 4531 4532 if ((error) || (req->newptr == NULL)) 4533 return (error); 4534 4535 if (input == adapter->fc) /* no change? */ 4536 return (error); 4537 4538 switch (input) { 4539 case e1000_fc_rx_pause: 4540 case e1000_fc_tx_pause: 4541 case e1000_fc_full: 4542 case e1000_fc_none: 4543 adapter->hw.fc.requested_mode = input; 4544 adapter->fc = input; 4545 break; 4546 default: 4547 /* Do nothing */ 4548 return (error); 4549 } 4550 4551 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4552 e1000_force_mac_fc(&adapter->hw); 4553 return (error); 4554 } 4555 4556 /* 4557 * Manage Energy Efficient Ethernet: 4558 * Control values: 4559 * 0/1 - enabled/disabled 4560 */ 4561 static int 4562 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4563 { 4564 struct adapter *adapter = (struct adapter *) arg1; 4565 int error, value; 4566 4567 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4568 error = sysctl_handle_int(oidp, &value, 0, req); 4569 if (error || req->newptr == NULL) 4570 return (error); 4571 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4572 em_if_init(adapter->ctx); 4573 4574 return (0); 4575 } 4576 4577 static int 4578 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4579 { 4580 struct adapter *adapter; 4581 int error; 4582 int result; 4583 4584 result = -1; 4585 error = sysctl_handle_int(oidp, &result, 0, req); 4586 4587 if (error || !req->newptr) 4588 return (error); 4589 4590 if (result == 1) { 4591 adapter = (struct adapter *) arg1; 4592 em_print_debug_info(adapter); 4593 } 4594 4595 return (error); 4596 } 4597 4598 static int 4599 em_get_rs(SYSCTL_HANDLER_ARGS) 4600 { 4601 struct adapter *adapter = (struct adapter *) arg1; 4602 int error; 4603 int result; 4604 4605 result = 0; 4606 error = sysctl_handle_int(oidp, &result, 0, req); 4607 4608 if (error || !req->newptr || result != 1) 4609 return (error); 4610 em_dump_rs(adapter); 4611 4612 return (error); 4613 } 4614 4615 static void 4616 em_if_debug(if_ctx_t ctx) 4617 { 4618 em_dump_rs(iflib_get_softc(ctx)); 4619 } 4620 4621 /* 4622 * This routine is meant to be fluid, add whatever is 4623 * needed for debugging a problem. -jfv 4624 */ 4625 static void 4626 em_print_debug_info(struct adapter *adapter) 4627 { 4628 device_t dev = iflib_get_dev(adapter->ctx); 4629 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4630 struct tx_ring *txr = &adapter->tx_queues->txr; 4631 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4632 4633 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4634 printf("Interface is RUNNING "); 4635 else 4636 printf("Interface is NOT RUNNING\n"); 4637 4638 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4639 printf("and INACTIVE\n"); 4640 else 4641 printf("and ACTIVE\n"); 4642 4643 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4644 device_printf(dev, "TX Queue %d ------\n", i); 4645 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4646 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4647 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4648 4649 } 4650 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4651 device_printf(dev, "RX Queue %d ------\n", j); 4652 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4653 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4654 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4655 } 4656 } 4657 4658 /* 4659 * 82574 only: 4660 * Write a new value to the EEPROM increasing the number of MSI-X 4661 * vectors from 3 to 5, for proper multiqueue support. 4662 */ 4663 static void 4664 em_enable_vectors_82574(if_ctx_t ctx) 4665 { 4666 struct adapter *adapter = iflib_get_softc(ctx); 4667 struct e1000_hw *hw = &adapter->hw; 4668 device_t dev = iflib_get_dev(ctx); 4669 u16 edata; 4670 4671 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4672 if (bootverbose) 4673 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4674 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4675 device_printf(dev, "Writing to eeprom: increasing " 4676 "reported MSI-X vectors from 3 to 5...\n"); 4677 edata &= ~(EM_NVM_MSIX_N_MASK); 4678 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4679 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4680 e1000_update_nvm_checksum(hw); 4681 device_printf(dev, "Writing to eeprom: done\n"); 4682 } 4683 } 4684