1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_device_polling.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #ifdef EM_TIMESYNC 55 #include <sys/ioccom.h> 56 #include <sys/time.h> 57 #endif 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <net/bpf.h> 62 #include <net/ethernet.h> 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 68 #include <net/if_types.h> 69 #include <net/if_vlan_var.h> 70 71 #include <netinet/in_systm.h> 72 #include <netinet/in.h> 73 #include <netinet/if_ether.h> 74 #include <netinet/ip.h> 75 #include <netinet/ip6.h> 76 #include <netinet/tcp.h> 77 #include <netinet/udp.h> 78 79 #include <machine/in_cksum.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 83 #include "e1000_api.h" 84 #include "e1000_82571.h" 85 #include "if_em.h" 86 87 /********************************************************************* 88 * Set this to one to display debug statistics 89 *********************************************************************/ 90 int em_display_debug_stats = 0; 91 92 /********************************************************************* 93 * Driver version: 94 *********************************************************************/ 95 char em_driver_version[] = "6.9.5"; 96 97 98 /********************************************************************* 99 * PCI Device ID Table 100 * 101 * Used by probe to select devices to load on 102 * Last field stores an index into e1000_strings 103 * Last entry must be all 0s 104 * 105 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 106 *********************************************************************/ 107 108 static em_vendor_info_t em_vendor_info_array[] = 109 { 110 /* Intel(R) PRO/1000 Network Connection */ 111 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 117 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 118 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 120 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 123 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 125 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 127 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 128 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 130 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 134 135 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 141 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 145 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 150 PCI_ANY_ID, PCI_ANY_ID, 0}, 151 152 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 156 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 157 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 159 { 0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 160 PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 162 PCI_ANY_ID, PCI_ANY_ID, 0}, 163 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 164 PCI_ANY_ID, PCI_ANY_ID, 0}, 165 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 166 PCI_ANY_ID, PCI_ANY_ID, 0}, 167 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 168 PCI_ANY_ID, PCI_ANY_ID, 0}, 169 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 170 PCI_ANY_ID, PCI_ANY_ID, 0}, 171 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 172 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 173 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 174 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 175 176 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 177 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 178 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 179 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 180 PCI_ANY_ID, PCI_ANY_ID, 0}, 181 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 182 PCI_ANY_ID, PCI_ANY_ID, 0}, 183 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 184 PCI_ANY_ID, PCI_ANY_ID, 0}, 185 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 186 PCI_ANY_ID, PCI_ANY_ID, 0}, 187 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 188 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 189 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 190 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 191 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 192 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 193 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 194 195 { 0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 196 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 197 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 198 { 0x8086, E1000_DEV_ID_ICH9_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 199 { 0x8086, E1000_DEV_ID_ICH9_IGP_M_V, PCI_ANY_ID, PCI_ANY_ID, 0}, 200 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 201 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 202 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 203 { 0x8086, E1000_DEV_ID_ICH9_BM, PCI_ANY_ID, PCI_ANY_ID, 0}, 204 { 0x8086, E1000_DEV_ID_82574L, PCI_ANY_ID, PCI_ANY_ID, 0}, 205 { 0x8086, E1000_DEV_ID_ICH10_R_BM_LM, PCI_ANY_ID, PCI_ANY_ID, 0}, 206 { 0x8086, E1000_DEV_ID_ICH10_R_BM_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 207 { 0x8086, E1000_DEV_ID_ICH10_R_BM_V, PCI_ANY_ID, PCI_ANY_ID, 0}, 208 { 0x8086, E1000_DEV_ID_ICH10_D_BM_LM, PCI_ANY_ID, PCI_ANY_ID, 0}, 209 { 0x8086, E1000_DEV_ID_ICH10_D_BM_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 210 /* required last entry */ 211 { 0, 0, 0, 0, 0} 212 }; 213 214 /********************************************************************* 215 * Table of branding strings for all supported NICs. 216 *********************************************************************/ 217 218 static char *em_strings[] = { 219 "Intel(R) PRO/1000 Network Connection" 220 }; 221 222 /********************************************************************* 223 * Function prototypes 224 *********************************************************************/ 225 static int em_probe(device_t); 226 static int em_attach(device_t); 227 static int em_detach(device_t); 228 static int em_shutdown(device_t); 229 static int em_suspend(device_t); 230 static int em_resume(device_t); 231 static void em_start(struct ifnet *); 232 static void em_start_locked(struct ifnet *ifp); 233 static int em_ioctl(struct ifnet *, u_long, caddr_t); 234 static void em_watchdog(struct adapter *); 235 static void em_init(void *); 236 static void em_init_locked(struct adapter *); 237 static void em_stop(void *); 238 static void em_media_status(struct ifnet *, struct ifmediareq *); 239 static int em_media_change(struct ifnet *); 240 static void em_identify_hardware(struct adapter *); 241 static int em_allocate_pci_resources(struct adapter *); 242 static int em_allocate_legacy(struct adapter *adapter); 243 static int em_allocate_msix(struct adapter *adapter); 244 static int em_setup_msix(struct adapter *); 245 static void em_free_pci_resources(struct adapter *); 246 static void em_local_timer(void *); 247 static int em_hardware_init(struct adapter *); 248 static void em_setup_interface(device_t, struct adapter *); 249 static void em_setup_transmit_structures(struct adapter *); 250 static void em_initialize_transmit_unit(struct adapter *); 251 static int em_setup_receive_structures(struct adapter *); 252 static void em_initialize_receive_unit(struct adapter *); 253 static void em_enable_intr(struct adapter *); 254 static void em_disable_intr(struct adapter *); 255 static void em_free_transmit_structures(struct adapter *); 256 static void em_free_receive_structures(struct adapter *); 257 static void em_update_stats_counters(struct adapter *); 258 static void em_txeof(struct adapter *); 259 static void em_tx_purge(struct adapter *); 260 static int em_allocate_receive_structures(struct adapter *); 261 static int em_allocate_transmit_structures(struct adapter *); 262 static int em_rxeof(struct adapter *, int); 263 #ifndef __NO_STRICT_ALIGNMENT 264 static int em_fixup_rx(struct adapter *); 265 #endif 266 static void em_receive_checksum(struct adapter *, struct e1000_rx_desc *, 267 struct mbuf *); 268 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 269 u32 *, u32 *); 270 #if __FreeBSD_version >= 700000 271 static bool em_tso_setup(struct adapter *, struct mbuf *, 272 u32 *, u32 *); 273 #endif /* FreeBSD_version >= 700000 */ 274 static void em_set_promisc(struct adapter *); 275 static void em_disable_promisc(struct adapter *); 276 static void em_set_multi(struct adapter *); 277 static void em_print_hw_stats(struct adapter *); 278 static void em_update_link_status(struct adapter *); 279 static int em_get_buf(struct adapter *, int); 280 static void em_enable_hw_vlans(struct adapter *); 281 static int em_xmit(struct adapter *, struct mbuf **); 282 static void em_smartspeed(struct adapter *); 283 static int em_82547_fifo_workaround(struct adapter *, int); 284 static void em_82547_update_fifo_head(struct adapter *, int); 285 static int em_82547_tx_fifo_reset(struct adapter *); 286 static void em_82547_move_tail(void *); 287 static int em_dma_malloc(struct adapter *, bus_size_t, 288 struct em_dma_alloc *, int); 289 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 290 static void em_print_debug_info(struct adapter *); 291 static void em_print_nvm_info(struct adapter *); 292 static int em_is_valid_ether_addr(u8 *); 293 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 294 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 295 static u32 em_fill_descriptors (bus_addr_t address, u32 length, 296 PDESC_ARRAY desc_array); 297 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 298 static void em_add_int_delay_sysctl(struct adapter *, const char *, 299 const char *, struct em_int_delay_info *, int, int); 300 /* Management and WOL Support */ 301 static void em_init_manageability(struct adapter *); 302 static void em_release_manageability(struct adapter *); 303 static void em_get_hw_control(struct adapter *); 304 static void em_release_hw_control(struct adapter *); 305 static void em_enable_wakeup(device_t); 306 307 #ifdef EM_TIMESYNC 308 /* Precision Time sync support */ 309 static int em_tsync_init(struct adapter *); 310 static void em_tsync_disable(struct adapter *); 311 #endif 312 313 #ifdef EM_LEGACY_IRQ 314 static void em_intr(void *); 315 #else /* FAST IRQ */ 316 #if __FreeBSD_version < 700000 317 static void em_irq_fast(void *); 318 #else 319 static int em_irq_fast(void *); 320 #endif 321 /* MSIX handlers */ 322 static void em_msix_tx(void *); 323 static void em_msix_rx(void *); 324 static void em_msix_link(void *); 325 static void em_add_rx_process_limit(struct adapter *, const char *, 326 const char *, int *, int); 327 static void em_handle_rxtx(void *context, int pending); 328 static void em_handle_rx(void *context, int pending); 329 static void em_handle_tx(void *context, int pending); 330 static void em_handle_link(void *context, int pending); 331 #endif /* EM_LEGACY_IRQ */ 332 333 #ifdef DEVICE_POLLING 334 static poll_handler_t em_poll; 335 #endif /* POLLING */ 336 337 /********************************************************************* 338 * FreeBSD Device Interface Entry Points 339 *********************************************************************/ 340 341 static device_method_t em_methods[] = { 342 /* Device interface */ 343 DEVMETHOD(device_probe, em_probe), 344 DEVMETHOD(device_attach, em_attach), 345 DEVMETHOD(device_detach, em_detach), 346 DEVMETHOD(device_shutdown, em_shutdown), 347 DEVMETHOD(device_suspend, em_suspend), 348 DEVMETHOD(device_resume, em_resume), 349 {0, 0} 350 }; 351 352 static driver_t em_driver = { 353 "em", em_methods, sizeof(struct adapter), 354 }; 355 356 static devclass_t em_devclass; 357 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 358 MODULE_DEPEND(em, pci, 1, 1, 1); 359 MODULE_DEPEND(em, ether, 1, 1, 1); 360 361 /********************************************************************* 362 * Tunable default values. 363 *********************************************************************/ 364 365 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 366 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 367 #define M_TSO_LEN 66 368 369 /* Allow common code without TSO */ 370 #ifndef CSUM_TSO 371 #define CSUM_TSO 0 372 #endif 373 374 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 375 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 376 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 377 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 378 static int em_rxd = EM_DEFAULT_RXD; 379 static int em_txd = EM_DEFAULT_TXD; 380 static int em_smart_pwr_down = FALSE; 381 /* Controls whether promiscuous also shows bad packets */ 382 static int em_debug_sbp = FALSE; 383 /* Local switch for MSI/MSIX */ 384 static int em_enable_msi = TRUE; 385 386 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 387 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 388 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 389 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 390 TUNABLE_INT("hw.em.rxd", &em_rxd); 391 TUNABLE_INT("hw.em.txd", &em_txd); 392 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 393 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 394 TUNABLE_INT("hw.em.enable_msi", &em_enable_msi); 395 396 #ifndef EM_LEGACY_IRQ 397 /* How many packets rxeof tries to clean at a time */ 398 static int em_rx_process_limit = 100; 399 TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 400 #endif 401 402 /* Global used in WOL setup with multiport cards */ 403 static int global_quad_port_a = 0; 404 405 /********************************************************************* 406 * Device identification routine 407 * 408 * em_probe determines if the driver should be loaded on 409 * adapter based on PCI vendor/device id of the adapter. 410 * 411 * return BUS_PROBE_DEFAULT on success, positive on failure 412 *********************************************************************/ 413 414 static int 415 em_probe(device_t dev) 416 { 417 char adapter_name[60]; 418 u16 pci_vendor_id = 0; 419 u16 pci_device_id = 0; 420 u16 pci_subvendor_id = 0; 421 u16 pci_subdevice_id = 0; 422 em_vendor_info_t *ent; 423 424 INIT_DEBUGOUT("em_probe: begin"); 425 426 pci_vendor_id = pci_get_vendor(dev); 427 if (pci_vendor_id != EM_VENDOR_ID) 428 return (ENXIO); 429 430 pci_device_id = pci_get_device(dev); 431 pci_subvendor_id = pci_get_subvendor(dev); 432 pci_subdevice_id = pci_get_subdevice(dev); 433 434 ent = em_vendor_info_array; 435 while (ent->vendor_id != 0) { 436 if ((pci_vendor_id == ent->vendor_id) && 437 (pci_device_id == ent->device_id) && 438 439 ((pci_subvendor_id == ent->subvendor_id) || 440 (ent->subvendor_id == PCI_ANY_ID)) && 441 442 ((pci_subdevice_id == ent->subdevice_id) || 443 (ent->subdevice_id == PCI_ANY_ID))) { 444 sprintf(adapter_name, "%s %s", 445 em_strings[ent->index], 446 em_driver_version); 447 device_set_desc_copy(dev, adapter_name); 448 return (BUS_PROBE_DEFAULT); 449 } 450 ent++; 451 } 452 453 return (ENXIO); 454 } 455 456 /********************************************************************* 457 * Device initialization routine 458 * 459 * The attach entry point is called when the driver is being loaded. 460 * This routine identifies the type of hardware, allocates all resources 461 * and initializes the hardware. 462 * 463 * return 0 on success, positive on failure 464 *********************************************************************/ 465 466 static int 467 em_attach(device_t dev) 468 { 469 struct adapter *adapter; 470 int tsize, rsize; 471 int error = 0; 472 u16 eeprom_data, device_id; 473 474 INIT_DEBUGOUT("em_attach: begin"); 475 476 adapter = device_get_softc(dev); 477 adapter->dev = adapter->osdep.dev = dev; 478 EM_CORE_LOCK_INIT(adapter, device_get_nameunit(dev)); 479 EM_TX_LOCK_INIT(adapter, device_get_nameunit(dev)); 480 EM_RX_LOCK_INIT(adapter, device_get_nameunit(dev)); 481 482 /* SYSCTL stuff */ 483 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 486 em_sysctl_debug_info, "I", "Debug Information"); 487 488 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 489 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 490 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 491 em_sysctl_stats, "I", "Statistics"); 492 493 callout_init_mtx(&adapter->timer, &adapter->core_mtx, 0); 494 callout_init_mtx(&adapter->tx_fifo_timer, &adapter->tx_mtx, 0); 495 496 /* Determine hardware and mac info */ 497 em_identify_hardware(adapter); 498 499 /* Setup PCI resources */ 500 if (em_allocate_pci_resources(adapter)) { 501 device_printf(dev, "Allocation of PCI resources failed\n"); 502 error = ENXIO; 503 goto err_pci; 504 } 505 506 /* 507 ** For ICH8 and family we need to 508 ** map the flash memory, and this 509 ** must happen after the MAC is 510 ** identified 511 */ 512 if ((adapter->hw.mac.type == e1000_ich8lan) || 513 (adapter->hw.mac.type == e1000_ich10lan) || 514 (adapter->hw.mac.type == e1000_ich9lan)) { 515 int rid = EM_BAR_TYPE_FLASH; 516 adapter->flash = bus_alloc_resource_any(dev, 517 SYS_RES_MEMORY, &rid, RF_ACTIVE); 518 if (adapter->flash == NULL) { 519 device_printf(dev, "Mapping of Flash failed\n"); 520 error = ENXIO; 521 goto err_pci; 522 } 523 /* This is used in the shared code */ 524 adapter->hw.flash_address = (u8 *)adapter->flash; 525 adapter->osdep.flash_bus_space_tag = 526 rman_get_bustag(adapter->flash); 527 adapter->osdep.flash_bus_space_handle = 528 rman_get_bushandle(adapter->flash); 529 } 530 531 /* Do Shared Code initialization */ 532 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 533 device_printf(dev, "Setup of Shared code failed\n"); 534 error = ENXIO; 535 goto err_pci; 536 } 537 538 e1000_get_bus_info(&adapter->hw); 539 540 /* Set up some sysctls for the tunable interrupt delays */ 541 em_add_int_delay_sysctl(adapter, "rx_int_delay", 542 "receive interrupt delay in usecs", &adapter->rx_int_delay, 543 E1000_REGISTER(&adapter->hw, E1000_RDTR), em_rx_int_delay_dflt); 544 em_add_int_delay_sysctl(adapter, "tx_int_delay", 545 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 546 E1000_REGISTER(&adapter->hw, E1000_TIDV), em_tx_int_delay_dflt); 547 if (adapter->hw.mac.type >= e1000_82540) { 548 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 549 "receive interrupt delay limit in usecs", 550 &adapter->rx_abs_int_delay, 551 E1000_REGISTER(&adapter->hw, E1000_RADV), 552 em_rx_abs_int_delay_dflt); 553 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 554 "transmit interrupt delay limit in usecs", 555 &adapter->tx_abs_int_delay, 556 E1000_REGISTER(&adapter->hw, E1000_TADV), 557 em_tx_abs_int_delay_dflt); 558 } 559 560 #ifndef EM_LEGACY_IRQ 561 /* Sysctls for limiting the amount of work done in the taskqueue */ 562 em_add_rx_process_limit(adapter, "rx_processing_limit", 563 "max number of rx packets to process", &adapter->rx_process_limit, 564 em_rx_process_limit); 565 #endif 566 567 /* 568 * Validate number of transmit and receive descriptors. It 569 * must not exceed hardware maximum, and must be multiple 570 * of E1000_DBA_ALIGN. 571 */ 572 if (((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN) != 0 || 573 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 574 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 575 (em_txd < EM_MIN_TXD)) { 576 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 577 EM_DEFAULT_TXD, em_txd); 578 adapter->num_tx_desc = EM_DEFAULT_TXD; 579 } else 580 adapter->num_tx_desc = em_txd; 581 if (((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN) != 0 || 582 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 583 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 584 (em_rxd < EM_MIN_RXD)) { 585 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 586 EM_DEFAULT_RXD, em_rxd); 587 adapter->num_rx_desc = EM_DEFAULT_RXD; 588 } else 589 adapter->num_rx_desc = em_rxd; 590 591 adapter->hw.mac.autoneg = DO_AUTO_NEG; 592 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 593 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 594 adapter->rx_buffer_len = 2048; 595 596 e1000_init_script_state_82541(&adapter->hw, TRUE); 597 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 598 599 /* Copper options */ 600 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 601 adapter->hw.phy.mdix = AUTO_ALL_MODES; 602 adapter->hw.phy.disable_polarity_correction = FALSE; 603 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 604 } 605 606 /* 607 * Set the frame limits assuming 608 * standard ethernet sized frames. 609 */ 610 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 611 adapter->min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE; 612 613 /* 614 * This controls when hardware reports transmit completion 615 * status. 616 */ 617 adapter->hw.mac.report_tx_early = 1; 618 619 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 620 EM_DBA_ALIGN); 621 622 /* Allocate Transmit Descriptor ring */ 623 if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { 624 device_printf(dev, "Unable to allocate tx_desc memory\n"); 625 error = ENOMEM; 626 goto err_tx_desc; 627 } 628 adapter->tx_desc_base = 629 (struct e1000_tx_desc *)adapter->txdma.dma_vaddr; 630 631 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 632 EM_DBA_ALIGN); 633 634 /* Allocate Receive Descriptor ring */ 635 if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { 636 device_printf(dev, "Unable to allocate rx_desc memory\n"); 637 error = ENOMEM; 638 goto err_rx_desc; 639 } 640 adapter->rx_desc_base = 641 (struct e1000_rx_desc *)adapter->rxdma.dma_vaddr; 642 643 /* Make sure we have a good EEPROM before we read from it */ 644 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 645 /* 646 ** Some PCI-E parts fail the first check due to 647 ** the link being in sleep state, call it again, 648 ** if it fails a second time its a real issue. 649 */ 650 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 651 device_printf(dev, 652 "The EEPROM Checksum Is Not Valid\n"); 653 error = EIO; 654 goto err_hw_init; 655 } 656 } 657 658 /* Initialize the hardware */ 659 if (em_hardware_init(adapter)) { 660 device_printf(dev, "Unable to initialize the hardware\n"); 661 error = EIO; 662 goto err_hw_init; 663 } 664 665 /* Copy the permanent MAC address out of the EEPROM */ 666 if (e1000_read_mac_addr(&adapter->hw) < 0) { 667 device_printf(dev, "EEPROM read error while reading MAC" 668 " address\n"); 669 error = EIO; 670 goto err_hw_init; 671 } 672 673 if (!em_is_valid_ether_addr(adapter->hw.mac.addr)) { 674 device_printf(dev, "Invalid MAC address\n"); 675 error = EIO; 676 goto err_hw_init; 677 } 678 679 /* Allocate transmit descriptors and buffers */ 680 if (em_allocate_transmit_structures(adapter)) { 681 device_printf(dev, "Could not setup transmit structures\n"); 682 error = ENOMEM; 683 goto err_tx_struct; 684 } 685 686 /* Allocate receive descriptors and buffers */ 687 if (em_allocate_receive_structures(adapter)) { 688 device_printf(dev, "Could not setup receive structures\n"); 689 error = ENOMEM; 690 goto err_rx_struct; 691 } 692 693 /* 694 ** Do interrupt configuration 695 */ 696 if (adapter->msi > 1) /* Do MSI/X */ 697 error = em_allocate_msix(adapter); 698 else /* MSI or Legacy */ 699 error = em_allocate_legacy(adapter); 700 if (error) 701 goto err_rx_struct; 702 703 /* Setup OS specific network interface */ 704 em_setup_interface(dev, adapter); 705 706 /* Initialize statistics */ 707 em_update_stats_counters(adapter); 708 709 adapter->hw.mac.get_link_status = 1; 710 em_update_link_status(adapter); 711 712 /* Indicate SOL/IDER usage */ 713 if (e1000_check_reset_block(&adapter->hw)) 714 device_printf(dev, 715 "PHY reset is blocked due to SOL/IDER session.\n"); 716 717 /* Determine if we have to control management hardware */ 718 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 719 720 /* 721 * Setup Wake-on-Lan 722 */ 723 switch (adapter->hw.mac.type) { 724 725 case e1000_82542: 726 case e1000_82543: 727 break; 728 case e1000_82546: 729 case e1000_82546_rev_3: 730 case e1000_82571: 731 case e1000_80003es2lan: 732 if (adapter->hw.bus.func == 1) 733 e1000_read_nvm(&adapter->hw, 734 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 735 else 736 e1000_read_nvm(&adapter->hw, 737 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 738 eeprom_data &= EM_EEPROM_APME; 739 break; 740 default: 741 /* APME bit in EEPROM is mapped to WUC.APME */ 742 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & 743 E1000_WUC_APME; 744 break; 745 } 746 if (eeprom_data) 747 adapter->wol = E1000_WUFC_MAG; 748 /* 749 * We have the eeprom settings, now apply the special cases 750 * where the eeprom may be wrong or the board won't support 751 * wake on lan on a particular port 752 */ 753 device_id = pci_get_device(dev); 754 switch (device_id) { 755 case E1000_DEV_ID_82546GB_PCIE: 756 adapter->wol = 0; 757 break; 758 case E1000_DEV_ID_82546EB_FIBER: 759 case E1000_DEV_ID_82546GB_FIBER: 760 case E1000_DEV_ID_82571EB_FIBER: 761 /* Wake events only supported on port A for dual fiber 762 * regardless of eeprom setting */ 763 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 764 E1000_STATUS_FUNC_1) 765 adapter->wol = 0; 766 break; 767 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 768 case E1000_DEV_ID_82571EB_QUAD_COPPER: 769 case E1000_DEV_ID_82571EB_QUAD_FIBER: 770 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 771 /* if quad port adapter, disable WoL on all but port A */ 772 if (global_quad_port_a != 0) 773 adapter->wol = 0; 774 /* Reset for multiple quad port adapters */ 775 if (++global_quad_port_a == 4) 776 global_quad_port_a = 0; 777 break; 778 } 779 780 /* Do we need workaround for 82544 PCI-X adapter? */ 781 if (adapter->hw.bus.type == e1000_bus_type_pcix && 782 adapter->hw.mac.type == e1000_82544) 783 adapter->pcix_82544 = TRUE; 784 else 785 adapter->pcix_82544 = FALSE; 786 787 /* Tell the stack that the interface is not active */ 788 adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 789 790 INIT_DEBUGOUT("em_attach: end"); 791 792 return (0); 793 794 err_rx_struct: 795 em_free_transmit_structures(adapter); 796 err_tx_struct: 797 err_hw_init: 798 em_release_hw_control(adapter); 799 e1000_remove_device(&adapter->hw); 800 em_dma_free(adapter, &adapter->rxdma); 801 err_rx_desc: 802 em_dma_free(adapter, &adapter->txdma); 803 err_tx_desc: 804 err_pci: 805 em_free_pci_resources(adapter); 806 EM_TX_LOCK_DESTROY(adapter); 807 EM_RX_LOCK_DESTROY(adapter); 808 EM_CORE_LOCK_DESTROY(adapter); 809 810 return (error); 811 } 812 813 /********************************************************************* 814 * Device removal routine 815 * 816 * The detach entry point is called when the driver is being removed. 817 * This routine stops the adapter and deallocates all the resources 818 * that were allocated for driver operation. 819 * 820 * return 0 on success, positive on failure 821 *********************************************************************/ 822 823 static int 824 em_detach(device_t dev) 825 { 826 struct adapter *adapter = device_get_softc(dev); 827 struct ifnet *ifp = adapter->ifp; 828 829 INIT_DEBUGOUT("em_detach: begin"); 830 831 /* Make sure VLANS are not using driver */ 832 #if __FreeBSD_version >= 700000 833 if (adapter->ifp->if_vlantrunk != NULL) { 834 #else 835 if (adapter->ifp->if_nvlans != 0) { 836 #endif 837 device_printf(dev,"Vlan in use, detach first\n"); 838 return (EBUSY); 839 } 840 841 #ifdef DEVICE_POLLING 842 if (ifp->if_capenable & IFCAP_POLLING) 843 ether_poll_deregister(ifp); 844 #endif 845 846 EM_CORE_LOCK(adapter); 847 EM_TX_LOCK(adapter); 848 adapter->in_detach = 1; 849 em_stop(adapter); 850 e1000_phy_hw_reset(&adapter->hw); 851 852 em_release_manageability(adapter); 853 854 if (((adapter->hw.mac.type == e1000_82573) || 855 (adapter->hw.mac.type == e1000_ich8lan) || 856 (adapter->hw.mac.type == e1000_ich10lan) || 857 (adapter->hw.mac.type == e1000_ich9lan)) && 858 e1000_check_mng_mode(&adapter->hw)) 859 em_release_hw_control(adapter); 860 861 if (adapter->wol) { 862 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 863 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 864 em_enable_wakeup(dev); 865 } 866 867 EM_TX_UNLOCK(adapter); 868 EM_CORE_UNLOCK(adapter); 869 870 ether_ifdetach(adapter->ifp); 871 callout_drain(&adapter->timer); 872 callout_drain(&adapter->tx_fifo_timer); 873 874 em_free_pci_resources(adapter); 875 bus_generic_detach(dev); 876 if_free(ifp); 877 878 e1000_remove_device(&adapter->hw); 879 em_free_transmit_structures(adapter); 880 em_free_receive_structures(adapter); 881 882 /* Free Transmit Descriptor ring */ 883 if (adapter->tx_desc_base) { 884 em_dma_free(adapter, &adapter->txdma); 885 adapter->tx_desc_base = NULL; 886 } 887 888 /* Free Receive Descriptor ring */ 889 if (adapter->rx_desc_base) { 890 em_dma_free(adapter, &adapter->rxdma); 891 adapter->rx_desc_base = NULL; 892 } 893 894 EM_TX_LOCK_DESTROY(adapter); 895 EM_RX_LOCK_DESTROY(adapter); 896 EM_CORE_LOCK_DESTROY(adapter); 897 898 return (0); 899 } 900 901 /********************************************************************* 902 * 903 * Shutdown entry point 904 * 905 **********************************************************************/ 906 907 static int 908 em_shutdown(device_t dev) 909 { 910 return em_suspend(dev); 911 } 912 913 /* 914 * Suspend/resume device methods. 915 */ 916 static int 917 em_suspend(device_t dev) 918 { 919 struct adapter *adapter = device_get_softc(dev); 920 921 EM_CORE_LOCK(adapter); 922 923 EM_TX_LOCK(adapter); 924 em_stop(adapter); 925 EM_TX_UNLOCK(adapter); 926 927 em_release_manageability(adapter); 928 929 if (((adapter->hw.mac.type == e1000_82573) || 930 (adapter->hw.mac.type == e1000_ich8lan) || 931 (adapter->hw.mac.type == e1000_ich10lan) || 932 (adapter->hw.mac.type == e1000_ich9lan)) && 933 e1000_check_mng_mode(&adapter->hw)) 934 em_release_hw_control(adapter); 935 936 if (adapter->wol) { 937 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 938 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 939 em_enable_wakeup(dev); 940 } 941 942 EM_CORE_UNLOCK(adapter); 943 944 return bus_generic_suspend(dev); 945 } 946 947 static int 948 em_resume(device_t dev) 949 { 950 struct adapter *adapter = device_get_softc(dev); 951 struct ifnet *ifp = adapter->ifp; 952 953 EM_CORE_LOCK(adapter); 954 em_init_locked(adapter); 955 em_init_manageability(adapter); 956 EM_CORE_UNLOCK(adapter); 957 em_start(ifp); 958 959 return bus_generic_resume(dev); 960 } 961 962 963 /********************************************************************* 964 * Transmit entry point 965 * 966 * em_start is called by the stack to initiate a transmit. 967 * The driver will remain in this routine as long as there are 968 * packets to transmit and transmit resources are available. 969 * In case resources are not available stack is notified and 970 * the packet is requeued. 971 **********************************************************************/ 972 973 static void 974 em_start_locked(struct ifnet *ifp) 975 { 976 struct adapter *adapter = ifp->if_softc; 977 struct mbuf *m_head; 978 979 EM_TX_LOCK_ASSERT(adapter); 980 981 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 982 IFF_DRV_RUNNING) 983 return; 984 if (!adapter->link_active) 985 return; 986 987 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 988 989 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 990 if (m_head == NULL) 991 break; 992 /* 993 * Encapsulation can modify our pointer, and or make it 994 * NULL on failure. In that event, we can't requeue. 995 */ 996 if (em_xmit(adapter, &m_head)) { 997 if (m_head == NULL) 998 break; 999 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1000 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1001 break; 1002 } 1003 1004 /* Send a copy of the frame to the BPF listener */ 1005 ETHER_BPF_MTAP(ifp, m_head); 1006 1007 /* Set timeout in case hardware has problems transmitting. */ 1008 adapter->watchdog_timer = EM_TX_TIMEOUT; 1009 } 1010 } 1011 1012 static void 1013 em_start(struct ifnet *ifp) 1014 { 1015 struct adapter *adapter = ifp->if_softc; 1016 1017 EM_TX_LOCK(adapter); 1018 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1019 em_start_locked(ifp); 1020 EM_TX_UNLOCK(adapter); 1021 } 1022 1023 /********************************************************************* 1024 * Ioctl entry point 1025 * 1026 * em_ioctl is called when the user wants to configure the 1027 * interface. 1028 * 1029 * return 0 on success, positive on failure 1030 **********************************************************************/ 1031 1032 static int 1033 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1034 { 1035 struct adapter *adapter = ifp->if_softc; 1036 struct ifreq *ifr = (struct ifreq *)data; 1037 #ifdef INET 1038 struct ifaddr *ifa = (struct ifaddr *)data; 1039 #endif 1040 int error = 0; 1041 1042 if (adapter->in_detach) 1043 return (error); 1044 1045 switch (command) { 1046 case SIOCSIFADDR: 1047 #ifdef INET 1048 if (ifa->ifa_addr->sa_family == AF_INET) { 1049 /* 1050 * XXX 1051 * Since resetting hardware takes a very long time 1052 * and results in link renegotiation we only 1053 * initialize the hardware only when it is absolutely 1054 * required. 1055 */ 1056 ifp->if_flags |= IFF_UP; 1057 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1058 EM_CORE_LOCK(adapter); 1059 em_init_locked(adapter); 1060 EM_CORE_UNLOCK(adapter); 1061 } 1062 arp_ifinit(ifp, ifa); 1063 } else 1064 #endif 1065 error = ether_ioctl(ifp, command, data); 1066 break; 1067 case SIOCSIFMTU: 1068 { 1069 int max_frame_size; 1070 u16 eeprom_data = 0; 1071 1072 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1073 1074 EM_CORE_LOCK(adapter); 1075 switch (adapter->hw.mac.type) { 1076 case e1000_82573: 1077 /* 1078 * 82573 only supports jumbo frames 1079 * if ASPM is disabled. 1080 */ 1081 e1000_read_nvm(&adapter->hw, 1082 NVM_INIT_3GIO_3, 1, &eeprom_data); 1083 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1084 max_frame_size = ETHER_MAX_LEN; 1085 break; 1086 } 1087 /* Allow Jumbo frames - fall thru */ 1088 case e1000_82571: 1089 case e1000_82572: 1090 case e1000_ich9lan: 1091 case e1000_ich10lan: 1092 case e1000_82574: 1093 case e1000_80003es2lan: /* Limit Jumbo Frame size */ 1094 max_frame_size = 9234; 1095 break; 1096 /* Adapters that do not support jumbo frames */ 1097 case e1000_82542: 1098 case e1000_ich8lan: 1099 max_frame_size = ETHER_MAX_LEN; 1100 break; 1101 default: 1102 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1103 } 1104 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1105 ETHER_CRC_LEN) { 1106 EM_CORE_UNLOCK(adapter); 1107 error = EINVAL; 1108 break; 1109 } 1110 1111 ifp->if_mtu = ifr->ifr_mtu; 1112 adapter->max_frame_size = 1113 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1114 em_init_locked(adapter); 1115 EM_CORE_UNLOCK(adapter); 1116 break; 1117 } 1118 case SIOCSIFFLAGS: 1119 IOCTL_DEBUGOUT("ioctl rcv'd:\ 1120 SIOCSIFFLAGS (Set Interface Flags)"); 1121 EM_CORE_LOCK(adapter); 1122 if (ifp->if_flags & IFF_UP) { 1123 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1124 if ((ifp->if_flags ^ adapter->if_flags) & 1125 (IFF_PROMISC | IFF_ALLMULTI)) { 1126 em_disable_promisc(adapter); 1127 em_set_promisc(adapter); 1128 } 1129 } else 1130 em_init_locked(adapter); 1131 } else 1132 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1133 EM_TX_LOCK(adapter); 1134 em_stop(adapter); 1135 EM_TX_UNLOCK(adapter); 1136 } 1137 adapter->if_flags = ifp->if_flags; 1138 EM_CORE_UNLOCK(adapter); 1139 break; 1140 case SIOCADDMULTI: 1141 case SIOCDELMULTI: 1142 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 1143 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1144 EM_CORE_LOCK(adapter); 1145 em_disable_intr(adapter); 1146 em_set_multi(adapter); 1147 if (adapter->hw.mac.type == e1000_82542 && 1148 adapter->hw.revision_id == E1000_REVISION_2) { 1149 em_initialize_receive_unit(adapter); 1150 } 1151 #ifdef DEVICE_POLLING 1152 if (!(ifp->if_capenable & IFCAP_POLLING)) 1153 #endif 1154 em_enable_intr(adapter); 1155 EM_CORE_UNLOCK(adapter); 1156 } 1157 break; 1158 case SIOCSIFMEDIA: 1159 /* Check SOL/IDER usage */ 1160 EM_CORE_LOCK(adapter); 1161 if (e1000_check_reset_block(&adapter->hw)) { 1162 EM_CORE_UNLOCK(adapter); 1163 device_printf(adapter->dev, "Media change is" 1164 " blocked due to SOL/IDER session.\n"); 1165 break; 1166 } 1167 EM_CORE_UNLOCK(adapter); 1168 case SIOCGIFMEDIA: 1169 IOCTL_DEBUGOUT("ioctl rcv'd: \ 1170 SIOCxIFMEDIA (Get/Set Interface Media)"); 1171 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1172 break; 1173 case SIOCSIFCAP: 1174 { 1175 int mask, reinit; 1176 1177 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 1178 reinit = 0; 1179 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1180 #ifdef DEVICE_POLLING 1181 if (mask & IFCAP_POLLING) { 1182 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1183 error = ether_poll_register(em_poll, ifp); 1184 if (error) 1185 return (error); 1186 EM_CORE_LOCK(adapter); 1187 em_disable_intr(adapter); 1188 ifp->if_capenable |= IFCAP_POLLING; 1189 EM_CORE_UNLOCK(adapter); 1190 } else { 1191 error = ether_poll_deregister(ifp); 1192 /* Enable interrupt even in error case */ 1193 EM_CORE_LOCK(adapter); 1194 em_enable_intr(adapter); 1195 ifp->if_capenable &= ~IFCAP_POLLING; 1196 EM_CORE_UNLOCK(adapter); 1197 } 1198 } 1199 #endif 1200 if (mask & IFCAP_HWCSUM) { 1201 ifp->if_capenable ^= IFCAP_HWCSUM; 1202 reinit = 1; 1203 } 1204 #if __FreeBSD_version >= 700000 1205 if (mask & IFCAP_TSO4) { 1206 ifp->if_capenable ^= IFCAP_TSO4; 1207 reinit = 1; 1208 } 1209 #endif 1210 1211 if (mask & IFCAP_VLAN_HWTAGGING) { 1212 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1213 reinit = 1; 1214 } 1215 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1216 em_init(adapter); 1217 #if __FreeBSD_version >= 700000 1218 VLAN_CAPABILITIES(ifp); 1219 #endif 1220 break; 1221 } 1222 1223 #ifdef EM_TIMESYNC 1224 /* 1225 ** IOCTL support for Precision Time (IEEE 1588) Support 1226 */ 1227 case EM_TIMESYNC_READTS: 1228 { 1229 u32 rx_ctl, tx_ctl; 1230 struct em_tsync_read *tdata; 1231 1232 tdata = (struct em_tsync_read *) ifr->ifr_data; 1233 1234 IOCTL_DEBUGOUT("Reading Timestamp\n"); 1235 1236 if (tdata->read_current_time) { 1237 getnanotime(&tdata->system_time); 1238 tdata->network_time = E1000_READ_REG(&adapter->hw, E1000_SYSTIML); 1239 tdata->network_time |= 1240 (u64)E1000_READ_REG(&adapter->hw, E1000_SYSTIMH ) << 32; 1241 } 1242 1243 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 1244 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 1245 1246 IOCTL_DEBUGOUT1("RX_CTL value = %u\n", rx_ctl); 1247 IOCTL_DEBUGOUT1("TX_CTL value = %u\n", tx_ctl); 1248 1249 if (rx_ctl & 0x1) { 1250 IOCTL_DEBUGOUT("RX timestamp is valid\n"); 1251 u32 tmp; 1252 unsigned char *tmp_cp; 1253 1254 tdata->rx_valid = 1; 1255 tdata->rx_stamp = E1000_READ_REG(&adapter->hw, E1000_RXSTMPL); 1256 tdata->rx_stamp |= (u64)E1000_READ_REG(&adapter->hw, 1257 E1000_RXSTMPH) << 32; 1258 1259 tmp = E1000_READ_REG(&adapter->hw, E1000_RXSATRL); 1260 tmp_cp = (unsigned char *) &tmp; 1261 tdata->srcid[0] = tmp_cp[0]; 1262 tdata->srcid[1] = tmp_cp[1]; 1263 tdata->srcid[2] = tmp_cp[2]; 1264 tdata->srcid[3] = tmp_cp[3]; 1265 tmp = E1000_READ_REG(&adapter->hw, E1000_RXSATRH); 1266 tmp_cp = (unsigned char *) &tmp; 1267 tdata->srcid[4] = tmp_cp[0]; 1268 tdata->srcid[5] = tmp_cp[1]; 1269 tdata->seqid = tmp >> 16; 1270 tdata->seqid = htons(tdata->seqid); 1271 } else 1272 tdata->rx_valid = 0; 1273 1274 if (tx_ctl & 0x1) { 1275 IOCTL_DEBUGOUT("TX timestamp is valid\n"); 1276 tdata->tx_valid = 1; 1277 tdata->tx_stamp = E1000_READ_REG(&adapter->hw, E1000_TXSTMPL); 1278 tdata->tx_stamp |= (u64) E1000_READ_REG(&adapter->hw, 1279 E1000_TXSTMPH) << 32; 1280 } else 1281 tdata->tx_valid = 0; 1282 1283 return (0); 1284 } 1285 #endif /* EM_TIMESYNC */ 1286 1287 default: 1288 error = ether_ioctl(ifp, command, data); 1289 break; 1290 } 1291 1292 return (error); 1293 } 1294 1295 /********************************************************************* 1296 * Watchdog timer: 1297 * 1298 * This routine is called from the local timer every second. 1299 * As long as transmit descriptors are being cleaned the value 1300 * is non-zero and we do nothing. Reaching 0 indicates a tx hang 1301 * and we then reset the device. 1302 * 1303 **********************************************************************/ 1304 1305 static void 1306 em_watchdog(struct adapter *adapter) 1307 { 1308 1309 EM_CORE_LOCK_ASSERT(adapter); 1310 1311 /* 1312 ** The timer is set to 5 every time start queues a packet. 1313 ** Then txeof keeps resetting it as long as it cleans at 1314 ** least one descriptor. 1315 ** Finally, anytime all descriptors are clean the timer is 1316 ** set to 0. 1317 */ 1318 EM_TX_LOCK(adapter); 1319 if ((adapter->watchdog_timer == 0) || (--adapter->watchdog_timer)) { 1320 EM_TX_UNLOCK(adapter); 1321 return; 1322 } 1323 1324 /* If we are in this routine because of pause frames, then 1325 * don't reset the hardware. 1326 */ 1327 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1328 E1000_STATUS_TXOFF) { 1329 adapter->watchdog_timer = EM_TX_TIMEOUT; 1330 EM_TX_UNLOCK(adapter); 1331 return; 1332 } 1333 1334 if (e1000_check_for_link(&adapter->hw) == 0) 1335 device_printf(adapter->dev, "watchdog timeout -- resetting\n"); 1336 adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1337 adapter->watchdog_events++; 1338 EM_TX_UNLOCK(adapter); 1339 1340 em_init_locked(adapter); 1341 } 1342 1343 /********************************************************************* 1344 * Init entry point 1345 * 1346 * This routine is used in two ways. It is used by the stack as 1347 * init entry point in network interface structure. It is also used 1348 * by the driver as a hw/sw initialization routine to get to a 1349 * consistent state. 1350 * 1351 * return 0 on success, positive on failure 1352 **********************************************************************/ 1353 1354 static void 1355 em_init_locked(struct adapter *adapter) 1356 { 1357 struct ifnet *ifp = adapter->ifp; 1358 device_t dev = adapter->dev; 1359 u32 pba; 1360 1361 INIT_DEBUGOUT("em_init: begin"); 1362 1363 EM_CORE_LOCK_ASSERT(adapter); 1364 1365 EM_TX_LOCK(adapter); 1366 em_stop(adapter); 1367 EM_TX_UNLOCK(adapter); 1368 1369 /* 1370 * Packet Buffer Allocation (PBA) 1371 * Writing PBA sets the receive portion of the buffer 1372 * the remainder is used for the transmit buffer. 1373 * 1374 * Devices before the 82547 had a Packet Buffer of 64K. 1375 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1376 * After the 82547 the buffer was reduced to 40K. 1377 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1378 * Note: default does not leave enough room for Jumbo Frame >10k. 1379 */ 1380 switch (adapter->hw.mac.type) { 1381 case e1000_82547: 1382 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1383 if (adapter->max_frame_size > 8192) 1384 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1385 else 1386 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1387 adapter->tx_fifo_head = 0; 1388 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1389 adapter->tx_fifo_size = 1390 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1391 break; 1392 /* Total Packet Buffer on these is 48K */ 1393 case e1000_82571: 1394 case e1000_82572: 1395 case e1000_80003es2lan: 1396 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1397 break; 1398 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1399 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1400 break; 1401 case e1000_82574: 1402 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1403 break; 1404 case e1000_ich9lan: 1405 case e1000_ich10lan: 1406 #define E1000_PBA_10K 0x000A 1407 pba = E1000_PBA_10K; 1408 break; 1409 case e1000_ich8lan: 1410 pba = E1000_PBA_8K; 1411 break; 1412 default: 1413 /* Devices before 82547 had a Packet Buffer of 64K. */ 1414 if (adapter->max_frame_size > 8192) 1415 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1416 else 1417 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1418 } 1419 1420 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1421 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1422 1423 /* Get the latest mac address, User can use a LAA */ 1424 bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr, 1425 ETHER_ADDR_LEN); 1426 1427 /* Put the address into the Receive Address Array */ 1428 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1429 1430 /* 1431 * With the 82571 adapter, RAR[0] may be overwritten 1432 * when the other port is reset, we make a duplicate 1433 * in RAR[14] for that eventuality, this assures 1434 * the interface continues to function. 1435 */ 1436 if (adapter->hw.mac.type == e1000_82571) { 1437 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1438 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1439 E1000_RAR_ENTRIES - 1); 1440 } 1441 1442 /* Initialize the hardware */ 1443 if (em_hardware_init(adapter)) { 1444 device_printf(dev, "Unable to initialize the hardware\n"); 1445 return; 1446 } 1447 em_update_link_status(adapter); 1448 1449 /* Setup VLAN support, basic and offload if available */ 1450 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1451 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1452 em_enable_hw_vlans(adapter); 1453 1454 /* Set hardware offload abilities */ 1455 ifp->if_hwassist = 0; 1456 if (adapter->hw.mac.type >= e1000_82543) { 1457 if (ifp->if_capenable & IFCAP_TXCSUM) 1458 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1459 #if __FreeBSD_version >= 700000 1460 if (ifp->if_capenable & IFCAP_TSO4) 1461 ifp->if_hwassist |= CSUM_TSO; 1462 #endif 1463 } 1464 1465 /* Configure for OS presence */ 1466 em_init_manageability(adapter); 1467 1468 /* Prepare transmit descriptors and buffers */ 1469 em_setup_transmit_structures(adapter); 1470 em_initialize_transmit_unit(adapter); 1471 1472 /* Setup Multicast table */ 1473 em_set_multi(adapter); 1474 1475 /* Prepare receive descriptors and buffers */ 1476 if (em_setup_receive_structures(adapter)) { 1477 device_printf(dev, "Could not setup receive structures\n"); 1478 EM_TX_LOCK(adapter); 1479 em_stop(adapter); 1480 EM_TX_UNLOCK(adapter); 1481 return; 1482 } 1483 em_initialize_receive_unit(adapter); 1484 1485 /* Don't lose promiscuous settings */ 1486 em_set_promisc(adapter); 1487 1488 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1489 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1490 1491 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1492 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1493 1494 /* MSI/X configuration for 82574 */ 1495 if (adapter->hw.mac.type == e1000_82574) { 1496 int tmp; 1497 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1498 tmp |= E1000_CTRL_EXT_PBA_CLR; 1499 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1500 /* 1501 ** Set the IVAR - interrupt vector routing. 1502 ** Each nibble represents a vector, high bit 1503 ** is enable, other 3 bits are the MSIX table 1504 ** entry, we map RXQ0 to 0, TXQ0 to 1, and 1505 ** Link (other) to 2, hence the magic number. 1506 */ 1507 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1508 } 1509 1510 #ifdef DEVICE_POLLING 1511 /* 1512 * Only enable interrupts if we are not polling, make sure 1513 * they are off otherwise. 1514 */ 1515 if (ifp->if_capenable & IFCAP_POLLING) 1516 em_disable_intr(adapter); 1517 else 1518 #endif /* DEVICE_POLLING */ 1519 em_enable_intr(adapter); 1520 1521 #ifdef EM_TIMESYNC 1522 /* Initializae IEEE 1588 Precision Time hardware */ 1523 if ((adapter->hw.mac.type == e1000_82574) || 1524 (adapter->hw.mac.type == e1000_ich10lan)) 1525 em_tsync_init(adapter); 1526 #endif 1527 1528 /* Don't reset the phy next time init gets called */ 1529 adapter->hw.phy.reset_disable = TRUE; 1530 } 1531 1532 static void 1533 em_init(void *arg) 1534 { 1535 struct adapter *adapter = arg; 1536 1537 EM_CORE_LOCK(adapter); 1538 em_init_locked(adapter); 1539 EM_CORE_UNLOCK(adapter); 1540 } 1541 1542 1543 #ifdef DEVICE_POLLING 1544 /********************************************************************* 1545 * 1546 * Legacy polling routine 1547 * 1548 *********************************************************************/ 1549 static void 1550 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1551 { 1552 struct adapter *adapter = ifp->if_softc; 1553 u32 reg_icr; 1554 1555 EM_CORE_LOCK(adapter); 1556 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1557 EM_CORE_UNLOCK(adapter); 1558 return; 1559 } 1560 1561 if (cmd == POLL_AND_CHECK_STATUS) { 1562 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1563 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1564 callout_stop(&adapter->timer); 1565 adapter->hw.mac.get_link_status = 1; 1566 em_update_link_status(adapter); 1567 callout_reset(&adapter->timer, hz, 1568 em_local_timer, adapter); 1569 } 1570 } 1571 EM_CORE_UNLOCK(adapter); 1572 1573 em_rxeof(adapter, count); 1574 1575 EM_TX_LOCK(adapter); 1576 em_txeof(adapter); 1577 1578 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1579 em_start_locked(ifp); 1580 EM_TX_UNLOCK(adapter); 1581 } 1582 #endif /* DEVICE_POLLING */ 1583 1584 #ifdef EM_LEGACY_IRQ 1585 /********************************************************************* 1586 * 1587 * Legacy Interrupt Service routine 1588 * 1589 *********************************************************************/ 1590 1591 static void 1592 em_intr(void *arg) 1593 { 1594 struct adapter *adapter = arg; 1595 struct ifnet *ifp = adapter->ifp; 1596 u32 reg_icr; 1597 1598 1599 if (ifp->if_capenable & IFCAP_POLLING) 1600 return; 1601 1602 EM_CORE_LOCK(adapter); 1603 for (;;) { 1604 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1605 1606 if (adapter->hw.mac.type >= e1000_82571 && 1607 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1608 break; 1609 else if (reg_icr == 0) 1610 break; 1611 1612 /* 1613 * XXX: some laptops trigger several spurious interrupts 1614 * on em(4) when in the resume cycle. The ICR register 1615 * reports all-ones value in this case. Processing such 1616 * interrupts would lead to a freeze. I don't know why. 1617 */ 1618 if (reg_icr == 0xffffffff) 1619 break; 1620 1621 EM_CORE_UNLOCK(adapter); 1622 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1623 em_rxeof(adapter, -1); 1624 EM_TX_LOCK(adapter); 1625 em_txeof(adapter); 1626 EM_TX_UNLOCK(adapter); 1627 } 1628 EM_CORE_LOCK(adapter); 1629 1630 /* Link status change */ 1631 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1632 callout_stop(&adapter->timer); 1633 adapter->hw.mac.get_link_status = 1; 1634 em_update_link_status(adapter); 1635 /* Deal with TX cruft when link lost */ 1636 em_tx_purge(adapter); 1637 callout_reset(&adapter->timer, hz, 1638 em_local_timer, adapter); 1639 } 1640 1641 if (reg_icr & E1000_ICR_RXO) 1642 adapter->rx_overruns++; 1643 } 1644 EM_CORE_UNLOCK(adapter); 1645 1646 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1647 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1648 em_start(ifp); 1649 } 1650 1651 #else /* EM_FAST_IRQ, then fast interrupt routines only */ 1652 1653 static void 1654 em_handle_link(void *context, int pending) 1655 { 1656 struct adapter *adapter = context; 1657 struct ifnet *ifp = adapter->ifp; 1658 1659 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1660 return; 1661 1662 EM_CORE_LOCK(adapter); 1663 callout_stop(&adapter->timer); 1664 em_update_link_status(adapter); 1665 /* Deal with TX cruft when link lost */ 1666 em_tx_purge(adapter); 1667 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1668 EM_CORE_UNLOCK(adapter); 1669 } 1670 1671 1672 /* Combined RX/TX handler, used by Legacy and MSI */ 1673 static void 1674 em_handle_rxtx(void *context, int pending) 1675 { 1676 struct adapter *adapter = context; 1677 struct ifnet *ifp = adapter->ifp; 1678 1679 1680 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1681 if (em_rxeof(adapter, adapter->rx_process_limit) != 0) 1682 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1683 EM_TX_LOCK(adapter); 1684 em_txeof(adapter); 1685 1686 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1687 em_start_locked(ifp); 1688 EM_TX_UNLOCK(adapter); 1689 } 1690 1691 em_enable_intr(adapter); 1692 } 1693 1694 static void 1695 em_handle_rx(void *context, int pending) 1696 { 1697 struct adapter *adapter = context; 1698 struct ifnet *ifp = adapter->ifp; 1699 1700 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1701 (em_rxeof(adapter, adapter->rx_process_limit) != 0)) 1702 taskqueue_enqueue(adapter->tq, &adapter->rx_task); 1703 1704 } 1705 1706 static void 1707 em_handle_tx(void *context, int pending) 1708 { 1709 struct adapter *adapter = context; 1710 struct ifnet *ifp = adapter->ifp; 1711 1712 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1713 EM_TX_LOCK(adapter); 1714 em_txeof(adapter); 1715 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1716 em_start_locked(ifp); 1717 EM_TX_UNLOCK(adapter); 1718 } 1719 } 1720 1721 /********************************************************************* 1722 * 1723 * Fast Legacy/MSI Combined Interrupt Service routine 1724 * 1725 *********************************************************************/ 1726 #if __FreeBSD_version < 700000 1727 #define FILTER_STRAY 1728 #define FILTER_HANDLED 1729 static void 1730 #else 1731 static int 1732 #endif 1733 em_irq_fast(void *arg) 1734 { 1735 struct adapter *adapter = arg; 1736 struct ifnet *ifp; 1737 u32 reg_icr; 1738 1739 ifp = adapter->ifp; 1740 1741 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1742 1743 /* Hot eject? */ 1744 if (reg_icr == 0xffffffff) 1745 return FILTER_STRAY; 1746 1747 /* Definitely not our interrupt. */ 1748 if (reg_icr == 0x0) 1749 return FILTER_STRAY; 1750 1751 /* 1752 * Starting with the 82571 chip, bit 31 should be used to 1753 * determine whether the interrupt belongs to us. 1754 */ 1755 if (adapter->hw.mac.type >= e1000_82571 && 1756 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1757 return FILTER_STRAY; 1758 1759 /* 1760 * Mask interrupts until the taskqueue is finished running. This is 1761 * cheap, just assume that it is needed. This also works around the 1762 * MSI message reordering errata on certain systems. 1763 */ 1764 em_disable_intr(adapter); 1765 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1766 1767 /* Link status change */ 1768 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1769 adapter->hw.mac.get_link_status = 1; 1770 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1771 } 1772 1773 if (reg_icr & E1000_ICR_RXO) 1774 adapter->rx_overruns++; 1775 return FILTER_HANDLED; 1776 } 1777 1778 /********************************************************************* 1779 * 1780 * MSIX Interrupt Service Routines 1781 * 1782 **********************************************************************/ 1783 #define EM_MSIX_TX 0x00040000 1784 #define EM_MSIX_RX 0x00010000 1785 #define EM_MSIX_LINK 0x00100000 1786 1787 static void 1788 em_msix_tx(void *arg) 1789 { 1790 struct adapter *adapter = arg; 1791 struct ifnet *ifp = adapter->ifp; 1792 1793 ++adapter->tx_irq; 1794 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1795 EM_TX_LOCK(adapter); 1796 em_txeof(adapter); 1797 EM_TX_UNLOCK(adapter); 1798 taskqueue_enqueue(adapter->tq, &adapter->tx_task); 1799 } 1800 /* Reenable this interrupt */ 1801 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_TX); 1802 return; 1803 } 1804 1805 /********************************************************************* 1806 * 1807 * MSIX RX Interrupt Service routine 1808 * 1809 **********************************************************************/ 1810 1811 static void 1812 em_msix_rx(void *arg) 1813 { 1814 struct adapter *adapter = arg; 1815 struct ifnet *ifp = adapter->ifp; 1816 1817 ++adapter->rx_irq; 1818 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1819 (em_rxeof(adapter, adapter->rx_process_limit) != 0)) 1820 taskqueue_enqueue(adapter->tq, &adapter->rx_task); 1821 /* Reenable this interrupt */ 1822 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_RX); 1823 return; 1824 } 1825 1826 /********************************************************************* 1827 * 1828 * MSIX Link Fast Interrupt Service routine 1829 * 1830 **********************************************************************/ 1831 1832 static void 1833 em_msix_link(void *arg) 1834 { 1835 struct adapter *adapter = arg; 1836 u32 reg_icr; 1837 1838 ++adapter->link_irq; 1839 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1840 1841 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1842 adapter->hw.mac.get_link_status = 1; 1843 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1844 } 1845 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1846 EM_MSIX_LINK | E1000_IMS_LSC); 1847 return; 1848 } 1849 #endif /* EM_FAST_IRQ */ 1850 1851 /********************************************************************* 1852 * 1853 * Media Ioctl callback 1854 * 1855 * This routine is called whenever the user queries the status of 1856 * the interface using ifconfig. 1857 * 1858 **********************************************************************/ 1859 static void 1860 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1861 { 1862 struct adapter *adapter = ifp->if_softc; 1863 u_char fiber_type = IFM_1000_SX; 1864 1865 INIT_DEBUGOUT("em_media_status: begin"); 1866 1867 EM_CORE_LOCK(adapter); 1868 em_update_link_status(adapter); 1869 1870 ifmr->ifm_status = IFM_AVALID; 1871 ifmr->ifm_active = IFM_ETHER; 1872 1873 if (!adapter->link_active) { 1874 EM_CORE_UNLOCK(adapter); 1875 return; 1876 } 1877 1878 ifmr->ifm_status |= IFM_ACTIVE; 1879 1880 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1881 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1882 if (adapter->hw.mac.type == e1000_82545) 1883 fiber_type = IFM_1000_LX; 1884 ifmr->ifm_active |= fiber_type | IFM_FDX; 1885 } else { 1886 switch (adapter->link_speed) { 1887 case 10: 1888 ifmr->ifm_active |= IFM_10_T; 1889 break; 1890 case 100: 1891 ifmr->ifm_active |= IFM_100_TX; 1892 break; 1893 case 1000: 1894 ifmr->ifm_active |= IFM_1000_T; 1895 break; 1896 } 1897 if (adapter->link_duplex == FULL_DUPLEX) 1898 ifmr->ifm_active |= IFM_FDX; 1899 else 1900 ifmr->ifm_active |= IFM_HDX; 1901 } 1902 EM_CORE_UNLOCK(adapter); 1903 } 1904 1905 /********************************************************************* 1906 * 1907 * Media Ioctl callback 1908 * 1909 * This routine is called when the user changes speed/duplex using 1910 * media/mediopt option with ifconfig. 1911 * 1912 **********************************************************************/ 1913 static int 1914 em_media_change(struct ifnet *ifp) 1915 { 1916 struct adapter *adapter = ifp->if_softc; 1917 struct ifmedia *ifm = &adapter->media; 1918 1919 INIT_DEBUGOUT("em_media_change: begin"); 1920 1921 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1922 return (EINVAL); 1923 1924 EM_CORE_LOCK(adapter); 1925 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1926 case IFM_AUTO: 1927 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1928 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1929 break; 1930 case IFM_1000_LX: 1931 case IFM_1000_SX: 1932 case IFM_1000_T: 1933 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1934 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1935 break; 1936 case IFM_100_TX: 1937 adapter->hw.mac.autoneg = FALSE; 1938 adapter->hw.phy.autoneg_advertised = 0; 1939 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1940 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1941 else 1942 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1943 break; 1944 case IFM_10_T: 1945 adapter->hw.mac.autoneg = FALSE; 1946 adapter->hw.phy.autoneg_advertised = 0; 1947 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1948 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1949 else 1950 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1951 break; 1952 default: 1953 device_printf(adapter->dev, "Unsupported media type\n"); 1954 } 1955 1956 /* As the speed/duplex settings my have changed we need to 1957 * reset the PHY. 1958 */ 1959 adapter->hw.phy.reset_disable = FALSE; 1960 1961 em_init_locked(adapter); 1962 EM_CORE_UNLOCK(adapter); 1963 1964 return (0); 1965 } 1966 1967 /********************************************************************* 1968 * 1969 * This routine maps the mbufs to tx descriptors. 1970 * 1971 * return 0 on success, positive on failure 1972 **********************************************************************/ 1973 1974 static int 1975 em_xmit(struct adapter *adapter, struct mbuf **m_headp) 1976 { 1977 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1978 bus_dmamap_t map; 1979 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1980 struct e1000_tx_desc *ctxd = NULL; 1981 struct mbuf *m_head; 1982 u32 txd_upper, txd_lower, txd_used, txd_saved; 1983 int nsegs, i, j, first, last = 0; 1984 int error, do_tso, tso_desc = 0; 1985 #if __FreeBSD_version < 700000 1986 struct m_tag *mtag; 1987 #endif 1988 m_head = *m_headp; 1989 txd_upper = txd_lower = txd_used = txd_saved = 0; 1990 1991 #if __FreeBSD_version >= 700000 1992 do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); 1993 #else 1994 do_tso = 0; 1995 #endif 1996 1997 /* 1998 * Force a cleanup if number of TX descriptors 1999 * available hits the threshold 2000 */ 2001 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 2002 em_txeof(adapter); 2003 /* Now do we at least have a minimal? */ 2004 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 2005 adapter->no_tx_desc_avail1++; 2006 return (ENOBUFS); 2007 } 2008 } 2009 2010 2011 /* 2012 * TSO workaround: 2013 * If an mbuf is only header we need 2014 * to pull 4 bytes of data into it. 2015 */ 2016 if (do_tso && (m_head->m_len <= M_TSO_LEN)) { 2017 m_head = m_pullup(m_head, M_TSO_LEN + 4); 2018 *m_headp = m_head; 2019 if (m_head == NULL) 2020 return (ENOBUFS); 2021 } 2022 2023 /* 2024 * Map the packet for DMA 2025 * 2026 * Capture the first descriptor index, 2027 * this descriptor will have the index 2028 * of the EOP which is the only one that 2029 * now gets a DONE bit writeback. 2030 */ 2031 first = adapter->next_avail_tx_desc; 2032 tx_buffer = &adapter->tx_buffer_area[first]; 2033 tx_buffer_mapped = tx_buffer; 2034 map = tx_buffer->map; 2035 2036 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2037 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2038 2039 /* 2040 * There are two types of errors we can (try) to handle: 2041 * - EFBIG means the mbuf chain was too long and bus_dma ran 2042 * out of segments. Defragment the mbuf chain and try again. 2043 * - ENOMEM means bus_dma could not obtain enough bounce buffers 2044 * at this point in time. Defer sending and try again later. 2045 * All other errors, in particular EINVAL, are fatal and prevent the 2046 * mbuf chain from ever going through. Drop it and report error. 2047 */ 2048 if (error == EFBIG) { 2049 struct mbuf *m; 2050 2051 m = m_defrag(*m_headp, M_DONTWAIT); 2052 if (m == NULL) { 2053 adapter->mbuf_alloc_failed++; 2054 m_freem(*m_headp); 2055 *m_headp = NULL; 2056 return (ENOBUFS); 2057 } 2058 *m_headp = m; 2059 2060 /* Try it again */ 2061 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2062 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2063 2064 if (error == ENOMEM) { 2065 adapter->no_tx_dma_setup++; 2066 return (error); 2067 } else if (error != 0) { 2068 adapter->no_tx_dma_setup++; 2069 m_freem(*m_headp); 2070 *m_headp = NULL; 2071 return (error); 2072 } 2073 } else if (error == ENOMEM) { 2074 adapter->no_tx_dma_setup++; 2075 return (error); 2076 } else if (error != 0) { 2077 adapter->no_tx_dma_setup++; 2078 m_freem(*m_headp); 2079 *m_headp = NULL; 2080 return (error); 2081 } 2082 2083 /* 2084 * TSO Hardware workaround, if this packet is not 2085 * TSO, and is only a single descriptor long, and 2086 * it follows a TSO burst, then we need to add a 2087 * sentinel descriptor to prevent premature writeback. 2088 */ 2089 if ((do_tso == 0) && (adapter->tx_tso == TRUE)) { 2090 if (nsegs == 1) 2091 tso_desc = TRUE; 2092 adapter->tx_tso = FALSE; 2093 } 2094 2095 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 2096 adapter->no_tx_desc_avail2++; 2097 bus_dmamap_unload(adapter->txtag, map); 2098 return (ENOBUFS); 2099 } 2100 m_head = *m_headp; 2101 2102 /* Do hardware assists */ 2103 #if __FreeBSD_version >= 700000 2104 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 2105 error = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 2106 if (error != TRUE) 2107 return (ENXIO); /* something foobar */ 2108 /* we need to make a final sentinel transmit desc */ 2109 tso_desc = TRUE; 2110 } else 2111 #endif 2112 #ifndef EM_TIMESYNC 2113 /* 2114 ** Timesync needs to check the packet header 2115 ** so call checksum code to do so, but don't 2116 ** penalize the code if not defined. 2117 */ 2118 if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) 2119 #endif 2120 em_transmit_checksum_setup(adapter, m_head, 2121 &txd_upper, &txd_lower); 2122 2123 i = adapter->next_avail_tx_desc; 2124 if (adapter->pcix_82544) 2125 txd_saved = i; 2126 2127 /* Set up our transmit descriptors */ 2128 for (j = 0; j < nsegs; j++) { 2129 bus_size_t seg_len; 2130 bus_addr_t seg_addr; 2131 /* If adapter is 82544 and on PCIX bus */ 2132 if(adapter->pcix_82544) { 2133 DESC_ARRAY desc_array; 2134 u32 array_elements, counter; 2135 /* 2136 * Check the Address and Length combination and 2137 * split the data accordingly 2138 */ 2139 array_elements = em_fill_descriptors(segs[j].ds_addr, 2140 segs[j].ds_len, &desc_array); 2141 for (counter = 0; counter < array_elements; counter++) { 2142 if (txd_used == adapter->num_tx_desc_avail) { 2143 adapter->next_avail_tx_desc = txd_saved; 2144 adapter->no_tx_desc_avail2++; 2145 bus_dmamap_unload(adapter->txtag, map); 2146 return (ENOBUFS); 2147 } 2148 tx_buffer = &adapter->tx_buffer_area[i]; 2149 ctxd = &adapter->tx_desc_base[i]; 2150 ctxd->buffer_addr = htole64( 2151 desc_array.descriptor[counter].address); 2152 ctxd->lower.data = htole32( 2153 (adapter->txd_cmd | txd_lower | (u16) 2154 desc_array.descriptor[counter].length)); 2155 ctxd->upper.data = 2156 htole32((txd_upper)); 2157 last = i; 2158 if (++i == adapter->num_tx_desc) 2159 i = 0; 2160 tx_buffer->m_head = NULL; 2161 tx_buffer->next_eop = -1; 2162 txd_used++; 2163 } 2164 } else { 2165 tx_buffer = &adapter->tx_buffer_area[i]; 2166 ctxd = &adapter->tx_desc_base[i]; 2167 seg_addr = segs[j].ds_addr; 2168 seg_len = segs[j].ds_len; 2169 /* 2170 ** TSO Workaround: 2171 ** If this is the last descriptor, we want to 2172 ** split it so we have a small final sentinel 2173 */ 2174 if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { 2175 seg_len -= 4; 2176 ctxd->buffer_addr = htole64(seg_addr); 2177 ctxd->lower.data = htole32( 2178 adapter->txd_cmd | txd_lower | seg_len); 2179 ctxd->upper.data = 2180 htole32(txd_upper); 2181 if (++i == adapter->num_tx_desc) 2182 i = 0; 2183 /* Now make the sentinel */ 2184 ++txd_used; /* using an extra txd */ 2185 ctxd = &adapter->tx_desc_base[i]; 2186 tx_buffer = &adapter->tx_buffer_area[i]; 2187 ctxd->buffer_addr = 2188 htole64(seg_addr + seg_len); 2189 ctxd->lower.data = htole32( 2190 adapter->txd_cmd | txd_lower | 4); 2191 ctxd->upper.data = 2192 htole32(txd_upper); 2193 last = i; 2194 if (++i == adapter->num_tx_desc) 2195 i = 0; 2196 } else { 2197 ctxd->buffer_addr = htole64(seg_addr); 2198 ctxd->lower.data = htole32( 2199 adapter->txd_cmd | txd_lower | seg_len); 2200 ctxd->upper.data = 2201 htole32(txd_upper); 2202 last = i; 2203 if (++i == adapter->num_tx_desc) 2204 i = 0; 2205 } 2206 tx_buffer->m_head = NULL; 2207 tx_buffer->next_eop = -1; 2208 } 2209 } 2210 2211 adapter->next_avail_tx_desc = i; 2212 if (adapter->pcix_82544) 2213 adapter->num_tx_desc_avail -= txd_used; 2214 else { 2215 adapter->num_tx_desc_avail -= nsegs; 2216 if (tso_desc) /* TSO used an extra for sentinel */ 2217 adapter->num_tx_desc_avail -= txd_used; 2218 } 2219 2220 /* 2221 ** Handle VLAN tag, this is the 2222 ** biggest difference between 2223 ** 6.x and 7 2224 */ 2225 #if __FreeBSD_version < 700000 2226 /* Find out if we are in vlan mode. */ 2227 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 2228 if (mtag != NULL) { 2229 ctxd->upper.fields.special = 2230 htole16(VLAN_TAG_VALUE(mtag)); 2231 #else /* FreeBSD 7 */ 2232 if (m_head->m_flags & M_VLANTAG) { 2233 /* Set the vlan id. */ 2234 ctxd->upper.fields.special = 2235 htole16(m_head->m_pkthdr.ether_vtag); 2236 #endif 2237 /* Tell hardware to add tag */ 2238 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 2239 } 2240 2241 tx_buffer->m_head = m_head; 2242 tx_buffer_mapped->map = tx_buffer->map; 2243 tx_buffer->map = map; 2244 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 2245 2246 /* 2247 * Last Descriptor of Packet 2248 * needs End Of Packet (EOP) 2249 * and Report Status (RS) 2250 */ 2251 ctxd->lower.data |= 2252 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 2253 /* 2254 * Keep track in the first buffer which 2255 * descriptor will be written back 2256 */ 2257 tx_buffer = &adapter->tx_buffer_area[first]; 2258 tx_buffer->next_eop = last; 2259 2260 /* 2261 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 2262 * that this frame is available to transmit. 2263 */ 2264 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2266 if (adapter->hw.mac.type == e1000_82547 && 2267 adapter->link_duplex == HALF_DUPLEX) 2268 em_82547_move_tail(adapter); 2269 else { 2270 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 2271 if (adapter->hw.mac.type == e1000_82547) 2272 em_82547_update_fifo_head(adapter, 2273 m_head->m_pkthdr.len); 2274 } 2275 2276 #ifdef EM_TIMESYNC 2277 if (ctxd->upper.data & E1000_TXD_EXTCMD_TSTAMP) { 2278 HW_DEBUGOUT( "@@@ Timestamp bit is set in transmit descriptor\n" ); 2279 } 2280 #endif 2281 return (0); 2282 } 2283 2284 /********************************************************************* 2285 * 2286 * 82547 workaround to avoid controller hang in half-duplex environment. 2287 * The workaround is to avoid queuing a large packet that would span 2288 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 2289 * in this case. We do that only when FIFO is quiescent. 2290 * 2291 **********************************************************************/ 2292 static void 2293 em_82547_move_tail(void *arg) 2294 { 2295 struct adapter *adapter = arg; 2296 struct e1000_tx_desc *tx_desc; 2297 u16 hw_tdt, sw_tdt, length = 0; 2298 bool eop = 0; 2299 2300 EM_TX_LOCK_ASSERT(adapter); 2301 2302 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 2303 sw_tdt = adapter->next_avail_tx_desc; 2304 2305 while (hw_tdt != sw_tdt) { 2306 tx_desc = &adapter->tx_desc_base[hw_tdt]; 2307 length += tx_desc->lower.flags.length; 2308 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 2309 if (++hw_tdt == adapter->num_tx_desc) 2310 hw_tdt = 0; 2311 2312 if (eop) { 2313 if (em_82547_fifo_workaround(adapter, length)) { 2314 adapter->tx_fifo_wrk_cnt++; 2315 callout_reset(&adapter->tx_fifo_timer, 1, 2316 em_82547_move_tail, adapter); 2317 break; 2318 } 2319 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 2320 em_82547_update_fifo_head(adapter, length); 2321 length = 0; 2322 } 2323 } 2324 } 2325 2326 static int 2327 em_82547_fifo_workaround(struct adapter *adapter, int len) 2328 { 2329 int fifo_space, fifo_pkt_len; 2330 2331 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2332 2333 if (adapter->link_duplex == HALF_DUPLEX) { 2334 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 2335 2336 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 2337 if (em_82547_tx_fifo_reset(adapter)) 2338 return (0); 2339 else 2340 return (1); 2341 } 2342 } 2343 2344 return (0); 2345 } 2346 2347 static void 2348 em_82547_update_fifo_head(struct adapter *adapter, int len) 2349 { 2350 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2351 2352 /* tx_fifo_head is always 16 byte aligned */ 2353 adapter->tx_fifo_head += fifo_pkt_len; 2354 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { 2355 adapter->tx_fifo_head -= adapter->tx_fifo_size; 2356 } 2357 } 2358 2359 2360 static int 2361 em_82547_tx_fifo_reset(struct adapter *adapter) 2362 { 2363 u32 tctl; 2364 2365 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 2366 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 2367 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 2368 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 2369 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 2370 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 2371 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 2372 /* Disable TX unit */ 2373 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2374 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 2375 tctl & ~E1000_TCTL_EN); 2376 2377 /* Reset FIFO pointers */ 2378 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 2379 adapter->tx_head_addr); 2380 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 2381 adapter->tx_head_addr); 2382 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 2383 adapter->tx_head_addr); 2384 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 2385 adapter->tx_head_addr); 2386 2387 /* Re-enable TX unit */ 2388 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2389 E1000_WRITE_FLUSH(&adapter->hw); 2390 2391 adapter->tx_fifo_head = 0; 2392 adapter->tx_fifo_reset_cnt++; 2393 2394 return (TRUE); 2395 } 2396 else { 2397 return (FALSE); 2398 } 2399 } 2400 2401 static void 2402 em_set_promisc(struct adapter *adapter) 2403 { 2404 struct ifnet *ifp = adapter->ifp; 2405 u32 reg_rctl; 2406 2407 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2408 2409 if (ifp->if_flags & IFF_PROMISC) { 2410 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2411 /* Turn this on if you want to see bad packets */ 2412 if (em_debug_sbp) 2413 reg_rctl |= E1000_RCTL_SBP; 2414 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2415 } else if (ifp->if_flags & IFF_ALLMULTI) { 2416 reg_rctl |= E1000_RCTL_MPE; 2417 reg_rctl &= ~E1000_RCTL_UPE; 2418 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2419 } 2420 } 2421 2422 static void 2423 em_disable_promisc(struct adapter *adapter) 2424 { 2425 u32 reg_rctl; 2426 2427 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2428 2429 reg_rctl &= (~E1000_RCTL_UPE); 2430 reg_rctl &= (~E1000_RCTL_MPE); 2431 reg_rctl &= (~E1000_RCTL_SBP); 2432 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2433 } 2434 2435 2436 /********************************************************************* 2437 * Multicast Update 2438 * 2439 * This routine is called whenever multicast address list is updated. 2440 * 2441 **********************************************************************/ 2442 2443 static void 2444 em_set_multi(struct adapter *adapter) 2445 { 2446 struct ifnet *ifp = adapter->ifp; 2447 struct ifmultiaddr *ifma; 2448 u32 reg_rctl = 0; 2449 u8 mta[512]; /* Largest MTS is 4096 bits */ 2450 int mcnt = 0; 2451 2452 IOCTL_DEBUGOUT("em_set_multi: begin"); 2453 2454 if (adapter->hw.mac.type == e1000_82542 && 2455 adapter->hw.revision_id == E1000_REVISION_2) { 2456 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2457 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2458 e1000_pci_clear_mwi(&adapter->hw); 2459 reg_rctl |= E1000_RCTL_RST; 2460 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2461 msec_delay(5); 2462 } 2463 2464 IF_ADDR_LOCK(ifp); 2465 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2466 if (ifma->ifma_addr->sa_family != AF_LINK) 2467 continue; 2468 2469 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2470 break; 2471 2472 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2473 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN); 2474 mcnt++; 2475 } 2476 IF_ADDR_UNLOCK(ifp); 2477 2478 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2479 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2480 reg_rctl |= E1000_RCTL_MPE; 2481 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2482 } else 2483 e1000_update_mc_addr_list(&adapter->hw, mta, 2484 mcnt, 1, adapter->hw.mac.rar_entry_count); 2485 2486 if (adapter->hw.mac.type == e1000_82542 && 2487 adapter->hw.revision_id == E1000_REVISION_2) { 2488 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2489 reg_rctl &= ~E1000_RCTL_RST; 2490 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2491 msec_delay(5); 2492 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2493 e1000_pci_set_mwi(&adapter->hw); 2494 } 2495 } 2496 2497 2498 /********************************************************************* 2499 * Timer routine 2500 * 2501 * This routine checks for link status and updates statistics. 2502 * 2503 **********************************************************************/ 2504 2505 static void 2506 em_local_timer(void *arg) 2507 { 2508 struct adapter *adapter = arg; 2509 struct ifnet *ifp = adapter->ifp; 2510 2511 EM_CORE_LOCK_ASSERT(adapter); 2512 2513 em_update_link_status(adapter); 2514 em_update_stats_counters(adapter); 2515 2516 /* Reset LAA into RAR[0] on 82571 */ 2517 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2518 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2519 2520 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 2521 em_print_hw_stats(adapter); 2522 2523 em_smartspeed(adapter); 2524 2525 /* 2526 * Each second we check the watchdog to 2527 * protect against hardware hangs. 2528 */ 2529 em_watchdog(adapter); 2530 2531 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 2532 2533 } 2534 2535 static void 2536 em_update_link_status(struct adapter *adapter) 2537 { 2538 struct e1000_hw *hw = &adapter->hw; 2539 struct ifnet *ifp = adapter->ifp; 2540 device_t dev = adapter->dev; 2541 u32 link_check = 0; 2542 2543 /* Get the cached link value or read phy for real */ 2544 switch (hw->phy.media_type) { 2545 case e1000_media_type_copper: 2546 if (hw->mac.get_link_status) { 2547 /* Do the work to read phy */ 2548 e1000_check_for_link(hw); 2549 link_check = !hw->mac.get_link_status; 2550 } else 2551 link_check = TRUE; 2552 break; 2553 case e1000_media_type_fiber: 2554 e1000_check_for_link(hw); 2555 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 2556 E1000_STATUS_LU); 2557 break; 2558 case e1000_media_type_internal_serdes: 2559 e1000_check_for_link(hw); 2560 link_check = adapter->hw.mac.serdes_has_link; 2561 break; 2562 default: 2563 case e1000_media_type_unknown: 2564 break; 2565 } 2566 2567 /* Now check for a transition */ 2568 if (link_check && (adapter->link_active == 0)) { 2569 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2570 &adapter->link_duplex); 2571 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2572 if ((adapter->link_speed != SPEED_1000) && 2573 ((hw->mac.type == e1000_82571) || 2574 (hw->mac.type == e1000_82572))) { 2575 int tarc0; 2576 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2577 tarc0 &= ~SPEED_MODE_BIT; 2578 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2579 } 2580 if (bootverbose) 2581 device_printf(dev, "Link is up %d Mbps %s\n", 2582 adapter->link_speed, 2583 ((adapter->link_duplex == FULL_DUPLEX) ? 2584 "Full Duplex" : "Half Duplex")); 2585 adapter->link_active = 1; 2586 adapter->smartspeed = 0; 2587 ifp->if_baudrate = adapter->link_speed * 1000000; 2588 if_link_state_change(ifp, LINK_STATE_UP); 2589 } else if (!link_check && (adapter->link_active == 1)) { 2590 ifp->if_baudrate = adapter->link_speed = 0; 2591 adapter->link_duplex = 0; 2592 if (bootverbose) 2593 device_printf(dev, "Link is Down\n"); 2594 adapter->link_active = 0; 2595 /* Link down, disable watchdog */ 2596 adapter->watchdog_timer = FALSE; 2597 if_link_state_change(ifp, LINK_STATE_DOWN); 2598 } 2599 } 2600 2601 /********************************************************************* 2602 * 2603 * This routine disables all traffic on the adapter by issuing a 2604 * global reset on the MAC and deallocates TX/RX buffers. 2605 * 2606 * This routine should always be called with BOTH the CORE 2607 * and TX locks. 2608 **********************************************************************/ 2609 2610 static void 2611 em_stop(void *arg) 2612 { 2613 struct adapter *adapter = arg; 2614 struct ifnet *ifp = adapter->ifp; 2615 2616 EM_CORE_LOCK_ASSERT(adapter); 2617 EM_TX_LOCK_ASSERT(adapter); 2618 2619 INIT_DEBUGOUT("em_stop: begin"); 2620 2621 em_disable_intr(adapter); 2622 callout_stop(&adapter->timer); 2623 callout_stop(&adapter->tx_fifo_timer); 2624 2625 /* Tell the stack that the interface is no longer active */ 2626 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2627 2628 #ifdef EM_TIMESYNC 2629 /* Disable IEEE 1588 Time hardware */ 2630 if ((adapter->hw.mac.type == e1000_82574) || 2631 (adapter->hw.mac.type == e1000_ich10lan)) 2632 em_tsync_disable(adapter); 2633 #endif 2634 2635 e1000_reset_hw(&adapter->hw); 2636 if (adapter->hw.mac.type >= e1000_82544) 2637 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2638 } 2639 2640 2641 /********************************************************************* 2642 * 2643 * Determine hardware revision. 2644 * 2645 **********************************************************************/ 2646 static void 2647 em_identify_hardware(struct adapter *adapter) 2648 { 2649 device_t dev = adapter->dev; 2650 2651 /* Make sure our PCI config space has the necessary stuff set */ 2652 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2653 if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && 2654 (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) { 2655 device_printf(dev, "Memory Access and/or Bus Master bits " 2656 "were not set!\n"); 2657 adapter->hw.bus.pci_cmd_word |= 2658 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 2659 pci_write_config(dev, PCIR_COMMAND, 2660 adapter->hw.bus.pci_cmd_word, 2); 2661 } 2662 2663 /* Save off the information about this board */ 2664 adapter->hw.vendor_id = pci_get_vendor(dev); 2665 adapter->hw.device_id = pci_get_device(dev); 2666 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2667 adapter->hw.subsystem_vendor_id = 2668 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2669 adapter->hw.subsystem_device_id = 2670 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2671 2672 /* Do Shared Code Init and Setup */ 2673 if (e1000_set_mac_type(&adapter->hw)) { 2674 device_printf(dev, "Setup init failure\n"); 2675 return; 2676 } 2677 } 2678 2679 static int 2680 em_allocate_pci_resources(struct adapter *adapter) 2681 { 2682 device_t dev = adapter->dev; 2683 int val, rid, error = E1000_SUCCESS; 2684 2685 rid = PCIR_BAR(0); 2686 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2687 &rid, RF_ACTIVE); 2688 if (adapter->memory == NULL) { 2689 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2690 return (ENXIO); 2691 } 2692 adapter->osdep.mem_bus_space_tag = 2693 rman_get_bustag(adapter->memory); 2694 adapter->osdep.mem_bus_space_handle = 2695 rman_get_bushandle(adapter->memory); 2696 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 2697 2698 /* Only older adapters use IO mapping */ 2699 if ((adapter->hw.mac.type > e1000_82543) && 2700 (adapter->hw.mac.type < e1000_82571)) { 2701 /* Figure our where our IO BAR is ? */ 2702 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2703 val = pci_read_config(dev, rid, 4); 2704 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2705 adapter->io_rid = rid; 2706 break; 2707 } 2708 rid += 4; 2709 /* check for 64bit BAR */ 2710 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2711 rid += 4; 2712 } 2713 if (rid >= PCIR_CIS) { 2714 device_printf(dev, "Unable to locate IO BAR\n"); 2715 return (ENXIO); 2716 } 2717 adapter->ioport = bus_alloc_resource_any(dev, 2718 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 2719 if (adapter->ioport == NULL) { 2720 device_printf(dev, "Unable to allocate bus resource: " 2721 "ioport\n"); 2722 return (ENXIO); 2723 } 2724 adapter->hw.io_base = 0; 2725 adapter->osdep.io_bus_space_tag = 2726 rman_get_bustag(adapter->ioport); 2727 adapter->osdep.io_bus_space_handle = 2728 rman_get_bushandle(adapter->ioport); 2729 } 2730 2731 /* 2732 ** Init the resource arrays 2733 ** used by MSIX setup 2734 */ 2735 for (int i = 0; i < 3; i++) { 2736 adapter->rid[i] = i + 1; /* MSI/X RID starts at 1 */ 2737 adapter->tag[i] = NULL; 2738 adapter->res[i] = NULL; 2739 } 2740 2741 /* 2742 * Setup MSI/X or MSI if PCI Express 2743 */ 2744 if (em_enable_msi) 2745 adapter->msi = em_setup_msix(adapter); 2746 2747 adapter->hw.back = &adapter->osdep; 2748 2749 return (error); 2750 } 2751 2752 /********************************************************************* 2753 * 2754 * Setup the Legacy or MSI Interrupt handler 2755 * 2756 **********************************************************************/ 2757 int 2758 em_allocate_legacy(struct adapter *adapter) 2759 { 2760 device_t dev = adapter->dev; 2761 int error; 2762 2763 /* Manually turn off all interrupts */ 2764 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2765 2766 /* Legacy RID is 0 */ 2767 if (adapter->msi == 0) 2768 adapter->rid[0] = 0; 2769 2770 /* We allocate a single interrupt resource */ 2771 adapter->res[0] = bus_alloc_resource_any(dev, 2772 SYS_RES_IRQ, &adapter->rid[0], RF_SHAREABLE | RF_ACTIVE); 2773 if (adapter->res[0] == NULL) { 2774 device_printf(dev, "Unable to allocate bus resource: " 2775 "interrupt\n"); 2776 return (ENXIO); 2777 } 2778 2779 #ifdef EM_LEGACY_IRQ 2780 /* We do Legacy setup */ 2781 if ((error = bus_setup_intr(dev, adapter->res[0], 2782 #if __FreeBSD_version > 700000 2783 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_intr, adapter, 2784 #else /* 6.X */ 2785 INTR_TYPE_NET | INTR_MPSAFE, em_intr, adapter, 2786 #endif 2787 &adapter->tag[0])) != 0) { 2788 device_printf(dev, "Failed to register interrupt handler"); 2789 return (error); 2790 } 2791 2792 #else /* FAST_IRQ */ 2793 /* 2794 * Try allocating a fast interrupt and the associated deferred 2795 * processing contexts. 2796 */ 2797 TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter); 2798 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2799 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2800 taskqueue_thread_enqueue, &adapter->tq); 2801 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2802 device_get_nameunit(adapter->dev)); 2803 #if __FreeBSD_version < 700000 2804 if ((error = bus_setup_intr(dev, adapter->res[0], 2805 INTR_TYPE_NET | INTR_FAST, em_irq_fast, adapter, 2806 #else 2807 if ((error = bus_setup_intr(dev, adapter->res[0], 2808 INTR_TYPE_NET, em_irq_fast, NULL, adapter, 2809 #endif 2810 &adapter->tag[0])) != 0) { 2811 device_printf(dev, "Failed to register fast interrupt " 2812 "handler: %d\n", error); 2813 taskqueue_free(adapter->tq); 2814 adapter->tq = NULL; 2815 return (error); 2816 } 2817 #endif /* EM_LEGACY_IRQ */ 2818 2819 return (0); 2820 } 2821 2822 /********************************************************************* 2823 * 2824 * Setup the MSIX Interrupt handlers 2825 * This is not really Multiqueue, rather 2826 * its just multiple interrupt vectors. 2827 * 2828 **********************************************************************/ 2829 int 2830 em_allocate_msix(struct adapter *adapter) 2831 { 2832 device_t dev = adapter->dev; 2833 int error; 2834 2835 /* Make sure all interrupts are disabled */ 2836 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2837 2838 /* First get the resources */ 2839 for (int i = 0; i < adapter->msi; i++) { 2840 adapter->res[i] = bus_alloc_resource_any(dev, 2841 SYS_RES_IRQ, &adapter->rid[i], RF_ACTIVE); 2842 if (adapter->res[i] == NULL) { 2843 device_printf(dev, 2844 "Unable to allocate bus resource: " 2845 "MSIX Interrupt\n"); 2846 return (ENXIO); 2847 } 2848 } 2849 2850 /* 2851 * Now allocate deferred processing contexts. 2852 */ 2853 TASK_INIT(&adapter->rx_task, 0, em_handle_rx, adapter); 2854 TASK_INIT(&adapter->tx_task, 0, em_handle_tx, adapter); 2855 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2856 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2857 taskqueue_thread_enqueue, &adapter->tq); 2858 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2859 device_get_nameunit(adapter->dev)); 2860 2861 /* 2862 * And setup the interrupt handlers 2863 */ 2864 2865 /* First slot to RX */ 2866 if ((error = bus_setup_intr(dev, adapter->res[0], 2867 #if __FreeBSD_version > 700000 2868 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_msix_rx, adapter, 2869 #else /* 6.X */ 2870 INTR_TYPE_NET | INTR_MPSAFE, em_msix_rx, adapter, 2871 #endif 2872 &adapter->tag[0])) != 0) { 2873 device_printf(dev, "Failed to register RX handler"); 2874 return (error); 2875 } 2876 2877 /* Next TX */ 2878 if ((error = bus_setup_intr(dev, adapter->res[1], 2879 #if __FreeBSD_version > 700000 2880 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_msix_tx, adapter, 2881 #else /* 6.X */ 2882 INTR_TYPE_NET | INTR_MPSAFE, em_msix_tx, adapter, 2883 #endif 2884 &adapter->tag[1])) != 0) { 2885 device_printf(dev, "Failed to register TX handler"); 2886 return (error); 2887 } 2888 2889 /* And Link */ 2890 if ((error = bus_setup_intr(dev, adapter->res[2], 2891 #if __FreeBSD_version > 700000 2892 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_msix_link, adapter, 2893 #else /* 6.X */ 2894 INTR_TYPE_NET | INTR_MPSAFE, em_msix_link, adapter, 2895 #endif 2896 &adapter->tag[2])) != 0) { 2897 device_printf(dev, "Failed to register TX handler"); 2898 return (error); 2899 } 2900 2901 return (0); 2902 } 2903 2904 static void 2905 em_free_pci_resources(struct adapter *adapter) 2906 { 2907 device_t dev = adapter->dev; 2908 2909 /* Make sure the for loop below runs once */ 2910 if (adapter->msi == 0) 2911 adapter->msi = 1; 2912 2913 /* 2914 * First release all the interrupt resources: 2915 * notice that since these are just kept 2916 * in an array we can do the same logic 2917 * whether its MSIX or just legacy. 2918 */ 2919 for (int i = 0; i < adapter->msi; i++) { 2920 if (adapter->tag[i] != NULL) { 2921 bus_teardown_intr(dev, adapter->res[i], 2922 adapter->tag[i]); 2923 adapter->tag[i] = NULL; 2924 } 2925 if (adapter->res[i] != NULL) { 2926 bus_release_resource(dev, SYS_RES_IRQ, 2927 adapter->rid[i], adapter->res[i]); 2928 } 2929 } 2930 2931 if (adapter->msi) 2932 pci_release_msi(dev); 2933 2934 if (adapter->msix != NULL) 2935 bus_release_resource(dev, SYS_RES_MEMORY, 2936 PCIR_BAR(EM_MSIX_BAR), adapter->msix); 2937 2938 if (adapter->memory != NULL) 2939 bus_release_resource(dev, SYS_RES_MEMORY, 2940 PCIR_BAR(0), adapter->memory); 2941 2942 if (adapter->flash != NULL) 2943 bus_release_resource(dev, SYS_RES_MEMORY, 2944 EM_FLASH, adapter->flash); 2945 2946 if (adapter->ioport != NULL) 2947 bus_release_resource(dev, SYS_RES_IOPORT, 2948 adapter->io_rid, adapter->ioport); 2949 } 2950 2951 /* 2952 * Setup MSI/X 2953 */ 2954 static int 2955 em_setup_msix(struct adapter *adapter) 2956 { 2957 device_t dev = adapter->dev; 2958 int val = 0; 2959 2960 if (adapter->hw.mac.type < e1000_82571) 2961 return (0); 2962 2963 /* Setup MSI/X for Hartwell */ 2964 if (adapter->hw.mac.type == e1000_82574) { 2965 /* Map the MSIX BAR */ 2966 int rid = PCIR_BAR(EM_MSIX_BAR); 2967 adapter->msix = bus_alloc_resource_any(dev, 2968 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2969 if (!adapter->msix) { 2970 /* May not be enabled */ 2971 device_printf(adapter->dev, 2972 "Unable to map MSIX table \n"); 2973 goto msi; 2974 } 2975 val = pci_msix_count(dev); 2976 /* 2977 ** 82574 can be configured for 5 but 2978 ** we limit use to 3. 2979 */ 2980 if (val > 3) val = 3; 2981 if ((val) && pci_alloc_msix(dev, &val) == 0) { 2982 device_printf(adapter->dev,"Using MSIX interrupts\n"); 2983 return (val); 2984 } 2985 } 2986 msi: 2987 val = pci_msi_count(dev); 2988 if (val == 1 && pci_alloc_msi(dev, &val) == 0) { 2989 adapter->msi = 1; 2990 device_printf(adapter->dev,"Using MSI interrupt\n"); 2991 return (val); 2992 } 2993 return (0); 2994 } 2995 2996 /********************************************************************* 2997 * 2998 * Initialize the hardware to a configuration 2999 * as specified by the adapter structure. 3000 * 3001 **********************************************************************/ 3002 static int 3003 em_hardware_init(struct adapter *adapter) 3004 { 3005 device_t dev = adapter->dev; 3006 u16 rx_buffer_size; 3007 3008 INIT_DEBUGOUT("em_hardware_init: begin"); 3009 3010 /* Issue a global reset */ 3011 e1000_reset_hw(&adapter->hw); 3012 3013 /* Get control from any management/hw control */ 3014 if (((adapter->hw.mac.type == e1000_82573) || 3015 (adapter->hw.mac.type == e1000_ich8lan) || 3016 (adapter->hw.mac.type == e1000_ich10lan) || 3017 (adapter->hw.mac.type == e1000_ich9lan)) && 3018 e1000_check_mng_mode(&adapter->hw)) 3019 em_get_hw_control(adapter); 3020 3021 /* When hardware is reset, fifo_head is also reset */ 3022 adapter->tx_fifo_head = 0; 3023 3024 /* Set up smart power down as default off on newer adapters. */ 3025 if (!em_smart_pwr_down && (adapter->hw.mac.type == e1000_82571 || 3026 adapter->hw.mac.type == e1000_82572)) { 3027 u16 phy_tmp = 0; 3028 3029 /* Speed up time to link by disabling smart power down. */ 3030 e1000_read_phy_reg(&adapter->hw, 3031 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3032 phy_tmp &= ~IGP02E1000_PM_SPD; 3033 e1000_write_phy_reg(&adapter->hw, 3034 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3035 } 3036 3037 /* 3038 * These parameters control the automatic generation (Tx) and 3039 * response (Rx) to Ethernet PAUSE frames. 3040 * - High water mark should allow for at least two frames to be 3041 * received after sending an XOFF. 3042 * - Low water mark works best when it is very near the high water mark. 3043 * This allows the receiver to restart by sending XON when it has 3044 * drained a bit. Here we use an arbitary value of 1500 which will 3045 * restart after one full frame is pulled from the buffer. There 3046 * could be several smaller frames in the buffer and if so they will 3047 * not trigger the XON until their total number reduces the buffer 3048 * by 1500. 3049 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3050 */ 3051 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 3052 0xffff) << 10 ); 3053 3054 adapter->hw.fc.high_water = rx_buffer_size - 3055 roundup2(adapter->max_frame_size, 1024); 3056 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 3057 3058 if (adapter->hw.mac.type == e1000_80003es2lan) 3059 adapter->hw.fc.pause_time = 0xFFFF; 3060 else 3061 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 3062 adapter->hw.fc.send_xon = TRUE; 3063 adapter->hw.fc.type = e1000_fc_full; 3064 3065 if (e1000_init_hw(&adapter->hw) < 0) { 3066 device_printf(dev, "Hardware Initialization Failed\n"); 3067 return (EIO); 3068 } 3069 3070 e1000_check_for_link(&adapter->hw); 3071 3072 return (0); 3073 } 3074 3075 /********************************************************************* 3076 * 3077 * Setup networking device structure and register an interface. 3078 * 3079 **********************************************************************/ 3080 static void 3081 em_setup_interface(device_t dev, struct adapter *adapter) 3082 { 3083 struct ifnet *ifp; 3084 3085 INIT_DEBUGOUT("em_setup_interface: begin"); 3086 3087 ifp = adapter->ifp = if_alloc(IFT_ETHER); 3088 if (ifp == NULL) 3089 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 3090 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3091 ifp->if_mtu = ETHERMTU; 3092 ifp->if_init = em_init; 3093 ifp->if_softc = adapter; 3094 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3095 ifp->if_ioctl = em_ioctl; 3096 ifp->if_start = em_start; 3097 IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); 3098 ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; 3099 IFQ_SET_READY(&ifp->if_snd); 3100 3101 ether_ifattach(ifp, adapter->hw.mac.addr); 3102 3103 ifp->if_capabilities = ifp->if_capenable = 0; 3104 3105 if (adapter->hw.mac.type >= e1000_82543) { 3106 int version_cap; 3107 #if __FreeBSD_version < 700000 3108 version_cap = IFCAP_HWCSUM; 3109 #else 3110 version_cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 3111 #endif 3112 ifp->if_capabilities |= version_cap; 3113 ifp->if_capenable |= version_cap; 3114 } 3115 3116 #if __FreeBSD_version >= 700000 3117 /* Identify TSO capable adapters */ 3118 if ((adapter->hw.mac.type > e1000_82544) && 3119 (adapter->hw.mac.type != e1000_82547)) 3120 ifp->if_capabilities |= IFCAP_TSO4; 3121 /* 3122 * By default only enable on PCI-E, this 3123 * can be overriden by ifconfig. 3124 */ 3125 if (adapter->hw.mac.type >= e1000_82571) 3126 ifp->if_capenable |= IFCAP_TSO4; 3127 #endif 3128 3129 /* 3130 * Tell the upper layer(s) we support long frames. 3131 */ 3132 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3133 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 3134 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 3135 3136 #ifdef DEVICE_POLLING 3137 ifp->if_capabilities |= IFCAP_POLLING; 3138 #endif 3139 3140 /* 3141 * Specify the media types supported by this adapter and register 3142 * callbacks to update media and link information 3143 */ 3144 ifmedia_init(&adapter->media, IFM_IMASK, 3145 em_media_change, em_media_status); 3146 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3147 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 3148 u_char fiber_type = IFM_1000_SX; /* default type */ 3149 3150 if (adapter->hw.mac.type == e1000_82545) 3151 fiber_type = IFM_1000_LX; 3152 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 3153 0, NULL); 3154 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 3155 } else { 3156 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 3157 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 3158 0, NULL); 3159 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 3160 0, NULL); 3161 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 3162 0, NULL); 3163 if (adapter->hw.phy.type != e1000_phy_ife) { 3164 ifmedia_add(&adapter->media, 3165 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3166 ifmedia_add(&adapter->media, 3167 IFM_ETHER | IFM_1000_T, 0, NULL); 3168 } 3169 } 3170 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3171 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 3172 } 3173 3174 3175 /********************************************************************* 3176 * 3177 * Workaround for SmartSpeed on 82541 and 82547 controllers 3178 * 3179 **********************************************************************/ 3180 static void 3181 em_smartspeed(struct adapter *adapter) 3182 { 3183 u16 phy_tmp; 3184 3185 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 3186 adapter->hw.mac.autoneg == 0 || 3187 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 3188 return; 3189 3190 if (adapter->smartspeed == 0) { 3191 /* If Master/Slave config fault is asserted twice, 3192 * we assume back-to-back */ 3193 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 3194 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 3195 return; 3196 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 3197 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 3198 e1000_read_phy_reg(&adapter->hw, 3199 PHY_1000T_CTRL, &phy_tmp); 3200 if(phy_tmp & CR_1000T_MS_ENABLE) { 3201 phy_tmp &= ~CR_1000T_MS_ENABLE; 3202 e1000_write_phy_reg(&adapter->hw, 3203 PHY_1000T_CTRL, phy_tmp); 3204 adapter->smartspeed++; 3205 if(adapter->hw.mac.autoneg && 3206 !e1000_phy_setup_autoneg(&adapter->hw) && 3207 !e1000_read_phy_reg(&adapter->hw, 3208 PHY_CONTROL, &phy_tmp)) { 3209 phy_tmp |= (MII_CR_AUTO_NEG_EN | 3210 MII_CR_RESTART_AUTO_NEG); 3211 e1000_write_phy_reg(&adapter->hw, 3212 PHY_CONTROL, phy_tmp); 3213 } 3214 } 3215 } 3216 return; 3217 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 3218 /* If still no link, perhaps using 2/3 pair cable */ 3219 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 3220 phy_tmp |= CR_1000T_MS_ENABLE; 3221 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 3222 if(adapter->hw.mac.autoneg && 3223 !e1000_phy_setup_autoneg(&adapter->hw) && 3224 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 3225 phy_tmp |= (MII_CR_AUTO_NEG_EN | 3226 MII_CR_RESTART_AUTO_NEG); 3227 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 3228 } 3229 } 3230 /* Restart process after EM_SMARTSPEED_MAX iterations */ 3231 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 3232 adapter->smartspeed = 0; 3233 } 3234 3235 3236 /* 3237 * Manage DMA'able memory. 3238 */ 3239 static void 3240 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3241 { 3242 if (error) 3243 return; 3244 *(bus_addr_t *) arg = segs[0].ds_addr; 3245 } 3246 3247 static int 3248 em_dma_malloc(struct adapter *adapter, bus_size_t size, 3249 struct em_dma_alloc *dma, int mapflags) 3250 { 3251 int error; 3252 3253 #if __FreeBSD_version >= 700000 3254 error = bus_dma_tag_create(bus_get_dma_tag(adapter->dev), /* parent */ 3255 #else 3256 error = bus_dma_tag_create(NULL, /* parent */ 3257 #endif 3258 EM_DBA_ALIGN, 0, /* alignment, bounds */ 3259 BUS_SPACE_MAXADDR, /* lowaddr */ 3260 BUS_SPACE_MAXADDR, /* highaddr */ 3261 NULL, NULL, /* filter, filterarg */ 3262 size, /* maxsize */ 3263 1, /* nsegments */ 3264 size, /* maxsegsize */ 3265 0, /* flags */ 3266 NULL, /* lockfunc */ 3267 NULL, /* lockarg */ 3268 &dma->dma_tag); 3269 if (error) { 3270 device_printf(adapter->dev, 3271 "%s: bus_dma_tag_create failed: %d\n", 3272 __func__, error); 3273 goto fail_0; 3274 } 3275 3276 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 3277 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 3278 if (error) { 3279 device_printf(adapter->dev, 3280 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 3281 __func__, (uintmax_t)size, error); 3282 goto fail_2; 3283 } 3284 3285 dma->dma_paddr = 0; 3286 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 3287 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 3288 if (error || dma->dma_paddr == 0) { 3289 device_printf(adapter->dev, 3290 "%s: bus_dmamap_load failed: %d\n", 3291 __func__, error); 3292 goto fail_3; 3293 } 3294 3295 return (0); 3296 3297 fail_3: 3298 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 3299 fail_2: 3300 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 3301 bus_dma_tag_destroy(dma->dma_tag); 3302 fail_0: 3303 dma->dma_map = NULL; 3304 dma->dma_tag = NULL; 3305 3306 return (error); 3307 } 3308 3309 static void 3310 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 3311 { 3312 if (dma->dma_tag == NULL) 3313 return; 3314 if (dma->dma_map != NULL) { 3315 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 3316 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3317 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 3318 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 3319 dma->dma_map = NULL; 3320 } 3321 bus_dma_tag_destroy(dma->dma_tag); 3322 dma->dma_tag = NULL; 3323 } 3324 3325 3326 /********************************************************************* 3327 * 3328 * Allocate memory for tx_buffer structures. The tx_buffer stores all 3329 * the information needed to transmit a packet on the wire. 3330 * 3331 **********************************************************************/ 3332 static int 3333 em_allocate_transmit_structures(struct adapter *adapter) 3334 { 3335 device_t dev = adapter->dev; 3336 struct em_buffer *tx_buffer; 3337 int error; 3338 3339 /* 3340 * Create DMA tags for tx descriptors 3341 */ 3342 #if __FreeBSD_version >= 700000 3343 if ((error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3344 #else 3345 if ((error = bus_dma_tag_create(NULL, /* parent */ 3346 #endif 3347 1, 0, /* alignment, bounds */ 3348 BUS_SPACE_MAXADDR, /* lowaddr */ 3349 BUS_SPACE_MAXADDR, /* highaddr */ 3350 NULL, NULL, /* filter, filterarg */ 3351 EM_TSO_SIZE, /* maxsize */ 3352 EM_MAX_SCATTER, /* nsegments */ 3353 EM_TSO_SEG_SIZE, /* maxsegsize */ 3354 0, /* flags */ 3355 NULL, /* lockfunc */ 3356 NULL, /* lockarg */ 3357 &adapter->txtag)) != 0) { 3358 device_printf(dev, "Unable to allocate TX DMA tag\n"); 3359 goto fail; 3360 } 3361 3362 adapter->tx_buffer_area = malloc(sizeof(struct em_buffer) * 3363 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 3364 if (adapter->tx_buffer_area == NULL) { 3365 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 3366 error = ENOMEM; 3367 goto fail; 3368 } 3369 3370 /* Create the descriptor buffer dma maps */ 3371 for (int i = 0; i < adapter->num_tx_desc; i++) { 3372 tx_buffer = &adapter->tx_buffer_area[i]; 3373 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 3374 if (error != 0) { 3375 device_printf(dev, "Unable to create TX DMA map\n"); 3376 goto fail; 3377 } 3378 tx_buffer->next_eop = -1; 3379 } 3380 3381 return (0); 3382 fail: 3383 em_free_transmit_structures(adapter); 3384 return (error); 3385 } 3386 3387 /********************************************************************* 3388 * 3389 * (Re)Initialize transmit structures. 3390 * 3391 **********************************************************************/ 3392 static void 3393 em_setup_transmit_structures(struct adapter *adapter) 3394 { 3395 struct em_buffer *tx_buffer; 3396 3397 /* Clear the old ring contents */ 3398 bzero(adapter->tx_desc_base, 3399 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 3400 3401 /* Free any existing TX buffers */ 3402 for (int i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 3403 tx_buffer = &adapter->tx_buffer_area[i]; 3404 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3405 BUS_DMASYNC_POSTWRITE); 3406 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 3407 m_freem(tx_buffer->m_head); 3408 tx_buffer->m_head = NULL; 3409 tx_buffer->next_eop = -1; 3410 } 3411 3412 /* Reset state */ 3413 adapter->next_avail_tx_desc = 0; 3414 adapter->next_tx_to_clean = 0; 3415 adapter->num_tx_desc_avail = adapter->num_tx_desc; 3416 3417 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3418 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3419 3420 return; 3421 } 3422 3423 /********************************************************************* 3424 * 3425 * Enable transmit unit. 3426 * 3427 **********************************************************************/ 3428 static void 3429 em_initialize_transmit_unit(struct adapter *adapter) 3430 { 3431 u32 tctl, tarc, tipg = 0; 3432 u64 bus_addr; 3433 3434 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3435 /* Setup the Base and Length of the Tx Descriptor Ring */ 3436 bus_addr = adapter->txdma.dma_paddr; 3437 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 3438 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 3439 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 3440 (u32)(bus_addr >> 32)); 3441 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 3442 (u32)bus_addr); 3443 /* Setup the HW Tx Head and Tail descriptor pointers */ 3444 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 3445 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 3446 3447 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3448 E1000_READ_REG(&adapter->hw, E1000_TDBAL(0)), 3449 E1000_READ_REG(&adapter->hw, E1000_TDLEN(0))); 3450 3451 /* Set the default values for the Tx Inter Packet Gap timer */ 3452 switch (adapter->hw.mac.type) { 3453 case e1000_82542: 3454 tipg = DEFAULT_82542_TIPG_IPGT; 3455 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3456 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3457 break; 3458 case e1000_80003es2lan: 3459 tipg = DEFAULT_82543_TIPG_IPGR1; 3460 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3461 E1000_TIPG_IPGR2_SHIFT; 3462 break; 3463 default: 3464 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3465 (adapter->hw.phy.media_type == 3466 e1000_media_type_internal_serdes)) 3467 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3468 else 3469 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3470 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3471 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3472 } 3473 3474 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3475 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3476 if(adapter->hw.mac.type >= e1000_82540) 3477 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3478 adapter->tx_abs_int_delay.value); 3479 3480 if ((adapter->hw.mac.type == e1000_82571) || 3481 (adapter->hw.mac.type == e1000_82572)) { 3482 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3483 tarc |= SPEED_MODE_BIT; 3484 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3485 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3486 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3487 tarc |= 1; 3488 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3489 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3490 tarc |= 1; 3491 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3492 } 3493 3494 /* Program the Transmit Control Register */ 3495 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3496 tctl &= ~E1000_TCTL_CT; 3497 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3498 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3499 3500 if (adapter->hw.mac.type >= e1000_82571) 3501 tctl |= E1000_TCTL_MULR; 3502 3503 /* This write will effectively turn on the transmit unit. */ 3504 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3505 3506 /* Setup Transmit Descriptor Base Settings */ 3507 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 3508 3509 if (adapter->tx_int_delay.value > 0) 3510 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3511 } 3512 3513 /********************************************************************* 3514 * 3515 * Free all transmit related data structures. 3516 * 3517 **********************************************************************/ 3518 static void 3519 em_free_transmit_structures(struct adapter *adapter) 3520 { 3521 struct em_buffer *tx_buffer; 3522 3523 INIT_DEBUGOUT("free_transmit_structures: begin"); 3524 3525 if (adapter->tx_buffer_area != NULL) { 3526 for (int i = 0; i < adapter->num_tx_desc; i++) { 3527 tx_buffer = &adapter->tx_buffer_area[i]; 3528 if (tx_buffer->m_head != NULL) { 3529 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3530 BUS_DMASYNC_POSTWRITE); 3531 bus_dmamap_unload(adapter->txtag, 3532 tx_buffer->map); 3533 m_freem(tx_buffer->m_head); 3534 tx_buffer->m_head = NULL; 3535 } else if (tx_buffer->map != NULL) 3536 bus_dmamap_unload(adapter->txtag, 3537 tx_buffer->map); 3538 if (tx_buffer->map != NULL) { 3539 bus_dmamap_destroy(adapter->txtag, 3540 tx_buffer->map); 3541 tx_buffer->map = NULL; 3542 } 3543 } 3544 } 3545 if (adapter->tx_buffer_area != NULL) { 3546 free(adapter->tx_buffer_area, M_DEVBUF); 3547 adapter->tx_buffer_area = NULL; 3548 } 3549 if (adapter->txtag != NULL) { 3550 bus_dma_tag_destroy(adapter->txtag); 3551 adapter->txtag = NULL; 3552 } 3553 } 3554 3555 /********************************************************************* 3556 * 3557 * The offload context needs to be set when we transfer the first 3558 * packet of a particular protocol (TCP/UDP). This routine has been 3559 * enhanced to deal with inserted VLAN headers, and IPV6 (not complete) 3560 * 3561 **********************************************************************/ 3562 static void 3563 em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp, 3564 u32 *txd_upper, u32 *txd_lower) 3565 { 3566 struct e1000_context_desc *TXD; 3567 struct em_buffer *tx_buffer; 3568 struct ether_vlan_header *eh; 3569 struct ip *ip = NULL; 3570 struct ip6_hdr *ip6; 3571 struct tcp_hdr *th; 3572 int curr_txd, ehdrlen; 3573 u32 cmd, hdr_len, ip_hlen; 3574 u16 etype; 3575 u8 ipproto; 3576 3577 cmd = hdr_len = ipproto = 0; 3578 /* Setup checksum offload context. */ 3579 curr_txd = adapter->next_avail_tx_desc; 3580 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3581 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3582 3583 /* 3584 * Determine where frame payload starts. 3585 * Jump over vlan headers if already present, 3586 * helpful for QinQ too. 3587 */ 3588 eh = mtod(mp, struct ether_vlan_header *); 3589 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3590 etype = ntohs(eh->evl_proto); 3591 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3592 } else { 3593 etype = ntohs(eh->evl_encap_proto); 3594 ehdrlen = ETHER_HDR_LEN; 3595 } 3596 3597 /* 3598 * We only support TCP/UDP for IPv4 and IPv6 for the moment. 3599 * TODO: Support SCTP too when it hits the tree. 3600 */ 3601 switch (etype) { 3602 case ETHERTYPE_IP: 3603 ip = (struct ip *)(mp->m_data + ehdrlen); 3604 ip_hlen = ip->ip_hl << 2; 3605 3606 /* Setup of IP header checksum. */ 3607 if (mp->m_pkthdr.csum_flags & CSUM_IP) { 3608 /* 3609 * Start offset for header checksum calculation. 3610 * End offset for header checksum calculation. 3611 * Offset of place to put the checksum. 3612 */ 3613 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3614 TXD->lower_setup.ip_fields.ipcse = 3615 htole16(ehdrlen + ip_hlen); 3616 TXD->lower_setup.ip_fields.ipcso = 3617 ehdrlen + offsetof(struct ip, ip_sum); 3618 cmd |= E1000_TXD_CMD_IP; 3619 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 3620 } 3621 3622 if (mp->m_len < ehdrlen + ip_hlen) 3623 return; /* failure */ 3624 3625 hdr_len = ehdrlen + ip_hlen; 3626 ipproto = ip->ip_p; 3627 3628 break; 3629 case ETHERTYPE_IPV6: 3630 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3631 ip_hlen = sizeof(struct ip6_hdr); /* XXX: No header stacking. */ 3632 3633 if (mp->m_len < ehdrlen + ip_hlen) 3634 return; /* failure */ 3635 3636 /* IPv6 doesn't have a header checksum. */ 3637 3638 hdr_len = ehdrlen + ip_hlen; 3639 ipproto = ip6->ip6_nxt; 3640 3641 break; 3642 #ifdef EM_TIMESYNC 3643 case ETHERTYPE_IEEE1588: 3644 *txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 3645 break; 3646 #endif 3647 default: 3648 *txd_upper = 0; 3649 *txd_lower = 0; 3650 return; 3651 } 3652 3653 switch (ipproto) { 3654 case IPPROTO_TCP: 3655 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 3656 /* 3657 * Start offset for payload checksum calculation. 3658 * End offset for payload checksum calculation. 3659 * Offset of place to put the checksum. 3660 */ 3661 th = (struct tcp_hdr *)(mp->m_data + hdr_len); 3662 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3663 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3664 TXD->upper_setup.tcp_fields.tucso = 3665 hdr_len + offsetof(struct tcphdr, th_sum); 3666 cmd |= E1000_TXD_CMD_TCP; 3667 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3668 } 3669 break; 3670 case IPPROTO_UDP: 3671 { 3672 #ifdef EM_TIMESYNC 3673 void *hdr = (caddr_t) ip + ip_hlen; 3674 struct udphdr *uh = (struct udphdr *)hdr; 3675 3676 if (uh->uh_dport == htons(TSYNC_PORT)) { 3677 *txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 3678 IOCTL_DEBUGOUT("@@@ Sending Event Packet\n"); 3679 } 3680 #endif 3681 if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 3682 /* 3683 * Start offset for header checksum calculation. 3684 * End offset for header checksum calculation. 3685 * Offset of place to put the checksum. 3686 */ 3687 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3688 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3689 TXD->upper_setup.tcp_fields.tucso = 3690 hdr_len + offsetof(struct udphdr, uh_sum); 3691 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3692 } 3693 /* Fall Thru */ 3694 } 3695 default: 3696 break; 3697 } 3698 3699 #ifdef EM_TIMESYNC 3700 /* 3701 ** We might be here just for TIMESYNC 3702 ** which means we don't need the context 3703 ** descriptor. 3704 */ 3705 if (!mp->m_pkthdr.csum_flags & CSUM_OFFLOAD) 3706 return; 3707 #endif 3708 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3709 E1000_TXD_DTYP_D; /* Data descr */ 3710 TXD->tcp_seg_setup.data = htole32(0); 3711 TXD->cmd_and_length = 3712 htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT | cmd); 3713 tx_buffer->m_head = NULL; 3714 tx_buffer->next_eop = -1; 3715 3716 if (++curr_txd == adapter->num_tx_desc) 3717 curr_txd = 0; 3718 3719 adapter->num_tx_desc_avail--; 3720 adapter->next_avail_tx_desc = curr_txd; 3721 } 3722 3723 3724 #if __FreeBSD_version >= 700000 3725 /********************************************************************** 3726 * 3727 * Setup work for hardware segmentation offload (TSO) 3728 * 3729 **********************************************************************/ 3730 static bool 3731 em_tso_setup(struct adapter *adapter, struct mbuf *mp, u32 *txd_upper, 3732 u32 *txd_lower) 3733 { 3734 struct e1000_context_desc *TXD; 3735 struct em_buffer *tx_buffer; 3736 struct ether_vlan_header *eh; 3737 struct ip *ip; 3738 struct ip6_hdr *ip6; 3739 struct tcphdr *th; 3740 int curr_txd, ehdrlen, hdr_len, ip_hlen, isip6; 3741 u16 etype; 3742 3743 /* 3744 * This function could/should be extended to support IP/IPv6 3745 * fragmentation as well. But as they say, one step at a time. 3746 */ 3747 3748 /* 3749 * Determine where frame payload starts. 3750 * Jump over vlan headers if already present, 3751 * helpful for QinQ too. 3752 */ 3753 eh = mtod(mp, struct ether_vlan_header *); 3754 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3755 etype = ntohs(eh->evl_proto); 3756 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3757 } else { 3758 etype = ntohs(eh->evl_encap_proto); 3759 ehdrlen = ETHER_HDR_LEN; 3760 } 3761 3762 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3763 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3764 return FALSE; /* -1 */ 3765 3766 /* 3767 * We only support TCP for IPv4 and IPv6 (notyet) for the moment. 3768 * TODO: Support SCTP too when it hits the tree. 3769 */ 3770 switch (etype) { 3771 case ETHERTYPE_IP: 3772 isip6 = 0; 3773 ip = (struct ip *)(mp->m_data + ehdrlen); 3774 if (ip->ip_p != IPPROTO_TCP) 3775 return FALSE; /* 0 */ 3776 ip->ip_len = 0; 3777 ip->ip_sum = 0; 3778 ip_hlen = ip->ip_hl << 2; 3779 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3780 return FALSE; /* -1 */ 3781 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3782 #if 1 3783 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3784 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3785 #else 3786 th->th_sum = mp->m_pkthdr.csum_data; 3787 #endif 3788 break; 3789 case ETHERTYPE_IPV6: 3790 isip6 = 1; 3791 return FALSE; /* Not supported yet. */ 3792 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3793 if (ip6->ip6_nxt != IPPROTO_TCP) 3794 return FALSE; /* 0 */ 3795 ip6->ip6_plen = 0; 3796 ip_hlen = sizeof(struct ip6_hdr); /* XXX: no header stacking. */ 3797 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3798 return FALSE; /* -1 */ 3799 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 3800 #if 0 3801 th->th_sum = in6_pseudo(ip6->ip6_src, ip->ip6_dst, 3802 htons(IPPROTO_TCP)); /* XXX: function notyet. */ 3803 #else 3804 th->th_sum = mp->m_pkthdr.csum_data; 3805 #endif 3806 break; 3807 default: 3808 return FALSE; 3809 } 3810 hdr_len = ehdrlen + ip_hlen + (th->th_off << 2); 3811 3812 *txd_lower = (E1000_TXD_CMD_DEXT | /* Extended descr type */ 3813 E1000_TXD_DTYP_D | /* Data descr type */ 3814 E1000_TXD_CMD_TSE); /* Do TSE on this packet */ 3815 3816 /* IP and/or TCP header checksum calculation and insertion. */ 3817 *txd_upper = ((isip6 ? 0 : E1000_TXD_POPTS_IXSM) | 3818 E1000_TXD_POPTS_TXSM) << 8; 3819 3820 curr_txd = adapter->next_avail_tx_desc; 3821 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3822 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3823 3824 /* IPv6 doesn't have a header checksum. */ 3825 if (!isip6) { 3826 /* 3827 * Start offset for header checksum calculation. 3828 * End offset for header checksum calculation. 3829 * Offset of place put the checksum. 3830 */ 3831 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3832 TXD->lower_setup.ip_fields.ipcse = 3833 htole16(ehdrlen + ip_hlen - 1); 3834 TXD->lower_setup.ip_fields.ipcso = 3835 ehdrlen + offsetof(struct ip, ip_sum); 3836 } 3837 /* 3838 * Start offset for payload checksum calculation. 3839 * End offset for payload checksum calculation. 3840 * Offset of place to put the checksum. 3841 */ 3842 TXD->upper_setup.tcp_fields.tucss = 3843 ehdrlen + ip_hlen; 3844 TXD->upper_setup.tcp_fields.tucse = 0; 3845 TXD->upper_setup.tcp_fields.tucso = 3846 ehdrlen + ip_hlen + offsetof(struct tcphdr, th_sum); 3847 /* 3848 * Payload size per packet w/o any headers. 3849 * Length of all headers up to payload. 3850 */ 3851 TXD->tcp_seg_setup.fields.mss = htole16(mp->m_pkthdr.tso_segsz); 3852 TXD->tcp_seg_setup.fields.hdr_len = hdr_len; 3853 3854 TXD->cmd_and_length = htole32(adapter->txd_cmd | 3855 E1000_TXD_CMD_DEXT | /* Extended descr */ 3856 E1000_TXD_CMD_TSE | /* TSE context */ 3857 (isip6 ? 0 : E1000_TXD_CMD_IP) | /* Do IP csum */ 3858 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3859 (mp->m_pkthdr.len - (hdr_len))); /* Total len */ 3860 3861 tx_buffer->m_head = NULL; 3862 tx_buffer->next_eop = -1; 3863 3864 if (++curr_txd == adapter->num_tx_desc) 3865 curr_txd = 0; 3866 3867 adapter->num_tx_desc_avail--; 3868 adapter->next_avail_tx_desc = curr_txd; 3869 adapter->tx_tso = TRUE; 3870 3871 return TRUE; 3872 } 3873 3874 #endif /* __FreeBSD_version >= 700000 */ 3875 3876 /********************************************************************** 3877 * 3878 * Examine each tx_buffer in the used queue. If the hardware is done 3879 * processing the packet then free associated resources. The 3880 * tx_buffer is put back on the free queue. 3881 * 3882 **********************************************************************/ 3883 static void 3884 em_txeof(struct adapter *adapter) 3885 { 3886 int first, last, done, num_avail; 3887 struct em_buffer *tx_buffer; 3888 struct e1000_tx_desc *tx_desc, *eop_desc; 3889 struct ifnet *ifp = adapter->ifp; 3890 3891 EM_TX_LOCK_ASSERT(adapter); 3892 3893 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3894 return; 3895 3896 num_avail = adapter->num_tx_desc_avail; 3897 first = adapter->next_tx_to_clean; 3898 tx_desc = &adapter->tx_desc_base[first]; 3899 tx_buffer = &adapter->tx_buffer_area[first]; 3900 last = tx_buffer->next_eop; 3901 eop_desc = &adapter->tx_desc_base[last]; 3902 3903 /* 3904 * What this does is get the index of the 3905 * first descriptor AFTER the EOP of the 3906 * first packet, that way we can do the 3907 * simple comparison on the inner while loop. 3908 */ 3909 if (++last == adapter->num_tx_desc) 3910 last = 0; 3911 done = last; 3912 3913 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3914 BUS_DMASYNC_POSTREAD); 3915 3916 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3917 /* We clean the range of the packet */ 3918 while (first != done) { 3919 tx_desc->upper.data = 0; 3920 tx_desc->lower.data = 0; 3921 tx_desc->buffer_addr = 0; 3922 num_avail++; 3923 3924 if (tx_buffer->m_head) { 3925 ifp->if_opackets++; 3926 bus_dmamap_sync(adapter->txtag, 3927 tx_buffer->map, 3928 BUS_DMASYNC_POSTWRITE); 3929 bus_dmamap_unload(adapter->txtag, 3930 tx_buffer->map); 3931 3932 m_freem(tx_buffer->m_head); 3933 tx_buffer->m_head = NULL; 3934 } 3935 tx_buffer->next_eop = -1; 3936 3937 if (++first == adapter->num_tx_desc) 3938 first = 0; 3939 3940 tx_buffer = &adapter->tx_buffer_area[first]; 3941 tx_desc = &adapter->tx_desc_base[first]; 3942 } 3943 /* See if we can continue to the next packet */ 3944 last = tx_buffer->next_eop; 3945 if (last != -1) { 3946 eop_desc = &adapter->tx_desc_base[last]; 3947 /* Get new done point */ 3948 if (++last == adapter->num_tx_desc) last = 0; 3949 done = last; 3950 } else 3951 break; 3952 } 3953 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3954 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3955 3956 adapter->next_tx_to_clean = first; 3957 3958 /* 3959 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 3960 * that it is OK to send packets. 3961 * If there are no pending descriptors, clear the timeout. Otherwise, 3962 * if some descriptors have been freed, restart the timeout. 3963 */ 3964 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 3965 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3966 /* All clean, turn off the timer */ 3967 if (num_avail == adapter->num_tx_desc) { 3968 adapter->watchdog_timer = 0; 3969 } else 3970 /* Some cleaned, reset the timer */ 3971 if (num_avail != adapter->num_tx_desc_avail) 3972 adapter->watchdog_timer = EM_TX_TIMEOUT; 3973 } 3974 adapter->num_tx_desc_avail = num_avail; 3975 return; 3976 } 3977 3978 /********************************************************************* 3979 * 3980 * When Link is lost sometimes there is work still in the TX ring 3981 * which will result in a watchdog, rather than allow that do an 3982 * attempted cleanup and then reinit here. Note that this has been 3983 * seens mostly with fiber adapters. 3984 * 3985 **********************************************************************/ 3986 static void 3987 em_tx_purge(struct adapter *adapter) 3988 { 3989 if ((!adapter->link_active) && (adapter->watchdog_timer)) { 3990 EM_TX_LOCK(adapter); 3991 em_txeof(adapter); 3992 EM_TX_UNLOCK(adapter); 3993 if (adapter->watchdog_timer) { /* Still not clean? */ 3994 adapter->watchdog_timer = 0; 3995 em_init_locked(adapter); 3996 } 3997 } 3998 } 3999 4000 /********************************************************************* 4001 * 4002 * Get a buffer from system mbuf buffer pool. 4003 * 4004 **********************************************************************/ 4005 static int 4006 em_get_buf(struct adapter *adapter, int i) 4007 { 4008 struct mbuf *m; 4009 bus_dma_segment_t segs[1]; 4010 bus_dmamap_t map; 4011 struct em_buffer *rx_buffer; 4012 int error, nsegs; 4013 4014 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 4015 if (m == NULL) { 4016 adapter->mbuf_cluster_failed++; 4017 return (ENOBUFS); 4018 } 4019 m->m_len = m->m_pkthdr.len = MCLBYTES; 4020 4021 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 4022 m_adj(m, ETHER_ALIGN); 4023 4024 /* 4025 * Using memory from the mbuf cluster pool, invoke the 4026 * bus_dma machinery to arrange the memory mapping. 4027 */ 4028 error = bus_dmamap_load_mbuf_sg(adapter->rxtag, 4029 adapter->rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 4030 if (error != 0) { 4031 m_free(m); 4032 return (error); 4033 } 4034 4035 /* If nsegs is wrong then the stack is corrupt. */ 4036 KASSERT(nsegs == 1, ("Too many segments returned!")); 4037 4038 rx_buffer = &adapter->rx_buffer_area[i]; 4039 if (rx_buffer->m_head != NULL) 4040 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 4041 4042 map = rx_buffer->map; 4043 rx_buffer->map = adapter->rx_sparemap; 4044 adapter->rx_sparemap = map; 4045 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 4046 rx_buffer->m_head = m; 4047 4048 adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 4049 return (0); 4050 } 4051 4052 /********************************************************************* 4053 * 4054 * Allocate memory for rx_buffer structures. Since we use one 4055 * rx_buffer per received packet, the maximum number of rx_buffer's 4056 * that we'll need is equal to the number of receive descriptors 4057 * that we've allocated. 4058 * 4059 **********************************************************************/ 4060 static int 4061 em_allocate_receive_structures(struct adapter *adapter) 4062 { 4063 device_t dev = adapter->dev; 4064 struct em_buffer *rx_buffer; 4065 int i, error; 4066 4067 adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * 4068 adapter->num_rx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 4069 if (adapter->rx_buffer_area == NULL) { 4070 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 4071 return (ENOMEM); 4072 } 4073 4074 #if __FreeBSD_version >= 700000 4075 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 4076 #else 4077 error = bus_dma_tag_create(NULL, /* parent */ 4078 #endif 4079 1, 0, /* alignment, bounds */ 4080 BUS_SPACE_MAXADDR, /* lowaddr */ 4081 BUS_SPACE_MAXADDR, /* highaddr */ 4082 NULL, NULL, /* filter, filterarg */ 4083 MCLBYTES, /* maxsize */ 4084 1, /* nsegments */ 4085 MCLBYTES, /* maxsegsize */ 4086 0, /* flags */ 4087 NULL, /* lockfunc */ 4088 NULL, /* lockarg */ 4089 &adapter->rxtag); 4090 if (error) { 4091 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 4092 __func__, error); 4093 goto fail; 4094 } 4095 4096 /* Create the spare map (used by getbuf) */ 4097 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 4098 &adapter->rx_sparemap); 4099 if (error) { 4100 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 4101 __func__, error); 4102 goto fail; 4103 } 4104 4105 rx_buffer = adapter->rx_buffer_area; 4106 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4107 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 4108 &rx_buffer->map); 4109 if (error) { 4110 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 4111 __func__, error); 4112 goto fail; 4113 } 4114 } 4115 4116 return (0); 4117 4118 fail: 4119 em_free_receive_structures(adapter); 4120 return (error); 4121 } 4122 4123 /********************************************************************* 4124 * 4125 * (Re)initialize receive structures. 4126 * 4127 **********************************************************************/ 4128 static int 4129 em_setup_receive_structures(struct adapter *adapter) 4130 { 4131 struct em_buffer *rx_buffer; 4132 int i, error; 4133 4134 /* Reset descriptor ring */ 4135 bzero(adapter->rx_desc_base, 4136 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 4137 4138 /* Free current RX buffers. */ 4139 rx_buffer = adapter->rx_buffer_area; 4140 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4141 if (rx_buffer->m_head != NULL) { 4142 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4143 BUS_DMASYNC_POSTREAD); 4144 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 4145 m_freem(rx_buffer->m_head); 4146 rx_buffer->m_head = NULL; 4147 } 4148 } 4149 4150 /* Allocate new ones. */ 4151 for (i = 0; i < adapter->num_rx_desc; i++) { 4152 error = em_get_buf(adapter, i); 4153 if (error) 4154 return (error); 4155 } 4156 4157 /* Setup our descriptor pointers */ 4158 adapter->next_rx_desc_to_check = 0; 4159 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4160 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4161 4162 return (0); 4163 } 4164 4165 /********************************************************************* 4166 * 4167 * Enable receive unit. 4168 * 4169 **********************************************************************/ 4170 #define MAX_INTS_PER_SEC 8000 4171 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4172 4173 static void 4174 em_initialize_receive_unit(struct adapter *adapter) 4175 { 4176 struct ifnet *ifp = adapter->ifp; 4177 u64 bus_addr; 4178 u32 rctl, rxcsum; 4179 4180 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 4181 4182 /* 4183 * Make sure receives are disabled while setting 4184 * up the descriptor ring 4185 */ 4186 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 4187 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 4188 4189 if (adapter->hw.mac.type >= e1000_82540) { 4190 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 4191 adapter->rx_abs_int_delay.value); 4192 /* 4193 * Set the interrupt throttling rate. Value is calculated 4194 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 4195 */ 4196 E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR); 4197 } 4198 4199 /* 4200 ** When using MSIX interrupts we need to throttle 4201 ** using the EITR register (82574 only) 4202 */ 4203 if (adapter->msix) 4204 for (int i = 0; i < 4; i++) 4205 E1000_WRITE_REG(&adapter->hw, 4206 E1000_EITR_82574(i), DEFAULT_ITR); 4207 4208 /* Disable accelerated ackknowledge */ 4209 if (adapter->hw.mac.type == e1000_82574) 4210 E1000_WRITE_REG(&adapter->hw, 4211 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 4212 4213 /* Setup the Base and Length of the Rx Descriptor Ring */ 4214 bus_addr = adapter->rxdma.dma_paddr; 4215 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 4216 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 4217 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 4218 (u32)(bus_addr >> 32)); 4219 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 4220 (u32)bus_addr); 4221 4222 /* Setup the Receive Control Register */ 4223 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4224 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 4225 E1000_RCTL_RDMTS_HALF | 4226 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4227 4228 /* Make sure VLAN Filters are off */ 4229 rctl &= ~E1000_RCTL_VFE; 4230 4231 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 4232 rctl |= E1000_RCTL_SBP; 4233 else 4234 rctl &= ~E1000_RCTL_SBP; 4235 4236 switch (adapter->rx_buffer_len) { 4237 default: 4238 case 2048: 4239 rctl |= E1000_RCTL_SZ_2048; 4240 break; 4241 case 4096: 4242 rctl |= E1000_RCTL_SZ_4096 | 4243 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4244 break; 4245 case 8192: 4246 rctl |= E1000_RCTL_SZ_8192 | 4247 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4248 break; 4249 case 16384: 4250 rctl |= E1000_RCTL_SZ_16384 | 4251 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4252 break; 4253 } 4254 4255 if (ifp->if_mtu > ETHERMTU) 4256 rctl |= E1000_RCTL_LPE; 4257 else 4258 rctl &= ~E1000_RCTL_LPE; 4259 4260 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 4261 if ((adapter->hw.mac.type >= e1000_82543) && 4262 (ifp->if_capenable & IFCAP_RXCSUM)) { 4263 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 4264 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 4265 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 4266 } 4267 4268 /* 4269 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 4270 ** long latencies are observed, like Lenovo X60. This 4271 ** change eliminates the problem, but since having positive 4272 ** values in RDTR is a known source of problems on other 4273 ** platforms another solution is being sought. 4274 */ 4275 if (adapter->hw.mac.type == e1000_82573) 4276 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 0x20); 4277 4278 /* Enable Receives */ 4279 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 4280 4281 /* 4282 * Setup the HW Rx Head and 4283 * Tail Descriptor Pointers 4284 */ 4285 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 4286 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 4287 4288 return; 4289 } 4290 4291 /********************************************************************* 4292 * 4293 * Free receive related data structures. 4294 * 4295 **********************************************************************/ 4296 static void 4297 em_free_receive_structures(struct adapter *adapter) 4298 { 4299 struct em_buffer *rx_buffer; 4300 int i; 4301 4302 INIT_DEBUGOUT("free_receive_structures: begin"); 4303 4304 if (adapter->rx_sparemap) { 4305 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 4306 adapter->rx_sparemap = NULL; 4307 } 4308 4309 /* Cleanup any existing buffers */ 4310 if (adapter->rx_buffer_area != NULL) { 4311 rx_buffer = adapter->rx_buffer_area; 4312 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4313 if (rx_buffer->m_head != NULL) { 4314 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4315 BUS_DMASYNC_POSTREAD); 4316 bus_dmamap_unload(adapter->rxtag, 4317 rx_buffer->map); 4318 m_freem(rx_buffer->m_head); 4319 rx_buffer->m_head = NULL; 4320 } else if (rx_buffer->map != NULL) 4321 bus_dmamap_unload(adapter->rxtag, 4322 rx_buffer->map); 4323 if (rx_buffer->map != NULL) { 4324 bus_dmamap_destroy(adapter->rxtag, 4325 rx_buffer->map); 4326 rx_buffer->map = NULL; 4327 } 4328 } 4329 } 4330 4331 if (adapter->rx_buffer_area != NULL) { 4332 free(adapter->rx_buffer_area, M_DEVBUF); 4333 adapter->rx_buffer_area = NULL; 4334 } 4335 4336 if (adapter->rxtag != NULL) { 4337 bus_dma_tag_destroy(adapter->rxtag); 4338 adapter->rxtag = NULL; 4339 } 4340 } 4341 4342 /********************************************************************* 4343 * 4344 * This routine executes in interrupt context. It replenishes 4345 * the mbufs in the descriptor and sends data which has been 4346 * dma'ed into host memory to upper layer. 4347 * 4348 * We loop at most count times if count is > 0, or until done if 4349 * count < 0. 4350 * 4351 *********************************************************************/ 4352 static int 4353 em_rxeof(struct adapter *adapter, int count) 4354 { 4355 struct ifnet *ifp = adapter->ifp;; 4356 struct mbuf *mp; 4357 u8 status, accept_frame = 0, eop = 0; 4358 u16 len, desc_len, prev_len_adj; 4359 int i; 4360 struct e1000_rx_desc *current_desc; 4361 4362 EM_RX_LOCK(adapter); 4363 i = adapter->next_rx_desc_to_check; 4364 current_desc = &adapter->rx_desc_base[i]; 4365 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4366 BUS_DMASYNC_POSTREAD); 4367 4368 if (!((current_desc->status) & E1000_RXD_STAT_DD)) { 4369 EM_RX_UNLOCK(adapter); 4370 return (0); 4371 } 4372 4373 while ((current_desc->status & E1000_RXD_STAT_DD) && 4374 (count != 0) && 4375 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4376 struct mbuf *m = NULL; 4377 4378 mp = adapter->rx_buffer_area[i].m_head; 4379 /* 4380 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 4381 * needs to access the last received byte in the mbuf. 4382 */ 4383 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 4384 BUS_DMASYNC_POSTREAD); 4385 4386 accept_frame = 1; 4387 prev_len_adj = 0; 4388 desc_len = le16toh(current_desc->length); 4389 status = current_desc->status; 4390 if (status & E1000_RXD_STAT_EOP) { 4391 count--; 4392 eop = 1; 4393 if (desc_len < ETHER_CRC_LEN) { 4394 len = 0; 4395 prev_len_adj = ETHER_CRC_LEN - desc_len; 4396 } else 4397 len = desc_len - ETHER_CRC_LEN; 4398 } else { 4399 eop = 0; 4400 len = desc_len; 4401 } 4402 4403 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 4404 u8 last_byte; 4405 u32 pkt_len = desc_len; 4406 4407 if (adapter->fmp != NULL) 4408 pkt_len += adapter->fmp->m_pkthdr.len; 4409 4410 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 4411 if (TBI_ACCEPT(&adapter->hw, status, 4412 current_desc->errors, pkt_len, last_byte, 4413 adapter->min_frame_size, adapter->max_frame_size)) { 4414 e1000_tbi_adjust_stats_82543(&adapter->hw, 4415 &adapter->stats, pkt_len, 4416 adapter->hw.mac.addr, 4417 adapter->max_frame_size); 4418 if (len > 0) 4419 len--; 4420 } else 4421 accept_frame = 0; 4422 } 4423 4424 if (accept_frame) { 4425 if (em_get_buf(adapter, i) != 0) { 4426 ifp->if_iqdrops++; 4427 goto discard; 4428 } 4429 4430 /* Assign correct length to the current fragment */ 4431 mp->m_len = len; 4432 4433 if (adapter->fmp == NULL) { 4434 mp->m_pkthdr.len = len; 4435 adapter->fmp = mp; /* Store the first mbuf */ 4436 adapter->lmp = mp; 4437 } else { 4438 /* Chain mbuf's together */ 4439 mp->m_flags &= ~M_PKTHDR; 4440 /* 4441 * Adjust length of previous mbuf in chain if 4442 * we received less than 4 bytes in the last 4443 * descriptor. 4444 */ 4445 if (prev_len_adj > 0) { 4446 adapter->lmp->m_len -= prev_len_adj; 4447 adapter->fmp->m_pkthdr.len -= 4448 prev_len_adj; 4449 } 4450 adapter->lmp->m_next = mp; 4451 adapter->lmp = adapter->lmp->m_next; 4452 adapter->fmp->m_pkthdr.len += len; 4453 } 4454 4455 if (eop) { 4456 adapter->fmp->m_pkthdr.rcvif = ifp; 4457 ifp->if_ipackets++; 4458 em_receive_checksum(adapter, current_desc, 4459 adapter->fmp); 4460 #ifndef __NO_STRICT_ALIGNMENT 4461 if (adapter->max_frame_size > 4462 (MCLBYTES - ETHER_ALIGN) && 4463 em_fixup_rx(adapter) != 0) 4464 goto skip; 4465 #endif 4466 if (status & E1000_RXD_STAT_VP) { 4467 #if __FreeBSD_version < 700000 4468 VLAN_INPUT_TAG_NEW(ifp, adapter->fmp, 4469 (le16toh(current_desc->special) & 4470 E1000_RXD_SPC_VLAN_MASK)); 4471 #else 4472 adapter->fmp->m_pkthdr.ether_vtag = 4473 (le16toh(current_desc->special) & 4474 E1000_RXD_SPC_VLAN_MASK); 4475 adapter->fmp->m_flags |= M_VLANTAG; 4476 #endif 4477 } 4478 #ifndef __NO_STRICT_ALIGNMENT 4479 skip: 4480 #endif 4481 m = adapter->fmp; 4482 adapter->fmp = NULL; 4483 adapter->lmp = NULL; 4484 } 4485 } else { 4486 ifp->if_ierrors++; 4487 discard: 4488 /* Reuse loaded DMA map and just update mbuf chain */ 4489 mp = adapter->rx_buffer_area[i].m_head; 4490 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 4491 mp->m_data = mp->m_ext.ext_buf; 4492 mp->m_next = NULL; 4493 if (adapter->max_frame_size <= 4494 (MCLBYTES - ETHER_ALIGN)) 4495 m_adj(mp, ETHER_ALIGN); 4496 if (adapter->fmp != NULL) { 4497 m_freem(adapter->fmp); 4498 adapter->fmp = NULL; 4499 adapter->lmp = NULL; 4500 } 4501 m = NULL; 4502 } 4503 4504 /* Zero out the receive descriptors status. */ 4505 current_desc->status = 0; 4506 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4508 4509 /* Advance our pointers to the next descriptor. */ 4510 if (++i == adapter->num_rx_desc) 4511 i = 0; 4512 if (m != NULL) { 4513 adapter->next_rx_desc_to_check = i; 4514 /* Unlock for call into stack */ 4515 EM_RX_UNLOCK(adapter); 4516 (*ifp->if_input)(ifp, m); 4517 EM_RX_LOCK(adapter); 4518 i = adapter->next_rx_desc_to_check; 4519 } 4520 current_desc = &adapter->rx_desc_base[i]; 4521 } 4522 adapter->next_rx_desc_to_check = i; 4523 4524 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 4525 if (--i < 0) 4526 i = adapter->num_rx_desc - 1; 4527 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 4528 EM_RX_UNLOCK(adapter); 4529 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4530 return (0); 4531 4532 return (1); 4533 } 4534 4535 #ifndef __NO_STRICT_ALIGNMENT 4536 /* 4537 * When jumbo frames are enabled we should realign entire payload on 4538 * architecures with strict alignment. This is serious design mistake of 8254x 4539 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 4540 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 4541 * payload. On architecures without strict alignment restrictions 8254x still 4542 * performs unaligned memory access which would reduce the performance too. 4543 * To avoid copying over an entire frame to align, we allocate a new mbuf and 4544 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 4545 * existing mbuf chain. 4546 * 4547 * Be aware, best performance of the 8254x is achived only when jumbo frame is 4548 * not used at all on architectures with strict alignment. 4549 */ 4550 static int 4551 em_fixup_rx(struct adapter *adapter) 4552 { 4553 struct mbuf *m, *n; 4554 int error; 4555 4556 error = 0; 4557 m = adapter->fmp; 4558 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 4559 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 4560 m->m_data += ETHER_HDR_LEN; 4561 } else { 4562 MGETHDR(n, M_DONTWAIT, MT_DATA); 4563 if (n != NULL) { 4564 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 4565 m->m_data += ETHER_HDR_LEN; 4566 m->m_len -= ETHER_HDR_LEN; 4567 n->m_len = ETHER_HDR_LEN; 4568 M_MOVE_PKTHDR(n, m); 4569 n->m_next = m; 4570 adapter->fmp = n; 4571 } else { 4572 adapter->dropped_pkts++; 4573 m_freem(adapter->fmp); 4574 adapter->fmp = NULL; 4575 error = ENOMEM; 4576 } 4577 } 4578 4579 return (error); 4580 } 4581 #endif 4582 4583 /********************************************************************* 4584 * 4585 * Verify that the hardware indicated that the checksum is valid. 4586 * Inform the stack about the status of checksum so that stack 4587 * doesn't spend time verifying the checksum. 4588 * 4589 *********************************************************************/ 4590 static void 4591 em_receive_checksum(struct adapter *adapter, 4592 struct e1000_rx_desc *rx_desc, struct mbuf *mp) 4593 { 4594 /* 82543 or newer only */ 4595 if ((adapter->hw.mac.type < e1000_82543) || 4596 /* Ignore Checksum bit is set */ 4597 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 4598 mp->m_pkthdr.csum_flags = 0; 4599 return; 4600 } 4601 4602 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 4603 /* Did it pass? */ 4604 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 4605 /* IP Checksum Good */ 4606 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 4607 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4608 4609 } else { 4610 mp->m_pkthdr.csum_flags = 0; 4611 } 4612 } 4613 4614 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 4615 /* Did it pass? */ 4616 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 4617 mp->m_pkthdr.csum_flags |= 4618 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 4619 mp->m_pkthdr.csum_data = htons(0xffff); 4620 } 4621 } 4622 } 4623 4624 /* 4625 * This turns on the hardware offload of the VLAN 4626 * tag insertion and strip 4627 */ 4628 static void 4629 em_enable_hw_vlans(struct adapter *adapter) 4630 { 4631 u32 ctrl; 4632 4633 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 4634 ctrl |= E1000_CTRL_VME; 4635 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 4636 } 4637 4638 static void 4639 em_enable_intr(struct adapter *adapter) 4640 { 4641 struct e1000_hw *hw = &adapter->hw; 4642 u32 ims_mask = IMS_ENABLE_MASK; 4643 4644 if (adapter->msix) { 4645 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 4646 ims_mask |= EM_MSIX_MASK; 4647 } 4648 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4649 } 4650 4651 static void 4652 em_disable_intr(struct adapter *adapter) 4653 { 4654 struct e1000_hw *hw = &adapter->hw; 4655 4656 if (adapter->msix) 4657 E1000_WRITE_REG(hw, EM_EIAC, 0); 4658 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 4659 } 4660 4661 /* 4662 * Bit of a misnomer, what this really means is 4663 * to enable OS management of the system... aka 4664 * to disable special hardware management features 4665 */ 4666 static void 4667 em_init_manageability(struct adapter *adapter) 4668 { 4669 /* A shared code workaround */ 4670 #define E1000_82542_MANC2H E1000_MANC2H 4671 if (adapter->has_manage) { 4672 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 4673 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4674 4675 /* disable hardware interception of ARP */ 4676 manc &= ~(E1000_MANC_ARP_EN); 4677 4678 /* enable receiving management packets to the host */ 4679 if (adapter->hw.mac.type >= e1000_82571) { 4680 manc |= E1000_MANC_EN_MNG2HOST; 4681 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4682 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4683 manc2h |= E1000_MNG2HOST_PORT_623; 4684 manc2h |= E1000_MNG2HOST_PORT_664; 4685 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 4686 } 4687 4688 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4689 } 4690 } 4691 4692 /* 4693 * Give control back to hardware management 4694 * controller if there is one. 4695 */ 4696 static void 4697 em_release_manageability(struct adapter *adapter) 4698 { 4699 if (adapter->has_manage) { 4700 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4701 4702 /* re-enable hardware interception of ARP */ 4703 manc |= E1000_MANC_ARP_EN; 4704 4705 if (adapter->hw.mac.type >= e1000_82571) 4706 manc &= ~E1000_MANC_EN_MNG2HOST; 4707 4708 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4709 } 4710 } 4711 4712 /* 4713 * em_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4714 * For ASF and Pass Through versions of f/w this means that 4715 * the driver is loaded. For AMT version (only with 82573) 4716 * of the f/w this means that the network i/f is open. 4717 * 4718 */ 4719 static void 4720 em_get_hw_control(struct adapter *adapter) 4721 { 4722 u32 ctrl_ext, swsm; 4723 4724 /* Let firmware know the driver has taken over */ 4725 switch (adapter->hw.mac.type) { 4726 case e1000_82573: 4727 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4728 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4729 swsm | E1000_SWSM_DRV_LOAD); 4730 break; 4731 case e1000_82571: 4732 case e1000_82572: 4733 case e1000_80003es2lan: 4734 case e1000_ich8lan: 4735 case e1000_ich9lan: 4736 case e1000_ich10lan: 4737 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4738 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4739 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4740 break; 4741 default: 4742 break; 4743 } 4744 } 4745 4746 /* 4747 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4748 * For ASF and Pass Through versions of f/w this means that the 4749 * driver is no longer loaded. For AMT version (only with 82573) i 4750 * of the f/w this means that the network i/f is closed. 4751 * 4752 */ 4753 static void 4754 em_release_hw_control(struct adapter *adapter) 4755 { 4756 u32 ctrl_ext, swsm; 4757 4758 /* Let firmware taken over control of h/w */ 4759 switch (adapter->hw.mac.type) { 4760 case e1000_82573: 4761 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4762 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4763 swsm & ~E1000_SWSM_DRV_LOAD); 4764 break; 4765 case e1000_82571: 4766 case e1000_82572: 4767 case e1000_80003es2lan: 4768 case e1000_ich8lan: 4769 case e1000_ich9lan: 4770 case e1000_ich10lan: 4771 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4772 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4773 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4774 break; 4775 default: 4776 break; 4777 4778 } 4779 } 4780 4781 static int 4782 em_is_valid_ether_addr(u8 *addr) 4783 { 4784 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4785 4786 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4787 return (FALSE); 4788 } 4789 4790 return (TRUE); 4791 } 4792 4793 /* 4794 * Enable PCI Wake On Lan capability 4795 */ 4796 void 4797 em_enable_wakeup(device_t dev) 4798 { 4799 u16 cap, status; 4800 u8 id; 4801 4802 /* First find the capabilities pointer*/ 4803 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 4804 /* Read the PM Capabilities */ 4805 id = pci_read_config(dev, cap, 1); 4806 if (id != PCIY_PMG) /* Something wrong */ 4807 return; 4808 /* OK, we have the power capabilities, so 4809 now get the status register */ 4810 cap += PCIR_POWER_STATUS; 4811 status = pci_read_config(dev, cap, 2); 4812 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4813 pci_write_config(dev, cap, status, 2); 4814 return; 4815 } 4816 4817 4818 /********************************************************************* 4819 * 82544 Coexistence issue workaround. 4820 * There are 2 issues. 4821 * 1. Transmit Hang issue. 4822 * To detect this issue, following equation can be used... 4823 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4824 * If SUM[3:0] is in between 1 to 4, we will have this issue. 4825 * 4826 * 2. DAC issue. 4827 * To detect this issue, following equation can be used... 4828 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4829 * If SUM[3:0] is in between 9 to c, we will have this issue. 4830 * 4831 * 4832 * WORKAROUND: 4833 * Make sure we do not have ending address 4834 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 4835 * 4836 *************************************************************************/ 4837 static u32 4838 em_fill_descriptors (bus_addr_t address, u32 length, 4839 PDESC_ARRAY desc_array) 4840 { 4841 u32 safe_terminator; 4842 4843 /* Since issue is sensitive to length and address.*/ 4844 /* Let us first check the address...*/ 4845 if (length <= 4) { 4846 desc_array->descriptor[0].address = address; 4847 desc_array->descriptor[0].length = length; 4848 desc_array->elements = 1; 4849 return (desc_array->elements); 4850 } 4851 safe_terminator = (u32)((((u32)address & 0x7) + 4852 (length & 0xF)) & 0xF); 4853 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 4854 if (safe_terminator == 0 || 4855 (safe_terminator > 4 && 4856 safe_terminator < 9) || 4857 (safe_terminator > 0xC && 4858 safe_terminator <= 0xF)) { 4859 desc_array->descriptor[0].address = address; 4860 desc_array->descriptor[0].length = length; 4861 desc_array->elements = 1; 4862 return (desc_array->elements); 4863 } 4864 4865 desc_array->descriptor[0].address = address; 4866 desc_array->descriptor[0].length = length - 4; 4867 desc_array->descriptor[1].address = address + (length - 4); 4868 desc_array->descriptor[1].length = 4; 4869 desc_array->elements = 2; 4870 return (desc_array->elements); 4871 } 4872 4873 /********************************************************************** 4874 * 4875 * Update the board statistics counters. 4876 * 4877 **********************************************************************/ 4878 static void 4879 em_update_stats_counters(struct adapter *adapter) 4880 { 4881 struct ifnet *ifp; 4882 4883 if(adapter->hw.phy.media_type == e1000_media_type_copper || 4884 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4885 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4886 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4887 } 4888 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4889 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4890 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4891 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4892 4893 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4894 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4895 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4896 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4897 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4898 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4899 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4900 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4901 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4902 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4903 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4904 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4905 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4906 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4907 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4908 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4909 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4910 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4911 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4912 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4913 4914 /* For the 64-bit byte counters the low dword must be read first. */ 4915 /* Both registers clear on the read of the high dword */ 4916 4917 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 4918 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 4919 4920 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4921 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4922 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4923 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4924 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4925 4926 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4927 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4928 4929 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4930 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4931 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4932 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4933 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4934 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4935 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4936 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4937 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4938 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4939 4940 if (adapter->hw.mac.type >= e1000_82543) { 4941 adapter->stats.algnerrc += 4942 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4943 adapter->stats.rxerrc += 4944 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4945 adapter->stats.tncrs += 4946 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4947 adapter->stats.cexterr += 4948 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4949 adapter->stats.tsctc += 4950 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4951 adapter->stats.tsctfc += 4952 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4953 } 4954 ifp = adapter->ifp; 4955 4956 ifp->if_collisions = adapter->stats.colc; 4957 4958 /* Rx Errors */ 4959 ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + 4960 adapter->stats.crcerrs + adapter->stats.algnerrc + 4961 adapter->stats.ruc + adapter->stats.roc + 4962 adapter->stats.mpc + adapter->stats.cexterr; 4963 4964 /* Tx Errors */ 4965 ifp->if_oerrors = adapter->stats.ecol + 4966 adapter->stats.latecol + adapter->watchdog_events; 4967 } 4968 4969 4970 /********************************************************************** 4971 * 4972 * This routine is called only when em_display_debug_stats is enabled. 4973 * This routine provides a way to take a look at important statistics 4974 * maintained by the driver and hardware. 4975 * 4976 **********************************************************************/ 4977 static void 4978 em_print_debug_info(struct adapter *adapter) 4979 { 4980 device_t dev = adapter->dev; 4981 u8 *hw_addr = adapter->hw.hw_addr; 4982 4983 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 4984 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 4985 E1000_READ_REG(&adapter->hw, E1000_CTRL), 4986 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 4987 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 4988 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 4989 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 4990 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 4991 adapter->hw.fc.high_water, 4992 adapter->hw.fc.low_water); 4993 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 4994 E1000_READ_REG(&adapter->hw, E1000_TIDV), 4995 E1000_READ_REG(&adapter->hw, E1000_TADV)); 4996 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 4997 E1000_READ_REG(&adapter->hw, E1000_RDTR), 4998 E1000_READ_REG(&adapter->hw, E1000_RADV)); 4999 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 5000 (long long)adapter->tx_fifo_wrk_cnt, 5001 (long long)adapter->tx_fifo_reset_cnt); 5002 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5003 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 5004 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 5005 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5006 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 5007 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 5008 device_printf(dev, "Num Tx descriptors avail = %d\n", 5009 adapter->num_tx_desc_avail); 5010 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 5011 adapter->no_tx_desc_avail1); 5012 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 5013 adapter->no_tx_desc_avail2); 5014 device_printf(dev, "Std mbuf failed = %ld\n", 5015 adapter->mbuf_alloc_failed); 5016 device_printf(dev, "Std mbuf cluster failed = %ld\n", 5017 adapter->mbuf_cluster_failed); 5018 device_printf(dev, "Driver dropped packets = %ld\n", 5019 adapter->dropped_pkts); 5020 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 5021 adapter->no_tx_dma_setup); 5022 } 5023 5024 static void 5025 em_print_hw_stats(struct adapter *adapter) 5026 { 5027 device_t dev = adapter->dev; 5028 5029 device_printf(dev, "Excessive collisions = %lld\n", 5030 (long long)adapter->stats.ecol); 5031 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 5032 device_printf(dev, "Symbol errors = %lld\n", 5033 (long long)adapter->stats.symerrs); 5034 #endif 5035 device_printf(dev, "Sequence errors = %lld\n", 5036 (long long)adapter->stats.sec); 5037 device_printf(dev, "Defer count = %lld\n", 5038 (long long)adapter->stats.dc); 5039 device_printf(dev, "Missed Packets = %lld\n", 5040 (long long)adapter->stats.mpc); 5041 device_printf(dev, "Receive No Buffers = %lld\n", 5042 (long long)adapter->stats.rnbc); 5043 /* RLEC is inaccurate on some hardware, calculate our own. */ 5044 device_printf(dev, "Receive Length Errors = %lld\n", 5045 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 5046 device_printf(dev, "Receive errors = %lld\n", 5047 (long long)adapter->stats.rxerrc); 5048 device_printf(dev, "Crc errors = %lld\n", 5049 (long long)adapter->stats.crcerrs); 5050 device_printf(dev, "Alignment errors = %lld\n", 5051 (long long)adapter->stats.algnerrc); 5052 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 5053 (long long)adapter->stats.cexterr); 5054 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 5055 device_printf(dev, "watchdog timeouts = %ld\n", 5056 adapter->watchdog_events); 5057 device_printf(dev, "RX MSIX IRQ = %ld TX MSIX IRQ = %ld" 5058 " LINK MSIX IRQ = %ld\n", adapter->rx_irq, 5059 adapter->tx_irq , adapter->link_irq); 5060 device_printf(dev, "XON Rcvd = %lld\n", 5061 (long long)adapter->stats.xonrxc); 5062 device_printf(dev, "XON Xmtd = %lld\n", 5063 (long long)adapter->stats.xontxc); 5064 device_printf(dev, "XOFF Rcvd = %lld\n", 5065 (long long)adapter->stats.xoffrxc); 5066 device_printf(dev, "XOFF Xmtd = %lld\n", 5067 (long long)adapter->stats.xofftxc); 5068 device_printf(dev, "Good Packets Rcvd = %lld\n", 5069 (long long)adapter->stats.gprc); 5070 device_printf(dev, "Good Packets Xmtd = %lld\n", 5071 (long long)adapter->stats.gptc); 5072 device_printf(dev, "TSO Contexts Xmtd = %lld\n", 5073 (long long)adapter->stats.tsctc); 5074 device_printf(dev, "TSO Contexts Failed = %lld\n", 5075 (long long)adapter->stats.tsctfc); 5076 } 5077 5078 /********************************************************************** 5079 * 5080 * This routine provides a way to dump out the adapter eeprom, 5081 * often a useful debug/service tool. This only dumps the first 5082 * 32 words, stuff that matters is in that extent. 5083 * 5084 **********************************************************************/ 5085 static void 5086 em_print_nvm_info(struct adapter *adapter) 5087 { 5088 u16 eeprom_data; 5089 int i, j, row = 0; 5090 5091 /* Its a bit crude, but it gets the job done */ 5092 printf("\nInterface EEPROM Dump:\n"); 5093 printf("Offset\n0x0000 "); 5094 for (i = 0, j = 0; i < 32; i++, j++) { 5095 if (j == 8) { /* Make the offset block */ 5096 j = 0; ++row; 5097 printf("\n0x00%x0 ",row); 5098 } 5099 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 5100 printf("%04x ", eeprom_data); 5101 } 5102 printf("\n"); 5103 } 5104 5105 static int 5106 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5107 { 5108 struct adapter *adapter; 5109 int error; 5110 int result; 5111 5112 result = -1; 5113 error = sysctl_handle_int(oidp, &result, 0, req); 5114 5115 if (error || !req->newptr) 5116 return (error); 5117 5118 if (result == 1) { 5119 adapter = (struct adapter *)arg1; 5120 em_print_debug_info(adapter); 5121 } 5122 /* 5123 * This value will cause a hex dump of the 5124 * first 32 16-bit words of the EEPROM to 5125 * the screen. 5126 */ 5127 if (result == 2) { 5128 adapter = (struct adapter *)arg1; 5129 em_print_nvm_info(adapter); 5130 } 5131 5132 return (error); 5133 } 5134 5135 5136 static int 5137 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 5138 { 5139 struct adapter *adapter; 5140 int error; 5141 int result; 5142 5143 result = -1; 5144 error = sysctl_handle_int(oidp, &result, 0, req); 5145 5146 if (error || !req->newptr) 5147 return (error); 5148 5149 if (result == 1) { 5150 adapter = (struct adapter *)arg1; 5151 em_print_hw_stats(adapter); 5152 } 5153 5154 return (error); 5155 } 5156 5157 static int 5158 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5159 { 5160 struct em_int_delay_info *info; 5161 struct adapter *adapter; 5162 u32 regval; 5163 int error; 5164 int usecs; 5165 int ticks; 5166 5167 info = (struct em_int_delay_info *)arg1; 5168 usecs = info->value; 5169 error = sysctl_handle_int(oidp, &usecs, 0, req); 5170 if (error != 0 || req->newptr == NULL) 5171 return (error); 5172 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5173 return (EINVAL); 5174 info->value = usecs; 5175 ticks = EM_USECS_TO_TICKS(usecs); 5176 5177 adapter = info->adapter; 5178 5179 EM_CORE_LOCK(adapter); 5180 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 5181 regval = (regval & ~0xffff) | (ticks & 0xffff); 5182 /* Handle a few special cases. */ 5183 switch (info->offset) { 5184 case E1000_RDTR: 5185 break; 5186 case E1000_TIDV: 5187 if (ticks == 0) { 5188 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 5189 /* Don't write 0 into the TIDV register. */ 5190 regval++; 5191 } else 5192 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 5193 break; 5194 } 5195 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 5196 EM_CORE_UNLOCK(adapter); 5197 return (0); 5198 } 5199 5200 static void 5201 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 5202 const char *description, struct em_int_delay_info *info, 5203 int offset, int value) 5204 { 5205 info->adapter = adapter; 5206 info->offset = offset; 5207 info->value = value; 5208 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 5209 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5210 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5211 info, 0, em_sysctl_int_delay, "I", description); 5212 } 5213 5214 #ifndef EM_LEGACY_IRQ 5215 static void 5216 em_add_rx_process_limit(struct adapter *adapter, const char *name, 5217 const char *description, int *limit, int value) 5218 { 5219 *limit = value; 5220 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 5221 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5222 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 5223 } 5224 #endif 5225 5226 #ifdef EM_TIMESYNC 5227 /* 5228 * Initialize the Time Sync Feature 5229 */ 5230 static int 5231 em_tsync_init(struct adapter *adapter) 5232 { 5233 device_t dev = adapter->dev; 5234 u32 tx_ctl, rx_ctl; 5235 5236 5237 E1000_WRITE_REG(&adapter->hw, E1000_TIMINCA, (1<<24) | 5238 20833/PICOSECS_PER_TICK); 5239 5240 adapter->last_stamp = E1000_READ_REG(&adapter->hw, E1000_SYSTIML); 5241 adapter->last_stamp |= (u64)E1000_READ_REG(&adapter->hw, 5242 E1000_SYSTIMH) << 32ULL; 5243 5244 /* Enable the TX side */ 5245 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5246 tx_ctl |= 0x10; 5247 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCTXCTL, tx_ctl); 5248 E1000_WRITE_FLUSH(&adapter->hw); 5249 5250 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5251 if ((tx_ctl & 0x10) == 0) { 5252 device_printf(dev, "Failed to enable TX timestamping\n"); 5253 return (ENXIO); 5254 } 5255 5256 /* Enable RX */ 5257 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5258 rx_ctl |= 0x10; /* Enable the feature */ 5259 rx_ctl |= 0x0a; /* This value turns on Ver 1 and 2 */ 5260 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCRXCTL, rx_ctl); 5261 5262 /* 5263 * Ethertype Stamping (Ethertype = 0x88F7) 5264 */ 5265 E1000_WRITE_REG(&adapter->hw, E1000_RXMTRL, htonl(0x440088f7)); 5266 5267 /* 5268 * Source Port Queue Filter Setup: 5269 * this is for UDP port filtering 5270 */ 5271 E1000_WRITE_REG(&adapter->hw, E1000_RXUDP, htons(TSYNC_PORT)); 5272 /* Protocol = UDP, enable Timestamp, and filter on source/protocol */ 5273 5274 E1000_WRITE_FLUSH(&adapter->hw); 5275 5276 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5277 if ((rx_ctl & 0x10) == 0) { 5278 device_printf(dev, "Failed to enable RX timestamping\n"); 5279 return (ENXIO); 5280 } 5281 5282 device_printf(dev, "IEEE 1588 Precision Time Protocol enabled\n"); 5283 5284 return (0); 5285 } 5286 5287 /* 5288 * Disable the Time Sync Feature 5289 */ 5290 static void 5291 em_tsync_disable(struct adapter *adapter) 5292 { 5293 u32 tx_ctl, rx_ctl; 5294 5295 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5296 tx_ctl &= ~0x10; 5297 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCTXCTL, tx_ctl); 5298 E1000_WRITE_FLUSH(&adapter->hw); 5299 5300 /* Invalidate TX Timestamp */ 5301 E1000_READ_REG(&adapter->hw, E1000_TXSTMPH); 5302 5303 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5304 if (tx_ctl & 0x10) 5305 HW_DEBUGOUT("Failed to disable TX timestamping\n"); 5306 5307 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5308 rx_ctl &= ~0x10; 5309 5310 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCRXCTL, rx_ctl); 5311 E1000_WRITE_FLUSH(&adapter->hw); 5312 5313 /* Invalidate RX Timestamp */ 5314 E1000_READ_REG(&adapter->hw, E1000_RXSATRH); 5315 5316 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5317 if (rx_ctl & 0x10) 5318 HW_DEBUGOUT("Failed to disable RX timestamping\n"); 5319 5320 return; 5321 } 5322 #endif /* EM_TIMESYNC */ 5323