1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_device_polling.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <sys/eventhandler.h> 55 #ifdef EM_TIMESYNC 56 #include <sys/ioccom.h> 57 #include <sys/time.h> 58 #endif 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/if.h> 65 #include <net/if_arp.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 69 #include <net/if_types.h> 70 #include <net/if_vlan_var.h> 71 72 #include <netinet/in_systm.h> 73 #include <netinet/in.h> 74 #include <netinet/if_ether.h> 75 #include <netinet/ip.h> 76 #include <netinet/ip6.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 80 #include <machine/in_cksum.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 84 #include "e1000_api.h" 85 #include "e1000_82571.h" 86 #include "if_em.h" 87 88 /********************************************************************* 89 * Set this to one to display debug statistics 90 *********************************************************************/ 91 int em_display_debug_stats = 0; 92 93 /********************************************************************* 94 * Driver version: 95 *********************************************************************/ 96 char em_driver_version[] = "6.9.6"; 97 98 99 /********************************************************************* 100 * PCI Device ID Table 101 * 102 * Used by probe to select devices to load on 103 * Last field stores an index into e1000_strings 104 * Last entry must be all 0s 105 * 106 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 107 *********************************************************************/ 108 109 static em_vendor_info_t em_vendor_info_array[] = 110 { 111 /* Intel(R) PRO/1000 Network Connection */ 112 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 118 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 120 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 122 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 123 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 126 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 128 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 131 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 134 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 136 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 142 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 145 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 147 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 151 PCI_ANY_ID, PCI_ANY_ID, 0}, 152 153 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 157 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 158 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 159 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 161 PCI_ANY_ID, PCI_ANY_ID, 0}, 162 { 0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 163 PCI_ANY_ID, PCI_ANY_ID, 0}, 164 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 165 PCI_ANY_ID, PCI_ANY_ID, 0}, 166 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 167 PCI_ANY_ID, PCI_ANY_ID, 0}, 168 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 169 PCI_ANY_ID, PCI_ANY_ID, 0}, 170 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 171 PCI_ANY_ID, PCI_ANY_ID, 0}, 172 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 173 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 174 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 175 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 176 177 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 178 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 179 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 180 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 181 PCI_ANY_ID, PCI_ANY_ID, 0}, 182 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 183 PCI_ANY_ID, PCI_ANY_ID, 0}, 184 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 185 PCI_ANY_ID, PCI_ANY_ID, 0}, 186 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 187 PCI_ANY_ID, PCI_ANY_ID, 0}, 188 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 189 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 190 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 191 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 192 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 193 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 194 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 195 196 { 0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 197 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 198 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 199 { 0x8086, E1000_DEV_ID_ICH9_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 200 { 0x8086, E1000_DEV_ID_ICH9_IGP_M_V, PCI_ANY_ID, PCI_ANY_ID, 0}, 201 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 202 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 203 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 204 { 0x8086, E1000_DEV_ID_ICH9_BM, PCI_ANY_ID, PCI_ANY_ID, 0}, 205 { 0x8086, E1000_DEV_ID_82574L, PCI_ANY_ID, PCI_ANY_ID, 0}, 206 { 0x8086, E1000_DEV_ID_ICH10_R_BM_LM, PCI_ANY_ID, PCI_ANY_ID, 0}, 207 { 0x8086, E1000_DEV_ID_ICH10_R_BM_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 208 { 0x8086, E1000_DEV_ID_ICH10_R_BM_V, PCI_ANY_ID, PCI_ANY_ID, 0}, 209 { 0x8086, E1000_DEV_ID_ICH10_D_BM_LM, PCI_ANY_ID, PCI_ANY_ID, 0}, 210 { 0x8086, E1000_DEV_ID_ICH10_D_BM_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 211 /* required last entry */ 212 { 0, 0, 0, 0, 0} 213 }; 214 215 /********************************************************************* 216 * Table of branding strings for all supported NICs. 217 *********************************************************************/ 218 219 static char *em_strings[] = { 220 "Intel(R) PRO/1000 Network Connection" 221 }; 222 223 /********************************************************************* 224 * Function prototypes 225 *********************************************************************/ 226 static int em_probe(device_t); 227 static int em_attach(device_t); 228 static int em_detach(device_t); 229 static int em_shutdown(device_t); 230 static int em_suspend(device_t); 231 static int em_resume(device_t); 232 static void em_start(struct ifnet *); 233 static void em_start_locked(struct ifnet *ifp); 234 static int em_ioctl(struct ifnet *, u_long, caddr_t); 235 static void em_watchdog(struct adapter *); 236 static void em_init(void *); 237 static void em_init_locked(struct adapter *); 238 static void em_stop(void *); 239 static void em_media_status(struct ifnet *, struct ifmediareq *); 240 static int em_media_change(struct ifnet *); 241 static void em_identify_hardware(struct adapter *); 242 static int em_allocate_pci_resources(struct adapter *); 243 static int em_allocate_legacy(struct adapter *adapter); 244 static int em_allocate_msix(struct adapter *adapter); 245 static int em_setup_msix(struct adapter *); 246 static void em_free_pci_resources(struct adapter *); 247 static void em_local_timer(void *); 248 static int em_hardware_init(struct adapter *); 249 static void em_setup_interface(device_t, struct adapter *); 250 static void em_setup_transmit_structures(struct adapter *); 251 static void em_initialize_transmit_unit(struct adapter *); 252 static int em_setup_receive_structures(struct adapter *); 253 static void em_initialize_receive_unit(struct adapter *); 254 static void em_enable_intr(struct adapter *); 255 static void em_disable_intr(struct adapter *); 256 static void em_free_transmit_structures(struct adapter *); 257 static void em_free_receive_structures(struct adapter *); 258 static void em_update_stats_counters(struct adapter *); 259 static void em_txeof(struct adapter *); 260 static void em_tx_purge(struct adapter *); 261 static int em_allocate_receive_structures(struct adapter *); 262 static int em_allocate_transmit_structures(struct adapter *); 263 static int em_rxeof(struct adapter *, int); 264 #ifndef __NO_STRICT_ALIGNMENT 265 static int em_fixup_rx(struct adapter *); 266 #endif 267 static void em_receive_checksum(struct adapter *, struct e1000_rx_desc *, 268 struct mbuf *); 269 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 270 u32 *, u32 *); 271 #if __FreeBSD_version >= 700000 272 static bool em_tso_setup(struct adapter *, struct mbuf *, 273 u32 *, u32 *); 274 #endif /* FreeBSD_version >= 700000 */ 275 static void em_set_promisc(struct adapter *); 276 static void em_disable_promisc(struct adapter *); 277 static void em_set_multi(struct adapter *); 278 static void em_print_hw_stats(struct adapter *); 279 static void em_update_link_status(struct adapter *); 280 static int em_get_buf(struct adapter *, int); 281 282 static void em_register_vlan(void *, struct ifnet *, u16); 283 static void em_unregister_vlan(void *, struct ifnet *, u16); 284 285 static int em_xmit(struct adapter *, struct mbuf **); 286 static void em_smartspeed(struct adapter *); 287 static int em_82547_fifo_workaround(struct adapter *, int); 288 static void em_82547_update_fifo_head(struct adapter *, int); 289 static int em_82547_tx_fifo_reset(struct adapter *); 290 static void em_82547_move_tail(void *); 291 static int em_dma_malloc(struct adapter *, bus_size_t, 292 struct em_dma_alloc *, int); 293 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 294 static void em_print_debug_info(struct adapter *); 295 static void em_print_nvm_info(struct adapter *); 296 static int em_is_valid_ether_addr(u8 *); 297 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 298 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 299 static u32 em_fill_descriptors (bus_addr_t address, u32 length, 300 PDESC_ARRAY desc_array); 301 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 302 static void em_add_int_delay_sysctl(struct adapter *, const char *, 303 const char *, struct em_int_delay_info *, int, int); 304 /* Management and WOL Support */ 305 static void em_init_manageability(struct adapter *); 306 static void em_release_manageability(struct adapter *); 307 static void em_get_hw_control(struct adapter *); 308 static void em_release_hw_control(struct adapter *); 309 static void em_enable_wakeup(device_t); 310 311 #ifdef EM_TIMESYNC 312 /* Precision Time sync support */ 313 static int em_tsync_init(struct adapter *); 314 static void em_tsync_disable(struct adapter *); 315 #endif 316 317 #ifdef EM_LEGACY_IRQ 318 static void em_intr(void *); 319 #else /* FAST IRQ */ 320 #if __FreeBSD_version < 700000 321 static void em_irq_fast(void *); 322 #else 323 static int em_irq_fast(void *); 324 #endif 325 /* MSIX handlers */ 326 static void em_msix_tx(void *); 327 static void em_msix_rx(void *); 328 static void em_msix_link(void *); 329 static void em_add_rx_process_limit(struct adapter *, const char *, 330 const char *, int *, int); 331 static void em_handle_rxtx(void *context, int pending); 332 static void em_handle_rx(void *context, int pending); 333 static void em_handle_tx(void *context, int pending); 334 static void em_handle_link(void *context, int pending); 335 #endif /* EM_LEGACY_IRQ */ 336 337 #ifdef DEVICE_POLLING 338 static poll_handler_t em_poll; 339 #endif /* POLLING */ 340 341 /********************************************************************* 342 * FreeBSD Device Interface Entry Points 343 *********************************************************************/ 344 345 static device_method_t em_methods[] = { 346 /* Device interface */ 347 DEVMETHOD(device_probe, em_probe), 348 DEVMETHOD(device_attach, em_attach), 349 DEVMETHOD(device_detach, em_detach), 350 DEVMETHOD(device_shutdown, em_shutdown), 351 DEVMETHOD(device_suspend, em_suspend), 352 DEVMETHOD(device_resume, em_resume), 353 {0, 0} 354 }; 355 356 static driver_t em_driver = { 357 "em", em_methods, sizeof(struct adapter), 358 }; 359 360 static devclass_t em_devclass; 361 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 362 MODULE_DEPEND(em, pci, 1, 1, 1); 363 MODULE_DEPEND(em, ether, 1, 1, 1); 364 365 /********************************************************************* 366 * Tunable default values. 367 *********************************************************************/ 368 369 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 370 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 371 #define M_TSO_LEN 66 372 373 /* Allow common code without TSO */ 374 #ifndef CSUM_TSO 375 #define CSUM_TSO 0 376 #endif 377 378 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 379 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 380 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 381 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 382 static int em_rxd = EM_DEFAULT_RXD; 383 static int em_txd = EM_DEFAULT_TXD; 384 static int em_smart_pwr_down = FALSE; 385 /* Controls whether promiscuous also shows bad packets */ 386 static int em_debug_sbp = FALSE; 387 /* Local switch for MSI/MSIX */ 388 static int em_enable_msi = TRUE; 389 390 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 391 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 392 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 393 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 394 TUNABLE_INT("hw.em.rxd", &em_rxd); 395 TUNABLE_INT("hw.em.txd", &em_txd); 396 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 397 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 398 TUNABLE_INT("hw.em.enable_msi", &em_enable_msi); 399 400 #ifndef EM_LEGACY_IRQ 401 /* How many packets rxeof tries to clean at a time */ 402 static int em_rx_process_limit = 100; 403 TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 404 #endif 405 406 /* Global used in WOL setup with multiport cards */ 407 static int global_quad_port_a = 0; 408 409 /********************************************************************* 410 * Device identification routine 411 * 412 * em_probe determines if the driver should be loaded on 413 * adapter based on PCI vendor/device id of the adapter. 414 * 415 * return BUS_PROBE_DEFAULT on success, positive on failure 416 *********************************************************************/ 417 418 static int 419 em_probe(device_t dev) 420 { 421 char adapter_name[60]; 422 u16 pci_vendor_id = 0; 423 u16 pci_device_id = 0; 424 u16 pci_subvendor_id = 0; 425 u16 pci_subdevice_id = 0; 426 em_vendor_info_t *ent; 427 428 INIT_DEBUGOUT("em_probe: begin"); 429 430 pci_vendor_id = pci_get_vendor(dev); 431 if (pci_vendor_id != EM_VENDOR_ID) 432 return (ENXIO); 433 434 pci_device_id = pci_get_device(dev); 435 pci_subvendor_id = pci_get_subvendor(dev); 436 pci_subdevice_id = pci_get_subdevice(dev); 437 438 ent = em_vendor_info_array; 439 while (ent->vendor_id != 0) { 440 if ((pci_vendor_id == ent->vendor_id) && 441 (pci_device_id == ent->device_id) && 442 443 ((pci_subvendor_id == ent->subvendor_id) || 444 (ent->subvendor_id == PCI_ANY_ID)) && 445 446 ((pci_subdevice_id == ent->subdevice_id) || 447 (ent->subdevice_id == PCI_ANY_ID))) { 448 sprintf(adapter_name, "%s %s", 449 em_strings[ent->index], 450 em_driver_version); 451 device_set_desc_copy(dev, adapter_name); 452 return (BUS_PROBE_DEFAULT); 453 } 454 ent++; 455 } 456 457 return (ENXIO); 458 } 459 460 /********************************************************************* 461 * Device initialization routine 462 * 463 * The attach entry point is called when the driver is being loaded. 464 * This routine identifies the type of hardware, allocates all resources 465 * and initializes the hardware. 466 * 467 * return 0 on success, positive on failure 468 *********************************************************************/ 469 470 static int 471 em_attach(device_t dev) 472 { 473 struct adapter *adapter; 474 int tsize, rsize; 475 int error = 0; 476 u16 eeprom_data, device_id; 477 478 INIT_DEBUGOUT("em_attach: begin"); 479 480 adapter = device_get_softc(dev); 481 adapter->dev = adapter->osdep.dev = dev; 482 EM_CORE_LOCK_INIT(adapter, device_get_nameunit(dev)); 483 EM_TX_LOCK_INIT(adapter, device_get_nameunit(dev)); 484 EM_RX_LOCK_INIT(adapter, device_get_nameunit(dev)); 485 486 /* SYSCTL stuff */ 487 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 490 em_sysctl_debug_info, "I", "Debug Information"); 491 492 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 493 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 494 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 495 em_sysctl_stats, "I", "Statistics"); 496 497 callout_init_mtx(&adapter->timer, &adapter->core_mtx, 0); 498 callout_init_mtx(&adapter->tx_fifo_timer, &adapter->tx_mtx, 0); 499 500 /* Determine hardware and mac info */ 501 em_identify_hardware(adapter); 502 503 /* Setup PCI resources */ 504 if (em_allocate_pci_resources(adapter)) { 505 device_printf(dev, "Allocation of PCI resources failed\n"); 506 error = ENXIO; 507 goto err_pci; 508 } 509 510 /* 511 ** For ICH8 and family we need to 512 ** map the flash memory, and this 513 ** must happen after the MAC is 514 ** identified 515 */ 516 if ((adapter->hw.mac.type == e1000_ich8lan) || 517 (adapter->hw.mac.type == e1000_ich10lan) || 518 (adapter->hw.mac.type == e1000_ich9lan)) { 519 int rid = EM_BAR_TYPE_FLASH; 520 adapter->flash = bus_alloc_resource_any(dev, 521 SYS_RES_MEMORY, &rid, RF_ACTIVE); 522 if (adapter->flash == NULL) { 523 device_printf(dev, "Mapping of Flash failed\n"); 524 error = ENXIO; 525 goto err_pci; 526 } 527 /* This is used in the shared code */ 528 adapter->hw.flash_address = (u8 *)adapter->flash; 529 adapter->osdep.flash_bus_space_tag = 530 rman_get_bustag(adapter->flash); 531 adapter->osdep.flash_bus_space_handle = 532 rman_get_bushandle(adapter->flash); 533 } 534 535 /* Do Shared Code initialization */ 536 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 537 device_printf(dev, "Setup of Shared code failed\n"); 538 error = ENXIO; 539 goto err_pci; 540 } 541 542 e1000_get_bus_info(&adapter->hw); 543 544 /* Set up some sysctls for the tunable interrupt delays */ 545 em_add_int_delay_sysctl(adapter, "rx_int_delay", 546 "receive interrupt delay in usecs", &adapter->rx_int_delay, 547 E1000_REGISTER(&adapter->hw, E1000_RDTR), em_rx_int_delay_dflt); 548 em_add_int_delay_sysctl(adapter, "tx_int_delay", 549 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 550 E1000_REGISTER(&adapter->hw, E1000_TIDV), em_tx_int_delay_dflt); 551 if (adapter->hw.mac.type >= e1000_82540) { 552 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 553 "receive interrupt delay limit in usecs", 554 &adapter->rx_abs_int_delay, 555 E1000_REGISTER(&adapter->hw, E1000_RADV), 556 em_rx_abs_int_delay_dflt); 557 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 558 "transmit interrupt delay limit in usecs", 559 &adapter->tx_abs_int_delay, 560 E1000_REGISTER(&adapter->hw, E1000_TADV), 561 em_tx_abs_int_delay_dflt); 562 } 563 564 #ifndef EM_LEGACY_IRQ 565 /* Sysctls for limiting the amount of work done in the taskqueue */ 566 em_add_rx_process_limit(adapter, "rx_processing_limit", 567 "max number of rx packets to process", &adapter->rx_process_limit, 568 em_rx_process_limit); 569 #endif 570 571 /* 572 * Validate number of transmit and receive descriptors. It 573 * must not exceed hardware maximum, and must be multiple 574 * of E1000_DBA_ALIGN. 575 */ 576 if (((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN) != 0 || 577 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 578 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 579 (em_txd < EM_MIN_TXD)) { 580 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 581 EM_DEFAULT_TXD, em_txd); 582 adapter->num_tx_desc = EM_DEFAULT_TXD; 583 } else 584 adapter->num_tx_desc = em_txd; 585 if (((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN) != 0 || 586 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 587 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 588 (em_rxd < EM_MIN_RXD)) { 589 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 590 EM_DEFAULT_RXD, em_rxd); 591 adapter->num_rx_desc = EM_DEFAULT_RXD; 592 } else 593 adapter->num_rx_desc = em_rxd; 594 595 adapter->hw.mac.autoneg = DO_AUTO_NEG; 596 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 597 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 598 adapter->rx_buffer_len = 2048; 599 600 e1000_init_script_state_82541(&adapter->hw, TRUE); 601 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 602 603 /* Copper options */ 604 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 605 adapter->hw.phy.mdix = AUTO_ALL_MODES; 606 adapter->hw.phy.disable_polarity_correction = FALSE; 607 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 608 } 609 610 /* 611 * Set the frame limits assuming 612 * standard ethernet sized frames. 613 */ 614 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 615 adapter->min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE; 616 617 /* 618 * This controls when hardware reports transmit completion 619 * status. 620 */ 621 adapter->hw.mac.report_tx_early = 1; 622 623 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 624 EM_DBA_ALIGN); 625 626 /* Allocate Transmit Descriptor ring */ 627 if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { 628 device_printf(dev, "Unable to allocate tx_desc memory\n"); 629 error = ENOMEM; 630 goto err_tx_desc; 631 } 632 adapter->tx_desc_base = 633 (struct e1000_tx_desc *)adapter->txdma.dma_vaddr; 634 635 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 636 EM_DBA_ALIGN); 637 638 /* Allocate Receive Descriptor ring */ 639 if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { 640 device_printf(dev, "Unable to allocate rx_desc memory\n"); 641 error = ENOMEM; 642 goto err_rx_desc; 643 } 644 adapter->rx_desc_base = 645 (struct e1000_rx_desc *)adapter->rxdma.dma_vaddr; 646 647 /* Make sure we have a good EEPROM before we read from it */ 648 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 649 /* 650 ** Some PCI-E parts fail the first check due to 651 ** the link being in sleep state, call it again, 652 ** if it fails a second time its a real issue. 653 */ 654 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 655 device_printf(dev, 656 "The EEPROM Checksum Is Not Valid\n"); 657 error = EIO; 658 goto err_hw_init; 659 } 660 } 661 662 /* Initialize the hardware */ 663 if (em_hardware_init(adapter)) { 664 device_printf(dev, "Unable to initialize the hardware\n"); 665 error = EIO; 666 goto err_hw_init; 667 } 668 669 /* Copy the permanent MAC address out of the EEPROM */ 670 if (e1000_read_mac_addr(&adapter->hw) < 0) { 671 device_printf(dev, "EEPROM read error while reading MAC" 672 " address\n"); 673 error = EIO; 674 goto err_hw_init; 675 } 676 677 if (!em_is_valid_ether_addr(adapter->hw.mac.addr)) { 678 device_printf(dev, "Invalid MAC address\n"); 679 error = EIO; 680 goto err_hw_init; 681 } 682 683 /* Allocate transmit descriptors and buffers */ 684 if (em_allocate_transmit_structures(adapter)) { 685 device_printf(dev, "Could not setup transmit structures\n"); 686 error = ENOMEM; 687 goto err_tx_struct; 688 } 689 690 /* Allocate receive descriptors and buffers */ 691 if (em_allocate_receive_structures(adapter)) { 692 device_printf(dev, "Could not setup receive structures\n"); 693 error = ENOMEM; 694 goto err_rx_struct; 695 } 696 697 /* 698 ** Do interrupt configuration 699 */ 700 if (adapter->msi > 1) /* Do MSI/X */ 701 error = em_allocate_msix(adapter); 702 else /* MSI or Legacy */ 703 error = em_allocate_legacy(adapter); 704 if (error) 705 goto err_rx_struct; 706 707 /* Setup OS specific network interface */ 708 em_setup_interface(dev, adapter); 709 710 /* Initialize statistics */ 711 em_update_stats_counters(adapter); 712 713 adapter->hw.mac.get_link_status = 1; 714 em_update_link_status(adapter); 715 716 /* Indicate SOL/IDER usage */ 717 if (e1000_check_reset_block(&adapter->hw)) 718 device_printf(dev, 719 "PHY reset is blocked due to SOL/IDER session.\n"); 720 721 /* Determine if we have to control management hardware */ 722 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 723 724 /* 725 * Setup Wake-on-Lan 726 */ 727 switch (adapter->hw.mac.type) { 728 729 case e1000_82542: 730 case e1000_82543: 731 break; 732 case e1000_82546: 733 case e1000_82546_rev_3: 734 case e1000_82571: 735 case e1000_80003es2lan: 736 if (adapter->hw.bus.func == 1) 737 e1000_read_nvm(&adapter->hw, 738 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 739 else 740 e1000_read_nvm(&adapter->hw, 741 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 742 eeprom_data &= EM_EEPROM_APME; 743 break; 744 default: 745 /* APME bit in EEPROM is mapped to WUC.APME */ 746 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & 747 E1000_WUC_APME; 748 break; 749 } 750 if (eeprom_data) 751 adapter->wol = E1000_WUFC_MAG; 752 /* 753 * We have the eeprom settings, now apply the special cases 754 * where the eeprom may be wrong or the board won't support 755 * wake on lan on a particular port 756 */ 757 device_id = pci_get_device(dev); 758 switch (device_id) { 759 case E1000_DEV_ID_82546GB_PCIE: 760 adapter->wol = 0; 761 break; 762 case E1000_DEV_ID_82546EB_FIBER: 763 case E1000_DEV_ID_82546GB_FIBER: 764 case E1000_DEV_ID_82571EB_FIBER: 765 /* Wake events only supported on port A for dual fiber 766 * regardless of eeprom setting */ 767 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 768 E1000_STATUS_FUNC_1) 769 adapter->wol = 0; 770 break; 771 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 772 case E1000_DEV_ID_82571EB_QUAD_COPPER: 773 case E1000_DEV_ID_82571EB_QUAD_FIBER: 774 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 775 /* if quad port adapter, disable WoL on all but port A */ 776 if (global_quad_port_a != 0) 777 adapter->wol = 0; 778 /* Reset for multiple quad port adapters */ 779 if (++global_quad_port_a == 4) 780 global_quad_port_a = 0; 781 break; 782 } 783 784 /* Do we need workaround for 82544 PCI-X adapter? */ 785 if (adapter->hw.bus.type == e1000_bus_type_pcix && 786 adapter->hw.mac.type == e1000_82544) 787 adapter->pcix_82544 = TRUE; 788 else 789 adapter->pcix_82544 = FALSE; 790 791 /* Register for VLAN events */ 792 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 793 em_register_vlan, 0, EVENTHANDLER_PRI_FIRST); 794 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 795 em_unregister_vlan, 0, EVENTHANDLER_PRI_FIRST); 796 797 /* Tell the stack that the interface is not active */ 798 adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 799 800 INIT_DEBUGOUT("em_attach: end"); 801 802 return (0); 803 804 err_rx_struct: 805 em_free_transmit_structures(adapter); 806 err_tx_struct: 807 err_hw_init: 808 em_release_hw_control(adapter); 809 em_dma_free(adapter, &adapter->rxdma); 810 err_rx_desc: 811 em_dma_free(adapter, &adapter->txdma); 812 err_tx_desc: 813 err_pci: 814 em_free_pci_resources(adapter); 815 EM_TX_LOCK_DESTROY(adapter); 816 EM_RX_LOCK_DESTROY(adapter); 817 EM_CORE_LOCK_DESTROY(adapter); 818 819 return (error); 820 } 821 822 /********************************************************************* 823 * Device removal routine 824 * 825 * The detach entry point is called when the driver is being removed. 826 * This routine stops the adapter and deallocates all the resources 827 * that were allocated for driver operation. 828 * 829 * return 0 on success, positive on failure 830 *********************************************************************/ 831 832 static int 833 em_detach(device_t dev) 834 { 835 struct adapter *adapter = device_get_softc(dev); 836 struct ifnet *ifp = adapter->ifp; 837 838 INIT_DEBUGOUT("em_detach: begin"); 839 840 /* Make sure VLANS are not using driver */ 841 #if __FreeBSD_version >= 700000 842 if (adapter->ifp->if_vlantrunk != NULL) { 843 #else 844 if (adapter->ifp->if_nvlans != 0) { 845 #endif 846 device_printf(dev,"Vlan in use, detach first\n"); 847 return (EBUSY); 848 } 849 850 #ifdef DEVICE_POLLING 851 if (ifp->if_capenable & IFCAP_POLLING) 852 ether_poll_deregister(ifp); 853 #endif 854 855 EM_CORE_LOCK(adapter); 856 EM_TX_LOCK(adapter); 857 adapter->in_detach = 1; 858 em_stop(adapter); 859 e1000_phy_hw_reset(&adapter->hw); 860 861 em_release_manageability(adapter); 862 863 if (((adapter->hw.mac.type == e1000_82573) || 864 (adapter->hw.mac.type == e1000_ich8lan) || 865 (adapter->hw.mac.type == e1000_ich10lan) || 866 (adapter->hw.mac.type == e1000_ich9lan)) && 867 e1000_check_mng_mode(&adapter->hw)) 868 em_release_hw_control(adapter); 869 870 if (adapter->wol) { 871 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 872 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 873 em_enable_wakeup(dev); 874 } 875 876 EM_TX_UNLOCK(adapter); 877 EM_CORE_UNLOCK(adapter); 878 879 /* Unregister VLAN events */ 880 if (adapter->vlan_attach != NULL) 881 EVENTHANDLER_DEREGISTER(vlan_config, adapter->vlan_attach); 882 if (adapter->vlan_detach != NULL) 883 EVENTHANDLER_DEREGISTER(vlan_unconfig, adapter->vlan_detach); 884 885 ether_ifdetach(adapter->ifp); 886 callout_drain(&adapter->timer); 887 callout_drain(&adapter->tx_fifo_timer); 888 889 em_free_pci_resources(adapter); 890 bus_generic_detach(dev); 891 if_free(ifp); 892 893 em_free_transmit_structures(adapter); 894 em_free_receive_structures(adapter); 895 896 /* Free Transmit Descriptor ring */ 897 if (adapter->tx_desc_base) { 898 em_dma_free(adapter, &adapter->txdma); 899 adapter->tx_desc_base = NULL; 900 } 901 902 /* Free Receive Descriptor ring */ 903 if (adapter->rx_desc_base) { 904 em_dma_free(adapter, &adapter->rxdma); 905 adapter->rx_desc_base = NULL; 906 } 907 908 EM_TX_LOCK_DESTROY(adapter); 909 EM_RX_LOCK_DESTROY(adapter); 910 EM_CORE_LOCK_DESTROY(adapter); 911 912 return (0); 913 } 914 915 /********************************************************************* 916 * 917 * Shutdown entry point 918 * 919 **********************************************************************/ 920 921 static int 922 em_shutdown(device_t dev) 923 { 924 return em_suspend(dev); 925 } 926 927 /* 928 * Suspend/resume device methods. 929 */ 930 static int 931 em_suspend(device_t dev) 932 { 933 struct adapter *adapter = device_get_softc(dev); 934 935 EM_CORE_LOCK(adapter); 936 937 EM_TX_LOCK(adapter); 938 em_stop(adapter); 939 EM_TX_UNLOCK(adapter); 940 941 em_release_manageability(adapter); 942 943 if (((adapter->hw.mac.type == e1000_82573) || 944 (adapter->hw.mac.type == e1000_ich8lan) || 945 (adapter->hw.mac.type == e1000_ich10lan) || 946 (adapter->hw.mac.type == e1000_ich9lan)) && 947 e1000_check_mng_mode(&adapter->hw)) 948 em_release_hw_control(adapter); 949 950 if (adapter->wol) { 951 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 952 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 953 em_enable_wakeup(dev); 954 } 955 956 EM_CORE_UNLOCK(adapter); 957 958 return bus_generic_suspend(dev); 959 } 960 961 static int 962 em_resume(device_t dev) 963 { 964 struct adapter *adapter = device_get_softc(dev); 965 struct ifnet *ifp = adapter->ifp; 966 967 EM_CORE_LOCK(adapter); 968 em_init_locked(adapter); 969 em_init_manageability(adapter); 970 EM_CORE_UNLOCK(adapter); 971 em_start(ifp); 972 973 return bus_generic_resume(dev); 974 } 975 976 977 /********************************************************************* 978 * Transmit entry point 979 * 980 * em_start is called by the stack to initiate a transmit. 981 * The driver will remain in this routine as long as there are 982 * packets to transmit and transmit resources are available. 983 * In case resources are not available stack is notified and 984 * the packet is requeued. 985 **********************************************************************/ 986 987 static void 988 em_start_locked(struct ifnet *ifp) 989 { 990 struct adapter *adapter = ifp->if_softc; 991 struct mbuf *m_head; 992 993 EM_TX_LOCK_ASSERT(adapter); 994 995 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 996 IFF_DRV_RUNNING) 997 return; 998 if (!adapter->link_active) 999 return; 1000 1001 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1002 1003 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1004 if (m_head == NULL) 1005 break; 1006 /* 1007 * Encapsulation can modify our pointer, and or make it 1008 * NULL on failure. In that event, we can't requeue. 1009 */ 1010 if (em_xmit(adapter, &m_head)) { 1011 if (m_head == NULL) 1012 break; 1013 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1014 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1015 break; 1016 } 1017 1018 /* Send a copy of the frame to the BPF listener */ 1019 ETHER_BPF_MTAP(ifp, m_head); 1020 1021 /* Set timeout in case hardware has problems transmitting. */ 1022 adapter->watchdog_timer = EM_TX_TIMEOUT; 1023 } 1024 } 1025 1026 static void 1027 em_start(struct ifnet *ifp) 1028 { 1029 struct adapter *adapter = ifp->if_softc; 1030 1031 EM_TX_LOCK(adapter); 1032 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1033 em_start_locked(ifp); 1034 EM_TX_UNLOCK(adapter); 1035 } 1036 1037 /********************************************************************* 1038 * Ioctl entry point 1039 * 1040 * em_ioctl is called when the user wants to configure the 1041 * interface. 1042 * 1043 * return 0 on success, positive on failure 1044 **********************************************************************/ 1045 1046 static int 1047 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1048 { 1049 struct adapter *adapter = ifp->if_softc; 1050 struct ifreq *ifr = (struct ifreq *)data; 1051 #ifdef INET 1052 struct ifaddr *ifa = (struct ifaddr *)data; 1053 #endif 1054 int error = 0; 1055 1056 if (adapter->in_detach) 1057 return (error); 1058 1059 switch (command) { 1060 case SIOCSIFADDR: 1061 #ifdef INET 1062 if (ifa->ifa_addr->sa_family == AF_INET) { 1063 /* 1064 * XXX 1065 * Since resetting hardware takes a very long time 1066 * and results in link renegotiation we only 1067 * initialize the hardware only when it is absolutely 1068 * required. 1069 */ 1070 ifp->if_flags |= IFF_UP; 1071 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1072 EM_CORE_LOCK(adapter); 1073 em_init_locked(adapter); 1074 EM_CORE_UNLOCK(adapter); 1075 } 1076 arp_ifinit(ifp, ifa); 1077 } else 1078 #endif 1079 error = ether_ioctl(ifp, command, data); 1080 break; 1081 case SIOCSIFMTU: 1082 { 1083 int max_frame_size; 1084 u16 eeprom_data = 0; 1085 1086 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1087 1088 EM_CORE_LOCK(adapter); 1089 switch (adapter->hw.mac.type) { 1090 case e1000_82573: 1091 /* 1092 * 82573 only supports jumbo frames 1093 * if ASPM is disabled. 1094 */ 1095 e1000_read_nvm(&adapter->hw, 1096 NVM_INIT_3GIO_3, 1, &eeprom_data); 1097 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1098 max_frame_size = ETHER_MAX_LEN; 1099 break; 1100 } 1101 /* Allow Jumbo frames - fall thru */ 1102 case e1000_82571: 1103 case e1000_82572: 1104 case e1000_ich9lan: 1105 case e1000_ich10lan: 1106 case e1000_82574: 1107 case e1000_80003es2lan: /* Limit Jumbo Frame size */ 1108 max_frame_size = 9234; 1109 break; 1110 /* Adapters that do not support jumbo frames */ 1111 case e1000_82542: 1112 case e1000_ich8lan: 1113 max_frame_size = ETHER_MAX_LEN; 1114 break; 1115 default: 1116 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1117 } 1118 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1119 ETHER_CRC_LEN) { 1120 EM_CORE_UNLOCK(adapter); 1121 error = EINVAL; 1122 break; 1123 } 1124 1125 ifp->if_mtu = ifr->ifr_mtu; 1126 adapter->max_frame_size = 1127 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1128 em_init_locked(adapter); 1129 EM_CORE_UNLOCK(adapter); 1130 break; 1131 } 1132 case SIOCSIFFLAGS: 1133 IOCTL_DEBUGOUT("ioctl rcv'd:\ 1134 SIOCSIFFLAGS (Set Interface Flags)"); 1135 EM_CORE_LOCK(adapter); 1136 if (ifp->if_flags & IFF_UP) { 1137 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1138 if ((ifp->if_flags ^ adapter->if_flags) & 1139 (IFF_PROMISC | IFF_ALLMULTI)) { 1140 em_disable_promisc(adapter); 1141 em_set_promisc(adapter); 1142 } 1143 } else 1144 em_init_locked(adapter); 1145 } else 1146 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1147 EM_TX_LOCK(adapter); 1148 em_stop(adapter); 1149 EM_TX_UNLOCK(adapter); 1150 } 1151 adapter->if_flags = ifp->if_flags; 1152 EM_CORE_UNLOCK(adapter); 1153 break; 1154 case SIOCADDMULTI: 1155 case SIOCDELMULTI: 1156 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 1157 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1158 EM_CORE_LOCK(adapter); 1159 em_disable_intr(adapter); 1160 em_set_multi(adapter); 1161 if (adapter->hw.mac.type == e1000_82542 && 1162 adapter->hw.revision_id == E1000_REVISION_2) { 1163 em_initialize_receive_unit(adapter); 1164 } 1165 #ifdef DEVICE_POLLING 1166 if (!(ifp->if_capenable & IFCAP_POLLING)) 1167 #endif 1168 em_enable_intr(adapter); 1169 EM_CORE_UNLOCK(adapter); 1170 } 1171 break; 1172 case SIOCSIFMEDIA: 1173 /* Check SOL/IDER usage */ 1174 EM_CORE_LOCK(adapter); 1175 if (e1000_check_reset_block(&adapter->hw)) { 1176 EM_CORE_UNLOCK(adapter); 1177 device_printf(adapter->dev, "Media change is" 1178 " blocked due to SOL/IDER session.\n"); 1179 break; 1180 } 1181 EM_CORE_UNLOCK(adapter); 1182 case SIOCGIFMEDIA: 1183 IOCTL_DEBUGOUT("ioctl rcv'd: \ 1184 SIOCxIFMEDIA (Get/Set Interface Media)"); 1185 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1186 break; 1187 case SIOCSIFCAP: 1188 { 1189 int mask, reinit; 1190 1191 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 1192 reinit = 0; 1193 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1194 #ifdef DEVICE_POLLING 1195 if (mask & IFCAP_POLLING) { 1196 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1197 error = ether_poll_register(em_poll, ifp); 1198 if (error) 1199 return (error); 1200 EM_CORE_LOCK(adapter); 1201 em_disable_intr(adapter); 1202 ifp->if_capenable |= IFCAP_POLLING; 1203 EM_CORE_UNLOCK(adapter); 1204 } else { 1205 error = ether_poll_deregister(ifp); 1206 /* Enable interrupt even in error case */ 1207 EM_CORE_LOCK(adapter); 1208 em_enable_intr(adapter); 1209 ifp->if_capenable &= ~IFCAP_POLLING; 1210 EM_CORE_UNLOCK(adapter); 1211 } 1212 } 1213 #endif 1214 if (mask & IFCAP_HWCSUM) { 1215 ifp->if_capenable ^= IFCAP_HWCSUM; 1216 reinit = 1; 1217 } 1218 #if __FreeBSD_version >= 700000 1219 if (mask & IFCAP_TSO4) { 1220 ifp->if_capenable ^= IFCAP_TSO4; 1221 reinit = 1; 1222 } 1223 #endif 1224 1225 if (mask & IFCAP_VLAN_HWTAGGING) { 1226 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1227 reinit = 1; 1228 } 1229 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1230 em_init(adapter); 1231 #if __FreeBSD_version >= 700000 1232 VLAN_CAPABILITIES(ifp); 1233 #endif 1234 break; 1235 } 1236 1237 #ifdef EM_TIMESYNC 1238 /* 1239 ** IOCTL support for Precision Time (IEEE 1588) Support 1240 */ 1241 case EM_TIMESYNC_READTS: 1242 { 1243 u32 rx_ctl, tx_ctl; 1244 struct em_tsync_read *tdata; 1245 1246 tdata = (struct em_tsync_read *) ifr->ifr_data; 1247 1248 IOCTL_DEBUGOUT("Reading Timestamp\n"); 1249 1250 if (tdata->read_current_time) { 1251 getnanotime(&tdata->system_time); 1252 tdata->network_time = E1000_READ_REG(&adapter->hw, E1000_SYSTIML); 1253 tdata->network_time |= 1254 (u64)E1000_READ_REG(&adapter->hw, E1000_SYSTIMH ) << 32; 1255 } 1256 1257 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 1258 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 1259 1260 IOCTL_DEBUGOUT1("RX_CTL value = %u\n", rx_ctl); 1261 IOCTL_DEBUGOUT1("TX_CTL value = %u\n", tx_ctl); 1262 1263 if (rx_ctl & 0x1) { 1264 IOCTL_DEBUGOUT("RX timestamp is valid\n"); 1265 u32 tmp; 1266 unsigned char *tmp_cp; 1267 1268 tdata->rx_valid = 1; 1269 tdata->rx_stamp = E1000_READ_REG(&adapter->hw, E1000_RXSTMPL); 1270 tdata->rx_stamp |= (u64)E1000_READ_REG(&adapter->hw, 1271 E1000_RXSTMPH) << 32; 1272 1273 tmp = E1000_READ_REG(&adapter->hw, E1000_RXSATRL); 1274 tmp_cp = (unsigned char *) &tmp; 1275 tdata->srcid[0] = tmp_cp[0]; 1276 tdata->srcid[1] = tmp_cp[1]; 1277 tdata->srcid[2] = tmp_cp[2]; 1278 tdata->srcid[3] = tmp_cp[3]; 1279 tmp = E1000_READ_REG(&adapter->hw, E1000_RXSATRH); 1280 tmp_cp = (unsigned char *) &tmp; 1281 tdata->srcid[4] = tmp_cp[0]; 1282 tdata->srcid[5] = tmp_cp[1]; 1283 tdata->seqid = tmp >> 16; 1284 tdata->seqid = htons(tdata->seqid); 1285 } else 1286 tdata->rx_valid = 0; 1287 1288 if (tx_ctl & 0x1) { 1289 IOCTL_DEBUGOUT("TX timestamp is valid\n"); 1290 tdata->tx_valid = 1; 1291 tdata->tx_stamp = E1000_READ_REG(&adapter->hw, E1000_TXSTMPL); 1292 tdata->tx_stamp |= (u64) E1000_READ_REG(&adapter->hw, 1293 E1000_TXSTMPH) << 32; 1294 } else 1295 tdata->tx_valid = 0; 1296 1297 return (0); 1298 } 1299 #endif /* EM_TIMESYNC */ 1300 1301 default: 1302 error = ether_ioctl(ifp, command, data); 1303 break; 1304 } 1305 1306 return (error); 1307 } 1308 1309 /********************************************************************* 1310 * Watchdog timer: 1311 * 1312 * This routine is called from the local timer every second. 1313 * As long as transmit descriptors are being cleaned the value 1314 * is non-zero and we do nothing. Reaching 0 indicates a tx hang 1315 * and we then reset the device. 1316 * 1317 **********************************************************************/ 1318 1319 static void 1320 em_watchdog(struct adapter *adapter) 1321 { 1322 1323 EM_CORE_LOCK_ASSERT(adapter); 1324 1325 /* 1326 ** The timer is set to 5 every time start queues a packet. 1327 ** Then txeof keeps resetting it as long as it cleans at 1328 ** least one descriptor. 1329 ** Finally, anytime all descriptors are clean the timer is 1330 ** set to 0. 1331 */ 1332 EM_TX_LOCK(adapter); 1333 if ((adapter->watchdog_timer == 0) || (--adapter->watchdog_timer)) { 1334 EM_TX_UNLOCK(adapter); 1335 return; 1336 } 1337 1338 /* If we are in this routine because of pause frames, then 1339 * don't reset the hardware. 1340 */ 1341 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1342 E1000_STATUS_TXOFF) { 1343 adapter->watchdog_timer = EM_TX_TIMEOUT; 1344 EM_TX_UNLOCK(adapter); 1345 return; 1346 } 1347 1348 if (e1000_check_for_link(&adapter->hw) == 0) 1349 device_printf(adapter->dev, "watchdog timeout -- resetting\n"); 1350 adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1351 adapter->watchdog_events++; 1352 EM_TX_UNLOCK(adapter); 1353 1354 em_init_locked(adapter); 1355 } 1356 1357 /********************************************************************* 1358 * Init entry point 1359 * 1360 * This routine is used in two ways. It is used by the stack as 1361 * init entry point in network interface structure. It is also used 1362 * by the driver as a hw/sw initialization routine to get to a 1363 * consistent state. 1364 * 1365 * return 0 on success, positive on failure 1366 **********************************************************************/ 1367 1368 static void 1369 em_init_locked(struct adapter *adapter) 1370 { 1371 struct ifnet *ifp = adapter->ifp; 1372 device_t dev = adapter->dev; 1373 u32 pba; 1374 1375 INIT_DEBUGOUT("em_init: begin"); 1376 1377 EM_CORE_LOCK_ASSERT(adapter); 1378 1379 EM_TX_LOCK(adapter); 1380 em_stop(adapter); 1381 EM_TX_UNLOCK(adapter); 1382 1383 /* 1384 * Packet Buffer Allocation (PBA) 1385 * Writing PBA sets the receive portion of the buffer 1386 * the remainder is used for the transmit buffer. 1387 * 1388 * Devices before the 82547 had a Packet Buffer of 64K. 1389 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1390 * After the 82547 the buffer was reduced to 40K. 1391 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1392 * Note: default does not leave enough room for Jumbo Frame >10k. 1393 */ 1394 switch (adapter->hw.mac.type) { 1395 case e1000_82547: 1396 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1397 if (adapter->max_frame_size > 8192) 1398 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1399 else 1400 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1401 adapter->tx_fifo_head = 0; 1402 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1403 adapter->tx_fifo_size = 1404 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1405 break; 1406 /* Total Packet Buffer on these is 48K */ 1407 case e1000_82571: 1408 case e1000_82572: 1409 case e1000_80003es2lan: 1410 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1411 break; 1412 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1413 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1414 break; 1415 case e1000_82574: 1416 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1417 break; 1418 case e1000_ich9lan: 1419 case e1000_ich10lan: 1420 #define E1000_PBA_10K 0x000A 1421 pba = E1000_PBA_10K; 1422 break; 1423 case e1000_ich8lan: 1424 pba = E1000_PBA_8K; 1425 break; 1426 default: 1427 /* Devices before 82547 had a Packet Buffer of 64K. */ 1428 if (adapter->max_frame_size > 8192) 1429 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1430 else 1431 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1432 } 1433 1434 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1435 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1436 1437 /* Get the latest mac address, User can use a LAA */ 1438 bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr, 1439 ETHER_ADDR_LEN); 1440 1441 /* Put the address into the Receive Address Array */ 1442 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1443 1444 /* 1445 * With the 82571 adapter, RAR[0] may be overwritten 1446 * when the other port is reset, we make a duplicate 1447 * in RAR[14] for that eventuality, this assures 1448 * the interface continues to function. 1449 */ 1450 if (adapter->hw.mac.type == e1000_82571) { 1451 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1452 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1453 E1000_RAR_ENTRIES - 1); 1454 } 1455 1456 /* Initialize the hardware */ 1457 if (em_hardware_init(adapter)) { 1458 device_printf(dev, "Unable to initialize the hardware\n"); 1459 return; 1460 } 1461 em_update_link_status(adapter); 1462 1463 /* Setup VLAN support, basic and offload if available */ 1464 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1465 1466 /* New register interface replaces this but 1467 waiting on kernel support to be added */ 1468 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) && 1469 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0)) { 1470 u32 ctrl; 1471 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1472 ctrl |= E1000_CTRL_VME; 1473 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1474 } 1475 1476 /* Set hardware offload abilities */ 1477 ifp->if_hwassist = 0; 1478 if (adapter->hw.mac.type >= e1000_82543) { 1479 if (ifp->if_capenable & IFCAP_TXCSUM) 1480 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1481 #if __FreeBSD_version >= 700000 1482 if (ifp->if_capenable & IFCAP_TSO4) 1483 ifp->if_hwassist |= CSUM_TSO; 1484 #endif 1485 } 1486 1487 /* Configure for OS presence */ 1488 em_init_manageability(adapter); 1489 1490 /* Prepare transmit descriptors and buffers */ 1491 em_setup_transmit_structures(adapter); 1492 em_initialize_transmit_unit(adapter); 1493 1494 /* Setup Multicast table */ 1495 em_set_multi(adapter); 1496 1497 /* Prepare receive descriptors and buffers */ 1498 if (em_setup_receive_structures(adapter)) { 1499 device_printf(dev, "Could not setup receive structures\n"); 1500 EM_TX_LOCK(adapter); 1501 em_stop(adapter); 1502 EM_TX_UNLOCK(adapter); 1503 return; 1504 } 1505 em_initialize_receive_unit(adapter); 1506 1507 /* Don't lose promiscuous settings */ 1508 em_set_promisc(adapter); 1509 1510 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1511 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1512 1513 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1514 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1515 1516 /* MSI/X configuration for 82574 */ 1517 if (adapter->hw.mac.type == e1000_82574) { 1518 int tmp; 1519 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1520 tmp |= E1000_CTRL_EXT_PBA_CLR; 1521 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1522 /* 1523 ** Set the IVAR - interrupt vector routing. 1524 ** Each nibble represents a vector, high bit 1525 ** is enable, other 3 bits are the MSIX table 1526 ** entry, we map RXQ0 to 0, TXQ0 to 1, and 1527 ** Link (other) to 2, hence the magic number. 1528 */ 1529 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1530 } 1531 1532 #ifdef DEVICE_POLLING 1533 /* 1534 * Only enable interrupts if we are not polling, make sure 1535 * they are off otherwise. 1536 */ 1537 if (ifp->if_capenable & IFCAP_POLLING) 1538 em_disable_intr(adapter); 1539 else 1540 #endif /* DEVICE_POLLING */ 1541 em_enable_intr(adapter); 1542 1543 #ifdef EM_TIMESYNC 1544 /* Initializae IEEE 1588 Precision Time hardware */ 1545 if ((adapter->hw.mac.type == e1000_82574) || 1546 (adapter->hw.mac.type == e1000_ich10lan)) 1547 em_tsync_init(adapter); 1548 #endif 1549 1550 /* Don't reset the phy next time init gets called */ 1551 adapter->hw.phy.reset_disable = TRUE; 1552 } 1553 1554 static void 1555 em_init(void *arg) 1556 { 1557 struct adapter *adapter = arg; 1558 1559 EM_CORE_LOCK(adapter); 1560 em_init_locked(adapter); 1561 EM_CORE_UNLOCK(adapter); 1562 } 1563 1564 1565 #ifdef DEVICE_POLLING 1566 /********************************************************************* 1567 * 1568 * Legacy polling routine 1569 * 1570 *********************************************************************/ 1571 static void 1572 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1573 { 1574 struct adapter *adapter = ifp->if_softc; 1575 u32 reg_icr; 1576 1577 EM_CORE_LOCK(adapter); 1578 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1579 EM_CORE_UNLOCK(adapter); 1580 return; 1581 } 1582 1583 if (cmd == POLL_AND_CHECK_STATUS) { 1584 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1585 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1586 callout_stop(&adapter->timer); 1587 adapter->hw.mac.get_link_status = 1; 1588 em_update_link_status(adapter); 1589 callout_reset(&adapter->timer, hz, 1590 em_local_timer, adapter); 1591 } 1592 } 1593 EM_CORE_UNLOCK(adapter); 1594 1595 em_rxeof(adapter, count); 1596 1597 EM_TX_LOCK(adapter); 1598 em_txeof(adapter); 1599 1600 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1601 em_start_locked(ifp); 1602 EM_TX_UNLOCK(adapter); 1603 } 1604 #endif /* DEVICE_POLLING */ 1605 1606 #ifdef EM_LEGACY_IRQ 1607 /********************************************************************* 1608 * 1609 * Legacy Interrupt Service routine 1610 * 1611 *********************************************************************/ 1612 1613 static void 1614 em_intr(void *arg) 1615 { 1616 struct adapter *adapter = arg; 1617 struct ifnet *ifp = adapter->ifp; 1618 u32 reg_icr; 1619 1620 1621 if (ifp->if_capenable & IFCAP_POLLING) 1622 return; 1623 1624 EM_CORE_LOCK(adapter); 1625 for (;;) { 1626 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1627 1628 if (adapter->hw.mac.type >= e1000_82571 && 1629 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1630 break; 1631 else if (reg_icr == 0) 1632 break; 1633 1634 /* 1635 * XXX: some laptops trigger several spurious interrupts 1636 * on em(4) when in the resume cycle. The ICR register 1637 * reports all-ones value in this case. Processing such 1638 * interrupts would lead to a freeze. I don't know why. 1639 */ 1640 if (reg_icr == 0xffffffff) 1641 break; 1642 1643 EM_CORE_UNLOCK(adapter); 1644 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1645 em_rxeof(adapter, -1); 1646 EM_TX_LOCK(adapter); 1647 em_txeof(adapter); 1648 EM_TX_UNLOCK(adapter); 1649 } 1650 EM_CORE_LOCK(adapter); 1651 1652 /* Link status change */ 1653 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1654 callout_stop(&adapter->timer); 1655 adapter->hw.mac.get_link_status = 1; 1656 em_update_link_status(adapter); 1657 /* Deal with TX cruft when link lost */ 1658 em_tx_purge(adapter); 1659 callout_reset(&adapter->timer, hz, 1660 em_local_timer, adapter); 1661 } 1662 1663 if (reg_icr & E1000_ICR_RXO) 1664 adapter->rx_overruns++; 1665 } 1666 EM_CORE_UNLOCK(adapter); 1667 1668 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1669 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1670 em_start(ifp); 1671 } 1672 1673 #else /* EM_FAST_IRQ, then fast interrupt routines only */ 1674 1675 static void 1676 em_handle_link(void *context, int pending) 1677 { 1678 struct adapter *adapter = context; 1679 struct ifnet *ifp = adapter->ifp; 1680 1681 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1682 return; 1683 1684 EM_CORE_LOCK(adapter); 1685 callout_stop(&adapter->timer); 1686 em_update_link_status(adapter); 1687 /* Deal with TX cruft when link lost */ 1688 em_tx_purge(adapter); 1689 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1690 EM_CORE_UNLOCK(adapter); 1691 } 1692 1693 1694 /* Combined RX/TX handler, used by Legacy and MSI */ 1695 static void 1696 em_handle_rxtx(void *context, int pending) 1697 { 1698 struct adapter *adapter = context; 1699 struct ifnet *ifp = adapter->ifp; 1700 1701 1702 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1703 if (em_rxeof(adapter, adapter->rx_process_limit) != 0) 1704 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1705 EM_TX_LOCK(adapter); 1706 em_txeof(adapter); 1707 1708 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1709 em_start_locked(ifp); 1710 EM_TX_UNLOCK(adapter); 1711 } 1712 1713 em_enable_intr(adapter); 1714 } 1715 1716 static void 1717 em_handle_rx(void *context, int pending) 1718 { 1719 struct adapter *adapter = context; 1720 struct ifnet *ifp = adapter->ifp; 1721 1722 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1723 (em_rxeof(adapter, adapter->rx_process_limit) != 0)) 1724 taskqueue_enqueue(adapter->tq, &adapter->rx_task); 1725 1726 } 1727 1728 static void 1729 em_handle_tx(void *context, int pending) 1730 { 1731 struct adapter *adapter = context; 1732 struct ifnet *ifp = adapter->ifp; 1733 1734 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1735 EM_TX_LOCK(adapter); 1736 em_txeof(adapter); 1737 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1738 em_start_locked(ifp); 1739 EM_TX_UNLOCK(adapter); 1740 } 1741 } 1742 1743 /********************************************************************* 1744 * 1745 * Fast Legacy/MSI Combined Interrupt Service routine 1746 * 1747 *********************************************************************/ 1748 #if __FreeBSD_version < 700000 1749 #define FILTER_STRAY 1750 #define FILTER_HANDLED 1751 static void 1752 #else 1753 static int 1754 #endif 1755 em_irq_fast(void *arg) 1756 { 1757 struct adapter *adapter = arg; 1758 struct ifnet *ifp; 1759 u32 reg_icr; 1760 1761 ifp = adapter->ifp; 1762 1763 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1764 1765 /* Hot eject? */ 1766 if (reg_icr == 0xffffffff) 1767 return FILTER_STRAY; 1768 1769 /* Definitely not our interrupt. */ 1770 if (reg_icr == 0x0) 1771 return FILTER_STRAY; 1772 1773 /* 1774 * Starting with the 82571 chip, bit 31 should be used to 1775 * determine whether the interrupt belongs to us. 1776 */ 1777 if (adapter->hw.mac.type >= e1000_82571 && 1778 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1779 return FILTER_STRAY; 1780 1781 /* 1782 * Mask interrupts until the taskqueue is finished running. This is 1783 * cheap, just assume that it is needed. This also works around the 1784 * MSI message reordering errata on certain systems. 1785 */ 1786 em_disable_intr(adapter); 1787 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1788 1789 /* Link status change */ 1790 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1791 adapter->hw.mac.get_link_status = 1; 1792 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1793 } 1794 1795 if (reg_icr & E1000_ICR_RXO) 1796 adapter->rx_overruns++; 1797 return FILTER_HANDLED; 1798 } 1799 1800 /********************************************************************* 1801 * 1802 * MSIX Interrupt Service Routines 1803 * 1804 **********************************************************************/ 1805 #define EM_MSIX_TX 0x00040000 1806 #define EM_MSIX_RX 0x00010000 1807 #define EM_MSIX_LINK 0x00100000 1808 1809 static void 1810 em_msix_tx(void *arg) 1811 { 1812 struct adapter *adapter = arg; 1813 struct ifnet *ifp = adapter->ifp; 1814 1815 ++adapter->tx_irq; 1816 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1817 EM_TX_LOCK(adapter); 1818 em_txeof(adapter); 1819 EM_TX_UNLOCK(adapter); 1820 taskqueue_enqueue(adapter->tq, &adapter->tx_task); 1821 } 1822 /* Reenable this interrupt */ 1823 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_TX); 1824 return; 1825 } 1826 1827 /********************************************************************* 1828 * 1829 * MSIX RX Interrupt Service routine 1830 * 1831 **********************************************************************/ 1832 1833 static void 1834 em_msix_rx(void *arg) 1835 { 1836 struct adapter *adapter = arg; 1837 struct ifnet *ifp = adapter->ifp; 1838 1839 ++adapter->rx_irq; 1840 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1841 (em_rxeof(adapter, adapter->rx_process_limit) != 0)) 1842 taskqueue_enqueue(adapter->tq, &adapter->rx_task); 1843 /* Reenable this interrupt */ 1844 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_RX); 1845 return; 1846 } 1847 1848 /********************************************************************* 1849 * 1850 * MSIX Link Fast Interrupt Service routine 1851 * 1852 **********************************************************************/ 1853 1854 static void 1855 em_msix_link(void *arg) 1856 { 1857 struct adapter *adapter = arg; 1858 u32 reg_icr; 1859 1860 ++adapter->link_irq; 1861 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1862 1863 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1864 adapter->hw.mac.get_link_status = 1; 1865 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1866 } 1867 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1868 EM_MSIX_LINK | E1000_IMS_LSC); 1869 return; 1870 } 1871 #endif /* EM_FAST_IRQ */ 1872 1873 /********************************************************************* 1874 * 1875 * Media Ioctl callback 1876 * 1877 * This routine is called whenever the user queries the status of 1878 * the interface using ifconfig. 1879 * 1880 **********************************************************************/ 1881 static void 1882 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1883 { 1884 struct adapter *adapter = ifp->if_softc; 1885 u_char fiber_type = IFM_1000_SX; 1886 1887 INIT_DEBUGOUT("em_media_status: begin"); 1888 1889 EM_CORE_LOCK(adapter); 1890 em_update_link_status(adapter); 1891 1892 ifmr->ifm_status = IFM_AVALID; 1893 ifmr->ifm_active = IFM_ETHER; 1894 1895 if (!adapter->link_active) { 1896 EM_CORE_UNLOCK(adapter); 1897 return; 1898 } 1899 1900 ifmr->ifm_status |= IFM_ACTIVE; 1901 1902 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1903 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1904 if (adapter->hw.mac.type == e1000_82545) 1905 fiber_type = IFM_1000_LX; 1906 ifmr->ifm_active |= fiber_type | IFM_FDX; 1907 } else { 1908 switch (adapter->link_speed) { 1909 case 10: 1910 ifmr->ifm_active |= IFM_10_T; 1911 break; 1912 case 100: 1913 ifmr->ifm_active |= IFM_100_TX; 1914 break; 1915 case 1000: 1916 ifmr->ifm_active |= IFM_1000_T; 1917 break; 1918 } 1919 if (adapter->link_duplex == FULL_DUPLEX) 1920 ifmr->ifm_active |= IFM_FDX; 1921 else 1922 ifmr->ifm_active |= IFM_HDX; 1923 } 1924 EM_CORE_UNLOCK(adapter); 1925 } 1926 1927 /********************************************************************* 1928 * 1929 * Media Ioctl callback 1930 * 1931 * This routine is called when the user changes speed/duplex using 1932 * media/mediopt option with ifconfig. 1933 * 1934 **********************************************************************/ 1935 static int 1936 em_media_change(struct ifnet *ifp) 1937 { 1938 struct adapter *adapter = ifp->if_softc; 1939 struct ifmedia *ifm = &adapter->media; 1940 1941 INIT_DEBUGOUT("em_media_change: begin"); 1942 1943 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1944 return (EINVAL); 1945 1946 EM_CORE_LOCK(adapter); 1947 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1948 case IFM_AUTO: 1949 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1950 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1951 break; 1952 case IFM_1000_LX: 1953 case IFM_1000_SX: 1954 case IFM_1000_T: 1955 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1956 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1957 break; 1958 case IFM_100_TX: 1959 adapter->hw.mac.autoneg = FALSE; 1960 adapter->hw.phy.autoneg_advertised = 0; 1961 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1962 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1963 else 1964 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1965 break; 1966 case IFM_10_T: 1967 adapter->hw.mac.autoneg = FALSE; 1968 adapter->hw.phy.autoneg_advertised = 0; 1969 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1970 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1971 else 1972 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1973 break; 1974 default: 1975 device_printf(adapter->dev, "Unsupported media type\n"); 1976 } 1977 1978 /* As the speed/duplex settings my have changed we need to 1979 * reset the PHY. 1980 */ 1981 adapter->hw.phy.reset_disable = FALSE; 1982 1983 em_init_locked(adapter); 1984 EM_CORE_UNLOCK(adapter); 1985 1986 return (0); 1987 } 1988 1989 /********************************************************************* 1990 * 1991 * This routine maps the mbufs to tx descriptors. 1992 * 1993 * return 0 on success, positive on failure 1994 **********************************************************************/ 1995 1996 static int 1997 em_xmit(struct adapter *adapter, struct mbuf **m_headp) 1998 { 1999 bus_dma_segment_t segs[EM_MAX_SCATTER]; 2000 bus_dmamap_t map; 2001 struct em_buffer *tx_buffer, *tx_buffer_mapped; 2002 struct e1000_tx_desc *ctxd = NULL; 2003 struct mbuf *m_head; 2004 u32 txd_upper, txd_lower, txd_used, txd_saved; 2005 int nsegs, i, j, first, last = 0; 2006 int error, do_tso, tso_desc = 0; 2007 #if __FreeBSD_version < 700000 2008 struct m_tag *mtag; 2009 #endif 2010 m_head = *m_headp; 2011 txd_upper = txd_lower = txd_used = txd_saved = 0; 2012 2013 #if __FreeBSD_version >= 700000 2014 do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); 2015 #else 2016 do_tso = 0; 2017 #endif 2018 2019 /* 2020 * Force a cleanup if number of TX descriptors 2021 * available hits the threshold 2022 */ 2023 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 2024 em_txeof(adapter); 2025 /* Now do we at least have a minimal? */ 2026 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 2027 adapter->no_tx_desc_avail1++; 2028 return (ENOBUFS); 2029 } 2030 } 2031 2032 2033 /* 2034 * TSO workaround: 2035 * If an mbuf is only header we need 2036 * to pull 4 bytes of data into it. 2037 */ 2038 if (do_tso && (m_head->m_len <= M_TSO_LEN)) { 2039 m_head = m_pullup(m_head, M_TSO_LEN + 4); 2040 *m_headp = m_head; 2041 if (m_head == NULL) 2042 return (ENOBUFS); 2043 } 2044 2045 /* 2046 * Map the packet for DMA 2047 * 2048 * Capture the first descriptor index, 2049 * this descriptor will have the index 2050 * of the EOP which is the only one that 2051 * now gets a DONE bit writeback. 2052 */ 2053 first = adapter->next_avail_tx_desc; 2054 tx_buffer = &adapter->tx_buffer_area[first]; 2055 tx_buffer_mapped = tx_buffer; 2056 map = tx_buffer->map; 2057 2058 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2059 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2060 2061 /* 2062 * There are two types of errors we can (try) to handle: 2063 * - EFBIG means the mbuf chain was too long and bus_dma ran 2064 * out of segments. Defragment the mbuf chain and try again. 2065 * - ENOMEM means bus_dma could not obtain enough bounce buffers 2066 * at this point in time. Defer sending and try again later. 2067 * All other errors, in particular EINVAL, are fatal and prevent the 2068 * mbuf chain from ever going through. Drop it and report error. 2069 */ 2070 if (error == EFBIG) { 2071 struct mbuf *m; 2072 2073 m = m_defrag(*m_headp, M_DONTWAIT); 2074 if (m == NULL) { 2075 adapter->mbuf_alloc_failed++; 2076 m_freem(*m_headp); 2077 *m_headp = NULL; 2078 return (ENOBUFS); 2079 } 2080 *m_headp = m; 2081 2082 /* Try it again */ 2083 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2084 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2085 2086 if (error == ENOMEM) { 2087 adapter->no_tx_dma_setup++; 2088 return (error); 2089 } else if (error != 0) { 2090 adapter->no_tx_dma_setup++; 2091 m_freem(*m_headp); 2092 *m_headp = NULL; 2093 return (error); 2094 } 2095 } else if (error == ENOMEM) { 2096 adapter->no_tx_dma_setup++; 2097 return (error); 2098 } else if (error != 0) { 2099 adapter->no_tx_dma_setup++; 2100 m_freem(*m_headp); 2101 *m_headp = NULL; 2102 return (error); 2103 } 2104 2105 /* 2106 * TSO Hardware workaround, if this packet is not 2107 * TSO, and is only a single descriptor long, and 2108 * it follows a TSO burst, then we need to add a 2109 * sentinel descriptor to prevent premature writeback. 2110 */ 2111 if ((do_tso == 0) && (adapter->tx_tso == TRUE)) { 2112 if (nsegs == 1) 2113 tso_desc = TRUE; 2114 adapter->tx_tso = FALSE; 2115 } 2116 2117 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 2118 adapter->no_tx_desc_avail2++; 2119 bus_dmamap_unload(adapter->txtag, map); 2120 return (ENOBUFS); 2121 } 2122 m_head = *m_headp; 2123 2124 /* Do hardware assists */ 2125 #if __FreeBSD_version >= 700000 2126 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 2127 error = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 2128 if (error != TRUE) 2129 return (ENXIO); /* something foobar */ 2130 /* we need to make a final sentinel transmit desc */ 2131 tso_desc = TRUE; 2132 } else 2133 #endif 2134 #ifndef EM_TIMESYNC 2135 /* 2136 ** Timesync needs to check the packet header 2137 ** so call checksum code to do so, but don't 2138 ** penalize the code if not defined. 2139 */ 2140 if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) 2141 #endif 2142 em_transmit_checksum_setup(adapter, m_head, 2143 &txd_upper, &txd_lower); 2144 2145 i = adapter->next_avail_tx_desc; 2146 if (adapter->pcix_82544) 2147 txd_saved = i; 2148 2149 /* Set up our transmit descriptors */ 2150 for (j = 0; j < nsegs; j++) { 2151 bus_size_t seg_len; 2152 bus_addr_t seg_addr; 2153 /* If adapter is 82544 and on PCIX bus */ 2154 if(adapter->pcix_82544) { 2155 DESC_ARRAY desc_array; 2156 u32 array_elements, counter; 2157 /* 2158 * Check the Address and Length combination and 2159 * split the data accordingly 2160 */ 2161 array_elements = em_fill_descriptors(segs[j].ds_addr, 2162 segs[j].ds_len, &desc_array); 2163 for (counter = 0; counter < array_elements; counter++) { 2164 if (txd_used == adapter->num_tx_desc_avail) { 2165 adapter->next_avail_tx_desc = txd_saved; 2166 adapter->no_tx_desc_avail2++; 2167 bus_dmamap_unload(adapter->txtag, map); 2168 return (ENOBUFS); 2169 } 2170 tx_buffer = &adapter->tx_buffer_area[i]; 2171 ctxd = &adapter->tx_desc_base[i]; 2172 ctxd->buffer_addr = htole64( 2173 desc_array.descriptor[counter].address); 2174 ctxd->lower.data = htole32( 2175 (adapter->txd_cmd | txd_lower | (u16) 2176 desc_array.descriptor[counter].length)); 2177 ctxd->upper.data = 2178 htole32((txd_upper)); 2179 last = i; 2180 if (++i == adapter->num_tx_desc) 2181 i = 0; 2182 tx_buffer->m_head = NULL; 2183 tx_buffer->next_eop = -1; 2184 txd_used++; 2185 } 2186 } else { 2187 tx_buffer = &adapter->tx_buffer_area[i]; 2188 ctxd = &adapter->tx_desc_base[i]; 2189 seg_addr = segs[j].ds_addr; 2190 seg_len = segs[j].ds_len; 2191 /* 2192 ** TSO Workaround: 2193 ** If this is the last descriptor, we want to 2194 ** split it so we have a small final sentinel 2195 */ 2196 if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { 2197 seg_len -= 4; 2198 ctxd->buffer_addr = htole64(seg_addr); 2199 ctxd->lower.data = htole32( 2200 adapter->txd_cmd | txd_lower | seg_len); 2201 ctxd->upper.data = 2202 htole32(txd_upper); 2203 if (++i == adapter->num_tx_desc) 2204 i = 0; 2205 /* Now make the sentinel */ 2206 ++txd_used; /* using an extra txd */ 2207 ctxd = &adapter->tx_desc_base[i]; 2208 tx_buffer = &adapter->tx_buffer_area[i]; 2209 ctxd->buffer_addr = 2210 htole64(seg_addr + seg_len); 2211 ctxd->lower.data = htole32( 2212 adapter->txd_cmd | txd_lower | 4); 2213 ctxd->upper.data = 2214 htole32(txd_upper); 2215 last = i; 2216 if (++i == adapter->num_tx_desc) 2217 i = 0; 2218 } else { 2219 ctxd->buffer_addr = htole64(seg_addr); 2220 ctxd->lower.data = htole32( 2221 adapter->txd_cmd | txd_lower | seg_len); 2222 ctxd->upper.data = 2223 htole32(txd_upper); 2224 last = i; 2225 if (++i == adapter->num_tx_desc) 2226 i = 0; 2227 } 2228 tx_buffer->m_head = NULL; 2229 tx_buffer->next_eop = -1; 2230 } 2231 } 2232 2233 adapter->next_avail_tx_desc = i; 2234 if (adapter->pcix_82544) 2235 adapter->num_tx_desc_avail -= txd_used; 2236 else { 2237 adapter->num_tx_desc_avail -= nsegs; 2238 if (tso_desc) /* TSO used an extra for sentinel */ 2239 adapter->num_tx_desc_avail -= txd_used; 2240 } 2241 2242 /* 2243 ** Handle VLAN tag, this is the 2244 ** biggest difference between 2245 ** 6.x and 7 2246 */ 2247 #if __FreeBSD_version < 700000 2248 /* Find out if we are in vlan mode. */ 2249 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 2250 if (mtag != NULL) { 2251 ctxd->upper.fields.special = 2252 htole16(VLAN_TAG_VALUE(mtag)); 2253 #else /* FreeBSD 7 */ 2254 if (m_head->m_flags & M_VLANTAG) { 2255 /* Set the vlan id. */ 2256 ctxd->upper.fields.special = 2257 htole16(m_head->m_pkthdr.ether_vtag); 2258 #endif 2259 /* Tell hardware to add tag */ 2260 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 2261 } 2262 2263 tx_buffer->m_head = m_head; 2264 tx_buffer_mapped->map = tx_buffer->map; 2265 tx_buffer->map = map; 2266 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 2267 2268 /* 2269 * Last Descriptor of Packet 2270 * needs End Of Packet (EOP) 2271 * and Report Status (RS) 2272 */ 2273 ctxd->lower.data |= 2274 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 2275 /* 2276 * Keep track in the first buffer which 2277 * descriptor will be written back 2278 */ 2279 tx_buffer = &adapter->tx_buffer_area[first]; 2280 tx_buffer->next_eop = last; 2281 2282 /* 2283 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 2284 * that this frame is available to transmit. 2285 */ 2286 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2287 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2288 if (adapter->hw.mac.type == e1000_82547 && 2289 adapter->link_duplex == HALF_DUPLEX) 2290 em_82547_move_tail(adapter); 2291 else { 2292 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 2293 if (adapter->hw.mac.type == e1000_82547) 2294 em_82547_update_fifo_head(adapter, 2295 m_head->m_pkthdr.len); 2296 } 2297 2298 #ifdef EM_TIMESYNC 2299 if (ctxd->upper.data & E1000_TXD_EXTCMD_TSTAMP) { 2300 HW_DEBUGOUT( "@@@ Timestamp bit is set in transmit descriptor\n" ); 2301 } 2302 #endif 2303 return (0); 2304 } 2305 2306 /********************************************************************* 2307 * 2308 * 82547 workaround to avoid controller hang in half-duplex environment. 2309 * The workaround is to avoid queuing a large packet that would span 2310 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 2311 * in this case. We do that only when FIFO is quiescent. 2312 * 2313 **********************************************************************/ 2314 static void 2315 em_82547_move_tail(void *arg) 2316 { 2317 struct adapter *adapter = arg; 2318 struct e1000_tx_desc *tx_desc; 2319 u16 hw_tdt, sw_tdt, length = 0; 2320 bool eop = 0; 2321 2322 EM_TX_LOCK_ASSERT(adapter); 2323 2324 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 2325 sw_tdt = adapter->next_avail_tx_desc; 2326 2327 while (hw_tdt != sw_tdt) { 2328 tx_desc = &adapter->tx_desc_base[hw_tdt]; 2329 length += tx_desc->lower.flags.length; 2330 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 2331 if (++hw_tdt == adapter->num_tx_desc) 2332 hw_tdt = 0; 2333 2334 if (eop) { 2335 if (em_82547_fifo_workaround(adapter, length)) { 2336 adapter->tx_fifo_wrk_cnt++; 2337 callout_reset(&adapter->tx_fifo_timer, 1, 2338 em_82547_move_tail, adapter); 2339 break; 2340 } 2341 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 2342 em_82547_update_fifo_head(adapter, length); 2343 length = 0; 2344 } 2345 } 2346 } 2347 2348 static int 2349 em_82547_fifo_workaround(struct adapter *adapter, int len) 2350 { 2351 int fifo_space, fifo_pkt_len; 2352 2353 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2354 2355 if (adapter->link_duplex == HALF_DUPLEX) { 2356 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 2357 2358 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 2359 if (em_82547_tx_fifo_reset(adapter)) 2360 return (0); 2361 else 2362 return (1); 2363 } 2364 } 2365 2366 return (0); 2367 } 2368 2369 static void 2370 em_82547_update_fifo_head(struct adapter *adapter, int len) 2371 { 2372 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2373 2374 /* tx_fifo_head is always 16 byte aligned */ 2375 adapter->tx_fifo_head += fifo_pkt_len; 2376 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { 2377 adapter->tx_fifo_head -= adapter->tx_fifo_size; 2378 } 2379 } 2380 2381 2382 static int 2383 em_82547_tx_fifo_reset(struct adapter *adapter) 2384 { 2385 u32 tctl; 2386 2387 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 2388 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 2389 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 2390 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 2391 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 2392 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 2393 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 2394 /* Disable TX unit */ 2395 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2396 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 2397 tctl & ~E1000_TCTL_EN); 2398 2399 /* Reset FIFO pointers */ 2400 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 2401 adapter->tx_head_addr); 2402 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 2403 adapter->tx_head_addr); 2404 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 2405 adapter->tx_head_addr); 2406 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 2407 adapter->tx_head_addr); 2408 2409 /* Re-enable TX unit */ 2410 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2411 E1000_WRITE_FLUSH(&adapter->hw); 2412 2413 adapter->tx_fifo_head = 0; 2414 adapter->tx_fifo_reset_cnt++; 2415 2416 return (TRUE); 2417 } 2418 else { 2419 return (FALSE); 2420 } 2421 } 2422 2423 static void 2424 em_set_promisc(struct adapter *adapter) 2425 { 2426 struct ifnet *ifp = adapter->ifp; 2427 u32 reg_rctl; 2428 2429 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2430 2431 if (ifp->if_flags & IFF_PROMISC) { 2432 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2433 /* Turn this on if you want to see bad packets */ 2434 if (em_debug_sbp) 2435 reg_rctl |= E1000_RCTL_SBP; 2436 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2437 } else if (ifp->if_flags & IFF_ALLMULTI) { 2438 reg_rctl |= E1000_RCTL_MPE; 2439 reg_rctl &= ~E1000_RCTL_UPE; 2440 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2441 } 2442 } 2443 2444 static void 2445 em_disable_promisc(struct adapter *adapter) 2446 { 2447 u32 reg_rctl; 2448 2449 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2450 2451 reg_rctl &= (~E1000_RCTL_UPE); 2452 reg_rctl &= (~E1000_RCTL_MPE); 2453 reg_rctl &= (~E1000_RCTL_SBP); 2454 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2455 } 2456 2457 2458 /********************************************************************* 2459 * Multicast Update 2460 * 2461 * This routine is called whenever multicast address list is updated. 2462 * 2463 **********************************************************************/ 2464 2465 static void 2466 em_set_multi(struct adapter *adapter) 2467 { 2468 struct ifnet *ifp = adapter->ifp; 2469 struct ifmultiaddr *ifma; 2470 u32 reg_rctl = 0; 2471 u8 mta[512]; /* Largest MTS is 4096 bits */ 2472 int mcnt = 0; 2473 2474 IOCTL_DEBUGOUT("em_set_multi: begin"); 2475 2476 if (adapter->hw.mac.type == e1000_82542 && 2477 adapter->hw.revision_id == E1000_REVISION_2) { 2478 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2479 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2480 e1000_pci_clear_mwi(&adapter->hw); 2481 reg_rctl |= E1000_RCTL_RST; 2482 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2483 msec_delay(5); 2484 } 2485 2486 IF_ADDR_LOCK(ifp); 2487 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2488 if (ifma->ifma_addr->sa_family != AF_LINK) 2489 continue; 2490 2491 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2492 break; 2493 2494 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2495 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN); 2496 mcnt++; 2497 } 2498 IF_ADDR_UNLOCK(ifp); 2499 2500 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2501 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2502 reg_rctl |= E1000_RCTL_MPE; 2503 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2504 } else 2505 e1000_update_mc_addr_list(&adapter->hw, mta, 2506 mcnt, 1, adapter->hw.mac.rar_entry_count); 2507 2508 if (adapter->hw.mac.type == e1000_82542 && 2509 adapter->hw.revision_id == E1000_REVISION_2) { 2510 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2511 reg_rctl &= ~E1000_RCTL_RST; 2512 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2513 msec_delay(5); 2514 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2515 e1000_pci_set_mwi(&adapter->hw); 2516 } 2517 } 2518 2519 2520 /********************************************************************* 2521 * Timer routine 2522 * 2523 * This routine checks for link status and updates statistics. 2524 * 2525 **********************************************************************/ 2526 2527 static void 2528 em_local_timer(void *arg) 2529 { 2530 struct adapter *adapter = arg; 2531 struct ifnet *ifp = adapter->ifp; 2532 2533 EM_CORE_LOCK_ASSERT(adapter); 2534 2535 em_update_link_status(adapter); 2536 em_update_stats_counters(adapter); 2537 2538 /* Reset LAA into RAR[0] on 82571 */ 2539 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2540 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2541 2542 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 2543 em_print_hw_stats(adapter); 2544 2545 em_smartspeed(adapter); 2546 2547 /* 2548 * Each second we check the watchdog to 2549 * protect against hardware hangs. 2550 */ 2551 em_watchdog(adapter); 2552 2553 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 2554 2555 } 2556 2557 static void 2558 em_update_link_status(struct adapter *adapter) 2559 { 2560 struct e1000_hw *hw = &adapter->hw; 2561 struct ifnet *ifp = adapter->ifp; 2562 device_t dev = adapter->dev; 2563 u32 link_check = 0; 2564 2565 /* Get the cached link value or read phy for real */ 2566 switch (hw->phy.media_type) { 2567 case e1000_media_type_copper: 2568 if (hw->mac.get_link_status) { 2569 /* Do the work to read phy */ 2570 e1000_check_for_link(hw); 2571 link_check = !hw->mac.get_link_status; 2572 if (link_check) /* ESB2 fix */ 2573 e1000_cfg_on_link_up(hw); 2574 } else 2575 link_check = TRUE; 2576 break; 2577 case e1000_media_type_fiber: 2578 e1000_check_for_link(hw); 2579 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 2580 E1000_STATUS_LU); 2581 break; 2582 case e1000_media_type_internal_serdes: 2583 e1000_check_for_link(hw); 2584 link_check = adapter->hw.mac.serdes_has_link; 2585 break; 2586 default: 2587 case e1000_media_type_unknown: 2588 break; 2589 } 2590 2591 /* Now check for a transition */ 2592 if (link_check && (adapter->link_active == 0)) { 2593 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2594 &adapter->link_duplex); 2595 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2596 if ((adapter->link_speed != SPEED_1000) && 2597 ((hw->mac.type == e1000_82571) || 2598 (hw->mac.type == e1000_82572))) { 2599 int tarc0; 2600 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2601 tarc0 &= ~SPEED_MODE_BIT; 2602 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2603 } 2604 if (bootverbose) 2605 device_printf(dev, "Link is up %d Mbps %s\n", 2606 adapter->link_speed, 2607 ((adapter->link_duplex == FULL_DUPLEX) ? 2608 "Full Duplex" : "Half Duplex")); 2609 adapter->link_active = 1; 2610 adapter->smartspeed = 0; 2611 ifp->if_baudrate = adapter->link_speed * 1000000; 2612 if_link_state_change(ifp, LINK_STATE_UP); 2613 } else if (!link_check && (adapter->link_active == 1)) { 2614 ifp->if_baudrate = adapter->link_speed = 0; 2615 adapter->link_duplex = 0; 2616 if (bootverbose) 2617 device_printf(dev, "Link is Down\n"); 2618 adapter->link_active = 0; 2619 /* Link down, disable watchdog */ 2620 adapter->watchdog_timer = FALSE; 2621 if_link_state_change(ifp, LINK_STATE_DOWN); 2622 } 2623 } 2624 2625 /********************************************************************* 2626 * 2627 * This routine disables all traffic on the adapter by issuing a 2628 * global reset on the MAC and deallocates TX/RX buffers. 2629 * 2630 * This routine should always be called with BOTH the CORE 2631 * and TX locks. 2632 **********************************************************************/ 2633 2634 static void 2635 em_stop(void *arg) 2636 { 2637 struct adapter *adapter = arg; 2638 struct ifnet *ifp = adapter->ifp; 2639 2640 EM_CORE_LOCK_ASSERT(adapter); 2641 EM_TX_LOCK_ASSERT(adapter); 2642 2643 INIT_DEBUGOUT("em_stop: begin"); 2644 2645 em_disable_intr(adapter); 2646 callout_stop(&adapter->timer); 2647 callout_stop(&adapter->tx_fifo_timer); 2648 2649 /* Tell the stack that the interface is no longer active */ 2650 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2651 2652 #ifdef EM_TIMESYNC 2653 /* Disable IEEE 1588 Time hardware */ 2654 if ((adapter->hw.mac.type == e1000_82574) || 2655 (adapter->hw.mac.type == e1000_ich10lan)) 2656 em_tsync_disable(adapter); 2657 #endif 2658 2659 e1000_reset_hw(&adapter->hw); 2660 if (adapter->hw.mac.type >= e1000_82544) 2661 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2662 } 2663 2664 2665 /********************************************************************* 2666 * 2667 * Determine hardware revision. 2668 * 2669 **********************************************************************/ 2670 static void 2671 em_identify_hardware(struct adapter *adapter) 2672 { 2673 device_t dev = adapter->dev; 2674 2675 /* Make sure our PCI config space has the necessary stuff set */ 2676 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2677 if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && 2678 (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) { 2679 device_printf(dev, "Memory Access and/or Bus Master bits " 2680 "were not set!\n"); 2681 adapter->hw.bus.pci_cmd_word |= 2682 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 2683 pci_write_config(dev, PCIR_COMMAND, 2684 adapter->hw.bus.pci_cmd_word, 2); 2685 } 2686 2687 /* Save off the information about this board */ 2688 adapter->hw.vendor_id = pci_get_vendor(dev); 2689 adapter->hw.device_id = pci_get_device(dev); 2690 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2691 adapter->hw.subsystem_vendor_id = 2692 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2693 adapter->hw.subsystem_device_id = 2694 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2695 2696 /* Do Shared Code Init and Setup */ 2697 if (e1000_set_mac_type(&adapter->hw)) { 2698 device_printf(dev, "Setup init failure\n"); 2699 return; 2700 } 2701 } 2702 2703 static int 2704 em_allocate_pci_resources(struct adapter *adapter) 2705 { 2706 device_t dev = adapter->dev; 2707 int val, rid, error = E1000_SUCCESS; 2708 2709 rid = PCIR_BAR(0); 2710 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2711 &rid, RF_ACTIVE); 2712 if (adapter->memory == NULL) { 2713 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2714 return (ENXIO); 2715 } 2716 adapter->osdep.mem_bus_space_tag = 2717 rman_get_bustag(adapter->memory); 2718 adapter->osdep.mem_bus_space_handle = 2719 rman_get_bushandle(adapter->memory); 2720 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 2721 2722 /* Only older adapters use IO mapping */ 2723 if ((adapter->hw.mac.type > e1000_82543) && 2724 (adapter->hw.mac.type < e1000_82571)) { 2725 /* Figure our where our IO BAR is ? */ 2726 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2727 val = pci_read_config(dev, rid, 4); 2728 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2729 adapter->io_rid = rid; 2730 break; 2731 } 2732 rid += 4; 2733 /* check for 64bit BAR */ 2734 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2735 rid += 4; 2736 } 2737 if (rid >= PCIR_CIS) { 2738 device_printf(dev, "Unable to locate IO BAR\n"); 2739 return (ENXIO); 2740 } 2741 adapter->ioport = bus_alloc_resource_any(dev, 2742 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 2743 if (adapter->ioport == NULL) { 2744 device_printf(dev, "Unable to allocate bus resource: " 2745 "ioport\n"); 2746 return (ENXIO); 2747 } 2748 adapter->hw.io_base = 0; 2749 adapter->osdep.io_bus_space_tag = 2750 rman_get_bustag(adapter->ioport); 2751 adapter->osdep.io_bus_space_handle = 2752 rman_get_bushandle(adapter->ioport); 2753 } 2754 2755 /* 2756 ** Init the resource arrays 2757 ** used by MSIX setup 2758 */ 2759 for (int i = 0; i < 3; i++) { 2760 adapter->rid[i] = i + 1; /* MSI/X RID starts at 1 */ 2761 adapter->tag[i] = NULL; 2762 adapter->res[i] = NULL; 2763 } 2764 2765 /* 2766 * Setup MSI/X or MSI if PCI Express 2767 */ 2768 if (em_enable_msi) 2769 adapter->msi = em_setup_msix(adapter); 2770 2771 adapter->hw.back = &adapter->osdep; 2772 2773 return (error); 2774 } 2775 2776 /********************************************************************* 2777 * 2778 * Setup the Legacy or MSI Interrupt handler 2779 * 2780 **********************************************************************/ 2781 int 2782 em_allocate_legacy(struct adapter *adapter) 2783 { 2784 device_t dev = adapter->dev; 2785 int error; 2786 2787 /* Manually turn off all interrupts */ 2788 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2789 2790 /* Legacy RID is 0 */ 2791 if (adapter->msi == 0) 2792 adapter->rid[0] = 0; 2793 2794 /* We allocate a single interrupt resource */ 2795 adapter->res[0] = bus_alloc_resource_any(dev, 2796 SYS_RES_IRQ, &adapter->rid[0], RF_SHAREABLE | RF_ACTIVE); 2797 if (adapter->res[0] == NULL) { 2798 device_printf(dev, "Unable to allocate bus resource: " 2799 "interrupt\n"); 2800 return (ENXIO); 2801 } 2802 2803 #ifdef EM_LEGACY_IRQ 2804 /* We do Legacy setup */ 2805 if ((error = bus_setup_intr(dev, adapter->res[0], 2806 #if __FreeBSD_version > 700000 2807 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_intr, adapter, 2808 #else /* 6.X */ 2809 INTR_TYPE_NET | INTR_MPSAFE, em_intr, adapter, 2810 #endif 2811 &adapter->tag[0])) != 0) { 2812 device_printf(dev, "Failed to register interrupt handler"); 2813 return (error); 2814 } 2815 2816 #else /* FAST_IRQ */ 2817 /* 2818 * Try allocating a fast interrupt and the associated deferred 2819 * processing contexts. 2820 */ 2821 TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter); 2822 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2823 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2824 taskqueue_thread_enqueue, &adapter->tq); 2825 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2826 device_get_nameunit(adapter->dev)); 2827 #if __FreeBSD_version < 700000 2828 if ((error = bus_setup_intr(dev, adapter->res[0], 2829 INTR_TYPE_NET | INTR_FAST, em_irq_fast, adapter, 2830 #else 2831 if ((error = bus_setup_intr(dev, adapter->res[0], 2832 INTR_TYPE_NET, em_irq_fast, NULL, adapter, 2833 #endif 2834 &adapter->tag[0])) != 0) { 2835 device_printf(dev, "Failed to register fast interrupt " 2836 "handler: %d\n", error); 2837 taskqueue_free(adapter->tq); 2838 adapter->tq = NULL; 2839 return (error); 2840 } 2841 #endif /* EM_LEGACY_IRQ */ 2842 2843 return (0); 2844 } 2845 2846 /********************************************************************* 2847 * 2848 * Setup the MSIX Interrupt handlers 2849 * This is not really Multiqueue, rather 2850 * its just multiple interrupt vectors. 2851 * 2852 **********************************************************************/ 2853 int 2854 em_allocate_msix(struct adapter *adapter) 2855 { 2856 device_t dev = adapter->dev; 2857 int error; 2858 2859 /* Make sure all interrupts are disabled */ 2860 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2861 2862 /* First get the resources */ 2863 for (int i = 0; i < adapter->msi; i++) { 2864 adapter->res[i] = bus_alloc_resource_any(dev, 2865 SYS_RES_IRQ, &adapter->rid[i], RF_ACTIVE); 2866 if (adapter->res[i] == NULL) { 2867 device_printf(dev, 2868 "Unable to allocate bus resource: " 2869 "MSIX Interrupt\n"); 2870 return (ENXIO); 2871 } 2872 } 2873 2874 /* 2875 * Now allocate deferred processing contexts. 2876 */ 2877 TASK_INIT(&adapter->rx_task, 0, em_handle_rx, adapter); 2878 TASK_INIT(&adapter->tx_task, 0, em_handle_tx, adapter); 2879 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2880 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2881 taskqueue_thread_enqueue, &adapter->tq); 2882 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2883 device_get_nameunit(adapter->dev)); 2884 2885 /* 2886 * And setup the interrupt handlers 2887 */ 2888 2889 /* First slot to RX */ 2890 if ((error = bus_setup_intr(dev, adapter->res[0], 2891 #if __FreeBSD_version > 700000 2892 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_msix_rx, adapter, 2893 #else /* 6.X */ 2894 INTR_TYPE_NET | INTR_MPSAFE, em_msix_rx, adapter, 2895 #endif 2896 &adapter->tag[0])) != 0) { 2897 device_printf(dev, "Failed to register RX handler"); 2898 return (error); 2899 } 2900 2901 /* Next TX */ 2902 if ((error = bus_setup_intr(dev, adapter->res[1], 2903 #if __FreeBSD_version > 700000 2904 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_msix_tx, adapter, 2905 #else /* 6.X */ 2906 INTR_TYPE_NET | INTR_MPSAFE, em_msix_tx, adapter, 2907 #endif 2908 &adapter->tag[1])) != 0) { 2909 device_printf(dev, "Failed to register TX handler"); 2910 return (error); 2911 } 2912 2913 /* And Link */ 2914 if ((error = bus_setup_intr(dev, adapter->res[2], 2915 #if __FreeBSD_version > 700000 2916 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_msix_link, adapter, 2917 #else /* 6.X */ 2918 INTR_TYPE_NET | INTR_MPSAFE, em_msix_link, adapter, 2919 #endif 2920 &adapter->tag[2])) != 0) { 2921 device_printf(dev, "Failed to register TX handler"); 2922 return (error); 2923 } 2924 2925 return (0); 2926 } 2927 2928 static void 2929 em_free_pci_resources(struct adapter *adapter) 2930 { 2931 device_t dev = adapter->dev; 2932 2933 /* Make sure the for loop below runs once */ 2934 if (adapter->msi == 0) 2935 adapter->msi = 1; 2936 2937 /* 2938 * First release all the interrupt resources: 2939 * notice that since these are just kept 2940 * in an array we can do the same logic 2941 * whether its MSIX or just legacy. 2942 */ 2943 for (int i = 0; i < adapter->msi; i++) { 2944 if (adapter->tag[i] != NULL) { 2945 bus_teardown_intr(dev, adapter->res[i], 2946 adapter->tag[i]); 2947 adapter->tag[i] = NULL; 2948 } 2949 if (adapter->res[i] != NULL) { 2950 bus_release_resource(dev, SYS_RES_IRQ, 2951 adapter->rid[i], adapter->res[i]); 2952 } 2953 } 2954 2955 if (adapter->msi) 2956 pci_release_msi(dev); 2957 2958 if (adapter->msix != NULL) 2959 bus_release_resource(dev, SYS_RES_MEMORY, 2960 PCIR_BAR(EM_MSIX_BAR), adapter->msix); 2961 2962 if (adapter->memory != NULL) 2963 bus_release_resource(dev, SYS_RES_MEMORY, 2964 PCIR_BAR(0), adapter->memory); 2965 2966 if (adapter->flash != NULL) 2967 bus_release_resource(dev, SYS_RES_MEMORY, 2968 EM_FLASH, adapter->flash); 2969 2970 if (adapter->ioport != NULL) 2971 bus_release_resource(dev, SYS_RES_IOPORT, 2972 adapter->io_rid, adapter->ioport); 2973 } 2974 2975 /* 2976 * Setup MSI/X 2977 */ 2978 static int 2979 em_setup_msix(struct adapter *adapter) 2980 { 2981 device_t dev = adapter->dev; 2982 int val = 0; 2983 2984 if (adapter->hw.mac.type < e1000_82571) 2985 return (0); 2986 2987 /* Setup MSI/X for Hartwell */ 2988 if (adapter->hw.mac.type == e1000_82574) { 2989 /* Map the MSIX BAR */ 2990 int rid = PCIR_BAR(EM_MSIX_BAR); 2991 adapter->msix = bus_alloc_resource_any(dev, 2992 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2993 if (!adapter->msix) { 2994 /* May not be enabled */ 2995 device_printf(adapter->dev, 2996 "Unable to map MSIX table \n"); 2997 goto msi; 2998 } 2999 val = pci_msix_count(dev); 3000 /* 3001 ** 82574 can be configured for 5 but 3002 ** we limit use to 3. 3003 */ 3004 if (val > 3) val = 3; 3005 if ((val) && pci_alloc_msix(dev, &val) == 0) { 3006 device_printf(adapter->dev,"Using MSIX interrupts\n"); 3007 return (val); 3008 } 3009 } 3010 msi: 3011 val = pci_msi_count(dev); 3012 if (val == 1 && pci_alloc_msi(dev, &val) == 0) { 3013 adapter->msi = 1; 3014 device_printf(adapter->dev,"Using MSI interrupt\n"); 3015 return (val); 3016 } 3017 return (0); 3018 } 3019 3020 /********************************************************************* 3021 * 3022 * Initialize the hardware to a configuration 3023 * as specified by the adapter structure. 3024 * 3025 **********************************************************************/ 3026 static int 3027 em_hardware_init(struct adapter *adapter) 3028 { 3029 device_t dev = adapter->dev; 3030 u16 rx_buffer_size; 3031 3032 INIT_DEBUGOUT("em_hardware_init: begin"); 3033 3034 /* Issue a global reset */ 3035 e1000_reset_hw(&adapter->hw); 3036 3037 /* Get control from any management/hw control */ 3038 if (((adapter->hw.mac.type == e1000_82573) || 3039 (adapter->hw.mac.type == e1000_ich8lan) || 3040 (adapter->hw.mac.type == e1000_ich10lan) || 3041 (adapter->hw.mac.type == e1000_ich9lan)) && 3042 e1000_check_mng_mode(&adapter->hw)) 3043 em_get_hw_control(adapter); 3044 3045 /* When hardware is reset, fifo_head is also reset */ 3046 adapter->tx_fifo_head = 0; 3047 3048 /* Set up smart power down as default off on newer adapters. */ 3049 if (!em_smart_pwr_down && (adapter->hw.mac.type == e1000_82571 || 3050 adapter->hw.mac.type == e1000_82572)) { 3051 u16 phy_tmp = 0; 3052 3053 /* Speed up time to link by disabling smart power down. */ 3054 e1000_read_phy_reg(&adapter->hw, 3055 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3056 phy_tmp &= ~IGP02E1000_PM_SPD; 3057 e1000_write_phy_reg(&adapter->hw, 3058 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3059 } 3060 3061 /* 3062 * These parameters control the automatic generation (Tx) and 3063 * response (Rx) to Ethernet PAUSE frames. 3064 * - High water mark should allow for at least two frames to be 3065 * received after sending an XOFF. 3066 * - Low water mark works best when it is very near the high water mark. 3067 * This allows the receiver to restart by sending XON when it has 3068 * drained a bit. Here we use an arbitary value of 1500 which will 3069 * restart after one full frame is pulled from the buffer. There 3070 * could be several smaller frames in the buffer and if so they will 3071 * not trigger the XON until their total number reduces the buffer 3072 * by 1500. 3073 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3074 */ 3075 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 3076 0xffff) << 10 ); 3077 3078 adapter->hw.fc.high_water = rx_buffer_size - 3079 roundup2(adapter->max_frame_size, 1024); 3080 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 3081 3082 if (adapter->hw.mac.type == e1000_80003es2lan) 3083 adapter->hw.fc.pause_time = 0xFFFF; 3084 else 3085 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 3086 adapter->hw.fc.send_xon = TRUE; 3087 adapter->hw.fc.requested_mode = e1000_fc_full; 3088 3089 if (e1000_init_hw(&adapter->hw) < 0) { 3090 device_printf(dev, "Hardware Initialization Failed\n"); 3091 return (EIO); 3092 } 3093 3094 e1000_check_for_link(&adapter->hw); 3095 3096 return (0); 3097 } 3098 3099 /********************************************************************* 3100 * 3101 * Setup networking device structure and register an interface. 3102 * 3103 **********************************************************************/ 3104 static void 3105 em_setup_interface(device_t dev, struct adapter *adapter) 3106 { 3107 struct ifnet *ifp; 3108 3109 INIT_DEBUGOUT("em_setup_interface: begin"); 3110 3111 ifp = adapter->ifp = if_alloc(IFT_ETHER); 3112 if (ifp == NULL) 3113 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 3114 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3115 ifp->if_mtu = ETHERMTU; 3116 ifp->if_init = em_init; 3117 ifp->if_softc = adapter; 3118 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3119 ifp->if_ioctl = em_ioctl; 3120 ifp->if_start = em_start; 3121 IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); 3122 ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; 3123 IFQ_SET_READY(&ifp->if_snd); 3124 3125 ether_ifattach(ifp, adapter->hw.mac.addr); 3126 3127 ifp->if_capabilities = ifp->if_capenable = 0; 3128 3129 if (adapter->hw.mac.type >= e1000_82543) { 3130 int version_cap; 3131 #if __FreeBSD_version < 700000 3132 version_cap = IFCAP_HWCSUM; 3133 #else 3134 version_cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 3135 #endif 3136 ifp->if_capabilities |= version_cap; 3137 ifp->if_capenable |= version_cap; 3138 } 3139 3140 #if __FreeBSD_version >= 700000 3141 /* Identify TSO capable adapters */ 3142 if ((adapter->hw.mac.type > e1000_82544) && 3143 (adapter->hw.mac.type != e1000_82547)) 3144 ifp->if_capabilities |= IFCAP_TSO4; 3145 /* 3146 * By default only enable on PCI-E, this 3147 * can be overriden by ifconfig. 3148 */ 3149 if (adapter->hw.mac.type >= e1000_82571) 3150 ifp->if_capenable |= IFCAP_TSO4; 3151 #endif 3152 3153 /* 3154 * Tell the upper layer(s) we support long frames. 3155 */ 3156 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3157 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 3158 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 3159 3160 #ifdef DEVICE_POLLING 3161 ifp->if_capabilities |= IFCAP_POLLING; 3162 #endif 3163 3164 /* 3165 * Specify the media types supported by this adapter and register 3166 * callbacks to update media and link information 3167 */ 3168 ifmedia_init(&adapter->media, IFM_IMASK, 3169 em_media_change, em_media_status); 3170 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3171 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 3172 u_char fiber_type = IFM_1000_SX; /* default type */ 3173 3174 if (adapter->hw.mac.type == e1000_82545) 3175 fiber_type = IFM_1000_LX; 3176 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 3177 0, NULL); 3178 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 3179 } else { 3180 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 3181 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 3182 0, NULL); 3183 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 3184 0, NULL); 3185 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 3186 0, NULL); 3187 if (adapter->hw.phy.type != e1000_phy_ife) { 3188 ifmedia_add(&adapter->media, 3189 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3190 ifmedia_add(&adapter->media, 3191 IFM_ETHER | IFM_1000_T, 0, NULL); 3192 } 3193 } 3194 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3195 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 3196 } 3197 3198 3199 /********************************************************************* 3200 * 3201 * Workaround for SmartSpeed on 82541 and 82547 controllers 3202 * 3203 **********************************************************************/ 3204 static void 3205 em_smartspeed(struct adapter *adapter) 3206 { 3207 u16 phy_tmp; 3208 3209 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 3210 adapter->hw.mac.autoneg == 0 || 3211 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 3212 return; 3213 3214 if (adapter->smartspeed == 0) { 3215 /* If Master/Slave config fault is asserted twice, 3216 * we assume back-to-back */ 3217 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 3218 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 3219 return; 3220 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 3221 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 3222 e1000_read_phy_reg(&adapter->hw, 3223 PHY_1000T_CTRL, &phy_tmp); 3224 if(phy_tmp & CR_1000T_MS_ENABLE) { 3225 phy_tmp &= ~CR_1000T_MS_ENABLE; 3226 e1000_write_phy_reg(&adapter->hw, 3227 PHY_1000T_CTRL, phy_tmp); 3228 adapter->smartspeed++; 3229 if(adapter->hw.mac.autoneg && 3230 !e1000_phy_setup_autoneg(&adapter->hw) && 3231 !e1000_read_phy_reg(&adapter->hw, 3232 PHY_CONTROL, &phy_tmp)) { 3233 phy_tmp |= (MII_CR_AUTO_NEG_EN | 3234 MII_CR_RESTART_AUTO_NEG); 3235 e1000_write_phy_reg(&adapter->hw, 3236 PHY_CONTROL, phy_tmp); 3237 } 3238 } 3239 } 3240 return; 3241 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 3242 /* If still no link, perhaps using 2/3 pair cable */ 3243 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 3244 phy_tmp |= CR_1000T_MS_ENABLE; 3245 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 3246 if(adapter->hw.mac.autoneg && 3247 !e1000_phy_setup_autoneg(&adapter->hw) && 3248 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 3249 phy_tmp |= (MII_CR_AUTO_NEG_EN | 3250 MII_CR_RESTART_AUTO_NEG); 3251 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 3252 } 3253 } 3254 /* Restart process after EM_SMARTSPEED_MAX iterations */ 3255 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 3256 adapter->smartspeed = 0; 3257 } 3258 3259 3260 /* 3261 * Manage DMA'able memory. 3262 */ 3263 static void 3264 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3265 { 3266 if (error) 3267 return; 3268 *(bus_addr_t *) arg = segs[0].ds_addr; 3269 } 3270 3271 static int 3272 em_dma_malloc(struct adapter *adapter, bus_size_t size, 3273 struct em_dma_alloc *dma, int mapflags) 3274 { 3275 int error; 3276 3277 #if __FreeBSD_version >= 700000 3278 error = bus_dma_tag_create(bus_get_dma_tag(adapter->dev), /* parent */ 3279 #else 3280 error = bus_dma_tag_create(NULL, /* parent */ 3281 #endif 3282 EM_DBA_ALIGN, 0, /* alignment, bounds */ 3283 BUS_SPACE_MAXADDR, /* lowaddr */ 3284 BUS_SPACE_MAXADDR, /* highaddr */ 3285 NULL, NULL, /* filter, filterarg */ 3286 size, /* maxsize */ 3287 1, /* nsegments */ 3288 size, /* maxsegsize */ 3289 0, /* flags */ 3290 NULL, /* lockfunc */ 3291 NULL, /* lockarg */ 3292 &dma->dma_tag); 3293 if (error) { 3294 device_printf(adapter->dev, 3295 "%s: bus_dma_tag_create failed: %d\n", 3296 __func__, error); 3297 goto fail_0; 3298 } 3299 3300 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 3301 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 3302 if (error) { 3303 device_printf(adapter->dev, 3304 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 3305 __func__, (uintmax_t)size, error); 3306 goto fail_2; 3307 } 3308 3309 dma->dma_paddr = 0; 3310 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 3311 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 3312 if (error || dma->dma_paddr == 0) { 3313 device_printf(adapter->dev, 3314 "%s: bus_dmamap_load failed: %d\n", 3315 __func__, error); 3316 goto fail_3; 3317 } 3318 3319 return (0); 3320 3321 fail_3: 3322 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 3323 fail_2: 3324 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 3325 bus_dma_tag_destroy(dma->dma_tag); 3326 fail_0: 3327 dma->dma_map = NULL; 3328 dma->dma_tag = NULL; 3329 3330 return (error); 3331 } 3332 3333 static void 3334 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 3335 { 3336 if (dma->dma_tag == NULL) 3337 return; 3338 if (dma->dma_map != NULL) { 3339 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 3340 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3341 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 3342 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 3343 dma->dma_map = NULL; 3344 } 3345 bus_dma_tag_destroy(dma->dma_tag); 3346 dma->dma_tag = NULL; 3347 } 3348 3349 3350 /********************************************************************* 3351 * 3352 * Allocate memory for tx_buffer structures. The tx_buffer stores all 3353 * the information needed to transmit a packet on the wire. 3354 * 3355 **********************************************************************/ 3356 static int 3357 em_allocate_transmit_structures(struct adapter *adapter) 3358 { 3359 device_t dev = adapter->dev; 3360 struct em_buffer *tx_buffer; 3361 int error; 3362 3363 /* 3364 * Create DMA tags for tx descriptors 3365 */ 3366 #if __FreeBSD_version >= 700000 3367 if ((error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3368 #else 3369 if ((error = bus_dma_tag_create(NULL, /* parent */ 3370 #endif 3371 1, 0, /* alignment, bounds */ 3372 BUS_SPACE_MAXADDR, /* lowaddr */ 3373 BUS_SPACE_MAXADDR, /* highaddr */ 3374 NULL, NULL, /* filter, filterarg */ 3375 EM_TSO_SIZE, /* maxsize */ 3376 EM_MAX_SCATTER, /* nsegments */ 3377 EM_TSO_SEG_SIZE, /* maxsegsize */ 3378 0, /* flags */ 3379 NULL, /* lockfunc */ 3380 NULL, /* lockarg */ 3381 &adapter->txtag)) != 0) { 3382 device_printf(dev, "Unable to allocate TX DMA tag\n"); 3383 goto fail; 3384 } 3385 3386 adapter->tx_buffer_area = malloc(sizeof(struct em_buffer) * 3387 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 3388 if (adapter->tx_buffer_area == NULL) { 3389 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 3390 error = ENOMEM; 3391 goto fail; 3392 } 3393 3394 /* Create the descriptor buffer dma maps */ 3395 for (int i = 0; i < adapter->num_tx_desc; i++) { 3396 tx_buffer = &adapter->tx_buffer_area[i]; 3397 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 3398 if (error != 0) { 3399 device_printf(dev, "Unable to create TX DMA map\n"); 3400 goto fail; 3401 } 3402 tx_buffer->next_eop = -1; 3403 } 3404 3405 return (0); 3406 fail: 3407 em_free_transmit_structures(adapter); 3408 return (error); 3409 } 3410 3411 /********************************************************************* 3412 * 3413 * (Re)Initialize transmit structures. 3414 * 3415 **********************************************************************/ 3416 static void 3417 em_setup_transmit_structures(struct adapter *adapter) 3418 { 3419 struct em_buffer *tx_buffer; 3420 3421 /* Clear the old ring contents */ 3422 bzero(adapter->tx_desc_base, 3423 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 3424 3425 /* Free any existing TX buffers */ 3426 for (int i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 3427 tx_buffer = &adapter->tx_buffer_area[i]; 3428 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3429 BUS_DMASYNC_POSTWRITE); 3430 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 3431 m_freem(tx_buffer->m_head); 3432 tx_buffer->m_head = NULL; 3433 tx_buffer->next_eop = -1; 3434 } 3435 3436 /* Reset state */ 3437 adapter->next_avail_tx_desc = 0; 3438 adapter->next_tx_to_clean = 0; 3439 adapter->num_tx_desc_avail = adapter->num_tx_desc; 3440 3441 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3442 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3443 3444 return; 3445 } 3446 3447 /********************************************************************* 3448 * 3449 * Enable transmit unit. 3450 * 3451 **********************************************************************/ 3452 static void 3453 em_initialize_transmit_unit(struct adapter *adapter) 3454 { 3455 u32 tctl, tarc, tipg = 0; 3456 u64 bus_addr; 3457 3458 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3459 /* Setup the Base and Length of the Tx Descriptor Ring */ 3460 bus_addr = adapter->txdma.dma_paddr; 3461 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 3462 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 3463 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 3464 (u32)(bus_addr >> 32)); 3465 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 3466 (u32)bus_addr); 3467 /* Setup the HW Tx Head and Tail descriptor pointers */ 3468 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 3469 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 3470 3471 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3472 E1000_READ_REG(&adapter->hw, E1000_TDBAL(0)), 3473 E1000_READ_REG(&adapter->hw, E1000_TDLEN(0))); 3474 3475 /* Set the default values for the Tx Inter Packet Gap timer */ 3476 switch (adapter->hw.mac.type) { 3477 case e1000_82542: 3478 tipg = DEFAULT_82542_TIPG_IPGT; 3479 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3480 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3481 break; 3482 case e1000_80003es2lan: 3483 tipg = DEFAULT_82543_TIPG_IPGR1; 3484 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3485 E1000_TIPG_IPGR2_SHIFT; 3486 break; 3487 default: 3488 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3489 (adapter->hw.phy.media_type == 3490 e1000_media_type_internal_serdes)) 3491 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3492 else 3493 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3494 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3495 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3496 } 3497 3498 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3499 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3500 if(adapter->hw.mac.type >= e1000_82540) 3501 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3502 adapter->tx_abs_int_delay.value); 3503 3504 if ((adapter->hw.mac.type == e1000_82571) || 3505 (adapter->hw.mac.type == e1000_82572)) { 3506 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3507 tarc |= SPEED_MODE_BIT; 3508 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3509 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3510 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3511 tarc |= 1; 3512 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3513 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3514 tarc |= 1; 3515 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3516 } 3517 3518 /* Program the Transmit Control Register */ 3519 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3520 tctl &= ~E1000_TCTL_CT; 3521 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3522 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3523 3524 if (adapter->hw.mac.type >= e1000_82571) 3525 tctl |= E1000_TCTL_MULR; 3526 3527 /* This write will effectively turn on the transmit unit. */ 3528 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3529 3530 /* Setup Transmit Descriptor Base Settings */ 3531 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 3532 3533 if (adapter->tx_int_delay.value > 0) 3534 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3535 } 3536 3537 /********************************************************************* 3538 * 3539 * Free all transmit related data structures. 3540 * 3541 **********************************************************************/ 3542 static void 3543 em_free_transmit_structures(struct adapter *adapter) 3544 { 3545 struct em_buffer *tx_buffer; 3546 3547 INIT_DEBUGOUT("free_transmit_structures: begin"); 3548 3549 if (adapter->tx_buffer_area != NULL) { 3550 for (int i = 0; i < adapter->num_tx_desc; i++) { 3551 tx_buffer = &adapter->tx_buffer_area[i]; 3552 if (tx_buffer->m_head != NULL) { 3553 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3554 BUS_DMASYNC_POSTWRITE); 3555 bus_dmamap_unload(adapter->txtag, 3556 tx_buffer->map); 3557 m_freem(tx_buffer->m_head); 3558 tx_buffer->m_head = NULL; 3559 } else if (tx_buffer->map != NULL) 3560 bus_dmamap_unload(adapter->txtag, 3561 tx_buffer->map); 3562 if (tx_buffer->map != NULL) { 3563 bus_dmamap_destroy(adapter->txtag, 3564 tx_buffer->map); 3565 tx_buffer->map = NULL; 3566 } 3567 } 3568 } 3569 if (adapter->tx_buffer_area != NULL) { 3570 free(adapter->tx_buffer_area, M_DEVBUF); 3571 adapter->tx_buffer_area = NULL; 3572 } 3573 if (adapter->txtag != NULL) { 3574 bus_dma_tag_destroy(adapter->txtag); 3575 adapter->txtag = NULL; 3576 } 3577 } 3578 3579 /********************************************************************* 3580 * 3581 * The offload context needs to be set when we transfer the first 3582 * packet of a particular protocol (TCP/UDP). This routine has been 3583 * enhanced to deal with inserted VLAN headers, and IPV6 (not complete) 3584 * 3585 **********************************************************************/ 3586 static void 3587 em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp, 3588 u32 *txd_upper, u32 *txd_lower) 3589 { 3590 struct e1000_context_desc *TXD; 3591 struct em_buffer *tx_buffer; 3592 struct ether_vlan_header *eh; 3593 struct ip *ip = NULL; 3594 struct ip6_hdr *ip6; 3595 struct tcp_hdr *th; 3596 int curr_txd, ehdrlen; 3597 u32 cmd, hdr_len, ip_hlen; 3598 u16 etype; 3599 u8 ipproto; 3600 3601 cmd = hdr_len = ipproto = 0; 3602 /* Setup checksum offload context. */ 3603 curr_txd = adapter->next_avail_tx_desc; 3604 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3605 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3606 3607 /* 3608 * Determine where frame payload starts. 3609 * Jump over vlan headers if already present, 3610 * helpful for QinQ too. 3611 */ 3612 eh = mtod(mp, struct ether_vlan_header *); 3613 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3614 etype = ntohs(eh->evl_proto); 3615 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3616 } else { 3617 etype = ntohs(eh->evl_encap_proto); 3618 ehdrlen = ETHER_HDR_LEN; 3619 } 3620 3621 /* 3622 * We only support TCP/UDP for IPv4 and IPv6 for the moment. 3623 * TODO: Support SCTP too when it hits the tree. 3624 */ 3625 switch (etype) { 3626 case ETHERTYPE_IP: 3627 ip = (struct ip *)(mp->m_data + ehdrlen); 3628 ip_hlen = ip->ip_hl << 2; 3629 3630 /* Setup of IP header checksum. */ 3631 if (mp->m_pkthdr.csum_flags & CSUM_IP) { 3632 /* 3633 * Start offset for header checksum calculation. 3634 * End offset for header checksum calculation. 3635 * Offset of place to put the checksum. 3636 */ 3637 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3638 TXD->lower_setup.ip_fields.ipcse = 3639 htole16(ehdrlen + ip_hlen); 3640 TXD->lower_setup.ip_fields.ipcso = 3641 ehdrlen + offsetof(struct ip, ip_sum); 3642 cmd |= E1000_TXD_CMD_IP; 3643 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 3644 } 3645 3646 if (mp->m_len < ehdrlen + ip_hlen) 3647 return; /* failure */ 3648 3649 hdr_len = ehdrlen + ip_hlen; 3650 ipproto = ip->ip_p; 3651 3652 break; 3653 case ETHERTYPE_IPV6: 3654 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3655 ip_hlen = sizeof(struct ip6_hdr); /* XXX: No header stacking. */ 3656 3657 if (mp->m_len < ehdrlen + ip_hlen) 3658 return; /* failure */ 3659 3660 /* IPv6 doesn't have a header checksum. */ 3661 3662 hdr_len = ehdrlen + ip_hlen; 3663 ipproto = ip6->ip6_nxt; 3664 3665 break; 3666 #ifdef EM_TIMESYNC 3667 case ETHERTYPE_IEEE1588: 3668 *txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 3669 break; 3670 #endif 3671 default: 3672 *txd_upper = 0; 3673 *txd_lower = 0; 3674 return; 3675 } 3676 3677 switch (ipproto) { 3678 case IPPROTO_TCP: 3679 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 3680 /* 3681 * Start offset for payload checksum calculation. 3682 * End offset for payload checksum calculation. 3683 * Offset of place to put the checksum. 3684 */ 3685 th = (struct tcp_hdr *)(mp->m_data + hdr_len); 3686 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3687 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3688 TXD->upper_setup.tcp_fields.tucso = 3689 hdr_len + offsetof(struct tcphdr, th_sum); 3690 cmd |= E1000_TXD_CMD_TCP; 3691 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3692 } 3693 break; 3694 case IPPROTO_UDP: 3695 { 3696 #ifdef EM_TIMESYNC 3697 void *hdr = (caddr_t) ip + ip_hlen; 3698 struct udphdr *uh = (struct udphdr *)hdr; 3699 3700 if (uh->uh_dport == htons(TSYNC_PORT)) { 3701 *txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 3702 IOCTL_DEBUGOUT("@@@ Sending Event Packet\n"); 3703 } 3704 #endif 3705 if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 3706 /* 3707 * Start offset for header checksum calculation. 3708 * End offset for header checksum calculation. 3709 * Offset of place to put the checksum. 3710 */ 3711 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3712 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3713 TXD->upper_setup.tcp_fields.tucso = 3714 hdr_len + offsetof(struct udphdr, uh_sum); 3715 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3716 } 3717 /* Fall Thru */ 3718 } 3719 default: 3720 break; 3721 } 3722 3723 #ifdef EM_TIMESYNC 3724 /* 3725 ** We might be here just for TIMESYNC 3726 ** which means we don't need the context 3727 ** descriptor. 3728 */ 3729 if (!mp->m_pkthdr.csum_flags & CSUM_OFFLOAD) 3730 return; 3731 #endif 3732 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3733 E1000_TXD_DTYP_D; /* Data descr */ 3734 TXD->tcp_seg_setup.data = htole32(0); 3735 TXD->cmd_and_length = 3736 htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT | cmd); 3737 tx_buffer->m_head = NULL; 3738 tx_buffer->next_eop = -1; 3739 3740 if (++curr_txd == adapter->num_tx_desc) 3741 curr_txd = 0; 3742 3743 adapter->num_tx_desc_avail--; 3744 adapter->next_avail_tx_desc = curr_txd; 3745 } 3746 3747 3748 #if __FreeBSD_version >= 700000 3749 /********************************************************************** 3750 * 3751 * Setup work for hardware segmentation offload (TSO) 3752 * 3753 **********************************************************************/ 3754 static bool 3755 em_tso_setup(struct adapter *adapter, struct mbuf *mp, u32 *txd_upper, 3756 u32 *txd_lower) 3757 { 3758 struct e1000_context_desc *TXD; 3759 struct em_buffer *tx_buffer; 3760 struct ether_vlan_header *eh; 3761 struct ip *ip; 3762 struct ip6_hdr *ip6; 3763 struct tcphdr *th; 3764 int curr_txd, ehdrlen, hdr_len, ip_hlen, isip6; 3765 u16 etype; 3766 3767 /* 3768 * This function could/should be extended to support IP/IPv6 3769 * fragmentation as well. But as they say, one step at a time. 3770 */ 3771 3772 /* 3773 * Determine where frame payload starts. 3774 * Jump over vlan headers if already present, 3775 * helpful for QinQ too. 3776 */ 3777 eh = mtod(mp, struct ether_vlan_header *); 3778 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3779 etype = ntohs(eh->evl_proto); 3780 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3781 } else { 3782 etype = ntohs(eh->evl_encap_proto); 3783 ehdrlen = ETHER_HDR_LEN; 3784 } 3785 3786 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3787 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3788 return FALSE; /* -1 */ 3789 3790 /* 3791 * We only support TCP for IPv4 and IPv6 (notyet) for the moment. 3792 * TODO: Support SCTP too when it hits the tree. 3793 */ 3794 switch (etype) { 3795 case ETHERTYPE_IP: 3796 isip6 = 0; 3797 ip = (struct ip *)(mp->m_data + ehdrlen); 3798 if (ip->ip_p != IPPROTO_TCP) 3799 return FALSE; /* 0 */ 3800 ip->ip_len = 0; 3801 ip->ip_sum = 0; 3802 ip_hlen = ip->ip_hl << 2; 3803 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3804 return FALSE; /* -1 */ 3805 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3806 #if 1 3807 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3808 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3809 #else 3810 th->th_sum = mp->m_pkthdr.csum_data; 3811 #endif 3812 break; 3813 case ETHERTYPE_IPV6: 3814 isip6 = 1; 3815 return FALSE; /* Not supported yet. */ 3816 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3817 if (ip6->ip6_nxt != IPPROTO_TCP) 3818 return FALSE; /* 0 */ 3819 ip6->ip6_plen = 0; 3820 ip_hlen = sizeof(struct ip6_hdr); /* XXX: no header stacking. */ 3821 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3822 return FALSE; /* -1 */ 3823 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 3824 #if 0 3825 th->th_sum = in6_pseudo(ip6->ip6_src, ip->ip6_dst, 3826 htons(IPPROTO_TCP)); /* XXX: function notyet. */ 3827 #else 3828 th->th_sum = mp->m_pkthdr.csum_data; 3829 #endif 3830 break; 3831 default: 3832 return FALSE; 3833 } 3834 hdr_len = ehdrlen + ip_hlen + (th->th_off << 2); 3835 3836 *txd_lower = (E1000_TXD_CMD_DEXT | /* Extended descr type */ 3837 E1000_TXD_DTYP_D | /* Data descr type */ 3838 E1000_TXD_CMD_TSE); /* Do TSE on this packet */ 3839 3840 /* IP and/or TCP header checksum calculation and insertion. */ 3841 *txd_upper = ((isip6 ? 0 : E1000_TXD_POPTS_IXSM) | 3842 E1000_TXD_POPTS_TXSM) << 8; 3843 3844 curr_txd = adapter->next_avail_tx_desc; 3845 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3846 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3847 3848 /* IPv6 doesn't have a header checksum. */ 3849 if (!isip6) { 3850 /* 3851 * Start offset for header checksum calculation. 3852 * End offset for header checksum calculation. 3853 * Offset of place put the checksum. 3854 */ 3855 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3856 TXD->lower_setup.ip_fields.ipcse = 3857 htole16(ehdrlen + ip_hlen - 1); 3858 TXD->lower_setup.ip_fields.ipcso = 3859 ehdrlen + offsetof(struct ip, ip_sum); 3860 } 3861 /* 3862 * Start offset for payload checksum calculation. 3863 * End offset for payload checksum calculation. 3864 * Offset of place to put the checksum. 3865 */ 3866 TXD->upper_setup.tcp_fields.tucss = 3867 ehdrlen + ip_hlen; 3868 TXD->upper_setup.tcp_fields.tucse = 0; 3869 TXD->upper_setup.tcp_fields.tucso = 3870 ehdrlen + ip_hlen + offsetof(struct tcphdr, th_sum); 3871 /* 3872 * Payload size per packet w/o any headers. 3873 * Length of all headers up to payload. 3874 */ 3875 TXD->tcp_seg_setup.fields.mss = htole16(mp->m_pkthdr.tso_segsz); 3876 TXD->tcp_seg_setup.fields.hdr_len = hdr_len; 3877 3878 TXD->cmd_and_length = htole32(adapter->txd_cmd | 3879 E1000_TXD_CMD_DEXT | /* Extended descr */ 3880 E1000_TXD_CMD_TSE | /* TSE context */ 3881 (isip6 ? 0 : E1000_TXD_CMD_IP) | /* Do IP csum */ 3882 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3883 (mp->m_pkthdr.len - (hdr_len))); /* Total len */ 3884 3885 tx_buffer->m_head = NULL; 3886 tx_buffer->next_eop = -1; 3887 3888 if (++curr_txd == adapter->num_tx_desc) 3889 curr_txd = 0; 3890 3891 adapter->num_tx_desc_avail--; 3892 adapter->next_avail_tx_desc = curr_txd; 3893 adapter->tx_tso = TRUE; 3894 3895 return TRUE; 3896 } 3897 3898 #endif /* __FreeBSD_version >= 700000 */ 3899 3900 /********************************************************************** 3901 * 3902 * Examine each tx_buffer in the used queue. If the hardware is done 3903 * processing the packet then free associated resources. The 3904 * tx_buffer is put back on the free queue. 3905 * 3906 **********************************************************************/ 3907 static void 3908 em_txeof(struct adapter *adapter) 3909 { 3910 int first, last, done, num_avail; 3911 struct em_buffer *tx_buffer; 3912 struct e1000_tx_desc *tx_desc, *eop_desc; 3913 struct ifnet *ifp = adapter->ifp; 3914 3915 EM_TX_LOCK_ASSERT(adapter); 3916 3917 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3918 return; 3919 3920 num_avail = adapter->num_tx_desc_avail; 3921 first = adapter->next_tx_to_clean; 3922 tx_desc = &adapter->tx_desc_base[first]; 3923 tx_buffer = &adapter->tx_buffer_area[first]; 3924 last = tx_buffer->next_eop; 3925 eop_desc = &adapter->tx_desc_base[last]; 3926 3927 /* 3928 * What this does is get the index of the 3929 * first descriptor AFTER the EOP of the 3930 * first packet, that way we can do the 3931 * simple comparison on the inner while loop. 3932 */ 3933 if (++last == adapter->num_tx_desc) 3934 last = 0; 3935 done = last; 3936 3937 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3938 BUS_DMASYNC_POSTREAD); 3939 3940 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3941 /* We clean the range of the packet */ 3942 while (first != done) { 3943 tx_desc->upper.data = 0; 3944 tx_desc->lower.data = 0; 3945 tx_desc->buffer_addr = 0; 3946 num_avail++; 3947 3948 if (tx_buffer->m_head) { 3949 ifp->if_opackets++; 3950 bus_dmamap_sync(adapter->txtag, 3951 tx_buffer->map, 3952 BUS_DMASYNC_POSTWRITE); 3953 bus_dmamap_unload(adapter->txtag, 3954 tx_buffer->map); 3955 3956 m_freem(tx_buffer->m_head); 3957 tx_buffer->m_head = NULL; 3958 } 3959 tx_buffer->next_eop = -1; 3960 3961 if (++first == adapter->num_tx_desc) 3962 first = 0; 3963 3964 tx_buffer = &adapter->tx_buffer_area[first]; 3965 tx_desc = &adapter->tx_desc_base[first]; 3966 } 3967 /* See if we can continue to the next packet */ 3968 last = tx_buffer->next_eop; 3969 if (last != -1) { 3970 eop_desc = &adapter->tx_desc_base[last]; 3971 /* Get new done point */ 3972 if (++last == adapter->num_tx_desc) last = 0; 3973 done = last; 3974 } else 3975 break; 3976 } 3977 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3979 3980 adapter->next_tx_to_clean = first; 3981 3982 /* 3983 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 3984 * that it is OK to send packets. 3985 * If there are no pending descriptors, clear the timeout. Otherwise, 3986 * if some descriptors have been freed, restart the timeout. 3987 */ 3988 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 3989 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3990 /* All clean, turn off the timer */ 3991 if (num_avail == adapter->num_tx_desc) { 3992 adapter->watchdog_timer = 0; 3993 } else 3994 /* Some cleaned, reset the timer */ 3995 if (num_avail != adapter->num_tx_desc_avail) 3996 adapter->watchdog_timer = EM_TX_TIMEOUT; 3997 } 3998 adapter->num_tx_desc_avail = num_avail; 3999 return; 4000 } 4001 4002 /********************************************************************* 4003 * 4004 * When Link is lost sometimes there is work still in the TX ring 4005 * which will result in a watchdog, rather than allow that do an 4006 * attempted cleanup and then reinit here. Note that this has been 4007 * seens mostly with fiber adapters. 4008 * 4009 **********************************************************************/ 4010 static void 4011 em_tx_purge(struct adapter *adapter) 4012 { 4013 if ((!adapter->link_active) && (adapter->watchdog_timer)) { 4014 EM_TX_LOCK(adapter); 4015 em_txeof(adapter); 4016 EM_TX_UNLOCK(adapter); 4017 if (adapter->watchdog_timer) { /* Still not clean? */ 4018 adapter->watchdog_timer = 0; 4019 em_init_locked(adapter); 4020 } 4021 } 4022 } 4023 4024 /********************************************************************* 4025 * 4026 * Get a buffer from system mbuf buffer pool. 4027 * 4028 **********************************************************************/ 4029 static int 4030 em_get_buf(struct adapter *adapter, int i) 4031 { 4032 struct mbuf *m; 4033 bus_dma_segment_t segs[1]; 4034 bus_dmamap_t map; 4035 struct em_buffer *rx_buffer; 4036 int error, nsegs; 4037 4038 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 4039 if (m == NULL) { 4040 adapter->mbuf_cluster_failed++; 4041 return (ENOBUFS); 4042 } 4043 m->m_len = m->m_pkthdr.len = MCLBYTES; 4044 4045 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 4046 m_adj(m, ETHER_ALIGN); 4047 4048 /* 4049 * Using memory from the mbuf cluster pool, invoke the 4050 * bus_dma machinery to arrange the memory mapping. 4051 */ 4052 error = bus_dmamap_load_mbuf_sg(adapter->rxtag, 4053 adapter->rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 4054 if (error != 0) { 4055 m_free(m); 4056 return (error); 4057 } 4058 4059 /* If nsegs is wrong then the stack is corrupt. */ 4060 KASSERT(nsegs == 1, ("Too many segments returned!")); 4061 4062 rx_buffer = &adapter->rx_buffer_area[i]; 4063 if (rx_buffer->m_head != NULL) 4064 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 4065 4066 map = rx_buffer->map; 4067 rx_buffer->map = adapter->rx_sparemap; 4068 adapter->rx_sparemap = map; 4069 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 4070 rx_buffer->m_head = m; 4071 4072 adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 4073 return (0); 4074 } 4075 4076 /********************************************************************* 4077 * 4078 * Allocate memory for rx_buffer structures. Since we use one 4079 * rx_buffer per received packet, the maximum number of rx_buffer's 4080 * that we'll need is equal to the number of receive descriptors 4081 * that we've allocated. 4082 * 4083 **********************************************************************/ 4084 static int 4085 em_allocate_receive_structures(struct adapter *adapter) 4086 { 4087 device_t dev = adapter->dev; 4088 struct em_buffer *rx_buffer; 4089 int i, error; 4090 4091 adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * 4092 adapter->num_rx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 4093 if (adapter->rx_buffer_area == NULL) { 4094 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 4095 return (ENOMEM); 4096 } 4097 4098 #if __FreeBSD_version >= 700000 4099 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 4100 #else 4101 error = bus_dma_tag_create(NULL, /* parent */ 4102 #endif 4103 1, 0, /* alignment, bounds */ 4104 BUS_SPACE_MAXADDR, /* lowaddr */ 4105 BUS_SPACE_MAXADDR, /* highaddr */ 4106 NULL, NULL, /* filter, filterarg */ 4107 MCLBYTES, /* maxsize */ 4108 1, /* nsegments */ 4109 MCLBYTES, /* maxsegsize */ 4110 0, /* flags */ 4111 NULL, /* lockfunc */ 4112 NULL, /* lockarg */ 4113 &adapter->rxtag); 4114 if (error) { 4115 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 4116 __func__, error); 4117 goto fail; 4118 } 4119 4120 /* Create the spare map (used by getbuf) */ 4121 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 4122 &adapter->rx_sparemap); 4123 if (error) { 4124 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 4125 __func__, error); 4126 goto fail; 4127 } 4128 4129 rx_buffer = adapter->rx_buffer_area; 4130 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4131 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 4132 &rx_buffer->map); 4133 if (error) { 4134 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 4135 __func__, error); 4136 goto fail; 4137 } 4138 } 4139 4140 return (0); 4141 4142 fail: 4143 em_free_receive_structures(adapter); 4144 return (error); 4145 } 4146 4147 /********************************************************************* 4148 * 4149 * (Re)initialize receive structures. 4150 * 4151 **********************************************************************/ 4152 static int 4153 em_setup_receive_structures(struct adapter *adapter) 4154 { 4155 struct em_buffer *rx_buffer; 4156 int i, error; 4157 4158 /* Reset descriptor ring */ 4159 bzero(adapter->rx_desc_base, 4160 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 4161 4162 /* Free current RX buffers. */ 4163 rx_buffer = adapter->rx_buffer_area; 4164 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4165 if (rx_buffer->m_head != NULL) { 4166 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4167 BUS_DMASYNC_POSTREAD); 4168 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 4169 m_freem(rx_buffer->m_head); 4170 rx_buffer->m_head = NULL; 4171 } 4172 } 4173 4174 /* Allocate new ones. */ 4175 for (i = 0; i < adapter->num_rx_desc; i++) { 4176 error = em_get_buf(adapter, i); 4177 if (error) 4178 return (error); 4179 } 4180 4181 /* Setup our descriptor pointers */ 4182 adapter->next_rx_desc_to_check = 0; 4183 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4185 4186 return (0); 4187 } 4188 4189 /********************************************************************* 4190 * 4191 * Enable receive unit. 4192 * 4193 **********************************************************************/ 4194 #define MAX_INTS_PER_SEC 8000 4195 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4196 4197 static void 4198 em_initialize_receive_unit(struct adapter *adapter) 4199 { 4200 struct ifnet *ifp = adapter->ifp; 4201 u64 bus_addr; 4202 u32 rctl, rxcsum; 4203 4204 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 4205 4206 /* 4207 * Make sure receives are disabled while setting 4208 * up the descriptor ring 4209 */ 4210 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 4211 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 4212 4213 if (adapter->hw.mac.type >= e1000_82540) { 4214 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 4215 adapter->rx_abs_int_delay.value); 4216 /* 4217 * Set the interrupt throttling rate. Value is calculated 4218 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 4219 */ 4220 E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR); 4221 } 4222 4223 /* 4224 ** When using MSIX interrupts we need to throttle 4225 ** using the EITR register (82574 only) 4226 */ 4227 if (adapter->msix) 4228 for (int i = 0; i < 4; i++) 4229 E1000_WRITE_REG(&adapter->hw, 4230 E1000_EITR_82574(i), DEFAULT_ITR); 4231 4232 /* Disable accelerated ackknowledge */ 4233 if (adapter->hw.mac.type == e1000_82574) 4234 E1000_WRITE_REG(&adapter->hw, 4235 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 4236 4237 /* Setup the Base and Length of the Rx Descriptor Ring */ 4238 bus_addr = adapter->rxdma.dma_paddr; 4239 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 4240 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 4241 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 4242 (u32)(bus_addr >> 32)); 4243 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 4244 (u32)bus_addr); 4245 4246 /* Setup the Receive Control Register */ 4247 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4248 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 4249 E1000_RCTL_RDMTS_HALF | 4250 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4251 4252 /* Make sure VLAN Filters are off */ 4253 rctl &= ~E1000_RCTL_VFE; 4254 4255 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 4256 rctl |= E1000_RCTL_SBP; 4257 else 4258 rctl &= ~E1000_RCTL_SBP; 4259 4260 switch (adapter->rx_buffer_len) { 4261 default: 4262 case 2048: 4263 rctl |= E1000_RCTL_SZ_2048; 4264 break; 4265 case 4096: 4266 rctl |= E1000_RCTL_SZ_4096 | 4267 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4268 break; 4269 case 8192: 4270 rctl |= E1000_RCTL_SZ_8192 | 4271 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4272 break; 4273 case 16384: 4274 rctl |= E1000_RCTL_SZ_16384 | 4275 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4276 break; 4277 } 4278 4279 if (ifp->if_mtu > ETHERMTU) 4280 rctl |= E1000_RCTL_LPE; 4281 else 4282 rctl &= ~E1000_RCTL_LPE; 4283 4284 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 4285 if ((adapter->hw.mac.type >= e1000_82543) && 4286 (ifp->if_capenable & IFCAP_RXCSUM)) { 4287 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 4288 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 4289 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 4290 } 4291 4292 /* 4293 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 4294 ** long latencies are observed, like Lenovo X60. This 4295 ** change eliminates the problem, but since having positive 4296 ** values in RDTR is a known source of problems on other 4297 ** platforms another solution is being sought. 4298 */ 4299 if (adapter->hw.mac.type == e1000_82573) 4300 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 0x20); 4301 4302 /* Enable Receives */ 4303 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 4304 4305 /* 4306 * Setup the HW Rx Head and 4307 * Tail Descriptor Pointers 4308 */ 4309 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 4310 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 4311 4312 return; 4313 } 4314 4315 /********************************************************************* 4316 * 4317 * Free receive related data structures. 4318 * 4319 **********************************************************************/ 4320 static void 4321 em_free_receive_structures(struct adapter *adapter) 4322 { 4323 struct em_buffer *rx_buffer; 4324 int i; 4325 4326 INIT_DEBUGOUT("free_receive_structures: begin"); 4327 4328 if (adapter->rx_sparemap) { 4329 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 4330 adapter->rx_sparemap = NULL; 4331 } 4332 4333 /* Cleanup any existing buffers */ 4334 if (adapter->rx_buffer_area != NULL) { 4335 rx_buffer = adapter->rx_buffer_area; 4336 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4337 if (rx_buffer->m_head != NULL) { 4338 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4339 BUS_DMASYNC_POSTREAD); 4340 bus_dmamap_unload(adapter->rxtag, 4341 rx_buffer->map); 4342 m_freem(rx_buffer->m_head); 4343 rx_buffer->m_head = NULL; 4344 } else if (rx_buffer->map != NULL) 4345 bus_dmamap_unload(adapter->rxtag, 4346 rx_buffer->map); 4347 if (rx_buffer->map != NULL) { 4348 bus_dmamap_destroy(adapter->rxtag, 4349 rx_buffer->map); 4350 rx_buffer->map = NULL; 4351 } 4352 } 4353 } 4354 4355 if (adapter->rx_buffer_area != NULL) { 4356 free(adapter->rx_buffer_area, M_DEVBUF); 4357 adapter->rx_buffer_area = NULL; 4358 } 4359 4360 if (adapter->rxtag != NULL) { 4361 bus_dma_tag_destroy(adapter->rxtag); 4362 adapter->rxtag = NULL; 4363 } 4364 } 4365 4366 /********************************************************************* 4367 * 4368 * This routine executes in interrupt context. It replenishes 4369 * the mbufs in the descriptor and sends data which has been 4370 * dma'ed into host memory to upper layer. 4371 * 4372 * We loop at most count times if count is > 0, or until done if 4373 * count < 0. 4374 * 4375 *********************************************************************/ 4376 static int 4377 em_rxeof(struct adapter *adapter, int count) 4378 { 4379 struct ifnet *ifp = adapter->ifp;; 4380 struct mbuf *mp; 4381 u8 status, accept_frame = 0, eop = 0; 4382 u16 len, desc_len, prev_len_adj; 4383 int i; 4384 struct e1000_rx_desc *current_desc; 4385 4386 EM_RX_LOCK(adapter); 4387 i = adapter->next_rx_desc_to_check; 4388 current_desc = &adapter->rx_desc_base[i]; 4389 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4390 BUS_DMASYNC_POSTREAD); 4391 4392 if (!((current_desc->status) & E1000_RXD_STAT_DD)) { 4393 EM_RX_UNLOCK(adapter); 4394 return (0); 4395 } 4396 4397 while ((current_desc->status & E1000_RXD_STAT_DD) && 4398 (count != 0) && 4399 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4400 struct mbuf *m = NULL; 4401 4402 mp = adapter->rx_buffer_area[i].m_head; 4403 /* 4404 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 4405 * needs to access the last received byte in the mbuf. 4406 */ 4407 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 4408 BUS_DMASYNC_POSTREAD); 4409 4410 accept_frame = 1; 4411 prev_len_adj = 0; 4412 desc_len = le16toh(current_desc->length); 4413 status = current_desc->status; 4414 if (status & E1000_RXD_STAT_EOP) { 4415 count--; 4416 eop = 1; 4417 if (desc_len < ETHER_CRC_LEN) { 4418 len = 0; 4419 prev_len_adj = ETHER_CRC_LEN - desc_len; 4420 } else 4421 len = desc_len - ETHER_CRC_LEN; 4422 } else { 4423 eop = 0; 4424 len = desc_len; 4425 } 4426 4427 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 4428 u8 last_byte; 4429 u32 pkt_len = desc_len; 4430 4431 if (adapter->fmp != NULL) 4432 pkt_len += adapter->fmp->m_pkthdr.len; 4433 4434 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 4435 if (TBI_ACCEPT(&adapter->hw, status, 4436 current_desc->errors, pkt_len, last_byte, 4437 adapter->min_frame_size, adapter->max_frame_size)) { 4438 e1000_tbi_adjust_stats_82543(&adapter->hw, 4439 &adapter->stats, pkt_len, 4440 adapter->hw.mac.addr, 4441 adapter->max_frame_size); 4442 if (len > 0) 4443 len--; 4444 } else 4445 accept_frame = 0; 4446 } 4447 4448 if (accept_frame) { 4449 if (em_get_buf(adapter, i) != 0) { 4450 ifp->if_iqdrops++; 4451 goto discard; 4452 } 4453 4454 /* Assign correct length to the current fragment */ 4455 mp->m_len = len; 4456 4457 if (adapter->fmp == NULL) { 4458 mp->m_pkthdr.len = len; 4459 adapter->fmp = mp; /* Store the first mbuf */ 4460 adapter->lmp = mp; 4461 } else { 4462 /* Chain mbuf's together */ 4463 mp->m_flags &= ~M_PKTHDR; 4464 /* 4465 * Adjust length of previous mbuf in chain if 4466 * we received less than 4 bytes in the last 4467 * descriptor. 4468 */ 4469 if (prev_len_adj > 0) { 4470 adapter->lmp->m_len -= prev_len_adj; 4471 adapter->fmp->m_pkthdr.len -= 4472 prev_len_adj; 4473 } 4474 adapter->lmp->m_next = mp; 4475 adapter->lmp = adapter->lmp->m_next; 4476 adapter->fmp->m_pkthdr.len += len; 4477 } 4478 4479 if (eop) { 4480 adapter->fmp->m_pkthdr.rcvif = ifp; 4481 ifp->if_ipackets++; 4482 em_receive_checksum(adapter, current_desc, 4483 adapter->fmp); 4484 #ifndef __NO_STRICT_ALIGNMENT 4485 if (adapter->max_frame_size > 4486 (MCLBYTES - ETHER_ALIGN) && 4487 em_fixup_rx(adapter) != 0) 4488 goto skip; 4489 #endif 4490 if (status & E1000_RXD_STAT_VP) { 4491 #if __FreeBSD_version < 700000 4492 VLAN_INPUT_TAG_NEW(ifp, adapter->fmp, 4493 (le16toh(current_desc->special) & 4494 E1000_RXD_SPC_VLAN_MASK)); 4495 #else 4496 adapter->fmp->m_pkthdr.ether_vtag = 4497 (le16toh(current_desc->special) & 4498 E1000_RXD_SPC_VLAN_MASK); 4499 adapter->fmp->m_flags |= M_VLANTAG; 4500 #endif 4501 } 4502 #ifndef __NO_STRICT_ALIGNMENT 4503 skip: 4504 #endif 4505 m = adapter->fmp; 4506 adapter->fmp = NULL; 4507 adapter->lmp = NULL; 4508 } 4509 } else { 4510 ifp->if_ierrors++; 4511 discard: 4512 /* Reuse loaded DMA map and just update mbuf chain */ 4513 mp = adapter->rx_buffer_area[i].m_head; 4514 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 4515 mp->m_data = mp->m_ext.ext_buf; 4516 mp->m_next = NULL; 4517 if (adapter->max_frame_size <= 4518 (MCLBYTES - ETHER_ALIGN)) 4519 m_adj(mp, ETHER_ALIGN); 4520 if (adapter->fmp != NULL) { 4521 m_freem(adapter->fmp); 4522 adapter->fmp = NULL; 4523 adapter->lmp = NULL; 4524 } 4525 m = NULL; 4526 } 4527 4528 /* Zero out the receive descriptors status. */ 4529 current_desc->status = 0; 4530 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4531 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4532 4533 /* Advance our pointers to the next descriptor. */ 4534 if (++i == adapter->num_rx_desc) 4535 i = 0; 4536 if (m != NULL) { 4537 adapter->next_rx_desc_to_check = i; 4538 /* Unlock for call into stack */ 4539 EM_RX_UNLOCK(adapter); 4540 (*ifp->if_input)(ifp, m); 4541 EM_RX_LOCK(adapter); 4542 i = adapter->next_rx_desc_to_check; 4543 } 4544 current_desc = &adapter->rx_desc_base[i]; 4545 } 4546 adapter->next_rx_desc_to_check = i; 4547 4548 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 4549 if (--i < 0) 4550 i = adapter->num_rx_desc - 1; 4551 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 4552 EM_RX_UNLOCK(adapter); 4553 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4554 return (0); 4555 4556 return (1); 4557 } 4558 4559 #ifndef __NO_STRICT_ALIGNMENT 4560 /* 4561 * When jumbo frames are enabled we should realign entire payload on 4562 * architecures with strict alignment. This is serious design mistake of 8254x 4563 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 4564 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 4565 * payload. On architecures without strict alignment restrictions 8254x still 4566 * performs unaligned memory access which would reduce the performance too. 4567 * To avoid copying over an entire frame to align, we allocate a new mbuf and 4568 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 4569 * existing mbuf chain. 4570 * 4571 * Be aware, best performance of the 8254x is achived only when jumbo frame is 4572 * not used at all on architectures with strict alignment. 4573 */ 4574 static int 4575 em_fixup_rx(struct adapter *adapter) 4576 { 4577 struct mbuf *m, *n; 4578 int error; 4579 4580 error = 0; 4581 m = adapter->fmp; 4582 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 4583 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 4584 m->m_data += ETHER_HDR_LEN; 4585 } else { 4586 MGETHDR(n, M_DONTWAIT, MT_DATA); 4587 if (n != NULL) { 4588 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 4589 m->m_data += ETHER_HDR_LEN; 4590 m->m_len -= ETHER_HDR_LEN; 4591 n->m_len = ETHER_HDR_LEN; 4592 M_MOVE_PKTHDR(n, m); 4593 n->m_next = m; 4594 adapter->fmp = n; 4595 } else { 4596 adapter->dropped_pkts++; 4597 m_freem(adapter->fmp); 4598 adapter->fmp = NULL; 4599 error = ENOMEM; 4600 } 4601 } 4602 4603 return (error); 4604 } 4605 #endif 4606 4607 /********************************************************************* 4608 * 4609 * Verify that the hardware indicated that the checksum is valid. 4610 * Inform the stack about the status of checksum so that stack 4611 * doesn't spend time verifying the checksum. 4612 * 4613 *********************************************************************/ 4614 static void 4615 em_receive_checksum(struct adapter *adapter, 4616 struct e1000_rx_desc *rx_desc, struct mbuf *mp) 4617 { 4618 /* 82543 or newer only */ 4619 if ((adapter->hw.mac.type < e1000_82543) || 4620 /* Ignore Checksum bit is set */ 4621 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 4622 mp->m_pkthdr.csum_flags = 0; 4623 return; 4624 } 4625 4626 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 4627 /* Did it pass? */ 4628 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 4629 /* IP Checksum Good */ 4630 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 4631 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4632 4633 } else { 4634 mp->m_pkthdr.csum_flags = 0; 4635 } 4636 } 4637 4638 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 4639 /* Did it pass? */ 4640 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 4641 mp->m_pkthdr.csum_flags |= 4642 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 4643 mp->m_pkthdr.csum_data = htons(0xffff); 4644 } 4645 } 4646 } 4647 4648 /* 4649 * This routine is run via an vlan 4650 * config EVENT 4651 */ 4652 static void 4653 em_register_vlan(void *unused, struct ifnet *ifp, u16 vtag) 4654 { 4655 struct adapter *adapter = ifp->if_softc; 4656 u32 ctrl, rctl, index, vfta; 4657 4658 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 4659 ctrl |= E1000_CTRL_VME; 4660 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 4661 4662 /* Setup for Hardware Filter */ 4663 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 4664 rctl |= E1000_RCTL_VFE; 4665 rctl &= ~E1000_RCTL_CFIEN; 4666 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 4667 4668 /* Make entry in the hardware filter table */ 4669 index = ((vtag >> 5) & 0x7F); 4670 vfta = E1000_READ_REG_ARRAY(&adapter->hw, E1000_VFTA, index); 4671 vfta |= (1 << (vtag & 0x1F)); 4672 E1000_WRITE_REG_ARRAY(&adapter->hw, E1000_VFTA, index, vfta); 4673 4674 /* Update the frame size */ 4675 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, 4676 adapter->max_frame_size + VLAN_TAG_SIZE); 4677 4678 } 4679 4680 /* 4681 * This routine is run via an vlan 4682 * unconfig EVENT 4683 */ 4684 static void 4685 em_unregister_vlan(void *unused, struct ifnet *ifp, u16 vtag) 4686 { 4687 struct adapter *adapter = ifp->if_softc; 4688 u32 index, vfta; 4689 4690 /* Remove entry in the hardware filter table */ 4691 index = ((vtag >> 5) & 0x7F); 4692 vfta = E1000_READ_REG_ARRAY(&adapter->hw, E1000_VFTA, index); 4693 vfta &= ~(1 << (vtag & 0x1F)); 4694 E1000_WRITE_REG_ARRAY(&adapter->hw, E1000_VFTA, index, vfta); 4695 /* Have all vlans unregistered? */ 4696 if (adapter->ifp->if_vlantrunk == NULL) { 4697 u32 rctl; 4698 /* Turn off the filter table */ 4699 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 4700 rctl &= ~E1000_RCTL_VFE; 4701 rctl |= E1000_RCTL_CFIEN; 4702 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 4703 /* Reset the frame size */ 4704 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, 4705 adapter->max_frame_size); 4706 } 4707 } 4708 4709 static void 4710 em_enable_intr(struct adapter *adapter) 4711 { 4712 struct e1000_hw *hw = &adapter->hw; 4713 u32 ims_mask = IMS_ENABLE_MASK; 4714 4715 if (adapter->msix) { 4716 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 4717 ims_mask |= EM_MSIX_MASK; 4718 } 4719 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4720 } 4721 4722 static void 4723 em_disable_intr(struct adapter *adapter) 4724 { 4725 struct e1000_hw *hw = &adapter->hw; 4726 4727 if (adapter->msix) 4728 E1000_WRITE_REG(hw, EM_EIAC, 0); 4729 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 4730 } 4731 4732 /* 4733 * Bit of a misnomer, what this really means is 4734 * to enable OS management of the system... aka 4735 * to disable special hardware management features 4736 */ 4737 static void 4738 em_init_manageability(struct adapter *adapter) 4739 { 4740 /* A shared code workaround */ 4741 #define E1000_82542_MANC2H E1000_MANC2H 4742 if (adapter->has_manage) { 4743 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 4744 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4745 4746 /* disable hardware interception of ARP */ 4747 manc &= ~(E1000_MANC_ARP_EN); 4748 4749 /* enable receiving management packets to the host */ 4750 if (adapter->hw.mac.type >= e1000_82571) { 4751 manc |= E1000_MANC_EN_MNG2HOST; 4752 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4753 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4754 manc2h |= E1000_MNG2HOST_PORT_623; 4755 manc2h |= E1000_MNG2HOST_PORT_664; 4756 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 4757 } 4758 4759 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4760 } 4761 } 4762 4763 /* 4764 * Give control back to hardware management 4765 * controller if there is one. 4766 */ 4767 static void 4768 em_release_manageability(struct adapter *adapter) 4769 { 4770 if (adapter->has_manage) { 4771 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4772 4773 /* re-enable hardware interception of ARP */ 4774 manc |= E1000_MANC_ARP_EN; 4775 4776 if (adapter->hw.mac.type >= e1000_82571) 4777 manc &= ~E1000_MANC_EN_MNG2HOST; 4778 4779 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4780 } 4781 } 4782 4783 /* 4784 * em_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4785 * For ASF and Pass Through versions of f/w this means that 4786 * the driver is loaded. For AMT version (only with 82573) 4787 * of the f/w this means that the network i/f is open. 4788 * 4789 */ 4790 static void 4791 em_get_hw_control(struct adapter *adapter) 4792 { 4793 u32 ctrl_ext, swsm; 4794 4795 /* Let firmware know the driver has taken over */ 4796 switch (adapter->hw.mac.type) { 4797 case e1000_82573: 4798 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4799 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4800 swsm | E1000_SWSM_DRV_LOAD); 4801 break; 4802 case e1000_82571: 4803 case e1000_82572: 4804 case e1000_80003es2lan: 4805 case e1000_ich8lan: 4806 case e1000_ich9lan: 4807 case e1000_ich10lan: 4808 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4809 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4810 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4811 break; 4812 default: 4813 break; 4814 } 4815 } 4816 4817 /* 4818 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4819 * For ASF and Pass Through versions of f/w this means that the 4820 * driver is no longer loaded. For AMT version (only with 82573) i 4821 * of the f/w this means that the network i/f is closed. 4822 * 4823 */ 4824 static void 4825 em_release_hw_control(struct adapter *adapter) 4826 { 4827 u32 ctrl_ext, swsm; 4828 4829 /* Let firmware taken over control of h/w */ 4830 switch (adapter->hw.mac.type) { 4831 case e1000_82573: 4832 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4833 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4834 swsm & ~E1000_SWSM_DRV_LOAD); 4835 break; 4836 case e1000_82571: 4837 case e1000_82572: 4838 case e1000_80003es2lan: 4839 case e1000_ich8lan: 4840 case e1000_ich9lan: 4841 case e1000_ich10lan: 4842 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4843 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4844 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4845 break; 4846 default: 4847 break; 4848 4849 } 4850 } 4851 4852 static int 4853 em_is_valid_ether_addr(u8 *addr) 4854 { 4855 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4856 4857 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4858 return (FALSE); 4859 } 4860 4861 return (TRUE); 4862 } 4863 4864 /* 4865 * Enable PCI Wake On Lan capability 4866 */ 4867 void 4868 em_enable_wakeup(device_t dev) 4869 { 4870 u16 cap, status; 4871 u8 id; 4872 4873 /* First find the capabilities pointer*/ 4874 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 4875 /* Read the PM Capabilities */ 4876 id = pci_read_config(dev, cap, 1); 4877 if (id != PCIY_PMG) /* Something wrong */ 4878 return; 4879 /* OK, we have the power capabilities, so 4880 now get the status register */ 4881 cap += PCIR_POWER_STATUS; 4882 status = pci_read_config(dev, cap, 2); 4883 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4884 pci_write_config(dev, cap, status, 2); 4885 return; 4886 } 4887 4888 4889 /********************************************************************* 4890 * 82544 Coexistence issue workaround. 4891 * There are 2 issues. 4892 * 1. Transmit Hang issue. 4893 * To detect this issue, following equation can be used... 4894 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4895 * If SUM[3:0] is in between 1 to 4, we will have this issue. 4896 * 4897 * 2. DAC issue. 4898 * To detect this issue, following equation can be used... 4899 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4900 * If SUM[3:0] is in between 9 to c, we will have this issue. 4901 * 4902 * 4903 * WORKAROUND: 4904 * Make sure we do not have ending address 4905 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 4906 * 4907 *************************************************************************/ 4908 static u32 4909 em_fill_descriptors (bus_addr_t address, u32 length, 4910 PDESC_ARRAY desc_array) 4911 { 4912 u32 safe_terminator; 4913 4914 /* Since issue is sensitive to length and address.*/ 4915 /* Let us first check the address...*/ 4916 if (length <= 4) { 4917 desc_array->descriptor[0].address = address; 4918 desc_array->descriptor[0].length = length; 4919 desc_array->elements = 1; 4920 return (desc_array->elements); 4921 } 4922 safe_terminator = (u32)((((u32)address & 0x7) + 4923 (length & 0xF)) & 0xF); 4924 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 4925 if (safe_terminator == 0 || 4926 (safe_terminator > 4 && 4927 safe_terminator < 9) || 4928 (safe_terminator > 0xC && 4929 safe_terminator <= 0xF)) { 4930 desc_array->descriptor[0].address = address; 4931 desc_array->descriptor[0].length = length; 4932 desc_array->elements = 1; 4933 return (desc_array->elements); 4934 } 4935 4936 desc_array->descriptor[0].address = address; 4937 desc_array->descriptor[0].length = length - 4; 4938 desc_array->descriptor[1].address = address + (length - 4); 4939 desc_array->descriptor[1].length = 4; 4940 desc_array->elements = 2; 4941 return (desc_array->elements); 4942 } 4943 4944 /********************************************************************** 4945 * 4946 * Update the board statistics counters. 4947 * 4948 **********************************************************************/ 4949 static void 4950 em_update_stats_counters(struct adapter *adapter) 4951 { 4952 struct ifnet *ifp; 4953 4954 if(adapter->hw.phy.media_type == e1000_media_type_copper || 4955 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4956 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4957 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4958 } 4959 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4960 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4961 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4962 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4963 4964 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4965 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4966 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4967 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4968 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4969 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4970 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4971 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4972 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4973 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4974 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4975 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4976 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4977 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4978 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4979 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4980 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4981 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4982 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4983 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4984 4985 /* For the 64-bit byte counters the low dword must be read first. */ 4986 /* Both registers clear on the read of the high dword */ 4987 4988 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 4989 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 4990 4991 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4992 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4993 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4994 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4995 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4996 4997 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4998 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4999 5000 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 5001 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 5002 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 5003 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 5004 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 5005 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 5006 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 5007 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 5008 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 5009 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 5010 5011 if (adapter->hw.mac.type >= e1000_82543) { 5012 adapter->stats.algnerrc += 5013 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 5014 adapter->stats.rxerrc += 5015 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 5016 adapter->stats.tncrs += 5017 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 5018 adapter->stats.cexterr += 5019 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 5020 adapter->stats.tsctc += 5021 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 5022 adapter->stats.tsctfc += 5023 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 5024 } 5025 ifp = adapter->ifp; 5026 5027 ifp->if_collisions = adapter->stats.colc; 5028 5029 /* Rx Errors */ 5030 ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + 5031 adapter->stats.crcerrs + adapter->stats.algnerrc + 5032 adapter->stats.ruc + adapter->stats.roc + 5033 adapter->stats.mpc + adapter->stats.cexterr; 5034 5035 /* Tx Errors */ 5036 ifp->if_oerrors = adapter->stats.ecol + 5037 adapter->stats.latecol + adapter->watchdog_events; 5038 } 5039 5040 5041 /********************************************************************** 5042 * 5043 * This routine is called only when em_display_debug_stats is enabled. 5044 * This routine provides a way to take a look at important statistics 5045 * maintained by the driver and hardware. 5046 * 5047 **********************************************************************/ 5048 static void 5049 em_print_debug_info(struct adapter *adapter) 5050 { 5051 device_t dev = adapter->dev; 5052 u8 *hw_addr = adapter->hw.hw_addr; 5053 5054 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 5055 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 5056 E1000_READ_REG(&adapter->hw, E1000_CTRL), 5057 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 5058 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 5059 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 5060 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 5061 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 5062 adapter->hw.fc.high_water, 5063 adapter->hw.fc.low_water); 5064 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 5065 E1000_READ_REG(&adapter->hw, E1000_TIDV), 5066 E1000_READ_REG(&adapter->hw, E1000_TADV)); 5067 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 5068 E1000_READ_REG(&adapter->hw, E1000_RDTR), 5069 E1000_READ_REG(&adapter->hw, E1000_RADV)); 5070 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 5071 (long long)adapter->tx_fifo_wrk_cnt, 5072 (long long)adapter->tx_fifo_reset_cnt); 5073 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5074 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 5075 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 5076 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5077 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 5078 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 5079 device_printf(dev, "Num Tx descriptors avail = %d\n", 5080 adapter->num_tx_desc_avail); 5081 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 5082 adapter->no_tx_desc_avail1); 5083 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 5084 adapter->no_tx_desc_avail2); 5085 device_printf(dev, "Std mbuf failed = %ld\n", 5086 adapter->mbuf_alloc_failed); 5087 device_printf(dev, "Std mbuf cluster failed = %ld\n", 5088 adapter->mbuf_cluster_failed); 5089 device_printf(dev, "Driver dropped packets = %ld\n", 5090 adapter->dropped_pkts); 5091 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 5092 adapter->no_tx_dma_setup); 5093 } 5094 5095 static void 5096 em_print_hw_stats(struct adapter *adapter) 5097 { 5098 device_t dev = adapter->dev; 5099 5100 device_printf(dev, "Excessive collisions = %lld\n", 5101 (long long)adapter->stats.ecol); 5102 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 5103 device_printf(dev, "Symbol errors = %lld\n", 5104 (long long)adapter->stats.symerrs); 5105 #endif 5106 device_printf(dev, "Sequence errors = %lld\n", 5107 (long long)adapter->stats.sec); 5108 device_printf(dev, "Defer count = %lld\n", 5109 (long long)adapter->stats.dc); 5110 device_printf(dev, "Missed Packets = %lld\n", 5111 (long long)adapter->stats.mpc); 5112 device_printf(dev, "Receive No Buffers = %lld\n", 5113 (long long)adapter->stats.rnbc); 5114 /* RLEC is inaccurate on some hardware, calculate our own. */ 5115 device_printf(dev, "Receive Length Errors = %lld\n", 5116 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 5117 device_printf(dev, "Receive errors = %lld\n", 5118 (long long)adapter->stats.rxerrc); 5119 device_printf(dev, "Crc errors = %lld\n", 5120 (long long)adapter->stats.crcerrs); 5121 device_printf(dev, "Alignment errors = %lld\n", 5122 (long long)adapter->stats.algnerrc); 5123 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 5124 (long long)adapter->stats.cexterr); 5125 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 5126 device_printf(dev, "watchdog timeouts = %ld\n", 5127 adapter->watchdog_events); 5128 device_printf(dev, "RX MSIX IRQ = %ld TX MSIX IRQ = %ld" 5129 " LINK MSIX IRQ = %ld\n", adapter->rx_irq, 5130 adapter->tx_irq , adapter->link_irq); 5131 device_printf(dev, "XON Rcvd = %lld\n", 5132 (long long)adapter->stats.xonrxc); 5133 device_printf(dev, "XON Xmtd = %lld\n", 5134 (long long)adapter->stats.xontxc); 5135 device_printf(dev, "XOFF Rcvd = %lld\n", 5136 (long long)adapter->stats.xoffrxc); 5137 device_printf(dev, "XOFF Xmtd = %lld\n", 5138 (long long)adapter->stats.xofftxc); 5139 device_printf(dev, "Good Packets Rcvd = %lld\n", 5140 (long long)adapter->stats.gprc); 5141 device_printf(dev, "Good Packets Xmtd = %lld\n", 5142 (long long)adapter->stats.gptc); 5143 device_printf(dev, "TSO Contexts Xmtd = %lld\n", 5144 (long long)adapter->stats.tsctc); 5145 device_printf(dev, "TSO Contexts Failed = %lld\n", 5146 (long long)adapter->stats.tsctfc); 5147 } 5148 5149 /********************************************************************** 5150 * 5151 * This routine provides a way to dump out the adapter eeprom, 5152 * often a useful debug/service tool. This only dumps the first 5153 * 32 words, stuff that matters is in that extent. 5154 * 5155 **********************************************************************/ 5156 static void 5157 em_print_nvm_info(struct adapter *adapter) 5158 { 5159 u16 eeprom_data; 5160 int i, j, row = 0; 5161 5162 /* Its a bit crude, but it gets the job done */ 5163 printf("\nInterface EEPROM Dump:\n"); 5164 printf("Offset\n0x0000 "); 5165 for (i = 0, j = 0; i < 32; i++, j++) { 5166 if (j == 8) { /* Make the offset block */ 5167 j = 0; ++row; 5168 printf("\n0x00%x0 ",row); 5169 } 5170 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 5171 printf("%04x ", eeprom_data); 5172 } 5173 printf("\n"); 5174 } 5175 5176 static int 5177 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5178 { 5179 struct adapter *adapter; 5180 int error; 5181 int result; 5182 5183 result = -1; 5184 error = sysctl_handle_int(oidp, &result, 0, req); 5185 5186 if (error || !req->newptr) 5187 return (error); 5188 5189 if (result == 1) { 5190 adapter = (struct adapter *)arg1; 5191 em_print_debug_info(adapter); 5192 } 5193 /* 5194 * This value will cause a hex dump of the 5195 * first 32 16-bit words of the EEPROM to 5196 * the screen. 5197 */ 5198 if (result == 2) { 5199 adapter = (struct adapter *)arg1; 5200 em_print_nvm_info(adapter); 5201 } 5202 5203 return (error); 5204 } 5205 5206 5207 static int 5208 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 5209 { 5210 struct adapter *adapter; 5211 int error; 5212 int result; 5213 5214 result = -1; 5215 error = sysctl_handle_int(oidp, &result, 0, req); 5216 5217 if (error || !req->newptr) 5218 return (error); 5219 5220 if (result == 1) { 5221 adapter = (struct adapter *)arg1; 5222 em_print_hw_stats(adapter); 5223 } 5224 5225 return (error); 5226 } 5227 5228 static int 5229 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5230 { 5231 struct em_int_delay_info *info; 5232 struct adapter *adapter; 5233 u32 regval; 5234 int error; 5235 int usecs; 5236 int ticks; 5237 5238 info = (struct em_int_delay_info *)arg1; 5239 usecs = info->value; 5240 error = sysctl_handle_int(oidp, &usecs, 0, req); 5241 if (error != 0 || req->newptr == NULL) 5242 return (error); 5243 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5244 return (EINVAL); 5245 info->value = usecs; 5246 ticks = EM_USECS_TO_TICKS(usecs); 5247 5248 adapter = info->adapter; 5249 5250 EM_CORE_LOCK(adapter); 5251 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 5252 regval = (regval & ~0xffff) | (ticks & 0xffff); 5253 /* Handle a few special cases. */ 5254 switch (info->offset) { 5255 case E1000_RDTR: 5256 break; 5257 case E1000_TIDV: 5258 if (ticks == 0) { 5259 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 5260 /* Don't write 0 into the TIDV register. */ 5261 regval++; 5262 } else 5263 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 5264 break; 5265 } 5266 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 5267 EM_CORE_UNLOCK(adapter); 5268 return (0); 5269 } 5270 5271 static void 5272 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 5273 const char *description, struct em_int_delay_info *info, 5274 int offset, int value) 5275 { 5276 info->adapter = adapter; 5277 info->offset = offset; 5278 info->value = value; 5279 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 5280 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5281 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5282 info, 0, em_sysctl_int_delay, "I", description); 5283 } 5284 5285 #ifndef EM_LEGACY_IRQ 5286 static void 5287 em_add_rx_process_limit(struct adapter *adapter, const char *name, 5288 const char *description, int *limit, int value) 5289 { 5290 *limit = value; 5291 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 5292 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5293 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 5294 } 5295 #endif 5296 5297 #ifdef EM_TIMESYNC 5298 /* 5299 * Initialize the Time Sync Feature 5300 */ 5301 static int 5302 em_tsync_init(struct adapter *adapter) 5303 { 5304 device_t dev = adapter->dev; 5305 u32 tx_ctl, rx_ctl; 5306 5307 5308 E1000_WRITE_REG(&adapter->hw, E1000_TIMINCA, (1<<24) | 5309 20833/PICOSECS_PER_TICK); 5310 5311 adapter->last_stamp = E1000_READ_REG(&adapter->hw, E1000_SYSTIML); 5312 adapter->last_stamp |= (u64)E1000_READ_REG(&adapter->hw, 5313 E1000_SYSTIMH) << 32ULL; 5314 5315 /* Enable the TX side */ 5316 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5317 tx_ctl |= 0x10; 5318 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCTXCTL, tx_ctl); 5319 E1000_WRITE_FLUSH(&adapter->hw); 5320 5321 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5322 if ((tx_ctl & 0x10) == 0) { 5323 device_printf(dev, "Failed to enable TX timestamping\n"); 5324 return (ENXIO); 5325 } 5326 5327 /* Enable RX */ 5328 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5329 rx_ctl |= 0x10; /* Enable the feature */ 5330 rx_ctl |= 0x0a; /* This value turns on Ver 1 and 2 */ 5331 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCRXCTL, rx_ctl); 5332 5333 /* 5334 * Ethertype Stamping (Ethertype = 0x88F7) 5335 */ 5336 E1000_WRITE_REG(&adapter->hw, E1000_RXMTRL, htonl(0x440088f7)); 5337 5338 /* 5339 * Source Port Queue Filter Setup: 5340 * this is for UDP port filtering 5341 */ 5342 E1000_WRITE_REG(&adapter->hw, E1000_RXUDP, htons(TSYNC_PORT)); 5343 /* Protocol = UDP, enable Timestamp, and filter on source/protocol */ 5344 5345 E1000_WRITE_FLUSH(&adapter->hw); 5346 5347 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5348 if ((rx_ctl & 0x10) == 0) { 5349 device_printf(dev, "Failed to enable RX timestamping\n"); 5350 return (ENXIO); 5351 } 5352 5353 device_printf(dev, "IEEE 1588 Precision Time Protocol enabled\n"); 5354 5355 return (0); 5356 } 5357 5358 /* 5359 * Disable the Time Sync Feature 5360 */ 5361 static void 5362 em_tsync_disable(struct adapter *adapter) 5363 { 5364 u32 tx_ctl, rx_ctl; 5365 5366 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5367 tx_ctl &= ~0x10; 5368 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCTXCTL, tx_ctl); 5369 E1000_WRITE_FLUSH(&adapter->hw); 5370 5371 /* Invalidate TX Timestamp */ 5372 E1000_READ_REG(&adapter->hw, E1000_TXSTMPH); 5373 5374 tx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCTXCTL); 5375 if (tx_ctl & 0x10) 5376 HW_DEBUGOUT("Failed to disable TX timestamping\n"); 5377 5378 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5379 rx_ctl &= ~0x10; 5380 5381 E1000_WRITE_REG(&adapter->hw, E1000_TSYNCRXCTL, rx_ctl); 5382 E1000_WRITE_FLUSH(&adapter->hw); 5383 5384 /* Invalidate RX Timestamp */ 5385 E1000_READ_REG(&adapter->hw, E1000_RXSATRH); 5386 5387 rx_ctl = E1000_READ_REG(&adapter->hw, E1000_TSYNCRXCTL); 5388 if (rx_ctl & 0x10) 5389 HW_DEBUGOUT("Failed to disable RX timestamping\n"); 5390 5391 return; 5392 } 5393 #endif /* EM_TIMESYNC */ 5394