1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 167 /* required last entry */ 168 PVID_END 169 }; 170 171 static pci_vendor_info_t igb_vendor_info_array[] = 172 { 173 /* Intel(R) PRO/1000 Network Connection - igb */ 174 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 /********************************************************************* 218 * Function prototypes 219 *********************************************************************/ 220 static void *em_register(device_t dev); 221 static void *igb_register(device_t dev); 222 static int em_if_attach_pre(if_ctx_t ctx); 223 static int em_if_attach_post(if_ctx_t ctx); 224 static int em_if_detach(if_ctx_t ctx); 225 static int em_if_shutdown(if_ctx_t ctx); 226 static int em_if_suspend(if_ctx_t ctx); 227 static int em_if_resume(if_ctx_t ctx); 228 229 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 230 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 231 static void em_if_queues_free(if_ctx_t ctx); 232 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 234 static void em_if_init(if_ctx_t ctx); 235 static void em_if_stop(if_ctx_t ctx); 236 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 237 static int em_if_media_change(if_ctx_t ctx); 238 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 239 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 240 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 241 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 242 243 static void em_identify_hardware(if_ctx_t ctx); 244 static int em_allocate_pci_resources(if_ctx_t ctx); 245 static void em_free_pci_resources(if_ctx_t ctx); 246 static void em_reset(if_ctx_t ctx); 247 static int em_setup_interface(if_ctx_t ctx); 248 static int em_setup_msix(if_ctx_t ctx); 249 250 static void em_initialize_transmit_unit(if_ctx_t ctx); 251 static void em_initialize_receive_unit(if_ctx_t ctx); 252 253 static void em_if_enable_intr(if_ctx_t ctx); 254 static void em_if_disable_intr(if_ctx_t ctx); 255 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 256 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 257 static void em_if_multi_set(if_ctx_t ctx); 258 static void em_if_update_admin_status(if_ctx_t ctx); 259 static void em_if_debug(if_ctx_t ctx); 260 static void em_update_stats_counters(struct adapter *); 261 static void em_add_hw_stats(struct adapter *adapter); 262 static int em_if_set_promisc(if_ctx_t ctx, int flags); 263 static void em_setup_vlan_hw_support(struct adapter *); 264 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 265 static void em_print_nvm_info(struct adapter *); 266 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 267 static int em_get_rs(SYSCTL_HANDLER_ARGS); 268 static void em_print_debug_info(struct adapter *); 269 static int em_is_valid_ether_addr(u8 *); 270 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 271 static void em_add_int_delay_sysctl(struct adapter *, const char *, 272 const char *, struct em_int_delay_info *, int, int); 273 /* Management and WOL Support */ 274 static void em_init_manageability(struct adapter *); 275 static void em_release_manageability(struct adapter *); 276 static void em_get_hw_control(struct adapter *); 277 static void em_release_hw_control(struct adapter *); 278 static void em_get_wakeup(if_ctx_t ctx); 279 static void em_enable_wakeup(if_ctx_t ctx); 280 static int em_enable_phy_wakeup(struct adapter *); 281 static void em_disable_aspm(struct adapter *); 282 283 int em_intr(void *arg); 284 static void em_disable_promisc(if_ctx_t ctx); 285 286 /* MSIX handlers */ 287 static int em_if_msix_intr_assign(if_ctx_t, int); 288 static int em_msix_link(void *); 289 static void em_handle_link(void *context); 290 291 static void em_enable_vectors_82574(if_ctx_t); 292 293 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 294 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 295 static void em_if_led_func(if_ctx_t ctx, int onoff); 296 297 static int em_get_regs(SYSCTL_HANDLER_ARGS); 298 299 static void lem_smartspeed(struct adapter *adapter); 300 static void igb_configure_queues(struct adapter *adapter); 301 302 303 /********************************************************************* 304 * FreeBSD Device Interface Entry Points 305 *********************************************************************/ 306 static device_method_t em_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_register, em_register), 309 DEVMETHOD(device_probe, iflib_device_probe), 310 DEVMETHOD(device_attach, iflib_device_attach), 311 DEVMETHOD(device_detach, iflib_device_detach), 312 DEVMETHOD(device_shutdown, iflib_device_shutdown), 313 DEVMETHOD(device_suspend, iflib_device_suspend), 314 DEVMETHOD(device_resume, iflib_device_resume), 315 DEVMETHOD_END 316 }; 317 318 static device_method_t igb_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_register, igb_register), 321 DEVMETHOD(device_probe, iflib_device_probe), 322 DEVMETHOD(device_attach, iflib_device_attach), 323 DEVMETHOD(device_detach, iflib_device_detach), 324 DEVMETHOD(device_shutdown, iflib_device_shutdown), 325 DEVMETHOD(device_suspend, iflib_device_suspend), 326 DEVMETHOD(device_resume, iflib_device_resume), 327 DEVMETHOD_END 328 }; 329 330 331 static driver_t em_driver = { 332 "em", em_methods, sizeof(struct adapter), 333 }; 334 335 static devclass_t em_devclass; 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 337 338 MODULE_DEPEND(em, pci, 1, 1, 1); 339 MODULE_DEPEND(em, ether, 1, 1, 1); 340 MODULE_DEPEND(em, iflib, 1, 1, 1); 341 342 static driver_t igb_driver = { 343 "igb", igb_methods, sizeof(struct adapter), 344 }; 345 346 static devclass_t igb_devclass; 347 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 348 349 MODULE_DEPEND(igb, pci, 1, 1, 1); 350 MODULE_DEPEND(igb, ether, 1, 1, 1); 351 MODULE_DEPEND(igb, iflib, 1, 1, 1); 352 353 354 static device_method_t em_if_methods[] = { 355 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 356 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 357 DEVMETHOD(ifdi_detach, em_if_detach), 358 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 359 DEVMETHOD(ifdi_suspend, em_if_suspend), 360 DEVMETHOD(ifdi_resume, em_if_resume), 361 DEVMETHOD(ifdi_init, em_if_init), 362 DEVMETHOD(ifdi_stop, em_if_stop), 363 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 364 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 365 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 366 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 367 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 368 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 369 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 370 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 371 DEVMETHOD(ifdi_media_status, em_if_media_status), 372 DEVMETHOD(ifdi_media_change, em_if_media_change), 373 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 374 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 375 DEVMETHOD(ifdi_timer, em_if_timer), 376 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 377 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 378 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 379 DEVMETHOD(ifdi_led_func, em_if_led_func), 380 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 381 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 382 DEVMETHOD(ifdi_debug, em_if_debug), 383 DEVMETHOD_END 384 }; 385 386 /* 387 * note that if (adapter->msix_mem) is replaced by: 388 * if (adapter->intr_type == IFLIB_INTR_MSIX) 389 */ 390 static driver_t em_if_driver = { 391 "em_if", em_if_methods, sizeof(struct adapter) 392 }; 393 394 /********************************************************************* 395 * Tunable default values. 396 *********************************************************************/ 397 398 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 399 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 400 #define M_TSO_LEN 66 401 402 #define MAX_INTS_PER_SEC 8000 403 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 404 405 /* Allow common code without TSO */ 406 #ifndef CSUM_TSO 407 #define CSUM_TSO 0 408 #endif 409 410 #define TSO_WORKAROUND 4 411 412 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 413 414 static int em_disable_crc_stripping = 0; 415 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 416 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 417 418 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 419 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 420 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 421 0, "Default transmit interrupt delay in usecs"); 422 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 423 0, "Default receive interrupt delay in usecs"); 424 425 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 426 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 427 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 428 &em_tx_abs_int_delay_dflt, 0, 429 "Default transmit interrupt delay limit in usecs"); 430 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 431 &em_rx_abs_int_delay_dflt, 0, 432 "Default receive interrupt delay limit in usecs"); 433 434 static int em_smart_pwr_down = FALSE; 435 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 436 0, "Set to true to leave smart power down enabled on newer adapters"); 437 438 /* Controls whether promiscuous also shows bad packets */ 439 static int em_debug_sbp = TRUE; 440 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 441 "Show bad packets in promiscuous mode"); 442 443 /* How many packets rxeof tries to clean at a time */ 444 static int em_rx_process_limit = 100; 445 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 446 &em_rx_process_limit, 0, 447 "Maximum number of received packets to process " 448 "at a time, -1 means unlimited"); 449 450 /* Energy efficient ethernet - default to OFF */ 451 static int eee_setting = 1; 452 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 453 "Enable Energy Efficient Ethernet"); 454 455 /* 456 ** Tuneable Interrupt rate 457 */ 458 static int em_max_interrupt_rate = 8000; 459 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 460 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 461 462 463 464 /* Global used in WOL setup with multiport cards */ 465 static int global_quad_port_a = 0; 466 467 extern struct if_txrx igb_txrx; 468 extern struct if_txrx em_txrx; 469 extern struct if_txrx lem_txrx; 470 471 static struct if_shared_ctx em_sctx_init = { 472 .isc_magic = IFLIB_MAGIC, 473 .isc_q_align = PAGE_SIZE, 474 .isc_tx_maxsize = EM_TSO_SIZE, 475 .isc_tx_maxsegsize = PAGE_SIZE, 476 .isc_rx_maxsize = MJUM9BYTES, 477 .isc_rx_nsegments = 1, 478 .isc_rx_maxsegsize = MJUM9BYTES, 479 .isc_nfl = 1, 480 .isc_nrxqs = 1, 481 .isc_ntxqs = 1, 482 .isc_admin_intrcnt = 1, 483 .isc_vendor_info = em_vendor_info_array, 484 .isc_driver_version = em_driver_version, 485 .isc_driver = &em_if_driver, 486 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 487 488 .isc_nrxd_min = {EM_MIN_RXD}, 489 .isc_ntxd_min = {EM_MIN_TXD}, 490 .isc_nrxd_max = {EM_MAX_RXD}, 491 .isc_ntxd_max = {EM_MAX_TXD}, 492 .isc_nrxd_default = {EM_DEFAULT_RXD}, 493 .isc_ntxd_default = {EM_DEFAULT_TXD}, 494 }; 495 496 if_shared_ctx_t em_sctx = &em_sctx_init; 497 498 499 static struct if_shared_ctx igb_sctx_init = { 500 .isc_magic = IFLIB_MAGIC, 501 .isc_q_align = PAGE_SIZE, 502 .isc_tx_maxsize = EM_TSO_SIZE, 503 .isc_tx_maxsegsize = PAGE_SIZE, 504 .isc_rx_maxsize = MJUM9BYTES, 505 .isc_rx_nsegments = 1, 506 .isc_rx_maxsegsize = MJUM9BYTES, 507 .isc_nfl = 1, 508 .isc_nrxqs = 1, 509 .isc_ntxqs = 1, 510 .isc_admin_intrcnt = 1, 511 .isc_vendor_info = igb_vendor_info_array, 512 .isc_driver_version = em_driver_version, 513 .isc_driver = &em_if_driver, 514 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 515 516 .isc_nrxd_min = {EM_MIN_RXD}, 517 .isc_ntxd_min = {EM_MIN_TXD}, 518 .isc_nrxd_max = {EM_MAX_RXD}, 519 .isc_ntxd_max = {EM_MAX_TXD}, 520 .isc_nrxd_default = {EM_DEFAULT_RXD}, 521 .isc_ntxd_default = {EM_DEFAULT_TXD}, 522 }; 523 524 if_shared_ctx_t igb_sctx = &igb_sctx_init; 525 526 /***************************************************************** 527 * 528 * Dump Registers 529 * 530 ****************************************************************/ 531 #define IGB_REGS_LEN 739 532 533 static int em_get_regs(SYSCTL_HANDLER_ARGS) 534 { 535 struct adapter *adapter = (struct adapter *)arg1; 536 struct e1000_hw *hw = &adapter->hw; 537 538 struct sbuf *sb; 539 u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT); 540 int rc; 541 542 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 543 544 rc = sysctl_wire_old_buffer(req, 0); 545 MPASS(rc == 0); 546 if (rc != 0) 547 return (rc); 548 549 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 550 MPASS(sb != NULL); 551 if (sb == NULL) 552 return (ENOMEM); 553 554 /* General Registers */ 555 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 556 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 557 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 558 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 559 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 560 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 561 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 562 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 563 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 564 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 565 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 566 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 567 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 568 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 569 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 570 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 571 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 572 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 573 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 574 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 575 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 576 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 577 578 sbuf_printf(sb, "General Registers\n"); 579 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 580 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 581 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 582 583 sbuf_printf(sb, "Interrupt Registers\n"); 584 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 585 586 sbuf_printf(sb, "RX Registers\n"); 587 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 588 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 589 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 590 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 591 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 592 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 593 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 594 595 sbuf_printf(sb, "TX Registers\n"); 596 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 597 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 598 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 599 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 600 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 601 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 602 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 603 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 604 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 605 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 606 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 607 608 #ifdef DUMP_DESCS 609 { 610 if_softc_ctx_t scctx = adapter->shared; 611 struct rx_ring *rxr = &rx_que->rxr; 612 struct tx_ring *txr = &tx_que->txr; 613 int ntxd = scctx->isc_ntxd[0]; 614 int nrxd = scctx->isc_nrxd[0]; 615 int j; 616 617 for (j = 0; j < nrxd; j++) { 618 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 619 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 620 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 621 } 622 623 for (j = 0; j < min(ntxd, 256); j++) { 624 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 625 626 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 627 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 628 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 629 630 } 631 } 632 #endif 633 634 rc = sbuf_finish(sb); 635 sbuf_delete(sb); 636 return(rc); 637 } 638 639 static void * 640 em_register(device_t dev) 641 { 642 return (em_sctx); 643 } 644 645 static void * 646 igb_register(device_t dev) 647 { 648 return (igb_sctx); 649 } 650 651 static int 652 em_set_num_queues(if_ctx_t ctx) 653 { 654 struct adapter *adapter = iflib_get_softc(ctx); 655 int maxqueues; 656 657 /* Sanity check based on HW */ 658 switch (adapter->hw.mac.type) { 659 case e1000_82576: 660 case e1000_82580: 661 case e1000_i350: 662 case e1000_i354: 663 maxqueues = 8; 664 break; 665 case e1000_i210: 666 case e1000_82575: 667 maxqueues = 4; 668 break; 669 case e1000_i211: 670 case e1000_82574: 671 maxqueues = 2; 672 break; 673 default: 674 maxqueues = 1; 675 break; 676 } 677 678 return (maxqueues); 679 } 680 681 682 #define EM_CAPS \ 683 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 684 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 685 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 686 687 #define IGB_CAPS \ 688 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 689 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 690 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 691 692 /********************************************************************* 693 * Device initialization routine 694 * 695 * The attach entry point is called when the driver is being loaded. 696 * This routine identifies the type of hardware, allocates all resources 697 * and initializes the hardware. 698 * 699 * return 0 on success, positive on failure 700 *********************************************************************/ 701 702 static int 703 em_if_attach_pre(if_ctx_t ctx) 704 { 705 struct adapter *adapter; 706 if_softc_ctx_t scctx; 707 device_t dev; 708 struct e1000_hw *hw; 709 int error = 0; 710 711 INIT_DEBUGOUT("em_if_attach_pre begin"); 712 dev = iflib_get_dev(ctx); 713 adapter = iflib_get_softc(ctx); 714 715 if (resource_disabled("em", device_get_unit(dev))) { 716 device_printf(dev, "Disabled by device hint\n"); 717 return (ENXIO); 718 } 719 720 adapter->ctx = ctx; 721 adapter->dev = adapter->osdep.dev = dev; 722 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 723 adapter->media = iflib_get_media(ctx); 724 hw = &adapter->hw; 725 726 adapter->tx_process_limit = scctx->isc_ntxd[0]; 727 728 /* SYSCTL stuff */ 729 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 730 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 731 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 732 em_sysctl_nvm_info, "I", "NVM Information"); 733 734 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 735 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 736 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 737 em_sysctl_debug_info, "I", "Debug Information"); 738 739 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 740 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 741 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 742 em_set_flowcntl, "I", "Flow Control"); 743 744 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 745 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 746 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 747 em_get_regs, "A", "Dump Registers"); 748 749 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 751 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 752 em_get_rs, "I", "Dump RS indexes"); 753 754 /* Determine hardware and mac info */ 755 em_identify_hardware(ctx); 756 757 /* Set isc_msix_bar */ 758 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 759 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 760 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 761 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 762 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 763 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 764 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 765 766 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 767 768 769 if (adapter->hw.mac.type >= igb_mac_min) { 770 int try_second_bar; 771 772 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 773 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 774 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 775 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 776 scctx->isc_txrx = &igb_txrx; 777 scctx->isc_capenable = IGB_CAPS; 778 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 779 | CSUM_IP6_UDP | CSUM_IP6_TCP; 780 if (adapter->hw.mac.type != e1000_82575) 781 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 782 783 /* 784 ** Some new devices, as with ixgbe, now may 785 ** use a different BAR, so we need to keep 786 ** track of which is used. 787 */ 788 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 789 if (try_second_bar == 0) 790 scctx->isc_msix_bar += 4; 791 792 } else if (adapter->hw.mac.type >= em_mac_min) { 793 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 794 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 795 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 796 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 797 scctx->isc_txrx = &em_txrx; 798 scctx->isc_capenable = EM_CAPS; 799 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 800 } else { 801 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 802 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 803 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 804 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 805 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 806 scctx->isc_txrx = &lem_txrx; 807 scctx->isc_capenable = EM_CAPS; 808 if (adapter->hw.mac.type < e1000_82543) 809 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 810 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 811 scctx->isc_msix_bar = 0; 812 } 813 814 /* Setup PCI resources */ 815 if (em_allocate_pci_resources(ctx)) { 816 device_printf(dev, "Allocation of PCI resources failed\n"); 817 error = ENXIO; 818 goto err_pci; 819 } 820 821 /* 822 ** For ICH8 and family we need to 823 ** map the flash memory, and this 824 ** must happen after the MAC is 825 ** identified 826 */ 827 if ((hw->mac.type == e1000_ich8lan) || 828 (hw->mac.type == e1000_ich9lan) || 829 (hw->mac.type == e1000_ich10lan) || 830 (hw->mac.type == e1000_pchlan) || 831 (hw->mac.type == e1000_pch2lan) || 832 (hw->mac.type == e1000_pch_lpt)) { 833 int rid = EM_BAR_TYPE_FLASH; 834 adapter->flash = bus_alloc_resource_any(dev, 835 SYS_RES_MEMORY, &rid, RF_ACTIVE); 836 if (adapter->flash == NULL) { 837 device_printf(dev, "Mapping of Flash failed\n"); 838 error = ENXIO; 839 goto err_pci; 840 } 841 /* This is used in the shared code */ 842 hw->flash_address = (u8 *)adapter->flash; 843 adapter->osdep.flash_bus_space_tag = 844 rman_get_bustag(adapter->flash); 845 adapter->osdep.flash_bus_space_handle = 846 rman_get_bushandle(adapter->flash); 847 } 848 /* 849 ** In the new SPT device flash is not a 850 ** separate BAR, rather it is also in BAR0, 851 ** so use the same tag and an offset handle for the 852 ** FLASH read/write macros in the shared code. 853 */ 854 else if (hw->mac.type == e1000_pch_spt) { 855 adapter->osdep.flash_bus_space_tag = 856 adapter->osdep.mem_bus_space_tag; 857 adapter->osdep.flash_bus_space_handle = 858 adapter->osdep.mem_bus_space_handle 859 + E1000_FLASH_BASE_ADDR; 860 } 861 862 /* Do Shared Code initialization */ 863 error = e1000_setup_init_funcs(hw, TRUE); 864 if (error) { 865 device_printf(dev, "Setup of Shared code failed, error %d\n", 866 error); 867 error = ENXIO; 868 goto err_pci; 869 } 870 871 em_setup_msix(ctx); 872 e1000_get_bus_info(hw); 873 874 /* Set up some sysctls for the tunable interrupt delays */ 875 em_add_int_delay_sysctl(adapter, "rx_int_delay", 876 "receive interrupt delay in usecs", &adapter->rx_int_delay, 877 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 878 em_add_int_delay_sysctl(adapter, "tx_int_delay", 879 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 880 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 881 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 882 "receive interrupt delay limit in usecs", 883 &adapter->rx_abs_int_delay, 884 E1000_REGISTER(hw, E1000_RADV), 885 em_rx_abs_int_delay_dflt); 886 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 887 "transmit interrupt delay limit in usecs", 888 &adapter->tx_abs_int_delay, 889 E1000_REGISTER(hw, E1000_TADV), 890 em_tx_abs_int_delay_dflt); 891 em_add_int_delay_sysctl(adapter, "itr", 892 "interrupt delay limit in usecs/4", 893 &adapter->tx_itr, 894 E1000_REGISTER(hw, E1000_ITR), 895 DEFAULT_ITR); 896 897 hw->mac.autoneg = DO_AUTO_NEG; 898 hw->phy.autoneg_wait_to_complete = FALSE; 899 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 900 901 if (adapter->hw.mac.type < em_mac_min) { 902 e1000_init_script_state_82541(&adapter->hw, TRUE); 903 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 904 } 905 /* Copper options */ 906 if (hw->phy.media_type == e1000_media_type_copper) { 907 hw->phy.mdix = AUTO_ALL_MODES; 908 hw->phy.disable_polarity_correction = FALSE; 909 hw->phy.ms_type = EM_MASTER_SLAVE; 910 } 911 912 /* 913 * Set the frame limits assuming 914 * standard ethernet sized frames. 915 */ 916 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 917 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 918 919 /* 920 * This controls when hardware reports transmit completion 921 * status. 922 */ 923 hw->mac.report_tx_early = 1; 924 925 /* Allocate multicast array memory. */ 926 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 927 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 928 if (adapter->mta == NULL) { 929 device_printf(dev, "Can not allocate multicast setup array\n"); 930 error = ENOMEM; 931 goto err_late; 932 } 933 934 /* Check SOL/IDER usage */ 935 if (e1000_check_reset_block(hw)) 936 device_printf(dev, "PHY reset is blocked" 937 " due to SOL/IDER session.\n"); 938 939 /* Sysctl for setting Energy Efficient Ethernet */ 940 hw->dev_spec.ich8lan.eee_disable = eee_setting; 941 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 942 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 943 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 944 adapter, 0, em_sysctl_eee, "I", 945 "Disable Energy Efficient Ethernet"); 946 947 /* 948 ** Start from a known state, this is 949 ** important in reading the nvm and 950 ** mac from that. 951 */ 952 e1000_reset_hw(hw); 953 954 /* Make sure we have a good EEPROM before we read from it */ 955 if (e1000_validate_nvm_checksum(hw) < 0) { 956 /* 957 ** Some PCI-E parts fail the first check due to 958 ** the link being in sleep state, call it again, 959 ** if it fails a second time its a real issue. 960 */ 961 if (e1000_validate_nvm_checksum(hw) < 0) { 962 device_printf(dev, 963 "The EEPROM Checksum Is Not Valid\n"); 964 error = EIO; 965 goto err_late; 966 } 967 } 968 969 /* Copy the permanent MAC address out of the EEPROM */ 970 if (e1000_read_mac_addr(hw) < 0) { 971 device_printf(dev, "EEPROM read error while reading MAC" 972 " address\n"); 973 error = EIO; 974 goto err_late; 975 } 976 977 if (!em_is_valid_ether_addr(hw->mac.addr)) { 978 device_printf(dev, "Invalid MAC address\n"); 979 error = EIO; 980 goto err_late; 981 } 982 983 /* Disable ULP support */ 984 e1000_disable_ulp_lpt_lp(hw, TRUE); 985 986 /* 987 * Get Wake-on-Lan and Management info for later use 988 */ 989 em_get_wakeup(ctx); 990 991 iflib_set_mac(ctx, hw->mac.addr); 992 993 return (0); 994 995 err_late: 996 em_release_hw_control(adapter); 997 err_pci: 998 em_free_pci_resources(ctx); 999 free(adapter->mta, M_DEVBUF); 1000 1001 return (error); 1002 } 1003 1004 static int 1005 em_if_attach_post(if_ctx_t ctx) 1006 { 1007 struct adapter *adapter = iflib_get_softc(ctx); 1008 struct e1000_hw *hw = &adapter->hw; 1009 int error = 0; 1010 1011 /* Setup OS specific network interface */ 1012 error = em_setup_interface(ctx); 1013 if (error != 0) { 1014 goto err_late; 1015 } 1016 1017 em_reset(ctx); 1018 1019 /* Initialize statistics */ 1020 em_update_stats_counters(adapter); 1021 hw->mac.get_link_status = 1; 1022 em_if_update_admin_status(ctx); 1023 em_add_hw_stats(adapter); 1024 1025 /* Non-AMT based hardware can now take control from firmware */ 1026 if (adapter->has_manage && !adapter->has_amt) 1027 em_get_hw_control(adapter); 1028 1029 INIT_DEBUGOUT("em_if_attach_post: end"); 1030 1031 return (error); 1032 1033 err_late: 1034 em_release_hw_control(adapter); 1035 em_free_pci_resources(ctx); 1036 em_if_queues_free(ctx); 1037 free(adapter->mta, M_DEVBUF); 1038 1039 return (error); 1040 } 1041 1042 /********************************************************************* 1043 * Device removal routine 1044 * 1045 * The detach entry point is called when the driver is being removed. 1046 * This routine stops the adapter and deallocates all the resources 1047 * that were allocated for driver operation. 1048 * 1049 * return 0 on success, positive on failure 1050 *********************************************************************/ 1051 1052 static int 1053 em_if_detach(if_ctx_t ctx) 1054 { 1055 struct adapter *adapter = iflib_get_softc(ctx); 1056 1057 INIT_DEBUGOUT("em_detach: begin"); 1058 1059 e1000_phy_hw_reset(&adapter->hw); 1060 1061 em_release_manageability(adapter); 1062 em_release_hw_control(adapter); 1063 em_free_pci_resources(ctx); 1064 1065 return (0); 1066 } 1067 1068 /********************************************************************* 1069 * 1070 * Shutdown entry point 1071 * 1072 **********************************************************************/ 1073 1074 static int 1075 em_if_shutdown(if_ctx_t ctx) 1076 { 1077 return em_if_suspend(ctx); 1078 } 1079 1080 /* 1081 * Suspend/resume device methods. 1082 */ 1083 static int 1084 em_if_suspend(if_ctx_t ctx) 1085 { 1086 struct adapter *adapter = iflib_get_softc(ctx); 1087 1088 em_release_manageability(adapter); 1089 em_release_hw_control(adapter); 1090 em_enable_wakeup(ctx); 1091 return (0); 1092 } 1093 1094 static int 1095 em_if_resume(if_ctx_t ctx) 1096 { 1097 struct adapter *adapter = iflib_get_softc(ctx); 1098 1099 if (adapter->hw.mac.type == e1000_pch2lan) 1100 e1000_resume_workarounds_pchlan(&adapter->hw); 1101 em_if_init(ctx); 1102 em_init_manageability(adapter); 1103 1104 return(0); 1105 } 1106 1107 static int 1108 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1109 { 1110 int max_frame_size; 1111 struct adapter *adapter = iflib_get_softc(ctx); 1112 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1113 1114 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1115 1116 switch (adapter->hw.mac.type) { 1117 case e1000_82571: 1118 case e1000_82572: 1119 case e1000_ich9lan: 1120 case e1000_ich10lan: 1121 case e1000_pch2lan: 1122 case e1000_pch_lpt: 1123 case e1000_pch_spt: 1124 case e1000_82574: 1125 case e1000_82583: 1126 case e1000_80003es2lan: 1127 /* 9K Jumbo Frame size */ 1128 max_frame_size = 9234; 1129 break; 1130 case e1000_pchlan: 1131 max_frame_size = 4096; 1132 break; 1133 case e1000_82542: 1134 case e1000_ich8lan: 1135 /* Adapters that do not support jumbo frames */ 1136 max_frame_size = ETHER_MAX_LEN; 1137 break; 1138 default: 1139 if (adapter->hw.mac.type >= igb_mac_min) 1140 max_frame_size = 9234; 1141 else /* lem */ 1142 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1143 } 1144 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1145 return (EINVAL); 1146 } 1147 1148 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1149 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1150 return (0); 1151 } 1152 1153 /********************************************************************* 1154 * Init entry point 1155 * 1156 * This routine is used in two ways. It is used by the stack as 1157 * init entry point in network interface structure. It is also used 1158 * by the driver as a hw/sw initialization routine to get to a 1159 * consistent state. 1160 * 1161 * return 0 on success, positive on failure 1162 **********************************************************************/ 1163 1164 static void 1165 em_if_init(if_ctx_t ctx) 1166 { 1167 struct adapter *adapter = iflib_get_softc(ctx); 1168 struct ifnet *ifp = iflib_get_ifp(ctx); 1169 struct em_tx_queue *tx_que; 1170 int i; 1171 INIT_DEBUGOUT("em_if_init: begin"); 1172 1173 /* Get the latest mac address, User can use a LAA */ 1174 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1175 ETHER_ADDR_LEN); 1176 1177 /* Put the address into the Receive Address Array */ 1178 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1179 1180 /* 1181 * With the 82571 adapter, RAR[0] may be overwritten 1182 * when the other port is reset, we make a duplicate 1183 * in RAR[14] for that eventuality, this assures 1184 * the interface continues to function. 1185 */ 1186 if (adapter->hw.mac.type == e1000_82571) { 1187 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1188 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1189 E1000_RAR_ENTRIES - 1); 1190 } 1191 1192 1193 /* Initialize the hardware */ 1194 em_reset(ctx); 1195 em_if_update_admin_status(ctx); 1196 1197 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1198 struct tx_ring *txr = &tx_que->txr; 1199 1200 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1201 } 1202 1203 /* Setup VLAN support, basic and offload if available */ 1204 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1205 1206 /* Clear bad data from Rx FIFOs */ 1207 if (adapter->hw.mac.type >= igb_mac_min) 1208 e1000_rx_fifo_flush_82575(&adapter->hw); 1209 1210 /* Configure for OS presence */ 1211 em_init_manageability(adapter); 1212 1213 /* Prepare transmit descriptors and buffers */ 1214 em_initialize_transmit_unit(ctx); 1215 1216 /* Setup Multicast table */ 1217 em_if_multi_set(ctx); 1218 1219 /* 1220 * Figure out the desired mbuf 1221 * pool for doing jumbos 1222 */ 1223 if (adapter->hw.mac.max_frame_size <= 2048) 1224 adapter->rx_mbuf_sz = MCLBYTES; 1225 #ifndef CONTIGMALLOC_WORKS 1226 else 1227 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1228 #else 1229 else if (adapter->hw.mac.max_frame_size <= 4096) 1230 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1231 else 1232 adapter->rx_mbuf_sz = MJUM9BYTES; 1233 #endif 1234 em_initialize_receive_unit(ctx); 1235 1236 /* Use real VLAN Filter support? */ 1237 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1238 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1239 /* Use real VLAN Filter support */ 1240 em_setup_vlan_hw_support(adapter); 1241 else { 1242 u32 ctrl; 1243 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1244 ctrl |= E1000_CTRL_VME; 1245 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1246 } 1247 } 1248 1249 /* Don't lose promiscuous settings */ 1250 em_if_set_promisc(ctx, IFF_PROMISC); 1251 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1252 1253 /* MSI/X configuration for 82574 */ 1254 if (adapter->hw.mac.type == e1000_82574) { 1255 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1256 1257 tmp |= E1000_CTRL_EXT_PBA_CLR; 1258 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1259 /* Set the IVAR - interrupt vector routing. */ 1260 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1261 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1262 igb_configure_queues(adapter); 1263 1264 /* this clears any pending interrupts */ 1265 E1000_READ_REG(&adapter->hw, E1000_ICR); 1266 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1267 1268 /* AMT based hardware can now take control from firmware */ 1269 if (adapter->has_manage && adapter->has_amt) 1270 em_get_hw_control(adapter); 1271 1272 /* Set Energy Efficient Ethernet */ 1273 if (adapter->hw.mac.type >= igb_mac_min && 1274 adapter->hw.phy.media_type == e1000_media_type_copper) { 1275 if (adapter->hw.mac.type == e1000_i354) 1276 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1277 else 1278 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1279 } 1280 } 1281 1282 /********************************************************************* 1283 * 1284 * Fast Legacy/MSI Combined Interrupt Service routine 1285 * 1286 *********************************************************************/ 1287 int 1288 em_intr(void *arg) 1289 { 1290 struct adapter *adapter = arg; 1291 if_ctx_t ctx = adapter->ctx; 1292 u32 reg_icr; 1293 1294 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1295 1296 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1297 goto skip_stray; 1298 /* Hot eject? */ 1299 if (reg_icr == 0xffffffff) 1300 return FILTER_STRAY; 1301 1302 /* Definitely not our interrupt. */ 1303 if (reg_icr == 0x0) 1304 return FILTER_STRAY; 1305 1306 /* 1307 * Starting with the 82571 chip, bit 31 should be used to 1308 * determine whether the interrupt belongs to us. 1309 */ 1310 if (adapter->hw.mac.type >= e1000_82571 && 1311 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1312 return FILTER_STRAY; 1313 1314 skip_stray: 1315 /* Link status change */ 1316 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1317 adapter->hw.mac.get_link_status = 1; 1318 iflib_admin_intr_deferred(ctx); 1319 } 1320 1321 if (reg_icr & E1000_ICR_RXO) 1322 adapter->rx_overruns++; 1323 1324 return (FILTER_SCHEDULE_THREAD); 1325 } 1326 1327 static void 1328 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1329 { 1330 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1331 } 1332 1333 static void 1334 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1335 { 1336 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1337 } 1338 1339 static void 1340 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1341 { 1342 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1343 } 1344 1345 static void 1346 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1347 { 1348 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1349 } 1350 1351 static int 1352 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1353 { 1354 struct adapter *adapter = iflib_get_softc(ctx); 1355 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1356 1357 if (adapter->hw.mac.type >= igb_mac_min) 1358 igb_rx_enable_queue(adapter, rxq); 1359 else 1360 em_rx_enable_queue(adapter, rxq); 1361 return (0); 1362 } 1363 1364 static int 1365 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1366 { 1367 struct adapter *adapter = iflib_get_softc(ctx); 1368 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1369 1370 if (adapter->hw.mac.type >= igb_mac_min) 1371 igb_tx_enable_queue(adapter, txq); 1372 else 1373 em_tx_enable_queue(adapter, txq); 1374 return (0); 1375 } 1376 1377 /********************************************************************* 1378 * 1379 * MSIX RX Interrupt Service routine 1380 * 1381 **********************************************************************/ 1382 static int 1383 em_msix_que(void *arg) 1384 { 1385 struct em_rx_queue *que = arg; 1386 1387 ++que->irqs; 1388 1389 return (FILTER_SCHEDULE_THREAD); 1390 } 1391 1392 /********************************************************************* 1393 * 1394 * MSIX Link Fast Interrupt Service routine 1395 * 1396 **********************************************************************/ 1397 static int 1398 em_msix_link(void *arg) 1399 { 1400 struct adapter *adapter = arg; 1401 u32 reg_icr; 1402 1403 ++adapter->link_irq; 1404 MPASS(adapter->hw.back != NULL); 1405 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1406 1407 if (reg_icr & E1000_ICR_RXO) 1408 adapter->rx_overruns++; 1409 1410 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1411 em_handle_link(adapter->ctx); 1412 } else { 1413 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1414 EM_MSIX_LINK | E1000_IMS_LSC); 1415 if (adapter->hw.mac.type >= igb_mac_min) 1416 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1417 } 1418 1419 /* 1420 * Because we must read the ICR for this interrupt 1421 * it may clear other causes using autoclear, for 1422 * this reason we simply create a soft interrupt 1423 * for all these vectors. 1424 */ 1425 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1426 E1000_WRITE_REG(&adapter->hw, 1427 E1000_ICS, adapter->ims); 1428 } 1429 1430 return (FILTER_HANDLED); 1431 } 1432 1433 static void 1434 em_handle_link(void *context) 1435 { 1436 if_ctx_t ctx = context; 1437 struct adapter *adapter = iflib_get_softc(ctx); 1438 1439 adapter->hw.mac.get_link_status = 1; 1440 iflib_admin_intr_deferred(ctx); 1441 } 1442 1443 1444 /********************************************************************* 1445 * 1446 * Media Ioctl callback 1447 * 1448 * This routine is called whenever the user queries the status of 1449 * the interface using ifconfig. 1450 * 1451 **********************************************************************/ 1452 static void 1453 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1454 { 1455 struct adapter *adapter = iflib_get_softc(ctx); 1456 u_char fiber_type = IFM_1000_SX; 1457 1458 INIT_DEBUGOUT("em_if_media_status: begin"); 1459 1460 iflib_admin_intr_deferred(ctx); 1461 1462 ifmr->ifm_status = IFM_AVALID; 1463 ifmr->ifm_active = IFM_ETHER; 1464 1465 if (!adapter->link_active) { 1466 return; 1467 } 1468 1469 ifmr->ifm_status |= IFM_ACTIVE; 1470 1471 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1472 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1473 if (adapter->hw.mac.type == e1000_82545) 1474 fiber_type = IFM_1000_LX; 1475 ifmr->ifm_active |= fiber_type | IFM_FDX; 1476 } else { 1477 switch (adapter->link_speed) { 1478 case 10: 1479 ifmr->ifm_active |= IFM_10_T; 1480 break; 1481 case 100: 1482 ifmr->ifm_active |= IFM_100_TX; 1483 break; 1484 case 1000: 1485 ifmr->ifm_active |= IFM_1000_T; 1486 break; 1487 } 1488 if (adapter->link_duplex == FULL_DUPLEX) 1489 ifmr->ifm_active |= IFM_FDX; 1490 else 1491 ifmr->ifm_active |= IFM_HDX; 1492 } 1493 } 1494 1495 /********************************************************************* 1496 * 1497 * Media Ioctl callback 1498 * 1499 * This routine is called when the user changes speed/duplex using 1500 * media/mediopt option with ifconfig. 1501 * 1502 **********************************************************************/ 1503 static int 1504 em_if_media_change(if_ctx_t ctx) 1505 { 1506 struct adapter *adapter = iflib_get_softc(ctx); 1507 struct ifmedia *ifm = iflib_get_media(ctx); 1508 1509 INIT_DEBUGOUT("em_if_media_change: begin"); 1510 1511 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1512 return (EINVAL); 1513 1514 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1515 case IFM_AUTO: 1516 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1517 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1518 break; 1519 case IFM_1000_LX: 1520 case IFM_1000_SX: 1521 case IFM_1000_T: 1522 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1523 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1524 break; 1525 case IFM_100_TX: 1526 adapter->hw.mac.autoneg = FALSE; 1527 adapter->hw.phy.autoneg_advertised = 0; 1528 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1529 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1530 else 1531 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1532 break; 1533 case IFM_10_T: 1534 adapter->hw.mac.autoneg = FALSE; 1535 adapter->hw.phy.autoneg_advertised = 0; 1536 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1537 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1538 else 1539 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1540 break; 1541 default: 1542 device_printf(adapter->dev, "Unsupported media type\n"); 1543 } 1544 1545 em_if_init(ctx); 1546 1547 return (0); 1548 } 1549 1550 static int 1551 em_if_set_promisc(if_ctx_t ctx, int flags) 1552 { 1553 struct adapter *adapter = iflib_get_softc(ctx); 1554 u32 reg_rctl; 1555 1556 em_disable_promisc(ctx); 1557 1558 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1559 1560 if (flags & IFF_PROMISC) { 1561 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1562 /* Turn this on if you want to see bad packets */ 1563 if (em_debug_sbp) 1564 reg_rctl |= E1000_RCTL_SBP; 1565 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1566 } else if (flags & IFF_ALLMULTI) { 1567 reg_rctl |= E1000_RCTL_MPE; 1568 reg_rctl &= ~E1000_RCTL_UPE; 1569 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1570 } 1571 return (0); 1572 } 1573 1574 static void 1575 em_disable_promisc(if_ctx_t ctx) 1576 { 1577 struct adapter *adapter = iflib_get_softc(ctx); 1578 struct ifnet *ifp = iflib_get_ifp(ctx); 1579 u32 reg_rctl; 1580 int mcnt = 0; 1581 1582 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1583 reg_rctl &= (~E1000_RCTL_UPE); 1584 if (if_getflags(ifp) & IFF_ALLMULTI) 1585 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1586 else 1587 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1588 /* Don't disable if in MAX groups */ 1589 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1590 reg_rctl &= (~E1000_RCTL_MPE); 1591 reg_rctl &= (~E1000_RCTL_SBP); 1592 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1593 } 1594 1595 1596 /********************************************************************* 1597 * Multicast Update 1598 * 1599 * This routine is called whenever multicast address list is updated. 1600 * 1601 **********************************************************************/ 1602 1603 static void 1604 em_if_multi_set(if_ctx_t ctx) 1605 { 1606 struct adapter *adapter = iflib_get_softc(ctx); 1607 struct ifnet *ifp = iflib_get_ifp(ctx); 1608 u32 reg_rctl = 0; 1609 u8 *mta; /* Multicast array memory */ 1610 int mcnt = 0; 1611 1612 IOCTL_DEBUGOUT("em_set_multi: begin"); 1613 1614 mta = adapter->mta; 1615 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1616 1617 if (adapter->hw.mac.type == e1000_82542 && 1618 adapter->hw.revision_id == E1000_REVISION_2) { 1619 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1620 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1621 e1000_pci_clear_mwi(&adapter->hw); 1622 reg_rctl |= E1000_RCTL_RST; 1623 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1624 msec_delay(5); 1625 } 1626 1627 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1628 1629 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1630 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1631 reg_rctl |= E1000_RCTL_MPE; 1632 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1633 } else 1634 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1635 1636 if (adapter->hw.mac.type == e1000_82542 && 1637 adapter->hw.revision_id == E1000_REVISION_2) { 1638 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1639 reg_rctl &= ~E1000_RCTL_RST; 1640 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1641 msec_delay(5); 1642 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1643 e1000_pci_set_mwi(&adapter->hw); 1644 } 1645 } 1646 1647 1648 /********************************************************************* 1649 * Timer routine 1650 * 1651 * This routine checks for link status and updates statistics. 1652 * 1653 **********************************************************************/ 1654 1655 static void 1656 em_if_timer(if_ctx_t ctx, uint16_t qid) 1657 { 1658 struct adapter *adapter = iflib_get_softc(ctx); 1659 struct em_rx_queue *que; 1660 int i; 1661 int trigger = 0; 1662 1663 if (qid != 0) 1664 return; 1665 1666 em_if_update_admin_status(ctx); 1667 em_update_stats_counters(adapter); 1668 1669 /* Reset LAA into RAR[0] on 82571 */ 1670 if ((adapter->hw.mac.type == e1000_82571) && 1671 e1000_get_laa_state_82571(&adapter->hw)) 1672 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1673 1674 if (adapter->hw.mac.type < em_mac_min) 1675 lem_smartspeed(adapter); 1676 1677 /* Mask to use in the irq trigger */ 1678 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1679 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1680 trigger |= que->eims; 1681 } else { 1682 trigger = E1000_ICS_RXDMT0; 1683 } 1684 } 1685 1686 1687 static void 1688 em_if_update_admin_status(if_ctx_t ctx) 1689 { 1690 struct adapter *adapter = iflib_get_softc(ctx); 1691 struct e1000_hw *hw = &adapter->hw; 1692 struct ifnet *ifp = iflib_get_ifp(ctx); 1693 device_t dev = iflib_get_dev(ctx); 1694 u32 link_check = 0; 1695 1696 /* Get the cached link value or read phy for real */ 1697 switch (hw->phy.media_type) { 1698 case e1000_media_type_copper: 1699 if (hw->mac.get_link_status) { 1700 if (hw->mac.type == e1000_pch_spt) 1701 msec_delay(50); 1702 /* Do the work to read phy */ 1703 e1000_check_for_link(hw); 1704 link_check = !hw->mac.get_link_status; 1705 if (link_check) /* ESB2 fix */ 1706 e1000_cfg_on_link_up(hw); 1707 } else { 1708 link_check = TRUE; 1709 } 1710 break; 1711 case e1000_media_type_fiber: 1712 e1000_check_for_link(hw); 1713 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1714 E1000_STATUS_LU); 1715 break; 1716 case e1000_media_type_internal_serdes: 1717 e1000_check_for_link(hw); 1718 link_check = adapter->hw.mac.serdes_has_link; 1719 break; 1720 default: 1721 case e1000_media_type_unknown: 1722 break; 1723 } 1724 1725 /* Now check for a transition */ 1726 if (link_check && (adapter->link_active == 0)) { 1727 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1728 &adapter->link_duplex); 1729 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1730 if ((adapter->link_speed != SPEED_1000) && 1731 ((hw->mac.type == e1000_82571) || 1732 (hw->mac.type == e1000_82572))) { 1733 int tarc0; 1734 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1735 tarc0 &= ~TARC_SPEED_MODE_BIT; 1736 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1737 } 1738 if (bootverbose) 1739 device_printf(dev, "Link is up %d Mbps %s\n", 1740 adapter->link_speed, 1741 ((adapter->link_duplex == FULL_DUPLEX) ? 1742 "Full Duplex" : "Half Duplex")); 1743 adapter->link_active = 1; 1744 adapter->smartspeed = 0; 1745 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1746 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1747 printf("Link state changed to up\n"); 1748 } else if (!link_check && (adapter->link_active == 1)) { 1749 if_setbaudrate(ifp, 0); 1750 adapter->link_speed = 0; 1751 adapter->link_duplex = 0; 1752 if (bootverbose) 1753 device_printf(dev, "Link is Down\n"); 1754 adapter->link_active = 0; 1755 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1756 printf("link state changed to down\n"); 1757 } 1758 1759 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1760 } 1761 1762 /********************************************************************* 1763 * 1764 * This routine disables all traffic on the adapter by issuing a 1765 * global reset on the MAC and deallocates TX/RX buffers. 1766 * 1767 * This routine should always be called with BOTH the CORE 1768 * and TX locks. 1769 **********************************************************************/ 1770 1771 static void 1772 em_if_stop(if_ctx_t ctx) 1773 { 1774 struct adapter *adapter = iflib_get_softc(ctx); 1775 1776 INIT_DEBUGOUT("em_stop: begin"); 1777 1778 e1000_reset_hw(&adapter->hw); 1779 if (adapter->hw.mac.type >= e1000_82544) 1780 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1781 1782 e1000_led_off(&adapter->hw); 1783 e1000_cleanup_led(&adapter->hw); 1784 } 1785 1786 1787 /********************************************************************* 1788 * 1789 * Determine hardware revision. 1790 * 1791 **********************************************************************/ 1792 static void 1793 em_identify_hardware(if_ctx_t ctx) 1794 { 1795 device_t dev = iflib_get_dev(ctx); 1796 struct adapter *adapter = iflib_get_softc(ctx); 1797 1798 /* Make sure our PCI config space has the necessary stuff set */ 1799 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1800 1801 /* Save off the information about this board */ 1802 adapter->hw.vendor_id = pci_get_vendor(dev); 1803 adapter->hw.device_id = pci_get_device(dev); 1804 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1805 adapter->hw.subsystem_vendor_id = 1806 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1807 adapter->hw.subsystem_device_id = 1808 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1809 1810 /* Do Shared Code Init and Setup */ 1811 if (e1000_set_mac_type(&adapter->hw)) { 1812 device_printf(dev, "Setup init failure\n"); 1813 return; 1814 } 1815 } 1816 1817 static int 1818 em_allocate_pci_resources(if_ctx_t ctx) 1819 { 1820 struct adapter *adapter = iflib_get_softc(ctx); 1821 device_t dev = iflib_get_dev(ctx); 1822 int rid, val; 1823 1824 rid = PCIR_BAR(0); 1825 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1826 &rid, RF_ACTIVE); 1827 if (adapter->memory == NULL) { 1828 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1829 return (ENXIO); 1830 } 1831 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1832 adapter->osdep.mem_bus_space_handle = 1833 rman_get_bushandle(adapter->memory); 1834 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1835 1836 /* Only older adapters use IO mapping */ 1837 if (adapter->hw.mac.type < em_mac_min && 1838 adapter->hw.mac.type > e1000_82543) { 1839 /* Figure our where our IO BAR is ? */ 1840 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1841 val = pci_read_config(dev, rid, 4); 1842 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1843 adapter->io_rid = rid; 1844 break; 1845 } 1846 rid += 4; 1847 /* check for 64bit BAR */ 1848 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1849 rid += 4; 1850 } 1851 if (rid >= PCIR_CIS) { 1852 device_printf(dev, "Unable to locate IO BAR\n"); 1853 return (ENXIO); 1854 } 1855 adapter->ioport = bus_alloc_resource_any(dev, 1856 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1857 if (adapter->ioport == NULL) { 1858 device_printf(dev, "Unable to allocate bus resource: " 1859 "ioport\n"); 1860 return (ENXIO); 1861 } 1862 adapter->hw.io_base = 0; 1863 adapter->osdep.io_bus_space_tag = 1864 rman_get_bustag(adapter->ioport); 1865 adapter->osdep.io_bus_space_handle = 1866 rman_get_bushandle(adapter->ioport); 1867 } 1868 1869 adapter->hw.back = &adapter->osdep; 1870 1871 return (0); 1872 } 1873 1874 /********************************************************************* 1875 * 1876 * Setup the MSIX Interrupt handlers 1877 * 1878 **********************************************************************/ 1879 static int 1880 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1881 { 1882 struct adapter *adapter = iflib_get_softc(ctx); 1883 struct em_rx_queue *rx_que = adapter->rx_queues; 1884 struct em_tx_queue *tx_que = adapter->tx_queues; 1885 int error, rid, i, vector = 0, rx_vectors; 1886 char buf[16]; 1887 1888 /* First set up ring resources */ 1889 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1890 rid = vector + 1; 1891 snprintf(buf, sizeof(buf), "rxq%d", i); 1892 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1893 if (error) { 1894 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1895 adapter->rx_num_queues = i + 1; 1896 goto fail; 1897 } 1898 1899 rx_que->msix = vector; 1900 1901 /* 1902 * Set the bit to enable interrupt 1903 * in E1000_IMS -- bits 20 and 21 1904 * are for RX0 and RX1, note this has 1905 * NOTHING to do with the MSIX vector 1906 */ 1907 if (adapter->hw.mac.type == e1000_82574) { 1908 rx_que->eims = 1 << (20 + i); 1909 adapter->ims |= rx_que->eims; 1910 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1911 } else if (adapter->hw.mac.type == e1000_82575) 1912 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1913 else 1914 rx_que->eims = 1 << vector; 1915 } 1916 rx_vectors = vector; 1917 1918 vector = 0; 1919 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1920 rid = vector + 1; 1921 snprintf(buf, sizeof(buf), "txq%d", i); 1922 tx_que = &adapter->tx_queues[i]; 1923 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1924 1925 tx_que->msix = (vector % adapter->tx_num_queues); 1926 1927 /* 1928 * Set the bit to enable interrupt 1929 * in E1000_IMS -- bits 22 and 23 1930 * are for TX0 and TX1, note this has 1931 * NOTHING to do with the MSIX vector 1932 */ 1933 if (adapter->hw.mac.type == e1000_82574) { 1934 tx_que->eims = 1 << (22 + i); 1935 adapter->ims |= tx_que->eims; 1936 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1937 } else if (adapter->hw.mac.type == e1000_82575) { 1938 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1939 } else { 1940 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1941 } 1942 } 1943 1944 /* Link interrupt */ 1945 rid = rx_vectors + 1; 1946 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1947 1948 if (error) { 1949 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1950 goto fail; 1951 } 1952 adapter->linkvec = rx_vectors; 1953 if (adapter->hw.mac.type < igb_mac_min) { 1954 adapter->ivars |= (8 | rx_vectors) << 16; 1955 adapter->ivars |= 0x80000000; 1956 } 1957 return (0); 1958 fail: 1959 iflib_irq_free(ctx, &adapter->irq); 1960 rx_que = adapter->rx_queues; 1961 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1962 iflib_irq_free(ctx, &rx_que->que_irq); 1963 return (error); 1964 } 1965 1966 static void 1967 igb_configure_queues(struct adapter *adapter) 1968 { 1969 struct e1000_hw *hw = &adapter->hw; 1970 struct em_rx_queue *rx_que; 1971 struct em_tx_queue *tx_que; 1972 u32 tmp, ivar = 0, newitr = 0; 1973 1974 /* First turn on RSS capability */ 1975 if (adapter->hw.mac.type != e1000_82575) 1976 E1000_WRITE_REG(hw, E1000_GPIE, 1977 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 1978 E1000_GPIE_PBA | E1000_GPIE_NSICR); 1979 1980 /* Turn on MSIX */ 1981 switch (adapter->hw.mac.type) { 1982 case e1000_82580: 1983 case e1000_i350: 1984 case e1000_i354: 1985 case e1000_i210: 1986 case e1000_i211: 1987 case e1000_vfadapt: 1988 case e1000_vfadapt_i350: 1989 /* RX entries */ 1990 for (int i = 0; i < adapter->rx_num_queues; i++) { 1991 u32 index = i >> 1; 1992 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1993 rx_que = &adapter->rx_queues[i]; 1994 if (i & 1) { 1995 ivar &= 0xFF00FFFF; 1996 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 1997 } else { 1998 ivar &= 0xFFFFFF00; 1999 ivar |= rx_que->msix | E1000_IVAR_VALID; 2000 } 2001 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2002 } 2003 /* TX entries */ 2004 for (int i = 0; i < adapter->tx_num_queues; i++) { 2005 u32 index = i >> 1; 2006 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2007 tx_que = &adapter->tx_queues[i]; 2008 if (i & 1) { 2009 ivar &= 0x00FFFFFF; 2010 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2011 } else { 2012 ivar &= 0xFFFF00FF; 2013 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2014 } 2015 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2016 adapter->que_mask |= tx_que->eims; 2017 } 2018 2019 /* And for the link interrupt */ 2020 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2021 adapter->link_mask = 1 << adapter->linkvec; 2022 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2023 break; 2024 case e1000_82576: 2025 /* RX entries */ 2026 for (int i = 0; i < adapter->rx_num_queues; i++) { 2027 u32 index = i & 0x7; /* Each IVAR has two entries */ 2028 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2029 rx_que = &adapter->rx_queues[i]; 2030 if (i < 8) { 2031 ivar &= 0xFFFFFF00; 2032 ivar |= rx_que->msix | E1000_IVAR_VALID; 2033 } else { 2034 ivar &= 0xFF00FFFF; 2035 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2036 } 2037 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2038 adapter->que_mask |= rx_que->eims; 2039 } 2040 /* TX entries */ 2041 for (int i = 0; i < adapter->tx_num_queues; i++) { 2042 u32 index = i & 0x7; /* Each IVAR has two entries */ 2043 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2044 tx_que = &adapter->tx_queues[i]; 2045 if (i < 8) { 2046 ivar &= 0xFFFF00FF; 2047 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2048 } else { 2049 ivar &= 0x00FFFFFF; 2050 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2051 } 2052 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2053 adapter->que_mask |= tx_que->eims; 2054 } 2055 2056 /* And for the link interrupt */ 2057 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2058 adapter->link_mask = 1 << adapter->linkvec; 2059 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2060 break; 2061 2062 case e1000_82575: 2063 /* enable MSI-X support*/ 2064 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2065 tmp |= E1000_CTRL_EXT_PBA_CLR; 2066 /* Auto-Mask interrupts upon ICR read. */ 2067 tmp |= E1000_CTRL_EXT_EIAME; 2068 tmp |= E1000_CTRL_EXT_IRCA; 2069 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2070 2071 /* Queues */ 2072 for (int i = 0; i < adapter->rx_num_queues; i++) { 2073 rx_que = &adapter->rx_queues[i]; 2074 tmp = E1000_EICR_RX_QUEUE0 << i; 2075 tmp |= E1000_EICR_TX_QUEUE0 << i; 2076 rx_que->eims = tmp; 2077 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2078 i, rx_que->eims); 2079 adapter->que_mask |= rx_que->eims; 2080 } 2081 2082 /* Link */ 2083 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2084 E1000_EIMS_OTHER); 2085 adapter->link_mask |= E1000_EIMS_OTHER; 2086 default: 2087 break; 2088 } 2089 2090 /* Set the starting interrupt rate */ 2091 if (em_max_interrupt_rate > 0) 2092 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2093 2094 if (hw->mac.type == e1000_82575) 2095 newitr |= newitr << 16; 2096 else 2097 newitr |= E1000_EITR_CNT_IGNR; 2098 2099 for (int i = 0; i < adapter->rx_num_queues; i++) { 2100 rx_que = &adapter->rx_queues[i]; 2101 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2102 } 2103 2104 return; 2105 } 2106 2107 static void 2108 em_free_pci_resources(if_ctx_t ctx) 2109 { 2110 struct adapter *adapter = iflib_get_softc(ctx); 2111 struct em_rx_queue *que = adapter->rx_queues; 2112 device_t dev = iflib_get_dev(ctx); 2113 2114 /* Release all msix queue resources */ 2115 if (adapter->intr_type == IFLIB_INTR_MSIX) 2116 iflib_irq_free(ctx, &adapter->irq); 2117 2118 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2119 iflib_irq_free(ctx, &que->que_irq); 2120 } 2121 2122 /* First release all the interrupt resources */ 2123 if (adapter->memory != NULL) { 2124 bus_release_resource(dev, SYS_RES_MEMORY, 2125 PCIR_BAR(0), adapter->memory); 2126 adapter->memory = NULL; 2127 } 2128 2129 if (adapter->flash != NULL) { 2130 bus_release_resource(dev, SYS_RES_MEMORY, 2131 EM_FLASH, adapter->flash); 2132 adapter->flash = NULL; 2133 } 2134 if (adapter->ioport != NULL) 2135 bus_release_resource(dev, SYS_RES_IOPORT, 2136 adapter->io_rid, adapter->ioport); 2137 } 2138 2139 /* Setup MSI or MSI/X */ 2140 static int 2141 em_setup_msix(if_ctx_t ctx) 2142 { 2143 struct adapter *adapter = iflib_get_softc(ctx); 2144 2145 if (adapter->hw.mac.type == e1000_82574) { 2146 em_enable_vectors_82574(ctx); 2147 } 2148 return (0); 2149 } 2150 2151 /********************************************************************* 2152 * 2153 * Initialize the hardware to a configuration 2154 * as specified by the adapter structure. 2155 * 2156 **********************************************************************/ 2157 2158 static void 2159 lem_smartspeed(struct adapter *adapter) 2160 { 2161 u16 phy_tmp; 2162 2163 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2164 adapter->hw.mac.autoneg == 0 || 2165 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2166 return; 2167 2168 if (adapter->smartspeed == 0) { 2169 /* If Master/Slave config fault is asserted twice, 2170 * we assume back-to-back */ 2171 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2172 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2173 return; 2174 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2175 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2176 e1000_read_phy_reg(&adapter->hw, 2177 PHY_1000T_CTRL, &phy_tmp); 2178 if(phy_tmp & CR_1000T_MS_ENABLE) { 2179 phy_tmp &= ~CR_1000T_MS_ENABLE; 2180 e1000_write_phy_reg(&adapter->hw, 2181 PHY_1000T_CTRL, phy_tmp); 2182 adapter->smartspeed++; 2183 if(adapter->hw.mac.autoneg && 2184 !e1000_copper_link_autoneg(&adapter->hw) && 2185 !e1000_read_phy_reg(&adapter->hw, 2186 PHY_CONTROL, &phy_tmp)) { 2187 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2188 MII_CR_RESTART_AUTO_NEG); 2189 e1000_write_phy_reg(&adapter->hw, 2190 PHY_CONTROL, phy_tmp); 2191 } 2192 } 2193 } 2194 return; 2195 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2196 /* If still no link, perhaps using 2/3 pair cable */ 2197 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2198 phy_tmp |= CR_1000T_MS_ENABLE; 2199 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2200 if(adapter->hw.mac.autoneg && 2201 !e1000_copper_link_autoneg(&adapter->hw) && 2202 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2203 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2204 MII_CR_RESTART_AUTO_NEG); 2205 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2206 } 2207 } 2208 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2209 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2210 adapter->smartspeed = 0; 2211 } 2212 2213 2214 static void 2215 em_reset(if_ctx_t ctx) 2216 { 2217 device_t dev = iflib_get_dev(ctx); 2218 struct adapter *adapter = iflib_get_softc(ctx); 2219 struct ifnet *ifp = iflib_get_ifp(ctx); 2220 struct e1000_hw *hw = &adapter->hw; 2221 u16 rx_buffer_size; 2222 u32 pba; 2223 2224 INIT_DEBUGOUT("em_reset: begin"); 2225 2226 /* Set up smart power down as default off on newer adapters. */ 2227 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2228 hw->mac.type == e1000_82572)) { 2229 u16 phy_tmp = 0; 2230 2231 /* Speed up time to link by disabling smart power down. */ 2232 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2233 phy_tmp &= ~IGP02E1000_PM_SPD; 2234 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2235 } 2236 2237 /* 2238 * Packet Buffer Allocation (PBA) 2239 * Writing PBA sets the receive portion of the buffer 2240 * the remainder is used for the transmit buffer. 2241 */ 2242 switch (hw->mac.type) { 2243 /* Total Packet Buffer on these is 48K */ 2244 case e1000_82571: 2245 case e1000_82572: 2246 case e1000_80003es2lan: 2247 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2248 break; 2249 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2250 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2251 break; 2252 case e1000_82574: 2253 case e1000_82583: 2254 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2255 break; 2256 case e1000_ich8lan: 2257 pba = E1000_PBA_8K; 2258 break; 2259 case e1000_ich9lan: 2260 case e1000_ich10lan: 2261 /* Boost Receive side for jumbo frames */ 2262 if (adapter->hw.mac.max_frame_size > 4096) 2263 pba = E1000_PBA_14K; 2264 else 2265 pba = E1000_PBA_10K; 2266 break; 2267 case e1000_pchlan: 2268 case e1000_pch2lan: 2269 case e1000_pch_lpt: 2270 case e1000_pch_spt: 2271 pba = E1000_PBA_26K; 2272 break; 2273 case e1000_82575: 2274 pba = E1000_PBA_32K; 2275 break; 2276 case e1000_82576: 2277 case e1000_vfadapt: 2278 pba = E1000_READ_REG(hw, E1000_RXPBS); 2279 pba &= E1000_RXPBS_SIZE_MASK_82576; 2280 break; 2281 case e1000_82580: 2282 case e1000_i350: 2283 case e1000_i354: 2284 case e1000_vfadapt_i350: 2285 pba = E1000_READ_REG(hw, E1000_RXPBS); 2286 pba = e1000_rxpbs_adjust_82580(pba); 2287 break; 2288 case e1000_i210: 2289 case e1000_i211: 2290 pba = E1000_PBA_34K; 2291 break; 2292 default: 2293 if (adapter->hw.mac.max_frame_size > 8192) 2294 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2295 else 2296 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2297 } 2298 2299 /* Special needs in case of Jumbo frames */ 2300 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2301 u32 tx_space, min_tx, min_rx; 2302 pba = E1000_READ_REG(hw, E1000_PBA); 2303 tx_space = pba >> 16; 2304 pba &= 0xffff; 2305 min_tx = (adapter->hw.mac.max_frame_size + 2306 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2307 min_tx = roundup2(min_tx, 1024); 2308 min_tx >>= 10; 2309 min_rx = adapter->hw.mac.max_frame_size; 2310 min_rx = roundup2(min_rx, 1024); 2311 min_rx >>= 10; 2312 if (tx_space < min_tx && 2313 ((min_tx - tx_space) < pba)) { 2314 pba = pba - (min_tx - tx_space); 2315 /* 2316 * if short on rx space, rx wins 2317 * and must trump tx adjustment 2318 */ 2319 if (pba < min_rx) 2320 pba = min_rx; 2321 } 2322 E1000_WRITE_REG(hw, E1000_PBA, pba); 2323 } 2324 2325 if (hw->mac.type < igb_mac_min) 2326 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2327 2328 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2329 2330 /* 2331 * These parameters control the automatic generation (Tx) and 2332 * response (Rx) to Ethernet PAUSE frames. 2333 * - High water mark should allow for at least two frames to be 2334 * received after sending an XOFF. 2335 * - Low water mark works best when it is very near the high water mark. 2336 * This allows the receiver to restart by sending XON when it has 2337 * drained a bit. Here we use an arbitrary value of 1500 which will 2338 * restart after one full frame is pulled from the buffer. There 2339 * could be several smaller frames in the buffer and if so they will 2340 * not trigger the XON until their total number reduces the buffer 2341 * by 1500. 2342 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2343 */ 2344 rx_buffer_size = (pba & 0xffff) << 10; 2345 hw->fc.high_water = rx_buffer_size - 2346 roundup2(adapter->hw.mac.max_frame_size, 1024); 2347 hw->fc.low_water = hw->fc.high_water - 1500; 2348 2349 if (adapter->fc) /* locally set flow control value? */ 2350 hw->fc.requested_mode = adapter->fc; 2351 else 2352 hw->fc.requested_mode = e1000_fc_full; 2353 2354 if (hw->mac.type == e1000_80003es2lan) 2355 hw->fc.pause_time = 0xFFFF; 2356 else 2357 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2358 2359 hw->fc.send_xon = TRUE; 2360 2361 /* Device specific overrides/settings */ 2362 switch (hw->mac.type) { 2363 case e1000_pchlan: 2364 /* Workaround: no TX flow ctrl for PCH */ 2365 hw->fc.requested_mode = e1000_fc_rx_pause; 2366 hw->fc.pause_time = 0xFFFF; /* override */ 2367 if (if_getmtu(ifp) > ETHERMTU) { 2368 hw->fc.high_water = 0x3500; 2369 hw->fc.low_water = 0x1500; 2370 } else { 2371 hw->fc.high_water = 0x5000; 2372 hw->fc.low_water = 0x3000; 2373 } 2374 hw->fc.refresh_time = 0x1000; 2375 break; 2376 case e1000_pch2lan: 2377 case e1000_pch_lpt: 2378 case e1000_pch_spt: 2379 hw->fc.high_water = 0x5C20; 2380 hw->fc.low_water = 0x5048; 2381 hw->fc.pause_time = 0x0650; 2382 hw->fc.refresh_time = 0x0400; 2383 /* Jumbos need adjusted PBA */ 2384 if (if_getmtu(ifp) > ETHERMTU) 2385 E1000_WRITE_REG(hw, E1000_PBA, 12); 2386 else 2387 E1000_WRITE_REG(hw, E1000_PBA, 26); 2388 break; 2389 case e1000_82575: 2390 case e1000_82576: 2391 /* 8-byte granularity */ 2392 hw->fc.low_water = hw->fc.high_water - 8; 2393 break; 2394 case e1000_82580: 2395 case e1000_i350: 2396 case e1000_i354: 2397 case e1000_i210: 2398 case e1000_i211: 2399 case e1000_vfadapt: 2400 case e1000_vfadapt_i350: 2401 /* 16-byte granularity */ 2402 hw->fc.low_water = hw->fc.high_water - 16; 2403 break; 2404 case e1000_ich9lan: 2405 case e1000_ich10lan: 2406 if (if_getmtu(ifp) > ETHERMTU) { 2407 hw->fc.high_water = 0x2800; 2408 hw->fc.low_water = hw->fc.high_water - 8; 2409 break; 2410 } 2411 /* else fall thru */ 2412 default: 2413 if (hw->mac.type == e1000_80003es2lan) 2414 hw->fc.pause_time = 0xFFFF; 2415 break; 2416 } 2417 2418 /* Issue a global reset */ 2419 e1000_reset_hw(hw); 2420 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2421 em_disable_aspm(adapter); 2422 /* and a re-init */ 2423 if (e1000_init_hw(hw) < 0) { 2424 device_printf(dev, "Hardware Initialization Failed\n"); 2425 return; 2426 } 2427 2428 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2429 e1000_get_phy_info(hw); 2430 e1000_check_for_link(hw); 2431 } 2432 2433 #define RSSKEYLEN 10 2434 static void 2435 em_initialize_rss_mapping(struct adapter *adapter) 2436 { 2437 uint8_t rss_key[4 * RSSKEYLEN]; 2438 uint32_t reta = 0; 2439 struct e1000_hw *hw = &adapter->hw; 2440 int i; 2441 2442 /* 2443 * Configure RSS key 2444 */ 2445 arc4rand(rss_key, sizeof(rss_key), 0); 2446 for (i = 0; i < RSSKEYLEN; ++i) { 2447 uint32_t rssrk = 0; 2448 2449 rssrk = EM_RSSRK_VAL(rss_key, i); 2450 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2451 } 2452 2453 /* 2454 * Configure RSS redirect table in following fashion: 2455 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2456 */ 2457 for (i = 0; i < sizeof(reta); ++i) { 2458 uint32_t q; 2459 2460 q = (i % adapter->rx_num_queues) << 7; 2461 reta |= q << (8 * i); 2462 } 2463 2464 for (i = 0; i < 32; ++i) 2465 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2466 2467 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2468 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2469 E1000_MRQC_RSS_FIELD_IPV4 | 2470 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2471 E1000_MRQC_RSS_FIELD_IPV6_EX | 2472 E1000_MRQC_RSS_FIELD_IPV6); 2473 2474 } 2475 2476 static void 2477 igb_initialize_rss_mapping(struct adapter *adapter) 2478 { 2479 struct e1000_hw *hw = &adapter->hw; 2480 int i; 2481 int queue_id; 2482 u32 reta; 2483 u32 rss_key[10], mrqc, shift = 0; 2484 2485 /* XXX? */ 2486 if (adapter->hw.mac.type == e1000_82575) 2487 shift = 6; 2488 2489 /* 2490 * The redirection table controls which destination 2491 * queue each bucket redirects traffic to. 2492 * Each DWORD represents four queues, with the LSB 2493 * being the first queue in the DWORD. 2494 * 2495 * This just allocates buckets to queues using round-robin 2496 * allocation. 2497 * 2498 * NOTE: It Just Happens to line up with the default 2499 * RSS allocation method. 2500 */ 2501 2502 /* Warning FM follows */ 2503 reta = 0; 2504 for (i = 0; i < 128; i++) { 2505 #ifdef RSS 2506 queue_id = rss_get_indirection_to_bucket(i); 2507 /* 2508 * If we have more queues than buckets, we'll 2509 * end up mapping buckets to a subset of the 2510 * queues. 2511 * 2512 * If we have more buckets than queues, we'll 2513 * end up instead assigning multiple buckets 2514 * to queues. 2515 * 2516 * Both are suboptimal, but we need to handle 2517 * the case so we don't go out of bounds 2518 * indexing arrays and such. 2519 */ 2520 queue_id = queue_id % adapter->rx_num_queues; 2521 #else 2522 queue_id = (i % adapter->rx_num_queues); 2523 #endif 2524 /* Adjust if required */ 2525 queue_id = queue_id << shift; 2526 2527 /* 2528 * The low 8 bits are for hash value (n+0); 2529 * The next 8 bits are for hash value (n+1), etc. 2530 */ 2531 reta = reta >> 8; 2532 reta = reta | ( ((uint32_t) queue_id) << 24); 2533 if ((i & 3) == 3) { 2534 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2535 reta = 0; 2536 } 2537 } 2538 2539 /* Now fill in hash table */ 2540 2541 /* 2542 * MRQC: Multiple Receive Queues Command 2543 * Set queuing to RSS control, number depends on the device. 2544 */ 2545 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2546 2547 #ifdef RSS 2548 /* XXX ew typecasting */ 2549 rss_getkey((uint8_t *) &rss_key); 2550 #else 2551 arc4rand(&rss_key, sizeof(rss_key), 0); 2552 #endif 2553 for (i = 0; i < 10; i++) 2554 E1000_WRITE_REG_ARRAY(hw, 2555 E1000_RSSRK(0), i, rss_key[i]); 2556 2557 /* 2558 * Configure the RSS fields to hash upon. 2559 */ 2560 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2561 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2562 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2563 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2564 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2565 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2566 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2567 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2568 2569 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2570 } 2571 2572 /********************************************************************* 2573 * 2574 * Setup networking device structure and register an interface. 2575 * 2576 **********************************************************************/ 2577 static int 2578 em_setup_interface(if_ctx_t ctx) 2579 { 2580 struct ifnet *ifp = iflib_get_ifp(ctx); 2581 struct adapter *adapter = iflib_get_softc(ctx); 2582 if_softc_ctx_t scctx = adapter->shared; 2583 uint64_t cap = 0; 2584 2585 INIT_DEBUGOUT("em_setup_interface: begin"); 2586 2587 /* TSO parameters */ 2588 if_sethwtsomax(ifp, IP_MAXPACKET); 2589 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2590 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2591 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2592 2593 /* Single Queue */ 2594 if (adapter->tx_num_queues == 1) { 2595 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2596 if_setsendqready(ifp); 2597 } 2598 2599 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2600 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2601 2602 /* 2603 * Tell the upper layer(s) we 2604 * support full VLAN capability 2605 */ 2606 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2607 if_setcapabilitiesbit(ifp, cap, 0); 2608 2609 /* 2610 * Don't turn this on by default, if vlans are 2611 * created on another pseudo device (eg. lagg) 2612 * then vlan events are not passed thru, breaking 2613 * operation, but with HW FILTER off it works. If 2614 * using vlans directly on the em driver you can 2615 * enable this and get full hardware tag filtering. 2616 */ 2617 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2618 2619 /* Enable only WOL MAGIC by default */ 2620 if (adapter->wol) { 2621 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2622 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2623 } else { 2624 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2625 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2626 } 2627 2628 /* 2629 * Specify the media types supported by this adapter and register 2630 * callbacks to update media and link information 2631 */ 2632 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2633 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2634 u_char fiber_type = IFM_1000_SX; /* default type */ 2635 2636 if (adapter->hw.mac.type == e1000_82545) 2637 fiber_type = IFM_1000_LX; 2638 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2639 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2640 } else { 2641 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2642 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2643 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2644 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2645 if (adapter->hw.phy.type != e1000_phy_ife) { 2646 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2647 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2648 } 2649 } 2650 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2651 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2652 return (0); 2653 } 2654 2655 static int 2656 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2657 { 2658 struct adapter *adapter = iflib_get_softc(ctx); 2659 if_softc_ctx_t scctx = adapter->shared; 2660 int error = E1000_SUCCESS; 2661 struct em_tx_queue *que; 2662 int i, j; 2663 2664 MPASS(adapter->tx_num_queues > 0); 2665 MPASS(adapter->tx_num_queues == ntxqsets); 2666 2667 /* First allocate the top level queue structs */ 2668 if (!(adapter->tx_queues = 2669 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2670 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2671 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2672 return(ENOMEM); 2673 } 2674 2675 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2676 /* Set up some basics */ 2677 2678 struct tx_ring *txr = &que->txr; 2679 txr->adapter = que->adapter = adapter; 2680 que->me = txr->me = i; 2681 2682 /* Allocate report status array */ 2683 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2684 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2685 error = ENOMEM; 2686 goto fail; 2687 } 2688 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2689 txr->tx_rsq[j] = QIDX_INVALID; 2690 /* get the virtual and physical address of the hardware queues */ 2691 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2692 txr->tx_paddr = paddrs[i*ntxqs]; 2693 } 2694 2695 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2696 return (0); 2697 fail: 2698 em_if_queues_free(ctx); 2699 return (error); 2700 } 2701 2702 static int 2703 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2704 { 2705 struct adapter *adapter = iflib_get_softc(ctx); 2706 int error = E1000_SUCCESS; 2707 struct em_rx_queue *que; 2708 int i; 2709 2710 MPASS(adapter->rx_num_queues > 0); 2711 MPASS(adapter->rx_num_queues == nrxqsets); 2712 2713 /* First allocate the top level queue structs */ 2714 if (!(adapter->rx_queues = 2715 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2716 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2717 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2718 error = ENOMEM; 2719 goto fail; 2720 } 2721 2722 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2723 /* Set up some basics */ 2724 struct rx_ring *rxr = &que->rxr; 2725 rxr->adapter = que->adapter = adapter; 2726 rxr->que = que; 2727 que->me = rxr->me = i; 2728 2729 /* get the virtual and physical address of the hardware queues */ 2730 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2731 rxr->rx_paddr = paddrs[i*nrxqs]; 2732 } 2733 2734 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2735 2736 return (0); 2737 fail: 2738 em_if_queues_free(ctx); 2739 return (error); 2740 } 2741 2742 static void 2743 em_if_queues_free(if_ctx_t ctx) 2744 { 2745 struct adapter *adapter = iflib_get_softc(ctx); 2746 struct em_tx_queue *tx_que = adapter->tx_queues; 2747 struct em_rx_queue *rx_que = adapter->rx_queues; 2748 2749 if (tx_que != NULL) { 2750 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2751 struct tx_ring *txr = &tx_que->txr; 2752 if (txr->tx_rsq == NULL) 2753 break; 2754 2755 free(txr->tx_rsq, M_DEVBUF); 2756 txr->tx_rsq = NULL; 2757 } 2758 free(adapter->tx_queues, M_DEVBUF); 2759 adapter->tx_queues = NULL; 2760 } 2761 2762 if (rx_que != NULL) { 2763 free(adapter->rx_queues, M_DEVBUF); 2764 adapter->rx_queues = NULL; 2765 } 2766 2767 em_release_hw_control(adapter); 2768 2769 if (adapter->mta != NULL) { 2770 free(adapter->mta, M_DEVBUF); 2771 } 2772 } 2773 2774 /********************************************************************* 2775 * 2776 * Enable transmit unit. 2777 * 2778 **********************************************************************/ 2779 static void 2780 em_initialize_transmit_unit(if_ctx_t ctx) 2781 { 2782 struct adapter *adapter = iflib_get_softc(ctx); 2783 if_softc_ctx_t scctx = adapter->shared; 2784 struct em_tx_queue *que; 2785 struct tx_ring *txr; 2786 struct e1000_hw *hw = &adapter->hw; 2787 u32 tctl, txdctl = 0, tarc, tipg = 0; 2788 2789 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2790 2791 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2792 u64 bus_addr; 2793 caddr_t offp, endp; 2794 2795 que = &adapter->tx_queues[i]; 2796 txr = &que->txr; 2797 bus_addr = txr->tx_paddr; 2798 2799 /* Clear checksum offload context. */ 2800 offp = (caddr_t)&txr->csum_flags; 2801 endp = (caddr_t)(txr + 1); 2802 bzero(offp, endp - offp); 2803 2804 /* Base and Len of TX Ring */ 2805 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2806 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2807 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2808 (u32)(bus_addr >> 32)); 2809 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2810 (u32)bus_addr); 2811 /* Init the HEAD/TAIL indices */ 2812 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2813 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2814 2815 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2816 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2817 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2818 2819 txdctl = 0; /* clear txdctl */ 2820 txdctl |= 0x1f; /* PTHRESH */ 2821 txdctl |= 1 << 8; /* HTHRESH */ 2822 txdctl |= 1 << 16;/* WTHRESH */ 2823 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2824 txdctl |= E1000_TXDCTL_GRAN; 2825 txdctl |= 1 << 25; /* LWTHRESH */ 2826 2827 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2828 } 2829 2830 /* Set the default values for the Tx Inter Packet Gap timer */ 2831 switch (adapter->hw.mac.type) { 2832 case e1000_80003es2lan: 2833 tipg = DEFAULT_82543_TIPG_IPGR1; 2834 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2835 E1000_TIPG_IPGR2_SHIFT; 2836 break; 2837 case e1000_82542: 2838 tipg = DEFAULT_82542_TIPG_IPGT; 2839 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2840 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2841 break; 2842 default: 2843 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2844 (adapter->hw.phy.media_type == 2845 e1000_media_type_internal_serdes)) 2846 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2847 else 2848 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2849 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2850 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2851 } 2852 2853 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2854 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 2855 2856 if(adapter->hw.mac.type >= e1000_82540) 2857 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 2858 adapter->tx_abs_int_delay.value); 2859 2860 if ((adapter->hw.mac.type == e1000_82571) || 2861 (adapter->hw.mac.type == e1000_82572)) { 2862 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2863 tarc |= TARC_SPEED_MODE_BIT; 2864 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2865 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2866 /* errata: program both queues to unweighted RR */ 2867 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2868 tarc |= 1; 2869 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2870 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2871 tarc |= 1; 2872 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2873 } else if (adapter->hw.mac.type == e1000_82574) { 2874 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2875 tarc |= TARC_ERRATA_BIT; 2876 if ( adapter->tx_num_queues > 1) { 2877 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 2878 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2879 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2880 } else 2881 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2882 } 2883 2884 if (adapter->tx_int_delay.value > 0) 2885 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2886 2887 /* Program the Transmit Control Register */ 2888 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2889 tctl &= ~E1000_TCTL_CT; 2890 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2891 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 2892 2893 if (adapter->hw.mac.type >= e1000_82571) 2894 tctl |= E1000_TCTL_MULR; 2895 2896 /* This write will effectively turn on the transmit unit. */ 2897 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2898 2899 if (hw->mac.type == e1000_pch_spt) { 2900 u32 reg; 2901 reg = E1000_READ_REG(hw, E1000_IOSFPC); 2902 reg |= E1000_RCTL_RDMTS_HEX; 2903 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 2904 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2905 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 2906 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2907 } 2908 } 2909 2910 /********************************************************************* 2911 * 2912 * Enable receive unit. 2913 * 2914 **********************************************************************/ 2915 2916 static void 2917 em_initialize_receive_unit(if_ctx_t ctx) 2918 { 2919 struct adapter *adapter = iflib_get_softc(ctx); 2920 if_softc_ctx_t scctx = adapter->shared; 2921 struct ifnet *ifp = iflib_get_ifp(ctx); 2922 struct e1000_hw *hw = &adapter->hw; 2923 struct em_rx_queue *que; 2924 int i; 2925 u32 rctl, rxcsum, rfctl; 2926 2927 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 2928 2929 /* 2930 * Make sure receives are disabled while setting 2931 * up the descriptor ring 2932 */ 2933 rctl = E1000_READ_REG(hw, E1000_RCTL); 2934 /* Do not disable if ever enabled on this hardware */ 2935 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 2936 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2937 2938 /* Setup the Receive Control Register */ 2939 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2940 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 2941 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 2942 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2943 2944 /* Do not store bad packets */ 2945 rctl &= ~E1000_RCTL_SBP; 2946 2947 /* Enable Long Packet receive */ 2948 if (if_getmtu(ifp) > ETHERMTU) 2949 rctl |= E1000_RCTL_LPE; 2950 else 2951 rctl &= ~E1000_RCTL_LPE; 2952 2953 /* Strip the CRC */ 2954 if (!em_disable_crc_stripping) 2955 rctl |= E1000_RCTL_SECRC; 2956 2957 if (adapter->hw.mac.type >= e1000_82540) { 2958 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 2959 adapter->rx_abs_int_delay.value); 2960 2961 /* 2962 * Set the interrupt throttling rate. Value is calculated 2963 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2964 */ 2965 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 2966 } 2967 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 2968 adapter->rx_int_delay.value); 2969 2970 /* Use extended rx descriptor formats */ 2971 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2972 rfctl |= E1000_RFCTL_EXTEN; 2973 /* 2974 * When using MSIX interrupts we need to throttle 2975 * using the EITR register (82574 only) 2976 */ 2977 if (hw->mac.type == e1000_82574) { 2978 for (int i = 0; i < 4; i++) 2979 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 2980 DEFAULT_ITR); 2981 /* Disable accelerated acknowledge */ 2982 rfctl |= E1000_RFCTL_ACK_DIS; 2983 } 2984 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2985 2986 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2987 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 2988 adapter->hw.mac.type >= e1000_82543) { 2989 if (adapter->tx_num_queues > 1) { 2990 if (adapter->hw.mac.type >= igb_mac_min) { 2991 rxcsum |= E1000_RXCSUM_PCSD; 2992 if (hw->mac.type != e1000_82575) 2993 rxcsum |= E1000_RXCSUM_CRCOFL; 2994 } else 2995 rxcsum |= E1000_RXCSUM_TUOFL | 2996 E1000_RXCSUM_IPOFL | 2997 E1000_RXCSUM_PCSD; 2998 } else { 2999 if (adapter->hw.mac.type >= igb_mac_min) 3000 rxcsum |= E1000_RXCSUM_IPPCSE; 3001 else 3002 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3003 if (adapter->hw.mac.type > e1000_82575) 3004 rxcsum |= E1000_RXCSUM_CRCOFL; 3005 } 3006 } else 3007 rxcsum &= ~E1000_RXCSUM_TUOFL; 3008 3009 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3010 3011 if (adapter->rx_num_queues > 1) { 3012 if (adapter->hw.mac.type >= igb_mac_min) 3013 igb_initialize_rss_mapping(adapter); 3014 else 3015 em_initialize_rss_mapping(adapter); 3016 } 3017 3018 /* 3019 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3020 * long latencies are observed, like Lenovo X60. This 3021 * change eliminates the problem, but since having positive 3022 * values in RDTR is a known source of problems on other 3023 * platforms another solution is being sought. 3024 */ 3025 if (hw->mac.type == e1000_82573) 3026 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3027 3028 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3029 struct rx_ring *rxr = &que->rxr; 3030 /* Setup the Base and Length of the Rx Descriptor Ring */ 3031 u64 bus_addr = rxr->rx_paddr; 3032 #if 0 3033 u32 rdt = adapter->rx_num_queues -1; /* default */ 3034 #endif 3035 3036 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3037 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3038 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3039 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3040 /* Setup the Head and Tail Descriptor Pointers */ 3041 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3042 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3043 } 3044 3045 /* 3046 * Set PTHRESH for improved jumbo performance 3047 * According to 10.2.5.11 of Intel 82574 Datasheet, 3048 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3049 * Only write to RXDCTL(1) if there is a need for different 3050 * settings. 3051 */ 3052 3053 if (((adapter->hw.mac.type == e1000_ich9lan) || 3054 (adapter->hw.mac.type == e1000_pch2lan) || 3055 (adapter->hw.mac.type == e1000_ich10lan)) && 3056 (if_getmtu(ifp) > ETHERMTU)) { 3057 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3058 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3059 } else if (adapter->hw.mac.type == e1000_82574) { 3060 for (int i = 0; i < adapter->rx_num_queues; i++) { 3061 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3062 rxdctl |= 0x20; /* PTHRESH */ 3063 rxdctl |= 4 << 8; /* HTHRESH */ 3064 rxdctl |= 4 << 16;/* WTHRESH */ 3065 rxdctl |= 1 << 24; /* Switch to granularity */ 3066 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3067 } 3068 } else if (adapter->hw.mac.type >= igb_mac_min) { 3069 u32 psize, srrctl = 0; 3070 3071 if (if_getmtu(ifp) > ETHERMTU) { 3072 /* Set maximum packet len */ 3073 if (adapter->rx_mbuf_sz <= 4096) { 3074 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3075 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3076 } else if (adapter->rx_mbuf_sz > 4096) { 3077 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3078 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3079 } 3080 psize = scctx->isc_max_frame_size; 3081 /* are we on a vlan? */ 3082 if (ifp->if_vlantrunk != NULL) 3083 psize += VLAN_TAG_SIZE; 3084 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3085 } else { 3086 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3087 rctl |= E1000_RCTL_SZ_2048; 3088 } 3089 3090 /* 3091 * If TX flow control is disabled and there's >1 queue defined, 3092 * enable DROP. 3093 * 3094 * This drops frames rather than hanging the RX MAC for all queues. 3095 */ 3096 if ((adapter->rx_num_queues > 1) && 3097 (adapter->fc == e1000_fc_none || 3098 adapter->fc == e1000_fc_rx_pause)) { 3099 srrctl |= E1000_SRRCTL_DROP_EN; 3100 } 3101 /* Setup the Base and Length of the Rx Descriptor Rings */ 3102 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3103 struct rx_ring *rxr = &que->rxr; 3104 u64 bus_addr = rxr->rx_paddr; 3105 u32 rxdctl; 3106 3107 #ifdef notyet 3108 /* Configure for header split? -- ignore for now */ 3109 rxr->hdr_split = igb_header_split; 3110 #else 3111 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3112 #endif 3113 3114 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3115 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3116 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3117 (uint32_t)(bus_addr >> 32)); 3118 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3119 (uint32_t)bus_addr); 3120 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3121 /* Enable this Queue */ 3122 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3123 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3124 rxdctl &= 0xFFF00000; 3125 rxdctl |= IGB_RX_PTHRESH; 3126 rxdctl |= IGB_RX_HTHRESH << 8; 3127 rxdctl |= IGB_RX_WTHRESH << 16; 3128 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3129 } 3130 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3131 if (if_getmtu(ifp) > ETHERMTU) 3132 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3133 else 3134 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3135 } 3136 3137 /* Make sure VLAN Filters are off */ 3138 rctl &= ~E1000_RCTL_VFE; 3139 3140 if (adapter->hw.mac.type < igb_mac_min) { 3141 if (adapter->rx_mbuf_sz == MCLBYTES) 3142 rctl |= E1000_RCTL_SZ_2048; 3143 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3144 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3145 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3146 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3147 3148 /* ensure we clear use DTYPE of 00 here */ 3149 rctl &= ~0x00000C00; 3150 } 3151 3152 /* Write out the settings */ 3153 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3154 3155 return; 3156 } 3157 3158 static void 3159 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3160 { 3161 struct adapter *adapter = iflib_get_softc(ctx); 3162 u32 index, bit; 3163 3164 index = (vtag >> 5) & 0x7F; 3165 bit = vtag & 0x1F; 3166 adapter->shadow_vfta[index] |= (1 << bit); 3167 ++adapter->num_vlans; 3168 } 3169 3170 static void 3171 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3172 { 3173 struct adapter *adapter = iflib_get_softc(ctx); 3174 u32 index, bit; 3175 3176 index = (vtag >> 5) & 0x7F; 3177 bit = vtag & 0x1F; 3178 adapter->shadow_vfta[index] &= ~(1 << bit); 3179 --adapter->num_vlans; 3180 } 3181 3182 static void 3183 em_setup_vlan_hw_support(struct adapter *adapter) 3184 { 3185 struct e1000_hw *hw = &adapter->hw; 3186 u32 reg; 3187 3188 /* 3189 * We get here thru init_locked, meaning 3190 * a soft reset, this has already cleared 3191 * the VFTA and other state, so if there 3192 * have been no vlan's registered do nothing. 3193 */ 3194 if (adapter->num_vlans == 0) 3195 return; 3196 3197 /* 3198 * A soft reset zero's out the VFTA, so 3199 * we need to repopulate it now. 3200 */ 3201 for (int i = 0; i < EM_VFTA_SIZE; i++) 3202 if (adapter->shadow_vfta[i] != 0) 3203 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3204 i, adapter->shadow_vfta[i]); 3205 3206 reg = E1000_READ_REG(hw, E1000_CTRL); 3207 reg |= E1000_CTRL_VME; 3208 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3209 3210 /* Enable the Filter Table */ 3211 reg = E1000_READ_REG(hw, E1000_RCTL); 3212 reg &= ~E1000_RCTL_CFIEN; 3213 reg |= E1000_RCTL_VFE; 3214 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3215 } 3216 3217 static void 3218 em_if_enable_intr(if_ctx_t ctx) 3219 { 3220 struct adapter *adapter = iflib_get_softc(ctx); 3221 struct e1000_hw *hw = &adapter->hw; 3222 u32 ims_mask = IMS_ENABLE_MASK; 3223 3224 if (hw->mac.type == e1000_82574) { 3225 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3226 ims_mask |= adapter->ims; 3227 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3228 u32 mask = (adapter->que_mask | adapter->link_mask); 3229 3230 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3231 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3232 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3233 ims_mask = E1000_IMS_LSC; 3234 } 3235 3236 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3237 } 3238 3239 static void 3240 em_if_disable_intr(if_ctx_t ctx) 3241 { 3242 struct adapter *adapter = iflib_get_softc(ctx); 3243 struct e1000_hw *hw = &adapter->hw; 3244 3245 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3246 if (hw->mac.type >= igb_mac_min) 3247 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3248 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3249 } 3250 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3251 } 3252 3253 /* 3254 * Bit of a misnomer, what this really means is 3255 * to enable OS management of the system... aka 3256 * to disable special hardware management features 3257 */ 3258 static void 3259 em_init_manageability(struct adapter *adapter) 3260 { 3261 /* A shared code workaround */ 3262 #define E1000_82542_MANC2H E1000_MANC2H 3263 if (adapter->has_manage) { 3264 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3265 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3266 3267 /* disable hardware interception of ARP */ 3268 manc &= ~(E1000_MANC_ARP_EN); 3269 3270 /* enable receiving management packets to the host */ 3271 manc |= E1000_MANC_EN_MNG2HOST; 3272 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3273 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3274 manc2h |= E1000_MNG2HOST_PORT_623; 3275 manc2h |= E1000_MNG2HOST_PORT_664; 3276 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3277 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3278 } 3279 } 3280 3281 /* 3282 * Give control back to hardware management 3283 * controller if there is one. 3284 */ 3285 static void 3286 em_release_manageability(struct adapter *adapter) 3287 { 3288 if (adapter->has_manage) { 3289 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3290 3291 /* re-enable hardware interception of ARP */ 3292 manc |= E1000_MANC_ARP_EN; 3293 manc &= ~E1000_MANC_EN_MNG2HOST; 3294 3295 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3296 } 3297 } 3298 3299 /* 3300 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3301 * For ASF and Pass Through versions of f/w this means 3302 * that the driver is loaded. For AMT version type f/w 3303 * this means that the network i/f is open. 3304 */ 3305 static void 3306 em_get_hw_control(struct adapter *adapter) 3307 { 3308 u32 ctrl_ext, swsm; 3309 3310 if (adapter->hw.mac.type == e1000_82573) { 3311 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3312 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3313 swsm | E1000_SWSM_DRV_LOAD); 3314 return; 3315 } 3316 /* else */ 3317 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3318 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3319 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3320 return; 3321 } 3322 3323 /* 3324 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3325 * For ASF and Pass Through versions of f/w this means that 3326 * the driver is no longer loaded. For AMT versions of the 3327 * f/w this means that the network i/f is closed. 3328 */ 3329 static void 3330 em_release_hw_control(struct adapter *adapter) 3331 { 3332 u32 ctrl_ext, swsm; 3333 3334 if (!adapter->has_manage) 3335 return; 3336 3337 if (adapter->hw.mac.type == e1000_82573) { 3338 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3339 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3340 swsm & ~E1000_SWSM_DRV_LOAD); 3341 return; 3342 } 3343 /* else */ 3344 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3345 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3346 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3347 return; 3348 } 3349 3350 static int 3351 em_is_valid_ether_addr(u8 *addr) 3352 { 3353 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3354 3355 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3356 return (FALSE); 3357 } 3358 3359 return (TRUE); 3360 } 3361 3362 /* 3363 ** Parse the interface capabilities with regard 3364 ** to both system management and wake-on-lan for 3365 ** later use. 3366 */ 3367 static void 3368 em_get_wakeup(if_ctx_t ctx) 3369 { 3370 struct adapter *adapter = iflib_get_softc(ctx); 3371 device_t dev = iflib_get_dev(ctx); 3372 u16 eeprom_data = 0, device_id, apme_mask; 3373 3374 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3375 apme_mask = EM_EEPROM_APME; 3376 3377 switch (adapter->hw.mac.type) { 3378 case e1000_82542: 3379 case e1000_82543: 3380 break; 3381 case e1000_82544: 3382 e1000_read_nvm(&adapter->hw, 3383 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3384 apme_mask = EM_82544_APME; 3385 break; 3386 case e1000_82546: 3387 case e1000_82546_rev_3: 3388 if (adapter->hw.bus.func == 1) { 3389 e1000_read_nvm(&adapter->hw, 3390 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3391 break; 3392 } else 3393 e1000_read_nvm(&adapter->hw, 3394 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3395 break; 3396 case e1000_82573: 3397 case e1000_82583: 3398 adapter->has_amt = TRUE; 3399 /* FALLTHROUGH */ 3400 case e1000_82571: 3401 case e1000_82572: 3402 case e1000_80003es2lan: 3403 if (adapter->hw.bus.func == 1) { 3404 e1000_read_nvm(&adapter->hw, 3405 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3406 break; 3407 } else 3408 e1000_read_nvm(&adapter->hw, 3409 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3410 break; 3411 case e1000_ich8lan: 3412 case e1000_ich9lan: 3413 case e1000_ich10lan: 3414 case e1000_pchlan: 3415 case e1000_pch2lan: 3416 case e1000_pch_lpt: 3417 case e1000_pch_spt: 3418 case e1000_82575: /* listing all igb devices */ 3419 case e1000_82576: 3420 case e1000_82580: 3421 case e1000_i350: 3422 case e1000_i354: 3423 case e1000_i210: 3424 case e1000_i211: 3425 case e1000_vfadapt: 3426 case e1000_vfadapt_i350: 3427 apme_mask = E1000_WUC_APME; 3428 adapter->has_amt = TRUE; 3429 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3430 break; 3431 default: 3432 e1000_read_nvm(&adapter->hw, 3433 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3434 break; 3435 } 3436 if (eeprom_data & apme_mask) 3437 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3438 /* 3439 * We have the eeprom settings, now apply the special cases 3440 * where the eeprom may be wrong or the board won't support 3441 * wake on lan on a particular port 3442 */ 3443 device_id = pci_get_device(dev); 3444 switch (device_id) { 3445 case E1000_DEV_ID_82546GB_PCIE: 3446 adapter->wol = 0; 3447 break; 3448 case E1000_DEV_ID_82546EB_FIBER: 3449 case E1000_DEV_ID_82546GB_FIBER: 3450 /* Wake events only supported on port A for dual fiber 3451 * regardless of eeprom setting */ 3452 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3453 E1000_STATUS_FUNC_1) 3454 adapter->wol = 0; 3455 break; 3456 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3457 /* if quad port adapter, disable WoL on all but port A */ 3458 if (global_quad_port_a != 0) 3459 adapter->wol = 0; 3460 /* Reset for multiple quad port adapters */ 3461 if (++global_quad_port_a == 4) 3462 global_quad_port_a = 0; 3463 break; 3464 case E1000_DEV_ID_82571EB_FIBER: 3465 /* Wake events only supported on port A for dual fiber 3466 * regardless of eeprom setting */ 3467 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3468 E1000_STATUS_FUNC_1) 3469 adapter->wol = 0; 3470 break; 3471 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3472 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3473 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3474 /* if quad port adapter, disable WoL on all but port A */ 3475 if (global_quad_port_a != 0) 3476 adapter->wol = 0; 3477 /* Reset for multiple quad port adapters */ 3478 if (++global_quad_port_a == 4) 3479 global_quad_port_a = 0; 3480 break; 3481 } 3482 return; 3483 } 3484 3485 3486 /* 3487 * Enable PCI Wake On Lan capability 3488 */ 3489 static void 3490 em_enable_wakeup(if_ctx_t ctx) 3491 { 3492 struct adapter *adapter = iflib_get_softc(ctx); 3493 device_t dev = iflib_get_dev(ctx); 3494 if_t ifp = iflib_get_ifp(ctx); 3495 u32 pmc, ctrl, ctrl_ext, rctl, wuc; 3496 u16 status; 3497 3498 if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) 3499 return; 3500 3501 /* Advertise the wakeup capability */ 3502 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3503 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3504 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3505 wuc = E1000_READ_REG(&adapter->hw, E1000_WUC); 3506 wuc |= (E1000_WUC_PME_EN | E1000_WUC_APME); 3507 E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc); 3508 3509 if ((adapter->hw.mac.type == e1000_ich8lan) || 3510 (adapter->hw.mac.type == e1000_pchlan) || 3511 (adapter->hw.mac.type == e1000_ich9lan) || 3512 (adapter->hw.mac.type == e1000_ich10lan)) 3513 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3514 3515 /* Keep the laser running on Fiber adapters */ 3516 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3517 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3518 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3519 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3520 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3521 } 3522 3523 /* 3524 * Determine type of Wakeup: note that wol 3525 * is set with all bits on by default. 3526 */ 3527 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3528 adapter->wol &= ~E1000_WUFC_MAG; 3529 3530 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3531 adapter->wol &= ~E1000_WUFC_EX; 3532 3533 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3534 adapter->wol &= ~E1000_WUFC_MC; 3535 else { 3536 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3537 rctl |= E1000_RCTL_MPE; 3538 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3539 } 3540 3541 if ( adapter->hw.mac.type >= e1000_pchlan) { 3542 if (em_enable_phy_wakeup(adapter)) 3543 return; 3544 } else { 3545 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3546 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3547 } 3548 3549 if (adapter->hw.phy.type == e1000_phy_igp_3) 3550 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3551 3552 /* Request PME */ 3553 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3554 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3555 if (if_getcapenable(ifp) & IFCAP_WOL) 3556 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3557 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3558 3559 return; 3560 } 3561 3562 /* 3563 * WOL in the newer chipset interfaces (pchlan) 3564 * require thing to be copied into the phy 3565 */ 3566 static int 3567 em_enable_phy_wakeup(struct adapter *adapter) 3568 { 3569 struct e1000_hw *hw = &adapter->hw; 3570 u32 mreg, ret = 0; 3571 u16 preg; 3572 3573 /* copy MAC RARs to PHY RARs */ 3574 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3575 3576 /* copy MAC MTA to PHY MTA */ 3577 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3578 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3579 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3580 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3581 (u16)((mreg >> 16) & 0xFFFF)); 3582 } 3583 3584 /* configure PHY Rx Control register */ 3585 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3586 mreg = E1000_READ_REG(hw, E1000_RCTL); 3587 if (mreg & E1000_RCTL_UPE) 3588 preg |= BM_RCTL_UPE; 3589 if (mreg & E1000_RCTL_MPE) 3590 preg |= BM_RCTL_MPE; 3591 preg &= ~(BM_RCTL_MO_MASK); 3592 if (mreg & E1000_RCTL_MO_3) 3593 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3594 << BM_RCTL_MO_SHIFT); 3595 if (mreg & E1000_RCTL_BAM) 3596 preg |= BM_RCTL_BAM; 3597 if (mreg & E1000_RCTL_PMCF) 3598 preg |= BM_RCTL_PMCF; 3599 mreg = E1000_READ_REG(hw, E1000_CTRL); 3600 if (mreg & E1000_CTRL_RFCE) 3601 preg |= BM_RCTL_RFCE; 3602 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3603 3604 /* enable PHY wakeup in MAC register */ 3605 E1000_WRITE_REG(hw, E1000_WUC, 3606 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3607 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3608 3609 /* configure and enable PHY wakeup in PHY registers */ 3610 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3611 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3612 3613 /* activate PHY wakeup */ 3614 ret = hw->phy.ops.acquire(hw); 3615 if (ret) { 3616 printf("Could not acquire PHY\n"); 3617 return ret; 3618 } 3619 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3620 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3621 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3622 if (ret) { 3623 printf("Could not read PHY page 769\n"); 3624 goto out; 3625 } 3626 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3627 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3628 if (ret) 3629 printf("Could not set PHY Host Wakeup bit\n"); 3630 out: 3631 hw->phy.ops.release(hw); 3632 3633 return ret; 3634 } 3635 3636 static void 3637 em_if_led_func(if_ctx_t ctx, int onoff) 3638 { 3639 struct adapter *adapter = iflib_get_softc(ctx); 3640 3641 if (onoff) { 3642 e1000_setup_led(&adapter->hw); 3643 e1000_led_on(&adapter->hw); 3644 } else { 3645 e1000_led_off(&adapter->hw); 3646 e1000_cleanup_led(&adapter->hw); 3647 } 3648 } 3649 3650 /* 3651 * Disable the L0S and L1 LINK states 3652 */ 3653 static void 3654 em_disable_aspm(struct adapter *adapter) 3655 { 3656 int base, reg; 3657 u16 link_cap,link_ctrl; 3658 device_t dev = adapter->dev; 3659 3660 switch (adapter->hw.mac.type) { 3661 case e1000_82573: 3662 case e1000_82574: 3663 case e1000_82583: 3664 break; 3665 default: 3666 return; 3667 } 3668 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3669 return; 3670 reg = base + PCIER_LINK_CAP; 3671 link_cap = pci_read_config(dev, reg, 2); 3672 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3673 return; 3674 reg = base + PCIER_LINK_CTL; 3675 link_ctrl = pci_read_config(dev, reg, 2); 3676 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3677 pci_write_config(dev, reg, link_ctrl, 2); 3678 return; 3679 } 3680 3681 /********************************************************************** 3682 * 3683 * Update the board statistics counters. 3684 * 3685 **********************************************************************/ 3686 static void 3687 em_update_stats_counters(struct adapter *adapter) 3688 { 3689 3690 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3691 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3692 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3693 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3694 } 3695 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3696 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3697 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3698 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3699 3700 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3701 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3702 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3703 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3704 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3705 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3706 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3707 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3708 /* 3709 ** For watchdog management we need to know if we have been 3710 ** paused during the last interval, so capture that here. 3711 */ 3712 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3713 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3714 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3715 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3716 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3717 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3718 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3719 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3720 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3721 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3722 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3723 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3724 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3725 3726 /* For the 64-bit byte counters the low dword must be read first. */ 3727 /* Both registers clear on the read of the high dword */ 3728 3729 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3730 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3731 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3732 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3733 3734 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3735 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3736 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3737 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3738 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3739 3740 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3741 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3742 3743 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3744 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3745 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3746 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3747 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3748 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3749 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3750 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3751 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3752 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3753 3754 /* Interrupt Counts */ 3755 3756 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3757 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3758 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3759 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3760 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3761 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3762 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3763 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3764 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3765 3766 if (adapter->hw.mac.type >= e1000_82543) { 3767 adapter->stats.algnerrc += 3768 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3769 adapter->stats.rxerrc += 3770 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3771 adapter->stats.tncrs += 3772 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3773 adapter->stats.cexterr += 3774 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3775 adapter->stats.tsctc += 3776 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3777 adapter->stats.tsctfc += 3778 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3779 } 3780 } 3781 3782 static uint64_t 3783 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3784 { 3785 struct adapter *adapter = iflib_get_softc(ctx); 3786 struct ifnet *ifp = iflib_get_ifp(ctx); 3787 3788 switch (cnt) { 3789 case IFCOUNTER_COLLISIONS: 3790 return (adapter->stats.colc); 3791 case IFCOUNTER_IERRORS: 3792 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3793 adapter->stats.crcerrs + adapter->stats.algnerrc + 3794 adapter->stats.ruc + adapter->stats.roc + 3795 adapter->stats.mpc + adapter->stats.cexterr); 3796 case IFCOUNTER_OERRORS: 3797 return (adapter->stats.ecol + adapter->stats.latecol + 3798 adapter->watchdog_events); 3799 default: 3800 return (if_get_counter_default(ifp, cnt)); 3801 } 3802 } 3803 3804 /* Export a single 32-bit register via a read-only sysctl. */ 3805 static int 3806 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3807 { 3808 struct adapter *adapter; 3809 u_int val; 3810 3811 adapter = oidp->oid_arg1; 3812 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3813 return (sysctl_handle_int(oidp, &val, 0, req)); 3814 } 3815 3816 /* 3817 * Add sysctl variables, one per statistic, to the system. 3818 */ 3819 static void 3820 em_add_hw_stats(struct adapter *adapter) 3821 { 3822 device_t dev = iflib_get_dev(adapter->ctx); 3823 struct em_tx_queue *tx_que = adapter->tx_queues; 3824 struct em_rx_queue *rx_que = adapter->rx_queues; 3825 3826 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3827 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3828 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3829 struct e1000_hw_stats *stats = &adapter->stats; 3830 3831 struct sysctl_oid *stat_node, *queue_node, *int_node; 3832 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3833 3834 #define QUEUE_NAME_LEN 32 3835 char namebuf[QUEUE_NAME_LEN]; 3836 3837 /* Driver Statistics */ 3838 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3839 CTLFLAG_RD, &adapter->dropped_pkts, 3840 "Driver dropped packets"); 3841 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3842 CTLFLAG_RD, &adapter->link_irq, 3843 "Link MSIX IRQ Handled"); 3844 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 3845 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 3846 "Defragmenting mbuf chain failed"); 3847 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 3848 CTLFLAG_RD, &adapter->no_tx_dma_setup, 3849 "Driver tx dma failure in xmit"); 3850 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3851 CTLFLAG_RD, &adapter->rx_overruns, 3852 "RX overruns"); 3853 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 3854 CTLFLAG_RD, &adapter->watchdog_events, 3855 "Watchdog timeouts"); 3856 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 3857 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 3858 em_sysctl_reg_handler, "IU", 3859 "Device Control Register"); 3860 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 3861 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 3862 em_sysctl_reg_handler, "IU", 3863 "Receiver Control Register"); 3864 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 3865 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 3866 "Flow Control High Watermark"); 3867 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 3868 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 3869 "Flow Control Low Watermark"); 3870 3871 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3872 struct tx_ring *txr = &tx_que->txr; 3873 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 3874 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3875 CTLFLAG_RD, NULL, "TX Queue Name"); 3876 queue_list = SYSCTL_CHILDREN(queue_node); 3877 3878 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 3879 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3880 E1000_TDH(txr->me), 3881 em_sysctl_reg_handler, "IU", 3882 "Transmit Descriptor Head"); 3883 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 3884 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3885 E1000_TDT(txr->me), 3886 em_sysctl_reg_handler, "IU", 3887 "Transmit Descriptor Tail"); 3888 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 3889 CTLFLAG_RD, &txr->tx_irq, 3890 "Queue MSI-X Transmit Interrupts"); 3891 } 3892 3893 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 3894 struct rx_ring *rxr = &rx_que->rxr; 3895 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 3896 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3897 CTLFLAG_RD, NULL, "RX Queue Name"); 3898 queue_list = SYSCTL_CHILDREN(queue_node); 3899 3900 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 3901 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3902 E1000_RDH(rxr->me), 3903 em_sysctl_reg_handler, "IU", 3904 "Receive Descriptor Head"); 3905 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 3906 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3907 E1000_RDT(rxr->me), 3908 em_sysctl_reg_handler, "IU", 3909 "Receive Descriptor Tail"); 3910 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 3911 CTLFLAG_RD, &rxr->rx_irq, 3912 "Queue MSI-X Receive Interrupts"); 3913 } 3914 3915 /* MAC stats get their own sub node */ 3916 3917 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 3918 CTLFLAG_RD, NULL, "Statistics"); 3919 stat_list = SYSCTL_CHILDREN(stat_node); 3920 3921 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 3922 CTLFLAG_RD, &stats->ecol, 3923 "Excessive collisions"); 3924 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 3925 CTLFLAG_RD, &stats->scc, 3926 "Single collisions"); 3927 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 3928 CTLFLAG_RD, &stats->mcc, 3929 "Multiple collisions"); 3930 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 3931 CTLFLAG_RD, &stats->latecol, 3932 "Late collisions"); 3933 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 3934 CTLFLAG_RD, &stats->colc, 3935 "Collision Count"); 3936 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 3937 CTLFLAG_RD, &adapter->stats.symerrs, 3938 "Symbol Errors"); 3939 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 3940 CTLFLAG_RD, &adapter->stats.sec, 3941 "Sequence Errors"); 3942 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 3943 CTLFLAG_RD, &adapter->stats.dc, 3944 "Defer Count"); 3945 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 3946 CTLFLAG_RD, &adapter->stats.mpc, 3947 "Missed Packets"); 3948 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 3949 CTLFLAG_RD, &adapter->stats.rnbc, 3950 "Receive No Buffers"); 3951 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 3952 CTLFLAG_RD, &adapter->stats.ruc, 3953 "Receive Undersize"); 3954 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 3955 CTLFLAG_RD, &adapter->stats.rfc, 3956 "Fragmented Packets Received "); 3957 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 3958 CTLFLAG_RD, &adapter->stats.roc, 3959 "Oversized Packets Received"); 3960 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 3961 CTLFLAG_RD, &adapter->stats.rjc, 3962 "Recevied Jabber"); 3963 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 3964 CTLFLAG_RD, &adapter->stats.rxerrc, 3965 "Receive Errors"); 3966 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 3967 CTLFLAG_RD, &adapter->stats.crcerrs, 3968 "CRC errors"); 3969 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 3970 CTLFLAG_RD, &adapter->stats.algnerrc, 3971 "Alignment Errors"); 3972 /* On 82575 these are collision counts */ 3973 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 3974 CTLFLAG_RD, &adapter->stats.cexterr, 3975 "Collision/Carrier extension errors"); 3976 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 3977 CTLFLAG_RD, &adapter->stats.xonrxc, 3978 "XON Received"); 3979 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 3980 CTLFLAG_RD, &adapter->stats.xontxc, 3981 "XON Transmitted"); 3982 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 3983 CTLFLAG_RD, &adapter->stats.xoffrxc, 3984 "XOFF Received"); 3985 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 3986 CTLFLAG_RD, &adapter->stats.xofftxc, 3987 "XOFF Transmitted"); 3988 3989 /* Packet Reception Stats */ 3990 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 3991 CTLFLAG_RD, &adapter->stats.tpr, 3992 "Total Packets Received "); 3993 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 3994 CTLFLAG_RD, &adapter->stats.gprc, 3995 "Good Packets Received"); 3996 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 3997 CTLFLAG_RD, &adapter->stats.bprc, 3998 "Broadcast Packets Received"); 3999 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4000 CTLFLAG_RD, &adapter->stats.mprc, 4001 "Multicast Packets Received"); 4002 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4003 CTLFLAG_RD, &adapter->stats.prc64, 4004 "64 byte frames received "); 4005 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4006 CTLFLAG_RD, &adapter->stats.prc127, 4007 "65-127 byte frames received"); 4008 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4009 CTLFLAG_RD, &adapter->stats.prc255, 4010 "128-255 byte frames received"); 4011 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4012 CTLFLAG_RD, &adapter->stats.prc511, 4013 "256-511 byte frames received"); 4014 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4015 CTLFLAG_RD, &adapter->stats.prc1023, 4016 "512-1023 byte frames received"); 4017 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4018 CTLFLAG_RD, &adapter->stats.prc1522, 4019 "1023-1522 byte frames received"); 4020 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4021 CTLFLAG_RD, &adapter->stats.gorc, 4022 "Good Octets Received"); 4023 4024 /* Packet Transmission Stats */ 4025 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4026 CTLFLAG_RD, &adapter->stats.gotc, 4027 "Good Octets Transmitted"); 4028 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4029 CTLFLAG_RD, &adapter->stats.tpt, 4030 "Total Packets Transmitted"); 4031 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4032 CTLFLAG_RD, &adapter->stats.gptc, 4033 "Good Packets Transmitted"); 4034 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4035 CTLFLAG_RD, &adapter->stats.bptc, 4036 "Broadcast Packets Transmitted"); 4037 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4038 CTLFLAG_RD, &adapter->stats.mptc, 4039 "Multicast Packets Transmitted"); 4040 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4041 CTLFLAG_RD, &adapter->stats.ptc64, 4042 "64 byte frames transmitted "); 4043 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4044 CTLFLAG_RD, &adapter->stats.ptc127, 4045 "65-127 byte frames transmitted"); 4046 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4047 CTLFLAG_RD, &adapter->stats.ptc255, 4048 "128-255 byte frames transmitted"); 4049 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4050 CTLFLAG_RD, &adapter->stats.ptc511, 4051 "256-511 byte frames transmitted"); 4052 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4053 CTLFLAG_RD, &adapter->stats.ptc1023, 4054 "512-1023 byte frames transmitted"); 4055 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4056 CTLFLAG_RD, &adapter->stats.ptc1522, 4057 "1024-1522 byte frames transmitted"); 4058 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4059 CTLFLAG_RD, &adapter->stats.tsctc, 4060 "TSO Contexts Transmitted"); 4061 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4062 CTLFLAG_RD, &adapter->stats.tsctfc, 4063 "TSO Contexts Failed"); 4064 4065 4066 /* Interrupt Stats */ 4067 4068 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4069 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4070 int_list = SYSCTL_CHILDREN(int_node); 4071 4072 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4073 CTLFLAG_RD, &adapter->stats.iac, 4074 "Interrupt Assertion Count"); 4075 4076 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4077 CTLFLAG_RD, &adapter->stats.icrxptc, 4078 "Interrupt Cause Rx Pkt Timer Expire Count"); 4079 4080 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4081 CTLFLAG_RD, &adapter->stats.icrxatc, 4082 "Interrupt Cause Rx Abs Timer Expire Count"); 4083 4084 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4085 CTLFLAG_RD, &adapter->stats.ictxptc, 4086 "Interrupt Cause Tx Pkt Timer Expire Count"); 4087 4088 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4089 CTLFLAG_RD, &adapter->stats.ictxatc, 4090 "Interrupt Cause Tx Abs Timer Expire Count"); 4091 4092 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4093 CTLFLAG_RD, &adapter->stats.ictxqec, 4094 "Interrupt Cause Tx Queue Empty Count"); 4095 4096 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4097 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4098 "Interrupt Cause Tx Queue Min Thresh Count"); 4099 4100 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4101 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4102 "Interrupt Cause Rx Desc Min Thresh Count"); 4103 4104 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4105 CTLFLAG_RD, &adapter->stats.icrxoc, 4106 "Interrupt Cause Receiver Overrun Count"); 4107 } 4108 4109 /********************************************************************** 4110 * 4111 * This routine provides a way to dump out the adapter eeprom, 4112 * often a useful debug/service tool. This only dumps the first 4113 * 32 words, stuff that matters is in that extent. 4114 * 4115 **********************************************************************/ 4116 static int 4117 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4118 { 4119 struct adapter *adapter = (struct adapter *)arg1; 4120 int error; 4121 int result; 4122 4123 result = -1; 4124 error = sysctl_handle_int(oidp, &result, 0, req); 4125 4126 if (error || !req->newptr) 4127 return (error); 4128 4129 /* 4130 * This value will cause a hex dump of the 4131 * first 32 16-bit words of the EEPROM to 4132 * the screen. 4133 */ 4134 if (result == 1) 4135 em_print_nvm_info(adapter); 4136 4137 return (error); 4138 } 4139 4140 static void 4141 em_print_nvm_info(struct adapter *adapter) 4142 { 4143 u16 eeprom_data; 4144 int i, j, row = 0; 4145 4146 /* Its a bit crude, but it gets the job done */ 4147 printf("\nInterface EEPROM Dump:\n"); 4148 printf("Offset\n0x0000 "); 4149 for (i = 0, j = 0; i < 32; i++, j++) { 4150 if (j == 8) { /* Make the offset block */ 4151 j = 0; ++row; 4152 printf("\n0x00%x0 ",row); 4153 } 4154 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4155 printf("%04x ", eeprom_data); 4156 } 4157 printf("\n"); 4158 } 4159 4160 static int 4161 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4162 { 4163 struct em_int_delay_info *info; 4164 struct adapter *adapter; 4165 u32 regval; 4166 int error, usecs, ticks; 4167 4168 info = (struct em_int_delay_info *) arg1; 4169 usecs = info->value; 4170 error = sysctl_handle_int(oidp, &usecs, 0, req); 4171 if (error != 0 || req->newptr == NULL) 4172 return (error); 4173 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4174 return (EINVAL); 4175 info->value = usecs; 4176 ticks = EM_USECS_TO_TICKS(usecs); 4177 if (info->offset == E1000_ITR) /* units are 256ns here */ 4178 ticks *= 4; 4179 4180 adapter = info->adapter; 4181 4182 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4183 regval = (regval & ~0xffff) | (ticks & 0xffff); 4184 /* Handle a few special cases. */ 4185 switch (info->offset) { 4186 case E1000_RDTR: 4187 break; 4188 case E1000_TIDV: 4189 if (ticks == 0) { 4190 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4191 /* Don't write 0 into the TIDV register. */ 4192 regval++; 4193 } else 4194 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4195 break; 4196 } 4197 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4198 return (0); 4199 } 4200 4201 static void 4202 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4203 const char *description, struct em_int_delay_info *info, 4204 int offset, int value) 4205 { 4206 info->adapter = adapter; 4207 info->offset = offset; 4208 info->value = value; 4209 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4210 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4211 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4212 info, 0, em_sysctl_int_delay, "I", description); 4213 } 4214 4215 /* 4216 * Set flow control using sysctl: 4217 * Flow control values: 4218 * 0 - off 4219 * 1 - rx pause 4220 * 2 - tx pause 4221 * 3 - full 4222 */ 4223 static int 4224 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4225 { 4226 int error; 4227 static int input = 3; /* default is full */ 4228 struct adapter *adapter = (struct adapter *) arg1; 4229 4230 error = sysctl_handle_int(oidp, &input, 0, req); 4231 4232 if ((error) || (req->newptr == NULL)) 4233 return (error); 4234 4235 if (input == adapter->fc) /* no change? */ 4236 return (error); 4237 4238 switch (input) { 4239 case e1000_fc_rx_pause: 4240 case e1000_fc_tx_pause: 4241 case e1000_fc_full: 4242 case e1000_fc_none: 4243 adapter->hw.fc.requested_mode = input; 4244 adapter->fc = input; 4245 break; 4246 default: 4247 /* Do nothing */ 4248 return (error); 4249 } 4250 4251 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4252 e1000_force_mac_fc(&adapter->hw); 4253 return (error); 4254 } 4255 4256 /* 4257 * Manage Energy Efficient Ethernet: 4258 * Control values: 4259 * 0/1 - enabled/disabled 4260 */ 4261 static int 4262 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4263 { 4264 struct adapter *adapter = (struct adapter *) arg1; 4265 int error, value; 4266 4267 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4268 error = sysctl_handle_int(oidp, &value, 0, req); 4269 if (error || req->newptr == NULL) 4270 return (error); 4271 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4272 em_if_init(adapter->ctx); 4273 4274 return (0); 4275 } 4276 4277 static int 4278 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4279 { 4280 struct adapter *adapter; 4281 int error; 4282 int result; 4283 4284 result = -1; 4285 error = sysctl_handle_int(oidp, &result, 0, req); 4286 4287 if (error || !req->newptr) 4288 return (error); 4289 4290 if (result == 1) { 4291 adapter = (struct adapter *) arg1; 4292 em_print_debug_info(adapter); 4293 } 4294 4295 return (error); 4296 } 4297 4298 static int 4299 em_get_rs(SYSCTL_HANDLER_ARGS) 4300 { 4301 struct adapter *adapter = (struct adapter *) arg1; 4302 int error; 4303 int result; 4304 4305 result = 0; 4306 error = sysctl_handle_int(oidp, &result, 0, req); 4307 4308 if (error || !req->newptr || result != 1) 4309 return (error); 4310 em_dump_rs(adapter); 4311 4312 return (error); 4313 } 4314 4315 static void 4316 em_if_debug(if_ctx_t ctx) 4317 { 4318 em_dump_rs(iflib_get_softc(ctx)); 4319 } 4320 4321 /* 4322 * This routine is meant to be fluid, add whatever is 4323 * needed for debugging a problem. -jfv 4324 */ 4325 static void 4326 em_print_debug_info(struct adapter *adapter) 4327 { 4328 device_t dev = iflib_get_dev(adapter->ctx); 4329 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4330 struct tx_ring *txr = &adapter->tx_queues->txr; 4331 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4332 4333 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4334 printf("Interface is RUNNING "); 4335 else 4336 printf("Interface is NOT RUNNING\n"); 4337 4338 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4339 printf("and INACTIVE\n"); 4340 else 4341 printf("and ACTIVE\n"); 4342 4343 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4344 device_printf(dev, "TX Queue %d ------\n", i); 4345 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4346 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4347 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4348 4349 } 4350 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4351 device_printf(dev, "RX Queue %d ------\n", j); 4352 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4353 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4354 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4355 } 4356 } 4357 4358 /* 4359 * 82574 only: 4360 * Write a new value to the EEPROM increasing the number of MSIX 4361 * vectors from 3 to 5, for proper multiqueue support. 4362 */ 4363 static void 4364 em_enable_vectors_82574(if_ctx_t ctx) 4365 { 4366 struct adapter *adapter = iflib_get_softc(ctx); 4367 struct e1000_hw *hw = &adapter->hw; 4368 device_t dev = iflib_get_dev(ctx); 4369 u16 edata; 4370 4371 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4372 printf("Current cap: %#06x\n", edata); 4373 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4374 device_printf(dev, "Writing to eeprom: increasing " 4375 "reported MSIX vectors from 3 to 5...\n"); 4376 edata &= ~(EM_NVM_MSIX_N_MASK); 4377 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4378 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4379 e1000_update_nvm_checksum(hw); 4380 device_printf(dev, "Writing to eeprom: done\n"); 4381 } 4382 } 4383