1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static bool em_automask_tso(if_ctx_t); 334 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 335 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 336 const char *, struct em_int_delay_info *, int, int); 337 /* Management and WOL Support */ 338 static void em_init_manageability(struct e1000_softc *); 339 static void em_release_manageability(struct e1000_softc *); 340 static void em_get_hw_control(struct e1000_softc *); 341 static void em_release_hw_control(struct e1000_softc *); 342 static void em_get_wakeup(if_ctx_t); 343 static void em_enable_wakeup(if_ctx_t); 344 static int em_enable_phy_wakeup(struct e1000_softc *); 345 static void em_disable_aspm(struct e1000_softc *); 346 347 int em_intr(void *); 348 349 /* MSI-X handlers */ 350 static int em_if_msix_intr_assign(if_ctx_t, int); 351 static int em_msix_link(void *); 352 static void em_handle_link(void *); 353 354 static void em_enable_vectors_82574(if_ctx_t); 355 356 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 357 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 358 static void em_if_led_func(if_ctx_t, int); 359 360 static int em_get_regs(SYSCTL_HANDLER_ARGS); 361 362 static void lem_smartspeed(struct e1000_softc *); 363 static void igb_configure_queues(struct e1000_softc *); 364 static void em_flush_desc_rings(struct e1000_softc *); 365 366 367 /********************************************************************* 368 * FreeBSD Device Interface Entry Points 369 *********************************************************************/ 370 static device_method_t em_methods[] = { 371 /* Device interface */ 372 DEVMETHOD(device_register, em_register), 373 DEVMETHOD(device_probe, iflib_device_probe), 374 DEVMETHOD(device_attach, iflib_device_attach), 375 DEVMETHOD(device_detach, iflib_device_detach), 376 DEVMETHOD(device_shutdown, iflib_device_shutdown), 377 DEVMETHOD(device_suspend, iflib_device_suspend), 378 DEVMETHOD(device_resume, iflib_device_resume), 379 DEVMETHOD_END 380 }; 381 382 static device_method_t igb_methods[] = { 383 /* Device interface */ 384 DEVMETHOD(device_register, igb_register), 385 DEVMETHOD(device_probe, iflib_device_probe), 386 DEVMETHOD(device_attach, iflib_device_attach), 387 DEVMETHOD(device_detach, iflib_device_detach), 388 DEVMETHOD(device_shutdown, iflib_device_shutdown), 389 DEVMETHOD(device_suspend, iflib_device_suspend), 390 DEVMETHOD(device_resume, iflib_device_resume), 391 DEVMETHOD_END 392 }; 393 394 395 static driver_t em_driver = { 396 "em", em_methods, sizeof(struct e1000_softc), 397 }; 398 399 DRIVER_MODULE(em, pci, em_driver, 0, 0); 400 401 MODULE_DEPEND(em, pci, 1, 1, 1); 402 MODULE_DEPEND(em, ether, 1, 1, 1); 403 MODULE_DEPEND(em, iflib, 1, 1, 1); 404 405 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 406 407 static driver_t igb_driver = { 408 "igb", igb_methods, sizeof(struct e1000_softc), 409 }; 410 411 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 412 413 MODULE_DEPEND(igb, pci, 1, 1, 1); 414 MODULE_DEPEND(igb, ether, 1, 1, 1); 415 MODULE_DEPEND(igb, iflib, 1, 1, 1); 416 417 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 418 419 static device_method_t em_if_methods[] = { 420 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 421 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 422 DEVMETHOD(ifdi_detach, em_if_detach), 423 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 424 DEVMETHOD(ifdi_suspend, em_if_suspend), 425 DEVMETHOD(ifdi_resume, em_if_resume), 426 DEVMETHOD(ifdi_init, em_if_init), 427 DEVMETHOD(ifdi_stop, em_if_stop), 428 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 429 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 430 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 431 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 432 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 433 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 434 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 435 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 436 DEVMETHOD(ifdi_media_status, em_if_media_status), 437 DEVMETHOD(ifdi_media_change, em_if_media_change), 438 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 439 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 440 DEVMETHOD(ifdi_timer, em_if_timer), 441 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 442 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 443 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 444 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 445 DEVMETHOD(ifdi_led_func, em_if_led_func), 446 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 447 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 448 DEVMETHOD(ifdi_debug, em_if_debug), 449 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 450 DEVMETHOD_END 451 }; 452 453 static driver_t em_if_driver = { 454 "em_if", em_if_methods, sizeof(struct e1000_softc) 455 }; 456 457 static device_method_t igb_if_methods[] = { 458 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 459 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 460 DEVMETHOD(ifdi_detach, em_if_detach), 461 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 462 DEVMETHOD(ifdi_suspend, em_if_suspend), 463 DEVMETHOD(ifdi_resume, em_if_resume), 464 DEVMETHOD(ifdi_init, em_if_init), 465 DEVMETHOD(ifdi_stop, em_if_stop), 466 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 467 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 468 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 469 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 470 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 471 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 472 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 473 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 474 DEVMETHOD(ifdi_media_status, em_if_media_status), 475 DEVMETHOD(ifdi_media_change, em_if_media_change), 476 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 477 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 478 DEVMETHOD(ifdi_timer, em_if_timer), 479 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 480 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 481 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 482 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 483 DEVMETHOD(ifdi_led_func, em_if_led_func), 484 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 485 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 486 DEVMETHOD(ifdi_debug, em_if_debug), 487 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 488 DEVMETHOD_END 489 }; 490 491 static driver_t igb_if_driver = { 492 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 493 }; 494 495 /********************************************************************* 496 * Tunable default values. 497 *********************************************************************/ 498 499 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 500 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 501 502 #define MAX_INTS_PER_SEC 8000 503 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 504 505 /* Allow common code without TSO */ 506 #ifndef CSUM_TSO 507 #define CSUM_TSO 0 508 #endif 509 510 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 511 "EM driver parameters"); 512 513 static int em_disable_crc_stripping = 0; 514 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 515 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 516 517 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 518 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 519 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 520 0, "Default transmit interrupt delay in usecs"); 521 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 522 0, "Default receive interrupt delay in usecs"); 523 524 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 525 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 526 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 527 &em_tx_abs_int_delay_dflt, 0, 528 "Default transmit interrupt delay limit in usecs"); 529 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 530 &em_rx_abs_int_delay_dflt, 0, 531 "Default receive interrupt delay limit in usecs"); 532 533 static int em_smart_pwr_down = false; 534 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 535 0, "Set to true to leave smart power down enabled on newer adapters"); 536 537 static bool em_unsupported_tso = false; 538 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 539 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 540 541 /* Controls whether promiscuous also shows bad packets */ 542 static int em_debug_sbp = false; 543 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 544 "Show bad packets in promiscuous mode"); 545 546 /* How many packets rxeof tries to clean at a time */ 547 static int em_rx_process_limit = 100; 548 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 549 &em_rx_process_limit, 0, 550 "Maximum number of received packets to process " 551 "at a time, -1 means unlimited"); 552 553 /* Energy efficient ethernet - default to OFF */ 554 static int eee_setting = 1; 555 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 556 "Enable Energy Efficient Ethernet"); 557 558 /* 559 ** Tuneable Interrupt rate 560 */ 561 static int em_max_interrupt_rate = 8000; 562 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 563 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 564 565 566 567 /* Global used in WOL setup with multiport cards */ 568 static int global_quad_port_a = 0; 569 570 extern struct if_txrx igb_txrx; 571 extern struct if_txrx em_txrx; 572 extern struct if_txrx lem_txrx; 573 574 static struct if_shared_ctx em_sctx_init = { 575 .isc_magic = IFLIB_MAGIC, 576 .isc_q_align = PAGE_SIZE, 577 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 578 .isc_tx_maxsegsize = PAGE_SIZE, 579 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 580 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 581 .isc_rx_maxsize = MJUM9BYTES, 582 .isc_rx_nsegments = 1, 583 .isc_rx_maxsegsize = MJUM9BYTES, 584 .isc_nfl = 1, 585 .isc_nrxqs = 1, 586 .isc_ntxqs = 1, 587 .isc_admin_intrcnt = 1, 588 .isc_vendor_info = em_vendor_info_array, 589 .isc_driver_version = em_driver_version, 590 .isc_driver = &em_if_driver, 591 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 592 593 .isc_nrxd_min = {EM_MIN_RXD}, 594 .isc_ntxd_min = {EM_MIN_TXD}, 595 .isc_nrxd_max = {EM_MAX_RXD}, 596 .isc_ntxd_max = {EM_MAX_TXD}, 597 .isc_nrxd_default = {EM_DEFAULT_RXD}, 598 .isc_ntxd_default = {EM_DEFAULT_TXD}, 599 }; 600 601 static struct if_shared_ctx igb_sctx_init = { 602 .isc_magic = IFLIB_MAGIC, 603 .isc_q_align = PAGE_SIZE, 604 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 605 .isc_tx_maxsegsize = PAGE_SIZE, 606 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 607 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 608 .isc_rx_maxsize = MJUM9BYTES, 609 .isc_rx_nsegments = 1, 610 .isc_rx_maxsegsize = MJUM9BYTES, 611 .isc_nfl = 1, 612 .isc_nrxqs = 1, 613 .isc_ntxqs = 1, 614 .isc_admin_intrcnt = 1, 615 .isc_vendor_info = igb_vendor_info_array, 616 .isc_driver_version = igb_driver_version, 617 .isc_driver = &igb_if_driver, 618 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 619 620 .isc_nrxd_min = {EM_MIN_RXD}, 621 .isc_ntxd_min = {EM_MIN_TXD}, 622 .isc_nrxd_max = {IGB_MAX_RXD}, 623 .isc_ntxd_max = {IGB_MAX_TXD}, 624 .isc_nrxd_default = {EM_DEFAULT_RXD}, 625 .isc_ntxd_default = {EM_DEFAULT_TXD}, 626 }; 627 628 /***************************************************************** 629 * 630 * Dump Registers 631 * 632 ****************************************************************/ 633 #define IGB_REGS_LEN 739 634 635 static int em_get_regs(SYSCTL_HANDLER_ARGS) 636 { 637 struct e1000_softc *sc = (struct e1000_softc *)arg1; 638 struct e1000_hw *hw = &sc->hw; 639 struct sbuf *sb; 640 u32 *regs_buff; 641 int rc; 642 643 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 644 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 645 646 rc = sysctl_wire_old_buffer(req, 0); 647 MPASS(rc == 0); 648 if (rc != 0) { 649 free(regs_buff, M_DEVBUF); 650 return (rc); 651 } 652 653 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 654 MPASS(sb != NULL); 655 if (sb == NULL) { 656 free(regs_buff, M_DEVBUF); 657 return (ENOMEM); 658 } 659 660 /* General Registers */ 661 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 662 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 663 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 664 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 665 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 666 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 667 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 668 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 669 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 670 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 671 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 672 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 673 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 674 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 675 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 676 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 677 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 678 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 679 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 680 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 681 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 682 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 683 684 sbuf_printf(sb, "General Registers\n"); 685 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 686 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 687 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 688 689 sbuf_printf(sb, "Interrupt Registers\n"); 690 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 691 692 sbuf_printf(sb, "RX Registers\n"); 693 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 694 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 695 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 696 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 697 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 698 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 699 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 700 701 sbuf_printf(sb, "TX Registers\n"); 702 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 703 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 704 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 705 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 706 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 707 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 708 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 709 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 710 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 711 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 712 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 713 714 free(regs_buff, M_DEVBUF); 715 716 #ifdef DUMP_DESCS 717 { 718 if_softc_ctx_t scctx = sc->shared; 719 struct rx_ring *rxr = &rx_que->rxr; 720 struct tx_ring *txr = &tx_que->txr; 721 int ntxd = scctx->isc_ntxd[0]; 722 int nrxd = scctx->isc_nrxd[0]; 723 int j; 724 725 for (j = 0; j < nrxd; j++) { 726 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 727 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 728 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 729 } 730 731 for (j = 0; j < min(ntxd, 256); j++) { 732 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 733 734 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 735 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 736 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 737 738 } 739 } 740 #endif 741 742 rc = sbuf_finish(sb); 743 sbuf_delete(sb); 744 return(rc); 745 } 746 747 static void * 748 em_register(device_t dev) 749 { 750 return (&em_sctx_init); 751 } 752 753 static void * 754 igb_register(device_t dev) 755 { 756 return (&igb_sctx_init); 757 } 758 759 static int 760 em_set_num_queues(if_ctx_t ctx) 761 { 762 struct e1000_softc *sc = iflib_get_softc(ctx); 763 int maxqueues; 764 765 /* Sanity check based on HW */ 766 switch (sc->hw.mac.type) { 767 case e1000_82576: 768 case e1000_82580: 769 case e1000_i350: 770 case e1000_i354: 771 maxqueues = 8; 772 break; 773 case e1000_i210: 774 case e1000_82575: 775 maxqueues = 4; 776 break; 777 case e1000_i211: 778 case e1000_82574: 779 maxqueues = 2; 780 break; 781 default: 782 maxqueues = 1; 783 break; 784 } 785 786 return (maxqueues); 787 } 788 789 #define LEM_CAPS \ 790 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 791 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 792 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 793 794 #define EM_CAPS \ 795 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 796 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 797 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 798 IFCAP_TSO6 799 800 #define IGB_CAPS \ 801 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 802 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 803 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 804 IFCAP_TSO6 805 806 /********************************************************************* 807 * Device initialization routine 808 * 809 * The attach entry point is called when the driver is being loaded. 810 * This routine identifies the type of hardware, allocates all resources 811 * and initializes the hardware. 812 * 813 * return 0 on success, positive on failure 814 *********************************************************************/ 815 static int 816 em_if_attach_pre(if_ctx_t ctx) 817 { 818 struct e1000_softc *sc; 819 if_softc_ctx_t scctx; 820 device_t dev; 821 struct e1000_hw *hw; 822 struct sysctl_oid_list *child; 823 struct sysctl_ctx_list *ctx_list; 824 int error = 0; 825 826 INIT_DEBUGOUT("em_if_attach_pre: begin"); 827 dev = iflib_get_dev(ctx); 828 sc = iflib_get_softc(ctx); 829 830 sc->ctx = sc->osdep.ctx = ctx; 831 sc->dev = sc->osdep.dev = dev; 832 scctx = sc->shared = iflib_get_softc_ctx(ctx); 833 sc->media = iflib_get_media(ctx); 834 hw = &sc->hw; 835 836 sc->tx_process_limit = scctx->isc_ntxd[0]; 837 838 /* Determine hardware and mac info */ 839 em_identify_hardware(ctx); 840 841 /* SYSCTL stuff */ 842 ctx_list = device_get_sysctl_ctx(dev); 843 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 844 845 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 846 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 847 em_sysctl_nvm_info, "I", "NVM Information"); 848 849 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 850 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 851 em_sysctl_print_fw_version, "A", 852 "Prints FW/NVM Versions"); 853 854 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 855 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 856 em_sysctl_debug_info, "I", "Debug Information"); 857 858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 859 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 860 em_set_flowcntl, "I", "Flow Control"); 861 862 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 863 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 864 em_get_regs, "A", "Dump Registers"); 865 866 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 867 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 868 em_get_rs, "I", "Dump RS indexes"); 869 870 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 871 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 872 if (bootverbose) 873 device_printf(dev, "attach_pre capping queues at %d\n", 874 scctx->isc_ntxqsets_max); 875 876 if (hw->mac.type >= igb_mac_min) { 877 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 878 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 879 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 880 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 881 scctx->isc_txrx = &igb_txrx; 882 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 883 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 884 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 885 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 886 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 887 CSUM_IP6_TCP | CSUM_IP6_UDP; 888 if (hw->mac.type != e1000_82575) 889 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 890 /* 891 ** Some new devices, as with ixgbe, now may 892 ** use a different BAR, so we need to keep 893 ** track of which is used. 894 */ 895 scctx->isc_msix_bar = pci_msix_table_bar(dev); 896 } else if (hw->mac.type >= em_mac_min) { 897 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 898 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 899 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 900 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 901 scctx->isc_txrx = &em_txrx; 902 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 903 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 904 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 905 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 906 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 907 CSUM_IP6_TCP | CSUM_IP6_UDP; 908 909 /* Disable TSO on all em(4) until ring stalls can be debugged */ 910 scctx->isc_capenable &= ~IFCAP_TSO; 911 912 /* 913 * Disable TSO on SPT due to errata that downclocks DMA performance 914 * i218-i219 Specification Update 1.5.4.5 915 */ 916 if (hw->mac.type == e1000_pch_spt) 917 scctx->isc_capenable &= ~IFCAP_TSO; 918 919 /* 920 * We support MSI-X with 82574 only, but indicate to iflib(4) 921 * that it shall give MSI at least a try with other devices. 922 */ 923 if (hw->mac.type == e1000_82574) { 924 scctx->isc_msix_bar = pci_msix_table_bar(dev); 925 } else { 926 scctx->isc_msix_bar = -1; 927 scctx->isc_disable_msix = 1; 928 } 929 } else { 930 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 931 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 932 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 933 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 934 scctx->isc_txrx = &lem_txrx; 935 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 936 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 937 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 938 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 939 if (em_unsupported_tso) 940 scctx->isc_capabilities |= IFCAP_TSO6; 941 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 942 CSUM_IP6_TCP | CSUM_IP6_UDP; 943 944 /* Disable TSO on all lem(4) until ring stalls can be debugged */ 945 scctx->isc_capenable &= ~IFCAP_TSO; 946 947 /* 82541ER doesn't do HW tagging */ 948 if (hw->device_id == E1000_DEV_ID_82541ER || 949 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 950 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 951 scctx->isc_capenable = scctx->isc_capabilities; 952 } 953 /* This is the first e1000 chip and it does not do offloads */ 954 if (hw->mac.type == e1000_82542) { 955 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 956 IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING | 957 IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO); 958 scctx->isc_capenable = scctx->isc_capabilities; 959 } 960 /* These can't do TSO for various reasons */ 961 if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 || 962 hw->mac.type == e1000_82547_rev_2) { 963 scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 964 scctx->isc_capenable = scctx->isc_capabilities; 965 } 966 /* XXXKB: No IPv6 before this? */ 967 if (hw->mac.type < e1000_82545){ 968 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 969 scctx->isc_capenable = scctx->isc_capabilities; 970 } 971 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 972 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 973 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 974 IFCAP_HWCSUM_IPV6); 975 976 /* INTx only */ 977 scctx->isc_msix_bar = 0; 978 } 979 980 /* Setup PCI resources */ 981 if (em_allocate_pci_resources(ctx)) { 982 device_printf(dev, "Allocation of PCI resources failed\n"); 983 error = ENXIO; 984 goto err_pci; 985 } 986 987 /* 988 ** For ICH8 and family we need to 989 ** map the flash memory, and this 990 ** must happen after the MAC is 991 ** identified 992 */ 993 if ((hw->mac.type == e1000_ich8lan) || 994 (hw->mac.type == e1000_ich9lan) || 995 (hw->mac.type == e1000_ich10lan) || 996 (hw->mac.type == e1000_pchlan) || 997 (hw->mac.type == e1000_pch2lan) || 998 (hw->mac.type == e1000_pch_lpt)) { 999 int rid = EM_BAR_TYPE_FLASH; 1000 sc->flash = bus_alloc_resource_any(dev, 1001 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1002 if (sc->flash == NULL) { 1003 device_printf(dev, "Mapping of Flash failed\n"); 1004 error = ENXIO; 1005 goto err_pci; 1006 } 1007 /* This is used in the shared code */ 1008 hw->flash_address = (u8 *)sc->flash; 1009 sc->osdep.flash_bus_space_tag = 1010 rman_get_bustag(sc->flash); 1011 sc->osdep.flash_bus_space_handle = 1012 rman_get_bushandle(sc->flash); 1013 } 1014 /* 1015 ** In the new SPT device flash is not a 1016 ** separate BAR, rather it is also in BAR0, 1017 ** so use the same tag and an offset handle for the 1018 ** FLASH read/write macros in the shared code. 1019 */ 1020 else if (hw->mac.type >= e1000_pch_spt) { 1021 sc->osdep.flash_bus_space_tag = 1022 sc->osdep.mem_bus_space_tag; 1023 sc->osdep.flash_bus_space_handle = 1024 sc->osdep.mem_bus_space_handle 1025 + E1000_FLASH_BASE_ADDR; 1026 } 1027 1028 /* Do Shared Code initialization */ 1029 error = e1000_setup_init_funcs(hw, true); 1030 if (error) { 1031 device_printf(dev, "Setup of Shared code failed, error %d\n", 1032 error); 1033 error = ENXIO; 1034 goto err_pci; 1035 } 1036 1037 em_setup_msix(ctx); 1038 e1000_get_bus_info(hw); 1039 1040 /* Set up some sysctls for the tunable interrupt delays */ 1041 em_add_int_delay_sysctl(sc, "rx_int_delay", 1042 "receive interrupt delay in usecs", &sc->rx_int_delay, 1043 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1044 em_add_int_delay_sysctl(sc, "tx_int_delay", 1045 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1046 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1047 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1048 "receive interrupt delay limit in usecs", 1049 &sc->rx_abs_int_delay, 1050 E1000_REGISTER(hw, E1000_RADV), 1051 em_rx_abs_int_delay_dflt); 1052 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1053 "transmit interrupt delay limit in usecs", 1054 &sc->tx_abs_int_delay, 1055 E1000_REGISTER(hw, E1000_TADV), 1056 em_tx_abs_int_delay_dflt); 1057 em_add_int_delay_sysctl(sc, "itr", 1058 "interrupt delay limit in usecs/4", 1059 &sc->tx_itr, 1060 E1000_REGISTER(hw, E1000_ITR), 1061 DEFAULT_ITR); 1062 1063 hw->mac.autoneg = DO_AUTO_NEG; 1064 hw->phy.autoneg_wait_to_complete = false; 1065 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1066 1067 if (hw->mac.type < em_mac_min) { 1068 e1000_init_script_state_82541(hw, true); 1069 e1000_set_tbi_compatibility_82543(hw, true); 1070 } 1071 /* Copper options */ 1072 if (hw->phy.media_type == e1000_media_type_copper) { 1073 hw->phy.mdix = AUTO_ALL_MODES; 1074 hw->phy.disable_polarity_correction = false; 1075 hw->phy.ms_type = EM_MASTER_SLAVE; 1076 } 1077 1078 /* 1079 * Set the frame limits assuming 1080 * standard ethernet sized frames. 1081 */ 1082 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1083 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1084 1085 /* 1086 * This controls when hardware reports transmit completion 1087 * status. 1088 */ 1089 hw->mac.report_tx_early = 1; 1090 1091 /* Allocate multicast array memory. */ 1092 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1093 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1094 if (sc->mta == NULL) { 1095 device_printf(dev, "Can not allocate multicast setup array\n"); 1096 error = ENOMEM; 1097 goto err_late; 1098 } 1099 1100 /* Clear the IFCAP_TSO auto mask */ 1101 sc->tso_automasked = 0; 1102 1103 /* Check SOL/IDER usage */ 1104 if (e1000_check_reset_block(hw)) 1105 device_printf(dev, "PHY reset is blocked" 1106 " due to SOL/IDER session.\n"); 1107 1108 /* Sysctl for setting Energy Efficient Ethernet */ 1109 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1110 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1111 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1112 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1113 1114 /* 1115 ** Start from a known state, this is 1116 ** important in reading the nvm and 1117 ** mac from that. 1118 */ 1119 e1000_reset_hw(hw); 1120 1121 /* Make sure we have a good EEPROM before we read from it */ 1122 if (e1000_validate_nvm_checksum(hw) < 0) { 1123 /* 1124 ** Some PCI-E parts fail the first check due to 1125 ** the link being in sleep state, call it again, 1126 ** if it fails a second time its a real issue. 1127 */ 1128 if (e1000_validate_nvm_checksum(hw) < 0) { 1129 device_printf(dev, 1130 "The EEPROM Checksum Is Not Valid\n"); 1131 error = EIO; 1132 goto err_late; 1133 } 1134 } 1135 1136 /* Copy the permanent MAC address out of the EEPROM */ 1137 if (e1000_read_mac_addr(hw) < 0) { 1138 device_printf(dev, "EEPROM read error while reading MAC" 1139 " address\n"); 1140 error = EIO; 1141 goto err_late; 1142 } 1143 1144 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1145 if (sc->vf_ifp) { 1146 ether_gen_addr(iflib_get_ifp(ctx), 1147 (struct ether_addr *)hw->mac.addr); 1148 } else { 1149 device_printf(dev, "Invalid MAC address\n"); 1150 error = EIO; 1151 goto err_late; 1152 } 1153 } 1154 1155 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1156 em_fw_version_locked(ctx); 1157 1158 em_print_fw_version(sc); 1159 1160 /* 1161 * Get Wake-on-Lan and Management info for later use 1162 */ 1163 em_get_wakeup(ctx); 1164 1165 /* Enable only WOL MAGIC by default */ 1166 scctx->isc_capenable &= ~IFCAP_WOL; 1167 if (sc->wol != 0) 1168 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1169 1170 iflib_set_mac(ctx, hw->mac.addr); 1171 1172 return (0); 1173 1174 err_late: 1175 em_release_hw_control(sc); 1176 err_pci: 1177 em_free_pci_resources(ctx); 1178 free(sc->mta, M_DEVBUF); 1179 1180 return (error); 1181 } 1182 1183 static int 1184 em_if_attach_post(if_ctx_t ctx) 1185 { 1186 struct e1000_softc *sc = iflib_get_softc(ctx); 1187 struct e1000_hw *hw = &sc->hw; 1188 int error = 0; 1189 1190 /* Setup OS specific network interface */ 1191 error = em_setup_interface(ctx); 1192 if (error != 0) { 1193 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1194 goto err_late; 1195 } 1196 1197 em_reset(ctx); 1198 1199 /* Initialize statistics */ 1200 em_update_stats_counters(sc); 1201 hw->mac.get_link_status = 1; 1202 em_if_update_admin_status(ctx); 1203 em_add_hw_stats(sc); 1204 1205 /* Non-AMT based hardware can now take control from firmware */ 1206 if (sc->has_manage && !sc->has_amt) 1207 em_get_hw_control(sc); 1208 1209 INIT_DEBUGOUT("em_if_attach_post: end"); 1210 1211 return (0); 1212 1213 err_late: 1214 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1215 return (error); 1216 } 1217 1218 /********************************************************************* 1219 * Device removal routine 1220 * 1221 * The detach entry point is called when the driver is being removed. 1222 * This routine stops the adapter and deallocates all the resources 1223 * that were allocated for driver operation. 1224 * 1225 * return 0 on success, positive on failure 1226 *********************************************************************/ 1227 static int 1228 em_if_detach(if_ctx_t ctx) 1229 { 1230 struct e1000_softc *sc = iflib_get_softc(ctx); 1231 1232 INIT_DEBUGOUT("em_if_detach: begin"); 1233 1234 e1000_phy_hw_reset(&sc->hw); 1235 1236 em_release_manageability(sc); 1237 em_release_hw_control(sc); 1238 em_free_pci_resources(ctx); 1239 free(sc->mta, M_DEVBUF); 1240 sc->mta = NULL; 1241 1242 return (0); 1243 } 1244 1245 /********************************************************************* 1246 * 1247 * Shutdown entry point 1248 * 1249 **********************************************************************/ 1250 1251 static int 1252 em_if_shutdown(if_ctx_t ctx) 1253 { 1254 return em_if_suspend(ctx); 1255 } 1256 1257 /* 1258 * Suspend/resume device methods. 1259 */ 1260 static int 1261 em_if_suspend(if_ctx_t ctx) 1262 { 1263 struct e1000_softc *sc = iflib_get_softc(ctx); 1264 1265 em_release_manageability(sc); 1266 em_release_hw_control(sc); 1267 em_enable_wakeup(ctx); 1268 return (0); 1269 } 1270 1271 static int 1272 em_if_resume(if_ctx_t ctx) 1273 { 1274 struct e1000_softc *sc = iflib_get_softc(ctx); 1275 1276 if (sc->hw.mac.type == e1000_pch2lan) 1277 e1000_resume_workarounds_pchlan(&sc->hw); 1278 em_if_init(ctx); 1279 em_init_manageability(sc); 1280 1281 return(0); 1282 } 1283 1284 static int 1285 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1286 { 1287 int max_frame_size; 1288 struct e1000_softc *sc = iflib_get_softc(ctx); 1289 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1290 1291 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1292 1293 switch (sc->hw.mac.type) { 1294 case e1000_82571: 1295 case e1000_82572: 1296 case e1000_ich9lan: 1297 case e1000_ich10lan: 1298 case e1000_pch2lan: 1299 case e1000_pch_lpt: 1300 case e1000_pch_spt: 1301 case e1000_pch_cnp: 1302 case e1000_pch_tgp: 1303 case e1000_pch_adp: 1304 case e1000_pch_mtp: 1305 case e1000_pch_ptp: 1306 case e1000_82574: 1307 case e1000_82583: 1308 case e1000_80003es2lan: 1309 /* 9K Jumbo Frame size */ 1310 max_frame_size = 9234; 1311 break; 1312 case e1000_pchlan: 1313 max_frame_size = 4096; 1314 break; 1315 case e1000_82542: 1316 case e1000_ich8lan: 1317 /* Adapters that do not support jumbo frames */ 1318 max_frame_size = ETHER_MAX_LEN; 1319 break; 1320 default: 1321 if (sc->hw.mac.type >= igb_mac_min) 1322 max_frame_size = 9234; 1323 else /* lem */ 1324 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1325 } 1326 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1327 return (EINVAL); 1328 } 1329 1330 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1331 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1332 return (0); 1333 } 1334 1335 /********************************************************************* 1336 * Init entry point 1337 * 1338 * This routine is used in two ways. It is used by the stack as 1339 * init entry point in network interface structure. It is also used 1340 * by the driver as a hw/sw initialization routine to get to a 1341 * consistent state. 1342 * 1343 **********************************************************************/ 1344 static void 1345 em_if_init(if_ctx_t ctx) 1346 { 1347 struct e1000_softc *sc = iflib_get_softc(ctx); 1348 if_softc_ctx_t scctx = sc->shared; 1349 if_t ifp = iflib_get_ifp(ctx); 1350 struct em_tx_queue *tx_que; 1351 int i; 1352 1353 INIT_DEBUGOUT("em_if_init: begin"); 1354 1355 /* Get the latest mac address, User can use a LAA */ 1356 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1357 ETHER_ADDR_LEN); 1358 1359 /* Put the address into the Receive Address Array */ 1360 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1361 1362 /* 1363 * With the 82571 adapter, RAR[0] may be overwritten 1364 * when the other port is reset, we make a duplicate 1365 * in RAR[14] for that eventuality, this assures 1366 * the interface continues to function. 1367 */ 1368 if (sc->hw.mac.type == e1000_82571) { 1369 e1000_set_laa_state_82571(&sc->hw, true); 1370 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1371 E1000_RAR_ENTRIES - 1); 1372 } 1373 1374 /* Initialize the hardware */ 1375 em_reset(ctx); 1376 em_if_update_admin_status(ctx); 1377 1378 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1379 struct tx_ring *txr = &tx_que->txr; 1380 1381 txr->tx_rs_cidx = txr->tx_rs_pidx; 1382 1383 /* Initialize the last processed descriptor to be the end of 1384 * the ring, rather than the start, so that we avoid an 1385 * off-by-one error when calculating how many descriptors are 1386 * done in the credits_update function. 1387 */ 1388 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1389 } 1390 1391 /* Setup VLAN support, basic and offload if available */ 1392 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1393 1394 /* Clear bad data from Rx FIFOs */ 1395 if (sc->hw.mac.type >= igb_mac_min) 1396 e1000_rx_fifo_flush_base(&sc->hw); 1397 1398 /* Configure for OS presence */ 1399 em_init_manageability(sc); 1400 1401 /* Prepare transmit descriptors and buffers */ 1402 em_initialize_transmit_unit(ctx); 1403 1404 /* Setup Multicast table */ 1405 em_if_multi_set(ctx); 1406 1407 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1408 em_initialize_receive_unit(ctx); 1409 1410 /* Set up VLAN support and filter */ 1411 em_setup_vlan_hw_support(ctx); 1412 1413 /* Don't lose promiscuous settings */ 1414 em_if_set_promisc(ctx, if_getflags(ifp)); 1415 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1416 1417 /* MSI-X configuration for 82574 */ 1418 if (sc->hw.mac.type == e1000_82574) { 1419 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1420 1421 tmp |= E1000_CTRL_EXT_PBA_CLR; 1422 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1423 /* Set the IVAR - interrupt vector routing. */ 1424 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1425 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1426 igb_configure_queues(sc); 1427 1428 /* this clears any pending interrupts */ 1429 E1000_READ_REG(&sc->hw, E1000_ICR); 1430 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1431 1432 /* AMT based hardware can now take control from firmware */ 1433 if (sc->has_manage && sc->has_amt) 1434 em_get_hw_control(sc); 1435 1436 /* Set Energy Efficient Ethernet */ 1437 if (sc->hw.mac.type >= igb_mac_min && 1438 sc->hw.phy.media_type == e1000_media_type_copper) { 1439 if (sc->hw.mac.type == e1000_i354) 1440 e1000_set_eee_i354(&sc->hw, true, true); 1441 else 1442 e1000_set_eee_i350(&sc->hw, true, true); 1443 } 1444 } 1445 1446 /********************************************************************* 1447 * 1448 * Fast Legacy/MSI Combined Interrupt Service routine 1449 * 1450 *********************************************************************/ 1451 int 1452 em_intr(void *arg) 1453 { 1454 struct e1000_softc *sc = arg; 1455 if_ctx_t ctx = sc->ctx; 1456 u32 reg_icr; 1457 1458 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1459 1460 /* Hot eject? */ 1461 if (reg_icr == 0xffffffff) 1462 return FILTER_STRAY; 1463 1464 /* Definitely not our interrupt. */ 1465 if (reg_icr == 0x0) 1466 return FILTER_STRAY; 1467 1468 /* 1469 * Starting with the 82571 chip, bit 31 should be used to 1470 * determine whether the interrupt belongs to us. 1471 */ 1472 if (sc->hw.mac.type >= e1000_82571 && 1473 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1474 return FILTER_STRAY; 1475 1476 /* 1477 * Only MSI-X interrupts have one-shot behavior by taking advantage 1478 * of the EIAC register. Thus, explicitly disable interrupts. This 1479 * also works around the MSI message reordering errata on certain 1480 * systems. 1481 */ 1482 IFDI_INTR_DISABLE(ctx); 1483 1484 /* Link status change */ 1485 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1486 em_handle_link(ctx); 1487 1488 if (reg_icr & E1000_ICR_RXO) 1489 sc->rx_overruns++; 1490 1491 return (FILTER_SCHEDULE_THREAD); 1492 } 1493 1494 static int 1495 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1496 { 1497 struct e1000_softc *sc = iflib_get_softc(ctx); 1498 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1499 1500 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1501 return (0); 1502 } 1503 1504 static int 1505 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1506 { 1507 struct e1000_softc *sc = iflib_get_softc(ctx); 1508 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1509 1510 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1511 return (0); 1512 } 1513 1514 static int 1515 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1516 { 1517 struct e1000_softc *sc = iflib_get_softc(ctx); 1518 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1519 1520 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1521 return (0); 1522 } 1523 1524 static int 1525 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1526 { 1527 struct e1000_softc *sc = iflib_get_softc(ctx); 1528 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1529 1530 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1531 return (0); 1532 } 1533 1534 /********************************************************************* 1535 * 1536 * MSI-X RX Interrupt Service routine 1537 * 1538 **********************************************************************/ 1539 static int 1540 em_msix_que(void *arg) 1541 { 1542 struct em_rx_queue *que = arg; 1543 1544 ++que->irqs; 1545 1546 return (FILTER_SCHEDULE_THREAD); 1547 } 1548 1549 /********************************************************************* 1550 * 1551 * MSI-X Link Fast Interrupt Service routine 1552 * 1553 **********************************************************************/ 1554 static int 1555 em_msix_link(void *arg) 1556 { 1557 struct e1000_softc *sc = arg; 1558 u32 reg_icr; 1559 1560 ++sc->link_irq; 1561 MPASS(sc->hw.back != NULL); 1562 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1563 1564 if (reg_icr & E1000_ICR_RXO) 1565 sc->rx_overruns++; 1566 1567 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1568 em_handle_link(sc->ctx); 1569 1570 /* Re-arm unconditionally */ 1571 if (sc->hw.mac.type >= igb_mac_min) { 1572 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1573 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1574 } else if (sc->hw.mac.type == e1000_82574) { 1575 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1576 E1000_IMS_OTHER); 1577 /* 1578 * Because we must read the ICR for this interrupt it may 1579 * clear other causes using autoclear, for this reason we 1580 * simply create a soft interrupt for all these vectors. 1581 */ 1582 if (reg_icr) 1583 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1584 } else 1585 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1586 1587 return (FILTER_HANDLED); 1588 } 1589 1590 static void 1591 em_handle_link(void *context) 1592 { 1593 if_ctx_t ctx = context; 1594 struct e1000_softc *sc = iflib_get_softc(ctx); 1595 1596 sc->hw.mac.get_link_status = 1; 1597 iflib_admin_intr_deferred(ctx); 1598 } 1599 1600 /********************************************************************* 1601 * 1602 * Media Ioctl callback 1603 * 1604 * This routine is called whenever the user queries the status of 1605 * the interface using ifconfig. 1606 * 1607 **********************************************************************/ 1608 static void 1609 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1610 { 1611 struct e1000_softc *sc = iflib_get_softc(ctx); 1612 u_char fiber_type = IFM_1000_SX; 1613 1614 INIT_DEBUGOUT("em_if_media_status: begin"); 1615 1616 iflib_admin_intr_deferred(ctx); 1617 1618 ifmr->ifm_status = IFM_AVALID; 1619 ifmr->ifm_active = IFM_ETHER; 1620 1621 if (!sc->link_active) { 1622 return; 1623 } 1624 1625 ifmr->ifm_status |= IFM_ACTIVE; 1626 1627 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1628 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1629 if (sc->hw.mac.type == e1000_82545) 1630 fiber_type = IFM_1000_LX; 1631 ifmr->ifm_active |= fiber_type | IFM_FDX; 1632 } else { 1633 switch (sc->link_speed) { 1634 case 10: 1635 ifmr->ifm_active |= IFM_10_T; 1636 break; 1637 case 100: 1638 ifmr->ifm_active |= IFM_100_TX; 1639 break; 1640 case 1000: 1641 ifmr->ifm_active |= IFM_1000_T; 1642 break; 1643 } 1644 if (sc->link_duplex == FULL_DUPLEX) 1645 ifmr->ifm_active |= IFM_FDX; 1646 else 1647 ifmr->ifm_active |= IFM_HDX; 1648 } 1649 } 1650 1651 /********************************************************************* 1652 * 1653 * Media Ioctl callback 1654 * 1655 * This routine is called when the user changes speed/duplex using 1656 * media/mediopt option with ifconfig. 1657 * 1658 **********************************************************************/ 1659 static int 1660 em_if_media_change(if_ctx_t ctx) 1661 { 1662 struct e1000_softc *sc = iflib_get_softc(ctx); 1663 struct ifmedia *ifm = iflib_get_media(ctx); 1664 1665 INIT_DEBUGOUT("em_if_media_change: begin"); 1666 1667 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1668 return (EINVAL); 1669 1670 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1671 case IFM_AUTO: 1672 sc->hw.mac.autoneg = DO_AUTO_NEG; 1673 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1674 break; 1675 case IFM_1000_LX: 1676 case IFM_1000_SX: 1677 case IFM_1000_T: 1678 sc->hw.mac.autoneg = DO_AUTO_NEG; 1679 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1680 break; 1681 case IFM_100_TX: 1682 sc->hw.mac.autoneg = false; 1683 sc->hw.phy.autoneg_advertised = 0; 1684 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1685 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1686 else 1687 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1688 break; 1689 case IFM_10_T: 1690 sc->hw.mac.autoneg = false; 1691 sc->hw.phy.autoneg_advertised = 0; 1692 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1693 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1694 else 1695 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1696 break; 1697 default: 1698 device_printf(sc->dev, "Unsupported media type\n"); 1699 } 1700 1701 em_if_init(ctx); 1702 1703 return (0); 1704 } 1705 1706 static int 1707 em_if_set_promisc(if_ctx_t ctx, int flags) 1708 { 1709 struct e1000_softc *sc = iflib_get_softc(ctx); 1710 if_t ifp = iflib_get_ifp(ctx); 1711 u32 reg_rctl; 1712 int mcnt = 0; 1713 1714 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1715 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1716 if (flags & IFF_ALLMULTI) 1717 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1718 else 1719 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1720 1721 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1722 reg_rctl &= (~E1000_RCTL_MPE); 1723 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1724 1725 if (flags & IFF_PROMISC) { 1726 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1727 em_if_vlan_filter_disable(sc); 1728 /* Turn this on if you want to see bad packets */ 1729 if (em_debug_sbp) 1730 reg_rctl |= E1000_RCTL_SBP; 1731 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1732 } else { 1733 if (flags & IFF_ALLMULTI) { 1734 reg_rctl |= E1000_RCTL_MPE; 1735 reg_rctl &= ~E1000_RCTL_UPE; 1736 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1737 } 1738 if (em_if_vlan_filter_used(ctx)) 1739 em_if_vlan_filter_enable(sc); 1740 } 1741 return (0); 1742 } 1743 1744 static u_int 1745 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1746 { 1747 u8 *mta = arg; 1748 1749 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1750 return (0); 1751 1752 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1753 1754 return (1); 1755 } 1756 1757 /********************************************************************* 1758 * Multicast Update 1759 * 1760 * This routine is called whenever multicast address list is updated. 1761 * 1762 **********************************************************************/ 1763 static void 1764 em_if_multi_set(if_ctx_t ctx) 1765 { 1766 struct e1000_softc *sc = iflib_get_softc(ctx); 1767 if_t ifp = iflib_get_ifp(ctx); 1768 u8 *mta; /* Multicast array memory */ 1769 u32 reg_rctl = 0; 1770 int mcnt = 0; 1771 1772 IOCTL_DEBUGOUT("em_set_multi: begin"); 1773 1774 mta = sc->mta; 1775 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1776 1777 if (sc->hw.mac.type == e1000_82542 && 1778 sc->hw.revision_id == E1000_REVISION_2) { 1779 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1780 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1781 e1000_pci_clear_mwi(&sc->hw); 1782 reg_rctl |= E1000_RCTL_RST; 1783 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1784 msec_delay(5); 1785 } 1786 1787 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1788 1789 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1790 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1791 1792 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1793 1794 if (if_getflags(ifp) & IFF_PROMISC) 1795 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1796 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1797 if_getflags(ifp) & IFF_ALLMULTI) { 1798 reg_rctl |= E1000_RCTL_MPE; 1799 reg_rctl &= ~E1000_RCTL_UPE; 1800 } else 1801 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1802 1803 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1804 1805 if (sc->hw.mac.type == e1000_82542 && 1806 sc->hw.revision_id == E1000_REVISION_2) { 1807 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1808 reg_rctl &= ~E1000_RCTL_RST; 1809 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1810 msec_delay(5); 1811 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1812 e1000_pci_set_mwi(&sc->hw); 1813 } 1814 } 1815 1816 /********************************************************************* 1817 * Timer routine 1818 * 1819 * This routine schedules em_if_update_admin_status() to check for 1820 * link status and to gather statistics as well as to perform some 1821 * controller-specific hardware patting. 1822 * 1823 **********************************************************************/ 1824 static void 1825 em_if_timer(if_ctx_t ctx, uint16_t qid) 1826 { 1827 1828 if (qid != 0) 1829 return; 1830 1831 iflib_admin_intr_deferred(ctx); 1832 } 1833 1834 static void 1835 em_if_update_admin_status(if_ctx_t ctx) 1836 { 1837 struct e1000_softc *sc = iflib_get_softc(ctx); 1838 struct e1000_hw *hw = &sc->hw; 1839 device_t dev = iflib_get_dev(ctx); 1840 u32 link_check, thstat, ctrl; 1841 bool automasked = false; 1842 1843 link_check = thstat = ctrl = 0; 1844 /* Get the cached link value or read phy for real */ 1845 switch (hw->phy.media_type) { 1846 case e1000_media_type_copper: 1847 if (hw->mac.get_link_status) { 1848 if (hw->mac.type == e1000_pch_spt) 1849 msec_delay(50); 1850 /* Do the work to read phy */ 1851 e1000_check_for_link(hw); 1852 link_check = !hw->mac.get_link_status; 1853 if (link_check) /* ESB2 fix */ 1854 e1000_cfg_on_link_up(hw); 1855 } else { 1856 link_check = true; 1857 } 1858 break; 1859 case e1000_media_type_fiber: 1860 e1000_check_for_link(hw); 1861 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1862 E1000_STATUS_LU); 1863 break; 1864 case e1000_media_type_internal_serdes: 1865 e1000_check_for_link(hw); 1866 link_check = hw->mac.serdes_has_link; 1867 break; 1868 /* VF device is type_unknown */ 1869 case e1000_media_type_unknown: 1870 e1000_check_for_link(hw); 1871 link_check = !hw->mac.get_link_status; 1872 /* FALLTHROUGH */ 1873 default: 1874 break; 1875 } 1876 1877 /* Check for thermal downshift or shutdown */ 1878 if (hw->mac.type == e1000_i350) { 1879 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1880 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1881 } 1882 1883 /* Now check for a transition */ 1884 if (link_check && (sc->link_active == 0)) { 1885 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1886 &sc->link_duplex); 1887 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1888 if ((sc->link_speed != SPEED_1000) && 1889 ((hw->mac.type == e1000_82571) || 1890 (hw->mac.type == e1000_82572))) { 1891 int tarc0; 1892 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1893 tarc0 &= ~TARC_SPEED_MODE_BIT; 1894 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1895 } 1896 if (bootverbose) 1897 device_printf(dev, "Link is up %d Mbps %s\n", 1898 sc->link_speed, 1899 ((sc->link_duplex == FULL_DUPLEX) ? 1900 "Full Duplex" : "Half Duplex")); 1901 sc->link_active = 1; 1902 sc->smartspeed = 0; 1903 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1904 E1000_CTRL_EXT_LINK_MODE_GMII && 1905 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1906 device_printf(dev, "Link: thermal downshift\n"); 1907 /* Delay Link Up for Phy update */ 1908 if (((hw->mac.type == e1000_i210) || 1909 (hw->mac.type == e1000_i211)) && 1910 (hw->phy.id == I210_I_PHY_ID)) 1911 msec_delay(I210_LINK_DELAY); 1912 /* Reset if the media type changed. */ 1913 if (hw->dev_spec._82575.media_changed && 1914 hw->mac.type >= igb_mac_min) { 1915 hw->dev_spec._82575.media_changed = false; 1916 sc->flags |= IGB_MEDIA_RESET; 1917 em_reset(ctx); 1918 } 1919 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 1920 if (hw->mac.type < igb_mac_min) 1921 automasked = em_automask_tso(ctx); 1922 1923 /* Automasking resets the interface, so don't mark it up yet */ 1924 if (!automasked) 1925 iflib_link_state_change(ctx, LINK_STATE_UP, 1926 IF_Mbps(sc->link_speed)); 1927 } else if (!link_check && (sc->link_active == 1)) { 1928 sc->link_speed = 0; 1929 sc->link_duplex = 0; 1930 sc->link_active = 0; 1931 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1932 } 1933 em_update_stats_counters(sc); 1934 1935 /* Reset LAA into RAR[0] on 82571 */ 1936 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1937 e1000_rar_set(hw, hw->mac.addr, 0); 1938 1939 if (hw->mac.type < em_mac_min) 1940 lem_smartspeed(sc); 1941 } 1942 1943 static void 1944 em_if_watchdog_reset(if_ctx_t ctx) 1945 { 1946 struct e1000_softc *sc = iflib_get_softc(ctx); 1947 1948 /* 1949 * Just count the event; iflib(4) will already trigger a 1950 * sufficient reset of the controller. 1951 */ 1952 sc->watchdog_events++; 1953 } 1954 1955 /********************************************************************* 1956 * 1957 * This routine disables all traffic on the adapter by issuing a 1958 * global reset on the MAC. 1959 * 1960 **********************************************************************/ 1961 static void 1962 em_if_stop(if_ctx_t ctx) 1963 { 1964 struct e1000_softc *sc = iflib_get_softc(ctx); 1965 1966 INIT_DEBUGOUT("em_if_stop: begin"); 1967 1968 /* I219 needs special flushing to avoid hangs */ 1969 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1970 em_flush_desc_rings(sc); 1971 1972 e1000_reset_hw(&sc->hw); 1973 if (sc->hw.mac.type >= e1000_82544) 1974 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1975 1976 e1000_led_off(&sc->hw); 1977 e1000_cleanup_led(&sc->hw); 1978 } 1979 1980 /********************************************************************* 1981 * 1982 * Determine hardware revision. 1983 * 1984 **********************************************************************/ 1985 static void 1986 em_identify_hardware(if_ctx_t ctx) 1987 { 1988 device_t dev = iflib_get_dev(ctx); 1989 struct e1000_softc *sc = iflib_get_softc(ctx); 1990 1991 /* Make sure our PCI config space has the necessary stuff set */ 1992 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1993 1994 /* Save off the information about this board */ 1995 sc->hw.vendor_id = pci_get_vendor(dev); 1996 sc->hw.device_id = pci_get_device(dev); 1997 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1998 sc->hw.subsystem_vendor_id = 1999 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2000 sc->hw.subsystem_device_id = 2001 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2002 2003 /* Do Shared Code Init and Setup */ 2004 if (e1000_set_mac_type(&sc->hw)) { 2005 device_printf(dev, "Setup init failure\n"); 2006 return; 2007 } 2008 2009 /* Are we a VF device? */ 2010 if ((sc->hw.mac.type == e1000_vfadapt) || 2011 (sc->hw.mac.type == e1000_vfadapt_i350)) 2012 sc->vf_ifp = 1; 2013 else 2014 sc->vf_ifp = 0; 2015 } 2016 2017 static int 2018 em_allocate_pci_resources(if_ctx_t ctx) 2019 { 2020 struct e1000_softc *sc = iflib_get_softc(ctx); 2021 device_t dev = iflib_get_dev(ctx); 2022 int rid, val; 2023 2024 rid = PCIR_BAR(0); 2025 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2026 &rid, RF_ACTIVE); 2027 if (sc->memory == NULL) { 2028 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2029 return (ENXIO); 2030 } 2031 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2032 sc->osdep.mem_bus_space_handle = 2033 rman_get_bushandle(sc->memory); 2034 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2035 2036 /* Only older adapters use IO mapping */ 2037 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2038 /* Figure our where our IO BAR is ? */ 2039 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2040 val = pci_read_config(dev, rid, 4); 2041 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2042 break; 2043 } 2044 rid += 4; 2045 /* check for 64bit BAR */ 2046 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2047 rid += 4; 2048 } 2049 if (rid >= PCIR_CIS) { 2050 device_printf(dev, "Unable to locate IO BAR\n"); 2051 return (ENXIO); 2052 } 2053 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2054 &rid, RF_ACTIVE); 2055 if (sc->ioport == NULL) { 2056 device_printf(dev, "Unable to allocate bus resource: " 2057 "ioport\n"); 2058 return (ENXIO); 2059 } 2060 sc->hw.io_base = 0; 2061 sc->osdep.io_bus_space_tag = 2062 rman_get_bustag(sc->ioport); 2063 sc->osdep.io_bus_space_handle = 2064 rman_get_bushandle(sc->ioport); 2065 } 2066 2067 sc->hw.back = &sc->osdep; 2068 2069 return (0); 2070 } 2071 2072 /********************************************************************* 2073 * 2074 * Set up the MSI-X Interrupt handlers 2075 * 2076 **********************************************************************/ 2077 static int 2078 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2079 { 2080 struct e1000_softc *sc = iflib_get_softc(ctx); 2081 struct em_rx_queue *rx_que = sc->rx_queues; 2082 struct em_tx_queue *tx_que = sc->tx_queues; 2083 int error, rid, i, vector = 0, rx_vectors; 2084 char buf[16]; 2085 2086 /* First set up ring resources */ 2087 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2088 rid = vector + 1; 2089 snprintf(buf, sizeof(buf), "rxq%d", i); 2090 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2091 if (error) { 2092 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2093 sc->rx_num_queues = i + 1; 2094 goto fail; 2095 } 2096 2097 rx_que->msix = vector; 2098 2099 /* 2100 * Set the bit to enable interrupt 2101 * in E1000_IMS -- bits 20 and 21 2102 * are for RX0 and RX1, note this has 2103 * NOTHING to do with the MSI-X vector 2104 */ 2105 if (sc->hw.mac.type == e1000_82574) { 2106 rx_que->eims = 1 << (20 + i); 2107 sc->ims |= rx_que->eims; 2108 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2109 } else if (sc->hw.mac.type == e1000_82575) 2110 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2111 else 2112 rx_que->eims = 1 << vector; 2113 } 2114 rx_vectors = vector; 2115 2116 vector = 0; 2117 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2118 snprintf(buf, sizeof(buf), "txq%d", i); 2119 tx_que = &sc->tx_queues[i]; 2120 iflib_softirq_alloc_generic(ctx, 2121 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2122 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2123 2124 tx_que->msix = (vector % sc->rx_num_queues); 2125 2126 /* 2127 * Set the bit to enable interrupt 2128 * in E1000_IMS -- bits 22 and 23 2129 * are for TX0 and TX1, note this has 2130 * NOTHING to do with the MSI-X vector 2131 */ 2132 if (sc->hw.mac.type == e1000_82574) { 2133 tx_que->eims = 1 << (22 + i); 2134 sc->ims |= tx_que->eims; 2135 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2136 } else if (sc->hw.mac.type == e1000_82575) { 2137 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2138 } else { 2139 tx_que->eims = 1 << i; 2140 } 2141 } 2142 2143 /* Link interrupt */ 2144 rid = rx_vectors + 1; 2145 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2146 2147 if (error) { 2148 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2149 goto fail; 2150 } 2151 sc->linkvec = rx_vectors; 2152 if (sc->hw.mac.type < igb_mac_min) { 2153 sc->ivars |= (8 | rx_vectors) << 16; 2154 sc->ivars |= 0x80000000; 2155 /* Enable the "Other" interrupt type for link status change */ 2156 sc->ims |= E1000_IMS_OTHER; 2157 } 2158 2159 return (0); 2160 fail: 2161 iflib_irq_free(ctx, &sc->irq); 2162 rx_que = sc->rx_queues; 2163 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2164 iflib_irq_free(ctx, &rx_que->que_irq); 2165 return (error); 2166 } 2167 2168 static void 2169 igb_configure_queues(struct e1000_softc *sc) 2170 { 2171 struct e1000_hw *hw = &sc->hw; 2172 struct em_rx_queue *rx_que; 2173 struct em_tx_queue *tx_que; 2174 u32 tmp, ivar = 0, newitr = 0; 2175 2176 /* First turn on RSS capability */ 2177 if (hw->mac.type != e1000_82575) 2178 E1000_WRITE_REG(hw, E1000_GPIE, 2179 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2180 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2181 2182 /* Turn on MSI-X */ 2183 switch (hw->mac.type) { 2184 case e1000_82580: 2185 case e1000_i350: 2186 case e1000_i354: 2187 case e1000_i210: 2188 case e1000_i211: 2189 case e1000_vfadapt: 2190 case e1000_vfadapt_i350: 2191 /* RX entries */ 2192 for (int i = 0; i < sc->rx_num_queues; i++) { 2193 u32 index = i >> 1; 2194 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2195 rx_que = &sc->rx_queues[i]; 2196 if (i & 1) { 2197 ivar &= 0xFF00FFFF; 2198 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2199 } else { 2200 ivar &= 0xFFFFFF00; 2201 ivar |= rx_que->msix | E1000_IVAR_VALID; 2202 } 2203 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2204 } 2205 /* TX entries */ 2206 for (int i = 0; i < sc->tx_num_queues; i++) { 2207 u32 index = i >> 1; 2208 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2209 tx_que = &sc->tx_queues[i]; 2210 if (i & 1) { 2211 ivar &= 0x00FFFFFF; 2212 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2213 } else { 2214 ivar &= 0xFFFF00FF; 2215 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2216 } 2217 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2218 sc->que_mask |= tx_que->eims; 2219 } 2220 2221 /* And for the link interrupt */ 2222 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2223 sc->link_mask = 1 << sc->linkvec; 2224 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2225 break; 2226 case e1000_82576: 2227 /* RX entries */ 2228 for (int i = 0; i < sc->rx_num_queues; i++) { 2229 u32 index = i & 0x7; /* Each IVAR has two entries */ 2230 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2231 rx_que = &sc->rx_queues[i]; 2232 if (i < 8) { 2233 ivar &= 0xFFFFFF00; 2234 ivar |= rx_que->msix | E1000_IVAR_VALID; 2235 } else { 2236 ivar &= 0xFF00FFFF; 2237 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2238 } 2239 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2240 sc->que_mask |= rx_que->eims; 2241 } 2242 /* TX entries */ 2243 for (int i = 0; i < sc->tx_num_queues; i++) { 2244 u32 index = i & 0x7; /* Each IVAR has two entries */ 2245 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2246 tx_que = &sc->tx_queues[i]; 2247 if (i < 8) { 2248 ivar &= 0xFFFF00FF; 2249 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2250 } else { 2251 ivar &= 0x00FFFFFF; 2252 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2253 } 2254 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2255 sc->que_mask |= tx_que->eims; 2256 } 2257 2258 /* And for the link interrupt */ 2259 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2260 sc->link_mask = 1 << sc->linkvec; 2261 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2262 break; 2263 2264 case e1000_82575: 2265 /* enable MSI-X support*/ 2266 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2267 tmp |= E1000_CTRL_EXT_PBA_CLR; 2268 /* Auto-Mask interrupts upon ICR read. */ 2269 tmp |= E1000_CTRL_EXT_EIAME; 2270 tmp |= E1000_CTRL_EXT_IRCA; 2271 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2272 2273 /* Queues */ 2274 for (int i = 0; i < sc->rx_num_queues; i++) { 2275 rx_que = &sc->rx_queues[i]; 2276 tmp = E1000_EICR_RX_QUEUE0 << i; 2277 tmp |= E1000_EICR_TX_QUEUE0 << i; 2278 rx_que->eims = tmp; 2279 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2280 i, rx_que->eims); 2281 sc->que_mask |= rx_que->eims; 2282 } 2283 2284 /* Link */ 2285 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2286 E1000_EIMS_OTHER); 2287 sc->link_mask |= E1000_EIMS_OTHER; 2288 default: 2289 break; 2290 } 2291 2292 /* Set the starting interrupt rate */ 2293 if (em_max_interrupt_rate > 0) 2294 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2295 2296 if (hw->mac.type == e1000_82575) 2297 newitr |= newitr << 16; 2298 else 2299 newitr |= E1000_EITR_CNT_IGNR; 2300 2301 for (int i = 0; i < sc->rx_num_queues; i++) { 2302 rx_que = &sc->rx_queues[i]; 2303 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2304 } 2305 2306 return; 2307 } 2308 2309 static void 2310 em_free_pci_resources(if_ctx_t ctx) 2311 { 2312 struct e1000_softc *sc = iflib_get_softc(ctx); 2313 struct em_rx_queue *que = sc->rx_queues; 2314 device_t dev = iflib_get_dev(ctx); 2315 2316 /* Release all MSI-X queue resources */ 2317 if (sc->intr_type == IFLIB_INTR_MSIX) 2318 iflib_irq_free(ctx, &sc->irq); 2319 2320 if (que != NULL) { 2321 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2322 iflib_irq_free(ctx, &que->que_irq); 2323 } 2324 } 2325 2326 if (sc->memory != NULL) { 2327 bus_release_resource(dev, SYS_RES_MEMORY, 2328 rman_get_rid(sc->memory), sc->memory); 2329 sc->memory = NULL; 2330 } 2331 2332 if (sc->flash != NULL) { 2333 bus_release_resource(dev, SYS_RES_MEMORY, 2334 rman_get_rid(sc->flash), sc->flash); 2335 sc->flash = NULL; 2336 } 2337 2338 if (sc->ioport != NULL) { 2339 bus_release_resource(dev, SYS_RES_IOPORT, 2340 rman_get_rid(sc->ioport), sc->ioport); 2341 sc->ioport = NULL; 2342 } 2343 } 2344 2345 /* Set up MSI or MSI-X */ 2346 static int 2347 em_setup_msix(if_ctx_t ctx) 2348 { 2349 struct e1000_softc *sc = iflib_get_softc(ctx); 2350 2351 if (sc->hw.mac.type == e1000_82574) { 2352 em_enable_vectors_82574(ctx); 2353 } 2354 return (0); 2355 } 2356 2357 /********************************************************************* 2358 * 2359 * Workaround for SmartSpeed on 82541 and 82547 controllers 2360 * 2361 **********************************************************************/ 2362 static void 2363 lem_smartspeed(struct e1000_softc *sc) 2364 { 2365 u16 phy_tmp; 2366 2367 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2368 sc->hw.mac.autoneg == 0 || 2369 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2370 return; 2371 2372 if (sc->smartspeed == 0) { 2373 /* If Master/Slave config fault is asserted twice, 2374 * we assume back-to-back */ 2375 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2376 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2377 return; 2378 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2379 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2380 e1000_read_phy_reg(&sc->hw, 2381 PHY_1000T_CTRL, &phy_tmp); 2382 if(phy_tmp & CR_1000T_MS_ENABLE) { 2383 phy_tmp &= ~CR_1000T_MS_ENABLE; 2384 e1000_write_phy_reg(&sc->hw, 2385 PHY_1000T_CTRL, phy_tmp); 2386 sc->smartspeed++; 2387 if(sc->hw.mac.autoneg && 2388 !e1000_copper_link_autoneg(&sc->hw) && 2389 !e1000_read_phy_reg(&sc->hw, 2390 PHY_CONTROL, &phy_tmp)) { 2391 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2392 MII_CR_RESTART_AUTO_NEG); 2393 e1000_write_phy_reg(&sc->hw, 2394 PHY_CONTROL, phy_tmp); 2395 } 2396 } 2397 } 2398 return; 2399 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2400 /* If still no link, perhaps using 2/3 pair cable */ 2401 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2402 phy_tmp |= CR_1000T_MS_ENABLE; 2403 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2404 if(sc->hw.mac.autoneg && 2405 !e1000_copper_link_autoneg(&sc->hw) && 2406 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2407 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2408 MII_CR_RESTART_AUTO_NEG); 2409 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2410 } 2411 } 2412 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2413 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2414 sc->smartspeed = 0; 2415 } 2416 2417 /********************************************************************* 2418 * 2419 * Initialize the DMA Coalescing feature 2420 * 2421 **********************************************************************/ 2422 static void 2423 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2424 { 2425 device_t dev = sc->dev; 2426 struct e1000_hw *hw = &sc->hw; 2427 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2428 u16 hwm; 2429 u16 max_frame_size; 2430 2431 if (hw->mac.type == e1000_i211) 2432 return; 2433 2434 max_frame_size = sc->shared->isc_max_frame_size; 2435 if (hw->mac.type > e1000_82580) { 2436 2437 if (sc->dmac == 0) { /* Disabling it */ 2438 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2439 return; 2440 } else 2441 device_printf(dev, "DMA Coalescing enabled\n"); 2442 2443 /* Set starting threshold */ 2444 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2445 2446 hwm = 64 * pba - max_frame_size / 16; 2447 if (hwm < 64 * (pba - 6)) 2448 hwm = 64 * (pba - 6); 2449 reg = E1000_READ_REG(hw, E1000_FCRTC); 2450 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2451 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2452 & E1000_FCRTC_RTH_COAL_MASK); 2453 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2454 2455 2456 dmac = pba - max_frame_size / 512; 2457 if (dmac < pba - 10) 2458 dmac = pba - 10; 2459 reg = E1000_READ_REG(hw, E1000_DMACR); 2460 reg &= ~E1000_DMACR_DMACTHR_MASK; 2461 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2462 & E1000_DMACR_DMACTHR_MASK); 2463 2464 /* transition to L0x or L1 if available..*/ 2465 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2466 2467 /* Check if status is 2.5Gb backplane connection 2468 * before configuration of watchdog timer, which is 2469 * in msec values in 12.8usec intervals 2470 * watchdog timer= msec values in 32usec intervals 2471 * for non 2.5Gb connection 2472 */ 2473 if (hw->mac.type == e1000_i354) { 2474 int status = E1000_READ_REG(hw, E1000_STATUS); 2475 if ((status & E1000_STATUS_2P5_SKU) && 2476 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2477 reg |= ((sc->dmac * 5) >> 6); 2478 else 2479 reg |= (sc->dmac >> 5); 2480 } else { 2481 reg |= (sc->dmac >> 5); 2482 } 2483 2484 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2485 2486 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2487 2488 /* Set the interval before transition */ 2489 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2490 if (hw->mac.type == e1000_i350) 2491 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2492 /* 2493 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2494 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2495 */ 2496 if (hw->mac.type == e1000_i354) { 2497 int status = E1000_READ_REG(hw, E1000_STATUS); 2498 if ((status & E1000_STATUS_2P5_SKU) && 2499 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2500 reg |= 0xA; 2501 else 2502 reg |= 0x4; 2503 } else { 2504 reg |= 0x4; 2505 } 2506 2507 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2508 2509 /* free space in tx packet buffer to wake from DMA coal */ 2510 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2511 (2 * max_frame_size)) >> 6); 2512 2513 /* make low power state decision controlled by DMA coal */ 2514 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2515 reg &= ~E1000_PCIEMISC_LX_DECISION; 2516 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2517 2518 } else if (hw->mac.type == e1000_82580) { 2519 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2520 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2521 reg & ~E1000_PCIEMISC_LX_DECISION); 2522 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2523 } 2524 } 2525 /********************************************************************* 2526 * The 3 following flush routines are used as a workaround in the 2527 * I219 client parts and only for them. 2528 * 2529 * em_flush_tx_ring - remove all descriptors from the tx_ring 2530 * 2531 * We want to clear all pending descriptors from the TX ring. 2532 * zeroing happens when the HW reads the regs. We assign the ring itself as 2533 * the data of the next descriptor. We don't care about the data we are about 2534 * to reset the HW. 2535 **********************************************************************/ 2536 static void 2537 em_flush_tx_ring(struct e1000_softc *sc) 2538 { 2539 struct e1000_hw *hw = &sc->hw; 2540 struct tx_ring *txr = &sc->tx_queues->txr; 2541 struct e1000_tx_desc *txd; 2542 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2543 u16 size = 512; 2544 2545 tctl = E1000_READ_REG(hw, E1000_TCTL); 2546 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2547 2548 txd = &txr->tx_base[txr->tx_cidx_processed]; 2549 2550 /* Just use the ring as a dummy buffer addr */ 2551 txd->buffer_addr = txr->tx_paddr; 2552 txd->lower.data = htole32(txd_lower | size); 2553 txd->upper.data = 0; 2554 2555 /* flush descriptors to memory before notifying the HW */ 2556 wmb(); 2557 2558 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2559 mb(); 2560 usec_delay(250); 2561 } 2562 2563 /********************************************************************* 2564 * em_flush_rx_ring - remove all descriptors from the rx_ring 2565 * 2566 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2567 **********************************************************************/ 2568 static void 2569 em_flush_rx_ring(struct e1000_softc *sc) 2570 { 2571 struct e1000_hw *hw = &sc->hw; 2572 u32 rctl, rxdctl; 2573 2574 rctl = E1000_READ_REG(hw, E1000_RCTL); 2575 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2576 E1000_WRITE_FLUSH(hw); 2577 usec_delay(150); 2578 2579 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2580 /* zero the lower 14 bits (prefetch and host thresholds) */ 2581 rxdctl &= 0xffffc000; 2582 /* 2583 * update thresholds: prefetch threshold to 31, host threshold to 1 2584 * and make sure the granularity is "descriptors" and not "cache lines" 2585 */ 2586 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2587 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2588 2589 /* momentarily enable the RX ring for the changes to take effect */ 2590 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2591 E1000_WRITE_FLUSH(hw); 2592 usec_delay(150); 2593 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2594 } 2595 2596 /********************************************************************* 2597 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2598 * 2599 * In I219, the descriptor rings must be emptied before resetting the HW 2600 * or before changing the device state to D3 during runtime (runtime PM). 2601 * 2602 * Failure to do this will cause the HW to enter a unit hang state which can 2603 * only be released by PCI reset on the device 2604 * 2605 **********************************************************************/ 2606 static void 2607 em_flush_desc_rings(struct e1000_softc *sc) 2608 { 2609 struct e1000_hw *hw = &sc->hw; 2610 device_t dev = sc->dev; 2611 u16 hang_state; 2612 u32 fext_nvm11, tdlen; 2613 2614 /* First, disable MULR fix in FEXTNVM11 */ 2615 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2616 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2617 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2618 2619 /* do nothing if we're not in faulty state, or if the queue is empty */ 2620 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2621 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2622 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2623 return; 2624 em_flush_tx_ring(sc); 2625 2626 /* recheck, maybe the fault is caused by the rx ring */ 2627 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2628 if (hang_state & FLUSH_DESC_REQUIRED) 2629 em_flush_rx_ring(sc); 2630 } 2631 2632 2633 /********************************************************************* 2634 * 2635 * Initialize the hardware to a configuration as specified by the 2636 * sc structure. 2637 * 2638 **********************************************************************/ 2639 static void 2640 em_reset(if_ctx_t ctx) 2641 { 2642 device_t dev = iflib_get_dev(ctx); 2643 struct e1000_softc *sc = iflib_get_softc(ctx); 2644 if_t ifp = iflib_get_ifp(ctx); 2645 struct e1000_hw *hw = &sc->hw; 2646 u32 rx_buffer_size; 2647 u32 pba; 2648 2649 INIT_DEBUGOUT("em_reset: begin"); 2650 /* Let the firmware know the OS is in control */ 2651 em_get_hw_control(sc); 2652 2653 /* Set up smart power down as default off on newer adapters. */ 2654 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2655 hw->mac.type == e1000_82572)) { 2656 u16 phy_tmp = 0; 2657 2658 /* Speed up time to link by disabling smart power down. */ 2659 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2660 phy_tmp &= ~IGP02E1000_PM_SPD; 2661 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2662 } 2663 2664 /* 2665 * Packet Buffer Allocation (PBA) 2666 * Writing PBA sets the receive portion of the buffer 2667 * the remainder is used for the transmit buffer. 2668 */ 2669 switch (hw->mac.type) { 2670 /* 82547: Total Packet Buffer is 40K */ 2671 case e1000_82547: 2672 case e1000_82547_rev_2: 2673 if (hw->mac.max_frame_size > 8192) 2674 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2675 else 2676 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2677 break; 2678 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2679 case e1000_82571: 2680 case e1000_82572: 2681 case e1000_80003es2lan: 2682 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2683 break; 2684 /* 82573: Total Packet Buffer is 32K */ 2685 case e1000_82573: 2686 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2687 break; 2688 case e1000_82574: 2689 case e1000_82583: 2690 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2691 break; 2692 case e1000_ich8lan: 2693 pba = E1000_PBA_8K; 2694 break; 2695 case e1000_ich9lan: 2696 case e1000_ich10lan: 2697 /* Boost Receive side for jumbo frames */ 2698 if (hw->mac.max_frame_size > 4096) 2699 pba = E1000_PBA_14K; 2700 else 2701 pba = E1000_PBA_10K; 2702 break; 2703 case e1000_pchlan: 2704 case e1000_pch2lan: 2705 case e1000_pch_lpt: 2706 case e1000_pch_spt: 2707 case e1000_pch_cnp: 2708 case e1000_pch_tgp: 2709 case e1000_pch_adp: 2710 case e1000_pch_mtp: 2711 case e1000_pch_ptp: 2712 pba = E1000_PBA_26K; 2713 break; 2714 case e1000_82575: 2715 pba = E1000_PBA_32K; 2716 break; 2717 case e1000_82576: 2718 case e1000_vfadapt: 2719 pba = E1000_READ_REG(hw, E1000_RXPBS); 2720 pba &= E1000_RXPBS_SIZE_MASK_82576; 2721 break; 2722 case e1000_82580: 2723 case e1000_i350: 2724 case e1000_i354: 2725 case e1000_vfadapt_i350: 2726 pba = E1000_READ_REG(hw, E1000_RXPBS); 2727 pba = e1000_rxpbs_adjust_82580(pba); 2728 break; 2729 case e1000_i210: 2730 case e1000_i211: 2731 pba = E1000_PBA_34K; 2732 break; 2733 default: 2734 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2735 if (hw->mac.max_frame_size > 8192) 2736 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2737 else 2738 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2739 } 2740 2741 /* Special needs in case of Jumbo frames */ 2742 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2743 u32 tx_space, min_tx, min_rx; 2744 pba = E1000_READ_REG(hw, E1000_PBA); 2745 tx_space = pba >> 16; 2746 pba &= 0xffff; 2747 min_tx = (hw->mac.max_frame_size + 2748 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2749 min_tx = roundup2(min_tx, 1024); 2750 min_tx >>= 10; 2751 min_rx = hw->mac.max_frame_size; 2752 min_rx = roundup2(min_rx, 1024); 2753 min_rx >>= 10; 2754 if (tx_space < min_tx && 2755 ((min_tx - tx_space) < pba)) { 2756 pba = pba - (min_tx - tx_space); 2757 /* 2758 * if short on rx space, rx wins 2759 * and must trump tx adjustment 2760 */ 2761 if (pba < min_rx) 2762 pba = min_rx; 2763 } 2764 E1000_WRITE_REG(hw, E1000_PBA, pba); 2765 } 2766 2767 if (hw->mac.type < igb_mac_min) 2768 E1000_WRITE_REG(hw, E1000_PBA, pba); 2769 2770 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2771 2772 /* 2773 * These parameters control the automatic generation (Tx) and 2774 * response (Rx) to Ethernet PAUSE frames. 2775 * - High water mark should allow for at least two frames to be 2776 * received after sending an XOFF. 2777 * - Low water mark works best when it is very near the high water mark. 2778 * This allows the receiver to restart by sending XON when it has 2779 * drained a bit. Here we use an arbitrary value of 1500 which will 2780 * restart after one full frame is pulled from the buffer. There 2781 * could be several smaller frames in the buffer and if so they will 2782 * not trigger the XON until their total number reduces the buffer 2783 * by 1500. 2784 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2785 */ 2786 rx_buffer_size = (pba & 0xffff) << 10; 2787 hw->fc.high_water = rx_buffer_size - 2788 roundup2(hw->mac.max_frame_size, 1024); 2789 hw->fc.low_water = hw->fc.high_water - 1500; 2790 2791 if (sc->fc) /* locally set flow control value? */ 2792 hw->fc.requested_mode = sc->fc; 2793 else 2794 hw->fc.requested_mode = e1000_fc_full; 2795 2796 if (hw->mac.type == e1000_80003es2lan) 2797 hw->fc.pause_time = 0xFFFF; 2798 else 2799 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2800 2801 hw->fc.send_xon = true; 2802 2803 /* Device specific overrides/settings */ 2804 switch (hw->mac.type) { 2805 case e1000_pchlan: 2806 /* Workaround: no TX flow ctrl for PCH */ 2807 hw->fc.requested_mode = e1000_fc_rx_pause; 2808 hw->fc.pause_time = 0xFFFF; /* override */ 2809 if (if_getmtu(ifp) > ETHERMTU) { 2810 hw->fc.high_water = 0x3500; 2811 hw->fc.low_water = 0x1500; 2812 } else { 2813 hw->fc.high_water = 0x5000; 2814 hw->fc.low_water = 0x3000; 2815 } 2816 hw->fc.refresh_time = 0x1000; 2817 break; 2818 case e1000_pch2lan: 2819 case e1000_pch_lpt: 2820 case e1000_pch_spt: 2821 case e1000_pch_cnp: 2822 case e1000_pch_tgp: 2823 case e1000_pch_adp: 2824 case e1000_pch_mtp: 2825 case e1000_pch_ptp: 2826 hw->fc.high_water = 0x5C20; 2827 hw->fc.low_water = 0x5048; 2828 hw->fc.pause_time = 0x0650; 2829 hw->fc.refresh_time = 0x0400; 2830 /* Jumbos need adjusted PBA */ 2831 if (if_getmtu(ifp) > ETHERMTU) 2832 E1000_WRITE_REG(hw, E1000_PBA, 12); 2833 else 2834 E1000_WRITE_REG(hw, E1000_PBA, 26); 2835 break; 2836 case e1000_82575: 2837 case e1000_82576: 2838 /* 8-byte granularity */ 2839 hw->fc.low_water = hw->fc.high_water - 8; 2840 break; 2841 case e1000_82580: 2842 case e1000_i350: 2843 case e1000_i354: 2844 case e1000_i210: 2845 case e1000_i211: 2846 case e1000_vfadapt: 2847 case e1000_vfadapt_i350: 2848 /* 16-byte granularity */ 2849 hw->fc.low_water = hw->fc.high_water - 16; 2850 break; 2851 case e1000_ich9lan: 2852 case e1000_ich10lan: 2853 if (if_getmtu(ifp) > ETHERMTU) { 2854 hw->fc.high_water = 0x2800; 2855 hw->fc.low_water = hw->fc.high_water - 8; 2856 break; 2857 } 2858 /* FALLTHROUGH */ 2859 default: 2860 if (hw->mac.type == e1000_80003es2lan) 2861 hw->fc.pause_time = 0xFFFF; 2862 break; 2863 } 2864 2865 /* I219 needs some special flushing to avoid hangs */ 2866 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2867 em_flush_desc_rings(sc); 2868 2869 /* Issue a global reset */ 2870 e1000_reset_hw(hw); 2871 if (hw->mac.type >= igb_mac_min) { 2872 E1000_WRITE_REG(hw, E1000_WUC, 0); 2873 } else { 2874 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2875 em_disable_aspm(sc); 2876 } 2877 if (sc->flags & IGB_MEDIA_RESET) { 2878 e1000_setup_init_funcs(hw, true); 2879 e1000_get_bus_info(hw); 2880 sc->flags &= ~IGB_MEDIA_RESET; 2881 } 2882 /* and a re-init */ 2883 if (e1000_init_hw(hw) < 0) { 2884 device_printf(dev, "Hardware Initialization Failed\n"); 2885 return; 2886 } 2887 if (hw->mac.type >= igb_mac_min) 2888 igb_init_dmac(sc, pba); 2889 2890 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2891 e1000_get_phy_info(hw); 2892 e1000_check_for_link(hw); 2893 } 2894 2895 /* 2896 * Initialise the RSS mapping for NICs that support multiple transmit/ 2897 * receive rings. 2898 */ 2899 2900 #define RSSKEYLEN 10 2901 static void 2902 em_initialize_rss_mapping(struct e1000_softc *sc) 2903 { 2904 uint8_t rss_key[4 * RSSKEYLEN]; 2905 uint32_t reta = 0; 2906 struct e1000_hw *hw = &sc->hw; 2907 int i; 2908 2909 /* 2910 * Configure RSS key 2911 */ 2912 arc4rand(rss_key, sizeof(rss_key), 0); 2913 for (i = 0; i < RSSKEYLEN; ++i) { 2914 uint32_t rssrk = 0; 2915 2916 rssrk = EM_RSSRK_VAL(rss_key, i); 2917 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2918 } 2919 2920 /* 2921 * Configure RSS redirect table in following fashion: 2922 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2923 */ 2924 for (i = 0; i < sizeof(reta); ++i) { 2925 uint32_t q; 2926 2927 q = (i % sc->rx_num_queues) << 7; 2928 reta |= q << (8 * i); 2929 } 2930 2931 for (i = 0; i < 32; ++i) 2932 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2933 2934 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2935 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2936 E1000_MRQC_RSS_FIELD_IPV4 | 2937 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2938 E1000_MRQC_RSS_FIELD_IPV6_EX | 2939 E1000_MRQC_RSS_FIELD_IPV6); 2940 } 2941 2942 static void 2943 igb_initialize_rss_mapping(struct e1000_softc *sc) 2944 { 2945 struct e1000_hw *hw = &sc->hw; 2946 int i; 2947 int queue_id; 2948 u32 reta; 2949 u32 rss_key[10], mrqc, shift = 0; 2950 2951 /* XXX? */ 2952 if (hw->mac.type == e1000_82575) 2953 shift = 6; 2954 2955 /* 2956 * The redirection table controls which destination 2957 * queue each bucket redirects traffic to. 2958 * Each DWORD represents four queues, with the LSB 2959 * being the first queue in the DWORD. 2960 * 2961 * This just allocates buckets to queues using round-robin 2962 * allocation. 2963 * 2964 * NOTE: It Just Happens to line up with the default 2965 * RSS allocation method. 2966 */ 2967 2968 /* Warning FM follows */ 2969 reta = 0; 2970 for (i = 0; i < 128; i++) { 2971 #ifdef RSS 2972 queue_id = rss_get_indirection_to_bucket(i); 2973 /* 2974 * If we have more queues than buckets, we'll 2975 * end up mapping buckets to a subset of the 2976 * queues. 2977 * 2978 * If we have more buckets than queues, we'll 2979 * end up instead assigning multiple buckets 2980 * to queues. 2981 * 2982 * Both are suboptimal, but we need to handle 2983 * the case so we don't go out of bounds 2984 * indexing arrays and such. 2985 */ 2986 queue_id = queue_id % sc->rx_num_queues; 2987 #else 2988 queue_id = (i % sc->rx_num_queues); 2989 #endif 2990 /* Adjust if required */ 2991 queue_id = queue_id << shift; 2992 2993 /* 2994 * The low 8 bits are for hash value (n+0); 2995 * The next 8 bits are for hash value (n+1), etc. 2996 */ 2997 reta = reta >> 8; 2998 reta = reta | ( ((uint32_t) queue_id) << 24); 2999 if ((i & 3) == 3) { 3000 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3001 reta = 0; 3002 } 3003 } 3004 3005 /* Now fill in hash table */ 3006 3007 /* 3008 * MRQC: Multiple Receive Queues Command 3009 * Set queuing to RSS control, number depends on the device. 3010 */ 3011 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3012 3013 #ifdef RSS 3014 /* XXX ew typecasting */ 3015 rss_getkey((uint8_t *) &rss_key); 3016 #else 3017 arc4rand(&rss_key, sizeof(rss_key), 0); 3018 #endif 3019 for (i = 0; i < 10; i++) 3020 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3021 3022 /* 3023 * Configure the RSS fields to hash upon. 3024 */ 3025 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3026 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3027 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3028 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3029 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3030 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3031 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3032 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3033 3034 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3035 } 3036 3037 /********************************************************************* 3038 * 3039 * Setup networking device structure and register interface media. 3040 * 3041 **********************************************************************/ 3042 static int 3043 em_setup_interface(if_ctx_t ctx) 3044 { 3045 if_t ifp = iflib_get_ifp(ctx); 3046 struct e1000_softc *sc = iflib_get_softc(ctx); 3047 if_softc_ctx_t scctx = sc->shared; 3048 3049 INIT_DEBUGOUT("em_setup_interface: begin"); 3050 3051 /* Single Queue */ 3052 if (sc->tx_num_queues == 1) { 3053 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3054 if_setsendqready(ifp); 3055 } 3056 3057 /* 3058 * Specify the media types supported by this adapter and register 3059 * callbacks to update media and link information 3060 */ 3061 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3062 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3063 u_char fiber_type = IFM_1000_SX; /* default type */ 3064 3065 if (sc->hw.mac.type == e1000_82545) 3066 fiber_type = IFM_1000_LX; 3067 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3068 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3069 } else { 3070 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3071 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3072 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3073 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3074 if (sc->hw.phy.type != e1000_phy_ife) { 3075 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3076 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3077 } 3078 } 3079 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3080 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3081 return (0); 3082 } 3083 3084 static int 3085 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3086 { 3087 struct e1000_softc *sc = iflib_get_softc(ctx); 3088 if_softc_ctx_t scctx = sc->shared; 3089 int error = E1000_SUCCESS; 3090 struct em_tx_queue *que; 3091 int i, j; 3092 3093 MPASS(sc->tx_num_queues > 0); 3094 MPASS(sc->tx_num_queues == ntxqsets); 3095 3096 /* First allocate the top level queue structs */ 3097 if (!(sc->tx_queues = 3098 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3099 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3100 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3101 return(ENOMEM); 3102 } 3103 3104 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3105 /* Set up some basics */ 3106 3107 struct tx_ring *txr = &que->txr; 3108 txr->sc = que->sc = sc; 3109 que->me = txr->me = i; 3110 3111 /* Allocate report status array */ 3112 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3113 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3114 error = ENOMEM; 3115 goto fail; 3116 } 3117 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3118 txr->tx_rsq[j] = QIDX_INVALID; 3119 /* get the virtual and physical address of the hardware queues */ 3120 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3121 txr->tx_paddr = paddrs[i*ntxqs]; 3122 } 3123 3124 if (bootverbose) 3125 device_printf(iflib_get_dev(ctx), 3126 "allocated for %d tx_queues\n", sc->tx_num_queues); 3127 return (0); 3128 fail: 3129 em_if_queues_free(ctx); 3130 return (error); 3131 } 3132 3133 static int 3134 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3135 { 3136 struct e1000_softc *sc = iflib_get_softc(ctx); 3137 int error = E1000_SUCCESS; 3138 struct em_rx_queue *que; 3139 int i; 3140 3141 MPASS(sc->rx_num_queues > 0); 3142 MPASS(sc->rx_num_queues == nrxqsets); 3143 3144 /* First allocate the top level queue structs */ 3145 if (!(sc->rx_queues = 3146 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3147 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3148 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3149 error = ENOMEM; 3150 goto fail; 3151 } 3152 3153 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3154 /* Set up some basics */ 3155 struct rx_ring *rxr = &que->rxr; 3156 rxr->sc = que->sc = sc; 3157 rxr->que = que; 3158 que->me = rxr->me = i; 3159 3160 /* get the virtual and physical address of the hardware queues */ 3161 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3162 rxr->rx_paddr = paddrs[i*nrxqs]; 3163 } 3164 3165 if (bootverbose) 3166 device_printf(iflib_get_dev(ctx), 3167 "allocated for %d rx_queues\n", sc->rx_num_queues); 3168 3169 return (0); 3170 fail: 3171 em_if_queues_free(ctx); 3172 return (error); 3173 } 3174 3175 static void 3176 em_if_queues_free(if_ctx_t ctx) 3177 { 3178 struct e1000_softc *sc = iflib_get_softc(ctx); 3179 struct em_tx_queue *tx_que = sc->tx_queues; 3180 struct em_rx_queue *rx_que = sc->rx_queues; 3181 3182 if (tx_que != NULL) { 3183 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3184 struct tx_ring *txr = &tx_que->txr; 3185 if (txr->tx_rsq == NULL) 3186 break; 3187 3188 free(txr->tx_rsq, M_DEVBUF); 3189 txr->tx_rsq = NULL; 3190 } 3191 free(sc->tx_queues, M_DEVBUF); 3192 sc->tx_queues = NULL; 3193 } 3194 3195 if (rx_que != NULL) { 3196 free(sc->rx_queues, M_DEVBUF); 3197 sc->rx_queues = NULL; 3198 } 3199 } 3200 3201 /********************************************************************* 3202 * 3203 * Enable transmit unit. 3204 * 3205 **********************************************************************/ 3206 static void 3207 em_initialize_transmit_unit(if_ctx_t ctx) 3208 { 3209 struct e1000_softc *sc = iflib_get_softc(ctx); 3210 if_softc_ctx_t scctx = sc->shared; 3211 struct em_tx_queue *que; 3212 struct tx_ring *txr; 3213 struct e1000_hw *hw = &sc->hw; 3214 u32 tctl, txdctl = 0, tarc, tipg = 0; 3215 3216 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3217 3218 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3219 u64 bus_addr; 3220 caddr_t offp, endp; 3221 3222 que = &sc->tx_queues[i]; 3223 txr = &que->txr; 3224 bus_addr = txr->tx_paddr; 3225 3226 /* Clear checksum offload context. */ 3227 offp = (caddr_t)&txr->csum_flags; 3228 endp = (caddr_t)(txr + 1); 3229 bzero(offp, endp - offp); 3230 3231 /* Base and Len of TX Ring */ 3232 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3233 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3234 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3235 (u32)(bus_addr >> 32)); 3236 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3237 (u32)bus_addr); 3238 /* Init the HEAD/TAIL indices */ 3239 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3240 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3241 3242 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3243 E1000_READ_REG(hw, E1000_TDBAL(i)), 3244 E1000_READ_REG(hw, E1000_TDLEN(i))); 3245 3246 txdctl = 0; /* clear txdctl */ 3247 txdctl |= 0x1f; /* PTHRESH */ 3248 txdctl |= 1 << 8; /* HTHRESH */ 3249 txdctl |= 1 << 16;/* WTHRESH */ 3250 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3251 txdctl |= E1000_TXDCTL_GRAN; 3252 txdctl |= 1 << 25; /* LWTHRESH */ 3253 3254 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3255 } 3256 3257 /* Set the default values for the Tx Inter Packet Gap timer */ 3258 switch (hw->mac.type) { 3259 case e1000_80003es2lan: 3260 tipg = DEFAULT_82543_TIPG_IPGR1; 3261 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3262 E1000_TIPG_IPGR2_SHIFT; 3263 break; 3264 case e1000_82542: 3265 tipg = DEFAULT_82542_TIPG_IPGT; 3266 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3267 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3268 break; 3269 default: 3270 if (hw->phy.media_type == e1000_media_type_fiber || 3271 hw->phy.media_type == e1000_media_type_internal_serdes) 3272 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3273 else 3274 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3275 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3276 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3277 } 3278 3279 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3280 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3281 3282 if(hw->mac.type >= e1000_82540) 3283 E1000_WRITE_REG(hw, E1000_TADV, 3284 sc->tx_abs_int_delay.value); 3285 3286 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3287 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3288 tarc |= TARC_SPEED_MODE_BIT; 3289 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3290 } else if (hw->mac.type == e1000_80003es2lan) { 3291 /* errata: program both queues to unweighted RR */ 3292 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3293 tarc |= 1; 3294 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3295 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3296 tarc |= 1; 3297 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3298 } else if (hw->mac.type == e1000_82574) { 3299 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3300 tarc |= TARC_ERRATA_BIT; 3301 if ( sc->tx_num_queues > 1) { 3302 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3303 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3304 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3305 } else 3306 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3307 } 3308 3309 if (sc->tx_int_delay.value > 0) 3310 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3311 3312 /* Program the Transmit Control Register */ 3313 tctl = E1000_READ_REG(hw, E1000_TCTL); 3314 tctl &= ~E1000_TCTL_CT; 3315 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3316 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3317 3318 if (hw->mac.type >= e1000_82571) 3319 tctl |= E1000_TCTL_MULR; 3320 3321 /* This write will effectively turn on the transmit unit. */ 3322 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3323 3324 /* SPT and KBL errata workarounds */ 3325 if (hw->mac.type == e1000_pch_spt) { 3326 u32 reg; 3327 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3328 reg |= E1000_RCTL_RDMTS_HEX; 3329 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3330 /* i218-i219 Specification Update 1.5.4.5 */ 3331 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3332 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3333 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3334 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3335 } 3336 } 3337 3338 /********************************************************************* 3339 * 3340 * Enable receive unit. 3341 * 3342 **********************************************************************/ 3343 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3344 3345 static void 3346 em_initialize_receive_unit(if_ctx_t ctx) 3347 { 3348 struct e1000_softc *sc = iflib_get_softc(ctx); 3349 if_softc_ctx_t scctx = sc->shared; 3350 if_t ifp = iflib_get_ifp(ctx); 3351 struct e1000_hw *hw = &sc->hw; 3352 struct em_rx_queue *que; 3353 int i; 3354 uint32_t rctl, rxcsum; 3355 3356 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3357 3358 /* 3359 * Make sure receives are disabled while setting 3360 * up the descriptor ring 3361 */ 3362 rctl = E1000_READ_REG(hw, E1000_RCTL); 3363 /* Do not disable if ever enabled on this hardware */ 3364 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3365 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3366 3367 /* Setup the Receive Control Register */ 3368 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3369 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3370 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3371 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3372 3373 /* Do not store bad packets */ 3374 rctl &= ~E1000_RCTL_SBP; 3375 3376 /* Enable Long Packet receive */ 3377 if (if_getmtu(ifp) > ETHERMTU) 3378 rctl |= E1000_RCTL_LPE; 3379 else 3380 rctl &= ~E1000_RCTL_LPE; 3381 3382 /* Strip the CRC */ 3383 if (!em_disable_crc_stripping) 3384 rctl |= E1000_RCTL_SECRC; 3385 3386 if (hw->mac.type >= e1000_82540) { 3387 E1000_WRITE_REG(hw, E1000_RADV, 3388 sc->rx_abs_int_delay.value); 3389 3390 /* 3391 * Set the interrupt throttling rate. Value is calculated 3392 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3393 */ 3394 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3395 } 3396 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3397 3398 if (hw->mac.type >= em_mac_min) { 3399 uint32_t rfctl; 3400 /* Use extended rx descriptor formats */ 3401 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3402 rfctl |= E1000_RFCTL_EXTEN; 3403 3404 /* 3405 * When using MSI-X interrupts we need to throttle 3406 * using the EITR register (82574 only) 3407 */ 3408 if (hw->mac.type == e1000_82574) { 3409 for (int i = 0; i < 4; i++) 3410 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3411 DEFAULT_ITR); 3412 /* Disable accelerated acknowledge */ 3413 rfctl |= E1000_RFCTL_ACK_DIS; 3414 } 3415 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3416 } 3417 3418 /* Set up L3 and L4 csum Rx descriptor offloads */ 3419 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3420 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3421 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3422 if (hw->mac.type > e1000_82575) 3423 rxcsum |= E1000_RXCSUM_CRCOFL; 3424 else if (hw->mac.type < em_mac_min && 3425 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3426 rxcsum |= E1000_RXCSUM_IPV6OFL; 3427 } else { 3428 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3429 if (hw->mac.type > e1000_82575) 3430 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3431 else if (hw->mac.type < em_mac_min) 3432 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3433 } 3434 3435 if (sc->rx_num_queues > 1) { 3436 /* RSS hash needed in the Rx descriptor */ 3437 rxcsum |= E1000_RXCSUM_PCSD; 3438 3439 if (hw->mac.type >= igb_mac_min) 3440 igb_initialize_rss_mapping(sc); 3441 else 3442 em_initialize_rss_mapping(sc); 3443 } 3444 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3445 3446 /* 3447 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3448 * long latencies are observed, like Lenovo X60. This 3449 * change eliminates the problem, but since having positive 3450 * values in RDTR is a known source of problems on other 3451 * platforms another solution is being sought. 3452 */ 3453 if (hw->mac.type == e1000_82573) 3454 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3455 3456 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3457 struct rx_ring *rxr = &que->rxr; 3458 /* Setup the Base and Length of the Rx Descriptor Ring */ 3459 u64 bus_addr = rxr->rx_paddr; 3460 #if 0 3461 u32 rdt = sc->rx_num_queues -1; /* default */ 3462 #endif 3463 3464 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3465 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3466 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3467 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3468 /* Setup the Head and Tail Descriptor Pointers */ 3469 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3470 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3471 } 3472 3473 /* 3474 * Set PTHRESH for improved jumbo performance 3475 * According to 10.2.5.11 of Intel 82574 Datasheet, 3476 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3477 * Only write to RXDCTL(1) if there is a need for different 3478 * settings. 3479 */ 3480 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3481 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3482 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3483 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3484 } else if (hw->mac.type == e1000_82574) { 3485 for (int i = 0; i < sc->rx_num_queues; i++) { 3486 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3487 rxdctl |= 0x20; /* PTHRESH */ 3488 rxdctl |= 4 << 8; /* HTHRESH */ 3489 rxdctl |= 4 << 16;/* WTHRESH */ 3490 rxdctl |= 1 << 24; /* Switch to granularity */ 3491 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3492 } 3493 } else if (hw->mac.type >= igb_mac_min) { 3494 u32 psize, srrctl = 0; 3495 3496 if (if_getmtu(ifp) > ETHERMTU) { 3497 psize = scctx->isc_max_frame_size; 3498 /* are we on a vlan? */ 3499 if (if_vlantrunkinuse(ifp)) 3500 psize += VLAN_TAG_SIZE; 3501 3502 if (sc->vf_ifp) 3503 e1000_rlpml_set_vf(hw, psize); 3504 else 3505 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3506 } 3507 3508 /* Set maximum packet buffer len */ 3509 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3510 E1000_SRRCTL_BSIZEPKT_SHIFT; 3511 3512 /* 3513 * If TX flow control is disabled and there's >1 queue defined, 3514 * enable DROP. 3515 * 3516 * This drops frames rather than hanging the RX MAC for all queues. 3517 */ 3518 if ((sc->rx_num_queues > 1) && 3519 (sc->fc == e1000_fc_none || 3520 sc->fc == e1000_fc_rx_pause)) { 3521 srrctl |= E1000_SRRCTL_DROP_EN; 3522 } 3523 /* Setup the Base and Length of the Rx Descriptor Rings */ 3524 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3525 struct rx_ring *rxr = &que->rxr; 3526 u64 bus_addr = rxr->rx_paddr; 3527 u32 rxdctl; 3528 3529 #ifdef notyet 3530 /* Configure for header split? -- ignore for now */ 3531 rxr->hdr_split = igb_header_split; 3532 #else 3533 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3534 #endif 3535 3536 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3537 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3538 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3539 (uint32_t)(bus_addr >> 32)); 3540 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3541 (uint32_t)bus_addr); 3542 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3543 /* Enable this Queue */ 3544 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3545 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3546 rxdctl &= 0xFFF00000; 3547 rxdctl |= IGB_RX_PTHRESH; 3548 rxdctl |= IGB_RX_HTHRESH << 8; 3549 rxdctl |= IGB_RX_WTHRESH << 16; 3550 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3551 } 3552 } else if (hw->mac.type >= e1000_pch2lan) { 3553 if (if_getmtu(ifp) > ETHERMTU) 3554 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3555 else 3556 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3557 } 3558 3559 /* Make sure VLAN Filters are off */ 3560 rctl &= ~E1000_RCTL_VFE; 3561 3562 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3563 if (hw->mac.type < igb_mac_min) { 3564 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3565 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3566 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3567 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3568 else if (sc->rx_mbuf_sz > 8192) 3569 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3570 else { 3571 rctl |= E1000_RCTL_SZ_2048; 3572 rctl &= ~E1000_RCTL_BSEX; 3573 } 3574 } else 3575 rctl |= E1000_RCTL_SZ_2048; 3576 3577 /* 3578 * rctl bits 11:10 are as follows 3579 * lem: reserved 3580 * em: DTYPE 3581 * igb: reserved 3582 * and should be 00 on all of the above 3583 */ 3584 rctl &= ~0x00000C00; 3585 3586 /* Write out the settings */ 3587 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3588 3589 return; 3590 } 3591 3592 static void 3593 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3594 { 3595 struct e1000_softc *sc = iflib_get_softc(ctx); 3596 u32 index, bit; 3597 3598 index = (vtag >> 5) & 0x7F; 3599 bit = vtag & 0x1F; 3600 sc->shadow_vfta[index] |= (1 << bit); 3601 ++sc->num_vlans; 3602 em_if_vlan_filter_write(sc); 3603 } 3604 3605 static void 3606 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3607 { 3608 struct e1000_softc *sc = iflib_get_softc(ctx); 3609 u32 index, bit; 3610 3611 index = (vtag >> 5) & 0x7F; 3612 bit = vtag & 0x1F; 3613 sc->shadow_vfta[index] &= ~(1 << bit); 3614 --sc->num_vlans; 3615 em_if_vlan_filter_write(sc); 3616 } 3617 3618 static bool 3619 em_if_vlan_filter_capable(if_ctx_t ctx) 3620 { 3621 if_t ifp = iflib_get_ifp(ctx); 3622 3623 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3624 !em_disable_crc_stripping) 3625 return (true); 3626 3627 return (false); 3628 } 3629 3630 static bool 3631 em_if_vlan_filter_used(if_ctx_t ctx) 3632 { 3633 struct e1000_softc *sc = iflib_get_softc(ctx); 3634 3635 if (!em_if_vlan_filter_capable(ctx)) 3636 return (false); 3637 3638 for (int i = 0; i < EM_VFTA_SIZE; i++) 3639 if (sc->shadow_vfta[i] != 0) 3640 return (true); 3641 3642 return (false); 3643 } 3644 3645 static void 3646 em_if_vlan_filter_enable(struct e1000_softc *sc) 3647 { 3648 struct e1000_hw *hw = &sc->hw; 3649 u32 reg; 3650 3651 reg = E1000_READ_REG(hw, E1000_RCTL); 3652 reg &= ~E1000_RCTL_CFIEN; 3653 reg |= E1000_RCTL_VFE; 3654 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3655 } 3656 3657 static void 3658 em_if_vlan_filter_disable(struct e1000_softc *sc) 3659 { 3660 struct e1000_hw *hw = &sc->hw; 3661 u32 reg; 3662 3663 reg = E1000_READ_REG(hw, E1000_RCTL); 3664 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3665 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3666 } 3667 3668 static void 3669 em_if_vlan_filter_write(struct e1000_softc *sc) 3670 { 3671 struct e1000_hw *hw = &sc->hw; 3672 3673 if (sc->vf_ifp) 3674 return; 3675 3676 /* Disable interrupts for lem-class devices during the filter change */ 3677 if (hw->mac.type < em_mac_min) 3678 em_if_intr_disable(sc->ctx); 3679 3680 for (int i = 0; i < EM_VFTA_SIZE; i++) 3681 if (sc->shadow_vfta[i] != 0) { 3682 /* XXXKB: incomplete VF support, we return early above */ 3683 if (sc->vf_ifp) 3684 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3685 else 3686 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3687 } 3688 3689 /* Re-enable interrupts for lem-class devices */ 3690 if (hw->mac.type < em_mac_min) 3691 em_if_intr_enable(sc->ctx); 3692 } 3693 3694 static void 3695 em_setup_vlan_hw_support(if_ctx_t ctx) 3696 { 3697 struct e1000_softc *sc = iflib_get_softc(ctx); 3698 struct e1000_hw *hw = &sc->hw; 3699 if_t ifp = iflib_get_ifp(ctx); 3700 u32 reg; 3701 3702 /* XXXKB: Return early if we are a VF until VF decap and filter management 3703 * is ready and tested. 3704 */ 3705 if (sc->vf_ifp) 3706 return; 3707 3708 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3709 !em_disable_crc_stripping) { 3710 reg = E1000_READ_REG(hw, E1000_CTRL); 3711 reg |= E1000_CTRL_VME; 3712 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3713 } else { 3714 reg = E1000_READ_REG(hw, E1000_CTRL); 3715 reg &= ~E1000_CTRL_VME; 3716 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3717 } 3718 3719 /* If we aren't doing HW filtering, we're done */ 3720 if (!em_if_vlan_filter_capable(ctx)) { 3721 em_if_vlan_filter_disable(sc); 3722 return; 3723 } 3724 3725 /* 3726 * A soft reset zero's out the VFTA, so 3727 * we need to repopulate it now. 3728 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3729 * traffic through. This will write the entire table. 3730 */ 3731 em_if_vlan_register(ctx, 0); 3732 3733 /* Enable the Filter Table */ 3734 em_if_vlan_filter_enable(sc); 3735 } 3736 3737 static void 3738 em_if_intr_enable(if_ctx_t ctx) 3739 { 3740 struct e1000_softc *sc = iflib_get_softc(ctx); 3741 struct e1000_hw *hw = &sc->hw; 3742 u32 ims_mask = IMS_ENABLE_MASK; 3743 3744 if (sc->intr_type == IFLIB_INTR_MSIX) { 3745 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3746 ims_mask |= sc->ims; 3747 } 3748 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3749 E1000_WRITE_FLUSH(hw); 3750 } 3751 3752 static void 3753 em_if_intr_disable(if_ctx_t ctx) 3754 { 3755 struct e1000_softc *sc = iflib_get_softc(ctx); 3756 struct e1000_hw *hw = &sc->hw; 3757 3758 if (sc->intr_type == IFLIB_INTR_MSIX) 3759 E1000_WRITE_REG(hw, EM_EIAC, 0); 3760 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3761 E1000_WRITE_FLUSH(hw); 3762 } 3763 3764 static void 3765 igb_if_intr_enable(if_ctx_t ctx) 3766 { 3767 struct e1000_softc *sc = iflib_get_softc(ctx); 3768 struct e1000_hw *hw = &sc->hw; 3769 u32 mask; 3770 3771 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3772 mask = (sc->que_mask | sc->link_mask); 3773 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3774 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3775 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3776 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3777 } else 3778 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3779 E1000_WRITE_FLUSH(hw); 3780 } 3781 3782 static void 3783 igb_if_intr_disable(if_ctx_t ctx) 3784 { 3785 struct e1000_softc *sc = iflib_get_softc(ctx); 3786 struct e1000_hw *hw = &sc->hw; 3787 3788 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3789 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3790 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3791 } 3792 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3793 E1000_WRITE_FLUSH(hw); 3794 } 3795 3796 /* 3797 * Bit of a misnomer, what this really means is 3798 * to enable OS management of the system... aka 3799 * to disable special hardware management features 3800 */ 3801 static void 3802 em_init_manageability(struct e1000_softc *sc) 3803 { 3804 /* A shared code workaround */ 3805 #define E1000_82542_MANC2H E1000_MANC2H 3806 if (sc->has_manage) { 3807 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3808 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3809 3810 /* disable hardware interception of ARP */ 3811 manc &= ~(E1000_MANC_ARP_EN); 3812 3813 /* enable receiving management packets to the host */ 3814 manc |= E1000_MANC_EN_MNG2HOST; 3815 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3816 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3817 manc2h |= E1000_MNG2HOST_PORT_623; 3818 manc2h |= E1000_MNG2HOST_PORT_664; 3819 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3820 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3821 } 3822 } 3823 3824 /* 3825 * Give control back to hardware management 3826 * controller if there is one. 3827 */ 3828 static void 3829 em_release_manageability(struct e1000_softc *sc) 3830 { 3831 if (sc->has_manage) { 3832 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3833 3834 /* re-enable hardware interception of ARP */ 3835 manc |= E1000_MANC_ARP_EN; 3836 manc &= ~E1000_MANC_EN_MNG2HOST; 3837 3838 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3839 } 3840 } 3841 3842 /* 3843 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3844 * For ASF and Pass Through versions of f/w this means 3845 * that the driver is loaded. For AMT version type f/w 3846 * this means that the network i/f is open. 3847 */ 3848 static void 3849 em_get_hw_control(struct e1000_softc *sc) 3850 { 3851 u32 ctrl_ext, swsm; 3852 3853 if (sc->vf_ifp) 3854 return; 3855 3856 if (sc->hw.mac.type == e1000_82573) { 3857 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3858 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3859 swsm | E1000_SWSM_DRV_LOAD); 3860 return; 3861 } 3862 /* else */ 3863 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3864 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3865 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3866 } 3867 3868 /* 3869 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3870 * For ASF and Pass Through versions of f/w this means that 3871 * the driver is no longer loaded. For AMT versions of the 3872 * f/w this means that the network i/f is closed. 3873 */ 3874 static void 3875 em_release_hw_control(struct e1000_softc *sc) 3876 { 3877 u32 ctrl_ext, swsm; 3878 3879 if (!sc->has_manage) 3880 return; 3881 3882 if (sc->hw.mac.type == e1000_82573) { 3883 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3884 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3885 swsm & ~E1000_SWSM_DRV_LOAD); 3886 return; 3887 } 3888 /* else */ 3889 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3890 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3891 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3892 return; 3893 } 3894 3895 static int 3896 em_is_valid_ether_addr(u8 *addr) 3897 { 3898 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3899 3900 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3901 return (false); 3902 } 3903 3904 return (true); 3905 } 3906 3907 static bool 3908 em_automask_tso(if_ctx_t ctx) 3909 { 3910 struct e1000_softc *sc = iflib_get_softc(ctx); 3911 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 3912 if_t ifp = iflib_get_ifp(ctx); 3913 3914 if (!em_unsupported_tso && sc->link_speed && 3915 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 3916 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 3917 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 3918 scctx->isc_capenable &= ~IFCAP_TSO; 3919 if_setcapenablebit(ifp, 0, IFCAP_TSO); 3920 /* iflib_init_locked handles ifnet hwassistbits */ 3921 iflib_request_reset(ctx); 3922 return true; 3923 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 3924 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 3925 scctx->isc_capenable |= sc->tso_automasked; 3926 if_setcapenablebit(ifp, sc->tso_automasked, 0); 3927 sc->tso_automasked = 0; 3928 /* iflib_init_locked handles ifnet hwassistbits */ 3929 iflib_request_reset(ctx); 3930 return true; 3931 } 3932 3933 return false; 3934 } 3935 3936 /* 3937 ** Parse the interface capabilities with regard 3938 ** to both system management and wake-on-lan for 3939 ** later use. 3940 */ 3941 static void 3942 em_get_wakeup(if_ctx_t ctx) 3943 { 3944 struct e1000_softc *sc = iflib_get_softc(ctx); 3945 device_t dev = iflib_get_dev(ctx); 3946 u16 eeprom_data = 0, device_id, apme_mask; 3947 3948 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3949 apme_mask = EM_EEPROM_APME; 3950 3951 switch (sc->hw.mac.type) { 3952 case e1000_82542: 3953 case e1000_82543: 3954 break; 3955 case e1000_82544: 3956 e1000_read_nvm(&sc->hw, 3957 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3958 apme_mask = EM_82544_APME; 3959 break; 3960 case e1000_82546: 3961 case e1000_82546_rev_3: 3962 if (sc->hw.bus.func == 1) { 3963 e1000_read_nvm(&sc->hw, 3964 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3965 break; 3966 } else 3967 e1000_read_nvm(&sc->hw, 3968 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3969 break; 3970 case e1000_82573: 3971 case e1000_82583: 3972 sc->has_amt = true; 3973 /* FALLTHROUGH */ 3974 case e1000_82571: 3975 case e1000_82572: 3976 case e1000_80003es2lan: 3977 if (sc->hw.bus.func == 1) { 3978 e1000_read_nvm(&sc->hw, 3979 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3980 break; 3981 } else 3982 e1000_read_nvm(&sc->hw, 3983 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3984 break; 3985 case e1000_ich8lan: 3986 case e1000_ich9lan: 3987 case e1000_ich10lan: 3988 case e1000_pchlan: 3989 case e1000_pch2lan: 3990 case e1000_pch_lpt: 3991 case e1000_pch_spt: 3992 case e1000_82575: /* listing all igb devices */ 3993 case e1000_82576: 3994 case e1000_82580: 3995 case e1000_i350: 3996 case e1000_i354: 3997 case e1000_i210: 3998 case e1000_i211: 3999 case e1000_vfadapt: 4000 case e1000_vfadapt_i350: 4001 apme_mask = E1000_WUC_APME; 4002 sc->has_amt = true; 4003 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4004 break; 4005 default: 4006 e1000_read_nvm(&sc->hw, 4007 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4008 break; 4009 } 4010 if (eeprom_data & apme_mask) 4011 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4012 /* 4013 * We have the eeprom settings, now apply the special cases 4014 * where the eeprom may be wrong or the board won't support 4015 * wake on lan on a particular port 4016 */ 4017 device_id = pci_get_device(dev); 4018 switch (device_id) { 4019 case E1000_DEV_ID_82546GB_PCIE: 4020 sc->wol = 0; 4021 break; 4022 case E1000_DEV_ID_82546EB_FIBER: 4023 case E1000_DEV_ID_82546GB_FIBER: 4024 /* Wake events only supported on port A for dual fiber 4025 * regardless of eeprom setting */ 4026 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4027 E1000_STATUS_FUNC_1) 4028 sc->wol = 0; 4029 break; 4030 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4031 /* if quad port adapter, disable WoL on all but port A */ 4032 if (global_quad_port_a != 0) 4033 sc->wol = 0; 4034 /* Reset for multiple quad port adapters */ 4035 if (++global_quad_port_a == 4) 4036 global_quad_port_a = 0; 4037 break; 4038 case E1000_DEV_ID_82571EB_FIBER: 4039 /* Wake events only supported on port A for dual fiber 4040 * regardless of eeprom setting */ 4041 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4042 E1000_STATUS_FUNC_1) 4043 sc->wol = 0; 4044 break; 4045 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4046 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4047 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4048 /* if quad port adapter, disable WoL on all but port A */ 4049 if (global_quad_port_a != 0) 4050 sc->wol = 0; 4051 /* Reset for multiple quad port adapters */ 4052 if (++global_quad_port_a == 4) 4053 global_quad_port_a = 0; 4054 break; 4055 } 4056 return; 4057 } 4058 4059 4060 /* 4061 * Enable PCI Wake On Lan capability 4062 */ 4063 static void 4064 em_enable_wakeup(if_ctx_t ctx) 4065 { 4066 struct e1000_softc *sc = iflib_get_softc(ctx); 4067 device_t dev = iflib_get_dev(ctx); 4068 if_t ifp = iflib_get_ifp(ctx); 4069 int error = 0; 4070 u32 pmc, ctrl, ctrl_ext, rctl; 4071 u16 status; 4072 4073 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4074 return; 4075 4076 /* 4077 * Determine type of Wakeup: note that wol 4078 * is set with all bits on by default. 4079 */ 4080 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4081 sc->wol &= ~E1000_WUFC_MAG; 4082 4083 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4084 sc->wol &= ~E1000_WUFC_EX; 4085 4086 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4087 sc->wol &= ~E1000_WUFC_MC; 4088 else { 4089 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4090 rctl |= E1000_RCTL_MPE; 4091 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4092 } 4093 4094 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4095 goto pme; 4096 4097 /* Advertise the wakeup capability */ 4098 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4099 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4100 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4101 4102 /* Keep the laser running on Fiber adapters */ 4103 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4104 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4105 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4106 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4107 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4108 } 4109 4110 if ((sc->hw.mac.type == e1000_ich8lan) || 4111 (sc->hw.mac.type == e1000_pchlan) || 4112 (sc->hw.mac.type == e1000_ich9lan) || 4113 (sc->hw.mac.type == e1000_ich10lan)) 4114 e1000_suspend_workarounds_ich8lan(&sc->hw); 4115 4116 if ( sc->hw.mac.type >= e1000_pchlan) { 4117 error = em_enable_phy_wakeup(sc); 4118 if (error) 4119 goto pme; 4120 } else { 4121 /* Enable wakeup by the MAC */ 4122 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4123 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4124 } 4125 4126 if (sc->hw.phy.type == e1000_phy_igp_3) 4127 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4128 4129 pme: 4130 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4131 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4132 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4133 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4134 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4135 4136 return; 4137 } 4138 4139 /* 4140 * WOL in the newer chipset interfaces (pchlan) 4141 * require thing to be copied into the phy 4142 */ 4143 static int 4144 em_enable_phy_wakeup(struct e1000_softc *sc) 4145 { 4146 struct e1000_hw *hw = &sc->hw; 4147 u32 mreg, ret = 0; 4148 u16 preg; 4149 4150 /* copy MAC RARs to PHY RARs */ 4151 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4152 4153 /* copy MAC MTA to PHY MTA */ 4154 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4155 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4156 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4157 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4158 (u16)((mreg >> 16) & 0xFFFF)); 4159 } 4160 4161 /* configure PHY Rx Control register */ 4162 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4163 mreg = E1000_READ_REG(hw, E1000_RCTL); 4164 if (mreg & E1000_RCTL_UPE) 4165 preg |= BM_RCTL_UPE; 4166 if (mreg & E1000_RCTL_MPE) 4167 preg |= BM_RCTL_MPE; 4168 preg &= ~(BM_RCTL_MO_MASK); 4169 if (mreg & E1000_RCTL_MO_3) 4170 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4171 << BM_RCTL_MO_SHIFT); 4172 if (mreg & E1000_RCTL_BAM) 4173 preg |= BM_RCTL_BAM; 4174 if (mreg & E1000_RCTL_PMCF) 4175 preg |= BM_RCTL_PMCF; 4176 mreg = E1000_READ_REG(hw, E1000_CTRL); 4177 if (mreg & E1000_CTRL_RFCE) 4178 preg |= BM_RCTL_RFCE; 4179 e1000_write_phy_reg(hw, BM_RCTL, preg); 4180 4181 /* enable PHY wakeup in MAC register */ 4182 E1000_WRITE_REG(hw, E1000_WUC, 4183 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4184 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4185 4186 /* configure and enable PHY wakeup in PHY registers */ 4187 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4188 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4189 4190 /* activate PHY wakeup */ 4191 ret = hw->phy.ops.acquire(hw); 4192 if (ret) { 4193 printf("Could not acquire PHY\n"); 4194 return ret; 4195 } 4196 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4197 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4198 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4199 if (ret) { 4200 printf("Could not read PHY page 769\n"); 4201 goto out; 4202 } 4203 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4204 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4205 if (ret) 4206 printf("Could not set PHY Host Wakeup bit\n"); 4207 out: 4208 hw->phy.ops.release(hw); 4209 4210 return ret; 4211 } 4212 4213 static void 4214 em_if_led_func(if_ctx_t ctx, int onoff) 4215 { 4216 struct e1000_softc *sc = iflib_get_softc(ctx); 4217 4218 if (onoff) { 4219 e1000_setup_led(&sc->hw); 4220 e1000_led_on(&sc->hw); 4221 } else { 4222 e1000_led_off(&sc->hw); 4223 e1000_cleanup_led(&sc->hw); 4224 } 4225 } 4226 4227 /* 4228 * Disable the L0S and L1 LINK states 4229 */ 4230 static void 4231 em_disable_aspm(struct e1000_softc *sc) 4232 { 4233 int base, reg; 4234 u16 link_cap,link_ctrl; 4235 device_t dev = sc->dev; 4236 4237 switch (sc->hw.mac.type) { 4238 case e1000_82573: 4239 case e1000_82574: 4240 case e1000_82583: 4241 break; 4242 default: 4243 return; 4244 } 4245 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4246 return; 4247 reg = base + PCIER_LINK_CAP; 4248 link_cap = pci_read_config(dev, reg, 2); 4249 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4250 return; 4251 reg = base + PCIER_LINK_CTL; 4252 link_ctrl = pci_read_config(dev, reg, 2); 4253 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4254 pci_write_config(dev, reg, link_ctrl, 2); 4255 return; 4256 } 4257 4258 /********************************************************************** 4259 * 4260 * Update the board statistics counters. 4261 * 4262 **********************************************************************/ 4263 static void 4264 em_update_stats_counters(struct e1000_softc *sc) 4265 { 4266 u64 prev_xoffrxc = sc->stats.xoffrxc; 4267 4268 if(sc->hw.phy.media_type == e1000_media_type_copper || 4269 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4270 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4271 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4272 } 4273 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4274 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4275 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4276 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4277 4278 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4279 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4280 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4281 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4282 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4283 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4284 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4285 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4286 /* 4287 ** For watchdog management we need to know if we have been 4288 ** paused during the last interval, so capture that here. 4289 */ 4290 if (sc->stats.xoffrxc != prev_xoffrxc) 4291 sc->shared->isc_pause_frames = 1; 4292 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4293 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4294 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4295 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4296 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4297 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4298 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4299 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4300 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4301 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4302 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4303 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4304 4305 /* For the 64-bit byte counters the low dword must be read first. */ 4306 /* Both registers clear on the read of the high dword */ 4307 4308 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4309 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4310 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4311 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4312 4313 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4314 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4315 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4316 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4317 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4318 4319 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4320 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4321 4322 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4323 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4324 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4325 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4326 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4327 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4328 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4329 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4330 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4331 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4332 4333 /* Interrupt Counts */ 4334 4335 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4336 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4337 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4338 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4339 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4340 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4341 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4342 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4343 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4344 4345 if (sc->hw.mac.type >= e1000_82543) { 4346 sc->stats.algnerrc += 4347 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4348 sc->stats.rxerrc += 4349 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4350 sc->stats.tncrs += 4351 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4352 sc->stats.cexterr += 4353 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4354 sc->stats.tsctc += 4355 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4356 sc->stats.tsctfc += 4357 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4358 } 4359 } 4360 4361 static uint64_t 4362 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4363 { 4364 struct e1000_softc *sc = iflib_get_softc(ctx); 4365 if_t ifp = iflib_get_ifp(ctx); 4366 4367 switch (cnt) { 4368 case IFCOUNTER_COLLISIONS: 4369 return (sc->stats.colc); 4370 case IFCOUNTER_IERRORS: 4371 return (sc->dropped_pkts + sc->stats.rxerrc + 4372 sc->stats.crcerrs + sc->stats.algnerrc + 4373 sc->stats.ruc + sc->stats.roc + 4374 sc->stats.mpc + sc->stats.cexterr); 4375 case IFCOUNTER_OERRORS: 4376 return (sc->stats.ecol + sc->stats.latecol + 4377 sc->watchdog_events); 4378 default: 4379 return (if_get_counter_default(ifp, cnt)); 4380 } 4381 } 4382 4383 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4384 * @ctx: iflib context 4385 * @event: event code to check 4386 * 4387 * Defaults to returning true for unknown events. 4388 * 4389 * @returns true if iflib needs to reinit the interface 4390 */ 4391 static bool 4392 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4393 { 4394 switch (event) { 4395 case IFLIB_RESTART_VLAN_CONFIG: 4396 return (false); 4397 default: 4398 return (true); 4399 } 4400 } 4401 4402 /* Export a single 32-bit register via a read-only sysctl. */ 4403 static int 4404 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4405 { 4406 struct e1000_softc *sc; 4407 u_int val; 4408 4409 sc = oidp->oid_arg1; 4410 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4411 return (sysctl_handle_int(oidp, &val, 0, req)); 4412 } 4413 4414 /* 4415 * Add sysctl variables, one per statistic, to the system. 4416 */ 4417 static void 4418 em_add_hw_stats(struct e1000_softc *sc) 4419 { 4420 device_t dev = iflib_get_dev(sc->ctx); 4421 struct em_tx_queue *tx_que = sc->tx_queues; 4422 struct em_rx_queue *rx_que = sc->rx_queues; 4423 4424 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4425 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4426 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4427 struct e1000_hw_stats *stats = &sc->stats; 4428 4429 struct sysctl_oid *stat_node, *queue_node, *int_node; 4430 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4431 4432 #define QUEUE_NAME_LEN 32 4433 char namebuf[QUEUE_NAME_LEN]; 4434 4435 /* Driver Statistics */ 4436 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4437 CTLFLAG_RD, &sc->dropped_pkts, 4438 "Driver dropped packets"); 4439 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4440 CTLFLAG_RD, &sc->link_irq, 4441 "Link MSI-X IRQ Handled"); 4442 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4443 CTLFLAG_RD, &sc->rx_overruns, 4444 "RX overruns"); 4445 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4446 CTLFLAG_RD, &sc->watchdog_events, 4447 "Watchdog timeouts"); 4448 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4449 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4450 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4451 "Device Control Register"); 4452 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4453 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4454 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4455 "Receiver Control Register"); 4456 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4457 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4458 "Flow Control High Watermark"); 4459 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4460 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4461 "Flow Control Low Watermark"); 4462 4463 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4464 struct tx_ring *txr = &tx_que->txr; 4465 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4466 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4467 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4468 queue_list = SYSCTL_CHILDREN(queue_node); 4469 4470 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4471 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4472 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4473 "Transmit Descriptor Head"); 4474 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4475 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4476 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4477 "Transmit Descriptor Tail"); 4478 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4479 CTLFLAG_RD, &txr->tx_irq, 4480 "Queue MSI-X Transmit Interrupts"); 4481 } 4482 4483 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4484 struct rx_ring *rxr = &rx_que->rxr; 4485 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4486 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4487 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4488 queue_list = SYSCTL_CHILDREN(queue_node); 4489 4490 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4491 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4492 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4493 "Receive Descriptor Head"); 4494 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4495 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4496 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4497 "Receive Descriptor Tail"); 4498 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4499 CTLFLAG_RD, &rxr->rx_irq, 4500 "Queue MSI-X Receive Interrupts"); 4501 } 4502 4503 /* MAC stats get their own sub node */ 4504 4505 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4506 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4507 stat_list = SYSCTL_CHILDREN(stat_node); 4508 4509 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4510 CTLFLAG_RD, &stats->ecol, 4511 "Excessive collisions"); 4512 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4513 CTLFLAG_RD, &stats->scc, 4514 "Single collisions"); 4515 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4516 CTLFLAG_RD, &stats->mcc, 4517 "Multiple collisions"); 4518 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4519 CTLFLAG_RD, &stats->latecol, 4520 "Late collisions"); 4521 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4522 CTLFLAG_RD, &stats->colc, 4523 "Collision Count"); 4524 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4525 CTLFLAG_RD, &sc->stats.symerrs, 4526 "Symbol Errors"); 4527 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4528 CTLFLAG_RD, &sc->stats.sec, 4529 "Sequence Errors"); 4530 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4531 CTLFLAG_RD, &sc->stats.dc, 4532 "Defer Count"); 4533 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4534 CTLFLAG_RD, &sc->stats.mpc, 4535 "Missed Packets"); 4536 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4537 CTLFLAG_RD, &sc->stats.rnbc, 4538 "Receive No Buffers"); 4539 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4540 CTLFLAG_RD, &sc->stats.ruc, 4541 "Receive Undersize"); 4542 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4543 CTLFLAG_RD, &sc->stats.rfc, 4544 "Fragmented Packets Received "); 4545 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4546 CTLFLAG_RD, &sc->stats.roc, 4547 "Oversized Packets Received"); 4548 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4549 CTLFLAG_RD, &sc->stats.rjc, 4550 "Recevied Jabber"); 4551 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4552 CTLFLAG_RD, &sc->stats.rxerrc, 4553 "Receive Errors"); 4554 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4555 CTLFLAG_RD, &sc->stats.crcerrs, 4556 "CRC errors"); 4557 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4558 CTLFLAG_RD, &sc->stats.algnerrc, 4559 "Alignment Errors"); 4560 /* On 82575 these are collision counts */ 4561 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4562 CTLFLAG_RD, &sc->stats.cexterr, 4563 "Collision/Carrier extension errors"); 4564 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4565 CTLFLAG_RD, &sc->stats.xonrxc, 4566 "XON Received"); 4567 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4568 CTLFLAG_RD, &sc->stats.xontxc, 4569 "XON Transmitted"); 4570 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4571 CTLFLAG_RD, &sc->stats.xoffrxc, 4572 "XOFF Received"); 4573 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4574 CTLFLAG_RD, &sc->stats.xofftxc, 4575 "XOFF Transmitted"); 4576 4577 /* Packet Reception Stats */ 4578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4579 CTLFLAG_RD, &sc->stats.tpr, 4580 "Total Packets Received "); 4581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4582 CTLFLAG_RD, &sc->stats.gprc, 4583 "Good Packets Received"); 4584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4585 CTLFLAG_RD, &sc->stats.bprc, 4586 "Broadcast Packets Received"); 4587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4588 CTLFLAG_RD, &sc->stats.mprc, 4589 "Multicast Packets Received"); 4590 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4591 CTLFLAG_RD, &sc->stats.prc64, 4592 "64 byte frames received "); 4593 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4594 CTLFLAG_RD, &sc->stats.prc127, 4595 "65-127 byte frames received"); 4596 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4597 CTLFLAG_RD, &sc->stats.prc255, 4598 "128-255 byte frames received"); 4599 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4600 CTLFLAG_RD, &sc->stats.prc511, 4601 "256-511 byte frames received"); 4602 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4603 CTLFLAG_RD, &sc->stats.prc1023, 4604 "512-1023 byte frames received"); 4605 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4606 CTLFLAG_RD, &sc->stats.prc1522, 4607 "1023-1522 byte frames received"); 4608 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4609 CTLFLAG_RD, &sc->stats.gorc, 4610 "Good Octets Received"); 4611 4612 /* Packet Transmission Stats */ 4613 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4614 CTLFLAG_RD, &sc->stats.gotc, 4615 "Good Octets Transmitted"); 4616 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4617 CTLFLAG_RD, &sc->stats.tpt, 4618 "Total Packets Transmitted"); 4619 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4620 CTLFLAG_RD, &sc->stats.gptc, 4621 "Good Packets Transmitted"); 4622 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4623 CTLFLAG_RD, &sc->stats.bptc, 4624 "Broadcast Packets Transmitted"); 4625 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4626 CTLFLAG_RD, &sc->stats.mptc, 4627 "Multicast Packets Transmitted"); 4628 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4629 CTLFLAG_RD, &sc->stats.ptc64, 4630 "64 byte frames transmitted "); 4631 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4632 CTLFLAG_RD, &sc->stats.ptc127, 4633 "65-127 byte frames transmitted"); 4634 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4635 CTLFLAG_RD, &sc->stats.ptc255, 4636 "128-255 byte frames transmitted"); 4637 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4638 CTLFLAG_RD, &sc->stats.ptc511, 4639 "256-511 byte frames transmitted"); 4640 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4641 CTLFLAG_RD, &sc->stats.ptc1023, 4642 "512-1023 byte frames transmitted"); 4643 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4644 CTLFLAG_RD, &sc->stats.ptc1522, 4645 "1024-1522 byte frames transmitted"); 4646 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4647 CTLFLAG_RD, &sc->stats.tsctc, 4648 "TSO Contexts Transmitted"); 4649 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4650 CTLFLAG_RD, &sc->stats.tsctfc, 4651 "TSO Contexts Failed"); 4652 4653 4654 /* Interrupt Stats */ 4655 4656 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4657 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4658 int_list = SYSCTL_CHILDREN(int_node); 4659 4660 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4661 CTLFLAG_RD, &sc->stats.iac, 4662 "Interrupt Assertion Count"); 4663 4664 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4665 CTLFLAG_RD, &sc->stats.icrxptc, 4666 "Interrupt Cause Rx Pkt Timer Expire Count"); 4667 4668 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4669 CTLFLAG_RD, &sc->stats.icrxatc, 4670 "Interrupt Cause Rx Abs Timer Expire Count"); 4671 4672 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4673 CTLFLAG_RD, &sc->stats.ictxptc, 4674 "Interrupt Cause Tx Pkt Timer Expire Count"); 4675 4676 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4677 CTLFLAG_RD, &sc->stats.ictxatc, 4678 "Interrupt Cause Tx Abs Timer Expire Count"); 4679 4680 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4681 CTLFLAG_RD, &sc->stats.ictxqec, 4682 "Interrupt Cause Tx Queue Empty Count"); 4683 4684 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4685 CTLFLAG_RD, &sc->stats.ictxqmtc, 4686 "Interrupt Cause Tx Queue Min Thresh Count"); 4687 4688 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4689 CTLFLAG_RD, &sc->stats.icrxdmtc, 4690 "Interrupt Cause Rx Desc Min Thresh Count"); 4691 4692 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4693 CTLFLAG_RD, &sc->stats.icrxoc, 4694 "Interrupt Cause Receiver Overrun Count"); 4695 } 4696 4697 static void 4698 em_fw_version_locked(if_ctx_t ctx) 4699 { 4700 struct e1000_softc *sc = iflib_get_softc(ctx); 4701 struct e1000_hw *hw = &sc->hw; 4702 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4703 uint16_t eep = 0; 4704 4705 /* 4706 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4707 * NVM locking model, so we do it in em_if_attach_pre() and store the 4708 * info in the softc 4709 */ 4710 ASSERT_CTX_LOCK_HELD(hw); 4711 4712 *fw_ver = (struct e1000_fw_version){0}; 4713 4714 if (hw->mac.type >= igb_mac_min) { 4715 /* 4716 * Use the Shared Code for igb(4) 4717 */ 4718 e1000_get_fw_version(hw, fw_ver); 4719 } else { 4720 /* 4721 * Otherwise, EEPROM version should be present on (almost?) all 4722 * devices here 4723 */ 4724 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4725 INIT_DEBUGOUT("can't get EEPROM version"); 4726 return; 4727 } 4728 4729 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4730 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4731 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4732 } 4733 } 4734 4735 static void 4736 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4737 { 4738 const char *space = ""; 4739 4740 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4741 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4742 fw_ver->eep_minor, fw_ver->eep_build); 4743 space = " "; 4744 } 4745 4746 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4747 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4748 space, fw_ver->invm_major, fw_ver->invm_minor, 4749 fw_ver->invm_img_type); 4750 space = " "; 4751 } 4752 4753 if (fw_ver->or_valid) { 4754 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4755 space, fw_ver->or_major, fw_ver->or_build, 4756 fw_ver->or_patch); 4757 space = " "; 4758 } 4759 4760 if (fw_ver->etrack_id) 4761 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4762 } 4763 4764 static void 4765 em_print_fw_version(struct e1000_softc *sc ) 4766 { 4767 device_t dev = sc->dev; 4768 struct sbuf *buf; 4769 int error = 0; 4770 4771 buf = sbuf_new_auto(); 4772 if (!buf) { 4773 device_printf(dev, "Could not allocate sbuf for output.\n"); 4774 return; 4775 } 4776 4777 em_sbuf_fw_version(&sc->fw_ver, buf); 4778 4779 error = sbuf_finish(buf); 4780 if (error) 4781 device_printf(dev, "Error finishing sbuf: %d\n", error); 4782 else if (sbuf_len(buf)) 4783 device_printf(dev, "%s\n", sbuf_data(buf)); 4784 4785 sbuf_delete(buf); 4786 } 4787 4788 static int 4789 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4790 { 4791 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4792 device_t dev = sc->dev; 4793 struct sbuf *buf; 4794 int error = 0; 4795 4796 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4797 if (!buf) { 4798 device_printf(dev, "Could not allocate sbuf for output.\n"); 4799 return (ENOMEM); 4800 } 4801 4802 em_sbuf_fw_version(&sc->fw_ver, buf); 4803 4804 error = sbuf_finish(buf); 4805 if (error) 4806 device_printf(dev, "Error finishing sbuf: %d\n", error); 4807 4808 sbuf_delete(buf); 4809 4810 return (0); 4811 } 4812 4813 /********************************************************************** 4814 * 4815 * This routine provides a way to dump out the adapter eeprom, 4816 * often a useful debug/service tool. This only dumps the first 4817 * 32 words, stuff that matters is in that extent. 4818 * 4819 **********************************************************************/ 4820 static int 4821 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4822 { 4823 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4824 int error; 4825 int result; 4826 4827 result = -1; 4828 error = sysctl_handle_int(oidp, &result, 0, req); 4829 4830 if (error || !req->newptr) 4831 return (error); 4832 4833 /* 4834 * This value will cause a hex dump of the 4835 * first 32 16-bit words of the EEPROM to 4836 * the screen. 4837 */ 4838 if (result == 1) 4839 em_print_nvm_info(sc); 4840 4841 return (error); 4842 } 4843 4844 static void 4845 em_print_nvm_info(struct e1000_softc *sc) 4846 { 4847 struct e1000_hw *hw = &sc->hw; 4848 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4849 u16 eeprom_data; 4850 int i, j, row = 0; 4851 4852 /* Its a bit crude, but it gets the job done */ 4853 printf("\nInterface EEPROM Dump:\n"); 4854 printf("Offset\n0x0000 "); 4855 4856 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4857 sx_xlock(iflib_ctx_lock); 4858 ASSERT_CTX_LOCK_HELD(hw); 4859 for (i = 0, j = 0; i < 32; i++, j++) { 4860 if (j == 8) { /* Make the offset block */ 4861 j = 0; ++row; 4862 printf("\n0x00%x0 ",row); 4863 } 4864 e1000_read_nvm(hw, i, 1, &eeprom_data); 4865 printf("%04x ", eeprom_data); 4866 } 4867 sx_xunlock(iflib_ctx_lock); 4868 printf("\n"); 4869 } 4870 4871 static int 4872 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4873 { 4874 struct em_int_delay_info *info; 4875 struct e1000_softc *sc; 4876 u32 regval; 4877 int error, usecs, ticks; 4878 4879 info = (struct em_int_delay_info *) arg1; 4880 usecs = info->value; 4881 error = sysctl_handle_int(oidp, &usecs, 0, req); 4882 if (error != 0 || req->newptr == NULL) 4883 return (error); 4884 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4885 return (EINVAL); 4886 info->value = usecs; 4887 ticks = EM_USECS_TO_TICKS(usecs); 4888 if (info->offset == E1000_ITR) /* units are 256ns here */ 4889 ticks *= 4; 4890 4891 sc = info->sc; 4892 4893 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4894 regval = (regval & ~0xffff) | (ticks & 0xffff); 4895 /* Handle a few special cases. */ 4896 switch (info->offset) { 4897 case E1000_RDTR: 4898 break; 4899 case E1000_TIDV: 4900 if (ticks == 0) { 4901 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4902 /* Don't write 0 into the TIDV register. */ 4903 regval++; 4904 } else 4905 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4906 break; 4907 } 4908 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4909 return (0); 4910 } 4911 4912 static void 4913 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4914 const char *description, struct em_int_delay_info *info, 4915 int offset, int value) 4916 { 4917 info->sc = sc; 4918 info->offset = offset; 4919 info->value = value; 4920 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4921 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4922 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4923 info, 0, em_sysctl_int_delay, "I", description); 4924 } 4925 4926 /* 4927 * Set flow control using sysctl: 4928 * Flow control values: 4929 * 0 - off 4930 * 1 - rx pause 4931 * 2 - tx pause 4932 * 3 - full 4933 */ 4934 static int 4935 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4936 { 4937 int error; 4938 static int input = 3; /* default is full */ 4939 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4940 4941 error = sysctl_handle_int(oidp, &input, 0, req); 4942 4943 if ((error) || (req->newptr == NULL)) 4944 return (error); 4945 4946 if (input == sc->fc) /* no change? */ 4947 return (error); 4948 4949 switch (input) { 4950 case e1000_fc_rx_pause: 4951 case e1000_fc_tx_pause: 4952 case e1000_fc_full: 4953 case e1000_fc_none: 4954 sc->hw.fc.requested_mode = input; 4955 sc->fc = input; 4956 break; 4957 default: 4958 /* Do nothing */ 4959 return (error); 4960 } 4961 4962 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4963 e1000_force_mac_fc(&sc->hw); 4964 return (error); 4965 } 4966 4967 /* 4968 * Manage Energy Efficient Ethernet: 4969 * Control values: 4970 * 0/1 - enabled/disabled 4971 */ 4972 static int 4973 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4974 { 4975 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4976 int error, value; 4977 4978 value = sc->hw.dev_spec.ich8lan.eee_disable; 4979 error = sysctl_handle_int(oidp, &value, 0, req); 4980 if (error || req->newptr == NULL) 4981 return (error); 4982 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4983 em_if_init(sc->ctx); 4984 4985 return (0); 4986 } 4987 4988 static int 4989 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4990 { 4991 struct e1000_softc *sc; 4992 int error; 4993 int result; 4994 4995 result = -1; 4996 error = sysctl_handle_int(oidp, &result, 0, req); 4997 4998 if (error || !req->newptr) 4999 return (error); 5000 5001 if (result == 1) { 5002 sc = (struct e1000_softc *) arg1; 5003 em_print_debug_info(sc); 5004 } 5005 5006 return (error); 5007 } 5008 5009 static int 5010 em_get_rs(SYSCTL_HANDLER_ARGS) 5011 { 5012 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5013 int error; 5014 int result; 5015 5016 result = 0; 5017 error = sysctl_handle_int(oidp, &result, 0, req); 5018 5019 if (error || !req->newptr || result != 1) 5020 return (error); 5021 em_dump_rs(sc); 5022 5023 return (error); 5024 } 5025 5026 static void 5027 em_if_debug(if_ctx_t ctx) 5028 { 5029 em_dump_rs(iflib_get_softc(ctx)); 5030 } 5031 5032 /* 5033 * This routine is meant to be fluid, add whatever is 5034 * needed for debugging a problem. -jfv 5035 */ 5036 static void 5037 em_print_debug_info(struct e1000_softc *sc) 5038 { 5039 device_t dev = iflib_get_dev(sc->ctx); 5040 if_t ifp = iflib_get_ifp(sc->ctx); 5041 struct tx_ring *txr = &sc->tx_queues->txr; 5042 struct rx_ring *rxr = &sc->rx_queues->rxr; 5043 5044 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5045 printf("Interface is RUNNING "); 5046 else 5047 printf("Interface is NOT RUNNING\n"); 5048 5049 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5050 printf("and INACTIVE\n"); 5051 else 5052 printf("and ACTIVE\n"); 5053 5054 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5055 device_printf(dev, "TX Queue %d ------\n", i); 5056 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5057 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5058 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5059 5060 } 5061 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5062 device_printf(dev, "RX Queue %d ------\n", j); 5063 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5064 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5065 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5066 } 5067 } 5068 5069 /* 5070 * 82574 only: 5071 * Write a new value to the EEPROM increasing the number of MSI-X 5072 * vectors from 3 to 5, for proper multiqueue support. 5073 */ 5074 static void 5075 em_enable_vectors_82574(if_ctx_t ctx) 5076 { 5077 struct e1000_softc *sc = iflib_get_softc(ctx); 5078 struct e1000_hw *hw = &sc->hw; 5079 device_t dev = iflib_get_dev(ctx); 5080 u16 edata; 5081 5082 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5083 if (bootverbose) 5084 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5085 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5086 device_printf(dev, "Writing to eeprom: increasing " 5087 "reported MSI-X vectors from 3 to 5...\n"); 5088 edata &= ~(EM_NVM_MSIX_N_MASK); 5089 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5090 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5091 e1000_update_nvm_checksum(hw); 5092 device_printf(dev, "Writing to eeprom: done\n"); 5093 } 5094 } 5095