1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_vf_counter(if_ctx_t, ift_counter); 411 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 412 static void em_if_init(if_ctx_t); 413 static void em_if_stop(if_ctx_t); 414 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 415 static int em_if_media_change(if_ctx_t); 416 static int em_if_mtu_set(if_ctx_t, uint32_t); 417 static void em_if_timer(if_ctx_t, uint16_t); 418 static void em_if_vlan_register(if_ctx_t, u16); 419 static void em_if_vlan_unregister(if_ctx_t, u16); 420 static void em_if_watchdog_reset(if_ctx_t); 421 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 422 423 static void em_identify_hardware(if_ctx_t); 424 static int em_allocate_pci_resources(if_ctx_t); 425 static void em_free_pci_resources(if_ctx_t); 426 static void em_reset(if_ctx_t); 427 static int em_setup_interface(if_ctx_t); 428 static int em_setup_msix(if_ctx_t); 429 430 static void em_initialize_transmit_unit(if_ctx_t); 431 static void em_initialize_receive_unit(if_ctx_t); 432 433 static void em_if_intr_enable(if_ctx_t); 434 static void em_if_intr_disable(if_ctx_t); 435 static void igb_if_intr_enable(if_ctx_t); 436 static void igb_if_intr_disable(if_ctx_t); 437 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 440 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 441 static void em_if_multi_set(if_ctx_t); 442 static void em_if_update_admin_status(if_ctx_t); 443 static void em_if_debug(if_ctx_t); 444 static void em_update_vf_stats_counters(struct e1000_softc *); 445 static void em_update_stats_counters(struct e1000_softc *); 446 static void em_add_hw_stats(struct e1000_softc *); 447 static int em_if_set_promisc(if_ctx_t, int); 448 static bool em_if_vlan_filter_capable(if_ctx_t); 449 static bool em_if_vlan_filter_used(if_ctx_t); 450 static void em_if_vlan_filter_enable(struct e1000_softc *); 451 static void em_if_vlan_filter_disable(struct e1000_softc *); 452 static void em_if_vlan_filter_write(struct e1000_softc *); 453 static void em_setup_vlan_hw_support(if_ctx_t ctx); 454 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 455 static void em_print_nvm_info(struct e1000_softc *); 456 static void em_fw_version_locked(if_ctx_t); 457 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 458 static void em_print_fw_version(struct e1000_softc *); 459 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 460 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 461 static int em_get_rs(SYSCTL_HANDLER_ARGS); 462 static void em_print_debug_info(struct e1000_softc *); 463 static int em_is_valid_ether_addr(u8 *); 464 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 465 struct rx_ring *); 466 static bool em_automask_tso(if_ctx_t); 467 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 468 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 469 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 470 const char *, struct em_int_delay_info *, int, int); 471 /* Management and WOL Support */ 472 static void em_init_manageability(struct e1000_softc *); 473 static void em_release_manageability(struct e1000_softc *); 474 static void em_get_hw_control(struct e1000_softc *); 475 static void em_release_hw_control(struct e1000_softc *); 476 static void em_get_wakeup(if_ctx_t); 477 static void em_enable_wakeup(if_ctx_t); 478 static int em_enable_phy_wakeup(struct e1000_softc *); 479 static void em_disable_aspm(struct e1000_softc *); 480 481 int em_intr(void *); 482 483 /* MSI-X handlers */ 484 static int em_if_msix_intr_assign(if_ctx_t, int); 485 static int em_msix_link(void *); 486 static void em_handle_link(void *); 487 488 static void em_enable_vectors_82574(if_ctx_t); 489 490 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 491 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 492 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 493 static void em_if_led_func(if_ctx_t, int); 494 495 static int em_get_regs(SYSCTL_HANDLER_ARGS); 496 497 static void lem_smartspeed(struct e1000_softc *); 498 static void igb_configure_queues(struct e1000_softc *); 499 static void igb_initialize_interrupt_rate(struct e1000_softc *); 500 static void em_flush_desc_rings(struct e1000_softc *); 501 502 503 /********************************************************************* 504 * FreeBSD Device Interface Entry Points 505 *********************************************************************/ 506 static device_method_t em_methods[] = { 507 /* Device interface */ 508 DEVMETHOD(device_register, em_register), 509 DEVMETHOD(device_probe, iflib_device_probe), 510 DEVMETHOD(device_attach, iflib_device_attach), 511 DEVMETHOD(device_detach, iflib_device_detach), 512 DEVMETHOD(device_shutdown, iflib_device_shutdown), 513 DEVMETHOD(device_suspend, iflib_device_suspend), 514 DEVMETHOD(device_resume, iflib_device_resume), 515 DEVMETHOD_END 516 }; 517 518 static device_method_t igb_methods[] = { 519 /* Device interface */ 520 DEVMETHOD(device_register, igb_register), 521 DEVMETHOD(device_probe, iflib_device_probe), 522 DEVMETHOD(device_attach, iflib_device_attach), 523 DEVMETHOD(device_detach, iflib_device_detach), 524 DEVMETHOD(device_shutdown, iflib_device_shutdown), 525 DEVMETHOD(device_suspend, iflib_device_suspend), 526 DEVMETHOD(device_resume, iflib_device_resume), 527 DEVMETHOD_END 528 }; 529 530 531 static driver_t em_driver = { 532 "em", em_methods, sizeof(struct e1000_softc), 533 }; 534 535 DRIVER_MODULE(em, pci, em_driver, 0, 0); 536 537 MODULE_DEPEND(em, pci, 1, 1, 1); 538 MODULE_DEPEND(em, ether, 1, 1, 1); 539 MODULE_DEPEND(em, iflib, 1, 1, 1); 540 541 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 542 543 static driver_t igb_driver = { 544 "igb", igb_methods, sizeof(struct e1000_softc), 545 }; 546 547 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 548 549 MODULE_DEPEND(igb, pci, 1, 1, 1); 550 MODULE_DEPEND(igb, ether, 1, 1, 1); 551 MODULE_DEPEND(igb, iflib, 1, 1, 1); 552 553 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 554 555 static device_method_t em_if_methods[] = { 556 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 557 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 558 DEVMETHOD(ifdi_detach, em_if_detach), 559 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 560 DEVMETHOD(ifdi_suspend, em_if_suspend), 561 DEVMETHOD(ifdi_resume, em_if_resume), 562 DEVMETHOD(ifdi_init, em_if_init), 563 DEVMETHOD(ifdi_stop, em_if_stop), 564 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 565 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 566 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 567 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 568 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 569 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 570 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 571 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 572 DEVMETHOD(ifdi_media_status, em_if_media_status), 573 DEVMETHOD(ifdi_media_change, em_if_media_change), 574 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 575 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 576 DEVMETHOD(ifdi_timer, em_if_timer), 577 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 578 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 579 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 580 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 581 DEVMETHOD(ifdi_led_func, em_if_led_func), 582 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 583 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 584 DEVMETHOD(ifdi_debug, em_if_debug), 585 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 586 DEVMETHOD_END 587 }; 588 589 static driver_t em_if_driver = { 590 "em_if", em_if_methods, sizeof(struct e1000_softc) 591 }; 592 593 static device_method_t igb_if_methods[] = { 594 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 595 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 596 DEVMETHOD(ifdi_detach, em_if_detach), 597 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 598 DEVMETHOD(ifdi_suspend, em_if_suspend), 599 DEVMETHOD(ifdi_resume, em_if_resume), 600 DEVMETHOD(ifdi_init, em_if_init), 601 DEVMETHOD(ifdi_stop, em_if_stop), 602 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 603 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 604 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 605 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 606 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 607 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 608 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 609 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 610 DEVMETHOD(ifdi_media_status, em_if_media_status), 611 DEVMETHOD(ifdi_media_change, em_if_media_change), 612 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 613 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 614 DEVMETHOD(ifdi_timer, em_if_timer), 615 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 616 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 617 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 618 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 619 DEVMETHOD(ifdi_led_func, em_if_led_func), 620 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 621 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 622 DEVMETHOD(ifdi_debug, em_if_debug), 623 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 624 DEVMETHOD_END 625 }; 626 627 static driver_t igb_if_driver = { 628 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 629 }; 630 631 /********************************************************************* 632 * Tunable default values. 633 *********************************************************************/ 634 635 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 636 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 637 638 /* Allow common code without TSO */ 639 #ifndef CSUM_TSO 640 #define CSUM_TSO 0 641 #endif 642 643 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 644 "EM driver parameters"); 645 646 static int em_disable_crc_stripping = 0; 647 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 648 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 649 650 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 651 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 652 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 653 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 654 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 655 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 656 657 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 658 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 659 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 660 &em_tx_abs_int_delay_dflt, 0, 661 "Default transmit interrupt delay limit in usecs"); 662 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 663 &em_rx_abs_int_delay_dflt, 0, 664 "Default receive interrupt delay limit in usecs"); 665 666 static int em_smart_pwr_down = false; 667 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 668 &em_smart_pwr_down, 669 0, "Set to true to leave smart power down enabled on newer adapters"); 670 671 static bool em_unsupported_tso = false; 672 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 673 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 674 675 /* Controls whether promiscuous also shows bad packets */ 676 static int em_debug_sbp = false; 677 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 678 "Show bad packets in promiscuous mode"); 679 680 /* Energy efficient ethernet - default to OFF */ 681 static int eee_setting = 1; 682 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 683 "Enable Energy Efficient Ethernet"); 684 685 /* 686 * AIM: Adaptive Interrupt Moderation 687 * which means that the interrupt rate is varied over time based on the 688 * traffic for that interrupt vector 689 */ 690 static int em_enable_aim = 1; 691 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 692 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 693 694 /* 695 ** Tuneable Interrupt rate 696 */ 697 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 698 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 699 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 700 701 /* Global used in WOL setup with multiport cards */ 702 static int global_quad_port_a = 0; 703 704 extern struct if_txrx igb_txrx; 705 extern struct if_txrx em_txrx; 706 extern struct if_txrx lem_txrx; 707 708 static struct if_shared_ctx em_sctx_init = { 709 .isc_magic = IFLIB_MAGIC, 710 .isc_q_align = PAGE_SIZE, 711 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 712 .isc_tx_maxsegsize = PAGE_SIZE, 713 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 714 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 715 .isc_rx_maxsize = MJUM9BYTES, 716 .isc_rx_nsegments = 1, 717 .isc_rx_maxsegsize = MJUM9BYTES, 718 .isc_nfl = 1, 719 .isc_nrxqs = 1, 720 .isc_ntxqs = 1, 721 .isc_admin_intrcnt = 1, 722 .isc_vendor_info = em_vendor_info_array, 723 .isc_driver_version = em_driver_version, 724 .isc_driver = &em_if_driver, 725 .isc_flags = 726 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 727 728 .isc_nrxd_min = {EM_MIN_RXD}, 729 .isc_ntxd_min = {EM_MIN_TXD}, 730 .isc_nrxd_max = {EM_MAX_RXD}, 731 .isc_ntxd_max = {EM_MAX_TXD}, 732 .isc_nrxd_default = {EM_DEFAULT_RXD}, 733 .isc_ntxd_default = {EM_DEFAULT_TXD}, 734 }; 735 736 static struct if_shared_ctx igb_sctx_init = { 737 .isc_magic = IFLIB_MAGIC, 738 .isc_q_align = PAGE_SIZE, 739 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 740 .isc_tx_maxsegsize = PAGE_SIZE, 741 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 742 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 743 .isc_rx_maxsize = MJUM9BYTES, 744 .isc_rx_nsegments = 1, 745 .isc_rx_maxsegsize = MJUM9BYTES, 746 .isc_nfl = 1, 747 .isc_nrxqs = 1, 748 .isc_ntxqs = 1, 749 .isc_admin_intrcnt = 1, 750 .isc_vendor_info = igb_vendor_info_array, 751 .isc_driver_version = igb_driver_version, 752 .isc_driver = &igb_if_driver, 753 .isc_flags = 754 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 755 756 .isc_nrxd_min = {EM_MIN_RXD}, 757 .isc_ntxd_min = {EM_MIN_TXD}, 758 .isc_nrxd_max = {IGB_MAX_RXD}, 759 .isc_ntxd_max = {IGB_MAX_TXD}, 760 .isc_nrxd_default = {EM_DEFAULT_RXD}, 761 .isc_ntxd_default = {EM_DEFAULT_TXD}, 762 }; 763 764 /***************************************************************** 765 * 766 * Dump Registers 767 * 768 ****************************************************************/ 769 #define IGB_REGS_LEN 739 770 771 static int em_get_regs(SYSCTL_HANDLER_ARGS) 772 { 773 struct e1000_softc *sc = (struct e1000_softc *)arg1; 774 struct e1000_hw *hw = &sc->hw; 775 struct sbuf *sb; 776 u32 *regs_buff; 777 int rc; 778 779 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 780 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 781 782 rc = sysctl_wire_old_buffer(req, 0); 783 MPASS(rc == 0); 784 if (rc != 0) { 785 free(regs_buff, M_DEVBUF); 786 return (rc); 787 } 788 789 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 790 MPASS(sb != NULL); 791 if (sb == NULL) { 792 free(regs_buff, M_DEVBUF); 793 return (ENOMEM); 794 } 795 796 /* General Registers */ 797 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 798 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 799 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 800 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 801 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 802 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 803 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 804 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 805 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 806 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 807 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 808 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 809 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 810 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 811 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 812 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 813 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 814 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 815 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 816 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 817 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 818 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 819 820 sbuf_printf(sb, "General Registers\n"); 821 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 822 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 823 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 824 825 sbuf_printf(sb, "Interrupt Registers\n"); 826 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 827 828 sbuf_printf(sb, "RX Registers\n"); 829 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 830 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 831 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 832 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 833 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 834 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 835 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 836 837 sbuf_printf(sb, "TX Registers\n"); 838 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 839 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 840 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 841 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 842 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 843 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 844 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 845 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 846 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 847 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 848 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 849 850 free(regs_buff, M_DEVBUF); 851 852 #ifdef DUMP_DESCS 853 { 854 if_softc_ctx_t scctx = sc->shared; 855 struct rx_ring *rxr = &rx_que->rxr; 856 struct tx_ring *txr = &tx_que->txr; 857 int ntxd = scctx->isc_ntxd[0]; 858 int nrxd = scctx->isc_nrxd[0]; 859 int j; 860 861 for (j = 0; j < nrxd; j++) { 862 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 863 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 864 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 865 PRIx64 " Error:%d Length:%d\n", 866 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 867 } 868 869 for (j = 0; j < min(ntxd, 256); j++) { 870 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 871 872 sbuf_printf(sb, 873 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 874 " eop: %d DD=%d\n", 875 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 876 buf->eop != -1 ? 877 txr->tx_base[buf->eop].upper.fields.status & 878 E1000_TXD_STAT_DD : 0); 879 880 } 881 } 882 #endif 883 884 rc = sbuf_finish(sb); 885 sbuf_delete(sb); 886 return(rc); 887 } 888 889 static void * 890 em_register(device_t dev) 891 { 892 return (&em_sctx_init); 893 } 894 895 static void * 896 igb_register(device_t dev) 897 { 898 return (&igb_sctx_init); 899 } 900 901 static int 902 em_set_num_queues(if_ctx_t ctx) 903 { 904 struct e1000_softc *sc = iflib_get_softc(ctx); 905 int maxqueues; 906 907 /* Sanity check based on HW */ 908 switch (sc->hw.mac.type) { 909 case e1000_82576: 910 case e1000_82580: 911 case e1000_i350: 912 case e1000_i354: 913 maxqueues = 8; 914 break; 915 case e1000_i210: 916 case e1000_82575: 917 maxqueues = 4; 918 break; 919 case e1000_i211: 920 case e1000_82574: 921 maxqueues = 2; 922 break; 923 default: 924 maxqueues = 1; 925 break; 926 } 927 928 return (maxqueues); 929 } 930 931 #define LEM_CAPS \ 932 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 933 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 934 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 935 936 #define EM_CAPS \ 937 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 938 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 939 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 940 IFCAP_TSO6 941 942 #define IGB_CAPS \ 943 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 944 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 945 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 946 IFCAP_TSO6 947 948 /********************************************************************* 949 * Device initialization routine 950 * 951 * The attach entry point is called when the driver is being loaded. 952 * This routine identifies the type of hardware, allocates all resources 953 * and initializes the hardware. 954 * 955 * return 0 on success, positive on failure 956 *********************************************************************/ 957 static int 958 em_if_attach_pre(if_ctx_t ctx) 959 { 960 struct e1000_softc *sc; 961 if_softc_ctx_t scctx; 962 device_t dev; 963 struct e1000_hw *hw; 964 struct sysctl_oid_list *child; 965 struct sysctl_ctx_list *ctx_list; 966 int error = 0; 967 968 INIT_DEBUGOUT("em_if_attach_pre: begin"); 969 dev = iflib_get_dev(ctx); 970 sc = iflib_get_softc(ctx); 971 972 if (em_max_interrupt_rate <= 0) { 973 device_printf(dev, 974 "Invalid max_interrupt_rate %d; using default %d\n", 975 em_max_interrupt_rate, EM_INTS_DEFAULT); 976 em_max_interrupt_rate = EM_INTS_DEFAULT; 977 } 978 979 sc->ctx = sc->osdep.ctx = ctx; 980 sc->dev = sc->osdep.dev = dev; 981 scctx = sc->shared = iflib_get_softc_ctx(ctx); 982 sc->media = iflib_get_media(ctx); 983 hw = &sc->hw; 984 985 /* Determine hardware and mac info */ 986 em_identify_hardware(ctx); 987 988 /* SYSCTL stuff */ 989 ctx_list = device_get_sysctl_ctx(dev); 990 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 991 992 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 993 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 994 em_sysctl_nvm_info, "I", "NVM Information"); 995 996 sc->enable_aim = em_enable_aim; 997 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 998 CTLFLAG_RW, &sc->enable_aim, 0, 999 "Interrupt Moderation (1=normal, 2=lowlatency)"); 1000 1001 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 1002 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 1003 em_sysctl_print_fw_version, "A", 1004 "Prints FW/NVM Versions"); 1005 1006 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 1007 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1008 em_sysctl_debug_info, "I", "Debug Information"); 1009 1010 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1011 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1012 em_set_flowcntl, "I", "Flow Control"); 1013 1014 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1015 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1016 em_get_regs, "A", "Dump Registers"); 1017 1018 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1019 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1020 em_get_rs, "I", "Dump RS indexes"); 1021 1022 if (hw->mac.type >= e1000_i350) { 1023 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1024 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1025 igb_sysctl_dmac, "I", "DMA Coalesce"); 1026 } 1027 1028 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1029 "tso_tcp_flags_mask_first_segment", 1030 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1031 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1032 "TSO TCP flags mask for first segment"); 1033 1034 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1035 "tso_tcp_flags_mask_middle_segment", 1036 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1037 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1038 "TSO TCP flags mask for middle segment"); 1039 1040 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1041 "tso_tcp_flags_mask_last_segment", 1042 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1043 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1044 "TSO TCP flags mask for last segment"); 1045 1046 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1047 scctx->isc_nrxqsets_max = 1048 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1049 if (bootverbose) 1050 device_printf(dev, "attach_pre capping queues at %d\n", 1051 scctx->isc_ntxqsets_max); 1052 1053 if (hw->mac.type >= igb_mac_min) { 1054 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1055 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1056 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1057 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1058 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1059 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1060 scctx->isc_txrx = &igb_txrx; 1061 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1062 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1063 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1064 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1065 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1066 CSUM_IP6_TCP | CSUM_IP6_UDP; 1067 if (hw->mac.type != e1000_82575) 1068 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1069 /* 1070 ** Some new devices, as with ixgbe, now may 1071 ** use a different BAR, so we need to keep 1072 ** track of which is used. 1073 */ 1074 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1075 } else if (hw->mac.type >= em_mac_min) { 1076 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1077 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1078 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1079 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1080 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1081 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1082 scctx->isc_txrx = &em_txrx; 1083 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1084 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1085 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1086 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1087 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1088 CSUM_IP6_TCP | CSUM_IP6_UDP; 1089 1090 /* Disable TSO on all em(4) until ring stalls are debugged */ 1091 scctx->isc_capenable &= ~IFCAP_TSO; 1092 1093 /* 1094 * Disable TSO on SPT due to errata that downclocks DMA 1095 * performance 1096 * i218-i219 Specification Update 1.5.4.5 1097 */ 1098 if (hw->mac.type == e1000_pch_spt) 1099 scctx->isc_capenable &= ~IFCAP_TSO; 1100 1101 /* 1102 * We support MSI-X with 82574 only, but indicate to iflib(4) 1103 * that it shall give MSI at least a try with other devices. 1104 */ 1105 if (hw->mac.type == e1000_82574) { 1106 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1107 } else { 1108 scctx->isc_msix_bar = -1; 1109 scctx->isc_disable_msix = 1; 1110 } 1111 } else { 1112 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1113 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1114 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1115 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1116 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1117 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1118 scctx->isc_txrx = &lem_txrx; 1119 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1120 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1121 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1122 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1123 if (em_unsupported_tso) 1124 scctx->isc_capabilities |= IFCAP_TSO6; 1125 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1126 CSUM_IP6_TCP | CSUM_IP6_UDP; 1127 1128 /* Disable TSO on all lem(4) until ring stalls debugged */ 1129 scctx->isc_capenable &= ~IFCAP_TSO; 1130 1131 /* 82541ER doesn't do HW tagging */ 1132 if (hw->device_id == E1000_DEV_ID_82541ER || 1133 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1134 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1135 scctx->isc_capenable = scctx->isc_capabilities; 1136 } 1137 /* This is the first e1000 chip and it does not do offloads */ 1138 if (hw->mac.type == e1000_82542) { 1139 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1140 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1141 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1142 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1143 scctx->isc_capenable = scctx->isc_capabilities; 1144 } 1145 /* These can't do TSO for various reasons */ 1146 if (hw->mac.type < e1000_82544 || 1147 hw->mac.type == e1000_82547 || 1148 hw->mac.type == e1000_82547_rev_2) { 1149 scctx->isc_capabilities &= 1150 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1151 scctx->isc_capenable = scctx->isc_capabilities; 1152 } 1153 /* XXXKB: No IPv6 before this? */ 1154 if (hw->mac.type < e1000_82545){ 1155 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1156 scctx->isc_capenable = scctx->isc_capabilities; 1157 } 1158 /* 1159 * "PCI/PCI-X SDM 4.0" page 33 (b): 1160 * FDX requirement on these chips 1161 */ 1162 if (hw->mac.type == e1000_82547 || 1163 hw->mac.type == e1000_82547_rev_2) 1164 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1165 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1166 1167 /* INTx only */ 1168 scctx->isc_msix_bar = 0; 1169 } 1170 1171 /* Setup PCI resources */ 1172 if (em_allocate_pci_resources(ctx)) { 1173 device_printf(dev, "Allocation of PCI resources failed\n"); 1174 error = ENXIO; 1175 goto err_pci; 1176 } 1177 1178 /* 1179 ** For ICH8 and family we need to 1180 ** map the flash memory, and this 1181 ** must happen after the MAC is 1182 ** identified 1183 */ 1184 if ((hw->mac.type == e1000_ich8lan) || 1185 (hw->mac.type == e1000_ich9lan) || 1186 (hw->mac.type == e1000_ich10lan) || 1187 (hw->mac.type == e1000_pchlan) || 1188 (hw->mac.type == e1000_pch2lan) || 1189 (hw->mac.type == e1000_pch_lpt)) { 1190 int rid = EM_BAR_TYPE_FLASH; 1191 sc->flash = bus_alloc_resource_any(dev, 1192 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1193 if (sc->flash == NULL) { 1194 device_printf(dev, "Mapping of Flash failed\n"); 1195 error = ENXIO; 1196 goto err_pci; 1197 } 1198 /* This is used in the shared code */ 1199 hw->flash_address = (u8 *)sc->flash; 1200 sc->osdep.flash_bus_space_tag = 1201 rman_get_bustag(sc->flash); 1202 sc->osdep.flash_bus_space_handle = 1203 rman_get_bushandle(sc->flash); 1204 } 1205 /* 1206 ** In the new SPT device flash is not a 1207 ** separate BAR, rather it is also in BAR0, 1208 ** so use the same tag and an offset handle for the 1209 ** FLASH read/write macros in the shared code. 1210 */ 1211 else if (hw->mac.type >= e1000_pch_spt) { 1212 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1213 sc->osdep.flash_bus_space_handle = 1214 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1215 } 1216 1217 /* Do Shared Code initialization */ 1218 error = e1000_setup_init_funcs(hw, true); 1219 if (error) { 1220 device_printf(dev, "Setup of Shared code failed, error %d\n", 1221 error); 1222 error = ENXIO; 1223 goto err_pci; 1224 } 1225 1226 em_setup_msix(ctx); 1227 e1000_get_bus_info(hw); 1228 1229 /* Set up some sysctls for the tunable interrupt delays */ 1230 if (hw->mac.type < igb_mac_min) { 1231 em_add_int_delay_sysctl(sc, "rx_int_delay", 1232 "receive interrupt delay in usecs", &sc->rx_int_delay, 1233 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1234 em_add_int_delay_sysctl(sc, "tx_int_delay", 1235 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1236 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1237 } 1238 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1239 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1240 "receive interrupt delay limit in usecs", 1241 &sc->rx_abs_int_delay, 1242 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1243 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1244 "transmit interrupt delay limit in usecs", 1245 &sc->tx_abs_int_delay, 1246 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1247 } 1248 1249 hw->mac.autoneg = DO_AUTO_NEG; 1250 hw->phy.autoneg_wait_to_complete = false; 1251 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1252 1253 if (hw->mac.type < em_mac_min) { 1254 e1000_init_script_state_82541(hw, true); 1255 e1000_set_tbi_compatibility_82543(hw, true); 1256 } 1257 /* Copper options */ 1258 if (hw->phy.media_type == e1000_media_type_copper) { 1259 hw->phy.mdix = AUTO_ALL_MODES; 1260 hw->phy.disable_polarity_correction = false; 1261 hw->phy.ms_type = EM_MASTER_SLAVE; 1262 } 1263 1264 /* 1265 * Set the frame limits assuming 1266 * standard ethernet sized frames. 1267 */ 1268 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1269 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1270 1271 /* 1272 * This controls when hardware reports transmit completion 1273 * status. 1274 */ 1275 hw->mac.report_tx_early = 1; 1276 1277 /* Allocate multicast array memory. */ 1278 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1279 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1280 if (sc->mta == NULL) { 1281 device_printf(dev, 1282 "Can not allocate multicast setup array\n"); 1283 error = ENOMEM; 1284 goto err_late; 1285 } 1286 1287 /* Clear the IFCAP_TSO auto mask */ 1288 sc->tso_automasked = 0; 1289 1290 /* Check SOL/IDER usage */ 1291 if (e1000_check_reset_block(hw)) 1292 device_printf(dev, 1293 "PHY reset is blocked due to SOL/IDER session.\n"); 1294 1295 /* Sysctl for setting Energy Efficient Ethernet */ 1296 if (hw->mac.type < igb_mac_min) 1297 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1298 else 1299 hw->dev_spec._82575.eee_disable = eee_setting; 1300 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1301 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1302 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1303 1304 /* 1305 ** Start from a known state, this is 1306 ** important in reading the nvm and 1307 ** mac from that. 1308 */ 1309 e1000_reset_hw(hw); 1310 1311 /* Make sure we have a good EEPROM before we read from it */ 1312 if (e1000_validate_nvm_checksum(hw) < 0) { 1313 /* 1314 ** Some PCI-E parts fail the first check due to 1315 ** the link being in sleep state, call it again, 1316 ** if it fails a second time its a real issue. 1317 */ 1318 if (e1000_validate_nvm_checksum(hw) < 0) { 1319 device_printf(dev, 1320 "The EEPROM Checksum Is Not Valid\n"); 1321 error = EIO; 1322 goto err_late; 1323 } 1324 } 1325 1326 /* Copy the permanent MAC address out of the EEPROM */ 1327 if (e1000_read_mac_addr(hw) < 0) { 1328 device_printf(dev, 1329 "EEPROM read error while reading MAC address\n"); 1330 error = EIO; 1331 goto err_late; 1332 } 1333 1334 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1335 if (sc->vf_ifp) { 1336 ether_gen_addr(iflib_get_ifp(ctx), 1337 (struct ether_addr *)hw->mac.addr); 1338 } else { 1339 device_printf(dev, "Invalid MAC address\n"); 1340 error = EIO; 1341 goto err_late; 1342 } 1343 } 1344 1345 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1346 em_fw_version_locked(ctx); 1347 1348 em_print_fw_version(sc); 1349 1350 /* 1351 * Get Wake-on-Lan and Management info for later use 1352 */ 1353 em_get_wakeup(ctx); 1354 1355 /* Enable only WOL MAGIC by default */ 1356 scctx->isc_capenable &= ~IFCAP_WOL; 1357 if (sc->wol != 0) 1358 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1359 1360 iflib_set_mac(ctx, hw->mac.addr); 1361 1362 return (0); 1363 1364 err_late: 1365 em_release_hw_control(sc); 1366 err_pci: 1367 em_free_pci_resources(ctx); 1368 free(sc->mta, M_DEVBUF); 1369 1370 return (error); 1371 } 1372 1373 static int 1374 em_if_attach_post(if_ctx_t ctx) 1375 { 1376 struct e1000_softc *sc = iflib_get_softc(ctx); 1377 struct e1000_hw *hw = &sc->hw; 1378 int error = 0; 1379 1380 /* Setup OS specific network interface */ 1381 error = em_setup_interface(ctx); 1382 if (error != 0) { 1383 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1384 goto err_late; 1385 } 1386 1387 em_reset(ctx); 1388 1389 /* Initialize statistics */ 1390 if (sc->vf_ifp) 1391 sc->ustats.vf_stats = (struct e1000_vf_stats){}; 1392 else 1393 sc->ustats.stats = (struct e1000_hw_stats){}; 1394 1395 em_update_stats_counters(sc); 1396 hw->mac.get_link_status = 1; 1397 em_if_update_admin_status(ctx); 1398 em_add_hw_stats(sc); 1399 1400 /* Non-AMT based hardware can now take control from firmware */ 1401 if (sc->has_manage && !sc->has_amt) 1402 em_get_hw_control(sc); 1403 1404 INIT_DEBUGOUT("em_if_attach_post: end"); 1405 1406 return (0); 1407 1408 err_late: 1409 /* 1410 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1411 * free resources 1412 */ 1413 return (error); 1414 } 1415 1416 /********************************************************************* 1417 * Device removal routine 1418 * 1419 * The detach entry point is called when the driver is being removed. 1420 * This routine stops the adapter and deallocates all the resources 1421 * that were allocated for driver operation. 1422 * 1423 * return 0 on success, positive on failure 1424 *********************************************************************/ 1425 static int 1426 em_if_detach(if_ctx_t ctx) 1427 { 1428 struct e1000_softc *sc = iflib_get_softc(ctx); 1429 1430 INIT_DEBUGOUT("em_if_detach: begin"); 1431 1432 e1000_phy_hw_reset(&sc->hw); 1433 1434 em_release_manageability(sc); 1435 em_release_hw_control(sc); 1436 em_free_pci_resources(ctx); 1437 free(sc->mta, M_DEVBUF); 1438 sc->mta = NULL; 1439 1440 return (0); 1441 } 1442 1443 /********************************************************************* 1444 * 1445 * Shutdown entry point 1446 * 1447 **********************************************************************/ 1448 1449 static int 1450 em_if_shutdown(if_ctx_t ctx) 1451 { 1452 return em_if_suspend(ctx); 1453 } 1454 1455 /* 1456 * Suspend/resume device methods. 1457 */ 1458 static int 1459 em_if_suspend(if_ctx_t ctx) 1460 { 1461 struct e1000_softc *sc = iflib_get_softc(ctx); 1462 1463 em_release_manageability(sc); 1464 em_release_hw_control(sc); 1465 em_enable_wakeup(ctx); 1466 return (0); 1467 } 1468 1469 static int 1470 em_if_resume(if_ctx_t ctx) 1471 { 1472 struct e1000_softc *sc = iflib_get_softc(ctx); 1473 1474 if (sc->hw.mac.type == e1000_pch2lan) 1475 e1000_resume_workarounds_pchlan(&sc->hw); 1476 em_if_init(ctx); 1477 em_init_manageability(sc); 1478 1479 return(0); 1480 } 1481 1482 static int 1483 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1484 { 1485 int max_frame_size; 1486 struct e1000_softc *sc = iflib_get_softc(ctx); 1487 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1488 1489 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1490 1491 switch (sc->hw.mac.type) { 1492 case e1000_82571: 1493 case e1000_82572: 1494 case e1000_ich9lan: 1495 case e1000_ich10lan: 1496 case e1000_pch2lan: 1497 case e1000_pch_lpt: 1498 case e1000_pch_spt: 1499 case e1000_pch_cnp: 1500 case e1000_pch_tgp: 1501 case e1000_pch_adp: 1502 case e1000_pch_mtp: 1503 case e1000_pch_ptp: 1504 case e1000_82574: 1505 case e1000_82583: 1506 case e1000_80003es2lan: 1507 /* 9K Jumbo Frame size */ 1508 max_frame_size = 9234; 1509 break; 1510 case e1000_pchlan: 1511 max_frame_size = 4096; 1512 break; 1513 case e1000_82542: 1514 case e1000_ich8lan: 1515 /* Adapters that do not support jumbo frames */ 1516 max_frame_size = ETHER_MAX_LEN; 1517 break; 1518 default: 1519 if (sc->hw.mac.type >= igb_mac_min) 1520 max_frame_size = 9234; 1521 else /* lem */ 1522 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1523 } 1524 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1525 return (EINVAL); 1526 } 1527 1528 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1529 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1530 return (0); 1531 } 1532 1533 /********************************************************************* 1534 * Init entry point 1535 * 1536 * This routine is used in two ways. It is used by the stack as 1537 * init entry point in network interface structure. It is also used 1538 * by the driver as a hw/sw initialization routine to get to a 1539 * consistent state. 1540 * 1541 **********************************************************************/ 1542 static void 1543 em_if_init(if_ctx_t ctx) 1544 { 1545 struct e1000_softc *sc = iflib_get_softc(ctx); 1546 if_softc_ctx_t scctx = sc->shared; 1547 if_t ifp = iflib_get_ifp(ctx); 1548 struct em_tx_queue *tx_que; 1549 int i; 1550 1551 INIT_DEBUGOUT("em_if_init: begin"); 1552 1553 /* Get the latest mac address, User can use a LAA */ 1554 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1555 1556 /* Put the address into the Receive Address Array */ 1557 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1558 1559 /* 1560 * With the 82571 adapter, RAR[0] may be overwritten 1561 * when the other port is reset, we make a duplicate 1562 * in RAR[14] for that eventuality, this assures 1563 * the interface continues to function. 1564 */ 1565 if (sc->hw.mac.type == e1000_82571) { 1566 e1000_set_laa_state_82571(&sc->hw, true); 1567 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1568 E1000_RAR_ENTRIES - 1); 1569 } 1570 1571 /* Initialize the hardware */ 1572 em_reset(ctx); 1573 /* Re-arm a link-up transition deferred for this reset. */ 1574 if (sc->link_state == EM_LINK_STATE_DOWN_RESET_PENDING || 1575 sc->link_state == EM_LINK_STATE_UP_RESET_PENDING) 1576 sc->link_state = EM_LINK_STATE_DOWN; 1577 em_if_update_admin_status(ctx); 1578 1579 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1580 i++, tx_que++) { 1581 struct tx_ring *txr = &tx_que->txr; 1582 1583 txr->tx_rs_cidx = txr->tx_rs_pidx; 1584 1585 /* Initialize the last processed descriptor to be the end of 1586 * the ring, rather than the start, so that we avoid an 1587 * off-by-one error when calculating how many descriptors are 1588 * done in the credits_update function. 1589 */ 1590 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1591 } 1592 1593 /* Setup VLAN support, basic and offload if available */ 1594 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1595 1596 /* Clear bad data from Rx FIFOs */ 1597 if (sc->hw.mac.type >= igb_mac_min && !sc->vf_ifp) 1598 e1000_rx_fifo_flush_base(&sc->hw); 1599 1600 /* Configure for OS presence */ 1601 em_init_manageability(sc); 1602 1603 /* Prepare transmit descriptors and buffers */ 1604 em_initialize_transmit_unit(ctx); 1605 1606 /* Setup Multicast table */ 1607 em_if_multi_set(ctx); 1608 1609 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1610 em_initialize_receive_unit(ctx); 1611 1612 /* Set up VLAN support and filter */ 1613 em_setup_vlan_hw_support(ctx); 1614 1615 /* Don't lose promiscuous settings */ 1616 em_if_set_promisc(ctx, if_getflags(ifp)); 1617 1618 if (sc->hw.mac.ops.clear_hw_cntrs != NULL) 1619 sc->hw.mac.ops.clear_hw_cntrs(&sc->hw); 1620 1621 /* MSI-X configuration for 82574 */ 1622 if (sc->hw.mac.type == e1000_82574) { 1623 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1624 1625 tmp |= E1000_CTRL_EXT_PBA_CLR; 1626 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1627 /* Set the IVAR - interrupt vector routing. */ 1628 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1629 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1630 /* Set up queue routing */ 1631 igb_configure_queues(sc); 1632 } 1633 if (sc->hw.mac.type >= igb_mac_min) 1634 igb_initialize_interrupt_rate(sc); 1635 1636 /* this clears any pending interrupts */ 1637 E1000_READ_REG(&sc->hw, E1000_ICR); 1638 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1639 1640 /* AMT based hardware can now take control from firmware */ 1641 if (sc->has_manage && sc->has_amt) 1642 em_get_hw_control(sc); 1643 1644 /* Set Energy Efficient Ethernet */ 1645 if (sc->hw.mac.type >= igb_mac_min && 1646 sc->hw.phy.media_type == e1000_media_type_copper) { 1647 if (sc->hw.mac.type == e1000_i354) 1648 e1000_set_eee_i354(&sc->hw, true, true); 1649 else 1650 e1000_set_eee_i350(&sc->hw, true, true); 1651 } 1652 } 1653 1654 /* 1655 * RX publishes its byte and packet counters as one snapshot when iflib 1656 * returns descriptors to hardware. This also covers watchdog-driven RX 1657 * processing, which can run while the interrupt vector is unmasked. 1658 */ 1659 static __inline void 1660 em_aim_rx_delta(struct rx_ring *rxr, u32 *bytes, u32 *packets) 1661 { 1662 uint64_t snapshot; 1663 u32 now_bytes, now_packets; 1664 1665 snapshot = atomic_load_acq_64(&rxr->rx_aim_snapshot); 1666 now_bytes = snapshot >> 32; 1667 now_packets = (u32)snapshot; 1668 *bytes = now_bytes - rxr->rx_bytes_last; 1669 *packets = now_packets - rxr->rx_packets_last; 1670 rxr->rx_bytes_last = now_bytes; 1671 rxr->rx_packets_last = now_packets; 1672 } 1673 1674 /* 1675 * TX publishes its byte and packet counters as one snapshot at the doorbell, 1676 * because encapsulation can overlap the interrupt filter. The two halves 1677 * remain independent free running u32 counters, so their deltas are correct 1678 * across wrap. 1679 */ 1680 static __inline void 1681 em_aim_tx_delta(struct tx_ring *txr, u32 *bytes, u32 *packets) 1682 { 1683 uint64_t snapshot; 1684 u32 now_bytes, now_packets; 1685 1686 snapshot = atomic_load_acq_64(&txr->tx_aim_snapshot); 1687 now_bytes = snapshot >> 32; 1688 now_packets = (u32)snapshot; 1689 *bytes = now_bytes - txr->tx_bytes_last; 1690 *packets = now_packets - txr->tx_packets_last; 1691 txr->tx_bytes_last = now_bytes; 1692 txr->tx_packets_last = now_packets; 1693 } 1694 1695 /********************************************************************* 1696 * 1697 * Do Adaptive Interrupt Moderation: 1698 * - Calculate based on average size over the last interval 1699 * 1700 * Returns interrupts per second rather than a register value, so that the 1701 * caller's EM_INTS_TO_ITR()/IGB_INTS_TO_EITR() conversion applies, or zero 1702 * if the interval carried no packet to measure. 1703 * 1704 *********************************************************************/ 1705 static u32 1706 em_ring_itr(struct e1000_softc *sc, u32 rxbytes, u32 rxpackets, u32 txbytes, 1707 u32 txpackets) 1708 { 1709 u32 newitr = 0; 1710 1711 if (txbytes && txpackets) 1712 newitr = txbytes / txpackets; 1713 if (rxbytes && rxpackets) 1714 newitr = max(newitr, rxbytes / rxpackets); 1715 1716 /* 1717 * No packet was observed, so there is no size to work from. Report no 1718 * observation and let the caller keep the rate it already has. 1719 */ 1720 if (newitr == 0) 1721 return (0); 1722 1723 newitr += 24; /* account for hardware frame, crc */ 1724 /* set an upper boundary */ 1725 newitr = min(newitr, 3000); 1726 /* Be nice to the mid range */ 1727 if ((newitr > 300) && (newitr < 1200)) 1728 newitr = (newitr / 3); 1729 else 1730 newitr = (newitr / 2); 1731 1732 /* The value above was written straight to EITR; make it a rate */ 1733 newitr = EM_AIM_DIVIDEND / newitr; 1734 1735 /* 1736 * Cap the rate: enable_aim=1 is the normal setting, enable_aim=2 opts 1737 * into the low latency end. The original was unbounded and would ask 1738 * for ~95k ints/s on minimum sized frames. There is deliberately no 1739 * floor, so jumbo traffic settles near 2.7k ints/s. 1740 */ 1741 if (sc->enable_aim == 1) 1742 newitr = min(newitr, EM_INTS_20K); 1743 else 1744 newitr = min(newitr, EM_INTS_70K); 1745 1746 return (newitr); 1747 } 1748 1749 /********************************************************************* 1750 * 1751 * Helper to calculate next (E)ITR value for AIM 1752 * 1753 *********************************************************************/ 1754 static void 1755 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1756 struct rx_ring *rxr) 1757 { 1758 struct e1000_hw *hw = &sc->hw; 1759 struct em_tx_queue *tx_que; 1760 u32 ringbytes, ringpackets, rxbytes, rxpackets, txbytes, txpackets; 1761 u32 newitr; 1762 int i; 1763 1764 em_aim_rx_delta(rxr, &rxbytes, &rxpackets); 1765 1766 /* 1767 * A vector can service more than one TX ring when iflib is configured 1768 * with unequal RX and TX queue counts. Sample every ring routed to 1769 * this vector rather than treating the vector as a TX queue index. 1770 */ 1771 txbytes = txpackets = 0; 1772 for (i = 0; i < sc->tx_num_queues; i++) { 1773 tx_que = &sc->tx_queues[i]; 1774 if (tx_que->msix != que->msix) 1775 continue; 1776 em_aim_tx_delta(&tx_que->txr, &ringbytes, &ringpackets); 1777 txbytes += ringbytes; 1778 txpackets += ringpackets; 1779 } 1780 1781 /* Idle, do nothing */ 1782 if (txbytes == 0 && rxbytes == 0) 1783 return; 1784 1785 if (sc->enable_aim == 0) { 1786 newitr = em_max_interrupt_rate; 1787 } else if (sc->link_speed < SPEED_1000) { 1788 /* Use half default (4K) ITR if sub-gig */ 1789 newitr = EM_INTS_4K; 1790 } else if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1791 /* Want at least enough packet buffer for two frames to AIM */ 1792 newitr = em_max_interrupt_rate; 1793 } else { 1794 newitr = em_ring_itr(sc, rxbytes, rxpackets, txbytes, 1795 txpackets); 1796 /* No usable observation; leave the rate where it is */ 1797 if (newitr == 0) 1798 return; 1799 } 1800 1801 if (hw->mac.type >= igb_mac_min) { 1802 newitr = IGB_INTS_TO_EITR(newitr); 1803 1804 if (hw->mac.type == e1000_82575) 1805 newitr |= newitr << 16; 1806 else 1807 newitr |= E1000_EITR_CNT_IGNR; 1808 1809 if (newitr != que->itr_setting) { 1810 que->itr_setting = newitr; 1811 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1812 que->itr_setting); 1813 } 1814 } else { 1815 newitr = EM_INTS_TO_ITR(newitr); 1816 1817 if (newitr != que->itr_setting) { 1818 que->itr_setting = newitr; 1819 if (hw->mac.type == e1000_82574 && 1820 sc->intr_type == IFLIB_INTR_MSIX) { 1821 E1000_WRITE_REG(hw, 1822 E1000_EITR_82574(que->msix), 1823 que->itr_setting); 1824 } else { 1825 E1000_WRITE_REG(hw, E1000_ITR, 1826 que->itr_setting); 1827 } 1828 } 1829 } 1830 } 1831 1832 /********************************************************************* 1833 * 1834 * Fast Legacy/MSI Combined Interrupt Service routine 1835 * 1836 *********************************************************************/ 1837 int 1838 em_intr(void *arg) 1839 { 1840 struct e1000_softc *sc = arg; 1841 struct e1000_hw *hw = &sc->hw; 1842 struct em_rx_queue *que = &sc->rx_queues[0]; 1843 struct rx_ring *rxr = &que->rxr; 1844 if_ctx_t ctx = sc->ctx; 1845 u32 reg_icr; 1846 1847 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1848 1849 /* Hot eject? */ 1850 if (reg_icr == 0xffffffff) 1851 return FILTER_STRAY; 1852 1853 /* Definitely not our interrupt. */ 1854 if (reg_icr == 0x0) 1855 return FILTER_STRAY; 1856 1857 /* 1858 * Starting with the 82571 chip, bit 31 should be used to 1859 * determine whether the interrupt belongs to us. 1860 */ 1861 if (hw->mac.type >= e1000_82571 && 1862 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1863 return FILTER_STRAY; 1864 1865 /* 1866 * Only MSI-X interrupts have one-shot behavior by taking advantage 1867 * of the EIAC register. Thus, explicitly disable interrupts. This 1868 * also works around the MSI message reordering errata on certain 1869 * systems. 1870 */ 1871 IFDI_INTR_DISABLE(ctx); 1872 1873 /* Link status change */ 1874 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1875 em_handle_link(ctx); 1876 1877 if (reg_icr & E1000_ICR_RXO) 1878 sc->rx_overruns++; 1879 1880 if (hw->mac.type >= e1000_82540) 1881 em_newitr(sc, que, rxr); 1882 1883 return (FILTER_SCHEDULE_THREAD); 1884 } 1885 1886 static int 1887 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1888 { 1889 struct e1000_softc *sc = iflib_get_softc(ctx); 1890 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1891 1892 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1893 return (0); 1894 } 1895 1896 static int 1897 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1898 { 1899 struct e1000_softc *sc = iflib_get_softc(ctx); 1900 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1901 1902 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1903 return (0); 1904 } 1905 1906 static int 1907 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1908 { 1909 struct e1000_softc *sc = iflib_get_softc(ctx); 1910 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1911 1912 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1913 return (0); 1914 } 1915 1916 static int 1917 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1918 { 1919 struct e1000_softc *sc = iflib_get_softc(ctx); 1920 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1921 1922 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1923 return (0); 1924 } 1925 1926 /********************************************************************* 1927 * 1928 * MSI-X RX Interrupt Service routine 1929 * 1930 **********************************************************************/ 1931 static int 1932 em_msix_que(void *arg) 1933 { 1934 struct em_rx_queue *que = arg; 1935 struct e1000_softc *sc = que->sc; 1936 struct rx_ring *rxr = &que->rxr; 1937 1938 ++que->irqs; 1939 1940 em_newitr(sc, que, rxr); 1941 1942 return (FILTER_SCHEDULE_THREAD); 1943 } 1944 1945 /********************************************************************* 1946 * 1947 * MSI-X Link Fast Interrupt Service routine 1948 * 1949 **********************************************************************/ 1950 static int 1951 em_msix_link(void *arg) 1952 { 1953 struct e1000_softc *sc = arg; 1954 u32 reg_icr; 1955 1956 ++sc->link_irq; 1957 MPASS(sc->hw.back != NULL); 1958 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1959 1960 if (reg_icr & E1000_ICR_RXO) 1961 sc->rx_overruns++; 1962 1963 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1964 em_handle_link(sc->ctx); 1965 1966 /* Re-arm unconditionally */ 1967 if (sc->hw.mac.type >= igb_mac_min) { 1968 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1969 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1970 } else if (sc->hw.mac.type == e1000_82574) { 1971 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1972 E1000_IMS_LSC | E1000_IMS_OTHER); 1973 /* 1974 * Because we must read the ICR for this interrupt it may 1975 * clear other causes using autoclear, for this reason we 1976 * simply create a soft interrupt for all these vectors. 1977 */ 1978 if (reg_icr) 1979 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1980 } else 1981 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1982 1983 return (FILTER_HANDLED); 1984 } 1985 1986 static void 1987 em_handle_link(void *context) 1988 { 1989 if_ctx_t ctx = context; 1990 struct e1000_softc *sc = iflib_get_softc(ctx); 1991 1992 sc->hw.mac.get_link_status = 1; 1993 iflib_admin_intr_deferred(ctx); 1994 } 1995 1996 /********************************************************************* 1997 * 1998 * Media Ioctl callback 1999 * 2000 * This routine is called whenever the user queries the status of 2001 * the interface using ifconfig. 2002 * 2003 **********************************************************************/ 2004 static void 2005 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 2006 { 2007 struct e1000_softc *sc = iflib_get_softc(ctx); 2008 u_char fiber_type = IFM_1000_SX; 2009 2010 INIT_DEBUGOUT("em_if_media_status: begin"); 2011 2012 iflib_admin_intr_deferred(ctx); 2013 2014 ifmr->ifm_status = IFM_AVALID; 2015 ifmr->ifm_active = IFM_ETHER; 2016 2017 if (sc->link_state == EM_LINK_STATE_DOWN || 2018 sc->link_state == EM_LINK_STATE_DOWN_RESET_PENDING) { 2019 return; 2020 } 2021 2022 ifmr->ifm_status |= IFM_ACTIVE; 2023 2024 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 2025 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2026 if (sc->hw.mac.type == e1000_82545) 2027 fiber_type = IFM_1000_LX; 2028 ifmr->ifm_active |= fiber_type | IFM_FDX; 2029 } else { 2030 switch (sc->link_speed) { 2031 case 10: 2032 ifmr->ifm_active |= IFM_10_T; 2033 break; 2034 case 100: 2035 ifmr->ifm_active |= IFM_100_TX; 2036 break; 2037 case 1000: 2038 ifmr->ifm_active |= IFM_1000_T; 2039 break; 2040 } 2041 if (sc->link_duplex == FULL_DUPLEX) 2042 ifmr->ifm_active |= IFM_FDX; 2043 else 2044 ifmr->ifm_active |= IFM_HDX; 2045 } 2046 } 2047 2048 /********************************************************************* 2049 * 2050 * Media Ioctl callback 2051 * 2052 * This routine is called when the user changes speed/duplex using 2053 * media/mediopt option with ifconfig. 2054 * 2055 **********************************************************************/ 2056 static int 2057 em_if_media_change(if_ctx_t ctx) 2058 { 2059 struct e1000_softc *sc = iflib_get_softc(ctx); 2060 struct ifmedia *ifm = iflib_get_media(ctx); 2061 2062 INIT_DEBUGOUT("em_if_media_change: begin"); 2063 2064 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2065 return (EINVAL); 2066 2067 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2068 case IFM_AUTO: 2069 sc->hw.mac.autoneg = DO_AUTO_NEG; 2070 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2071 break; 2072 case IFM_1000_LX: 2073 case IFM_1000_SX: 2074 case IFM_1000_T: 2075 sc->hw.mac.autoneg = DO_AUTO_NEG; 2076 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2077 break; 2078 case IFM_100_TX: 2079 sc->hw.mac.autoneg = false; 2080 sc->hw.phy.autoneg_advertised = 0; 2081 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2082 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2083 else 2084 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2085 break; 2086 case IFM_10_T: 2087 sc->hw.mac.autoneg = false; 2088 sc->hw.phy.autoneg_advertised = 0; 2089 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2090 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2091 else 2092 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2093 break; 2094 default: 2095 device_printf(sc->dev, "Unsupported media type\n"); 2096 } 2097 2098 em_if_init(ctx); 2099 2100 return (0); 2101 } 2102 2103 static int 2104 em_if_set_promisc(if_ctx_t ctx, int flags) 2105 { 2106 struct e1000_softc *sc = iflib_get_softc(ctx); 2107 if_t ifp = iflib_get_ifp(ctx); 2108 u32 reg_rctl; 2109 int mcnt = 0; 2110 2111 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2112 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2113 if (flags & IFF_ALLMULTI) 2114 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2115 else 2116 mcnt = min(if_llmaddr_count(ifp), 2117 MAX_NUM_MULTICAST_ADDRESSES); 2118 2119 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2120 reg_rctl &= (~E1000_RCTL_MPE); 2121 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2122 2123 if (flags & IFF_PROMISC) { 2124 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2125 /* Turn this on if you want to see bad packets */ 2126 if (em_debug_sbp) 2127 reg_rctl |= E1000_RCTL_SBP; 2128 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2129 em_if_vlan_filter_disable(sc); 2130 } else { 2131 if (flags & IFF_ALLMULTI) { 2132 reg_rctl |= E1000_RCTL_MPE; 2133 reg_rctl &= ~E1000_RCTL_UPE; 2134 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2135 } 2136 if (em_if_vlan_filter_used(ctx)) 2137 em_if_vlan_filter_enable(sc); 2138 } 2139 return (0); 2140 } 2141 2142 static u_int 2143 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2144 { 2145 u8 *mta = arg; 2146 2147 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2148 return (0); 2149 2150 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2151 2152 return (1); 2153 } 2154 2155 /********************************************************************* 2156 * Multicast Update 2157 * 2158 * This routine is called whenever multicast address list is updated. 2159 * 2160 **********************************************************************/ 2161 static void 2162 em_if_multi_set(if_ctx_t ctx) 2163 { 2164 struct e1000_softc *sc = iflib_get_softc(ctx); 2165 if_t ifp = iflib_get_ifp(ctx); 2166 u8 *mta; /* Multicast array memory */ 2167 u32 reg_rctl = 0; 2168 int mcnt = 0; 2169 2170 IOCTL_DEBUGOUT("em_set_multi: begin"); 2171 2172 mta = sc->mta; 2173 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2174 2175 if (sc->hw.mac.type == e1000_82542 && 2176 sc->hw.revision_id == E1000_REVISION_2) { 2177 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2178 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2179 e1000_pci_clear_mwi(&sc->hw); 2180 reg_rctl |= E1000_RCTL_RST; 2181 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2182 msec_delay(5); 2183 } 2184 2185 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2186 2187 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2188 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2189 2190 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2191 2192 if (if_getflags(ifp) & IFF_PROMISC) 2193 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2194 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2195 if_getflags(ifp) & IFF_ALLMULTI) { 2196 reg_rctl |= E1000_RCTL_MPE; 2197 reg_rctl &= ~E1000_RCTL_UPE; 2198 } else 2199 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2200 2201 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2202 2203 if (sc->hw.mac.type == e1000_82542 && 2204 sc->hw.revision_id == E1000_REVISION_2) { 2205 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2206 reg_rctl &= ~E1000_RCTL_RST; 2207 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2208 msec_delay(5); 2209 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2210 e1000_pci_set_mwi(&sc->hw); 2211 } 2212 } 2213 2214 /********************************************************************* 2215 * Timer routine 2216 * 2217 * This routine schedules em_if_update_admin_status() to check for 2218 * link status and to gather statistics as well as to perform some 2219 * controller-specific hardware patting. 2220 * 2221 **********************************************************************/ 2222 static void 2223 em_if_timer(if_ctx_t ctx, uint16_t qid) 2224 { 2225 if (qid != 0) 2226 return; 2227 2228 iflib_admin_intr_deferred(ctx); 2229 } 2230 2231 static void 2232 em_if_update_admin_status(if_ctx_t ctx) 2233 { 2234 struct e1000_softc *sc = iflib_get_softc(ctx); 2235 struct e1000_hw *hw = &sc->hw; 2236 device_t dev = iflib_get_dev(ctx); 2237 u32 link_check, thstat, ctrl; 2238 bool reset_requested = false; 2239 2240 link_check = thstat = ctrl = 0; 2241 /* Get the cached link value or read phy for real */ 2242 switch (hw->phy.media_type) { 2243 case e1000_media_type_copper: 2244 if (hw->mac.get_link_status) { 2245 if (hw->mac.type == e1000_pch_spt) 2246 msec_delay(50); 2247 /* Do the work to read phy */ 2248 e1000_check_for_link(hw); 2249 link_check = !hw->mac.get_link_status; 2250 if (link_check) /* ESB2 fix */ 2251 e1000_cfg_on_link_up(hw); 2252 } else { 2253 link_check = true; 2254 } 2255 break; 2256 case e1000_media_type_fiber: 2257 e1000_check_for_link(hw); 2258 link_check = 2259 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2260 break; 2261 case e1000_media_type_internal_serdes: 2262 e1000_check_for_link(hw); 2263 link_check = hw->mac.serdes_has_link; 2264 break; 2265 /* VF device is type_unknown */ 2266 case e1000_media_type_unknown: 2267 e1000_check_for_link(hw); 2268 link_check = !hw->mac.get_link_status; 2269 /* FALLTHROUGH */ 2270 default: 2271 break; 2272 } 2273 2274 /* Check for thermal downshift or shutdown */ 2275 if (hw->mac.type == e1000_i350) { 2276 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2277 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2278 } 2279 2280 /* Now check for a transition */ 2281 if (link_check && 2282 (sc->link_state == EM_LINK_STATE_DOWN || 2283 sc->link_state == EM_LINK_STATE_DOWN_RESET_PENDING)) { 2284 bool reset_pending; 2285 2286 reset_pending = 2287 sc->link_state == EM_LINK_STATE_DOWN_RESET_PENDING; 2288 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2289 &sc->link_duplex); 2290 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2291 if ((sc->link_speed != SPEED_1000) && 2292 ((hw->mac.type == e1000_82571) || 2293 (hw->mac.type == e1000_82572))) { 2294 int tarc0; 2295 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2296 tarc0 &= ~TARC_SPEED_MODE_BIT; 2297 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2298 } 2299 if (bootverbose) 2300 device_printf(dev, "Link is up %d Mbps %s\n", 2301 sc->link_speed, 2302 ((sc->link_duplex == FULL_DUPLEX) ? 2303 "Full Duplex" : "Half Duplex")); 2304 sc->link_state = EM_LINK_STATE_UP; 2305 sc->smartspeed = 0; 2306 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2307 E1000_CTRL_EXT_LINK_MODE_GMII && 2308 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2309 device_printf(dev, "Link: thermal downshift\n"); 2310 /* Delay Link Up for Phy update */ 2311 if (((hw->mac.type == e1000_i210) || 2312 (hw->mac.type == e1000_i211)) && 2313 (hw->phy.id == I210_I_PHY_ID)) 2314 msec_delay(I210_LINK_DELAY); 2315 /* Reset if the media type changed. */ 2316 if (hw->dev_spec._82575.media_changed && 2317 hw->mac.type >= igb_mac_min) { 2318 hw->dev_spec._82575.media_changed = false; 2319 sc->flags |= IGB_MEDIA_RESET; 2320 em_reset(ctx); 2321 } 2322 /* Only do TSO on gigabit for older chips due to errata */ 2323 if (hw->mac.type < igb_mac_min) 2324 reset_requested = em_automask_tso(ctx); 2325 2326 if (reset_pending || reset_requested) { 2327 /* 2328 * The PHY is up, but publish it only after the TSO 2329 * capability-change reset. 2330 */ 2331 sc->link_state = EM_LINK_STATE_UP_RESET_PENDING; 2332 } else { 2333 iflib_link_state_change(ctx, LINK_STATE_UP, 2334 IF_Mbps(sc->link_speed)); 2335 } 2336 } else if (!link_check && 2337 (sc->link_state == EM_LINK_STATE_UP || 2338 sc->link_state == EM_LINK_STATE_UP_RESET_PENDING)) { 2339 bool link_was_published; 2340 bool reset_pending; 2341 2342 link_was_published = sc->link_state == EM_LINK_STATE_UP; 2343 reset_pending = 2344 sc->link_state == EM_LINK_STATE_UP_RESET_PENDING; 2345 sc->link_speed = 0; 2346 sc->link_duplex = 0; 2347 sc->link_state = reset_pending ? 2348 EM_LINK_STATE_DOWN_RESET_PENDING : EM_LINK_STATE_DOWN; 2349 if (link_was_published) 2350 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2351 } 2352 em_update_stats_counters(sc); 2353 2354 /* Reset LAA into RAR[0] on 82571 */ 2355 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2356 e1000_rar_set(hw, hw->mac.addr, 0); 2357 2358 if (hw->mac.type < em_mac_min) 2359 lem_smartspeed(sc); 2360 } 2361 2362 static void 2363 em_if_watchdog_reset(if_ctx_t ctx) 2364 { 2365 struct e1000_softc *sc = iflib_get_softc(ctx); 2366 2367 /* 2368 * Just count the event; iflib(4) will already trigger a 2369 * sufficient reset of the controller. 2370 */ 2371 sc->watchdog_events++; 2372 } 2373 2374 /********************************************************************* 2375 * 2376 * This routine disables all traffic on the adapter by issuing a 2377 * global reset on the MAC. 2378 * 2379 **********************************************************************/ 2380 static void 2381 em_if_stop(if_ctx_t ctx) 2382 { 2383 struct e1000_softc *sc = iflib_get_softc(ctx); 2384 2385 INIT_DEBUGOUT("em_if_stop: begin"); 2386 2387 /* I219 needs special flushing to avoid hangs */ 2388 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2389 em_flush_desc_rings(sc); 2390 2391 e1000_reset_hw(&sc->hw); 2392 if (sc->hw.mac.type >= e1000_82544 && !sc->vf_ifp) 2393 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2394 2395 e1000_led_off(&sc->hw); 2396 e1000_cleanup_led(&sc->hw); 2397 } 2398 2399 /********************************************************************* 2400 * 2401 * Determine hardware revision. 2402 * 2403 **********************************************************************/ 2404 static void 2405 em_identify_hardware(if_ctx_t ctx) 2406 { 2407 device_t dev = iflib_get_dev(ctx); 2408 struct e1000_softc *sc = iflib_get_softc(ctx); 2409 2410 /* Make sure our PCI config space has the necessary stuff set */ 2411 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2412 2413 /* Save off the information about this board */ 2414 sc->hw.vendor_id = pci_get_vendor(dev); 2415 sc->hw.device_id = pci_get_device(dev); 2416 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2417 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2418 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2419 2420 /* Do Shared Code Init and Setup */ 2421 if (e1000_set_mac_type(&sc->hw)) { 2422 device_printf(dev, "Setup init failure\n"); 2423 return; 2424 } 2425 2426 /* Are we a VF device? */ 2427 if ((sc->hw.mac.type == e1000_vfadapt) || 2428 (sc->hw.mac.type == e1000_vfadapt_i350)) 2429 sc->vf_ifp = 1; 2430 else 2431 sc->vf_ifp = 0; 2432 } 2433 2434 static int 2435 em_allocate_pci_resources(if_ctx_t ctx) 2436 { 2437 struct e1000_softc *sc = iflib_get_softc(ctx); 2438 device_t dev = iflib_get_dev(ctx); 2439 int rid, val; 2440 2441 rid = PCIR_BAR(0); 2442 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2443 RF_ACTIVE); 2444 if (sc->memory == NULL) { 2445 device_printf(dev, 2446 "Unable to allocate bus resource: memory\n"); 2447 return (ENXIO); 2448 } 2449 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2450 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2451 #ifdef INVARIANTS 2452 sc->osdep.mem_bus_space_size = rman_get_size(sc->memory); 2453 #endif 2454 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2455 2456 /* Only older adapters use IO mapping */ 2457 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2458 /* Figure our where our IO BAR is ? */ 2459 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2460 val = pci_read_config(dev, rid, 4); 2461 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2462 break; 2463 } 2464 rid += 4; 2465 /* check for 64bit BAR */ 2466 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2467 rid += 4; 2468 } 2469 if (rid >= PCIR_CIS) { 2470 device_printf(dev, "Unable to locate IO BAR\n"); 2471 return (ENXIO); 2472 } 2473 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2474 &rid, RF_ACTIVE); 2475 if (sc->ioport == NULL) { 2476 device_printf(dev, 2477 "Unable to allocate bus resource: ioport\n"); 2478 return (ENXIO); 2479 } 2480 sc->hw.io_base = 0; 2481 sc->osdep.io_bus_space_tag = 2482 rman_get_bustag(sc->ioport); 2483 sc->osdep.io_bus_space_handle = 2484 rman_get_bushandle(sc->ioport); 2485 } 2486 2487 sc->hw.back = &sc->osdep; 2488 2489 return (0); 2490 } 2491 2492 /********************************************************************* 2493 * 2494 * Set up the MSI-X Interrupt handlers 2495 * 2496 **********************************************************************/ 2497 static int 2498 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2499 { 2500 struct e1000_softc *sc = iflib_get_softc(ctx); 2501 struct em_rx_queue *rx_que = sc->rx_queues; 2502 struct em_tx_queue *tx_que = sc->tx_queues; 2503 int error, rid, i, vector = 0, rx_vectors; 2504 char buf[16]; 2505 2506 /* First set up ring resources */ 2507 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2508 rid = vector + 1; 2509 snprintf(buf, sizeof(buf), "rxq%d", i); 2510 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2511 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2512 if (error) { 2513 device_printf(iflib_get_dev(ctx), 2514 "Failed to allocate que int %d err: %d", 2515 i, error); 2516 sc->rx_num_queues = i + 1; 2517 goto fail; 2518 } 2519 2520 rx_que->msix = vector; 2521 2522 /* 2523 * Set the bit to enable interrupt 2524 * in E1000_IMS -- bits 20 and 21 2525 * are for RX0 and RX1, note this has 2526 * NOTHING to do with the MSI-X vector 2527 */ 2528 if (sc->hw.mac.type == e1000_82574) { 2529 rx_que->eims = 1 << (20 + i); 2530 sc->ims |= rx_que->eims; 2531 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2532 } else if (sc->hw.mac.type == e1000_82575) 2533 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2534 else 2535 rx_que->eims = 1 << vector; 2536 } 2537 rx_vectors = vector; 2538 2539 vector = 0; 2540 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2541 snprintf(buf, sizeof(buf), "txq%d", i); 2542 tx_que = &sc->tx_queues[i]; 2543 iflib_softirq_alloc_generic(ctx, 2544 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2545 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2546 2547 tx_que->msix = (vector % sc->rx_num_queues); 2548 2549 /* 2550 * Set the bit to enable interrupt 2551 * in E1000_IMS -- bits 22 and 23 2552 * are for TX0 and TX1, note this has 2553 * NOTHING to do with the MSI-X vector 2554 */ 2555 if (sc->hw.mac.type == e1000_82574) { 2556 tx_que->eims = 1 << (22 + i); 2557 sc->ims |= tx_que->eims; 2558 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2559 } else if (sc->hw.mac.type == e1000_82575) { 2560 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2561 } else { 2562 tx_que->eims = 1 << i; 2563 } 2564 } 2565 2566 /* Link interrupt */ 2567 rid = rx_vectors + 1; 2568 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2569 em_msix_link, sc, 0, "aq"); 2570 2571 if (error) { 2572 device_printf(iflib_get_dev(ctx), 2573 "Failed to register admin handler"); 2574 goto fail; 2575 } 2576 sc->linkvec = rx_vectors; 2577 if (sc->hw.mac.type < igb_mac_min) { 2578 sc->ivars |= (8 | rx_vectors) << 16; 2579 sc->ivars |= 0x80000000; 2580 /* Enable the "Other" interrupt type for link status change */ 2581 sc->ims |= E1000_IMS_OTHER; 2582 } 2583 2584 return (0); 2585 fail: 2586 iflib_irq_free(ctx, &sc->irq); 2587 rx_que = sc->rx_queues; 2588 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2589 iflib_irq_free(ctx, &rx_que->que_irq); 2590 return (error); 2591 } 2592 2593 static void 2594 igb_configure_queues(struct e1000_softc *sc) 2595 { 2596 struct e1000_hw *hw = &sc->hw; 2597 struct em_rx_queue *rx_que; 2598 struct em_tx_queue *tx_que; 2599 u32 tmp, ivar = 0; 2600 2601 /* First turn on RSS capability */ 2602 if (hw->mac.type != e1000_82575) 2603 E1000_WRITE_REG(hw, E1000_GPIE, 2604 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2605 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2606 2607 /* Turn on MSI-X */ 2608 switch (hw->mac.type) { 2609 case e1000_82580: 2610 case e1000_i350: 2611 case e1000_i354: 2612 case e1000_i210: 2613 case e1000_i211: 2614 case e1000_vfadapt: 2615 case e1000_vfadapt_i350: 2616 /* RX entries */ 2617 for (int i = 0; i < sc->rx_num_queues; i++) { 2618 u32 index = i >> 1; 2619 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2620 rx_que = &sc->rx_queues[i]; 2621 if (i & 1) { 2622 ivar &= 0xFF00FFFF; 2623 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2624 16; 2625 } else { 2626 ivar &= 0xFFFFFF00; 2627 ivar |= rx_que->msix | E1000_IVAR_VALID; 2628 } 2629 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2630 } 2631 /* TX entries */ 2632 for (int i = 0; i < sc->tx_num_queues; i++) { 2633 u32 index = i >> 1; 2634 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2635 tx_que = &sc->tx_queues[i]; 2636 if (i & 1) { 2637 ivar &= 0x00FFFFFF; 2638 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2639 24; 2640 } else { 2641 ivar &= 0xFFFF00FF; 2642 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2643 8; 2644 } 2645 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2646 sc->que_mask |= tx_que->eims; 2647 } 2648 2649 /* And for the link interrupt */ 2650 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2651 sc->link_mask = 1 << sc->linkvec; 2652 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2653 break; 2654 case e1000_82576: 2655 /* RX entries */ 2656 for (int i = 0; i < sc->rx_num_queues; i++) { 2657 u32 index = i & 0x7; /* Each IVAR has two entries */ 2658 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2659 rx_que = &sc->rx_queues[i]; 2660 if (i < 8) { 2661 ivar &= 0xFFFFFF00; 2662 ivar |= rx_que->msix | E1000_IVAR_VALID; 2663 } else { 2664 ivar &= 0xFF00FFFF; 2665 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2666 16; 2667 } 2668 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2669 sc->que_mask |= rx_que->eims; 2670 } 2671 /* TX entries */ 2672 for (int i = 0; i < sc->tx_num_queues; i++) { 2673 u32 index = i & 0x7; /* Each IVAR has two entries */ 2674 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2675 tx_que = &sc->tx_queues[i]; 2676 if (i < 8) { 2677 ivar &= 0xFFFF00FF; 2678 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2679 8; 2680 } else { 2681 ivar &= 0x00FFFFFF; 2682 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2683 24; 2684 } 2685 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2686 sc->que_mask |= tx_que->eims; 2687 } 2688 2689 /* And for the link interrupt */ 2690 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2691 sc->link_mask = 1 << sc->linkvec; 2692 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2693 break; 2694 2695 case e1000_82575: 2696 /* enable MSI-X support*/ 2697 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2698 tmp |= E1000_CTRL_EXT_PBA_CLR; 2699 /* Auto-Mask interrupts upon ICR read. */ 2700 tmp |= E1000_CTRL_EXT_EIAME; 2701 tmp |= E1000_CTRL_EXT_IRCA; 2702 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2703 2704 /* Queues */ 2705 for (int i = 0; i < sc->rx_num_queues; i++) { 2706 rx_que = &sc->rx_queues[i]; 2707 tmp = E1000_EICR_RX_QUEUE0 << i; 2708 tmp |= E1000_EICR_TX_QUEUE0 << i; 2709 rx_que->eims = tmp; 2710 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2711 rx_que->eims); 2712 sc->que_mask |= rx_que->eims; 2713 } 2714 2715 /* Link */ 2716 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2717 E1000_EIMS_OTHER); 2718 sc->link_mask |= E1000_EIMS_OTHER; 2719 default: 2720 break; 2721 } 2722 2723 return; 2724 } 2725 2726 static void 2727 igb_initialize_interrupt_rate(struct e1000_softc *sc) 2728 { 2729 struct e1000_hw *hw = &sc->hw; 2730 struct em_rx_queue *rx_que; 2731 u32 newitr; 2732 2733 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2734 if (hw->mac.type == e1000_82575) 2735 newitr |= newitr << 16; 2736 else 2737 newitr |= E1000_EITR_CNT_IGNR; 2738 2739 for (int i = 0; i < sc->rx_num_queues; i++) { 2740 rx_que = &sc->rx_queues[i]; 2741 rx_que->itr_setting = newitr; 2742 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), 2743 rx_que->itr_setting); 2744 } 2745 } 2746 2747 static void 2748 em_free_pci_resources(if_ctx_t ctx) 2749 { 2750 struct e1000_softc *sc = iflib_get_softc(ctx); 2751 struct em_rx_queue *que = sc->rx_queues; 2752 device_t dev = iflib_get_dev(ctx); 2753 2754 /* Release all MSI-X queue resources */ 2755 if (sc->intr_type == IFLIB_INTR_MSIX) 2756 iflib_irq_free(ctx, &sc->irq); 2757 2758 if (que != NULL) { 2759 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2760 iflib_irq_free(ctx, &que->que_irq); 2761 } 2762 } 2763 2764 if (sc->memory != NULL) { 2765 bus_release_resource(dev, SYS_RES_MEMORY, 2766 rman_get_rid(sc->memory), sc->memory); 2767 sc->memory = NULL; 2768 } 2769 2770 if (sc->flash != NULL) { 2771 bus_release_resource(dev, SYS_RES_MEMORY, 2772 rman_get_rid(sc->flash), sc->flash); 2773 sc->flash = NULL; 2774 } 2775 2776 if (sc->ioport != NULL) { 2777 bus_release_resource(dev, SYS_RES_IOPORT, 2778 rman_get_rid(sc->ioport), sc->ioport); 2779 sc->ioport = NULL; 2780 } 2781 } 2782 2783 /* Set up MSI or MSI-X */ 2784 static int 2785 em_setup_msix(if_ctx_t ctx) 2786 { 2787 struct e1000_softc *sc = iflib_get_softc(ctx); 2788 2789 if (sc->hw.mac.type == e1000_82574) { 2790 em_enable_vectors_82574(ctx); 2791 } 2792 return (0); 2793 } 2794 2795 /********************************************************************* 2796 * 2797 * Workaround for SmartSpeed on 82541 and 82547 controllers 2798 * 2799 **********************************************************************/ 2800 static void 2801 lem_smartspeed(struct e1000_softc *sc) 2802 { 2803 u16 phy_tmp; 2804 2805 if (sc->link_state == EM_LINK_STATE_UP || 2806 sc->link_state == EM_LINK_STATE_UP_RESET_PENDING || 2807 (sc->hw.phy.type != e1000_phy_igp) || 2808 sc->hw.mac.autoneg == 0 || 2809 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2810 return; 2811 2812 if (sc->smartspeed == 0) { 2813 /* If Master/Slave config fault is asserted twice, 2814 * we assume back-to-back */ 2815 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2816 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2817 return; 2818 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2819 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2820 e1000_read_phy_reg(&sc->hw, 2821 PHY_1000T_CTRL, &phy_tmp); 2822 if(phy_tmp & CR_1000T_MS_ENABLE) { 2823 phy_tmp &= ~CR_1000T_MS_ENABLE; 2824 e1000_write_phy_reg(&sc->hw, 2825 PHY_1000T_CTRL, phy_tmp); 2826 sc->smartspeed++; 2827 if(sc->hw.mac.autoneg && 2828 !e1000_copper_link_autoneg(&sc->hw) && 2829 !e1000_read_phy_reg(&sc->hw, 2830 PHY_CONTROL, &phy_tmp)) { 2831 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2832 MII_CR_RESTART_AUTO_NEG); 2833 e1000_write_phy_reg(&sc->hw, 2834 PHY_CONTROL, phy_tmp); 2835 } 2836 } 2837 } 2838 return; 2839 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2840 /* If still no link, perhaps using 2/3 pair cable */ 2841 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2842 phy_tmp |= CR_1000T_MS_ENABLE; 2843 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2844 if(sc->hw.mac.autoneg && 2845 !e1000_copper_link_autoneg(&sc->hw) && 2846 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2847 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2848 MII_CR_RESTART_AUTO_NEG); 2849 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2850 } 2851 } 2852 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2853 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2854 sc->smartspeed = 0; 2855 } 2856 2857 /********************************************************************* 2858 * 2859 * Initialize the DMA Coalescing feature 2860 * 2861 **********************************************************************/ 2862 static void 2863 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2864 { 2865 device_t dev = sc->dev; 2866 struct e1000_hw *hw = &sc->hw; 2867 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2868 u16 hwm; 2869 u16 max_frame_size; 2870 2871 if (hw->mac.type == e1000_i211) 2872 return; 2873 2874 max_frame_size = sc->shared->isc_max_frame_size; 2875 if (hw->mac.type > e1000_82580) { 2876 2877 if (sc->dmac == 0) { /* Disabling it */ 2878 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2879 return; 2880 } else 2881 device_printf(dev, "DMA Coalescing enabled\n"); 2882 2883 /* Set starting threshold */ 2884 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2885 2886 hwm = 64 * pba - max_frame_size / 16; 2887 if (hwm < 64 * (pba - 6)) 2888 hwm = 64 * (pba - 6); 2889 reg = E1000_READ_REG(hw, E1000_FCRTC); 2890 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2891 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2892 & E1000_FCRTC_RTH_COAL_MASK); 2893 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2894 2895 2896 dmac = pba - max_frame_size / 512; 2897 if (dmac < pba - 10) 2898 dmac = pba - 10; 2899 reg = E1000_READ_REG(hw, E1000_DMACR); 2900 reg &= ~E1000_DMACR_DMACTHR_MASK; 2901 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2902 & E1000_DMACR_DMACTHR_MASK); 2903 2904 /* transition to L0x or L1 if available..*/ 2905 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2906 2907 /* Check if status is 2.5Gb backplane connection 2908 * before configuration of watchdog timer, which is 2909 * in msec values in 12.8usec intervals 2910 * watchdog timer= msec values in 32usec intervals 2911 * for non 2.5Gb connection 2912 */ 2913 if (hw->mac.type == e1000_i354) { 2914 int status = E1000_READ_REG(hw, E1000_STATUS); 2915 if ((status & E1000_STATUS_2P5_SKU) && 2916 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2917 reg |= ((sc->dmac * 5) >> 6); 2918 else 2919 reg |= (sc->dmac >> 5); 2920 } else { 2921 reg |= (sc->dmac >> 5); 2922 } 2923 2924 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2925 2926 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2927 2928 /* Set the interval before transition */ 2929 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2930 if (hw->mac.type == e1000_i350) 2931 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2932 /* 2933 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2934 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2935 */ 2936 if (hw->mac.type == e1000_i354) { 2937 int status = E1000_READ_REG(hw, E1000_STATUS); 2938 if ((status & E1000_STATUS_2P5_SKU) && 2939 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2940 reg |= 0xA; 2941 else 2942 reg |= 0x4; 2943 } else { 2944 reg |= 0x4; 2945 } 2946 2947 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2948 2949 /* free space in tx packet buffer to wake from DMA coal */ 2950 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2951 (2 * max_frame_size)) >> 6); 2952 2953 /* make low power state decision controlled by DMA coal */ 2954 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2955 reg &= ~E1000_PCIEMISC_LX_DECISION; 2956 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2957 2958 } else if (hw->mac.type == e1000_82580) { 2959 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2960 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2961 reg & ~E1000_PCIEMISC_LX_DECISION); 2962 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2963 } 2964 } 2965 /********************************************************************* 2966 * The 3 following flush routines are used as a workaround in the 2967 * I219 client parts and only for them. 2968 * 2969 * em_flush_tx_ring - remove all descriptors from the tx_ring 2970 * 2971 * We want to clear all pending descriptors from the TX ring. 2972 * zeroing happens when the HW reads the regs. We assign the ring itself as 2973 * the data of the next descriptor. We don't care about the data we are about 2974 * to reset the HW. 2975 **********************************************************************/ 2976 static void 2977 em_flush_tx_ring(struct e1000_softc *sc) 2978 { 2979 struct e1000_hw *hw = &sc->hw; 2980 struct tx_ring *txr = &sc->tx_queues->txr; 2981 struct e1000_tx_desc *txd; 2982 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2983 u16 size = 512; 2984 2985 tctl = E1000_READ_REG(hw, E1000_TCTL); 2986 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2987 2988 txd = &txr->tx_base[txr->tx_cidx_processed]; 2989 2990 /* Just use the ring as a dummy buffer addr */ 2991 txd->buffer_addr = txr->tx_paddr; 2992 txd->lower.data = htole32(txd_lower | size); 2993 txd->upper.data = 0; 2994 2995 /* flush descriptors to memory before notifying the HW */ 2996 wmb(); 2997 2998 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2999 mb(); 3000 usec_delay(250); 3001 } 3002 3003 /********************************************************************* 3004 * em_flush_rx_ring - remove all descriptors from the rx_ring 3005 * 3006 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3007 **********************************************************************/ 3008 static void 3009 em_flush_rx_ring(struct e1000_softc *sc) 3010 { 3011 struct e1000_hw *hw = &sc->hw; 3012 u32 rctl, rxdctl; 3013 3014 rctl = E1000_READ_REG(hw, E1000_RCTL); 3015 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3016 E1000_WRITE_FLUSH(hw); 3017 usec_delay(150); 3018 3019 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3020 /* zero the lower 14 bits (prefetch and host thresholds) */ 3021 rxdctl &= 0xffffc000; 3022 /* 3023 * update thresholds: prefetch threshold to 31, host threshold to 1 3024 * and make sure the granularity is "descriptors" and not 3025 * "cache lines" 3026 */ 3027 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3028 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 3029 3030 /* momentarily enable the RX ring for the changes to take effect */ 3031 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3032 E1000_WRITE_FLUSH(hw); 3033 usec_delay(150); 3034 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3035 } 3036 3037 /********************************************************************* 3038 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3039 * 3040 * In I219, the descriptor rings must be emptied before resetting the HW 3041 * or before changing the device state to D3 during runtime (runtime PM). 3042 * 3043 * Failure to do this will cause the HW to enter a unit hang state which can 3044 * only be released by PCI reset on the device 3045 * 3046 **********************************************************************/ 3047 static void 3048 em_flush_desc_rings(struct e1000_softc *sc) 3049 { 3050 struct e1000_hw *hw = &sc->hw; 3051 device_t dev = sc->dev; 3052 u16 hang_state; 3053 u32 fext_nvm11, tdlen; 3054 3055 /* First, disable MULR fix in FEXTNVM11 */ 3056 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 3057 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3058 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3059 3060 /* do nothing if we're not in faulty state, or the queue is empty */ 3061 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3062 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3063 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3064 return; 3065 em_flush_tx_ring(sc); 3066 3067 /* recheck, maybe the fault is caused by the rx ring */ 3068 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3069 if (hang_state & FLUSH_DESC_REQUIRED) 3070 em_flush_rx_ring(sc); 3071 } 3072 3073 3074 /********************************************************************* 3075 * 3076 * Initialize the hardware to a configuration as specified by the 3077 * sc structure. 3078 * 3079 **********************************************************************/ 3080 static void 3081 em_reset(if_ctx_t ctx) 3082 { 3083 device_t dev = iflib_get_dev(ctx); 3084 struct e1000_softc *sc = iflib_get_softc(ctx); 3085 if_t ifp = iflib_get_ifp(ctx); 3086 struct e1000_hw *hw = &sc->hw; 3087 u32 rx_buffer_size; 3088 u32 pba; 3089 3090 INIT_DEBUGOUT("em_reset: begin"); 3091 /* Let the firmware know the OS is in control */ 3092 em_get_hw_control(sc); 3093 3094 /* Set up smart power down as default off on newer adapters. */ 3095 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3096 hw->mac.type == e1000_82572)) { 3097 u16 phy_tmp = 0; 3098 3099 /* Speed up time to link by disabling smart power down. */ 3100 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3101 phy_tmp &= ~IGP02E1000_PM_SPD; 3102 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3103 } 3104 3105 /* 3106 * Packet Buffer Allocation (PBA) 3107 * Writing PBA sets the receive portion of the buffer 3108 * the remainder is used for the transmit buffer. 3109 */ 3110 switch (hw->mac.type) { 3111 /* 82547: Total Packet Buffer is 40K */ 3112 case e1000_82547: 3113 case e1000_82547_rev_2: 3114 if (hw->mac.max_frame_size > 8192) 3115 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3116 else 3117 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3118 break; 3119 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3120 case e1000_82571: 3121 case e1000_82572: 3122 case e1000_80003es2lan: 3123 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3124 break; 3125 /* 82573: Total Packet Buffer is 32K */ 3126 case e1000_82573: 3127 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3128 break; 3129 /* 82574/82583: Total Packet Buffer is 40K */ 3130 case e1000_82574: 3131 case e1000_82583: 3132 if (hw->mac.max_frame_size > 8192) 3133 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3134 else 3135 pba = E1000_PBA_32K; /* 32K for RX, 8K for Tx */ 3136 break; 3137 case e1000_ich8lan: 3138 pba = E1000_PBA_8K; 3139 break; 3140 case e1000_ich9lan: 3141 case e1000_ich10lan: 3142 /* Boost Receive side for jumbo frames */ 3143 if (hw->mac.max_frame_size > 4096) 3144 pba = E1000_PBA_14K; 3145 else 3146 pba = E1000_PBA_10K; 3147 break; 3148 case e1000_pchlan: 3149 case e1000_pch2lan: 3150 case e1000_pch_lpt: 3151 case e1000_pch_spt: 3152 case e1000_pch_cnp: 3153 case e1000_pch_tgp: 3154 case e1000_pch_adp: 3155 case e1000_pch_mtp: 3156 case e1000_pch_ptp: 3157 pba = E1000_PBA_26K; 3158 break; 3159 case e1000_82575: 3160 pba = E1000_PBA_32K; 3161 break; 3162 case e1000_82576: 3163 case e1000_vfadapt: 3164 pba = E1000_READ_REG(hw, E1000_RXPBS); 3165 pba &= E1000_RXPBS_SIZE_MASK_82576; 3166 break; 3167 case e1000_82580: 3168 case e1000_i350: 3169 case e1000_i354: 3170 case e1000_vfadapt_i350: 3171 pba = E1000_READ_REG(hw, E1000_RXPBS); 3172 pba = e1000_rxpbs_adjust_82580(pba); 3173 break; 3174 case e1000_i210: 3175 case e1000_i211: 3176 pba = E1000_PBA_34K; 3177 break; 3178 default: 3179 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3180 if (hw->mac.max_frame_size > 8192) 3181 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3182 else 3183 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3184 } 3185 3186 /* Special needs in case of Jumbo frames */ 3187 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3188 u32 tx_space, min_tx, min_rx; 3189 pba = E1000_READ_REG(hw, E1000_PBA); 3190 tx_space = pba >> 16; 3191 pba &= 0xffff; 3192 min_tx = (hw->mac.max_frame_size + 3193 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3194 min_tx = roundup2(min_tx, 1024); 3195 min_tx >>= 10; 3196 min_rx = hw->mac.max_frame_size; 3197 min_rx = roundup2(min_rx, 1024); 3198 min_rx >>= 10; 3199 if (tx_space < min_tx && 3200 ((min_tx - tx_space) < pba)) { 3201 pba = pba - (min_tx - tx_space); 3202 /* 3203 * if short on rx space, rx wins 3204 * and must trump tx adjustment 3205 */ 3206 if (pba < min_rx) 3207 pba = min_rx; 3208 } 3209 E1000_WRITE_REG(hw, E1000_PBA, pba); 3210 } 3211 3212 if (hw->mac.type < igb_mac_min) 3213 E1000_WRITE_REG(hw, E1000_PBA, pba); 3214 3215 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3216 3217 /* 3218 * These parameters control the automatic generation (Tx) and 3219 * response (Rx) to Ethernet PAUSE frames. 3220 * - High water mark should allow for at least two frames to be 3221 * received after sending an XOFF. 3222 * - Low water mark works best when it is very near the high water 3223 mark. 3224 * This allows the receiver to restart by sending XON when it has 3225 * drained a bit. Here we use an arbitrary value of 1500 which will 3226 * restart after one full frame is pulled from the buffer. There 3227 * could be several smaller frames in the buffer and if so they will 3228 * not trigger the XON until their total number reduces the buffer 3229 * by 1500. 3230 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3231 */ 3232 rx_buffer_size = (pba & 0xffff) << 10; 3233 hw->fc.high_water = rx_buffer_size - 3234 roundup2(hw->mac.max_frame_size, 1024); 3235 hw->fc.low_water = hw->fc.high_water - 1500; 3236 3237 if (sc->fc) /* locally set flow control value? */ 3238 hw->fc.requested_mode = sc->fc; 3239 else 3240 hw->fc.requested_mode = e1000_fc_full; 3241 3242 if (hw->mac.type == e1000_80003es2lan) 3243 hw->fc.pause_time = 0xFFFF; 3244 else 3245 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3246 3247 hw->fc.send_xon = true; 3248 3249 /* Device specific overrides/settings */ 3250 switch (hw->mac.type) { 3251 case e1000_pchlan: 3252 /* Workaround: no TX flow ctrl for PCH */ 3253 hw->fc.requested_mode = e1000_fc_rx_pause; 3254 hw->fc.pause_time = 0xFFFF; /* override */ 3255 if (if_getmtu(ifp) > ETHERMTU) { 3256 hw->fc.high_water = 0x3500; 3257 hw->fc.low_water = 0x1500; 3258 } else { 3259 hw->fc.high_water = 0x5000; 3260 hw->fc.low_water = 0x3000; 3261 } 3262 hw->fc.refresh_time = 0x1000; 3263 break; 3264 case e1000_pch2lan: 3265 case e1000_pch_lpt: 3266 case e1000_pch_spt: 3267 case e1000_pch_cnp: 3268 case e1000_pch_tgp: 3269 case e1000_pch_adp: 3270 case e1000_pch_mtp: 3271 case e1000_pch_ptp: 3272 hw->fc.high_water = 0x5C20; 3273 hw->fc.low_water = 0x5048; 3274 hw->fc.pause_time = 0xFFFF; 3275 hw->fc.refresh_time = 0xFFFF; 3276 /* Jumbos need adjusted PBA */ 3277 if (if_getmtu(ifp) > ETHERMTU) 3278 pba = E1000_PBA_12K; 3279 else 3280 pba = E1000_PBA_26K; 3281 E1000_WRITE_REG(hw, E1000_PBA, pba); 3282 break; 3283 case e1000_82575: 3284 case e1000_82576: 3285 /* 8-byte granularity */ 3286 hw->fc.low_water = hw->fc.high_water - 8; 3287 break; 3288 case e1000_82580: 3289 case e1000_i350: 3290 case e1000_i354: 3291 case e1000_i210: 3292 case e1000_i211: 3293 case e1000_vfadapt: 3294 case e1000_vfadapt_i350: 3295 /* 16-byte granularity */ 3296 hw->fc.low_water = hw->fc.high_water - 16; 3297 break; 3298 case e1000_ich9lan: 3299 case e1000_ich10lan: 3300 if (if_getmtu(ifp) > ETHERMTU) { 3301 hw->fc.high_water = 0x2800; 3302 hw->fc.low_water = hw->fc.high_water - 8; 3303 break; 3304 } 3305 /* FALLTHROUGH */ 3306 default: 3307 if (hw->mac.type == e1000_80003es2lan) 3308 hw->fc.pause_time = 0xFFFF; 3309 break; 3310 } 3311 3312 /* I219 needs some special flushing to avoid hangs */ 3313 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3314 em_flush_desc_rings(sc); 3315 3316 /* Issue a global reset */ 3317 e1000_reset_hw(hw); 3318 if (!sc->vf_ifp) { 3319 if (hw->mac.type >= igb_mac_min) { 3320 E1000_WRITE_REG(hw, E1000_WUC, 0); 3321 } else { 3322 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3323 em_disable_aspm(sc); 3324 } 3325 } 3326 if (sc->flags & IGB_MEDIA_RESET) { 3327 e1000_setup_init_funcs(hw, true); 3328 e1000_get_bus_info(hw); 3329 sc->flags &= ~IGB_MEDIA_RESET; 3330 } 3331 /* and a re-init */ 3332 if (e1000_init_hw(hw) < 0) { 3333 device_printf(dev, "Hardware Initialization Failed\n"); 3334 return; 3335 } 3336 if (hw->mac.type >= igb_mac_min) 3337 igb_init_dmac(sc, pba); 3338 3339 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3340 sc->pba = pba; 3341 3342 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3343 e1000_get_phy_info(hw); 3344 e1000_check_for_link(hw); 3345 } 3346 3347 /* 3348 * Initialise the RSS mapping for NICs that support multiple transmit/ 3349 * receive rings. 3350 */ 3351 3352 #define RSSKEYLEN 10 3353 static void 3354 em_initialize_rss_mapping(struct e1000_softc *sc) 3355 { 3356 uint8_t rss_key[4 * RSSKEYLEN]; 3357 uint32_t reta = 0; 3358 struct e1000_hw *hw = &sc->hw; 3359 int i; 3360 3361 /* 3362 * Configure RSS key 3363 */ 3364 arc4rand(rss_key, sizeof(rss_key), 0); 3365 for (i = 0; i < RSSKEYLEN; ++i) { 3366 uint32_t rssrk = 0; 3367 3368 rssrk = EM_RSSRK_VAL(rss_key, i); 3369 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3370 } 3371 3372 /* 3373 * Configure RSS redirect table in following fashion: 3374 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3375 */ 3376 for (i = 0; i < sizeof(reta); ++i) { 3377 uint32_t q; 3378 3379 q = (i % sc->rx_num_queues) << 7; 3380 reta |= q << (8 * i); 3381 } 3382 3383 for (i = 0; i < 32; ++i) 3384 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3385 3386 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3387 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3388 E1000_MRQC_RSS_FIELD_IPV4 | 3389 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3390 E1000_MRQC_RSS_FIELD_IPV6_EX | 3391 E1000_MRQC_RSS_FIELD_IPV6); 3392 } 3393 3394 static void 3395 igb_initialize_rss_mapping(struct e1000_softc *sc) 3396 { 3397 struct e1000_hw *hw = &sc->hw; 3398 int i; 3399 int queue_id; 3400 u32 reta; 3401 u32 rss_key[10], mrqc, shift = 0; 3402 3403 /* XXX? */ 3404 if (hw->mac.type == e1000_82575) 3405 shift = 6; 3406 3407 /* 3408 * The redirection table controls which destination 3409 * queue each bucket redirects traffic to. 3410 * Each DWORD represents four queues, with the LSB 3411 * being the first queue in the DWORD. 3412 * 3413 * This just allocates buckets to queues using round-robin 3414 * allocation. 3415 * 3416 * NOTE: It Just Happens to line up with the default 3417 * RSS allocation method. 3418 */ 3419 3420 /* Warning FM follows */ 3421 reta = 0; 3422 for (i = 0; i < 128; i++) { 3423 #ifdef RSS 3424 queue_id = rss_get_indirection_to_bucket(i); 3425 /* 3426 * If we have more queues than buckets, we'll 3427 * end up mapping buckets to a subset of the 3428 * queues. 3429 * 3430 * If we have more buckets than queues, we'll 3431 * end up instead assigning multiple buckets 3432 * to queues. 3433 * 3434 * Both are suboptimal, but we need to handle 3435 * the case so we don't go out of bounds 3436 * indexing arrays and such. 3437 */ 3438 queue_id = queue_id % sc->rx_num_queues; 3439 #else 3440 queue_id = (i % sc->rx_num_queues); 3441 #endif 3442 /* Adjust if required */ 3443 queue_id = queue_id << shift; 3444 3445 /* 3446 * The low 8 bits are for hash value (n+0); 3447 * The next 8 bits are for hash value (n+1), etc. 3448 */ 3449 reta = reta >> 8; 3450 reta = reta | ( ((uint32_t) queue_id) << 24); 3451 if ((i & 3) == 3) { 3452 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3453 reta = 0; 3454 } 3455 } 3456 3457 /* Now fill in hash table */ 3458 3459 /* 3460 * MRQC: Multiple Receive Queues Command 3461 * Set queuing to RSS control, number depends on the device. 3462 */ 3463 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3464 3465 /* XXX ew typecasting */ 3466 rss_getkey((uint8_t *) &rss_key); 3467 for (i = 0; i < 10; i++) 3468 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3469 3470 /* 3471 * Configure the RSS fields to hash upon. 3472 */ 3473 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3474 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3475 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3476 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3477 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3478 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3479 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3480 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3481 3482 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3483 } 3484 3485 /********************************************************************* 3486 * 3487 * Setup networking device structure and register interface media. 3488 * 3489 **********************************************************************/ 3490 static int 3491 em_setup_interface(if_ctx_t ctx) 3492 { 3493 if_t ifp = iflib_get_ifp(ctx); 3494 struct e1000_softc *sc = iflib_get_softc(ctx); 3495 if_softc_ctx_t scctx = sc->shared; 3496 3497 INIT_DEBUGOUT("em_setup_interface: begin"); 3498 3499 /* Single Queue */ 3500 if (sc->tx_num_queues == 1) { 3501 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3502 if_setsendqready(ifp); 3503 } 3504 3505 /* 3506 * Specify the media types supported by this adapter and register 3507 * callbacks to update media and link information 3508 */ 3509 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3510 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3511 u_char fiber_type = IFM_1000_SX; /* default type */ 3512 3513 if (sc->hw.mac.type == e1000_82545) 3514 fiber_type = IFM_1000_LX; 3515 ifmedia_add(sc->media, 3516 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3517 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3518 } else { 3519 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3520 ifmedia_add(sc->media, 3521 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3522 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3523 ifmedia_add(sc->media, 3524 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3525 if (sc->hw.phy.type != e1000_phy_ife) { 3526 ifmedia_add(sc->media, 3527 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3528 ifmedia_add(sc->media, 3529 IFM_ETHER | IFM_1000_T, 0, NULL); 3530 } 3531 } 3532 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3533 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3534 return (0); 3535 } 3536 3537 static int 3538 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3539 int ntxqs, int ntxqsets) 3540 { 3541 struct e1000_softc *sc = iflib_get_softc(ctx); 3542 if_softc_ctx_t scctx = sc->shared; 3543 int error = E1000_SUCCESS; 3544 struct em_tx_queue *que; 3545 int i, j; 3546 3547 MPASS(sc->tx_num_queues > 0); 3548 MPASS(sc->tx_num_queues == ntxqsets); 3549 3550 /* First allocate the top level queue structs */ 3551 if (!(sc->tx_queues = 3552 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3553 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3554 device_printf(iflib_get_dev(ctx), 3555 "Unable to allocate queue memory\n"); 3556 return(ENOMEM); 3557 } 3558 3559 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3560 /* Set up some basics */ 3561 3562 struct tx_ring *txr = &que->txr; 3563 KASSERT(__is_aligned(&txr->tx_aim_snapshot, sizeof(uint64_t)), 3564 ("%s: misaligned TX AIM snapshot %p", __func__, 3565 &txr->tx_aim_snapshot)); 3566 txr->sc = que->sc = sc; 3567 que->me = txr->me = i; 3568 3569 /* Allocate report status array */ 3570 if (!(txr->tx_rsq = 3571 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3572 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3573 device_printf(iflib_get_dev(ctx), 3574 "failed to allocate rs_idxs memory\n"); 3575 error = ENOMEM; 3576 goto fail; 3577 } 3578 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3579 txr->tx_rsq[j] = QIDX_INVALID; 3580 /* get the virtual and physical address of hardware queues */ 3581 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3582 txr->tx_paddr = paddrs[i*ntxqs]; 3583 } 3584 3585 if (bootverbose) 3586 device_printf(iflib_get_dev(ctx), 3587 "allocated for %d tx_queues\n", sc->tx_num_queues); 3588 return (0); 3589 fail: 3590 em_if_queues_free(ctx); 3591 return (error); 3592 } 3593 3594 static int 3595 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3596 int nrxqs, int nrxqsets) 3597 { 3598 struct e1000_softc *sc = iflib_get_softc(ctx); 3599 int error = E1000_SUCCESS; 3600 struct em_rx_queue *que; 3601 int i; 3602 3603 MPASS(sc->rx_num_queues > 0); 3604 MPASS(sc->rx_num_queues == nrxqsets); 3605 3606 /* First allocate the top level queue structs */ 3607 if (!(sc->rx_queues = 3608 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3609 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3610 device_printf(iflib_get_dev(ctx), 3611 "Unable to allocate queue memory\n"); 3612 error = ENOMEM; 3613 goto fail; 3614 } 3615 3616 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3617 /* Set up some basics */ 3618 struct rx_ring *rxr = &que->rxr; 3619 KASSERT(__is_aligned(&rxr->rx_aim_snapshot, sizeof(uint64_t)), 3620 ("%s: misaligned RX AIM snapshot %p", __func__, 3621 &rxr->rx_aim_snapshot)); 3622 rxr->sc = que->sc = sc; 3623 rxr->que = que; 3624 que->me = rxr->me = i; 3625 3626 /* get the virtual and physical address of hardware queues */ 3627 rxr->rx_base = 3628 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3629 rxr->rx_paddr = paddrs[i*nrxqs]; 3630 } 3631 3632 if (bootverbose) 3633 device_printf(iflib_get_dev(ctx), 3634 "allocated for %d rx_queues\n", sc->rx_num_queues); 3635 3636 return (0); 3637 fail: 3638 em_if_queues_free(ctx); 3639 return (error); 3640 } 3641 3642 static void 3643 em_if_queues_free(if_ctx_t ctx) 3644 { 3645 struct e1000_softc *sc = iflib_get_softc(ctx); 3646 struct em_tx_queue *tx_que = sc->tx_queues; 3647 struct em_rx_queue *rx_que = sc->rx_queues; 3648 3649 if (tx_que != NULL) { 3650 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3651 struct tx_ring *txr = &tx_que->txr; 3652 if (txr->tx_rsq == NULL) 3653 break; 3654 3655 free(txr->tx_rsq, M_DEVBUF); 3656 txr->tx_rsq = NULL; 3657 } 3658 free(sc->tx_queues, M_DEVBUF); 3659 sc->tx_queues = NULL; 3660 } 3661 3662 if (rx_que != NULL) { 3663 free(sc->rx_queues, M_DEVBUF); 3664 sc->rx_queues = NULL; 3665 } 3666 } 3667 3668 /********************************************************************* 3669 * 3670 * Enable transmit unit. 3671 * 3672 **********************************************************************/ 3673 static void 3674 em_initialize_transmit_unit(if_ctx_t ctx) 3675 { 3676 struct e1000_softc *sc = iflib_get_softc(ctx); 3677 if_softc_ctx_t scctx = sc->shared; 3678 struct em_tx_queue *que; 3679 struct tx_ring *txr; 3680 struct e1000_hw *hw = &sc->hw; 3681 u32 tctl, txdctl = 0, tarc, tipg = 0; 3682 3683 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3684 3685 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3686 u64 bus_addr; 3687 caddr_t offp, endp; 3688 3689 que = &sc->tx_queues[i]; 3690 txr = &que->txr; 3691 bus_addr = txr->tx_paddr; 3692 3693 /* Clear checksum offload context. */ 3694 offp = (caddr_t)txr + offsetof(struct tx_ring, csum_flags); 3695 endp = (caddr_t)(txr + 1); 3696 bzero(offp, endp - offp); 3697 3698 /* Base and Len of TX Ring */ 3699 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3700 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3701 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3702 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3703 /* Init the HEAD/TAIL indices */ 3704 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3705 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3706 3707 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3708 E1000_READ_REG(hw, E1000_TDBAL(i)), 3709 E1000_READ_REG(hw, E1000_TDLEN(i))); 3710 3711 txdctl = 0; /* clear txdctl */ 3712 txdctl |= 0x1f; /* PTHRESH */ 3713 txdctl |= 1 << 8; /* HTHRESH */ 3714 txdctl |= 1 << 16;/* WTHRESH */ 3715 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3716 txdctl |= E1000_TXDCTL_GRAN; 3717 txdctl |= 1 << 25; /* LWTHRESH */ 3718 3719 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3720 } 3721 3722 /* Set the default values for the Tx Inter Packet Gap timer */ 3723 switch (hw->mac.type) { 3724 case e1000_80003es2lan: 3725 tipg = DEFAULT_82543_TIPG_IPGR1; 3726 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3727 E1000_TIPG_IPGR2_SHIFT; 3728 break; 3729 case e1000_82542: 3730 tipg = DEFAULT_82542_TIPG_IPGT; 3731 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3732 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3733 break; 3734 default: 3735 if (hw->phy.media_type == e1000_media_type_fiber || 3736 hw->phy.media_type == e1000_media_type_internal_serdes) 3737 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3738 else 3739 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3740 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3741 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3742 } 3743 3744 if (hw->mac.type < igb_mac_min) { 3745 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3746 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3747 3748 if (sc->tx_int_delay.value > 0) 3749 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3750 } 3751 3752 if (hw->mac.type >= e1000_82540) 3753 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3754 3755 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3756 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3757 tarc |= TARC_SPEED_MODE_BIT; 3758 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3759 } else if (hw->mac.type == e1000_80003es2lan) { 3760 /* errata: program both queues to unweighted RR */ 3761 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3762 tarc |= 1; 3763 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3764 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3765 tarc |= 1; 3766 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3767 } else if (hw->mac.type == e1000_82574) { 3768 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3769 tarc |= TARC_ERRATA_BIT; 3770 if ( sc->tx_num_queues > 1) { 3771 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3772 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3773 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3774 } else 3775 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3776 } 3777 3778 /* Program the Transmit Control Register */ 3779 tctl = E1000_READ_REG(hw, E1000_TCTL); 3780 tctl &= ~E1000_TCTL_CT; 3781 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3782 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3783 3784 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3785 tctl |= E1000_TCTL_MULR; 3786 3787 /* This write will effectively turn on the transmit unit. */ 3788 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3789 3790 /* SPT and KBL errata workarounds */ 3791 if (hw->mac.type == e1000_pch_spt) { 3792 u32 reg; 3793 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3794 reg |= E1000_RCTL_RDMTS_HEX; 3795 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3796 /* i218-i219 Specification Update 1.5.4.5 */ 3797 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3798 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3799 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3800 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3801 } 3802 } 3803 3804 /********************************************************************* 3805 * 3806 * Enable receive unit. 3807 * 3808 **********************************************************************/ 3809 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3810 3811 static void 3812 em_initialize_receive_unit(if_ctx_t ctx) 3813 { 3814 struct e1000_softc *sc = iflib_get_softc(ctx); 3815 if_softc_ctx_t scctx = sc->shared; 3816 if_t ifp = iflib_get_ifp(ctx); 3817 struct e1000_hw *hw = &sc->hw; 3818 struct em_rx_queue *que; 3819 int i; 3820 uint32_t rctl, rxcsum; 3821 3822 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3823 3824 /* 3825 * Make sure receives are disabled while setting 3826 * up the descriptor ring 3827 */ 3828 rctl = E1000_READ_REG(hw, E1000_RCTL); 3829 /* Do not disable if ever enabled on this hardware */ 3830 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3831 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3832 3833 /* Setup the Receive Control Register */ 3834 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3835 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3836 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3837 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3838 3839 /* Do not store bad packets */ 3840 rctl &= ~E1000_RCTL_SBP; 3841 3842 /* Enable Long Packet receive */ 3843 if (if_getmtu(ifp) > ETHERMTU) 3844 rctl |= E1000_RCTL_LPE; 3845 else 3846 rctl &= ~E1000_RCTL_LPE; 3847 3848 /* Strip the CRC */ 3849 if (!em_disable_crc_stripping) 3850 rctl |= E1000_RCTL_SECRC; 3851 3852 /* lem/em default interrupt moderation */ 3853 if (hw->mac.type < igb_mac_min) { 3854 if (hw->mac.type >= e1000_82540) { 3855 E1000_WRITE_REG(hw, E1000_RADV, 3856 sc->rx_abs_int_delay.value); 3857 3858 /* Set the default interrupt throttling rate */ 3859 E1000_WRITE_REG(hw, E1000_ITR, 3860 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3861 3862 /* 3863 * The 82574 MSI-X EITR registers are programmed 3864 * with the same value further below. Either way 3865 * the hardware now holds the default rate, so seed 3866 * the software copy to match; otherwise a stale 3867 * itr_setting left over from AIM makes em_newitr() 3868 * skip the write that would restore it. 3869 */ 3870 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3871 i++, que++) 3872 que->itr_setting = 3873 EM_INTS_TO_ITR(em_max_interrupt_rate); 3874 } 3875 3876 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3877 * long latencies are observed, like Lenovo X60. This 3878 * change eliminates the problem, but since having positive 3879 * values in RDTR is a known source of problems on other 3880 * platforms another solution is being sought. 3881 */ 3882 if (hw->mac.type == e1000_82573) 3883 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3884 else 3885 E1000_WRITE_REG(hw, E1000_RDTR, 3886 sc->rx_int_delay.value); 3887 } 3888 3889 if (hw->mac.type >= em_mac_min && !sc->vf_ifp) { 3890 uint32_t rfctl; 3891 /* Use extended rx descriptor formats */ 3892 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3893 rfctl |= E1000_RFCTL_EXTEN; 3894 3895 /* 3896 * When using MSI-X interrupts we need to throttle 3897 * using the EITR register (82574 only) 3898 */ 3899 if (hw->mac.type == e1000_82574) { 3900 for (int i = 0; i < 4; i++) 3901 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3902 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3903 /* Disable accelerated acknowledge */ 3904 rfctl |= E1000_RFCTL_ACK_DIS; 3905 } 3906 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3907 } 3908 3909 /* 3910 * Set up L3 and L4 csum Rx descriptor offloads only on Physical 3911 * Functions. Virtual Functions have no access to this register. 3912 */ 3913 if (!sc->vf_ifp) { 3914 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3915 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3916 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3917 if (hw->mac.type > e1000_82575) 3918 rxcsum |= E1000_RXCSUM_CRCOFL; 3919 else if (hw->mac.type < em_mac_min && 3920 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3921 rxcsum |= E1000_RXCSUM_IPV6OFL; 3922 } else { 3923 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3924 if (hw->mac.type > e1000_82575) 3925 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3926 else if (hw->mac.type < em_mac_min) 3927 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3928 } 3929 3930 if (sc->rx_num_queues > 1) { 3931 /* RSS hash needed in the Rx descriptor */ 3932 rxcsum |= E1000_RXCSUM_PCSD; 3933 3934 if (hw->mac.type >= igb_mac_min) 3935 igb_initialize_rss_mapping(sc); 3936 else 3937 em_initialize_rss_mapping(sc); 3938 } 3939 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3940 } 3941 3942 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3943 struct rx_ring *rxr = &que->rxr; 3944 /* Setup the Base and Length of the Rx Descriptor Ring */ 3945 u64 bus_addr = rxr->rx_paddr; 3946 #if 0 3947 u32 rdt = sc->rx_num_queues -1; /* default */ 3948 #endif 3949 3950 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3951 scctx->isc_nrxd[0] * 3952 sizeof(union e1000_rx_desc_extended)); 3953 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3954 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3955 /* Setup the Head and Tail Descriptor Pointers */ 3956 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3957 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3958 } 3959 3960 /* 3961 * Set PTHRESH for improved jumbo performance 3962 * According to 10.2.5.11 of Intel 82574 Datasheet, 3963 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3964 * Only write to RXDCTL(1) if there is a need for different 3965 * settings. 3966 */ 3967 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3968 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3969 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3970 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3971 } else if (hw->mac.type == e1000_82574) { 3972 for (int i = 0; i < sc->rx_num_queues; i++) { 3973 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3974 rxdctl |= 0x20; /* PTHRESH */ 3975 rxdctl |= 4 << 8; /* HTHRESH */ 3976 rxdctl |= 4 << 16;/* WTHRESH */ 3977 rxdctl |= 1 << 24; /* Switch to granularity */ 3978 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3979 } 3980 } else if (hw->mac.type >= igb_mac_min) { 3981 u32 psize, srrctl = 0; 3982 3983 if (if_getmtu(ifp) > ETHERMTU) { 3984 psize = scctx->isc_max_frame_size; 3985 /* are we on a vlan? */ 3986 if (if_vlantrunkinuse(ifp)) 3987 psize += VLAN_TAG_SIZE; 3988 3989 if (sc->vf_ifp) 3990 e1000_rlpml_set_vf(hw, psize); 3991 else 3992 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3993 } 3994 3995 /* Set maximum packet buffer len */ 3996 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3997 E1000_SRRCTL_BSIZEPKT_SHIFT; 3998 3999 /* 4000 * If TX flow control is disabled and there's >1 queue 4001 * defined, enable DROP. 4002 * 4003 * This drops frames rather than hanging the RX MAC for all 4004 * queues. 4005 */ 4006 if ((sc->rx_num_queues > 1) && 4007 (sc->fc == e1000_fc_none || 4008 sc->fc == e1000_fc_rx_pause)) { 4009 srrctl |= E1000_SRRCTL_DROP_EN; 4010 } 4011 /* Setup the Base and Length of the Rx Descriptor Rings */ 4012 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 4013 i++, que++) { 4014 struct rx_ring *rxr = &que->rxr; 4015 u64 bus_addr = rxr->rx_paddr; 4016 u32 rxdctl; 4017 4018 #ifdef notyet 4019 /* Configure for header split? -- ignore for now */ 4020 rxr->hdr_split = igb_header_split; 4021 #else 4022 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4023 #endif 4024 4025 E1000_WRITE_REG(hw, E1000_RDLEN(i), 4026 scctx->isc_nrxd[0] * 4027 sizeof(struct e1000_rx_desc)); 4028 E1000_WRITE_REG(hw, E1000_RDBAH(i), 4029 (uint32_t)(bus_addr >> 32)); 4030 E1000_WRITE_REG(hw, E1000_RDBAL(i), 4031 (uint32_t)bus_addr); 4032 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 4033 /* Enable this Queue */ 4034 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 4035 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4036 rxdctl &= 0xFFF00000; 4037 rxdctl |= IGB_RX_PTHRESH; 4038 rxdctl |= IGB_RX_HTHRESH << 8; 4039 rxdctl |= IGB_RX_WTHRESH << 16; 4040 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 4041 } 4042 } else if (hw->mac.type >= e1000_pch2lan) { 4043 if (if_getmtu(ifp) > ETHERMTU) 4044 e1000_lv_jumbo_workaround_ich8lan(hw, true); 4045 else 4046 e1000_lv_jumbo_workaround_ich8lan(hw, false); 4047 } 4048 4049 /* Make sure VLAN Filters are off */ 4050 rctl &= ~E1000_RCTL_VFE; 4051 4052 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 4053 if (hw->mac.type < igb_mac_min) { 4054 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 4055 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 4056 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 4057 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 4058 else if (sc->rx_mbuf_sz > 8192) 4059 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 4060 else { 4061 rctl |= E1000_RCTL_SZ_2048; 4062 rctl &= ~E1000_RCTL_BSEX; 4063 } 4064 } else 4065 rctl |= E1000_RCTL_SZ_2048; 4066 4067 /* 4068 * rctl bits 11:10 are as follows 4069 * lem: reserved 4070 * em: DTYPE 4071 * igb: reserved 4072 * and should be 00 on all of the above 4073 */ 4074 rctl &= ~0x00000C00; 4075 4076 /* Write out the settings */ 4077 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4078 4079 return; 4080 } 4081 4082 static void 4083 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 4084 { 4085 struct e1000_softc *sc = iflib_get_softc(ctx); 4086 u32 index, bit; 4087 4088 index = (vtag >> 5) & 0x7F; 4089 bit = vtag & 0x1F; 4090 sc->shadow_vfta[index] |= (1 << bit); 4091 ++sc->num_vlans; 4092 if (!sc->vf_ifp) 4093 em_if_vlan_filter_write(sc); 4094 else 4095 /* 4096 * Physical funtion may reject registering VLAN 4097 * but we have no way to inform the stack 4098 * about that. 4099 */ 4100 e1000_vfta_set_vf(&sc->hw, vtag, true); 4101 } 4102 4103 static void 4104 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4105 { 4106 struct e1000_softc *sc = iflib_get_softc(ctx); 4107 u32 index, bit; 4108 4109 index = (vtag >> 5) & 0x7F; 4110 bit = vtag & 0x1F; 4111 sc->shadow_vfta[index] &= ~(1 << bit); 4112 --sc->num_vlans; 4113 if (!sc->vf_ifp) 4114 em_if_vlan_filter_write(sc); 4115 else 4116 e1000_vfta_set_vf(&sc->hw, vtag, false); 4117 } 4118 4119 static bool 4120 em_if_vlan_filter_capable(if_ctx_t ctx) 4121 { 4122 if_t ifp = iflib_get_ifp(ctx); 4123 4124 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4125 !em_disable_crc_stripping) 4126 return (true); 4127 4128 return (false); 4129 } 4130 4131 static bool 4132 em_if_vlan_filter_used(if_ctx_t ctx) 4133 { 4134 struct e1000_softc *sc = iflib_get_softc(ctx); 4135 4136 if (!em_if_vlan_filter_capable(ctx)) 4137 return (false); 4138 4139 for (int i = 0; i < EM_VFTA_SIZE; i++) 4140 if (sc->shadow_vfta[i] != 0) 4141 return (true); 4142 4143 return (false); 4144 } 4145 4146 static void 4147 em_if_vlan_filter_enable(struct e1000_softc *sc) 4148 { 4149 struct e1000_hw *hw = &sc->hw; 4150 u32 reg; 4151 4152 reg = E1000_READ_REG(hw, E1000_RCTL); 4153 reg &= ~E1000_RCTL_CFIEN; 4154 reg |= E1000_RCTL_VFE; 4155 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4156 } 4157 4158 static void 4159 em_if_vlan_filter_disable(struct e1000_softc *sc) 4160 { 4161 struct e1000_hw *hw = &sc->hw; 4162 u32 reg; 4163 4164 reg = E1000_READ_REG(hw, E1000_RCTL); 4165 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4166 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4167 } 4168 4169 static void 4170 em_if_vlan_filter_write(struct e1000_softc *sc) 4171 { 4172 struct e1000_hw *hw = &sc->hw; 4173 4174 KASSERT(!sc->vf_ifp, ("VLAN filter write on VF\n")); 4175 4176 /* Disable interrupts for lem(4) devices during the filter change */ 4177 if (hw->mac.type < em_mac_min) 4178 em_if_intr_disable(sc->ctx); 4179 4180 for (int i = 0; i < EM_VFTA_SIZE; i++) 4181 if (sc->shadow_vfta[i] != 0) 4182 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4183 4184 /* Re-enable interrupts for lem-class devices */ 4185 if (hw->mac.type < em_mac_min) 4186 em_if_intr_enable(sc->ctx); 4187 } 4188 4189 static void 4190 em_setup_vlan_hw_support(if_ctx_t ctx) 4191 { 4192 struct e1000_softc *sc = iflib_get_softc(ctx); 4193 struct e1000_hw *hw = &sc->hw; 4194 if_t ifp = iflib_get_ifp(ctx); 4195 u32 reg; 4196 4197 /* 4198 * Only PFs have control over VLAN HW filtering 4199 * configuration. VFs have to act as if it's always 4200 * enabled. 4201 */ 4202 if (sc->vf_ifp) 4203 return; 4204 4205 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4206 !em_disable_crc_stripping) { 4207 reg = E1000_READ_REG(hw, E1000_CTRL); 4208 reg |= E1000_CTRL_VME; 4209 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4210 } else { 4211 reg = E1000_READ_REG(hw, E1000_CTRL); 4212 reg &= ~E1000_CTRL_VME; 4213 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4214 } 4215 4216 /* If we aren't doing HW filtering, we're done */ 4217 if (!em_if_vlan_filter_capable(ctx)) { 4218 em_if_vlan_filter_disable(sc); 4219 return; 4220 } 4221 4222 /* 4223 * A soft reset zero's out the VFTA, so 4224 * we need to repopulate it now. 4225 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4226 * traffic through. This will write the entire table. 4227 */ 4228 em_if_vlan_register(ctx, 0); 4229 4230 /* Enable the Filter Table */ 4231 em_if_vlan_filter_enable(sc); 4232 } 4233 4234 static void 4235 em_if_intr_enable(if_ctx_t ctx) 4236 { 4237 struct e1000_softc *sc = iflib_get_softc(ctx); 4238 struct e1000_hw *hw = &sc->hw; 4239 u32 ims_mask = IMS_ENABLE_MASK; 4240 4241 if (sc->intr_type == IFLIB_INTR_MSIX) { 4242 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4243 ims_mask |= sc->ims; 4244 } 4245 4246 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4247 E1000_WRITE_FLUSH(hw); 4248 } 4249 4250 static void 4251 em_if_intr_disable(if_ctx_t ctx) 4252 { 4253 struct e1000_softc *sc = iflib_get_softc(ctx); 4254 struct e1000_hw *hw = &sc->hw; 4255 4256 if (sc->intr_type == IFLIB_INTR_MSIX) 4257 E1000_WRITE_REG(hw, EM_EIAC, 0); 4258 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4259 E1000_WRITE_FLUSH(hw); 4260 } 4261 4262 static void 4263 igb_if_intr_enable(if_ctx_t ctx) 4264 { 4265 struct e1000_softc *sc = iflib_get_softc(ctx); 4266 struct e1000_hw *hw = &sc->hw; 4267 u32 mask; 4268 4269 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4270 mask = (sc->que_mask | sc->link_mask); 4271 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4272 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4273 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4274 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4275 } else 4276 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4277 E1000_WRITE_FLUSH(hw); 4278 } 4279 4280 static void 4281 igb_if_intr_disable(if_ctx_t ctx) 4282 { 4283 struct e1000_softc *sc = iflib_get_softc(ctx); 4284 struct e1000_hw *hw = &sc->hw; 4285 4286 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4287 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4288 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4289 } 4290 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4291 E1000_WRITE_FLUSH(hw); 4292 } 4293 4294 /* 4295 * Bit of a misnomer, what this really means is 4296 * to enable OS management of the system... aka 4297 * to disable special hardware management features 4298 */ 4299 static void 4300 em_init_manageability(struct e1000_softc *sc) 4301 { 4302 /* A shared code workaround */ 4303 #define E1000_82542_MANC2H E1000_MANC2H 4304 if (sc->has_manage) { 4305 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4306 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4307 4308 /* disable hardware interception of ARP */ 4309 manc &= ~(E1000_MANC_ARP_EN); 4310 4311 /* enable receiving management packets to the host */ 4312 manc |= E1000_MANC_EN_MNG2HOST; 4313 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4314 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4315 manc2h |= E1000_MNG2HOST_PORT_623; 4316 manc2h |= E1000_MNG2HOST_PORT_664; 4317 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4318 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4319 } 4320 } 4321 4322 /* 4323 * Give control back to hardware management 4324 * controller if there is one. 4325 */ 4326 static void 4327 em_release_manageability(struct e1000_softc *sc) 4328 { 4329 if (sc->has_manage) { 4330 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4331 4332 /* re-enable hardware interception of ARP */ 4333 manc |= E1000_MANC_ARP_EN; 4334 manc &= ~E1000_MANC_EN_MNG2HOST; 4335 4336 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4337 } 4338 } 4339 4340 /* 4341 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4342 * For ASF and Pass Through versions of f/w this means 4343 * that the driver is loaded. For AMT version type f/w 4344 * this means that the network i/f is open. 4345 */ 4346 static void 4347 em_get_hw_control(struct e1000_softc *sc) 4348 { 4349 u32 ctrl_ext, swsm; 4350 4351 if (sc->vf_ifp) 4352 return; 4353 4354 if (sc->hw.mac.type == e1000_82573) { 4355 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4356 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4357 swsm | E1000_SWSM_DRV_LOAD); 4358 return; 4359 } 4360 /* else */ 4361 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4362 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4363 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4364 } 4365 4366 /* 4367 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4368 * For ASF and Pass Through versions of f/w this means that 4369 * the driver is no longer loaded. For AMT versions of the 4370 * f/w this means that the network i/f is closed. 4371 */ 4372 static void 4373 em_release_hw_control(struct e1000_softc *sc) 4374 { 4375 u32 ctrl_ext, swsm; 4376 4377 if (!sc->has_manage) 4378 return; 4379 4380 if (sc->hw.mac.type == e1000_82573) { 4381 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4382 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4383 swsm & ~E1000_SWSM_DRV_LOAD); 4384 return; 4385 } 4386 /* else */ 4387 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4388 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4389 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4390 return; 4391 } 4392 4393 static int 4394 em_is_valid_ether_addr(u8 *addr) 4395 { 4396 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4397 4398 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4399 return (false); 4400 } 4401 4402 return (true); 4403 } 4404 4405 static bool 4406 em_automask_tso(if_ctx_t ctx) 4407 { 4408 struct e1000_softc *sc = iflib_get_softc(ctx); 4409 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4410 if_t ifp = iflib_get_ifp(ctx); 4411 bool reset_needed; 4412 int drvflags; 4413 4414 if (!em_unsupported_tso && sc->link_speed && 4415 sc->link_speed != SPEED_1000 && 4416 scctx->isc_capenable & IFCAP_TSO) { 4417 device_printf(sc->dev, 4418 "Disabling TSO for 10/100 Ethernet.\n"); 4419 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4420 scctx->isc_capenable &= ~IFCAP_TSO; 4421 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4422 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4423 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4424 scctx->isc_capenable |= sc->tso_automasked; 4425 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4426 sc->tso_automasked = 0; 4427 } else { 4428 return (false); 4429 } 4430 4431 /* 4432 * Reset a running interface, or one being initialized while 4433 * administratively up. OACTIVE remains set after iflib_stop(), so 4434 * it alone cannot distinguish initialization from an interface that 4435 * is down. In other states, the next initialization will apply the 4436 * updated capabilities. 4437 */ 4438 drvflags = if_getdrvflags(ifp); 4439 reset_needed = (drvflags & IFF_DRV_RUNNING) != 0 || 4440 ((drvflags & IFF_DRV_OACTIVE) != 0 && 4441 (if_getflags(ifp) & IFF_UP) != 0); 4442 if (!reset_needed) 4443 return (false); 4444 4445 /* iflib_init_locked handles ifnet hwassistbits */ 4446 iflib_request_reset(ctx); 4447 return (true); 4448 } 4449 4450 /* 4451 ** Parse the interface capabilities with regard 4452 ** to both system management and wake-on-lan for 4453 ** later use. 4454 */ 4455 static void 4456 em_get_wakeup(if_ctx_t ctx) 4457 { 4458 struct e1000_softc *sc = iflib_get_softc(ctx); 4459 device_t dev = iflib_get_dev(ctx); 4460 u16 eeprom_data = 0, device_id, apme_mask; 4461 4462 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4463 apme_mask = EM_EEPROM_APME; 4464 4465 switch (sc->hw.mac.type) { 4466 case e1000_82542: 4467 case e1000_82543: 4468 case e1000_vfadapt: 4469 case e1000_vfadapt_i350: 4470 break; 4471 case e1000_82544: 4472 e1000_read_nvm(&sc->hw, 4473 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4474 apme_mask = EM_82544_APME; 4475 break; 4476 case e1000_82546: 4477 case e1000_82546_rev_3: 4478 if (sc->hw.bus.func == 1) { 4479 e1000_read_nvm(&sc->hw, 4480 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4481 break; 4482 } else 4483 e1000_read_nvm(&sc->hw, 4484 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4485 break; 4486 case e1000_82573: 4487 case e1000_82583: 4488 sc->has_amt = true; 4489 /* FALLTHROUGH */ 4490 case e1000_82571: 4491 case e1000_82572: 4492 case e1000_80003es2lan: 4493 if (sc->hw.bus.func == 1) { 4494 e1000_read_nvm(&sc->hw, 4495 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4496 break; 4497 } else 4498 e1000_read_nvm(&sc->hw, 4499 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4500 break; 4501 case e1000_ich8lan: 4502 case e1000_ich9lan: 4503 case e1000_ich10lan: 4504 case e1000_pchlan: 4505 case e1000_pch2lan: 4506 case e1000_pch_lpt: 4507 case e1000_pch_spt: 4508 case e1000_82575: /* listing all igb devices */ 4509 case e1000_82576: 4510 case e1000_82580: 4511 case e1000_i350: 4512 case e1000_i354: 4513 case e1000_i210: 4514 case e1000_i211: 4515 apme_mask = E1000_WUC_APME; 4516 sc->has_amt = true; 4517 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4518 break; 4519 default: 4520 e1000_read_nvm(&sc->hw, 4521 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4522 break; 4523 } 4524 if (eeprom_data & apme_mask) 4525 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4526 /* 4527 * We have the eeprom settings, now apply the special cases 4528 * where the eeprom may be wrong or the board won't support 4529 * wake on lan on a particular port 4530 */ 4531 device_id = pci_get_device(dev); 4532 switch (device_id) { 4533 case E1000_DEV_ID_82546GB_PCIE: 4534 sc->wol = 0; 4535 break; 4536 case E1000_DEV_ID_82546EB_FIBER: 4537 case E1000_DEV_ID_82546GB_FIBER: 4538 /* Wake events only supported on port A for dual fiber 4539 * regardless of eeprom setting */ 4540 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4541 E1000_STATUS_FUNC_1) 4542 sc->wol = 0; 4543 break; 4544 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4545 /* if quad port adapter, disable WoL on all but port A */ 4546 if (global_quad_port_a != 0) 4547 sc->wol = 0; 4548 /* Reset for multiple quad port adapters */ 4549 if (++global_quad_port_a == 4) 4550 global_quad_port_a = 0; 4551 break; 4552 case E1000_DEV_ID_82571EB_FIBER: 4553 /* Wake events only supported on port A for dual fiber 4554 * regardless of eeprom setting */ 4555 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4556 E1000_STATUS_FUNC_1) 4557 sc->wol = 0; 4558 break; 4559 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4560 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4561 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4562 /* if quad port adapter, disable WoL on all but port A */ 4563 if (global_quad_port_a != 0) 4564 sc->wol = 0; 4565 /* Reset for multiple quad port adapters */ 4566 if (++global_quad_port_a == 4) 4567 global_quad_port_a = 0; 4568 break; 4569 } 4570 } 4571 4572 4573 /* 4574 * Enable PCI Wake On Lan capability 4575 */ 4576 static void 4577 em_enable_wakeup(if_ctx_t ctx) 4578 { 4579 struct e1000_softc *sc = iflib_get_softc(ctx); 4580 device_t dev = iflib_get_dev(ctx); 4581 if_t ifp = iflib_get_ifp(ctx); 4582 int error = 0; 4583 u32 ctrl, ctrl_ext, rctl; 4584 4585 if (!pci_has_pm(dev)) 4586 return; 4587 4588 /* 4589 * Determine type of Wakeup: note that wol 4590 * is set with all bits on by default. 4591 */ 4592 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4593 sc->wol &= ~E1000_WUFC_MAG; 4594 4595 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4596 sc->wol &= ~E1000_WUFC_EX; 4597 4598 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4599 sc->wol &= ~E1000_WUFC_MC; 4600 else { 4601 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4602 rctl |= E1000_RCTL_MPE; 4603 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4604 } 4605 4606 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4607 goto pme; 4608 4609 /* Advertise the wakeup capability */ 4610 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4611 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4612 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4613 4614 /* Keep the laser running on Fiber adapters */ 4615 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4616 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4617 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4618 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4619 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4620 } 4621 4622 if ((sc->hw.mac.type == e1000_ich8lan) || 4623 (sc->hw.mac.type == e1000_pchlan) || 4624 (sc->hw.mac.type == e1000_ich9lan) || 4625 (sc->hw.mac.type == e1000_ich10lan)) 4626 e1000_suspend_workarounds_ich8lan(&sc->hw); 4627 4628 if ( sc->hw.mac.type >= e1000_pchlan) { 4629 error = em_enable_phy_wakeup(sc); 4630 if (error) 4631 goto pme; 4632 } else { 4633 /* Enable wakeup by the MAC */ 4634 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4635 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4636 } 4637 4638 if (sc->hw.phy.type == e1000_phy_igp_3) 4639 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4640 4641 pme: 4642 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4643 pci_enable_pme(dev); 4644 4645 return; 4646 } 4647 4648 /* 4649 * WOL in the newer chipset interfaces (pchlan) 4650 * require thing to be copied into the phy 4651 */ 4652 static int 4653 em_enable_phy_wakeup(struct e1000_softc *sc) 4654 { 4655 struct e1000_hw *hw = &sc->hw; 4656 u32 mreg, ret = 0; 4657 u16 preg; 4658 4659 /* copy MAC RARs to PHY RARs */ 4660 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4661 4662 /* copy MAC MTA to PHY MTA */ 4663 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4664 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4665 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4666 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4667 (u16)((mreg >> 16) & 0xFFFF)); 4668 } 4669 4670 /* configure PHY Rx Control register */ 4671 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4672 mreg = E1000_READ_REG(hw, E1000_RCTL); 4673 if (mreg & E1000_RCTL_UPE) 4674 preg |= BM_RCTL_UPE; 4675 if (mreg & E1000_RCTL_MPE) 4676 preg |= BM_RCTL_MPE; 4677 preg &= ~(BM_RCTL_MO_MASK); 4678 if (mreg & E1000_RCTL_MO_3) 4679 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4680 << BM_RCTL_MO_SHIFT); 4681 if (mreg & E1000_RCTL_BAM) 4682 preg |= BM_RCTL_BAM; 4683 if (mreg & E1000_RCTL_PMCF) 4684 preg |= BM_RCTL_PMCF; 4685 mreg = E1000_READ_REG(hw, E1000_CTRL); 4686 if (mreg & E1000_CTRL_RFCE) 4687 preg |= BM_RCTL_RFCE; 4688 e1000_write_phy_reg(hw, BM_RCTL, preg); 4689 4690 /* enable PHY wakeup in MAC register */ 4691 E1000_WRITE_REG(hw, E1000_WUC, 4692 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4693 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4694 4695 /* configure and enable PHY wakeup in PHY registers */ 4696 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4697 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4698 4699 /* activate PHY wakeup */ 4700 ret = hw->phy.ops.acquire(hw); 4701 if (ret) { 4702 printf("Could not acquire PHY\n"); 4703 return ret; 4704 } 4705 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4706 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4707 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4708 if (ret) { 4709 printf("Could not read PHY page 769\n"); 4710 goto out; 4711 } 4712 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4713 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4714 if (ret) 4715 printf("Could not set PHY Host Wakeup bit\n"); 4716 out: 4717 hw->phy.ops.release(hw); 4718 4719 return ret; 4720 } 4721 4722 static void 4723 em_if_led_func(if_ctx_t ctx, int onoff) 4724 { 4725 struct e1000_softc *sc = iflib_get_softc(ctx); 4726 4727 if (onoff) { 4728 e1000_setup_led(&sc->hw); 4729 e1000_led_on(&sc->hw); 4730 } else { 4731 e1000_led_off(&sc->hw); 4732 e1000_cleanup_led(&sc->hw); 4733 } 4734 } 4735 4736 /* 4737 * Disable the L0S and L1 LINK states 4738 */ 4739 static void 4740 em_disable_aspm(struct e1000_softc *sc) 4741 { 4742 int base, reg; 4743 u16 link_cap,link_ctrl; 4744 device_t dev = sc->dev; 4745 4746 switch (sc->hw.mac.type) { 4747 case e1000_82573: 4748 case e1000_82574: 4749 case e1000_82583: 4750 break; 4751 default: 4752 return; 4753 } 4754 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4755 return; 4756 reg = base + PCIER_LINK_CAP; 4757 link_cap = pci_read_config(dev, reg, 2); 4758 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4759 return; 4760 reg = base + PCIER_LINK_CTL; 4761 link_ctrl = pci_read_config(dev, reg, 2); 4762 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4763 pci_write_config(dev, reg, link_ctrl, 2); 4764 return; 4765 } 4766 4767 /********************************************************************** 4768 * 4769 * Update the board statistics counters. 4770 * 4771 **********************************************************************/ 4772 static void 4773 em_update_stats_counters(struct e1000_softc *sc) 4774 { 4775 struct e1000_hw_stats *stats; 4776 u64 prev_xoffrxc; 4777 4778 if (sc->vf_ifp) { 4779 em_update_vf_stats_counters(sc); 4780 return; 4781 } 4782 4783 stats = &sc->ustats.stats; 4784 prev_xoffrxc = stats->xoffrxc; 4785 4786 if(sc->hw.phy.media_type == e1000_media_type_copper || 4787 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4788 stats->symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4789 stats->sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4790 } 4791 stats->crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4792 stats->mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4793 stats->scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4794 stats->ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4795 4796 stats->mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4797 stats->latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4798 stats->colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4799 stats->dc += E1000_READ_REG(&sc->hw, E1000_DC); 4800 stats->rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4801 stats->xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4802 stats->xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4803 stats->xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4804 /* 4805 ** For watchdog management we need to know if we have been 4806 ** paused during the last interval, so capture that here. 4807 */ 4808 if (stats->xoffrxc != prev_xoffrxc) 4809 sc->shared->isc_pause_frames = 1; 4810 stats->xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4811 stats->fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4812 stats->prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4813 stats->prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4814 stats->prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4815 stats->prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4816 stats->prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4817 stats->prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4818 stats->gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4819 stats->bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4820 stats->mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4821 stats->gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4822 4823 /* For the 64-bit byte counters the low dword must be read first. */ 4824 /* Both registers clear on the read of the high dword */ 4825 4826 stats->gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4827 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4828 stats->gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4829 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4830 4831 stats->rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4832 stats->ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4833 stats->rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4834 stats->roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4835 stats->rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4836 4837 stats->mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4838 stats->mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4839 stats->mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4840 4841 stats->tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4842 stats->tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4843 4844 stats->tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4845 stats->tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4846 stats->ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4847 stats->ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4848 stats->ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4849 stats->ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4850 stats->ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4851 stats->ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4852 stats->mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4853 stats->bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4854 4855 /* Interrupt Counts */ 4856 4857 stats->iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4858 stats->icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4859 stats->icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4860 stats->ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4861 stats->ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4862 stats->ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4863 stats->ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4864 stats->icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4865 stats->icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4866 4867 if (sc->hw.mac.type >= e1000_82543) { 4868 stats->algnerrc += 4869 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4870 stats->rxerrc += 4871 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4872 stats->tncrs += 4873 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4874 stats->cexterr += 4875 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4876 stats->tsctc += 4877 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4878 stats->tsctfc += 4879 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4880 } 4881 } 4882 4883 static void 4884 em_update_vf_stats_counters(struct e1000_softc *sc) 4885 { 4886 struct e1000_vf_stats *stats; 4887 4888 if (sc->link_speed == 0) 4889 return; 4890 4891 stats = &sc->ustats.vf_stats; 4892 4893 UPDATE_VF_REG(E1000_VFGPRC, 4894 stats->last_gprc, stats->gprc); 4895 UPDATE_VF_REG(E1000_VFGORC, 4896 stats->last_gorc, stats->gorc); 4897 UPDATE_VF_REG(E1000_VFGPTC, 4898 stats->last_gptc, stats->gptc); 4899 UPDATE_VF_REG(E1000_VFGOTC, 4900 stats->last_gotc, stats->gotc); 4901 UPDATE_VF_REG(E1000_VFMPRC, 4902 stats->last_mprc, stats->mprc); 4903 } 4904 4905 static uint64_t 4906 em_if_get_vf_counter(if_ctx_t ctx, ift_counter cnt) 4907 { 4908 struct e1000_softc *sc = iflib_get_softc(ctx); 4909 if_t ifp = iflib_get_ifp(ctx); 4910 4911 switch (cnt) { 4912 case IFCOUNTER_IERRORS: 4913 return sc->dropped_pkts; 4914 case IFCOUNTER_OERRORS: 4915 return (if_get_counter_default(ifp, cnt) + 4916 sc->watchdog_events); 4917 default: 4918 return (if_get_counter_default(ifp, cnt)); 4919 } 4920 } 4921 4922 static uint64_t 4923 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4924 { 4925 struct e1000_softc *sc = iflib_get_softc(ctx); 4926 struct e1000_hw_stats *stats; 4927 if_t ifp = iflib_get_ifp(ctx); 4928 4929 if (sc->vf_ifp) 4930 return (em_if_get_vf_counter(ctx, cnt)); 4931 4932 stats = &sc->ustats.stats; 4933 4934 switch (cnt) { 4935 case IFCOUNTER_COLLISIONS: 4936 return (stats->colc); 4937 case IFCOUNTER_IERRORS: 4938 return (sc->dropped_pkts + stats->rxerrc + 4939 stats->crcerrs + stats->algnerrc + 4940 stats->ruc + stats->roc + 4941 stats->mpc + stats->cexterr); 4942 case IFCOUNTER_OERRORS: 4943 return (if_get_counter_default(ifp, cnt) + 4944 stats->ecol + stats->latecol + sc->watchdog_events); 4945 default: 4946 return (if_get_counter_default(ifp, cnt)); 4947 } 4948 } 4949 4950 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4951 * @ctx: iflib context 4952 * @event: event code to check 4953 * 4954 * Defaults to returning false for unknown events. 4955 * 4956 * @returns true if iflib needs to reinit the interface 4957 */ 4958 static bool 4959 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4960 { 4961 switch (event) { 4962 case IFLIB_RESTART_VLAN_CONFIG: 4963 default: 4964 return (false); 4965 } 4966 } 4967 4968 /* Export a single 32-bit register via a read-only sysctl. */ 4969 static int 4970 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4971 { 4972 struct e1000_softc *sc; 4973 u_int val; 4974 4975 sc = oidp->oid_arg1; 4976 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4977 return (sysctl_handle_int(oidp, &val, 0, req)); 4978 } 4979 4980 /* Per queue holdoff interrupt rate handler */ 4981 static int 4982 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4983 { 4984 struct em_rx_queue *rque; 4985 struct em_tx_queue *tque; 4986 struct e1000_hw *hw; 4987 int error; 4988 u32 reg, usec, rate; 4989 4990 bool tx = oidp->oid_arg2; 4991 4992 if (tx) { 4993 tque = oidp->oid_arg1; 4994 hw = &tque->sc->hw; 4995 if (hw->mac.type >= igb_mac_min) 4996 reg = E1000_READ_REG(hw, E1000_EITR(tque->msix)); 4997 else if (hw->mac.type == e1000_82574 && 4998 tque->sc->intr_type == IFLIB_INTR_MSIX) 4999 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->msix)); 5000 else 5001 reg = E1000_READ_REG(hw, E1000_ITR); 5002 } else { 5003 rque = oidp->oid_arg1; 5004 hw = &rque->sc->hw; 5005 if (hw->mac.type >= igb_mac_min) 5006 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 5007 else if (hw->mac.type == e1000_82574 && 5008 rque->sc->intr_type == IFLIB_INTR_MSIX) 5009 reg = E1000_READ_REG(hw, 5010 E1000_EITR_82574(rque->msix)); 5011 else 5012 reg = E1000_READ_REG(hw, E1000_ITR); 5013 } 5014 5015 if (hw->mac.type < igb_mac_min) { 5016 if (reg > 0) 5017 rate = EM_INTS_TO_ITR(reg); 5018 else 5019 rate = 0; 5020 } else { 5021 usec = (reg & IGB_QVECTOR_MASK); 5022 if (usec > 0) 5023 rate = IGB_EITR_TO_INTS(usec); 5024 else 5025 rate = 0; 5026 } 5027 5028 error = sysctl_handle_int(oidp, &rate, 0, req); 5029 if (error || !req->newptr) 5030 return error; 5031 return 0; 5032 } 5033 5034 /* 5035 * Add sysctl variables, one per statistic, to the system. 5036 */ 5037 static void 5038 em_add_hw_stats(struct e1000_softc *sc) 5039 { 5040 device_t dev = iflib_get_dev(sc->ctx); 5041 struct em_tx_queue *tx_que = sc->tx_queues; 5042 struct em_rx_queue *rx_que = sc->rx_queues; 5043 5044 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 5045 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 5046 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 5047 struct e1000_hw_stats *stats; 5048 5049 struct sysctl_oid *stat_node, *queue_node, *int_node; 5050 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 5051 5052 #define QUEUE_NAME_LEN 32 5053 char namebuf[QUEUE_NAME_LEN]; 5054 5055 /* Driver Statistics */ 5056 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 5057 CTLFLAG_RD, &sc->dropped_pkts, 5058 "Driver dropped packets"); 5059 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 5060 CTLFLAG_RD, &sc->link_irq, 5061 "Link MSI-X IRQ Handled"); 5062 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 5063 CTLFLAG_RD, &sc->rx_overruns, 5064 "RX overruns"); 5065 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 5066 CTLFLAG_RD, &sc->watchdog_events, 5067 "Watchdog timeouts"); 5068 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 5069 CTLTYPE_UINT | CTLFLAG_RD, 5070 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 5071 "Device Control Register"); 5072 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 5073 CTLTYPE_UINT | CTLFLAG_RD, 5074 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 5075 "Receiver Control Register"); 5076 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 5077 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 5078 "Flow Control High Watermark"); 5079 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 5080 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 5081 "Flow Control Low Watermark"); 5082 5083 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 5084 struct tx_ring *txr = &tx_que->txr; 5085 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 5086 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 5087 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 5088 queue_list = SYSCTL_CHILDREN(queue_node); 5089 5090 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 5091 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 5092 true, em_sysctl_interrupt_rate_handler, 5093 "IU", "Interrupt Rate"); 5094 5095 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 5096 CTLTYPE_UINT | CTLFLAG_RD, sc, 5097 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 5098 "Transmit Descriptor Head"); 5099 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 5100 CTLTYPE_UINT | CTLFLAG_RD, sc, 5101 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 5102 "Transmit Descriptor Tail"); 5103 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 5104 CTLFLAG_RD, &txr->tx_irq, 5105 "Queue MSI-X Transmit Interrupts"); 5106 } 5107 5108 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 5109 struct rx_ring *rxr = &rx_que->rxr; 5110 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 5111 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 5112 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 5113 queue_list = SYSCTL_CHILDREN(queue_node); 5114 5115 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 5116 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 5117 false, em_sysctl_interrupt_rate_handler, 5118 "IU", "Interrupt Rate"); 5119 5120 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 5121 CTLTYPE_UINT | CTLFLAG_RD, sc, 5122 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 5123 "Receive Descriptor Head"); 5124 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 5125 CTLTYPE_UINT | CTLFLAG_RD, sc, 5126 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 5127 "Receive Descriptor Tail"); 5128 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 5129 CTLFLAG_RD, &rxr->rx_irq, 5130 "Queue MSI-X Receive Interrupts"); 5131 } 5132 5133 /* MAC stats get their own sub node */ 5134 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 5135 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 5136 stat_list = SYSCTL_CHILDREN(stat_node); 5137 5138 /* 5139 ** VF adapter has a very limited set of stats 5140 ** since its not managing the metal, so to speak. 5141 */ 5142 if (sc->vf_ifp) { 5143 struct e1000_vf_stats *vfstats = &sc->ustats.vf_stats; 5144 5145 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5146 CTLFLAG_RD, &vfstats->gprc, 5147 "Good Packets Received"); 5148 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5149 CTLFLAG_RD, &vfstats->gptc, 5150 "Good Packets Transmitted"); 5151 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5152 CTLFLAG_RD, &vfstats->gorc, 5153 "Good Octets Received"); 5154 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5155 CTLFLAG_RD, &vfstats->gotc, 5156 "Good Octets Transmitted"); 5157 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5158 CTLFLAG_RD, &vfstats->mprc, 5159 "Multicast Packets Received"); 5160 return; 5161 } 5162 5163 stats = &sc->ustats.stats; 5164 5165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 5166 CTLFLAG_RD, &stats->ecol, 5167 "Excessive collisions"); 5168 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 5169 CTLFLAG_RD, &stats->scc, 5170 "Single collisions"); 5171 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 5172 CTLFLAG_RD, &stats->mcc, 5173 "Multiple collisions"); 5174 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 5175 CTLFLAG_RD, &stats->latecol, 5176 "Late collisions"); 5177 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 5178 CTLFLAG_RD, &stats->colc, 5179 "Collision Count"); 5180 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 5181 CTLFLAG_RD, &stats->symerrs, 5182 "Symbol Errors"); 5183 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 5184 CTLFLAG_RD, &stats->sec, 5185 "Sequence Errors"); 5186 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5187 CTLFLAG_RD, &stats->dc, 5188 "Defer Count"); 5189 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5190 CTLFLAG_RD, &stats->mpc, 5191 "Missed Packets"); 5192 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5193 CTLFLAG_RD, &stats->rlec, 5194 "Receive Length Errors"); 5195 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5196 CTLFLAG_RD, &stats->rnbc, 5197 "Receive No Buffers"); 5198 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5199 CTLFLAG_RD, &stats->ruc, 5200 "Receive Undersize"); 5201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5202 CTLFLAG_RD, &stats->rfc, 5203 "Fragmented Packets Received "); 5204 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5205 CTLFLAG_RD, &stats->roc, 5206 "Oversized Packets Received"); 5207 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5208 CTLFLAG_RD, &stats->rjc, 5209 "Recevied Jabber"); 5210 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5211 CTLFLAG_RD, &stats->rxerrc, 5212 "Receive Errors"); 5213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5214 CTLFLAG_RD, &stats->crcerrs, 5215 "CRC errors"); 5216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5217 CTLFLAG_RD, &stats->algnerrc, 5218 "Alignment Errors"); 5219 /* On 82575 these are collision counts */ 5220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5221 CTLFLAG_RD, &stats->cexterr, 5222 "Collision/Carrier extension errors"); 5223 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5224 CTLFLAG_RD, &stats->xonrxc, 5225 "XON Received"); 5226 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5227 CTLFLAG_RD, &stats->xontxc, 5228 "XON Transmitted"); 5229 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5230 CTLFLAG_RD, &stats->xoffrxc, 5231 "XOFF Received"); 5232 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5233 CTLFLAG_RD, &stats->xofftxc, 5234 "XOFF Transmitted"); 5235 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5236 CTLFLAG_RD, &stats->fcruc, 5237 "Unsupported Flow Control Received"); 5238 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5239 CTLFLAG_RD, &stats->mgprc, 5240 "Management Packets Received"); 5241 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5242 CTLFLAG_RD, &stats->mgpdc, 5243 "Management Packets Dropped"); 5244 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5245 CTLFLAG_RD, &stats->mgptc, 5246 "Management Packets Transmitted"); 5247 5248 /* Packet Reception Stats */ 5249 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5250 CTLFLAG_RD, &stats->tpr, 5251 "Total Packets Received "); 5252 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5253 CTLFLAG_RD, &stats->gprc, 5254 "Good Packets Received"); 5255 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5256 CTLFLAG_RD, &stats->bprc, 5257 "Broadcast Packets Received"); 5258 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5259 CTLFLAG_RD, &stats->mprc, 5260 "Multicast Packets Received"); 5261 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5262 CTLFLAG_RD, &stats->prc64, 5263 "64 byte frames received "); 5264 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5265 CTLFLAG_RD, &stats->prc127, 5266 "65-127 byte frames received"); 5267 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5268 CTLFLAG_RD, &stats->prc255, 5269 "128-255 byte frames received"); 5270 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5271 CTLFLAG_RD, &stats->prc511, 5272 "256-511 byte frames received"); 5273 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5274 CTLFLAG_RD, &stats->prc1023, 5275 "512-1023 byte frames received"); 5276 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5277 CTLFLAG_RD, &stats->prc1522, 5278 "1023-1522 byte frames received"); 5279 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5280 CTLFLAG_RD, &stats->gorc, 5281 "Good Octets Received"); 5282 5283 /* Packet Transmission Stats */ 5284 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5285 CTLFLAG_RD, &stats->gotc, 5286 "Good Octets Transmitted"); 5287 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5288 CTLFLAG_RD, &stats->tpt, 5289 "Total Packets Transmitted"); 5290 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5291 CTLFLAG_RD, &stats->gptc, 5292 "Good Packets Transmitted"); 5293 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5294 CTLFLAG_RD, &stats->bptc, 5295 "Broadcast Packets Transmitted"); 5296 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5297 CTLFLAG_RD, &stats->mptc, 5298 "Multicast Packets Transmitted"); 5299 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5300 CTLFLAG_RD, &stats->ptc64, 5301 "64 byte frames transmitted "); 5302 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5303 CTLFLAG_RD, &stats->ptc127, 5304 "65-127 byte frames transmitted"); 5305 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5306 CTLFLAG_RD, &stats->ptc255, 5307 "128-255 byte frames transmitted"); 5308 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5309 CTLFLAG_RD, &stats->ptc511, 5310 "256-511 byte frames transmitted"); 5311 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5312 CTLFLAG_RD, &stats->ptc1023, 5313 "512-1023 byte frames transmitted"); 5314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5315 CTLFLAG_RD, &stats->ptc1522, 5316 "1024-1522 byte frames transmitted"); 5317 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5318 CTLFLAG_RD, &stats->tsctc, 5319 "TSO Contexts Transmitted"); 5320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5321 CTLFLAG_RD, &stats->tsctfc, 5322 "TSO Contexts Failed"); 5323 5324 /* Interrupt Stats */ 5325 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5326 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5327 int_list = SYSCTL_CHILDREN(int_node); 5328 5329 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5330 CTLFLAG_RD, &stats->iac, 5331 "Interrupt Assertion Count"); 5332 5333 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5334 CTLFLAG_RD, &stats->icrxptc, 5335 "Interrupt Cause Rx Pkt Timer Expire Count"); 5336 5337 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5338 CTLFLAG_RD, &stats->icrxatc, 5339 "Interrupt Cause Rx Abs Timer Expire Count"); 5340 5341 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5342 CTLFLAG_RD, &stats->ictxptc, 5343 "Interrupt Cause Tx Pkt Timer Expire Count"); 5344 5345 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5346 CTLFLAG_RD, &stats->ictxatc, 5347 "Interrupt Cause Tx Abs Timer Expire Count"); 5348 5349 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5350 CTLFLAG_RD, &stats->ictxqec, 5351 "Interrupt Cause Tx Queue Empty Count"); 5352 5353 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5354 CTLFLAG_RD, &stats->ictxqmtc, 5355 "Interrupt Cause Tx Queue Min Thresh Count"); 5356 5357 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5358 CTLFLAG_RD, &stats->icrxdmtc, 5359 "Interrupt Cause Rx Desc Min Thresh Count"); 5360 5361 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5362 CTLFLAG_RD, &stats->icrxoc, 5363 "Interrupt Cause Receiver Overrun Count"); 5364 } 5365 5366 static void 5367 em_fw_version_locked(if_ctx_t ctx) 5368 { 5369 struct e1000_softc *sc = iflib_get_softc(ctx); 5370 struct e1000_hw *hw = &sc->hw; 5371 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5372 uint16_t eep = 0; 5373 5374 /* 5375 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5376 * the NVM locking model, so we do it in em_if_attach_pre() and store 5377 * the info in the softc 5378 */ 5379 ASSERT_CTX_LOCK_HELD(hw); 5380 5381 *fw_ver = (struct e1000_fw_version){0}; 5382 5383 if (hw->mac.type >= igb_mac_min) { 5384 /* 5385 * Use the Shared Code for igb(4) 5386 */ 5387 e1000_get_fw_version(hw, fw_ver); 5388 } else { 5389 /* 5390 * Otherwise, EEPROM version should be present on (almost?) 5391 * all devices here 5392 */ 5393 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5394 INIT_DEBUGOUT("can't get EEPROM version"); 5395 return; 5396 } 5397 5398 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5399 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5400 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5401 } 5402 } 5403 5404 static void 5405 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5406 { 5407 const char *space = ""; 5408 5409 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5410 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5411 fw_ver->eep_minor, fw_ver->eep_build); 5412 space = " "; 5413 } 5414 5415 if (fw_ver->invm_major || fw_ver->invm_minor || 5416 fw_ver->invm_img_type) { 5417 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5418 space, fw_ver->invm_major, fw_ver->invm_minor, 5419 fw_ver->invm_img_type); 5420 space = " "; 5421 } 5422 5423 if (fw_ver->or_valid) { 5424 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5425 space, fw_ver->or_major, fw_ver->or_build, 5426 fw_ver->or_patch); 5427 space = " "; 5428 } 5429 5430 if (fw_ver->etrack_id) 5431 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5432 } 5433 5434 static void 5435 em_print_fw_version(struct e1000_softc *sc ) 5436 { 5437 device_t dev = sc->dev; 5438 struct sbuf *buf; 5439 int error = 0; 5440 5441 buf = sbuf_new_auto(); 5442 if (!buf) { 5443 device_printf(dev, "Could not allocate sbuf for output.\n"); 5444 return; 5445 } 5446 5447 em_sbuf_fw_version(&sc->fw_ver, buf); 5448 5449 error = sbuf_finish(buf); 5450 if (error) 5451 device_printf(dev, "Error finishing sbuf: %d\n", error); 5452 else if (sbuf_len(buf)) 5453 device_printf(dev, "%s\n", sbuf_data(buf)); 5454 5455 sbuf_delete(buf); 5456 } 5457 5458 static int 5459 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5460 { 5461 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5462 device_t dev = sc->dev; 5463 struct sbuf *buf; 5464 int error = 0; 5465 5466 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5467 if (!buf) { 5468 device_printf(dev, "Could not allocate sbuf for output.\n"); 5469 return (ENOMEM); 5470 } 5471 5472 em_sbuf_fw_version(&sc->fw_ver, buf); 5473 5474 error = sbuf_finish(buf); 5475 if (error) 5476 device_printf(dev, "Error finishing sbuf: %d\n", error); 5477 5478 sbuf_delete(buf); 5479 5480 return (0); 5481 } 5482 5483 /********************************************************************** 5484 * 5485 * This routine provides a way to dump out the adapter eeprom, 5486 * often a useful debug/service tool. This only dumps the first 5487 * 32 words, stuff that matters is in that extent. 5488 * 5489 **********************************************************************/ 5490 static int 5491 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5492 { 5493 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5494 int error; 5495 int result; 5496 5497 result = -1; 5498 error = sysctl_handle_int(oidp, &result, 0, req); 5499 5500 if (error || !req->newptr) 5501 return (error); 5502 5503 /* 5504 * This value will cause a hex dump of the 5505 * first 32 16-bit words of the EEPROM to 5506 * the screen. 5507 */ 5508 if (result == 1) 5509 em_print_nvm_info(sc); 5510 5511 return (error); 5512 } 5513 5514 static void 5515 em_print_nvm_info(struct e1000_softc *sc) 5516 { 5517 struct e1000_hw *hw = &sc->hw; 5518 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5519 u16 eeprom_data; 5520 int i, j, row = 0; 5521 5522 /* Its a bit crude, but it gets the job done */ 5523 printf("\nInterface EEPROM Dump:\n"); 5524 printf("Offset\n0x0000 "); 5525 5526 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5527 sx_xlock(iflib_ctx_lock); 5528 ASSERT_CTX_LOCK_HELD(hw); 5529 for (i = 0, j = 0; i < 32; i++, j++) { 5530 if (j == 8) { /* Make the offset block */ 5531 j = 0; ++row; 5532 printf("\n0x00%x0 ",row); 5533 } 5534 e1000_read_nvm(hw, i, 1, &eeprom_data); 5535 printf("%04x ", eeprom_data); 5536 } 5537 sx_xunlock(iflib_ctx_lock); 5538 printf("\n"); 5539 } 5540 5541 static int 5542 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5543 { 5544 struct em_int_delay_info *info; 5545 struct e1000_softc *sc; 5546 u32 regval; 5547 int error, usecs, ticks; 5548 5549 info = (struct em_int_delay_info *) arg1; 5550 usecs = info->value; 5551 error = sysctl_handle_int(oidp, &usecs, 0, req); 5552 if (error != 0 || req->newptr == NULL) 5553 return (error); 5554 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5555 return (EINVAL); 5556 info->value = usecs; 5557 ticks = EM_USECS_TO_TICKS(usecs); 5558 5559 sc = info->sc; 5560 5561 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5562 regval = (regval & ~0xffff) | (ticks & 0xffff); 5563 /* Handle a few special cases. */ 5564 switch (info->offset) { 5565 case E1000_RDTR: 5566 break; 5567 case E1000_TIDV: 5568 if (ticks == 0) { 5569 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5570 /* Don't write 0 into the TIDV register. */ 5571 regval++; 5572 } else 5573 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5574 break; 5575 } 5576 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5577 return (0); 5578 } 5579 5580 static int 5581 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5582 { 5583 struct e1000_softc *sc; 5584 u32 reg, val, shift; 5585 int error, mask; 5586 5587 sc = oidp->oid_arg1; 5588 switch (oidp->oid_arg2) { 5589 case 0: 5590 reg = E1000_DTXTCPFLGL; 5591 shift = 0; 5592 break; 5593 case 1: 5594 reg = E1000_DTXTCPFLGL; 5595 shift = 16; 5596 break; 5597 case 2: 5598 reg = E1000_DTXTCPFLGH; 5599 shift = 0; 5600 break; 5601 default: 5602 return (EINVAL); 5603 break; 5604 } 5605 val = E1000_READ_REG(&sc->hw, reg); 5606 mask = (val >> shift) & 0xfff; 5607 error = sysctl_handle_int(oidp, &mask, 0, req); 5608 if (error != 0 || req->newptr == NULL) 5609 return (error); 5610 if (mask < 0 || mask > 0xfff) 5611 return (EINVAL); 5612 val = (val & ~(0xfff << shift)) | (mask << shift); 5613 E1000_WRITE_REG(&sc->hw, reg, val); 5614 return (0); 5615 } 5616 5617 static void 5618 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5619 const char *description, struct em_int_delay_info *info, int offset, 5620 int value) 5621 { 5622 info->sc = sc; 5623 info->offset = offset; 5624 info->value = value; 5625 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5626 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5627 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5628 info, 0, em_sysctl_int_delay, "I", description); 5629 } 5630 5631 /* 5632 * Set flow control using sysctl: 5633 * Flow control values: 5634 * 0 - off 5635 * 1 - rx pause 5636 * 2 - tx pause 5637 * 3 - full 5638 */ 5639 static int 5640 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5641 { 5642 int error; 5643 static int input = 3; /* default is full */ 5644 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5645 5646 error = sysctl_handle_int(oidp, &input, 0, req); 5647 5648 if ((error) || (req->newptr == NULL)) 5649 return (error); 5650 5651 if (input == sc->fc) /* no change? */ 5652 return (error); 5653 5654 switch (input) { 5655 case e1000_fc_rx_pause: 5656 case e1000_fc_tx_pause: 5657 case e1000_fc_full: 5658 case e1000_fc_none: 5659 sc->hw.fc.requested_mode = input; 5660 sc->fc = input; 5661 break; 5662 default: 5663 /* Do nothing */ 5664 return (error); 5665 } 5666 5667 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5668 e1000_force_mac_fc(&sc->hw); 5669 return (error); 5670 } 5671 5672 /* 5673 * Manage DMA Coalesce: 5674 * Control values: 5675 * 0/1 - off/on 5676 * Legal timer values are: 5677 * 250,500,1000-10000 in thousands 5678 */ 5679 static int 5680 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5681 { 5682 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5683 int error; 5684 5685 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5686 5687 if ((error) || (req->newptr == NULL)) 5688 return (error); 5689 5690 switch (sc->dmac) { 5691 case 0: 5692 /* Disabling */ 5693 break; 5694 case 1: /* Just enable and use default */ 5695 sc->dmac = 1000; 5696 break; 5697 case 250: 5698 case 500: 5699 case 1000: 5700 case 2000: 5701 case 3000: 5702 case 4000: 5703 case 5000: 5704 case 6000: 5705 case 7000: 5706 case 8000: 5707 case 9000: 5708 case 10000: 5709 /* Legal values - allow */ 5710 break; 5711 default: 5712 /* Do nothing, illegal value */ 5713 sc->dmac = 0; 5714 return (EINVAL); 5715 } 5716 /* Reinit the interface */ 5717 em_if_init(sc->ctx); 5718 return (error); 5719 } 5720 5721 /* 5722 * Manage Energy Efficient Ethernet: 5723 * Control values: 5724 * 0/1 - enabled/disabled 5725 */ 5726 static int 5727 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5728 { 5729 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5730 int error, value; 5731 5732 if (sc->hw.mac.type < igb_mac_min) 5733 value = sc->hw.dev_spec.ich8lan.eee_disable; 5734 else 5735 value = sc->hw.dev_spec._82575.eee_disable; 5736 error = sysctl_handle_int(oidp, &value, 0, req); 5737 if (error || req->newptr == NULL) 5738 return (error); 5739 if (sc->hw.mac.type < igb_mac_min) 5740 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5741 else 5742 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5743 em_if_init(sc->ctx); 5744 5745 return (0); 5746 } 5747 5748 static int 5749 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5750 { 5751 struct e1000_softc *sc; 5752 int error; 5753 int result; 5754 5755 result = -1; 5756 error = sysctl_handle_int(oidp, &result, 0, req); 5757 5758 if (error || !req->newptr) 5759 return (error); 5760 5761 if (result == 1) { 5762 sc = (struct e1000_softc *) arg1; 5763 em_print_debug_info(sc); 5764 } 5765 5766 return (error); 5767 } 5768 5769 static int 5770 em_get_rs(SYSCTL_HANDLER_ARGS) 5771 { 5772 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5773 int error; 5774 int result; 5775 5776 result = 0; 5777 error = sysctl_handle_int(oidp, &result, 0, req); 5778 5779 if (error || !req->newptr || result != 1) 5780 return (error); 5781 em_dump_rs(sc); 5782 5783 return (error); 5784 } 5785 5786 static void 5787 em_if_debug(if_ctx_t ctx) 5788 { 5789 em_dump_rs(iflib_get_softc(ctx)); 5790 } 5791 5792 /* 5793 * This routine is meant to be fluid, add whatever is 5794 * needed for debugging a problem. -jfv 5795 */ 5796 static void 5797 em_print_debug_info(struct e1000_softc *sc) 5798 { 5799 device_t dev = iflib_get_dev(sc->ctx); 5800 if_t ifp = iflib_get_ifp(sc->ctx); 5801 struct tx_ring *txr = &sc->tx_queues->txr; 5802 struct rx_ring *rxr = &sc->rx_queues->rxr; 5803 5804 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5805 printf("Interface is RUNNING "); 5806 else 5807 printf("Interface is NOT RUNNING\n"); 5808 5809 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5810 printf("and INACTIVE\n"); 5811 else 5812 printf("and ACTIVE\n"); 5813 5814 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5815 device_printf(dev, "TX Queue %d ------\n", i); 5816 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5817 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5818 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5819 5820 } 5821 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5822 device_printf(dev, "RX Queue %d ------\n", j); 5823 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5824 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5825 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5826 } 5827 } 5828 5829 /* 5830 * 82574 only: 5831 * Write a new value to the EEPROM increasing the number of MSI-X 5832 * vectors from 3 to 5, for proper multiqueue support. 5833 */ 5834 static void 5835 em_enable_vectors_82574(if_ctx_t ctx) 5836 { 5837 struct e1000_softc *sc = iflib_get_softc(ctx); 5838 struct e1000_hw *hw = &sc->hw; 5839 device_t dev = iflib_get_dev(ctx); 5840 u16 edata; 5841 5842 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5843 if (bootverbose) 5844 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5845 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5846 device_printf(dev, "Writing to eeprom: increasing " 5847 "reported MSI-X vectors from 3 to 5...\n"); 5848 edata &= ~(EM_NVM_MSIX_N_MASK); 5849 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5850 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5851 e1000_update_nvm_checksum(hw); 5852 device_printf(dev, "Writing to eeprom: done\n"); 5853 } 5854 } 5855