1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 /* required last entry */ 178 PVID_END 179 }; 180 181 static pci_vendor_info_t igb_vendor_info_array[] = 182 { 183 /* Intel(R) PRO/1000 Network Connection - igb */ 184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 /* required last entry */ 224 PVID_END 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 static void *em_register(device_t dev); 231 static void *igb_register(device_t dev); 232 static int em_if_attach_pre(if_ctx_t ctx); 233 static int em_if_attach_post(if_ctx_t ctx); 234 static int em_if_detach(if_ctx_t ctx); 235 static int em_if_shutdown(if_ctx_t ctx); 236 static int em_if_suspend(if_ctx_t ctx); 237 static int em_if_resume(if_ctx_t ctx); 238 239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 241 static void em_if_queues_free(if_ctx_t ctx); 242 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 244 static void em_if_init(if_ctx_t ctx); 245 static void em_if_stop(if_ctx_t ctx); 246 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 247 static int em_if_media_change(if_ctx_t ctx); 248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 249 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 252 253 static void em_identify_hardware(if_ctx_t ctx); 254 static int em_allocate_pci_resources(if_ctx_t ctx); 255 static void em_free_pci_resources(if_ctx_t ctx); 256 static void em_reset(if_ctx_t ctx); 257 static int em_setup_interface(if_ctx_t ctx); 258 static int em_setup_msix(if_ctx_t ctx); 259 260 static void em_initialize_transmit_unit(if_ctx_t ctx); 261 static void em_initialize_receive_unit(if_ctx_t ctx); 262 263 static void em_if_enable_intr(if_ctx_t ctx); 264 static void em_if_disable_intr(if_ctx_t ctx); 265 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 266 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 267 static void em_if_multi_set(if_ctx_t ctx); 268 static void em_if_update_admin_status(if_ctx_t ctx); 269 static void em_if_debug(if_ctx_t ctx); 270 static void em_update_stats_counters(struct adapter *); 271 static void em_add_hw_stats(struct adapter *adapter); 272 static int em_if_set_promisc(if_ctx_t ctx, int flags); 273 static void em_setup_vlan_hw_support(struct adapter *); 274 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 275 static void em_print_nvm_info(struct adapter *); 276 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 277 static int em_get_rs(SYSCTL_HANDLER_ARGS); 278 static void em_print_debug_info(struct adapter *); 279 static int em_is_valid_ether_addr(u8 *); 280 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 281 static void em_add_int_delay_sysctl(struct adapter *, const char *, 282 const char *, struct em_int_delay_info *, int, int); 283 /* Management and WOL Support */ 284 static void em_init_manageability(struct adapter *); 285 static void em_release_manageability(struct adapter *); 286 static void em_get_hw_control(struct adapter *); 287 static void em_release_hw_control(struct adapter *); 288 static void em_get_wakeup(if_ctx_t ctx); 289 static void em_enable_wakeup(if_ctx_t ctx); 290 static int em_enable_phy_wakeup(struct adapter *); 291 static void em_disable_aspm(struct adapter *); 292 293 int em_intr(void *arg); 294 static void em_disable_promisc(if_ctx_t ctx); 295 296 /* MSIX handlers */ 297 static int em_if_msix_intr_assign(if_ctx_t, int); 298 static int em_msix_link(void *); 299 static void em_handle_link(void *context); 300 301 static void em_enable_vectors_82574(if_ctx_t); 302 303 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 304 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 305 static void em_if_led_func(if_ctx_t ctx, int onoff); 306 307 static int em_get_regs(SYSCTL_HANDLER_ARGS); 308 309 static void lem_smartspeed(struct adapter *adapter); 310 static void igb_configure_queues(struct adapter *adapter); 311 312 313 /********************************************************************* 314 * FreeBSD Device Interface Entry Points 315 *********************************************************************/ 316 static device_method_t em_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_register, em_register), 319 DEVMETHOD(device_probe, iflib_device_probe), 320 DEVMETHOD(device_attach, iflib_device_attach), 321 DEVMETHOD(device_detach, iflib_device_detach), 322 DEVMETHOD(device_shutdown, iflib_device_shutdown), 323 DEVMETHOD(device_suspend, iflib_device_suspend), 324 DEVMETHOD(device_resume, iflib_device_resume), 325 DEVMETHOD_END 326 }; 327 328 static device_method_t igb_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, igb_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 341 static driver_t em_driver = { 342 "em", em_methods, sizeof(struct adapter), 343 }; 344 345 static devclass_t em_devclass; 346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 347 348 MODULE_DEPEND(em, pci, 1, 1, 1); 349 MODULE_DEPEND(em, ether, 1, 1, 1); 350 MODULE_DEPEND(em, iflib, 1, 1, 1); 351 352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 353 354 static driver_t igb_driver = { 355 "igb", igb_methods, sizeof(struct adapter), 356 }; 357 358 static devclass_t igb_devclass; 359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 360 361 MODULE_DEPEND(igb, pci, 1, 1, 1); 362 MODULE_DEPEND(igb, ether, 1, 1, 1); 363 MODULE_DEPEND(igb, iflib, 1, 1, 1); 364 365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 366 367 static device_method_t em_if_methods[] = { 368 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 369 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 370 DEVMETHOD(ifdi_detach, em_if_detach), 371 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 372 DEVMETHOD(ifdi_suspend, em_if_suspend), 373 DEVMETHOD(ifdi_resume, em_if_resume), 374 DEVMETHOD(ifdi_init, em_if_init), 375 DEVMETHOD(ifdi_stop, em_if_stop), 376 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 377 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 378 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 379 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 380 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 381 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 382 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 383 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 384 DEVMETHOD(ifdi_media_status, em_if_media_status), 385 DEVMETHOD(ifdi_media_change, em_if_media_change), 386 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 387 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 388 DEVMETHOD(ifdi_timer, em_if_timer), 389 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 390 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 391 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 392 DEVMETHOD(ifdi_led_func, em_if_led_func), 393 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 394 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 395 DEVMETHOD(ifdi_debug, em_if_debug), 396 DEVMETHOD_END 397 }; 398 399 /* 400 * note that if (adapter->msix_mem) is replaced by: 401 * if (adapter->intr_type == IFLIB_INTR_MSIX) 402 */ 403 static driver_t em_if_driver = { 404 "em_if", em_if_methods, sizeof(struct adapter) 405 }; 406 407 /********************************************************************* 408 * Tunable default values. 409 *********************************************************************/ 410 411 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 412 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 413 414 #define MAX_INTS_PER_SEC 8000 415 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 416 417 /* Allow common code without TSO */ 418 #ifndef CSUM_TSO 419 #define CSUM_TSO 0 420 #endif 421 422 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 423 424 static int em_disable_crc_stripping = 0; 425 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 426 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 427 428 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 429 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 430 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 431 0, "Default transmit interrupt delay in usecs"); 432 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 433 0, "Default receive interrupt delay in usecs"); 434 435 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 436 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 437 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 438 &em_tx_abs_int_delay_dflt, 0, 439 "Default transmit interrupt delay limit in usecs"); 440 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 441 &em_rx_abs_int_delay_dflt, 0, 442 "Default receive interrupt delay limit in usecs"); 443 444 static int em_smart_pwr_down = FALSE; 445 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 446 0, "Set to true to leave smart power down enabled on newer adapters"); 447 448 /* Controls whether promiscuous also shows bad packets */ 449 static int em_debug_sbp = TRUE; 450 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 451 "Show bad packets in promiscuous mode"); 452 453 /* How many packets rxeof tries to clean at a time */ 454 static int em_rx_process_limit = 100; 455 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 456 &em_rx_process_limit, 0, 457 "Maximum number of received packets to process " 458 "at a time, -1 means unlimited"); 459 460 /* Energy efficient ethernet - default to OFF */ 461 static int eee_setting = 1; 462 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 463 "Enable Energy Efficient Ethernet"); 464 465 /* 466 ** Tuneable Interrupt rate 467 */ 468 static int em_max_interrupt_rate = 8000; 469 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 470 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 471 472 473 474 /* Global used in WOL setup with multiport cards */ 475 static int global_quad_port_a = 0; 476 477 extern struct if_txrx igb_txrx; 478 extern struct if_txrx em_txrx; 479 extern struct if_txrx lem_txrx; 480 481 static struct if_shared_ctx em_sctx_init = { 482 .isc_magic = IFLIB_MAGIC, 483 .isc_q_align = PAGE_SIZE, 484 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 485 .isc_tx_maxsegsize = PAGE_SIZE, 486 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 487 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 488 .isc_rx_maxsize = MJUM9BYTES, 489 .isc_rx_nsegments = 1, 490 .isc_rx_maxsegsize = MJUM9BYTES, 491 .isc_nfl = 1, 492 .isc_nrxqs = 1, 493 .isc_ntxqs = 1, 494 .isc_admin_intrcnt = 1, 495 .isc_vendor_info = em_vendor_info_array, 496 .isc_driver_version = em_driver_version, 497 .isc_driver = &em_if_driver, 498 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 499 500 .isc_nrxd_min = {EM_MIN_RXD}, 501 .isc_ntxd_min = {EM_MIN_TXD}, 502 .isc_nrxd_max = {EM_MAX_RXD}, 503 .isc_ntxd_max = {EM_MAX_TXD}, 504 .isc_nrxd_default = {EM_DEFAULT_RXD}, 505 .isc_ntxd_default = {EM_DEFAULT_TXD}, 506 }; 507 508 if_shared_ctx_t em_sctx = &em_sctx_init; 509 510 static struct if_shared_ctx igb_sctx_init = { 511 .isc_magic = IFLIB_MAGIC, 512 .isc_q_align = PAGE_SIZE, 513 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 514 .isc_tx_maxsegsize = PAGE_SIZE, 515 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 516 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 517 .isc_rx_maxsize = MJUM9BYTES, 518 .isc_rx_nsegments = 1, 519 .isc_rx_maxsegsize = MJUM9BYTES, 520 .isc_nfl = 1, 521 .isc_nrxqs = 1, 522 .isc_ntxqs = 1, 523 .isc_admin_intrcnt = 1, 524 .isc_vendor_info = igb_vendor_info_array, 525 .isc_driver_version = em_driver_version, 526 .isc_driver = &em_if_driver, 527 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 528 529 .isc_nrxd_min = {EM_MIN_RXD}, 530 .isc_ntxd_min = {EM_MIN_TXD}, 531 .isc_nrxd_max = {IGB_MAX_RXD}, 532 .isc_ntxd_max = {IGB_MAX_TXD}, 533 .isc_nrxd_default = {EM_DEFAULT_RXD}, 534 .isc_ntxd_default = {EM_DEFAULT_TXD}, 535 }; 536 537 if_shared_ctx_t igb_sctx = &igb_sctx_init; 538 539 /***************************************************************** 540 * 541 * Dump Registers 542 * 543 ****************************************************************/ 544 #define IGB_REGS_LEN 739 545 546 static int em_get_regs(SYSCTL_HANDLER_ARGS) 547 { 548 struct adapter *adapter = (struct adapter *)arg1; 549 struct e1000_hw *hw = &adapter->hw; 550 struct sbuf *sb; 551 u32 *regs_buff; 552 int rc; 553 554 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 555 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 556 557 rc = sysctl_wire_old_buffer(req, 0); 558 MPASS(rc == 0); 559 if (rc != 0) { 560 free(regs_buff, M_DEVBUF); 561 return (rc); 562 } 563 564 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 565 MPASS(sb != NULL); 566 if (sb == NULL) { 567 free(regs_buff, M_DEVBUF); 568 return (ENOMEM); 569 } 570 571 /* General Registers */ 572 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 573 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 574 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 575 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 576 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 577 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 578 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 579 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 580 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 581 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 582 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 583 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 584 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 585 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 586 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 587 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 588 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 589 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 590 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 591 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 592 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 593 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 594 595 sbuf_printf(sb, "General Registers\n"); 596 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 597 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 598 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 599 600 sbuf_printf(sb, "Interrupt Registers\n"); 601 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 602 603 sbuf_printf(sb, "RX Registers\n"); 604 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 605 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 606 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 607 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 608 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 609 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 610 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 611 612 sbuf_printf(sb, "TX Registers\n"); 613 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 614 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 615 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 616 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 617 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 618 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 619 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 620 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 621 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 622 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 623 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 624 625 free(regs_buff, M_DEVBUF); 626 627 #ifdef DUMP_DESCS 628 { 629 if_softc_ctx_t scctx = adapter->shared; 630 struct rx_ring *rxr = &rx_que->rxr; 631 struct tx_ring *txr = &tx_que->txr; 632 int ntxd = scctx->isc_ntxd[0]; 633 int nrxd = scctx->isc_nrxd[0]; 634 int j; 635 636 for (j = 0; j < nrxd; j++) { 637 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 638 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 639 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 640 } 641 642 for (j = 0; j < min(ntxd, 256); j++) { 643 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 644 645 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 646 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 647 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 648 649 } 650 } 651 #endif 652 653 rc = sbuf_finish(sb); 654 sbuf_delete(sb); 655 return(rc); 656 } 657 658 static void * 659 em_register(device_t dev) 660 { 661 return (em_sctx); 662 } 663 664 static void * 665 igb_register(device_t dev) 666 { 667 return (igb_sctx); 668 } 669 670 static int 671 em_set_num_queues(if_ctx_t ctx) 672 { 673 struct adapter *adapter = iflib_get_softc(ctx); 674 int maxqueues; 675 676 /* Sanity check based on HW */ 677 switch (adapter->hw.mac.type) { 678 case e1000_82576: 679 case e1000_82580: 680 case e1000_i350: 681 case e1000_i354: 682 maxqueues = 8; 683 break; 684 case e1000_i210: 685 case e1000_82575: 686 maxqueues = 4; 687 break; 688 case e1000_i211: 689 case e1000_82574: 690 maxqueues = 2; 691 break; 692 default: 693 maxqueues = 1; 694 break; 695 } 696 697 return (maxqueues); 698 } 699 700 #define LEM_CAPS \ 701 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 702 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 703 704 #define EM_CAPS \ 705 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 706 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 707 IFCAP_LRO | IFCAP_VLAN_HWTSO 708 709 #define IGB_CAPS \ 710 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 711 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 712 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 713 IFCAP_TSO6 714 715 /********************************************************************* 716 * Device initialization routine 717 * 718 * The attach entry point is called when the driver is being loaded. 719 * This routine identifies the type of hardware, allocates all resources 720 * and initializes the hardware. 721 * 722 * return 0 on success, positive on failure 723 *********************************************************************/ 724 725 static int 726 em_if_attach_pre(if_ctx_t ctx) 727 { 728 struct adapter *adapter; 729 if_softc_ctx_t scctx; 730 device_t dev; 731 struct e1000_hw *hw; 732 int error = 0; 733 734 INIT_DEBUGOUT("em_if_attach_pre begin"); 735 dev = iflib_get_dev(ctx); 736 adapter = iflib_get_softc(ctx); 737 738 if (resource_disabled("em", device_get_unit(dev))) { 739 device_printf(dev, "Disabled by device hint\n"); 740 return (ENXIO); 741 } 742 743 adapter->ctx = adapter->osdep.ctx = ctx; 744 adapter->dev = adapter->osdep.dev = dev; 745 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 746 adapter->media = iflib_get_media(ctx); 747 hw = &adapter->hw; 748 749 adapter->tx_process_limit = scctx->isc_ntxd[0]; 750 751 /* SYSCTL stuff */ 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 754 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 755 em_sysctl_nvm_info, "I", "NVM Information"); 756 757 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 759 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 760 em_sysctl_debug_info, "I", "Debug Information"); 761 762 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 763 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 764 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 765 em_set_flowcntl, "I", "Flow Control"); 766 767 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 768 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 769 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 770 em_get_regs, "A", "Dump Registers"); 771 772 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 773 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 774 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 775 em_get_rs, "I", "Dump RS indexes"); 776 777 /* Determine hardware and mac info */ 778 em_identify_hardware(ctx); 779 780 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 781 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 782 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 783 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 784 785 if (adapter->hw.mac.type >= igb_mac_min) { 786 int try_second_bar; 787 788 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 789 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 790 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 791 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 792 scctx->isc_txrx = &igb_txrx; 793 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 794 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 795 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 796 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 797 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 798 CSUM_IP6_TCP | CSUM_IP6_UDP; 799 if (adapter->hw.mac.type != e1000_82575) 800 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 801 802 /* 803 ** Some new devices, as with ixgbe, now may 804 ** use a different BAR, so we need to keep 805 ** track of which is used. 806 */ 807 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 808 if (try_second_bar == 0) 809 scctx->isc_msix_bar += 4; 810 } else if (adapter->hw.mac.type >= em_mac_min) { 811 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 812 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 813 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 814 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 815 scctx->isc_txrx = &em_txrx; 816 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 817 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 818 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 819 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 820 /* 821 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 822 * by default as we don't have workarounds for all associated 823 * silicon errata. E. g., with several MACs such as 82573E, 824 * TSO only works at Gigabit speed and otherwise can cause the 825 * hardware to hang (which also would be next to impossible to 826 * work around given that already queued TSO-using descriptors 827 * would need to be flushed and vlan(4) reconfigured at runtime 828 * in case of a link speed change). Moreover, MACs like 82579 829 * still can hang at Gigabit even with all publicly documented 830 * TSO workarounds implemented. Generally, the penality of 831 * these workarounds is rather high and may involve copying 832 * mbuf data around so advantages of TSO lapse. Still, TSO may 833 * work for a few MACs of this class - at least when sticking 834 * with Gigabit - in which case users may enable TSO manually. 835 */ 836 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 837 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 838 } else { 839 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 840 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 841 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 842 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 843 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 844 scctx->isc_txrx = &lem_txrx; 845 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 846 if (adapter->hw.mac.type < e1000_82543) 847 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 848 scctx->isc_msix_bar = 0; 849 } 850 851 /* Setup PCI resources */ 852 if (em_allocate_pci_resources(ctx)) { 853 device_printf(dev, "Allocation of PCI resources failed\n"); 854 error = ENXIO; 855 goto err_pci; 856 } 857 858 /* 859 ** For ICH8 and family we need to 860 ** map the flash memory, and this 861 ** must happen after the MAC is 862 ** identified 863 */ 864 if ((hw->mac.type == e1000_ich8lan) || 865 (hw->mac.type == e1000_ich9lan) || 866 (hw->mac.type == e1000_ich10lan) || 867 (hw->mac.type == e1000_pchlan) || 868 (hw->mac.type == e1000_pch2lan) || 869 (hw->mac.type == e1000_pch_lpt)) { 870 int rid = EM_BAR_TYPE_FLASH; 871 adapter->flash = bus_alloc_resource_any(dev, 872 SYS_RES_MEMORY, &rid, RF_ACTIVE); 873 if (adapter->flash == NULL) { 874 device_printf(dev, "Mapping of Flash failed\n"); 875 error = ENXIO; 876 goto err_pci; 877 } 878 /* This is used in the shared code */ 879 hw->flash_address = (u8 *)adapter->flash; 880 adapter->osdep.flash_bus_space_tag = 881 rman_get_bustag(adapter->flash); 882 adapter->osdep.flash_bus_space_handle = 883 rman_get_bushandle(adapter->flash); 884 } 885 /* 886 ** In the new SPT device flash is not a 887 ** separate BAR, rather it is also in BAR0, 888 ** so use the same tag and an offset handle for the 889 ** FLASH read/write macros in the shared code. 890 */ 891 else if (hw->mac.type >= e1000_pch_spt) { 892 adapter->osdep.flash_bus_space_tag = 893 adapter->osdep.mem_bus_space_tag; 894 adapter->osdep.flash_bus_space_handle = 895 adapter->osdep.mem_bus_space_handle 896 + E1000_FLASH_BASE_ADDR; 897 } 898 899 /* Do Shared Code initialization */ 900 error = e1000_setup_init_funcs(hw, TRUE); 901 if (error) { 902 device_printf(dev, "Setup of Shared code failed, error %d\n", 903 error); 904 error = ENXIO; 905 goto err_pci; 906 } 907 908 em_setup_msix(ctx); 909 e1000_get_bus_info(hw); 910 911 /* Set up some sysctls for the tunable interrupt delays */ 912 em_add_int_delay_sysctl(adapter, "rx_int_delay", 913 "receive interrupt delay in usecs", &adapter->rx_int_delay, 914 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 915 em_add_int_delay_sysctl(adapter, "tx_int_delay", 916 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 917 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 918 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 919 "receive interrupt delay limit in usecs", 920 &adapter->rx_abs_int_delay, 921 E1000_REGISTER(hw, E1000_RADV), 922 em_rx_abs_int_delay_dflt); 923 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 924 "transmit interrupt delay limit in usecs", 925 &adapter->tx_abs_int_delay, 926 E1000_REGISTER(hw, E1000_TADV), 927 em_tx_abs_int_delay_dflt); 928 em_add_int_delay_sysctl(adapter, "itr", 929 "interrupt delay limit in usecs/4", 930 &adapter->tx_itr, 931 E1000_REGISTER(hw, E1000_ITR), 932 DEFAULT_ITR); 933 934 hw->mac.autoneg = DO_AUTO_NEG; 935 hw->phy.autoneg_wait_to_complete = FALSE; 936 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 937 938 if (adapter->hw.mac.type < em_mac_min) { 939 e1000_init_script_state_82541(&adapter->hw, TRUE); 940 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 941 } 942 /* Copper options */ 943 if (hw->phy.media_type == e1000_media_type_copper) { 944 hw->phy.mdix = AUTO_ALL_MODES; 945 hw->phy.disable_polarity_correction = FALSE; 946 hw->phy.ms_type = EM_MASTER_SLAVE; 947 } 948 949 /* 950 * Set the frame limits assuming 951 * standard ethernet sized frames. 952 */ 953 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 954 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 955 956 /* 957 * This controls when hardware reports transmit completion 958 * status. 959 */ 960 hw->mac.report_tx_early = 1; 961 962 /* Allocate multicast array memory. */ 963 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 964 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 965 if (adapter->mta == NULL) { 966 device_printf(dev, "Can not allocate multicast setup array\n"); 967 error = ENOMEM; 968 goto err_late; 969 } 970 971 /* Check SOL/IDER usage */ 972 if (e1000_check_reset_block(hw)) 973 device_printf(dev, "PHY reset is blocked" 974 " due to SOL/IDER session.\n"); 975 976 /* Sysctl for setting Energy Efficient Ethernet */ 977 hw->dev_spec.ich8lan.eee_disable = eee_setting; 978 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 979 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 980 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 981 adapter, 0, em_sysctl_eee, "I", 982 "Disable Energy Efficient Ethernet"); 983 984 /* 985 ** Start from a known state, this is 986 ** important in reading the nvm and 987 ** mac from that. 988 */ 989 e1000_reset_hw(hw); 990 991 /* Make sure we have a good EEPROM before we read from it */ 992 if (e1000_validate_nvm_checksum(hw) < 0) { 993 /* 994 ** Some PCI-E parts fail the first check due to 995 ** the link being in sleep state, call it again, 996 ** if it fails a second time its a real issue. 997 */ 998 if (e1000_validate_nvm_checksum(hw) < 0) { 999 device_printf(dev, 1000 "The EEPROM Checksum Is Not Valid\n"); 1001 error = EIO; 1002 goto err_late; 1003 } 1004 } 1005 1006 /* Copy the permanent MAC address out of the EEPROM */ 1007 if (e1000_read_mac_addr(hw) < 0) { 1008 device_printf(dev, "EEPROM read error while reading MAC" 1009 " address\n"); 1010 error = EIO; 1011 goto err_late; 1012 } 1013 1014 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1015 device_printf(dev, "Invalid MAC address\n"); 1016 error = EIO; 1017 goto err_late; 1018 } 1019 1020 /* Disable ULP support */ 1021 e1000_disable_ulp_lpt_lp(hw, TRUE); 1022 1023 /* 1024 * Get Wake-on-Lan and Management info for later use 1025 */ 1026 em_get_wakeup(ctx); 1027 1028 /* Enable only WOL MAGIC by default */ 1029 scctx->isc_capenable &= ~IFCAP_WOL; 1030 if (adapter->wol != 0) 1031 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1032 1033 iflib_set_mac(ctx, hw->mac.addr); 1034 1035 return (0); 1036 1037 err_late: 1038 em_release_hw_control(adapter); 1039 err_pci: 1040 em_free_pci_resources(ctx); 1041 free(adapter->mta, M_DEVBUF); 1042 1043 return (error); 1044 } 1045 1046 static int 1047 em_if_attach_post(if_ctx_t ctx) 1048 { 1049 struct adapter *adapter = iflib_get_softc(ctx); 1050 struct e1000_hw *hw = &adapter->hw; 1051 int error = 0; 1052 1053 /* Setup OS specific network interface */ 1054 error = em_setup_interface(ctx); 1055 if (error != 0) { 1056 goto err_late; 1057 } 1058 1059 em_reset(ctx); 1060 1061 /* Initialize statistics */ 1062 em_update_stats_counters(adapter); 1063 hw->mac.get_link_status = 1; 1064 em_if_update_admin_status(ctx); 1065 em_add_hw_stats(adapter); 1066 1067 /* Non-AMT based hardware can now take control from firmware */ 1068 if (adapter->has_manage && !adapter->has_amt) 1069 em_get_hw_control(adapter); 1070 1071 INIT_DEBUGOUT("em_if_attach_post: end"); 1072 1073 return (error); 1074 1075 err_late: 1076 em_release_hw_control(adapter); 1077 em_free_pci_resources(ctx); 1078 em_if_queues_free(ctx); 1079 free(adapter->mta, M_DEVBUF); 1080 1081 return (error); 1082 } 1083 1084 /********************************************************************* 1085 * Device removal routine 1086 * 1087 * The detach entry point is called when the driver is being removed. 1088 * This routine stops the adapter and deallocates all the resources 1089 * that were allocated for driver operation. 1090 * 1091 * return 0 on success, positive on failure 1092 *********************************************************************/ 1093 1094 static int 1095 em_if_detach(if_ctx_t ctx) 1096 { 1097 struct adapter *adapter = iflib_get_softc(ctx); 1098 1099 INIT_DEBUGOUT("em_detach: begin"); 1100 1101 e1000_phy_hw_reset(&adapter->hw); 1102 1103 em_release_manageability(adapter); 1104 em_release_hw_control(adapter); 1105 em_free_pci_resources(ctx); 1106 1107 return (0); 1108 } 1109 1110 /********************************************************************* 1111 * 1112 * Shutdown entry point 1113 * 1114 **********************************************************************/ 1115 1116 static int 1117 em_if_shutdown(if_ctx_t ctx) 1118 { 1119 return em_if_suspend(ctx); 1120 } 1121 1122 /* 1123 * Suspend/resume device methods. 1124 */ 1125 static int 1126 em_if_suspend(if_ctx_t ctx) 1127 { 1128 struct adapter *adapter = iflib_get_softc(ctx); 1129 1130 em_release_manageability(adapter); 1131 em_release_hw_control(adapter); 1132 em_enable_wakeup(ctx); 1133 return (0); 1134 } 1135 1136 static int 1137 em_if_resume(if_ctx_t ctx) 1138 { 1139 struct adapter *adapter = iflib_get_softc(ctx); 1140 1141 if (adapter->hw.mac.type == e1000_pch2lan) 1142 e1000_resume_workarounds_pchlan(&adapter->hw); 1143 em_if_init(ctx); 1144 em_init_manageability(adapter); 1145 1146 return(0); 1147 } 1148 1149 static int 1150 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1151 { 1152 int max_frame_size; 1153 struct adapter *adapter = iflib_get_softc(ctx); 1154 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1155 1156 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1157 1158 switch (adapter->hw.mac.type) { 1159 case e1000_82571: 1160 case e1000_82572: 1161 case e1000_ich9lan: 1162 case e1000_ich10lan: 1163 case e1000_pch2lan: 1164 case e1000_pch_lpt: 1165 case e1000_pch_spt: 1166 case e1000_pch_cnp: 1167 case e1000_82574: 1168 case e1000_82583: 1169 case e1000_80003es2lan: 1170 /* 9K Jumbo Frame size */ 1171 max_frame_size = 9234; 1172 break; 1173 case e1000_pchlan: 1174 max_frame_size = 4096; 1175 break; 1176 case e1000_82542: 1177 case e1000_ich8lan: 1178 /* Adapters that do not support jumbo frames */ 1179 max_frame_size = ETHER_MAX_LEN; 1180 break; 1181 default: 1182 if (adapter->hw.mac.type >= igb_mac_min) 1183 max_frame_size = 9234; 1184 else /* lem */ 1185 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1186 } 1187 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1188 return (EINVAL); 1189 } 1190 1191 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1192 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1193 return (0); 1194 } 1195 1196 /********************************************************************* 1197 * Init entry point 1198 * 1199 * This routine is used in two ways. It is used by the stack as 1200 * init entry point in network interface structure. It is also used 1201 * by the driver as a hw/sw initialization routine to get to a 1202 * consistent state. 1203 * 1204 * return 0 on success, positive on failure 1205 **********************************************************************/ 1206 1207 static void 1208 em_if_init(if_ctx_t ctx) 1209 { 1210 struct adapter *adapter = iflib_get_softc(ctx); 1211 if_softc_ctx_t scctx = adapter->shared; 1212 struct ifnet *ifp = iflib_get_ifp(ctx); 1213 struct em_tx_queue *tx_que; 1214 int i; 1215 INIT_DEBUGOUT("em_if_init: begin"); 1216 1217 /* Get the latest mac address, User can use a LAA */ 1218 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1219 ETHER_ADDR_LEN); 1220 1221 /* Put the address into the Receive Address Array */ 1222 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1223 1224 /* 1225 * With the 82571 adapter, RAR[0] may be overwritten 1226 * when the other port is reset, we make a duplicate 1227 * in RAR[14] for that eventuality, this assures 1228 * the interface continues to function. 1229 */ 1230 if (adapter->hw.mac.type == e1000_82571) { 1231 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1232 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1233 E1000_RAR_ENTRIES - 1); 1234 } 1235 1236 1237 /* Initialize the hardware */ 1238 em_reset(ctx); 1239 em_if_update_admin_status(ctx); 1240 1241 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1242 struct tx_ring *txr = &tx_que->txr; 1243 1244 txr->tx_rs_cidx = txr->tx_rs_pidx; 1245 1246 /* Initialize the last processed descriptor to be the end of 1247 * the ring, rather than the start, so that we avoid an 1248 * off-by-one error when calculating how many descriptors are 1249 * done in the credits_update function. 1250 */ 1251 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1252 } 1253 1254 /* Setup VLAN support, basic and offload if available */ 1255 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1256 1257 /* Clear bad data from Rx FIFOs */ 1258 if (adapter->hw.mac.type >= igb_mac_min) 1259 e1000_rx_fifo_flush_82575(&adapter->hw); 1260 1261 /* Configure for OS presence */ 1262 em_init_manageability(adapter); 1263 1264 /* Prepare transmit descriptors and buffers */ 1265 em_initialize_transmit_unit(ctx); 1266 1267 /* Setup Multicast table */ 1268 em_if_multi_set(ctx); 1269 1270 /* 1271 * Figure out the desired mbuf 1272 * pool for doing jumbos 1273 */ 1274 if (adapter->hw.mac.max_frame_size <= 2048) 1275 adapter->rx_mbuf_sz = MCLBYTES; 1276 #ifndef CONTIGMALLOC_WORKS 1277 else 1278 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1279 #else 1280 else if (adapter->hw.mac.max_frame_size <= 4096) 1281 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1282 else 1283 adapter->rx_mbuf_sz = MJUM9BYTES; 1284 #endif 1285 em_initialize_receive_unit(ctx); 1286 1287 /* Use real VLAN Filter support? */ 1288 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1289 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1290 /* Use real VLAN Filter support */ 1291 em_setup_vlan_hw_support(adapter); 1292 else { 1293 u32 ctrl; 1294 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1295 ctrl |= E1000_CTRL_VME; 1296 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1297 } 1298 } 1299 1300 /* Don't lose promiscuous settings */ 1301 em_if_set_promisc(ctx, IFF_PROMISC); 1302 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1303 1304 /* MSI/X configuration for 82574 */ 1305 if (adapter->hw.mac.type == e1000_82574) { 1306 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1307 1308 tmp |= E1000_CTRL_EXT_PBA_CLR; 1309 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1310 /* Set the IVAR - interrupt vector routing. */ 1311 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1312 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1313 igb_configure_queues(adapter); 1314 1315 /* this clears any pending interrupts */ 1316 E1000_READ_REG(&adapter->hw, E1000_ICR); 1317 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1318 1319 /* AMT based hardware can now take control from firmware */ 1320 if (adapter->has_manage && adapter->has_amt) 1321 em_get_hw_control(adapter); 1322 1323 /* Set Energy Efficient Ethernet */ 1324 if (adapter->hw.mac.type >= igb_mac_min && 1325 adapter->hw.phy.media_type == e1000_media_type_copper) { 1326 if (adapter->hw.mac.type == e1000_i354) 1327 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1328 else 1329 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1330 } 1331 } 1332 1333 /********************************************************************* 1334 * 1335 * Fast Legacy/MSI Combined Interrupt Service routine 1336 * 1337 *********************************************************************/ 1338 int 1339 em_intr(void *arg) 1340 { 1341 struct adapter *adapter = arg; 1342 if_ctx_t ctx = adapter->ctx; 1343 u32 reg_icr; 1344 1345 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1346 1347 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1348 goto skip_stray; 1349 /* Hot eject? */ 1350 if (reg_icr == 0xffffffff) 1351 return FILTER_STRAY; 1352 1353 /* Definitely not our interrupt. */ 1354 if (reg_icr == 0x0) 1355 return FILTER_STRAY; 1356 1357 /* 1358 * Starting with the 82571 chip, bit 31 should be used to 1359 * determine whether the interrupt belongs to us. 1360 */ 1361 if (adapter->hw.mac.type >= e1000_82571 && 1362 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1363 return FILTER_STRAY; 1364 1365 skip_stray: 1366 /* Link status change */ 1367 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1368 adapter->hw.mac.get_link_status = 1; 1369 iflib_admin_intr_deferred(ctx); 1370 } 1371 1372 if (reg_icr & E1000_ICR_RXO) 1373 adapter->rx_overruns++; 1374 1375 return (FILTER_SCHEDULE_THREAD); 1376 } 1377 1378 static void 1379 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1380 { 1381 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1382 } 1383 1384 static void 1385 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1386 { 1387 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1388 } 1389 1390 static void 1391 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1392 { 1393 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1394 } 1395 1396 static void 1397 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1398 { 1399 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1400 } 1401 1402 static int 1403 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1404 { 1405 struct adapter *adapter = iflib_get_softc(ctx); 1406 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1407 1408 if (adapter->hw.mac.type >= igb_mac_min) 1409 igb_rx_enable_queue(adapter, rxq); 1410 else 1411 em_rx_enable_queue(adapter, rxq); 1412 return (0); 1413 } 1414 1415 static int 1416 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1417 { 1418 struct adapter *adapter = iflib_get_softc(ctx); 1419 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1420 1421 if (adapter->hw.mac.type >= igb_mac_min) 1422 igb_tx_enable_queue(adapter, txq); 1423 else 1424 em_tx_enable_queue(adapter, txq); 1425 return (0); 1426 } 1427 1428 /********************************************************************* 1429 * 1430 * MSIX RX Interrupt Service routine 1431 * 1432 **********************************************************************/ 1433 static int 1434 em_msix_que(void *arg) 1435 { 1436 struct em_rx_queue *que = arg; 1437 1438 ++que->irqs; 1439 1440 return (FILTER_SCHEDULE_THREAD); 1441 } 1442 1443 /********************************************************************* 1444 * 1445 * MSIX Link Fast Interrupt Service routine 1446 * 1447 **********************************************************************/ 1448 static int 1449 em_msix_link(void *arg) 1450 { 1451 struct adapter *adapter = arg; 1452 u32 reg_icr; 1453 1454 ++adapter->link_irq; 1455 MPASS(adapter->hw.back != NULL); 1456 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1457 1458 if (reg_icr & E1000_ICR_RXO) 1459 adapter->rx_overruns++; 1460 1461 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1462 em_handle_link(adapter->ctx); 1463 } else { 1464 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1465 EM_MSIX_LINK | E1000_IMS_LSC); 1466 if (adapter->hw.mac.type >= igb_mac_min) 1467 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1468 } 1469 1470 /* 1471 * Because we must read the ICR for this interrupt 1472 * it may clear other causes using autoclear, for 1473 * this reason we simply create a soft interrupt 1474 * for all these vectors. 1475 */ 1476 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1477 E1000_WRITE_REG(&adapter->hw, 1478 E1000_ICS, adapter->ims); 1479 } 1480 1481 return (FILTER_HANDLED); 1482 } 1483 1484 static void 1485 em_handle_link(void *context) 1486 { 1487 if_ctx_t ctx = context; 1488 struct adapter *adapter = iflib_get_softc(ctx); 1489 1490 adapter->hw.mac.get_link_status = 1; 1491 iflib_admin_intr_deferred(ctx); 1492 } 1493 1494 1495 /********************************************************************* 1496 * 1497 * Media Ioctl callback 1498 * 1499 * This routine is called whenever the user queries the status of 1500 * the interface using ifconfig. 1501 * 1502 **********************************************************************/ 1503 static void 1504 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1505 { 1506 struct adapter *adapter = iflib_get_softc(ctx); 1507 u_char fiber_type = IFM_1000_SX; 1508 1509 INIT_DEBUGOUT("em_if_media_status: begin"); 1510 1511 iflib_admin_intr_deferred(ctx); 1512 1513 ifmr->ifm_status = IFM_AVALID; 1514 ifmr->ifm_active = IFM_ETHER; 1515 1516 if (!adapter->link_active) { 1517 return; 1518 } 1519 1520 ifmr->ifm_status |= IFM_ACTIVE; 1521 1522 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1523 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1524 if (adapter->hw.mac.type == e1000_82545) 1525 fiber_type = IFM_1000_LX; 1526 ifmr->ifm_active |= fiber_type | IFM_FDX; 1527 } else { 1528 switch (adapter->link_speed) { 1529 case 10: 1530 ifmr->ifm_active |= IFM_10_T; 1531 break; 1532 case 100: 1533 ifmr->ifm_active |= IFM_100_TX; 1534 break; 1535 case 1000: 1536 ifmr->ifm_active |= IFM_1000_T; 1537 break; 1538 } 1539 if (adapter->link_duplex == FULL_DUPLEX) 1540 ifmr->ifm_active |= IFM_FDX; 1541 else 1542 ifmr->ifm_active |= IFM_HDX; 1543 } 1544 } 1545 1546 /********************************************************************* 1547 * 1548 * Media Ioctl callback 1549 * 1550 * This routine is called when the user changes speed/duplex using 1551 * media/mediopt option with ifconfig. 1552 * 1553 **********************************************************************/ 1554 static int 1555 em_if_media_change(if_ctx_t ctx) 1556 { 1557 struct adapter *adapter = iflib_get_softc(ctx); 1558 struct ifmedia *ifm = iflib_get_media(ctx); 1559 1560 INIT_DEBUGOUT("em_if_media_change: begin"); 1561 1562 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1563 return (EINVAL); 1564 1565 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1566 case IFM_AUTO: 1567 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1568 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1569 break; 1570 case IFM_1000_LX: 1571 case IFM_1000_SX: 1572 case IFM_1000_T: 1573 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1574 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1575 break; 1576 case IFM_100_TX: 1577 adapter->hw.mac.autoneg = FALSE; 1578 adapter->hw.phy.autoneg_advertised = 0; 1579 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1580 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1581 else 1582 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1583 break; 1584 case IFM_10_T: 1585 adapter->hw.mac.autoneg = FALSE; 1586 adapter->hw.phy.autoneg_advertised = 0; 1587 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1588 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1589 else 1590 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1591 break; 1592 default: 1593 device_printf(adapter->dev, "Unsupported media type\n"); 1594 } 1595 1596 em_if_init(ctx); 1597 1598 return (0); 1599 } 1600 1601 static int 1602 em_if_set_promisc(if_ctx_t ctx, int flags) 1603 { 1604 struct adapter *adapter = iflib_get_softc(ctx); 1605 u32 reg_rctl; 1606 1607 em_disable_promisc(ctx); 1608 1609 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1610 1611 if (flags & IFF_PROMISC) { 1612 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1613 /* Turn this on if you want to see bad packets */ 1614 if (em_debug_sbp) 1615 reg_rctl |= E1000_RCTL_SBP; 1616 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1617 } else if (flags & IFF_ALLMULTI) { 1618 reg_rctl |= E1000_RCTL_MPE; 1619 reg_rctl &= ~E1000_RCTL_UPE; 1620 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1621 } 1622 return (0); 1623 } 1624 1625 static void 1626 em_disable_promisc(if_ctx_t ctx) 1627 { 1628 struct adapter *adapter = iflib_get_softc(ctx); 1629 struct ifnet *ifp = iflib_get_ifp(ctx); 1630 u32 reg_rctl; 1631 int mcnt = 0; 1632 1633 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1634 reg_rctl &= (~E1000_RCTL_UPE); 1635 if (if_getflags(ifp) & IFF_ALLMULTI) 1636 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1637 else 1638 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1639 /* Don't disable if in MAX groups */ 1640 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1641 reg_rctl &= (~E1000_RCTL_MPE); 1642 reg_rctl &= (~E1000_RCTL_SBP); 1643 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1644 } 1645 1646 1647 /********************************************************************* 1648 * Multicast Update 1649 * 1650 * This routine is called whenever multicast address list is updated. 1651 * 1652 **********************************************************************/ 1653 1654 static void 1655 em_if_multi_set(if_ctx_t ctx) 1656 { 1657 struct adapter *adapter = iflib_get_softc(ctx); 1658 struct ifnet *ifp = iflib_get_ifp(ctx); 1659 u32 reg_rctl = 0; 1660 u8 *mta; /* Multicast array memory */ 1661 int mcnt = 0; 1662 1663 IOCTL_DEBUGOUT("em_set_multi: begin"); 1664 1665 mta = adapter->mta; 1666 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1667 1668 if (adapter->hw.mac.type == e1000_82542 && 1669 adapter->hw.revision_id == E1000_REVISION_2) { 1670 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1671 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1672 e1000_pci_clear_mwi(&adapter->hw); 1673 reg_rctl |= E1000_RCTL_RST; 1674 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1675 msec_delay(5); 1676 } 1677 1678 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1679 1680 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1681 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1682 reg_rctl |= E1000_RCTL_MPE; 1683 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1684 } else 1685 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1686 1687 if (adapter->hw.mac.type == e1000_82542 && 1688 adapter->hw.revision_id == E1000_REVISION_2) { 1689 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1690 reg_rctl &= ~E1000_RCTL_RST; 1691 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1692 msec_delay(5); 1693 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1694 e1000_pci_set_mwi(&adapter->hw); 1695 } 1696 } 1697 1698 1699 /********************************************************************* 1700 * Timer routine 1701 * 1702 * This routine checks for link status and updates statistics. 1703 * 1704 **********************************************************************/ 1705 1706 static void 1707 em_if_timer(if_ctx_t ctx, uint16_t qid) 1708 { 1709 struct adapter *adapter = iflib_get_softc(ctx); 1710 struct em_rx_queue *que; 1711 int i; 1712 int trigger = 0; 1713 1714 if (qid != 0) 1715 return; 1716 1717 iflib_admin_intr_deferred(ctx); 1718 1719 /* Mask to use in the irq trigger */ 1720 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1721 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1722 trigger |= que->eims; 1723 } else { 1724 trigger = E1000_ICS_RXDMT0; 1725 } 1726 } 1727 1728 1729 static void 1730 em_if_update_admin_status(if_ctx_t ctx) 1731 { 1732 struct adapter *adapter = iflib_get_softc(ctx); 1733 struct e1000_hw *hw = &adapter->hw; 1734 device_t dev = iflib_get_dev(ctx); 1735 u32 link_check, thstat, ctrl; 1736 1737 link_check = thstat = ctrl = 0; 1738 /* Get the cached link value or read phy for real */ 1739 switch (hw->phy.media_type) { 1740 case e1000_media_type_copper: 1741 if (hw->mac.get_link_status) { 1742 if (hw->mac.type == e1000_pch_spt) 1743 msec_delay(50); 1744 /* Do the work to read phy */ 1745 e1000_check_for_link(hw); 1746 link_check = !hw->mac.get_link_status; 1747 if (link_check) /* ESB2 fix */ 1748 e1000_cfg_on_link_up(hw); 1749 } else { 1750 link_check = TRUE; 1751 } 1752 break; 1753 case e1000_media_type_fiber: 1754 e1000_check_for_link(hw); 1755 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1756 E1000_STATUS_LU); 1757 break; 1758 case e1000_media_type_internal_serdes: 1759 e1000_check_for_link(hw); 1760 link_check = adapter->hw.mac.serdes_has_link; 1761 break; 1762 /* VF device is type_unknown */ 1763 case e1000_media_type_unknown: 1764 e1000_check_for_link(hw); 1765 link_check = !hw->mac.get_link_status; 1766 /* FALLTHROUGH */ 1767 default: 1768 break; 1769 } 1770 1771 /* Check for thermal downshift or shutdown */ 1772 if (hw->mac.type == e1000_i350) { 1773 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1774 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1775 } 1776 1777 /* Now check for a transition */ 1778 if (link_check && (adapter->link_active == 0)) { 1779 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1780 &adapter->link_duplex); 1781 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1782 if ((adapter->link_speed != SPEED_1000) && 1783 ((hw->mac.type == e1000_82571) || 1784 (hw->mac.type == e1000_82572))) { 1785 int tarc0; 1786 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1787 tarc0 &= ~TARC_SPEED_MODE_BIT; 1788 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1789 } 1790 if (bootverbose) 1791 device_printf(dev, "Link is up %d Mbps %s\n", 1792 adapter->link_speed, 1793 ((adapter->link_duplex == FULL_DUPLEX) ? 1794 "Full Duplex" : "Half Duplex")); 1795 adapter->link_active = 1; 1796 adapter->smartspeed = 0; 1797 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1798 E1000_CTRL_EXT_LINK_MODE_GMII && 1799 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1800 device_printf(dev, "Link: thermal downshift\n"); 1801 /* Delay Link Up for Phy update */ 1802 if (((hw->mac.type == e1000_i210) || 1803 (hw->mac.type == e1000_i211)) && 1804 (hw->phy.id == I210_I_PHY_ID)) 1805 msec_delay(I210_LINK_DELAY); 1806 /* Reset if the media type changed. */ 1807 if ((hw->dev_spec._82575.media_changed) && 1808 (adapter->hw.mac.type >= igb_mac_min)) { 1809 hw->dev_spec._82575.media_changed = false; 1810 adapter->flags |= IGB_MEDIA_RESET; 1811 em_reset(ctx); 1812 } 1813 iflib_link_state_change(ctx, LINK_STATE_UP, 1814 IF_Mbps(adapter->link_speed)); 1815 } else if (!link_check && (adapter->link_active == 1)) { 1816 adapter->link_speed = 0; 1817 adapter->link_duplex = 0; 1818 adapter->link_active = 0; 1819 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1820 } 1821 em_update_stats_counters(adapter); 1822 1823 /* Reset LAA into RAR[0] on 82571 */ 1824 if ((adapter->hw.mac.type == e1000_82571) && 1825 e1000_get_laa_state_82571(&adapter->hw)) 1826 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1827 1828 if (adapter->hw.mac.type < em_mac_min) 1829 lem_smartspeed(adapter); 1830 1831 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1832 } 1833 1834 /********************************************************************* 1835 * 1836 * This routine disables all traffic on the adapter by issuing a 1837 * global reset on the MAC and deallocates TX/RX buffers. 1838 * 1839 * This routine should always be called with BOTH the CORE 1840 * and TX locks. 1841 **********************************************************************/ 1842 1843 static void 1844 em_if_stop(if_ctx_t ctx) 1845 { 1846 struct adapter *adapter = iflib_get_softc(ctx); 1847 1848 INIT_DEBUGOUT("em_stop: begin"); 1849 1850 e1000_reset_hw(&adapter->hw); 1851 if (adapter->hw.mac.type >= e1000_82544) 1852 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1853 1854 e1000_led_off(&adapter->hw); 1855 e1000_cleanup_led(&adapter->hw); 1856 } 1857 1858 1859 /********************************************************************* 1860 * 1861 * Determine hardware revision. 1862 * 1863 **********************************************************************/ 1864 static void 1865 em_identify_hardware(if_ctx_t ctx) 1866 { 1867 device_t dev = iflib_get_dev(ctx); 1868 struct adapter *adapter = iflib_get_softc(ctx); 1869 1870 /* Make sure our PCI config space has the necessary stuff set */ 1871 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1872 1873 /* Save off the information about this board */ 1874 adapter->hw.vendor_id = pci_get_vendor(dev); 1875 adapter->hw.device_id = pci_get_device(dev); 1876 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1877 adapter->hw.subsystem_vendor_id = 1878 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1879 adapter->hw.subsystem_device_id = 1880 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1881 1882 /* Do Shared Code Init and Setup */ 1883 if (e1000_set_mac_type(&adapter->hw)) { 1884 device_printf(dev, "Setup init failure\n"); 1885 return; 1886 } 1887 } 1888 1889 static int 1890 em_allocate_pci_resources(if_ctx_t ctx) 1891 { 1892 struct adapter *adapter = iflib_get_softc(ctx); 1893 device_t dev = iflib_get_dev(ctx); 1894 int rid, val; 1895 1896 rid = PCIR_BAR(0); 1897 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1898 &rid, RF_ACTIVE); 1899 if (adapter->memory == NULL) { 1900 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1901 return (ENXIO); 1902 } 1903 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1904 adapter->osdep.mem_bus_space_handle = 1905 rman_get_bushandle(adapter->memory); 1906 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1907 1908 /* Only older adapters use IO mapping */ 1909 if (adapter->hw.mac.type < em_mac_min && 1910 adapter->hw.mac.type > e1000_82543) { 1911 /* Figure our where our IO BAR is ? */ 1912 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1913 val = pci_read_config(dev, rid, 4); 1914 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1915 adapter->io_rid = rid; 1916 break; 1917 } 1918 rid += 4; 1919 /* check for 64bit BAR */ 1920 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1921 rid += 4; 1922 } 1923 if (rid >= PCIR_CIS) { 1924 device_printf(dev, "Unable to locate IO BAR\n"); 1925 return (ENXIO); 1926 } 1927 adapter->ioport = bus_alloc_resource_any(dev, 1928 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1929 if (adapter->ioport == NULL) { 1930 device_printf(dev, "Unable to allocate bus resource: " 1931 "ioport\n"); 1932 return (ENXIO); 1933 } 1934 adapter->hw.io_base = 0; 1935 adapter->osdep.io_bus_space_tag = 1936 rman_get_bustag(adapter->ioport); 1937 adapter->osdep.io_bus_space_handle = 1938 rman_get_bushandle(adapter->ioport); 1939 } 1940 1941 adapter->hw.back = &adapter->osdep; 1942 1943 return (0); 1944 } 1945 1946 /********************************************************************* 1947 * 1948 * Setup the MSIX Interrupt handlers 1949 * 1950 **********************************************************************/ 1951 static int 1952 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1953 { 1954 struct adapter *adapter = iflib_get_softc(ctx); 1955 struct em_rx_queue *rx_que = adapter->rx_queues; 1956 struct em_tx_queue *tx_que = adapter->tx_queues; 1957 int error, rid, i, vector = 0, rx_vectors; 1958 char buf[16]; 1959 1960 /* First set up ring resources */ 1961 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1962 rid = vector + 1; 1963 snprintf(buf, sizeof(buf), "rxq%d", i); 1964 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1965 if (error) { 1966 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1967 adapter->rx_num_queues = i + 1; 1968 goto fail; 1969 } 1970 1971 rx_que->msix = vector; 1972 1973 /* 1974 * Set the bit to enable interrupt 1975 * in E1000_IMS -- bits 20 and 21 1976 * are for RX0 and RX1, note this has 1977 * NOTHING to do with the MSIX vector 1978 */ 1979 if (adapter->hw.mac.type == e1000_82574) { 1980 rx_que->eims = 1 << (20 + i); 1981 adapter->ims |= rx_que->eims; 1982 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1983 } else if (adapter->hw.mac.type == e1000_82575) 1984 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1985 else 1986 rx_que->eims = 1 << vector; 1987 } 1988 rx_vectors = vector; 1989 1990 vector = 0; 1991 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1992 snprintf(buf, sizeof(buf), "txq%d", i); 1993 tx_que = &adapter->tx_queues[i]; 1994 iflib_softirq_alloc_generic(ctx, 1995 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1996 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1997 1998 tx_que->msix = (vector % adapter->tx_num_queues); 1999 2000 /* 2001 * Set the bit to enable interrupt 2002 * in E1000_IMS -- bits 22 and 23 2003 * are for TX0 and TX1, note this has 2004 * NOTHING to do with the MSIX vector 2005 */ 2006 if (adapter->hw.mac.type == e1000_82574) { 2007 tx_que->eims = 1 << (22 + i); 2008 adapter->ims |= tx_que->eims; 2009 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2010 } else if (adapter->hw.mac.type == e1000_82575) { 2011 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 2012 } else { 2013 tx_que->eims = 1 << (i % adapter->tx_num_queues); 2014 } 2015 } 2016 2017 /* Link interrupt */ 2018 rid = rx_vectors + 1; 2019 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2020 2021 if (error) { 2022 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2023 goto fail; 2024 } 2025 adapter->linkvec = rx_vectors; 2026 if (adapter->hw.mac.type < igb_mac_min) { 2027 adapter->ivars |= (8 | rx_vectors) << 16; 2028 adapter->ivars |= 0x80000000; 2029 } 2030 return (0); 2031 fail: 2032 iflib_irq_free(ctx, &adapter->irq); 2033 rx_que = adapter->rx_queues; 2034 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2035 iflib_irq_free(ctx, &rx_que->que_irq); 2036 return (error); 2037 } 2038 2039 static void 2040 igb_configure_queues(struct adapter *adapter) 2041 { 2042 struct e1000_hw *hw = &adapter->hw; 2043 struct em_rx_queue *rx_que; 2044 struct em_tx_queue *tx_que; 2045 u32 tmp, ivar = 0, newitr = 0; 2046 2047 /* First turn on RSS capability */ 2048 if (adapter->hw.mac.type != e1000_82575) 2049 E1000_WRITE_REG(hw, E1000_GPIE, 2050 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2051 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2052 2053 /* Turn on MSIX */ 2054 switch (adapter->hw.mac.type) { 2055 case e1000_82580: 2056 case e1000_i350: 2057 case e1000_i354: 2058 case e1000_i210: 2059 case e1000_i211: 2060 case e1000_vfadapt: 2061 case e1000_vfadapt_i350: 2062 /* RX entries */ 2063 for (int i = 0; i < adapter->rx_num_queues; i++) { 2064 u32 index = i >> 1; 2065 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2066 rx_que = &adapter->rx_queues[i]; 2067 if (i & 1) { 2068 ivar &= 0xFF00FFFF; 2069 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2070 } else { 2071 ivar &= 0xFFFFFF00; 2072 ivar |= rx_que->msix | E1000_IVAR_VALID; 2073 } 2074 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2075 } 2076 /* TX entries */ 2077 for (int i = 0; i < adapter->tx_num_queues; i++) { 2078 u32 index = i >> 1; 2079 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2080 tx_que = &adapter->tx_queues[i]; 2081 if (i & 1) { 2082 ivar &= 0x00FFFFFF; 2083 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2084 } else { 2085 ivar &= 0xFFFF00FF; 2086 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2087 } 2088 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2089 adapter->que_mask |= tx_que->eims; 2090 } 2091 2092 /* And for the link interrupt */ 2093 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2094 adapter->link_mask = 1 << adapter->linkvec; 2095 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2096 break; 2097 case e1000_82576: 2098 /* RX entries */ 2099 for (int i = 0; i < adapter->rx_num_queues; i++) { 2100 u32 index = i & 0x7; /* Each IVAR has two entries */ 2101 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2102 rx_que = &adapter->rx_queues[i]; 2103 if (i < 8) { 2104 ivar &= 0xFFFFFF00; 2105 ivar |= rx_que->msix | E1000_IVAR_VALID; 2106 } else { 2107 ivar &= 0xFF00FFFF; 2108 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2109 } 2110 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2111 adapter->que_mask |= rx_que->eims; 2112 } 2113 /* TX entries */ 2114 for (int i = 0; i < adapter->tx_num_queues; i++) { 2115 u32 index = i & 0x7; /* Each IVAR has two entries */ 2116 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2117 tx_que = &adapter->tx_queues[i]; 2118 if (i < 8) { 2119 ivar &= 0xFFFF00FF; 2120 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2121 } else { 2122 ivar &= 0x00FFFFFF; 2123 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2124 } 2125 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2126 adapter->que_mask |= tx_que->eims; 2127 } 2128 2129 /* And for the link interrupt */ 2130 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2131 adapter->link_mask = 1 << adapter->linkvec; 2132 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2133 break; 2134 2135 case e1000_82575: 2136 /* enable MSI-X support*/ 2137 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2138 tmp |= E1000_CTRL_EXT_PBA_CLR; 2139 /* Auto-Mask interrupts upon ICR read. */ 2140 tmp |= E1000_CTRL_EXT_EIAME; 2141 tmp |= E1000_CTRL_EXT_IRCA; 2142 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2143 2144 /* Queues */ 2145 for (int i = 0; i < adapter->rx_num_queues; i++) { 2146 rx_que = &adapter->rx_queues[i]; 2147 tmp = E1000_EICR_RX_QUEUE0 << i; 2148 tmp |= E1000_EICR_TX_QUEUE0 << i; 2149 rx_que->eims = tmp; 2150 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2151 i, rx_que->eims); 2152 adapter->que_mask |= rx_que->eims; 2153 } 2154 2155 /* Link */ 2156 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2157 E1000_EIMS_OTHER); 2158 adapter->link_mask |= E1000_EIMS_OTHER; 2159 default: 2160 break; 2161 } 2162 2163 /* Set the starting interrupt rate */ 2164 if (em_max_interrupt_rate > 0) 2165 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2166 2167 if (hw->mac.type == e1000_82575) 2168 newitr |= newitr << 16; 2169 else 2170 newitr |= E1000_EITR_CNT_IGNR; 2171 2172 for (int i = 0; i < adapter->rx_num_queues; i++) { 2173 rx_que = &adapter->rx_queues[i]; 2174 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2175 } 2176 2177 return; 2178 } 2179 2180 static void 2181 em_free_pci_resources(if_ctx_t ctx) 2182 { 2183 struct adapter *adapter = iflib_get_softc(ctx); 2184 struct em_rx_queue *que = adapter->rx_queues; 2185 device_t dev = iflib_get_dev(ctx); 2186 2187 /* Release all msix queue resources */ 2188 if (adapter->intr_type == IFLIB_INTR_MSIX) 2189 iflib_irq_free(ctx, &adapter->irq); 2190 2191 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2192 iflib_irq_free(ctx, &que->que_irq); 2193 } 2194 2195 /* First release all the interrupt resources */ 2196 if (adapter->memory != NULL) { 2197 bus_release_resource(dev, SYS_RES_MEMORY, 2198 PCIR_BAR(0), adapter->memory); 2199 adapter->memory = NULL; 2200 } 2201 2202 if (adapter->flash != NULL) { 2203 bus_release_resource(dev, SYS_RES_MEMORY, 2204 EM_FLASH, adapter->flash); 2205 adapter->flash = NULL; 2206 } 2207 if (adapter->ioport != NULL) 2208 bus_release_resource(dev, SYS_RES_IOPORT, 2209 adapter->io_rid, adapter->ioport); 2210 } 2211 2212 /* Setup MSI or MSI/X */ 2213 static int 2214 em_setup_msix(if_ctx_t ctx) 2215 { 2216 struct adapter *adapter = iflib_get_softc(ctx); 2217 2218 if (adapter->hw.mac.type == e1000_82574) { 2219 em_enable_vectors_82574(ctx); 2220 } 2221 return (0); 2222 } 2223 2224 /********************************************************************* 2225 * 2226 * Initialize the hardware to a configuration 2227 * as specified by the adapter structure. 2228 * 2229 **********************************************************************/ 2230 2231 static void 2232 lem_smartspeed(struct adapter *adapter) 2233 { 2234 u16 phy_tmp; 2235 2236 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2237 adapter->hw.mac.autoneg == 0 || 2238 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2239 return; 2240 2241 if (adapter->smartspeed == 0) { 2242 /* If Master/Slave config fault is asserted twice, 2243 * we assume back-to-back */ 2244 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2245 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2246 return; 2247 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2248 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2249 e1000_read_phy_reg(&adapter->hw, 2250 PHY_1000T_CTRL, &phy_tmp); 2251 if(phy_tmp & CR_1000T_MS_ENABLE) { 2252 phy_tmp &= ~CR_1000T_MS_ENABLE; 2253 e1000_write_phy_reg(&adapter->hw, 2254 PHY_1000T_CTRL, phy_tmp); 2255 adapter->smartspeed++; 2256 if(adapter->hw.mac.autoneg && 2257 !e1000_copper_link_autoneg(&adapter->hw) && 2258 !e1000_read_phy_reg(&adapter->hw, 2259 PHY_CONTROL, &phy_tmp)) { 2260 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2261 MII_CR_RESTART_AUTO_NEG); 2262 e1000_write_phy_reg(&adapter->hw, 2263 PHY_CONTROL, phy_tmp); 2264 } 2265 } 2266 } 2267 return; 2268 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2269 /* If still no link, perhaps using 2/3 pair cable */ 2270 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2271 phy_tmp |= CR_1000T_MS_ENABLE; 2272 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2273 if(adapter->hw.mac.autoneg && 2274 !e1000_copper_link_autoneg(&adapter->hw) && 2275 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2276 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2277 MII_CR_RESTART_AUTO_NEG); 2278 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2279 } 2280 } 2281 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2282 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2283 adapter->smartspeed = 0; 2284 } 2285 2286 /********************************************************************* 2287 * 2288 * Initialize the DMA Coalescing feature 2289 * 2290 **********************************************************************/ 2291 static void 2292 igb_init_dmac(struct adapter *adapter, u32 pba) 2293 { 2294 device_t dev = adapter->dev; 2295 struct e1000_hw *hw = &adapter->hw; 2296 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2297 u16 hwm; 2298 u16 max_frame_size; 2299 2300 if (hw->mac.type == e1000_i211) 2301 return; 2302 2303 max_frame_size = adapter->shared->isc_max_frame_size; 2304 if (hw->mac.type > e1000_82580) { 2305 2306 if (adapter->dmac == 0) { /* Disabling it */ 2307 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2308 return; 2309 } else 2310 device_printf(dev, "DMA Coalescing enabled\n"); 2311 2312 /* Set starting threshold */ 2313 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2314 2315 hwm = 64 * pba - max_frame_size / 16; 2316 if (hwm < 64 * (pba - 6)) 2317 hwm = 64 * (pba - 6); 2318 reg = E1000_READ_REG(hw, E1000_FCRTC); 2319 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2320 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2321 & E1000_FCRTC_RTH_COAL_MASK); 2322 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2323 2324 2325 dmac = pba - max_frame_size / 512; 2326 if (dmac < pba - 10) 2327 dmac = pba - 10; 2328 reg = E1000_READ_REG(hw, E1000_DMACR); 2329 reg &= ~E1000_DMACR_DMACTHR_MASK; 2330 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2331 & E1000_DMACR_DMACTHR_MASK); 2332 2333 /* transition to L0x or L1 if available..*/ 2334 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2335 2336 /* Check if status is 2.5Gb backplane connection 2337 * before configuration of watchdog timer, which is 2338 * in msec values in 12.8usec intervals 2339 * watchdog timer= msec values in 32usec intervals 2340 * for non 2.5Gb connection 2341 */ 2342 if (hw->mac.type == e1000_i354) { 2343 int status = E1000_READ_REG(hw, E1000_STATUS); 2344 if ((status & E1000_STATUS_2P5_SKU) && 2345 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2346 reg |= ((adapter->dmac * 5) >> 6); 2347 else 2348 reg |= (adapter->dmac >> 5); 2349 } else { 2350 reg |= (adapter->dmac >> 5); 2351 } 2352 2353 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2354 2355 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2356 2357 /* Set the interval before transition */ 2358 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2359 if (hw->mac.type == e1000_i350) 2360 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2361 /* 2362 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2363 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2364 */ 2365 if (hw->mac.type == e1000_i354) { 2366 int status = E1000_READ_REG(hw, E1000_STATUS); 2367 if ((status & E1000_STATUS_2P5_SKU) && 2368 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2369 reg |= 0xA; 2370 else 2371 reg |= 0x4; 2372 } else { 2373 reg |= 0x4; 2374 } 2375 2376 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2377 2378 /* free space in tx packet buffer to wake from DMA coal */ 2379 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2380 (2 * max_frame_size)) >> 6); 2381 2382 /* make low power state decision controlled by DMA coal */ 2383 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2384 reg &= ~E1000_PCIEMISC_LX_DECISION; 2385 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2386 2387 } else if (hw->mac.type == e1000_82580) { 2388 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2389 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2390 reg & ~E1000_PCIEMISC_LX_DECISION); 2391 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2392 } 2393 } 2394 2395 static void 2396 em_reset(if_ctx_t ctx) 2397 { 2398 device_t dev = iflib_get_dev(ctx); 2399 struct adapter *adapter = iflib_get_softc(ctx); 2400 struct ifnet *ifp = iflib_get_ifp(ctx); 2401 struct e1000_hw *hw = &adapter->hw; 2402 u16 rx_buffer_size; 2403 u32 pba; 2404 2405 INIT_DEBUGOUT("em_reset: begin"); 2406 /* Let the firmware know the OS is in control */ 2407 em_get_hw_control(adapter); 2408 2409 /* Set up smart power down as default off on newer adapters. */ 2410 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2411 hw->mac.type == e1000_82572)) { 2412 u16 phy_tmp = 0; 2413 2414 /* Speed up time to link by disabling smart power down. */ 2415 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2416 phy_tmp &= ~IGP02E1000_PM_SPD; 2417 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2418 } 2419 2420 /* 2421 * Packet Buffer Allocation (PBA) 2422 * Writing PBA sets the receive portion of the buffer 2423 * the remainder is used for the transmit buffer. 2424 */ 2425 switch (hw->mac.type) { 2426 /* Total Packet Buffer on these is 48K */ 2427 case e1000_82571: 2428 case e1000_82572: 2429 case e1000_80003es2lan: 2430 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2431 break; 2432 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2433 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2434 break; 2435 case e1000_82574: 2436 case e1000_82583: 2437 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2438 break; 2439 case e1000_ich8lan: 2440 pba = E1000_PBA_8K; 2441 break; 2442 case e1000_ich9lan: 2443 case e1000_ich10lan: 2444 /* Boost Receive side for jumbo frames */ 2445 if (adapter->hw.mac.max_frame_size > 4096) 2446 pba = E1000_PBA_14K; 2447 else 2448 pba = E1000_PBA_10K; 2449 break; 2450 case e1000_pchlan: 2451 case e1000_pch2lan: 2452 case e1000_pch_lpt: 2453 case e1000_pch_spt: 2454 case e1000_pch_cnp: 2455 pba = E1000_PBA_26K; 2456 break; 2457 case e1000_82575: 2458 pba = E1000_PBA_32K; 2459 break; 2460 case e1000_82576: 2461 case e1000_vfadapt: 2462 pba = E1000_READ_REG(hw, E1000_RXPBS); 2463 pba &= E1000_RXPBS_SIZE_MASK_82576; 2464 break; 2465 case e1000_82580: 2466 case e1000_i350: 2467 case e1000_i354: 2468 case e1000_vfadapt_i350: 2469 pba = E1000_READ_REG(hw, E1000_RXPBS); 2470 pba = e1000_rxpbs_adjust_82580(pba); 2471 break; 2472 case e1000_i210: 2473 case e1000_i211: 2474 pba = E1000_PBA_34K; 2475 break; 2476 default: 2477 if (adapter->hw.mac.max_frame_size > 8192) 2478 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2479 else 2480 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2481 } 2482 2483 /* Special needs in case of Jumbo frames */ 2484 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2485 u32 tx_space, min_tx, min_rx; 2486 pba = E1000_READ_REG(hw, E1000_PBA); 2487 tx_space = pba >> 16; 2488 pba &= 0xffff; 2489 min_tx = (adapter->hw.mac.max_frame_size + 2490 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2491 min_tx = roundup2(min_tx, 1024); 2492 min_tx >>= 10; 2493 min_rx = adapter->hw.mac.max_frame_size; 2494 min_rx = roundup2(min_rx, 1024); 2495 min_rx >>= 10; 2496 if (tx_space < min_tx && 2497 ((min_tx - tx_space) < pba)) { 2498 pba = pba - (min_tx - tx_space); 2499 /* 2500 * if short on rx space, rx wins 2501 * and must trump tx adjustment 2502 */ 2503 if (pba < min_rx) 2504 pba = min_rx; 2505 } 2506 E1000_WRITE_REG(hw, E1000_PBA, pba); 2507 } 2508 2509 if (hw->mac.type < igb_mac_min) 2510 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2511 2512 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2513 2514 /* 2515 * These parameters control the automatic generation (Tx) and 2516 * response (Rx) to Ethernet PAUSE frames. 2517 * - High water mark should allow for at least two frames to be 2518 * received after sending an XOFF. 2519 * - Low water mark works best when it is very near the high water mark. 2520 * This allows the receiver to restart by sending XON when it has 2521 * drained a bit. Here we use an arbitrary value of 1500 which will 2522 * restart after one full frame is pulled from the buffer. There 2523 * could be several smaller frames in the buffer and if so they will 2524 * not trigger the XON until their total number reduces the buffer 2525 * by 1500. 2526 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2527 */ 2528 rx_buffer_size = (pba & 0xffff) << 10; 2529 hw->fc.high_water = rx_buffer_size - 2530 roundup2(adapter->hw.mac.max_frame_size, 1024); 2531 hw->fc.low_water = hw->fc.high_water - 1500; 2532 2533 if (adapter->fc) /* locally set flow control value? */ 2534 hw->fc.requested_mode = adapter->fc; 2535 else 2536 hw->fc.requested_mode = e1000_fc_full; 2537 2538 if (hw->mac.type == e1000_80003es2lan) 2539 hw->fc.pause_time = 0xFFFF; 2540 else 2541 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2542 2543 hw->fc.send_xon = TRUE; 2544 2545 /* Device specific overrides/settings */ 2546 switch (hw->mac.type) { 2547 case e1000_pchlan: 2548 /* Workaround: no TX flow ctrl for PCH */ 2549 hw->fc.requested_mode = e1000_fc_rx_pause; 2550 hw->fc.pause_time = 0xFFFF; /* override */ 2551 if (if_getmtu(ifp) > ETHERMTU) { 2552 hw->fc.high_water = 0x3500; 2553 hw->fc.low_water = 0x1500; 2554 } else { 2555 hw->fc.high_water = 0x5000; 2556 hw->fc.low_water = 0x3000; 2557 } 2558 hw->fc.refresh_time = 0x1000; 2559 break; 2560 case e1000_pch2lan: 2561 case e1000_pch_lpt: 2562 case e1000_pch_spt: 2563 case e1000_pch_cnp: 2564 hw->fc.high_water = 0x5C20; 2565 hw->fc.low_water = 0x5048; 2566 hw->fc.pause_time = 0x0650; 2567 hw->fc.refresh_time = 0x0400; 2568 /* Jumbos need adjusted PBA */ 2569 if (if_getmtu(ifp) > ETHERMTU) 2570 E1000_WRITE_REG(hw, E1000_PBA, 12); 2571 else 2572 E1000_WRITE_REG(hw, E1000_PBA, 26); 2573 break; 2574 case e1000_82575: 2575 case e1000_82576: 2576 /* 8-byte granularity */ 2577 hw->fc.low_water = hw->fc.high_water - 8; 2578 break; 2579 case e1000_82580: 2580 case e1000_i350: 2581 case e1000_i354: 2582 case e1000_i210: 2583 case e1000_i211: 2584 case e1000_vfadapt: 2585 case e1000_vfadapt_i350: 2586 /* 16-byte granularity */ 2587 hw->fc.low_water = hw->fc.high_water - 16; 2588 break; 2589 case e1000_ich9lan: 2590 case e1000_ich10lan: 2591 if (if_getmtu(ifp) > ETHERMTU) { 2592 hw->fc.high_water = 0x2800; 2593 hw->fc.low_water = hw->fc.high_water - 8; 2594 break; 2595 } 2596 /* FALLTHROUGH */ 2597 default: 2598 if (hw->mac.type == e1000_80003es2lan) 2599 hw->fc.pause_time = 0xFFFF; 2600 break; 2601 } 2602 2603 /* Issue a global reset */ 2604 e1000_reset_hw(hw); 2605 if (adapter->hw.mac.type >= igb_mac_min) { 2606 E1000_WRITE_REG(hw, E1000_WUC, 0); 2607 } else { 2608 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2609 em_disable_aspm(adapter); 2610 } 2611 if (adapter->flags & IGB_MEDIA_RESET) { 2612 e1000_setup_init_funcs(hw, TRUE); 2613 e1000_get_bus_info(hw); 2614 adapter->flags &= ~IGB_MEDIA_RESET; 2615 } 2616 /* and a re-init */ 2617 if (e1000_init_hw(hw) < 0) { 2618 device_printf(dev, "Hardware Initialization Failed\n"); 2619 return; 2620 } 2621 if (adapter->hw.mac.type >= igb_mac_min) 2622 igb_init_dmac(adapter, pba); 2623 2624 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2625 e1000_get_phy_info(hw); 2626 e1000_check_for_link(hw); 2627 } 2628 2629 #define RSSKEYLEN 10 2630 static void 2631 em_initialize_rss_mapping(struct adapter *adapter) 2632 { 2633 uint8_t rss_key[4 * RSSKEYLEN]; 2634 uint32_t reta = 0; 2635 struct e1000_hw *hw = &adapter->hw; 2636 int i; 2637 2638 /* 2639 * Configure RSS key 2640 */ 2641 arc4rand(rss_key, sizeof(rss_key), 0); 2642 for (i = 0; i < RSSKEYLEN; ++i) { 2643 uint32_t rssrk = 0; 2644 2645 rssrk = EM_RSSRK_VAL(rss_key, i); 2646 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2647 } 2648 2649 /* 2650 * Configure RSS redirect table in following fashion: 2651 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2652 */ 2653 for (i = 0; i < sizeof(reta); ++i) { 2654 uint32_t q; 2655 2656 q = (i % adapter->rx_num_queues) << 7; 2657 reta |= q << (8 * i); 2658 } 2659 2660 for (i = 0; i < 32; ++i) 2661 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2662 2663 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2664 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2665 E1000_MRQC_RSS_FIELD_IPV4 | 2666 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2667 E1000_MRQC_RSS_FIELD_IPV6_EX | 2668 E1000_MRQC_RSS_FIELD_IPV6); 2669 2670 } 2671 2672 static void 2673 igb_initialize_rss_mapping(struct adapter *adapter) 2674 { 2675 struct e1000_hw *hw = &adapter->hw; 2676 int i; 2677 int queue_id; 2678 u32 reta; 2679 u32 rss_key[10], mrqc, shift = 0; 2680 2681 /* XXX? */ 2682 if (adapter->hw.mac.type == e1000_82575) 2683 shift = 6; 2684 2685 /* 2686 * The redirection table controls which destination 2687 * queue each bucket redirects traffic to. 2688 * Each DWORD represents four queues, with the LSB 2689 * being the first queue in the DWORD. 2690 * 2691 * This just allocates buckets to queues using round-robin 2692 * allocation. 2693 * 2694 * NOTE: It Just Happens to line up with the default 2695 * RSS allocation method. 2696 */ 2697 2698 /* Warning FM follows */ 2699 reta = 0; 2700 for (i = 0; i < 128; i++) { 2701 #ifdef RSS 2702 queue_id = rss_get_indirection_to_bucket(i); 2703 /* 2704 * If we have more queues than buckets, we'll 2705 * end up mapping buckets to a subset of the 2706 * queues. 2707 * 2708 * If we have more buckets than queues, we'll 2709 * end up instead assigning multiple buckets 2710 * to queues. 2711 * 2712 * Both are suboptimal, but we need to handle 2713 * the case so we don't go out of bounds 2714 * indexing arrays and such. 2715 */ 2716 queue_id = queue_id % adapter->rx_num_queues; 2717 #else 2718 queue_id = (i % adapter->rx_num_queues); 2719 #endif 2720 /* Adjust if required */ 2721 queue_id = queue_id << shift; 2722 2723 /* 2724 * The low 8 bits are for hash value (n+0); 2725 * The next 8 bits are for hash value (n+1), etc. 2726 */ 2727 reta = reta >> 8; 2728 reta = reta | ( ((uint32_t) queue_id) << 24); 2729 if ((i & 3) == 3) { 2730 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2731 reta = 0; 2732 } 2733 } 2734 2735 /* Now fill in hash table */ 2736 2737 /* 2738 * MRQC: Multiple Receive Queues Command 2739 * Set queuing to RSS control, number depends on the device. 2740 */ 2741 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2742 2743 #ifdef RSS 2744 /* XXX ew typecasting */ 2745 rss_getkey((uint8_t *) &rss_key); 2746 #else 2747 arc4rand(&rss_key, sizeof(rss_key), 0); 2748 #endif 2749 for (i = 0; i < 10; i++) 2750 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2751 2752 /* 2753 * Configure the RSS fields to hash upon. 2754 */ 2755 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2756 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2757 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2758 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2759 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2760 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2761 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2762 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2763 2764 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2765 } 2766 2767 /********************************************************************* 2768 * 2769 * Setup networking device structure and register an interface. 2770 * 2771 **********************************************************************/ 2772 static int 2773 em_setup_interface(if_ctx_t ctx) 2774 { 2775 struct ifnet *ifp = iflib_get_ifp(ctx); 2776 struct adapter *adapter = iflib_get_softc(ctx); 2777 if_softc_ctx_t scctx = adapter->shared; 2778 2779 INIT_DEBUGOUT("em_setup_interface: begin"); 2780 2781 /* Single Queue */ 2782 if (adapter->tx_num_queues == 1) { 2783 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2784 if_setsendqready(ifp); 2785 } 2786 2787 /* 2788 * Specify the media types supported by this adapter and register 2789 * callbacks to update media and link information 2790 */ 2791 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2792 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2793 u_char fiber_type = IFM_1000_SX; /* default type */ 2794 2795 if (adapter->hw.mac.type == e1000_82545) 2796 fiber_type = IFM_1000_LX; 2797 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2798 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2799 } else { 2800 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2801 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2802 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2803 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2804 if (adapter->hw.phy.type != e1000_phy_ife) { 2805 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2806 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2807 } 2808 } 2809 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2810 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2811 return (0); 2812 } 2813 2814 static int 2815 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2816 { 2817 struct adapter *adapter = iflib_get_softc(ctx); 2818 if_softc_ctx_t scctx = adapter->shared; 2819 int error = E1000_SUCCESS; 2820 struct em_tx_queue *que; 2821 int i, j; 2822 2823 MPASS(adapter->tx_num_queues > 0); 2824 MPASS(adapter->tx_num_queues == ntxqsets); 2825 2826 /* First allocate the top level queue structs */ 2827 if (!(adapter->tx_queues = 2828 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2829 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2830 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2831 return(ENOMEM); 2832 } 2833 2834 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2835 /* Set up some basics */ 2836 2837 struct tx_ring *txr = &que->txr; 2838 txr->adapter = que->adapter = adapter; 2839 que->me = txr->me = i; 2840 2841 /* Allocate report status array */ 2842 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2843 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2844 error = ENOMEM; 2845 goto fail; 2846 } 2847 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2848 txr->tx_rsq[j] = QIDX_INVALID; 2849 /* get the virtual and physical address of the hardware queues */ 2850 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2851 txr->tx_paddr = paddrs[i*ntxqs]; 2852 } 2853 2854 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2855 return (0); 2856 fail: 2857 em_if_queues_free(ctx); 2858 return (error); 2859 } 2860 2861 static int 2862 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2863 { 2864 struct adapter *adapter = iflib_get_softc(ctx); 2865 int error = E1000_SUCCESS; 2866 struct em_rx_queue *que; 2867 int i; 2868 2869 MPASS(adapter->rx_num_queues > 0); 2870 MPASS(adapter->rx_num_queues == nrxqsets); 2871 2872 /* First allocate the top level queue structs */ 2873 if (!(adapter->rx_queues = 2874 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2875 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2876 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2877 error = ENOMEM; 2878 goto fail; 2879 } 2880 2881 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2882 /* Set up some basics */ 2883 struct rx_ring *rxr = &que->rxr; 2884 rxr->adapter = que->adapter = adapter; 2885 rxr->que = que; 2886 que->me = rxr->me = i; 2887 2888 /* get the virtual and physical address of the hardware queues */ 2889 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2890 rxr->rx_paddr = paddrs[i*nrxqs]; 2891 } 2892 2893 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2894 2895 return (0); 2896 fail: 2897 em_if_queues_free(ctx); 2898 return (error); 2899 } 2900 2901 static void 2902 em_if_queues_free(if_ctx_t ctx) 2903 { 2904 struct adapter *adapter = iflib_get_softc(ctx); 2905 struct em_tx_queue *tx_que = adapter->tx_queues; 2906 struct em_rx_queue *rx_que = adapter->rx_queues; 2907 2908 if (tx_que != NULL) { 2909 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2910 struct tx_ring *txr = &tx_que->txr; 2911 if (txr->tx_rsq == NULL) 2912 break; 2913 2914 free(txr->tx_rsq, M_DEVBUF); 2915 txr->tx_rsq = NULL; 2916 } 2917 free(adapter->tx_queues, M_DEVBUF); 2918 adapter->tx_queues = NULL; 2919 } 2920 2921 if (rx_que != NULL) { 2922 free(adapter->rx_queues, M_DEVBUF); 2923 adapter->rx_queues = NULL; 2924 } 2925 2926 em_release_hw_control(adapter); 2927 2928 if (adapter->mta != NULL) { 2929 free(adapter->mta, M_DEVBUF); 2930 } 2931 } 2932 2933 /********************************************************************* 2934 * 2935 * Enable transmit unit. 2936 * 2937 **********************************************************************/ 2938 static void 2939 em_initialize_transmit_unit(if_ctx_t ctx) 2940 { 2941 struct adapter *adapter = iflib_get_softc(ctx); 2942 if_softc_ctx_t scctx = adapter->shared; 2943 struct em_tx_queue *que; 2944 struct tx_ring *txr; 2945 struct e1000_hw *hw = &adapter->hw; 2946 u32 tctl, txdctl = 0, tarc, tipg = 0; 2947 2948 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2949 2950 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2951 u64 bus_addr; 2952 caddr_t offp, endp; 2953 2954 que = &adapter->tx_queues[i]; 2955 txr = &que->txr; 2956 bus_addr = txr->tx_paddr; 2957 2958 /* Clear checksum offload context. */ 2959 offp = (caddr_t)&txr->csum_flags; 2960 endp = (caddr_t)(txr + 1); 2961 bzero(offp, endp - offp); 2962 2963 /* Base and Len of TX Ring */ 2964 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2965 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2966 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2967 (u32)(bus_addr >> 32)); 2968 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2969 (u32)bus_addr); 2970 /* Init the HEAD/TAIL indices */ 2971 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2972 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2973 2974 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2975 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2976 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2977 2978 txdctl = 0; /* clear txdctl */ 2979 txdctl |= 0x1f; /* PTHRESH */ 2980 txdctl |= 1 << 8; /* HTHRESH */ 2981 txdctl |= 1 << 16;/* WTHRESH */ 2982 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2983 txdctl |= E1000_TXDCTL_GRAN; 2984 txdctl |= 1 << 25; /* LWTHRESH */ 2985 2986 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2987 } 2988 2989 /* Set the default values for the Tx Inter Packet Gap timer */ 2990 switch (adapter->hw.mac.type) { 2991 case e1000_80003es2lan: 2992 tipg = DEFAULT_82543_TIPG_IPGR1; 2993 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2994 E1000_TIPG_IPGR2_SHIFT; 2995 break; 2996 case e1000_82542: 2997 tipg = DEFAULT_82542_TIPG_IPGT; 2998 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2999 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3000 break; 3001 default: 3002 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3003 (adapter->hw.phy.media_type == 3004 e1000_media_type_internal_serdes)) 3005 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3006 else 3007 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3008 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3009 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3010 } 3011 3012 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3013 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3014 3015 if(adapter->hw.mac.type >= e1000_82540) 3016 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3017 adapter->tx_abs_int_delay.value); 3018 3019 if ((adapter->hw.mac.type == e1000_82571) || 3020 (adapter->hw.mac.type == e1000_82572)) { 3021 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3022 tarc |= TARC_SPEED_MODE_BIT; 3023 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3024 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3025 /* errata: program both queues to unweighted RR */ 3026 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3027 tarc |= 1; 3028 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3029 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3030 tarc |= 1; 3031 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3032 } else if (adapter->hw.mac.type == e1000_82574) { 3033 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3034 tarc |= TARC_ERRATA_BIT; 3035 if ( adapter->tx_num_queues > 1) { 3036 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3037 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3038 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3039 } else 3040 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3041 } 3042 3043 if (adapter->tx_int_delay.value > 0) 3044 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3045 3046 /* Program the Transmit Control Register */ 3047 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3048 tctl &= ~E1000_TCTL_CT; 3049 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3050 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3051 3052 if (adapter->hw.mac.type >= e1000_82571) 3053 tctl |= E1000_TCTL_MULR; 3054 3055 /* This write will effectively turn on the transmit unit. */ 3056 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3057 3058 /* SPT and KBL errata workarounds */ 3059 if (hw->mac.type == e1000_pch_spt) { 3060 u32 reg; 3061 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3062 reg |= E1000_RCTL_RDMTS_HEX; 3063 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3064 /* i218-i219 Specification Update 1.5.4.5 */ 3065 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3066 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3067 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3068 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3069 } 3070 } 3071 3072 /********************************************************************* 3073 * 3074 * Enable receive unit. 3075 * 3076 **********************************************************************/ 3077 3078 static void 3079 em_initialize_receive_unit(if_ctx_t ctx) 3080 { 3081 struct adapter *adapter = iflib_get_softc(ctx); 3082 if_softc_ctx_t scctx = adapter->shared; 3083 struct ifnet *ifp = iflib_get_ifp(ctx); 3084 struct e1000_hw *hw = &adapter->hw; 3085 struct em_rx_queue *que; 3086 int i; 3087 u32 rctl, rxcsum, rfctl; 3088 3089 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3090 3091 /* 3092 * Make sure receives are disabled while setting 3093 * up the descriptor ring 3094 */ 3095 rctl = E1000_READ_REG(hw, E1000_RCTL); 3096 /* Do not disable if ever enabled on this hardware */ 3097 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3098 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3099 3100 /* Setup the Receive Control Register */ 3101 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3102 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3103 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3104 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3105 3106 /* Do not store bad packets */ 3107 rctl &= ~E1000_RCTL_SBP; 3108 3109 /* Enable Long Packet receive */ 3110 if (if_getmtu(ifp) > ETHERMTU) 3111 rctl |= E1000_RCTL_LPE; 3112 else 3113 rctl &= ~E1000_RCTL_LPE; 3114 3115 /* Strip the CRC */ 3116 if (!em_disable_crc_stripping) 3117 rctl |= E1000_RCTL_SECRC; 3118 3119 if (adapter->hw.mac.type >= e1000_82540) { 3120 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3121 adapter->rx_abs_int_delay.value); 3122 3123 /* 3124 * Set the interrupt throttling rate. Value is calculated 3125 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3126 */ 3127 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3128 } 3129 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3130 adapter->rx_int_delay.value); 3131 3132 /* Use extended rx descriptor formats */ 3133 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3134 rfctl |= E1000_RFCTL_EXTEN; 3135 /* 3136 * When using MSIX interrupts we need to throttle 3137 * using the EITR register (82574 only) 3138 */ 3139 if (hw->mac.type == e1000_82574) { 3140 for (int i = 0; i < 4; i++) 3141 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3142 DEFAULT_ITR); 3143 /* Disable accelerated acknowledge */ 3144 rfctl |= E1000_RFCTL_ACK_DIS; 3145 } 3146 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3147 3148 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3149 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3150 adapter->hw.mac.type >= e1000_82543) { 3151 if (adapter->tx_num_queues > 1) { 3152 if (adapter->hw.mac.type >= igb_mac_min) { 3153 rxcsum |= E1000_RXCSUM_PCSD; 3154 if (hw->mac.type != e1000_82575) 3155 rxcsum |= E1000_RXCSUM_CRCOFL; 3156 } else 3157 rxcsum |= E1000_RXCSUM_TUOFL | 3158 E1000_RXCSUM_IPOFL | 3159 E1000_RXCSUM_PCSD; 3160 } else { 3161 if (adapter->hw.mac.type >= igb_mac_min) 3162 rxcsum |= E1000_RXCSUM_IPPCSE; 3163 else 3164 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3165 if (adapter->hw.mac.type > e1000_82575) 3166 rxcsum |= E1000_RXCSUM_CRCOFL; 3167 } 3168 } else 3169 rxcsum &= ~E1000_RXCSUM_TUOFL; 3170 3171 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3172 3173 if (adapter->rx_num_queues > 1) { 3174 if (adapter->hw.mac.type >= igb_mac_min) 3175 igb_initialize_rss_mapping(adapter); 3176 else 3177 em_initialize_rss_mapping(adapter); 3178 } 3179 3180 /* 3181 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3182 * long latencies are observed, like Lenovo X60. This 3183 * change eliminates the problem, but since having positive 3184 * values in RDTR is a known source of problems on other 3185 * platforms another solution is being sought. 3186 */ 3187 if (hw->mac.type == e1000_82573) 3188 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3189 3190 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3191 struct rx_ring *rxr = &que->rxr; 3192 /* Setup the Base and Length of the Rx Descriptor Ring */ 3193 u64 bus_addr = rxr->rx_paddr; 3194 #if 0 3195 u32 rdt = adapter->rx_num_queues -1; /* default */ 3196 #endif 3197 3198 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3199 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3200 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3201 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3202 /* Setup the Head and Tail Descriptor Pointers */ 3203 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3204 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3205 } 3206 3207 /* 3208 * Set PTHRESH for improved jumbo performance 3209 * According to 10.2.5.11 of Intel 82574 Datasheet, 3210 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3211 * Only write to RXDCTL(1) if there is a need for different 3212 * settings. 3213 */ 3214 3215 if (((adapter->hw.mac.type == e1000_ich9lan) || 3216 (adapter->hw.mac.type == e1000_pch2lan) || 3217 (adapter->hw.mac.type == e1000_ich10lan)) && 3218 (if_getmtu(ifp) > ETHERMTU)) { 3219 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3220 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3221 } else if (adapter->hw.mac.type == e1000_82574) { 3222 for (int i = 0; i < adapter->rx_num_queues; i++) { 3223 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3224 rxdctl |= 0x20; /* PTHRESH */ 3225 rxdctl |= 4 << 8; /* HTHRESH */ 3226 rxdctl |= 4 << 16;/* WTHRESH */ 3227 rxdctl |= 1 << 24; /* Switch to granularity */ 3228 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3229 } 3230 } else if (adapter->hw.mac.type >= igb_mac_min) { 3231 u32 psize, srrctl = 0; 3232 3233 if (if_getmtu(ifp) > ETHERMTU) { 3234 /* Set maximum packet len */ 3235 if (adapter->rx_mbuf_sz <= 4096) { 3236 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3237 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3238 } else if (adapter->rx_mbuf_sz > 4096) { 3239 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3240 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3241 } 3242 psize = scctx->isc_max_frame_size; 3243 /* are we on a vlan? */ 3244 if (ifp->if_vlantrunk != NULL) 3245 psize += VLAN_TAG_SIZE; 3246 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3247 } else { 3248 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3249 rctl |= E1000_RCTL_SZ_2048; 3250 } 3251 3252 /* 3253 * If TX flow control is disabled and there's >1 queue defined, 3254 * enable DROP. 3255 * 3256 * This drops frames rather than hanging the RX MAC for all queues. 3257 */ 3258 if ((adapter->rx_num_queues > 1) && 3259 (adapter->fc == e1000_fc_none || 3260 adapter->fc == e1000_fc_rx_pause)) { 3261 srrctl |= E1000_SRRCTL_DROP_EN; 3262 } 3263 /* Setup the Base and Length of the Rx Descriptor Rings */ 3264 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3265 struct rx_ring *rxr = &que->rxr; 3266 u64 bus_addr = rxr->rx_paddr; 3267 u32 rxdctl; 3268 3269 #ifdef notyet 3270 /* Configure for header split? -- ignore for now */ 3271 rxr->hdr_split = igb_header_split; 3272 #else 3273 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3274 #endif 3275 3276 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3277 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3278 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3279 (uint32_t)(bus_addr >> 32)); 3280 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3281 (uint32_t)bus_addr); 3282 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3283 /* Enable this Queue */ 3284 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3285 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3286 rxdctl &= 0xFFF00000; 3287 rxdctl |= IGB_RX_PTHRESH; 3288 rxdctl |= IGB_RX_HTHRESH << 8; 3289 rxdctl |= IGB_RX_WTHRESH << 16; 3290 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3291 } 3292 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3293 if (if_getmtu(ifp) > ETHERMTU) 3294 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3295 else 3296 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3297 } 3298 3299 /* Make sure VLAN Filters are off */ 3300 rctl &= ~E1000_RCTL_VFE; 3301 3302 if (adapter->hw.mac.type < igb_mac_min) { 3303 if (adapter->rx_mbuf_sz == MCLBYTES) 3304 rctl |= E1000_RCTL_SZ_2048; 3305 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3306 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3307 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3308 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3309 3310 /* ensure we clear use DTYPE of 00 here */ 3311 rctl &= ~0x00000C00; 3312 } 3313 3314 /* Write out the settings */ 3315 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3316 3317 return; 3318 } 3319 3320 static void 3321 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3322 { 3323 struct adapter *adapter = iflib_get_softc(ctx); 3324 u32 index, bit; 3325 3326 index = (vtag >> 5) & 0x7F; 3327 bit = vtag & 0x1F; 3328 adapter->shadow_vfta[index] |= (1 << bit); 3329 ++adapter->num_vlans; 3330 } 3331 3332 static void 3333 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3334 { 3335 struct adapter *adapter = iflib_get_softc(ctx); 3336 u32 index, bit; 3337 3338 index = (vtag >> 5) & 0x7F; 3339 bit = vtag & 0x1F; 3340 adapter->shadow_vfta[index] &= ~(1 << bit); 3341 --adapter->num_vlans; 3342 } 3343 3344 static void 3345 em_setup_vlan_hw_support(struct adapter *adapter) 3346 { 3347 struct e1000_hw *hw = &adapter->hw; 3348 u32 reg; 3349 3350 /* 3351 * We get here thru init_locked, meaning 3352 * a soft reset, this has already cleared 3353 * the VFTA and other state, so if there 3354 * have been no vlan's registered do nothing. 3355 */ 3356 if (adapter->num_vlans == 0) 3357 return; 3358 3359 /* 3360 * A soft reset zero's out the VFTA, so 3361 * we need to repopulate it now. 3362 */ 3363 for (int i = 0; i < EM_VFTA_SIZE; i++) 3364 if (adapter->shadow_vfta[i] != 0) 3365 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3366 i, adapter->shadow_vfta[i]); 3367 3368 reg = E1000_READ_REG(hw, E1000_CTRL); 3369 reg |= E1000_CTRL_VME; 3370 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3371 3372 /* Enable the Filter Table */ 3373 reg = E1000_READ_REG(hw, E1000_RCTL); 3374 reg &= ~E1000_RCTL_CFIEN; 3375 reg |= E1000_RCTL_VFE; 3376 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3377 } 3378 3379 static void 3380 em_if_enable_intr(if_ctx_t ctx) 3381 { 3382 struct adapter *adapter = iflib_get_softc(ctx); 3383 struct e1000_hw *hw = &adapter->hw; 3384 u32 ims_mask = IMS_ENABLE_MASK; 3385 3386 if (hw->mac.type == e1000_82574) { 3387 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3388 ims_mask |= adapter->ims; 3389 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3390 u32 mask = (adapter->que_mask | adapter->link_mask); 3391 3392 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3393 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3394 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3395 ims_mask = E1000_IMS_LSC; 3396 } 3397 3398 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3399 } 3400 3401 static void 3402 em_if_disable_intr(if_ctx_t ctx) 3403 { 3404 struct adapter *adapter = iflib_get_softc(ctx); 3405 struct e1000_hw *hw = &adapter->hw; 3406 3407 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3408 if (hw->mac.type >= igb_mac_min) 3409 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3410 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3411 } 3412 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3413 } 3414 3415 /* 3416 * Bit of a misnomer, what this really means is 3417 * to enable OS management of the system... aka 3418 * to disable special hardware management features 3419 */ 3420 static void 3421 em_init_manageability(struct adapter *adapter) 3422 { 3423 /* A shared code workaround */ 3424 #define E1000_82542_MANC2H E1000_MANC2H 3425 if (adapter->has_manage) { 3426 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3427 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3428 3429 /* disable hardware interception of ARP */ 3430 manc &= ~(E1000_MANC_ARP_EN); 3431 3432 /* enable receiving management packets to the host */ 3433 manc |= E1000_MANC_EN_MNG2HOST; 3434 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3435 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3436 manc2h |= E1000_MNG2HOST_PORT_623; 3437 manc2h |= E1000_MNG2HOST_PORT_664; 3438 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3439 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3440 } 3441 } 3442 3443 /* 3444 * Give control back to hardware management 3445 * controller if there is one. 3446 */ 3447 static void 3448 em_release_manageability(struct adapter *adapter) 3449 { 3450 if (adapter->has_manage) { 3451 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3452 3453 /* re-enable hardware interception of ARP */ 3454 manc |= E1000_MANC_ARP_EN; 3455 manc &= ~E1000_MANC_EN_MNG2HOST; 3456 3457 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3458 } 3459 } 3460 3461 /* 3462 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3463 * For ASF and Pass Through versions of f/w this means 3464 * that the driver is loaded. For AMT version type f/w 3465 * this means that the network i/f is open. 3466 */ 3467 static void 3468 em_get_hw_control(struct adapter *adapter) 3469 { 3470 u32 ctrl_ext, swsm; 3471 3472 if (adapter->vf_ifp) 3473 return; 3474 3475 if (adapter->hw.mac.type == e1000_82573) { 3476 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3477 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3478 swsm | E1000_SWSM_DRV_LOAD); 3479 return; 3480 } 3481 /* else */ 3482 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3483 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3484 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3485 } 3486 3487 /* 3488 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3489 * For ASF and Pass Through versions of f/w this means that 3490 * the driver is no longer loaded. For AMT versions of the 3491 * f/w this means that the network i/f is closed. 3492 */ 3493 static void 3494 em_release_hw_control(struct adapter *adapter) 3495 { 3496 u32 ctrl_ext, swsm; 3497 3498 if (!adapter->has_manage) 3499 return; 3500 3501 if (adapter->hw.mac.type == e1000_82573) { 3502 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3503 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3504 swsm & ~E1000_SWSM_DRV_LOAD); 3505 return; 3506 } 3507 /* else */ 3508 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3509 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3510 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3511 return; 3512 } 3513 3514 static int 3515 em_is_valid_ether_addr(u8 *addr) 3516 { 3517 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3518 3519 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3520 return (FALSE); 3521 } 3522 3523 return (TRUE); 3524 } 3525 3526 /* 3527 ** Parse the interface capabilities with regard 3528 ** to both system management and wake-on-lan for 3529 ** later use. 3530 */ 3531 static void 3532 em_get_wakeup(if_ctx_t ctx) 3533 { 3534 struct adapter *adapter = iflib_get_softc(ctx); 3535 device_t dev = iflib_get_dev(ctx); 3536 u16 eeprom_data = 0, device_id, apme_mask; 3537 3538 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3539 apme_mask = EM_EEPROM_APME; 3540 3541 switch (adapter->hw.mac.type) { 3542 case e1000_82542: 3543 case e1000_82543: 3544 break; 3545 case e1000_82544: 3546 e1000_read_nvm(&adapter->hw, 3547 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3548 apme_mask = EM_82544_APME; 3549 break; 3550 case e1000_82546: 3551 case e1000_82546_rev_3: 3552 if (adapter->hw.bus.func == 1) { 3553 e1000_read_nvm(&adapter->hw, 3554 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3555 break; 3556 } else 3557 e1000_read_nvm(&adapter->hw, 3558 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3559 break; 3560 case e1000_82573: 3561 case e1000_82583: 3562 adapter->has_amt = TRUE; 3563 /* FALLTHROUGH */ 3564 case e1000_82571: 3565 case e1000_82572: 3566 case e1000_80003es2lan: 3567 if (adapter->hw.bus.func == 1) { 3568 e1000_read_nvm(&adapter->hw, 3569 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3570 break; 3571 } else 3572 e1000_read_nvm(&adapter->hw, 3573 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3574 break; 3575 case e1000_ich8lan: 3576 case e1000_ich9lan: 3577 case e1000_ich10lan: 3578 case e1000_pchlan: 3579 case e1000_pch2lan: 3580 case e1000_pch_lpt: 3581 case e1000_pch_spt: 3582 case e1000_82575: /* listing all igb devices */ 3583 case e1000_82576: 3584 case e1000_82580: 3585 case e1000_i350: 3586 case e1000_i354: 3587 case e1000_i210: 3588 case e1000_i211: 3589 case e1000_vfadapt: 3590 case e1000_vfadapt_i350: 3591 apme_mask = E1000_WUC_APME; 3592 adapter->has_amt = TRUE; 3593 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3594 break; 3595 default: 3596 e1000_read_nvm(&adapter->hw, 3597 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3598 break; 3599 } 3600 if (eeprom_data & apme_mask) 3601 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3602 /* 3603 * We have the eeprom settings, now apply the special cases 3604 * where the eeprom may be wrong or the board won't support 3605 * wake on lan on a particular port 3606 */ 3607 device_id = pci_get_device(dev); 3608 switch (device_id) { 3609 case E1000_DEV_ID_82546GB_PCIE: 3610 adapter->wol = 0; 3611 break; 3612 case E1000_DEV_ID_82546EB_FIBER: 3613 case E1000_DEV_ID_82546GB_FIBER: 3614 /* Wake events only supported on port A for dual fiber 3615 * regardless of eeprom setting */ 3616 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3617 E1000_STATUS_FUNC_1) 3618 adapter->wol = 0; 3619 break; 3620 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3621 /* if quad port adapter, disable WoL on all but port A */ 3622 if (global_quad_port_a != 0) 3623 adapter->wol = 0; 3624 /* Reset for multiple quad port adapters */ 3625 if (++global_quad_port_a == 4) 3626 global_quad_port_a = 0; 3627 break; 3628 case E1000_DEV_ID_82571EB_FIBER: 3629 /* Wake events only supported on port A for dual fiber 3630 * regardless of eeprom setting */ 3631 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3632 E1000_STATUS_FUNC_1) 3633 adapter->wol = 0; 3634 break; 3635 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3636 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3637 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3638 /* if quad port adapter, disable WoL on all but port A */ 3639 if (global_quad_port_a != 0) 3640 adapter->wol = 0; 3641 /* Reset for multiple quad port adapters */ 3642 if (++global_quad_port_a == 4) 3643 global_quad_port_a = 0; 3644 break; 3645 } 3646 return; 3647 } 3648 3649 3650 /* 3651 * Enable PCI Wake On Lan capability 3652 */ 3653 static void 3654 em_enable_wakeup(if_ctx_t ctx) 3655 { 3656 struct adapter *adapter = iflib_get_softc(ctx); 3657 device_t dev = iflib_get_dev(ctx); 3658 if_t ifp = iflib_get_ifp(ctx); 3659 int error = 0; 3660 u32 pmc, ctrl, ctrl_ext, rctl; 3661 u16 status; 3662 3663 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3664 return; 3665 3666 /* 3667 * Determine type of Wakeup: note that wol 3668 * is set with all bits on by default. 3669 */ 3670 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3671 adapter->wol &= ~E1000_WUFC_MAG; 3672 3673 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3674 adapter->wol &= ~E1000_WUFC_EX; 3675 3676 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3677 adapter->wol &= ~E1000_WUFC_MC; 3678 else { 3679 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3680 rctl |= E1000_RCTL_MPE; 3681 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3682 } 3683 3684 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3685 goto pme; 3686 3687 /* Advertise the wakeup capability */ 3688 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3689 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3690 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3691 3692 /* Keep the laser running on Fiber adapters */ 3693 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3694 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3695 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3696 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3697 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3698 } 3699 3700 if ((adapter->hw.mac.type == e1000_ich8lan) || 3701 (adapter->hw.mac.type == e1000_pchlan) || 3702 (adapter->hw.mac.type == e1000_ich9lan) || 3703 (adapter->hw.mac.type == e1000_ich10lan)) 3704 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3705 3706 if ( adapter->hw.mac.type >= e1000_pchlan) { 3707 error = em_enable_phy_wakeup(adapter); 3708 if (error) 3709 goto pme; 3710 } else { 3711 /* Enable wakeup by the MAC */ 3712 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3713 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3714 } 3715 3716 if (adapter->hw.phy.type == e1000_phy_igp_3) 3717 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3718 3719 pme: 3720 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3721 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3722 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3723 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3724 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3725 3726 return; 3727 } 3728 3729 /* 3730 * WOL in the newer chipset interfaces (pchlan) 3731 * require thing to be copied into the phy 3732 */ 3733 static int 3734 em_enable_phy_wakeup(struct adapter *adapter) 3735 { 3736 struct e1000_hw *hw = &adapter->hw; 3737 u32 mreg, ret = 0; 3738 u16 preg; 3739 3740 /* copy MAC RARs to PHY RARs */ 3741 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3742 3743 /* copy MAC MTA to PHY MTA */ 3744 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3745 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3746 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3747 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3748 (u16)((mreg >> 16) & 0xFFFF)); 3749 } 3750 3751 /* configure PHY Rx Control register */ 3752 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3753 mreg = E1000_READ_REG(hw, E1000_RCTL); 3754 if (mreg & E1000_RCTL_UPE) 3755 preg |= BM_RCTL_UPE; 3756 if (mreg & E1000_RCTL_MPE) 3757 preg |= BM_RCTL_MPE; 3758 preg &= ~(BM_RCTL_MO_MASK); 3759 if (mreg & E1000_RCTL_MO_3) 3760 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3761 << BM_RCTL_MO_SHIFT); 3762 if (mreg & E1000_RCTL_BAM) 3763 preg |= BM_RCTL_BAM; 3764 if (mreg & E1000_RCTL_PMCF) 3765 preg |= BM_RCTL_PMCF; 3766 mreg = E1000_READ_REG(hw, E1000_CTRL); 3767 if (mreg & E1000_CTRL_RFCE) 3768 preg |= BM_RCTL_RFCE; 3769 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3770 3771 /* enable PHY wakeup in MAC register */ 3772 E1000_WRITE_REG(hw, E1000_WUC, 3773 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3774 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3775 3776 /* configure and enable PHY wakeup in PHY registers */ 3777 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3778 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3779 3780 /* activate PHY wakeup */ 3781 ret = hw->phy.ops.acquire(hw); 3782 if (ret) { 3783 printf("Could not acquire PHY\n"); 3784 return ret; 3785 } 3786 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3787 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3788 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3789 if (ret) { 3790 printf("Could not read PHY page 769\n"); 3791 goto out; 3792 } 3793 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3794 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3795 if (ret) 3796 printf("Could not set PHY Host Wakeup bit\n"); 3797 out: 3798 hw->phy.ops.release(hw); 3799 3800 return ret; 3801 } 3802 3803 static void 3804 em_if_led_func(if_ctx_t ctx, int onoff) 3805 { 3806 struct adapter *adapter = iflib_get_softc(ctx); 3807 3808 if (onoff) { 3809 e1000_setup_led(&adapter->hw); 3810 e1000_led_on(&adapter->hw); 3811 } else { 3812 e1000_led_off(&adapter->hw); 3813 e1000_cleanup_led(&adapter->hw); 3814 } 3815 } 3816 3817 /* 3818 * Disable the L0S and L1 LINK states 3819 */ 3820 static void 3821 em_disable_aspm(struct adapter *adapter) 3822 { 3823 int base, reg; 3824 u16 link_cap,link_ctrl; 3825 device_t dev = adapter->dev; 3826 3827 switch (adapter->hw.mac.type) { 3828 case e1000_82573: 3829 case e1000_82574: 3830 case e1000_82583: 3831 break; 3832 default: 3833 return; 3834 } 3835 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3836 return; 3837 reg = base + PCIER_LINK_CAP; 3838 link_cap = pci_read_config(dev, reg, 2); 3839 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3840 return; 3841 reg = base + PCIER_LINK_CTL; 3842 link_ctrl = pci_read_config(dev, reg, 2); 3843 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3844 pci_write_config(dev, reg, link_ctrl, 2); 3845 return; 3846 } 3847 3848 /********************************************************************** 3849 * 3850 * Update the board statistics counters. 3851 * 3852 **********************************************************************/ 3853 static void 3854 em_update_stats_counters(struct adapter *adapter) 3855 { 3856 3857 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3858 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3859 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3860 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3861 } 3862 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3863 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3864 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3865 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3866 3867 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3868 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3869 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3870 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3871 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3872 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3873 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3874 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3875 /* 3876 ** For watchdog management we need to know if we have been 3877 ** paused during the last interval, so capture that here. 3878 */ 3879 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3880 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3881 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3882 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3883 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3884 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3885 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3886 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3887 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3888 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3889 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3890 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3891 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3892 3893 /* For the 64-bit byte counters the low dword must be read first. */ 3894 /* Both registers clear on the read of the high dword */ 3895 3896 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3897 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3898 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3899 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3900 3901 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3902 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3903 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3904 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3905 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3906 3907 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3908 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3909 3910 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3911 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3912 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3913 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3914 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3915 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3916 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3917 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3918 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3919 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3920 3921 /* Interrupt Counts */ 3922 3923 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3924 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3925 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3926 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3927 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3928 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3929 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3930 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3931 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3932 3933 if (adapter->hw.mac.type >= e1000_82543) { 3934 adapter->stats.algnerrc += 3935 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3936 adapter->stats.rxerrc += 3937 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3938 adapter->stats.tncrs += 3939 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3940 adapter->stats.cexterr += 3941 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3942 adapter->stats.tsctc += 3943 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3944 adapter->stats.tsctfc += 3945 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3946 } 3947 } 3948 3949 static uint64_t 3950 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3951 { 3952 struct adapter *adapter = iflib_get_softc(ctx); 3953 struct ifnet *ifp = iflib_get_ifp(ctx); 3954 3955 switch (cnt) { 3956 case IFCOUNTER_COLLISIONS: 3957 return (adapter->stats.colc); 3958 case IFCOUNTER_IERRORS: 3959 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3960 adapter->stats.crcerrs + adapter->stats.algnerrc + 3961 adapter->stats.ruc + adapter->stats.roc + 3962 adapter->stats.mpc + adapter->stats.cexterr); 3963 case IFCOUNTER_OERRORS: 3964 return (adapter->stats.ecol + adapter->stats.latecol + 3965 adapter->watchdog_events); 3966 default: 3967 return (if_get_counter_default(ifp, cnt)); 3968 } 3969 } 3970 3971 /* Export a single 32-bit register via a read-only sysctl. */ 3972 static int 3973 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3974 { 3975 struct adapter *adapter; 3976 u_int val; 3977 3978 adapter = oidp->oid_arg1; 3979 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3980 return (sysctl_handle_int(oidp, &val, 0, req)); 3981 } 3982 3983 /* 3984 * Add sysctl variables, one per statistic, to the system. 3985 */ 3986 static void 3987 em_add_hw_stats(struct adapter *adapter) 3988 { 3989 device_t dev = iflib_get_dev(adapter->ctx); 3990 struct em_tx_queue *tx_que = adapter->tx_queues; 3991 struct em_rx_queue *rx_que = adapter->rx_queues; 3992 3993 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3994 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3995 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3996 struct e1000_hw_stats *stats = &adapter->stats; 3997 3998 struct sysctl_oid *stat_node, *queue_node, *int_node; 3999 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4000 4001 #define QUEUE_NAME_LEN 32 4002 char namebuf[QUEUE_NAME_LEN]; 4003 4004 /* Driver Statistics */ 4005 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4006 CTLFLAG_RD, &adapter->dropped_pkts, 4007 "Driver dropped packets"); 4008 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4009 CTLFLAG_RD, &adapter->link_irq, 4010 "Link MSIX IRQ Handled"); 4011 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4012 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4013 "Defragmenting mbuf chain failed"); 4014 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4015 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4016 "Driver tx dma failure in xmit"); 4017 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4018 CTLFLAG_RD, &adapter->rx_overruns, 4019 "RX overruns"); 4020 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4021 CTLFLAG_RD, &adapter->watchdog_events, 4022 "Watchdog timeouts"); 4023 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4024 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4025 em_sysctl_reg_handler, "IU", 4026 "Device Control Register"); 4027 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4028 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4029 em_sysctl_reg_handler, "IU", 4030 "Receiver Control Register"); 4031 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4032 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4033 "Flow Control High Watermark"); 4034 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4035 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4036 "Flow Control Low Watermark"); 4037 4038 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4039 struct tx_ring *txr = &tx_que->txr; 4040 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4041 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4042 CTLFLAG_RD, NULL, "TX Queue Name"); 4043 queue_list = SYSCTL_CHILDREN(queue_node); 4044 4045 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4046 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4047 E1000_TDH(txr->me), 4048 em_sysctl_reg_handler, "IU", 4049 "Transmit Descriptor Head"); 4050 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4051 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4052 E1000_TDT(txr->me), 4053 em_sysctl_reg_handler, "IU", 4054 "Transmit Descriptor Tail"); 4055 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4056 CTLFLAG_RD, &txr->tx_irq, 4057 "Queue MSI-X Transmit Interrupts"); 4058 } 4059 4060 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4061 struct rx_ring *rxr = &rx_que->rxr; 4062 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4063 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4064 CTLFLAG_RD, NULL, "RX Queue Name"); 4065 queue_list = SYSCTL_CHILDREN(queue_node); 4066 4067 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4068 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4069 E1000_RDH(rxr->me), 4070 em_sysctl_reg_handler, "IU", 4071 "Receive Descriptor Head"); 4072 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4073 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4074 E1000_RDT(rxr->me), 4075 em_sysctl_reg_handler, "IU", 4076 "Receive Descriptor Tail"); 4077 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4078 CTLFLAG_RD, &rxr->rx_irq, 4079 "Queue MSI-X Receive Interrupts"); 4080 } 4081 4082 /* MAC stats get their own sub node */ 4083 4084 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4085 CTLFLAG_RD, NULL, "Statistics"); 4086 stat_list = SYSCTL_CHILDREN(stat_node); 4087 4088 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4089 CTLFLAG_RD, &stats->ecol, 4090 "Excessive collisions"); 4091 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4092 CTLFLAG_RD, &stats->scc, 4093 "Single collisions"); 4094 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4095 CTLFLAG_RD, &stats->mcc, 4096 "Multiple collisions"); 4097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4098 CTLFLAG_RD, &stats->latecol, 4099 "Late collisions"); 4100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4101 CTLFLAG_RD, &stats->colc, 4102 "Collision Count"); 4103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4104 CTLFLAG_RD, &adapter->stats.symerrs, 4105 "Symbol Errors"); 4106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4107 CTLFLAG_RD, &adapter->stats.sec, 4108 "Sequence Errors"); 4109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4110 CTLFLAG_RD, &adapter->stats.dc, 4111 "Defer Count"); 4112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4113 CTLFLAG_RD, &adapter->stats.mpc, 4114 "Missed Packets"); 4115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4116 CTLFLAG_RD, &adapter->stats.rnbc, 4117 "Receive No Buffers"); 4118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4119 CTLFLAG_RD, &adapter->stats.ruc, 4120 "Receive Undersize"); 4121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4122 CTLFLAG_RD, &adapter->stats.rfc, 4123 "Fragmented Packets Received "); 4124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4125 CTLFLAG_RD, &adapter->stats.roc, 4126 "Oversized Packets Received"); 4127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4128 CTLFLAG_RD, &adapter->stats.rjc, 4129 "Recevied Jabber"); 4130 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4131 CTLFLAG_RD, &adapter->stats.rxerrc, 4132 "Receive Errors"); 4133 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4134 CTLFLAG_RD, &adapter->stats.crcerrs, 4135 "CRC errors"); 4136 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4137 CTLFLAG_RD, &adapter->stats.algnerrc, 4138 "Alignment Errors"); 4139 /* On 82575 these are collision counts */ 4140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4141 CTLFLAG_RD, &adapter->stats.cexterr, 4142 "Collision/Carrier extension errors"); 4143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4144 CTLFLAG_RD, &adapter->stats.xonrxc, 4145 "XON Received"); 4146 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4147 CTLFLAG_RD, &adapter->stats.xontxc, 4148 "XON Transmitted"); 4149 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4150 CTLFLAG_RD, &adapter->stats.xoffrxc, 4151 "XOFF Received"); 4152 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4153 CTLFLAG_RD, &adapter->stats.xofftxc, 4154 "XOFF Transmitted"); 4155 4156 /* Packet Reception Stats */ 4157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4158 CTLFLAG_RD, &adapter->stats.tpr, 4159 "Total Packets Received "); 4160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4161 CTLFLAG_RD, &adapter->stats.gprc, 4162 "Good Packets Received"); 4163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4164 CTLFLAG_RD, &adapter->stats.bprc, 4165 "Broadcast Packets Received"); 4166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4167 CTLFLAG_RD, &adapter->stats.mprc, 4168 "Multicast Packets Received"); 4169 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4170 CTLFLAG_RD, &adapter->stats.prc64, 4171 "64 byte frames received "); 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4173 CTLFLAG_RD, &adapter->stats.prc127, 4174 "65-127 byte frames received"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4176 CTLFLAG_RD, &adapter->stats.prc255, 4177 "128-255 byte frames received"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4179 CTLFLAG_RD, &adapter->stats.prc511, 4180 "256-511 byte frames received"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4182 CTLFLAG_RD, &adapter->stats.prc1023, 4183 "512-1023 byte frames received"); 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4185 CTLFLAG_RD, &adapter->stats.prc1522, 4186 "1023-1522 byte frames received"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4188 CTLFLAG_RD, &adapter->stats.gorc, 4189 "Good Octets Received"); 4190 4191 /* Packet Transmission Stats */ 4192 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4193 CTLFLAG_RD, &adapter->stats.gotc, 4194 "Good Octets Transmitted"); 4195 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4196 CTLFLAG_RD, &adapter->stats.tpt, 4197 "Total Packets Transmitted"); 4198 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4199 CTLFLAG_RD, &adapter->stats.gptc, 4200 "Good Packets Transmitted"); 4201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4202 CTLFLAG_RD, &adapter->stats.bptc, 4203 "Broadcast Packets Transmitted"); 4204 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4205 CTLFLAG_RD, &adapter->stats.mptc, 4206 "Multicast Packets Transmitted"); 4207 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4208 CTLFLAG_RD, &adapter->stats.ptc64, 4209 "64 byte frames transmitted "); 4210 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4211 CTLFLAG_RD, &adapter->stats.ptc127, 4212 "65-127 byte frames transmitted"); 4213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4214 CTLFLAG_RD, &adapter->stats.ptc255, 4215 "128-255 byte frames transmitted"); 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4217 CTLFLAG_RD, &adapter->stats.ptc511, 4218 "256-511 byte frames transmitted"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4220 CTLFLAG_RD, &adapter->stats.ptc1023, 4221 "512-1023 byte frames transmitted"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4223 CTLFLAG_RD, &adapter->stats.ptc1522, 4224 "1024-1522 byte frames transmitted"); 4225 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4226 CTLFLAG_RD, &adapter->stats.tsctc, 4227 "TSO Contexts Transmitted"); 4228 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4229 CTLFLAG_RD, &adapter->stats.tsctfc, 4230 "TSO Contexts Failed"); 4231 4232 4233 /* Interrupt Stats */ 4234 4235 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4236 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4237 int_list = SYSCTL_CHILDREN(int_node); 4238 4239 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4240 CTLFLAG_RD, &adapter->stats.iac, 4241 "Interrupt Assertion Count"); 4242 4243 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4244 CTLFLAG_RD, &adapter->stats.icrxptc, 4245 "Interrupt Cause Rx Pkt Timer Expire Count"); 4246 4247 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4248 CTLFLAG_RD, &adapter->stats.icrxatc, 4249 "Interrupt Cause Rx Abs Timer Expire Count"); 4250 4251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4252 CTLFLAG_RD, &adapter->stats.ictxptc, 4253 "Interrupt Cause Tx Pkt Timer Expire Count"); 4254 4255 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4256 CTLFLAG_RD, &adapter->stats.ictxatc, 4257 "Interrupt Cause Tx Abs Timer Expire Count"); 4258 4259 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4260 CTLFLAG_RD, &adapter->stats.ictxqec, 4261 "Interrupt Cause Tx Queue Empty Count"); 4262 4263 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4264 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4265 "Interrupt Cause Tx Queue Min Thresh Count"); 4266 4267 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4268 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4269 "Interrupt Cause Rx Desc Min Thresh Count"); 4270 4271 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4272 CTLFLAG_RD, &adapter->stats.icrxoc, 4273 "Interrupt Cause Receiver Overrun Count"); 4274 } 4275 4276 /********************************************************************** 4277 * 4278 * This routine provides a way to dump out the adapter eeprom, 4279 * often a useful debug/service tool. This only dumps the first 4280 * 32 words, stuff that matters is in that extent. 4281 * 4282 **********************************************************************/ 4283 static int 4284 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4285 { 4286 struct adapter *adapter = (struct adapter *)arg1; 4287 int error; 4288 int result; 4289 4290 result = -1; 4291 error = sysctl_handle_int(oidp, &result, 0, req); 4292 4293 if (error || !req->newptr) 4294 return (error); 4295 4296 /* 4297 * This value will cause a hex dump of the 4298 * first 32 16-bit words of the EEPROM to 4299 * the screen. 4300 */ 4301 if (result == 1) 4302 em_print_nvm_info(adapter); 4303 4304 return (error); 4305 } 4306 4307 static void 4308 em_print_nvm_info(struct adapter *adapter) 4309 { 4310 u16 eeprom_data; 4311 int i, j, row = 0; 4312 4313 /* Its a bit crude, but it gets the job done */ 4314 printf("\nInterface EEPROM Dump:\n"); 4315 printf("Offset\n0x0000 "); 4316 for (i = 0, j = 0; i < 32; i++, j++) { 4317 if (j == 8) { /* Make the offset block */ 4318 j = 0; ++row; 4319 printf("\n0x00%x0 ",row); 4320 } 4321 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4322 printf("%04x ", eeprom_data); 4323 } 4324 printf("\n"); 4325 } 4326 4327 static int 4328 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4329 { 4330 struct em_int_delay_info *info; 4331 struct adapter *adapter; 4332 u32 regval; 4333 int error, usecs, ticks; 4334 4335 info = (struct em_int_delay_info *) arg1; 4336 usecs = info->value; 4337 error = sysctl_handle_int(oidp, &usecs, 0, req); 4338 if (error != 0 || req->newptr == NULL) 4339 return (error); 4340 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4341 return (EINVAL); 4342 info->value = usecs; 4343 ticks = EM_USECS_TO_TICKS(usecs); 4344 if (info->offset == E1000_ITR) /* units are 256ns here */ 4345 ticks *= 4; 4346 4347 adapter = info->adapter; 4348 4349 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4350 regval = (regval & ~0xffff) | (ticks & 0xffff); 4351 /* Handle a few special cases. */ 4352 switch (info->offset) { 4353 case E1000_RDTR: 4354 break; 4355 case E1000_TIDV: 4356 if (ticks == 0) { 4357 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4358 /* Don't write 0 into the TIDV register. */ 4359 regval++; 4360 } else 4361 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4362 break; 4363 } 4364 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4365 return (0); 4366 } 4367 4368 static void 4369 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4370 const char *description, struct em_int_delay_info *info, 4371 int offset, int value) 4372 { 4373 info->adapter = adapter; 4374 info->offset = offset; 4375 info->value = value; 4376 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4377 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4378 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4379 info, 0, em_sysctl_int_delay, "I", description); 4380 } 4381 4382 /* 4383 * Set flow control using sysctl: 4384 * Flow control values: 4385 * 0 - off 4386 * 1 - rx pause 4387 * 2 - tx pause 4388 * 3 - full 4389 */ 4390 static int 4391 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4392 { 4393 int error; 4394 static int input = 3; /* default is full */ 4395 struct adapter *adapter = (struct adapter *) arg1; 4396 4397 error = sysctl_handle_int(oidp, &input, 0, req); 4398 4399 if ((error) || (req->newptr == NULL)) 4400 return (error); 4401 4402 if (input == adapter->fc) /* no change? */ 4403 return (error); 4404 4405 switch (input) { 4406 case e1000_fc_rx_pause: 4407 case e1000_fc_tx_pause: 4408 case e1000_fc_full: 4409 case e1000_fc_none: 4410 adapter->hw.fc.requested_mode = input; 4411 adapter->fc = input; 4412 break; 4413 default: 4414 /* Do nothing */ 4415 return (error); 4416 } 4417 4418 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4419 e1000_force_mac_fc(&adapter->hw); 4420 return (error); 4421 } 4422 4423 /* 4424 * Manage Energy Efficient Ethernet: 4425 * Control values: 4426 * 0/1 - enabled/disabled 4427 */ 4428 static int 4429 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4430 { 4431 struct adapter *adapter = (struct adapter *) arg1; 4432 int error, value; 4433 4434 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4435 error = sysctl_handle_int(oidp, &value, 0, req); 4436 if (error || req->newptr == NULL) 4437 return (error); 4438 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4439 em_if_init(adapter->ctx); 4440 4441 return (0); 4442 } 4443 4444 static int 4445 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4446 { 4447 struct adapter *adapter; 4448 int error; 4449 int result; 4450 4451 result = -1; 4452 error = sysctl_handle_int(oidp, &result, 0, req); 4453 4454 if (error || !req->newptr) 4455 return (error); 4456 4457 if (result == 1) { 4458 adapter = (struct adapter *) arg1; 4459 em_print_debug_info(adapter); 4460 } 4461 4462 return (error); 4463 } 4464 4465 static int 4466 em_get_rs(SYSCTL_HANDLER_ARGS) 4467 { 4468 struct adapter *adapter = (struct adapter *) arg1; 4469 int error; 4470 int result; 4471 4472 result = 0; 4473 error = sysctl_handle_int(oidp, &result, 0, req); 4474 4475 if (error || !req->newptr || result != 1) 4476 return (error); 4477 em_dump_rs(adapter); 4478 4479 return (error); 4480 } 4481 4482 static void 4483 em_if_debug(if_ctx_t ctx) 4484 { 4485 em_dump_rs(iflib_get_softc(ctx)); 4486 } 4487 4488 /* 4489 * This routine is meant to be fluid, add whatever is 4490 * needed for debugging a problem. -jfv 4491 */ 4492 static void 4493 em_print_debug_info(struct adapter *adapter) 4494 { 4495 device_t dev = iflib_get_dev(adapter->ctx); 4496 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4497 struct tx_ring *txr = &adapter->tx_queues->txr; 4498 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4499 4500 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4501 printf("Interface is RUNNING "); 4502 else 4503 printf("Interface is NOT RUNNING\n"); 4504 4505 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4506 printf("and INACTIVE\n"); 4507 else 4508 printf("and ACTIVE\n"); 4509 4510 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4511 device_printf(dev, "TX Queue %d ------\n", i); 4512 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4513 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4514 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4515 4516 } 4517 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4518 device_printf(dev, "RX Queue %d ------\n", j); 4519 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4520 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4521 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4522 } 4523 } 4524 4525 /* 4526 * 82574 only: 4527 * Write a new value to the EEPROM increasing the number of MSIX 4528 * vectors from 3 to 5, for proper multiqueue support. 4529 */ 4530 static void 4531 em_enable_vectors_82574(if_ctx_t ctx) 4532 { 4533 struct adapter *adapter = iflib_get_softc(ctx); 4534 struct e1000_hw *hw = &adapter->hw; 4535 device_t dev = iflib_get_dev(ctx); 4536 u16 edata; 4537 4538 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4539 printf("Current cap: %#06x\n", edata); 4540 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4541 device_printf(dev, "Writing to eeprom: increasing " 4542 "reported MSIX vectors from 3 to 5...\n"); 4543 edata &= ~(EM_NVM_MSIX_N_MASK); 4544 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4545 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4546 e1000_update_nvm_checksum(hw); 4547 device_printf(dev, "Writing to eeprom: done\n"); 4548 } 4549 } 4550