1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 /* required last entry */ 178 PVID_END 179 }; 180 181 static pci_vendor_info_t igb_vendor_info_array[] = 182 { 183 /* Intel(R) PRO/1000 Network Connection - igb */ 184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 /* required last entry */ 224 PVID_END 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 static void *em_register(device_t dev); 231 static void *igb_register(device_t dev); 232 static int em_if_attach_pre(if_ctx_t ctx); 233 static int em_if_attach_post(if_ctx_t ctx); 234 static int em_if_detach(if_ctx_t ctx); 235 static int em_if_shutdown(if_ctx_t ctx); 236 static int em_if_suspend(if_ctx_t ctx); 237 static int em_if_resume(if_ctx_t ctx); 238 239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 241 static void em_if_queues_free(if_ctx_t ctx); 242 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 244 static void em_if_init(if_ctx_t ctx); 245 static void em_if_stop(if_ctx_t ctx); 246 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 247 static int em_if_media_change(if_ctx_t ctx); 248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 249 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 252 253 static void em_identify_hardware(if_ctx_t ctx); 254 static int em_allocate_pci_resources(if_ctx_t ctx); 255 static void em_free_pci_resources(if_ctx_t ctx); 256 static void em_reset(if_ctx_t ctx); 257 static int em_setup_interface(if_ctx_t ctx); 258 static int em_setup_msix(if_ctx_t ctx); 259 260 static void em_initialize_transmit_unit(if_ctx_t ctx); 261 static void em_initialize_receive_unit(if_ctx_t ctx); 262 263 static void em_if_enable_intr(if_ctx_t ctx); 264 static void em_if_disable_intr(if_ctx_t ctx); 265 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 266 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 267 static void em_if_multi_set(if_ctx_t ctx); 268 static void em_if_update_admin_status(if_ctx_t ctx); 269 static void em_if_debug(if_ctx_t ctx); 270 static void em_update_stats_counters(struct adapter *); 271 static void em_add_hw_stats(struct adapter *adapter); 272 static int em_if_set_promisc(if_ctx_t ctx, int flags); 273 static void em_setup_vlan_hw_support(struct adapter *); 274 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 275 static void em_print_nvm_info(struct adapter *); 276 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 277 static int em_get_rs(SYSCTL_HANDLER_ARGS); 278 static void em_print_debug_info(struct adapter *); 279 static int em_is_valid_ether_addr(u8 *); 280 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 281 static void em_add_int_delay_sysctl(struct adapter *, const char *, 282 const char *, struct em_int_delay_info *, int, int); 283 /* Management and WOL Support */ 284 static void em_init_manageability(struct adapter *); 285 static void em_release_manageability(struct adapter *); 286 static void em_get_hw_control(struct adapter *); 287 static void em_release_hw_control(struct adapter *); 288 static void em_get_wakeup(if_ctx_t ctx); 289 static void em_enable_wakeup(if_ctx_t ctx); 290 static int em_enable_phy_wakeup(struct adapter *); 291 static void em_disable_aspm(struct adapter *); 292 293 int em_intr(void *arg); 294 static void em_disable_promisc(if_ctx_t ctx); 295 296 /* MSIX handlers */ 297 static int em_if_msix_intr_assign(if_ctx_t, int); 298 static int em_msix_link(void *); 299 static void em_handle_link(void *context); 300 301 static void em_enable_vectors_82574(if_ctx_t); 302 303 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 304 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 305 static void em_if_led_func(if_ctx_t ctx, int onoff); 306 307 static int em_get_regs(SYSCTL_HANDLER_ARGS); 308 309 static void lem_smartspeed(struct adapter *adapter); 310 static void igb_configure_queues(struct adapter *adapter); 311 312 313 /********************************************************************* 314 * FreeBSD Device Interface Entry Points 315 *********************************************************************/ 316 static device_method_t em_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_register, em_register), 319 DEVMETHOD(device_probe, iflib_device_probe), 320 DEVMETHOD(device_attach, iflib_device_attach), 321 DEVMETHOD(device_detach, iflib_device_detach), 322 DEVMETHOD(device_shutdown, iflib_device_shutdown), 323 DEVMETHOD(device_suspend, iflib_device_suspend), 324 DEVMETHOD(device_resume, iflib_device_resume), 325 DEVMETHOD_END 326 }; 327 328 static device_method_t igb_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, igb_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 341 static driver_t em_driver = { 342 "em", em_methods, sizeof(struct adapter), 343 }; 344 345 static devclass_t em_devclass; 346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 347 348 MODULE_DEPEND(em, pci, 1, 1, 1); 349 MODULE_DEPEND(em, ether, 1, 1, 1); 350 MODULE_DEPEND(em, iflib, 1, 1, 1); 351 352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 353 354 static driver_t igb_driver = { 355 "igb", igb_methods, sizeof(struct adapter), 356 }; 357 358 static devclass_t igb_devclass; 359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 360 361 MODULE_DEPEND(igb, pci, 1, 1, 1); 362 MODULE_DEPEND(igb, ether, 1, 1, 1); 363 MODULE_DEPEND(igb, iflib, 1, 1, 1); 364 365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 366 367 static device_method_t em_if_methods[] = { 368 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 369 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 370 DEVMETHOD(ifdi_detach, em_if_detach), 371 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 372 DEVMETHOD(ifdi_suspend, em_if_suspend), 373 DEVMETHOD(ifdi_resume, em_if_resume), 374 DEVMETHOD(ifdi_init, em_if_init), 375 DEVMETHOD(ifdi_stop, em_if_stop), 376 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 377 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 378 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 379 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 380 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 381 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 382 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 383 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 384 DEVMETHOD(ifdi_media_status, em_if_media_status), 385 DEVMETHOD(ifdi_media_change, em_if_media_change), 386 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 387 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 388 DEVMETHOD(ifdi_timer, em_if_timer), 389 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 390 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 391 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 392 DEVMETHOD(ifdi_led_func, em_if_led_func), 393 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 394 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 395 DEVMETHOD(ifdi_debug, em_if_debug), 396 DEVMETHOD_END 397 }; 398 399 /* 400 * note that if (adapter->msix_mem) is replaced by: 401 * if (adapter->intr_type == IFLIB_INTR_MSIX) 402 */ 403 static driver_t em_if_driver = { 404 "em_if", em_if_methods, sizeof(struct adapter) 405 }; 406 407 /********************************************************************* 408 * Tunable default values. 409 *********************************************************************/ 410 411 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 412 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 413 414 #define MAX_INTS_PER_SEC 8000 415 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 416 417 /* Allow common code without TSO */ 418 #ifndef CSUM_TSO 419 #define CSUM_TSO 0 420 #endif 421 422 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 423 424 static int em_disable_crc_stripping = 0; 425 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 426 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 427 428 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 429 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 430 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 431 0, "Default transmit interrupt delay in usecs"); 432 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 433 0, "Default receive interrupt delay in usecs"); 434 435 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 436 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 437 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 438 &em_tx_abs_int_delay_dflt, 0, 439 "Default transmit interrupt delay limit in usecs"); 440 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 441 &em_rx_abs_int_delay_dflt, 0, 442 "Default receive interrupt delay limit in usecs"); 443 444 static int em_smart_pwr_down = FALSE; 445 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 446 0, "Set to true to leave smart power down enabled on newer adapters"); 447 448 /* Controls whether promiscuous also shows bad packets */ 449 static int em_debug_sbp = TRUE; 450 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 451 "Show bad packets in promiscuous mode"); 452 453 /* How many packets rxeof tries to clean at a time */ 454 static int em_rx_process_limit = 100; 455 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 456 &em_rx_process_limit, 0, 457 "Maximum number of received packets to process " 458 "at a time, -1 means unlimited"); 459 460 /* Energy efficient ethernet - default to OFF */ 461 static int eee_setting = 1; 462 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 463 "Enable Energy Efficient Ethernet"); 464 465 /* 466 ** Tuneable Interrupt rate 467 */ 468 static int em_max_interrupt_rate = 8000; 469 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 470 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 471 472 473 474 /* Global used in WOL setup with multiport cards */ 475 static int global_quad_port_a = 0; 476 477 extern struct if_txrx igb_txrx; 478 extern struct if_txrx em_txrx; 479 extern struct if_txrx lem_txrx; 480 481 static struct if_shared_ctx em_sctx_init = { 482 .isc_magic = IFLIB_MAGIC, 483 .isc_q_align = PAGE_SIZE, 484 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 485 .isc_tx_maxsegsize = PAGE_SIZE, 486 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 487 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 488 .isc_rx_maxsize = MJUM9BYTES, 489 .isc_rx_nsegments = 1, 490 .isc_rx_maxsegsize = MJUM9BYTES, 491 .isc_nfl = 1, 492 .isc_nrxqs = 1, 493 .isc_ntxqs = 1, 494 .isc_admin_intrcnt = 1, 495 .isc_vendor_info = em_vendor_info_array, 496 .isc_driver_version = em_driver_version, 497 .isc_driver = &em_if_driver, 498 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 499 500 .isc_nrxd_min = {EM_MIN_RXD}, 501 .isc_ntxd_min = {EM_MIN_TXD}, 502 .isc_nrxd_max = {EM_MAX_RXD}, 503 .isc_ntxd_max = {EM_MAX_TXD}, 504 .isc_nrxd_default = {EM_DEFAULT_RXD}, 505 .isc_ntxd_default = {EM_DEFAULT_TXD}, 506 }; 507 508 if_shared_ctx_t em_sctx = &em_sctx_init; 509 510 static struct if_shared_ctx igb_sctx_init = { 511 .isc_magic = IFLIB_MAGIC, 512 .isc_q_align = PAGE_SIZE, 513 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 514 .isc_tx_maxsegsize = PAGE_SIZE, 515 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 516 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 517 .isc_rx_maxsize = MJUM9BYTES, 518 .isc_rx_nsegments = 1, 519 .isc_rx_maxsegsize = MJUM9BYTES, 520 .isc_nfl = 1, 521 .isc_nrxqs = 1, 522 .isc_ntxqs = 1, 523 .isc_admin_intrcnt = 1, 524 .isc_vendor_info = igb_vendor_info_array, 525 .isc_driver_version = em_driver_version, 526 .isc_driver = &em_if_driver, 527 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 528 529 .isc_nrxd_min = {EM_MIN_RXD}, 530 .isc_ntxd_min = {EM_MIN_TXD}, 531 .isc_nrxd_max = {IGB_MAX_RXD}, 532 .isc_ntxd_max = {IGB_MAX_TXD}, 533 .isc_nrxd_default = {EM_DEFAULT_RXD}, 534 .isc_ntxd_default = {EM_DEFAULT_TXD}, 535 }; 536 537 if_shared_ctx_t igb_sctx = &igb_sctx_init; 538 539 /***************************************************************** 540 * 541 * Dump Registers 542 * 543 ****************************************************************/ 544 #define IGB_REGS_LEN 739 545 546 static int em_get_regs(SYSCTL_HANDLER_ARGS) 547 { 548 struct adapter *adapter = (struct adapter *)arg1; 549 struct e1000_hw *hw = &adapter->hw; 550 struct sbuf *sb; 551 u32 *regs_buff; 552 int rc; 553 554 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 555 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 556 557 rc = sysctl_wire_old_buffer(req, 0); 558 MPASS(rc == 0); 559 if (rc != 0) { 560 free(regs_buff, M_DEVBUF); 561 return (rc); 562 } 563 564 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 565 MPASS(sb != NULL); 566 if (sb == NULL) { 567 free(regs_buff, M_DEVBUF); 568 return (ENOMEM); 569 } 570 571 /* General Registers */ 572 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 573 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 574 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 575 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 576 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 577 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 578 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 579 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 580 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 581 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 582 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 583 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 584 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 585 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 586 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 587 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 588 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 589 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 590 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 591 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 592 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 593 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 594 595 sbuf_printf(sb, "General Registers\n"); 596 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 597 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 598 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 599 600 sbuf_printf(sb, "Interrupt Registers\n"); 601 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 602 603 sbuf_printf(sb, "RX Registers\n"); 604 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 605 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 606 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 607 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 608 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 609 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 610 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 611 612 sbuf_printf(sb, "TX Registers\n"); 613 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 614 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 615 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 616 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 617 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 618 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 619 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 620 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 621 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 622 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 623 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 624 625 free(regs_buff, M_DEVBUF); 626 627 #ifdef DUMP_DESCS 628 { 629 if_softc_ctx_t scctx = adapter->shared; 630 struct rx_ring *rxr = &rx_que->rxr; 631 struct tx_ring *txr = &tx_que->txr; 632 int ntxd = scctx->isc_ntxd[0]; 633 int nrxd = scctx->isc_nrxd[0]; 634 int j; 635 636 for (j = 0; j < nrxd; j++) { 637 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 638 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 639 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 640 } 641 642 for (j = 0; j < min(ntxd, 256); j++) { 643 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 644 645 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 646 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 647 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 648 649 } 650 } 651 #endif 652 653 rc = sbuf_finish(sb); 654 sbuf_delete(sb); 655 return(rc); 656 } 657 658 static void * 659 em_register(device_t dev) 660 { 661 return (em_sctx); 662 } 663 664 static void * 665 igb_register(device_t dev) 666 { 667 return (igb_sctx); 668 } 669 670 static int 671 em_set_num_queues(if_ctx_t ctx) 672 { 673 struct adapter *adapter = iflib_get_softc(ctx); 674 int maxqueues; 675 676 /* Sanity check based on HW */ 677 switch (adapter->hw.mac.type) { 678 case e1000_82576: 679 case e1000_82580: 680 case e1000_i350: 681 case e1000_i354: 682 maxqueues = 8; 683 break; 684 case e1000_i210: 685 case e1000_82575: 686 maxqueues = 4; 687 break; 688 case e1000_i211: 689 case e1000_82574: 690 maxqueues = 2; 691 break; 692 default: 693 maxqueues = 1; 694 break; 695 } 696 697 return (maxqueues); 698 } 699 700 #define LEM_CAPS \ 701 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 702 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 703 704 #define EM_CAPS \ 705 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 706 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 707 IFCAP_LRO | IFCAP_VLAN_HWTSO 708 709 #define IGB_CAPS \ 710 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 711 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 712 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 713 IFCAP_TSO6 714 715 /********************************************************************* 716 * Device initialization routine 717 * 718 * The attach entry point is called when the driver is being loaded. 719 * This routine identifies the type of hardware, allocates all resources 720 * and initializes the hardware. 721 * 722 * return 0 on success, positive on failure 723 *********************************************************************/ 724 725 static int 726 em_if_attach_pre(if_ctx_t ctx) 727 { 728 struct adapter *adapter; 729 if_softc_ctx_t scctx; 730 device_t dev; 731 struct e1000_hw *hw; 732 int error = 0; 733 734 INIT_DEBUGOUT("em_if_attach_pre begin"); 735 dev = iflib_get_dev(ctx); 736 adapter = iflib_get_softc(ctx); 737 738 if (resource_disabled("em", device_get_unit(dev))) { 739 device_printf(dev, "Disabled by device hint\n"); 740 return (ENXIO); 741 } 742 743 adapter->ctx = adapter->osdep.ctx = ctx; 744 adapter->dev = adapter->osdep.dev = dev; 745 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 746 adapter->media = iflib_get_media(ctx); 747 hw = &adapter->hw; 748 749 adapter->tx_process_limit = scctx->isc_ntxd[0]; 750 751 /* SYSCTL stuff */ 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 754 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 755 em_sysctl_nvm_info, "I", "NVM Information"); 756 757 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 759 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 760 em_sysctl_debug_info, "I", "Debug Information"); 761 762 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 763 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 764 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 765 em_set_flowcntl, "I", "Flow Control"); 766 767 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 768 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 769 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 770 em_get_regs, "A", "Dump Registers"); 771 772 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 773 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 774 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 775 em_get_rs, "I", "Dump RS indexes"); 776 777 /* Determine hardware and mac info */ 778 em_identify_hardware(ctx); 779 780 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 781 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 782 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 783 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 784 785 if (adapter->hw.mac.type >= igb_mac_min) { 786 int try_second_bar; 787 788 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 789 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 790 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 791 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 792 scctx->isc_txrx = &igb_txrx; 793 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 794 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 795 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 796 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 797 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 798 CSUM_IP6_TCP | CSUM_IP6_UDP; 799 if (adapter->hw.mac.type != e1000_82575) 800 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 801 802 /* 803 ** Some new devices, as with ixgbe, now may 804 ** use a different BAR, so we need to keep 805 ** track of which is used. 806 */ 807 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 808 if (try_second_bar == 0) 809 scctx->isc_msix_bar += 4; 810 } else if (adapter->hw.mac.type >= em_mac_min) { 811 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 812 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 813 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 814 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 815 scctx->isc_txrx = &em_txrx; 816 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 817 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 818 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 819 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 820 /* 821 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 822 * by default as we don't have workarounds for all associated 823 * silicon errata. E. g., with several MACs such as 82573E, 824 * TSO only works at Gigabit speed and otherwise can cause the 825 * hardware to hang (which also would be next to impossible to 826 * work around given that already queued TSO-using descriptors 827 * would need to be flushed and vlan(4) reconfigured at runtime 828 * in case of a link speed change). Moreover, MACs like 82579 829 * still can hang at Gigabit even with all publicly documented 830 * TSO workarounds implemented. Generally, the penality of 831 * these workarounds is rather high and may involve copying 832 * mbuf data around so advantages of TSO lapse. Still, TSO may 833 * work for a few MACs of this class - at least when sticking 834 * with Gigabit - in which case users may enable TSO manually. 835 */ 836 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 837 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 838 } else { 839 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 840 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 841 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 842 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 843 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 844 scctx->isc_txrx = &lem_txrx; 845 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 846 if (adapter->hw.mac.type < e1000_82543) 847 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 848 scctx->isc_msix_bar = 0; 849 } 850 851 /* Setup PCI resources */ 852 if (em_allocate_pci_resources(ctx)) { 853 device_printf(dev, "Allocation of PCI resources failed\n"); 854 error = ENXIO; 855 goto err_pci; 856 } 857 858 /* 859 ** For ICH8 and family we need to 860 ** map the flash memory, and this 861 ** must happen after the MAC is 862 ** identified 863 */ 864 if ((hw->mac.type == e1000_ich8lan) || 865 (hw->mac.type == e1000_ich9lan) || 866 (hw->mac.type == e1000_ich10lan) || 867 (hw->mac.type == e1000_pchlan) || 868 (hw->mac.type == e1000_pch2lan) || 869 (hw->mac.type == e1000_pch_lpt)) { 870 int rid = EM_BAR_TYPE_FLASH; 871 adapter->flash = bus_alloc_resource_any(dev, 872 SYS_RES_MEMORY, &rid, RF_ACTIVE); 873 if (adapter->flash == NULL) { 874 device_printf(dev, "Mapping of Flash failed\n"); 875 error = ENXIO; 876 goto err_pci; 877 } 878 /* This is used in the shared code */ 879 hw->flash_address = (u8 *)adapter->flash; 880 adapter->osdep.flash_bus_space_tag = 881 rman_get_bustag(adapter->flash); 882 adapter->osdep.flash_bus_space_handle = 883 rman_get_bushandle(adapter->flash); 884 } 885 /* 886 ** In the new SPT device flash is not a 887 ** separate BAR, rather it is also in BAR0, 888 ** so use the same tag and an offset handle for the 889 ** FLASH read/write macros in the shared code. 890 */ 891 else if (hw->mac.type >= e1000_pch_spt) { 892 adapter->osdep.flash_bus_space_tag = 893 adapter->osdep.mem_bus_space_tag; 894 adapter->osdep.flash_bus_space_handle = 895 adapter->osdep.mem_bus_space_handle 896 + E1000_FLASH_BASE_ADDR; 897 } 898 899 /* Do Shared Code initialization */ 900 error = e1000_setup_init_funcs(hw, TRUE); 901 if (error) { 902 device_printf(dev, "Setup of Shared code failed, error %d\n", 903 error); 904 error = ENXIO; 905 goto err_pci; 906 } 907 908 em_setup_msix(ctx); 909 e1000_get_bus_info(hw); 910 911 /* Set up some sysctls for the tunable interrupt delays */ 912 em_add_int_delay_sysctl(adapter, "rx_int_delay", 913 "receive interrupt delay in usecs", &adapter->rx_int_delay, 914 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 915 em_add_int_delay_sysctl(adapter, "tx_int_delay", 916 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 917 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 918 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 919 "receive interrupt delay limit in usecs", 920 &adapter->rx_abs_int_delay, 921 E1000_REGISTER(hw, E1000_RADV), 922 em_rx_abs_int_delay_dflt); 923 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 924 "transmit interrupt delay limit in usecs", 925 &adapter->tx_abs_int_delay, 926 E1000_REGISTER(hw, E1000_TADV), 927 em_tx_abs_int_delay_dflt); 928 em_add_int_delay_sysctl(adapter, "itr", 929 "interrupt delay limit in usecs/4", 930 &adapter->tx_itr, 931 E1000_REGISTER(hw, E1000_ITR), 932 DEFAULT_ITR); 933 934 hw->mac.autoneg = DO_AUTO_NEG; 935 hw->phy.autoneg_wait_to_complete = FALSE; 936 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 937 938 if (adapter->hw.mac.type < em_mac_min) { 939 e1000_init_script_state_82541(&adapter->hw, TRUE); 940 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 941 } 942 /* Copper options */ 943 if (hw->phy.media_type == e1000_media_type_copper) { 944 hw->phy.mdix = AUTO_ALL_MODES; 945 hw->phy.disable_polarity_correction = FALSE; 946 hw->phy.ms_type = EM_MASTER_SLAVE; 947 } 948 949 /* 950 * Set the frame limits assuming 951 * standard ethernet sized frames. 952 */ 953 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 954 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 955 956 /* 957 * This controls when hardware reports transmit completion 958 * status. 959 */ 960 hw->mac.report_tx_early = 1; 961 962 /* Allocate multicast array memory. */ 963 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 964 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 965 if (adapter->mta == NULL) { 966 device_printf(dev, "Can not allocate multicast setup array\n"); 967 error = ENOMEM; 968 goto err_late; 969 } 970 971 /* Check SOL/IDER usage */ 972 if (e1000_check_reset_block(hw)) 973 device_printf(dev, "PHY reset is blocked" 974 " due to SOL/IDER session.\n"); 975 976 /* Sysctl for setting Energy Efficient Ethernet */ 977 hw->dev_spec.ich8lan.eee_disable = eee_setting; 978 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 979 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 980 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 981 adapter, 0, em_sysctl_eee, "I", 982 "Disable Energy Efficient Ethernet"); 983 984 /* 985 ** Start from a known state, this is 986 ** important in reading the nvm and 987 ** mac from that. 988 */ 989 e1000_reset_hw(hw); 990 991 /* Make sure we have a good EEPROM before we read from it */ 992 if (e1000_validate_nvm_checksum(hw) < 0) { 993 /* 994 ** Some PCI-E parts fail the first check due to 995 ** the link being in sleep state, call it again, 996 ** if it fails a second time its a real issue. 997 */ 998 if (e1000_validate_nvm_checksum(hw) < 0) { 999 device_printf(dev, 1000 "The EEPROM Checksum Is Not Valid\n"); 1001 error = EIO; 1002 goto err_late; 1003 } 1004 } 1005 1006 /* Copy the permanent MAC address out of the EEPROM */ 1007 if (e1000_read_mac_addr(hw) < 0) { 1008 device_printf(dev, "EEPROM read error while reading MAC" 1009 " address\n"); 1010 error = EIO; 1011 goto err_late; 1012 } 1013 1014 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1015 device_printf(dev, "Invalid MAC address\n"); 1016 error = EIO; 1017 goto err_late; 1018 } 1019 1020 /* Disable ULP support */ 1021 e1000_disable_ulp_lpt_lp(hw, TRUE); 1022 1023 /* 1024 * Get Wake-on-Lan and Management info for later use 1025 */ 1026 em_get_wakeup(ctx); 1027 1028 /* Enable only WOL MAGIC by default */ 1029 scctx->isc_capenable &= ~IFCAP_WOL; 1030 if (adapter->wol != 0) 1031 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1032 1033 iflib_set_mac(ctx, hw->mac.addr); 1034 1035 return (0); 1036 1037 err_late: 1038 em_release_hw_control(adapter); 1039 err_pci: 1040 em_free_pci_resources(ctx); 1041 free(adapter->mta, M_DEVBUF); 1042 1043 return (error); 1044 } 1045 1046 static int 1047 em_if_attach_post(if_ctx_t ctx) 1048 { 1049 struct adapter *adapter = iflib_get_softc(ctx); 1050 struct e1000_hw *hw = &adapter->hw; 1051 int error = 0; 1052 1053 /* Setup OS specific network interface */ 1054 error = em_setup_interface(ctx); 1055 if (error != 0) { 1056 goto err_late; 1057 } 1058 1059 em_reset(ctx); 1060 1061 /* Initialize statistics */ 1062 em_update_stats_counters(adapter); 1063 hw->mac.get_link_status = 1; 1064 em_if_update_admin_status(ctx); 1065 em_add_hw_stats(adapter); 1066 1067 /* Non-AMT based hardware can now take control from firmware */ 1068 if (adapter->has_manage && !adapter->has_amt) 1069 em_get_hw_control(adapter); 1070 1071 INIT_DEBUGOUT("em_if_attach_post: end"); 1072 1073 return (error); 1074 1075 err_late: 1076 em_release_hw_control(adapter); 1077 em_free_pci_resources(ctx); 1078 em_if_queues_free(ctx); 1079 free(adapter->mta, M_DEVBUF); 1080 1081 return (error); 1082 } 1083 1084 /********************************************************************* 1085 * Device removal routine 1086 * 1087 * The detach entry point is called when the driver is being removed. 1088 * This routine stops the adapter and deallocates all the resources 1089 * that were allocated for driver operation. 1090 * 1091 * return 0 on success, positive on failure 1092 *********************************************************************/ 1093 1094 static int 1095 em_if_detach(if_ctx_t ctx) 1096 { 1097 struct adapter *adapter = iflib_get_softc(ctx); 1098 1099 INIT_DEBUGOUT("em_detach: begin"); 1100 1101 e1000_phy_hw_reset(&adapter->hw); 1102 1103 em_release_manageability(adapter); 1104 em_release_hw_control(adapter); 1105 em_free_pci_resources(ctx); 1106 1107 return (0); 1108 } 1109 1110 /********************************************************************* 1111 * 1112 * Shutdown entry point 1113 * 1114 **********************************************************************/ 1115 1116 static int 1117 em_if_shutdown(if_ctx_t ctx) 1118 { 1119 return em_if_suspend(ctx); 1120 } 1121 1122 /* 1123 * Suspend/resume device methods. 1124 */ 1125 static int 1126 em_if_suspend(if_ctx_t ctx) 1127 { 1128 struct adapter *adapter = iflib_get_softc(ctx); 1129 1130 em_release_manageability(adapter); 1131 em_release_hw_control(adapter); 1132 em_enable_wakeup(ctx); 1133 return (0); 1134 } 1135 1136 static int 1137 em_if_resume(if_ctx_t ctx) 1138 { 1139 struct adapter *adapter = iflib_get_softc(ctx); 1140 1141 if (adapter->hw.mac.type == e1000_pch2lan) 1142 e1000_resume_workarounds_pchlan(&adapter->hw); 1143 em_if_init(ctx); 1144 em_init_manageability(adapter); 1145 1146 return(0); 1147 } 1148 1149 static int 1150 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1151 { 1152 int max_frame_size; 1153 struct adapter *adapter = iflib_get_softc(ctx); 1154 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1155 1156 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1157 1158 switch (adapter->hw.mac.type) { 1159 case e1000_82571: 1160 case e1000_82572: 1161 case e1000_ich9lan: 1162 case e1000_ich10lan: 1163 case e1000_pch2lan: 1164 case e1000_pch_lpt: 1165 case e1000_pch_spt: 1166 case e1000_pch_cnp: 1167 case e1000_82574: 1168 case e1000_82583: 1169 case e1000_80003es2lan: 1170 /* 9K Jumbo Frame size */ 1171 max_frame_size = 9234; 1172 break; 1173 case e1000_pchlan: 1174 max_frame_size = 4096; 1175 break; 1176 case e1000_82542: 1177 case e1000_ich8lan: 1178 /* Adapters that do not support jumbo frames */ 1179 max_frame_size = ETHER_MAX_LEN; 1180 break; 1181 default: 1182 if (adapter->hw.mac.type >= igb_mac_min) 1183 max_frame_size = 9234; 1184 else /* lem */ 1185 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1186 } 1187 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1188 return (EINVAL); 1189 } 1190 1191 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1192 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1193 return (0); 1194 } 1195 1196 /********************************************************************* 1197 * Init entry point 1198 * 1199 * This routine is used in two ways. It is used by the stack as 1200 * init entry point in network interface structure. It is also used 1201 * by the driver as a hw/sw initialization routine to get to a 1202 * consistent state. 1203 * 1204 * return 0 on success, positive on failure 1205 **********************************************************************/ 1206 1207 static void 1208 em_if_init(if_ctx_t ctx) 1209 { 1210 struct adapter *adapter = iflib_get_softc(ctx); 1211 struct ifnet *ifp = iflib_get_ifp(ctx); 1212 struct em_tx_queue *tx_que; 1213 int i; 1214 INIT_DEBUGOUT("em_if_init: begin"); 1215 1216 /* Get the latest mac address, User can use a LAA */ 1217 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1218 ETHER_ADDR_LEN); 1219 1220 /* Put the address into the Receive Address Array */ 1221 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1222 1223 /* 1224 * With the 82571 adapter, RAR[0] may be overwritten 1225 * when the other port is reset, we make a duplicate 1226 * in RAR[14] for that eventuality, this assures 1227 * the interface continues to function. 1228 */ 1229 if (adapter->hw.mac.type == e1000_82571) { 1230 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1231 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1232 E1000_RAR_ENTRIES - 1); 1233 } 1234 1235 1236 /* Initialize the hardware */ 1237 em_reset(ctx); 1238 em_if_update_admin_status(ctx); 1239 1240 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1241 struct tx_ring *txr = &tx_que->txr; 1242 1243 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1244 } 1245 1246 /* Setup VLAN support, basic and offload if available */ 1247 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1248 1249 /* Clear bad data from Rx FIFOs */ 1250 if (adapter->hw.mac.type >= igb_mac_min) 1251 e1000_rx_fifo_flush_82575(&adapter->hw); 1252 1253 /* Configure for OS presence */ 1254 em_init_manageability(adapter); 1255 1256 /* Prepare transmit descriptors and buffers */ 1257 em_initialize_transmit_unit(ctx); 1258 1259 /* Setup Multicast table */ 1260 em_if_multi_set(ctx); 1261 1262 /* 1263 * Figure out the desired mbuf 1264 * pool for doing jumbos 1265 */ 1266 if (adapter->hw.mac.max_frame_size <= 2048) 1267 adapter->rx_mbuf_sz = MCLBYTES; 1268 #ifndef CONTIGMALLOC_WORKS 1269 else 1270 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1271 #else 1272 else if (adapter->hw.mac.max_frame_size <= 4096) 1273 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1274 else 1275 adapter->rx_mbuf_sz = MJUM9BYTES; 1276 #endif 1277 em_initialize_receive_unit(ctx); 1278 1279 /* Use real VLAN Filter support? */ 1280 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1281 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1282 /* Use real VLAN Filter support */ 1283 em_setup_vlan_hw_support(adapter); 1284 else { 1285 u32 ctrl; 1286 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1287 ctrl |= E1000_CTRL_VME; 1288 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1289 } 1290 } 1291 1292 /* Don't lose promiscuous settings */ 1293 em_if_set_promisc(ctx, IFF_PROMISC); 1294 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1295 1296 /* MSI/X configuration for 82574 */ 1297 if (adapter->hw.mac.type == e1000_82574) { 1298 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1299 1300 tmp |= E1000_CTRL_EXT_PBA_CLR; 1301 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1302 /* Set the IVAR - interrupt vector routing. */ 1303 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1304 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1305 igb_configure_queues(adapter); 1306 1307 /* this clears any pending interrupts */ 1308 E1000_READ_REG(&adapter->hw, E1000_ICR); 1309 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1310 1311 /* AMT based hardware can now take control from firmware */ 1312 if (adapter->has_manage && adapter->has_amt) 1313 em_get_hw_control(adapter); 1314 1315 /* Set Energy Efficient Ethernet */ 1316 if (adapter->hw.mac.type >= igb_mac_min && 1317 adapter->hw.phy.media_type == e1000_media_type_copper) { 1318 if (adapter->hw.mac.type == e1000_i354) 1319 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1320 else 1321 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1322 } 1323 } 1324 1325 /********************************************************************* 1326 * 1327 * Fast Legacy/MSI Combined Interrupt Service routine 1328 * 1329 *********************************************************************/ 1330 int 1331 em_intr(void *arg) 1332 { 1333 struct adapter *adapter = arg; 1334 if_ctx_t ctx = adapter->ctx; 1335 u32 reg_icr; 1336 1337 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1338 1339 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1340 goto skip_stray; 1341 /* Hot eject? */ 1342 if (reg_icr == 0xffffffff) 1343 return FILTER_STRAY; 1344 1345 /* Definitely not our interrupt. */ 1346 if (reg_icr == 0x0) 1347 return FILTER_STRAY; 1348 1349 /* 1350 * Starting with the 82571 chip, bit 31 should be used to 1351 * determine whether the interrupt belongs to us. 1352 */ 1353 if (adapter->hw.mac.type >= e1000_82571 && 1354 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1355 return FILTER_STRAY; 1356 1357 skip_stray: 1358 /* Link status change */ 1359 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1360 adapter->hw.mac.get_link_status = 1; 1361 iflib_admin_intr_deferred(ctx); 1362 } 1363 1364 if (reg_icr & E1000_ICR_RXO) 1365 adapter->rx_overruns++; 1366 1367 return (FILTER_SCHEDULE_THREAD); 1368 } 1369 1370 static void 1371 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1372 { 1373 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1374 } 1375 1376 static void 1377 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1378 { 1379 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1380 } 1381 1382 static void 1383 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1384 { 1385 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1386 } 1387 1388 static void 1389 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1390 { 1391 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1392 } 1393 1394 static int 1395 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1396 { 1397 struct adapter *adapter = iflib_get_softc(ctx); 1398 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1399 1400 if (adapter->hw.mac.type >= igb_mac_min) 1401 igb_rx_enable_queue(adapter, rxq); 1402 else 1403 em_rx_enable_queue(adapter, rxq); 1404 return (0); 1405 } 1406 1407 static int 1408 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1409 { 1410 struct adapter *adapter = iflib_get_softc(ctx); 1411 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1412 1413 if (adapter->hw.mac.type >= igb_mac_min) 1414 igb_tx_enable_queue(adapter, txq); 1415 else 1416 em_tx_enable_queue(adapter, txq); 1417 return (0); 1418 } 1419 1420 /********************************************************************* 1421 * 1422 * MSIX RX Interrupt Service routine 1423 * 1424 **********************************************************************/ 1425 static int 1426 em_msix_que(void *arg) 1427 { 1428 struct em_rx_queue *que = arg; 1429 1430 ++que->irqs; 1431 1432 return (FILTER_SCHEDULE_THREAD); 1433 } 1434 1435 /********************************************************************* 1436 * 1437 * MSIX Link Fast Interrupt Service routine 1438 * 1439 **********************************************************************/ 1440 static int 1441 em_msix_link(void *arg) 1442 { 1443 struct adapter *adapter = arg; 1444 u32 reg_icr; 1445 1446 ++adapter->link_irq; 1447 MPASS(adapter->hw.back != NULL); 1448 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1449 1450 if (reg_icr & E1000_ICR_RXO) 1451 adapter->rx_overruns++; 1452 1453 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1454 em_handle_link(adapter->ctx); 1455 } else { 1456 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1457 EM_MSIX_LINK | E1000_IMS_LSC); 1458 if (adapter->hw.mac.type >= igb_mac_min) 1459 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1460 } 1461 1462 /* 1463 * Because we must read the ICR for this interrupt 1464 * it may clear other causes using autoclear, for 1465 * this reason we simply create a soft interrupt 1466 * for all these vectors. 1467 */ 1468 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1469 E1000_WRITE_REG(&adapter->hw, 1470 E1000_ICS, adapter->ims); 1471 } 1472 1473 return (FILTER_HANDLED); 1474 } 1475 1476 static void 1477 em_handle_link(void *context) 1478 { 1479 if_ctx_t ctx = context; 1480 struct adapter *adapter = iflib_get_softc(ctx); 1481 1482 adapter->hw.mac.get_link_status = 1; 1483 iflib_admin_intr_deferred(ctx); 1484 } 1485 1486 1487 /********************************************************************* 1488 * 1489 * Media Ioctl callback 1490 * 1491 * This routine is called whenever the user queries the status of 1492 * the interface using ifconfig. 1493 * 1494 **********************************************************************/ 1495 static void 1496 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1497 { 1498 struct adapter *adapter = iflib_get_softc(ctx); 1499 u_char fiber_type = IFM_1000_SX; 1500 1501 INIT_DEBUGOUT("em_if_media_status: begin"); 1502 1503 iflib_admin_intr_deferred(ctx); 1504 1505 ifmr->ifm_status = IFM_AVALID; 1506 ifmr->ifm_active = IFM_ETHER; 1507 1508 if (!adapter->link_active) { 1509 return; 1510 } 1511 1512 ifmr->ifm_status |= IFM_ACTIVE; 1513 1514 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1515 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1516 if (adapter->hw.mac.type == e1000_82545) 1517 fiber_type = IFM_1000_LX; 1518 ifmr->ifm_active |= fiber_type | IFM_FDX; 1519 } else { 1520 switch (adapter->link_speed) { 1521 case 10: 1522 ifmr->ifm_active |= IFM_10_T; 1523 break; 1524 case 100: 1525 ifmr->ifm_active |= IFM_100_TX; 1526 break; 1527 case 1000: 1528 ifmr->ifm_active |= IFM_1000_T; 1529 break; 1530 } 1531 if (adapter->link_duplex == FULL_DUPLEX) 1532 ifmr->ifm_active |= IFM_FDX; 1533 else 1534 ifmr->ifm_active |= IFM_HDX; 1535 } 1536 } 1537 1538 /********************************************************************* 1539 * 1540 * Media Ioctl callback 1541 * 1542 * This routine is called when the user changes speed/duplex using 1543 * media/mediopt option with ifconfig. 1544 * 1545 **********************************************************************/ 1546 static int 1547 em_if_media_change(if_ctx_t ctx) 1548 { 1549 struct adapter *adapter = iflib_get_softc(ctx); 1550 struct ifmedia *ifm = iflib_get_media(ctx); 1551 1552 INIT_DEBUGOUT("em_if_media_change: begin"); 1553 1554 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1555 return (EINVAL); 1556 1557 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1558 case IFM_AUTO: 1559 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1560 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1561 break; 1562 case IFM_1000_LX: 1563 case IFM_1000_SX: 1564 case IFM_1000_T: 1565 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1566 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1567 break; 1568 case IFM_100_TX: 1569 adapter->hw.mac.autoneg = FALSE; 1570 adapter->hw.phy.autoneg_advertised = 0; 1571 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1572 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1573 else 1574 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1575 break; 1576 case IFM_10_T: 1577 adapter->hw.mac.autoneg = FALSE; 1578 adapter->hw.phy.autoneg_advertised = 0; 1579 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1580 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1581 else 1582 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1583 break; 1584 default: 1585 device_printf(adapter->dev, "Unsupported media type\n"); 1586 } 1587 1588 em_if_init(ctx); 1589 1590 return (0); 1591 } 1592 1593 static int 1594 em_if_set_promisc(if_ctx_t ctx, int flags) 1595 { 1596 struct adapter *adapter = iflib_get_softc(ctx); 1597 u32 reg_rctl; 1598 1599 em_disable_promisc(ctx); 1600 1601 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1602 1603 if (flags & IFF_PROMISC) { 1604 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1605 /* Turn this on if you want to see bad packets */ 1606 if (em_debug_sbp) 1607 reg_rctl |= E1000_RCTL_SBP; 1608 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1609 } else if (flags & IFF_ALLMULTI) { 1610 reg_rctl |= E1000_RCTL_MPE; 1611 reg_rctl &= ~E1000_RCTL_UPE; 1612 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1613 } 1614 return (0); 1615 } 1616 1617 static void 1618 em_disable_promisc(if_ctx_t ctx) 1619 { 1620 struct adapter *adapter = iflib_get_softc(ctx); 1621 struct ifnet *ifp = iflib_get_ifp(ctx); 1622 u32 reg_rctl; 1623 int mcnt = 0; 1624 1625 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1626 reg_rctl &= (~E1000_RCTL_UPE); 1627 if (if_getflags(ifp) & IFF_ALLMULTI) 1628 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1629 else 1630 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1631 /* Don't disable if in MAX groups */ 1632 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1633 reg_rctl &= (~E1000_RCTL_MPE); 1634 reg_rctl &= (~E1000_RCTL_SBP); 1635 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1636 } 1637 1638 1639 /********************************************************************* 1640 * Multicast Update 1641 * 1642 * This routine is called whenever multicast address list is updated. 1643 * 1644 **********************************************************************/ 1645 1646 static void 1647 em_if_multi_set(if_ctx_t ctx) 1648 { 1649 struct adapter *adapter = iflib_get_softc(ctx); 1650 struct ifnet *ifp = iflib_get_ifp(ctx); 1651 u32 reg_rctl = 0; 1652 u8 *mta; /* Multicast array memory */ 1653 int mcnt = 0; 1654 1655 IOCTL_DEBUGOUT("em_set_multi: begin"); 1656 1657 mta = adapter->mta; 1658 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1659 1660 if (adapter->hw.mac.type == e1000_82542 && 1661 adapter->hw.revision_id == E1000_REVISION_2) { 1662 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1663 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1664 e1000_pci_clear_mwi(&adapter->hw); 1665 reg_rctl |= E1000_RCTL_RST; 1666 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1667 msec_delay(5); 1668 } 1669 1670 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1671 1672 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1673 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1674 reg_rctl |= E1000_RCTL_MPE; 1675 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1676 } else 1677 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1678 1679 if (adapter->hw.mac.type == e1000_82542 && 1680 adapter->hw.revision_id == E1000_REVISION_2) { 1681 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1682 reg_rctl &= ~E1000_RCTL_RST; 1683 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1684 msec_delay(5); 1685 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1686 e1000_pci_set_mwi(&adapter->hw); 1687 } 1688 } 1689 1690 1691 /********************************************************************* 1692 * Timer routine 1693 * 1694 * This routine checks for link status and updates statistics. 1695 * 1696 **********************************************************************/ 1697 1698 static void 1699 em_if_timer(if_ctx_t ctx, uint16_t qid) 1700 { 1701 struct adapter *adapter = iflib_get_softc(ctx); 1702 struct em_rx_queue *que; 1703 int i; 1704 int trigger = 0; 1705 1706 if (qid != 0) 1707 return; 1708 1709 iflib_admin_intr_deferred(ctx); 1710 1711 /* Mask to use in the irq trigger */ 1712 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1713 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1714 trigger |= que->eims; 1715 } else { 1716 trigger = E1000_ICS_RXDMT0; 1717 } 1718 } 1719 1720 1721 static void 1722 em_if_update_admin_status(if_ctx_t ctx) 1723 { 1724 struct adapter *adapter = iflib_get_softc(ctx); 1725 struct e1000_hw *hw = &adapter->hw; 1726 device_t dev = iflib_get_dev(ctx); 1727 u32 link_check, thstat, ctrl; 1728 1729 link_check = thstat = ctrl = 0; 1730 /* Get the cached link value or read phy for real */ 1731 switch (hw->phy.media_type) { 1732 case e1000_media_type_copper: 1733 if (hw->mac.get_link_status) { 1734 if (hw->mac.type == e1000_pch_spt) 1735 msec_delay(50); 1736 /* Do the work to read phy */ 1737 e1000_check_for_link(hw); 1738 link_check = !hw->mac.get_link_status; 1739 if (link_check) /* ESB2 fix */ 1740 e1000_cfg_on_link_up(hw); 1741 } else { 1742 link_check = TRUE; 1743 } 1744 break; 1745 case e1000_media_type_fiber: 1746 e1000_check_for_link(hw); 1747 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1748 E1000_STATUS_LU); 1749 break; 1750 case e1000_media_type_internal_serdes: 1751 e1000_check_for_link(hw); 1752 link_check = adapter->hw.mac.serdes_has_link; 1753 break; 1754 /* VF device is type_unknown */ 1755 case e1000_media_type_unknown: 1756 e1000_check_for_link(hw); 1757 link_check = !hw->mac.get_link_status; 1758 /* FALLTHROUGH */ 1759 default: 1760 break; 1761 } 1762 1763 /* Check for thermal downshift or shutdown */ 1764 if (hw->mac.type == e1000_i350) { 1765 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1766 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1767 } 1768 1769 /* Now check for a transition */ 1770 if (link_check && (adapter->link_active == 0)) { 1771 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1772 &adapter->link_duplex); 1773 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1774 if ((adapter->link_speed != SPEED_1000) && 1775 ((hw->mac.type == e1000_82571) || 1776 (hw->mac.type == e1000_82572))) { 1777 int tarc0; 1778 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1779 tarc0 &= ~TARC_SPEED_MODE_BIT; 1780 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1781 } 1782 if (bootverbose) 1783 device_printf(dev, "Link is up %d Mbps %s\n", 1784 adapter->link_speed, 1785 ((adapter->link_duplex == FULL_DUPLEX) ? 1786 "Full Duplex" : "Half Duplex")); 1787 adapter->link_active = 1; 1788 adapter->smartspeed = 0; 1789 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1790 E1000_CTRL_EXT_LINK_MODE_GMII && 1791 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1792 device_printf(dev, "Link: thermal downshift\n"); 1793 /* Delay Link Up for Phy update */ 1794 if (((hw->mac.type == e1000_i210) || 1795 (hw->mac.type == e1000_i211)) && 1796 (hw->phy.id == I210_I_PHY_ID)) 1797 msec_delay(I210_LINK_DELAY); 1798 /* Reset if the media type changed. */ 1799 if ((hw->dev_spec._82575.media_changed) && 1800 (adapter->hw.mac.type >= igb_mac_min)) { 1801 hw->dev_spec._82575.media_changed = false; 1802 adapter->flags |= IGB_MEDIA_RESET; 1803 em_reset(ctx); 1804 } 1805 iflib_link_state_change(ctx, LINK_STATE_UP, 1806 IF_Mbps(adapter->link_speed)); 1807 printf("Link state changed to up\n"); 1808 } else if (!link_check && (adapter->link_active == 1)) { 1809 adapter->link_speed = 0; 1810 adapter->link_duplex = 0; 1811 adapter->link_active = 0; 1812 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1813 printf("Link state changed to down\n"); 1814 } 1815 em_update_stats_counters(adapter); 1816 1817 /* Reset LAA into RAR[0] on 82571 */ 1818 if ((adapter->hw.mac.type == e1000_82571) && 1819 e1000_get_laa_state_82571(&adapter->hw)) 1820 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1821 1822 if (adapter->hw.mac.type < em_mac_min) 1823 lem_smartspeed(adapter); 1824 1825 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1826 } 1827 1828 /********************************************************************* 1829 * 1830 * This routine disables all traffic on the adapter by issuing a 1831 * global reset on the MAC and deallocates TX/RX buffers. 1832 * 1833 * This routine should always be called with BOTH the CORE 1834 * and TX locks. 1835 **********************************************************************/ 1836 1837 static void 1838 em_if_stop(if_ctx_t ctx) 1839 { 1840 struct adapter *adapter = iflib_get_softc(ctx); 1841 1842 INIT_DEBUGOUT("em_stop: begin"); 1843 1844 e1000_reset_hw(&adapter->hw); 1845 if (adapter->hw.mac.type >= e1000_82544) 1846 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1847 1848 e1000_led_off(&adapter->hw); 1849 e1000_cleanup_led(&adapter->hw); 1850 } 1851 1852 1853 /********************************************************************* 1854 * 1855 * Determine hardware revision. 1856 * 1857 **********************************************************************/ 1858 static void 1859 em_identify_hardware(if_ctx_t ctx) 1860 { 1861 device_t dev = iflib_get_dev(ctx); 1862 struct adapter *adapter = iflib_get_softc(ctx); 1863 1864 /* Make sure our PCI config space has the necessary stuff set */ 1865 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1866 1867 /* Save off the information about this board */ 1868 adapter->hw.vendor_id = pci_get_vendor(dev); 1869 adapter->hw.device_id = pci_get_device(dev); 1870 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1871 adapter->hw.subsystem_vendor_id = 1872 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1873 adapter->hw.subsystem_device_id = 1874 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1875 1876 /* Do Shared Code Init and Setup */ 1877 if (e1000_set_mac_type(&adapter->hw)) { 1878 device_printf(dev, "Setup init failure\n"); 1879 return; 1880 } 1881 } 1882 1883 static int 1884 em_allocate_pci_resources(if_ctx_t ctx) 1885 { 1886 struct adapter *adapter = iflib_get_softc(ctx); 1887 device_t dev = iflib_get_dev(ctx); 1888 int rid, val; 1889 1890 rid = PCIR_BAR(0); 1891 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1892 &rid, RF_ACTIVE); 1893 if (adapter->memory == NULL) { 1894 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1895 return (ENXIO); 1896 } 1897 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1898 adapter->osdep.mem_bus_space_handle = 1899 rman_get_bushandle(adapter->memory); 1900 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1901 1902 /* Only older adapters use IO mapping */ 1903 if (adapter->hw.mac.type < em_mac_min && 1904 adapter->hw.mac.type > e1000_82543) { 1905 /* Figure our where our IO BAR is ? */ 1906 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1907 val = pci_read_config(dev, rid, 4); 1908 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1909 adapter->io_rid = rid; 1910 break; 1911 } 1912 rid += 4; 1913 /* check for 64bit BAR */ 1914 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1915 rid += 4; 1916 } 1917 if (rid >= PCIR_CIS) { 1918 device_printf(dev, "Unable to locate IO BAR\n"); 1919 return (ENXIO); 1920 } 1921 adapter->ioport = bus_alloc_resource_any(dev, 1922 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1923 if (adapter->ioport == NULL) { 1924 device_printf(dev, "Unable to allocate bus resource: " 1925 "ioport\n"); 1926 return (ENXIO); 1927 } 1928 adapter->hw.io_base = 0; 1929 adapter->osdep.io_bus_space_tag = 1930 rman_get_bustag(adapter->ioport); 1931 adapter->osdep.io_bus_space_handle = 1932 rman_get_bushandle(adapter->ioport); 1933 } 1934 1935 adapter->hw.back = &adapter->osdep; 1936 1937 return (0); 1938 } 1939 1940 /********************************************************************* 1941 * 1942 * Setup the MSIX Interrupt handlers 1943 * 1944 **********************************************************************/ 1945 static int 1946 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1947 { 1948 struct adapter *adapter = iflib_get_softc(ctx); 1949 struct em_rx_queue *rx_que = adapter->rx_queues; 1950 struct em_tx_queue *tx_que = adapter->tx_queues; 1951 int error, rid, i, vector = 0, rx_vectors; 1952 char buf[16]; 1953 1954 /* First set up ring resources */ 1955 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1956 rid = vector + 1; 1957 snprintf(buf, sizeof(buf), "rxq%d", i); 1958 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1959 if (error) { 1960 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1961 adapter->rx_num_queues = i + 1; 1962 goto fail; 1963 } 1964 1965 rx_que->msix = vector; 1966 1967 /* 1968 * Set the bit to enable interrupt 1969 * in E1000_IMS -- bits 20 and 21 1970 * are for RX0 and RX1, note this has 1971 * NOTHING to do with the MSIX vector 1972 */ 1973 if (adapter->hw.mac.type == e1000_82574) { 1974 rx_que->eims = 1 << (20 + i); 1975 adapter->ims |= rx_que->eims; 1976 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1977 } else if (adapter->hw.mac.type == e1000_82575) 1978 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1979 else 1980 rx_que->eims = 1 << vector; 1981 } 1982 rx_vectors = vector; 1983 1984 vector = 0; 1985 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1986 snprintf(buf, sizeof(buf), "txq%d", i); 1987 tx_que = &adapter->tx_queues[i]; 1988 iflib_softirq_alloc_generic(ctx, 1989 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1990 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1991 1992 tx_que->msix = (vector % adapter->tx_num_queues); 1993 1994 /* 1995 * Set the bit to enable interrupt 1996 * in E1000_IMS -- bits 22 and 23 1997 * are for TX0 and TX1, note this has 1998 * NOTHING to do with the MSIX vector 1999 */ 2000 if (adapter->hw.mac.type == e1000_82574) { 2001 tx_que->eims = 1 << (22 + i); 2002 adapter->ims |= tx_que->eims; 2003 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2004 } else if (adapter->hw.mac.type == e1000_82575) { 2005 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 2006 } else { 2007 tx_que->eims = 1 << (i % adapter->tx_num_queues); 2008 } 2009 } 2010 2011 /* Link interrupt */ 2012 rid = rx_vectors + 1; 2013 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2014 2015 if (error) { 2016 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2017 goto fail; 2018 } 2019 adapter->linkvec = rx_vectors; 2020 if (adapter->hw.mac.type < igb_mac_min) { 2021 adapter->ivars |= (8 | rx_vectors) << 16; 2022 adapter->ivars |= 0x80000000; 2023 } 2024 return (0); 2025 fail: 2026 iflib_irq_free(ctx, &adapter->irq); 2027 rx_que = adapter->rx_queues; 2028 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2029 iflib_irq_free(ctx, &rx_que->que_irq); 2030 return (error); 2031 } 2032 2033 static void 2034 igb_configure_queues(struct adapter *adapter) 2035 { 2036 struct e1000_hw *hw = &adapter->hw; 2037 struct em_rx_queue *rx_que; 2038 struct em_tx_queue *tx_que; 2039 u32 tmp, ivar = 0, newitr = 0; 2040 2041 /* First turn on RSS capability */ 2042 if (adapter->hw.mac.type != e1000_82575) 2043 E1000_WRITE_REG(hw, E1000_GPIE, 2044 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2045 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2046 2047 /* Turn on MSIX */ 2048 switch (adapter->hw.mac.type) { 2049 case e1000_82580: 2050 case e1000_i350: 2051 case e1000_i354: 2052 case e1000_i210: 2053 case e1000_i211: 2054 case e1000_vfadapt: 2055 case e1000_vfadapt_i350: 2056 /* RX entries */ 2057 for (int i = 0; i < adapter->rx_num_queues; i++) { 2058 u32 index = i >> 1; 2059 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2060 rx_que = &adapter->rx_queues[i]; 2061 if (i & 1) { 2062 ivar &= 0xFF00FFFF; 2063 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2064 } else { 2065 ivar &= 0xFFFFFF00; 2066 ivar |= rx_que->msix | E1000_IVAR_VALID; 2067 } 2068 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2069 } 2070 /* TX entries */ 2071 for (int i = 0; i < adapter->tx_num_queues; i++) { 2072 u32 index = i >> 1; 2073 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2074 tx_que = &adapter->tx_queues[i]; 2075 if (i & 1) { 2076 ivar &= 0x00FFFFFF; 2077 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2078 } else { 2079 ivar &= 0xFFFF00FF; 2080 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2081 } 2082 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2083 adapter->que_mask |= tx_que->eims; 2084 } 2085 2086 /* And for the link interrupt */ 2087 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2088 adapter->link_mask = 1 << adapter->linkvec; 2089 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2090 break; 2091 case e1000_82576: 2092 /* RX entries */ 2093 for (int i = 0; i < adapter->rx_num_queues; i++) { 2094 u32 index = i & 0x7; /* Each IVAR has two entries */ 2095 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2096 rx_que = &adapter->rx_queues[i]; 2097 if (i < 8) { 2098 ivar &= 0xFFFFFF00; 2099 ivar |= rx_que->msix | E1000_IVAR_VALID; 2100 } else { 2101 ivar &= 0xFF00FFFF; 2102 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2103 } 2104 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2105 adapter->que_mask |= rx_que->eims; 2106 } 2107 /* TX entries */ 2108 for (int i = 0; i < adapter->tx_num_queues; i++) { 2109 u32 index = i & 0x7; /* Each IVAR has two entries */ 2110 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2111 tx_que = &adapter->tx_queues[i]; 2112 if (i < 8) { 2113 ivar &= 0xFFFF00FF; 2114 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2115 } else { 2116 ivar &= 0x00FFFFFF; 2117 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2118 } 2119 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2120 adapter->que_mask |= tx_que->eims; 2121 } 2122 2123 /* And for the link interrupt */ 2124 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2125 adapter->link_mask = 1 << adapter->linkvec; 2126 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2127 break; 2128 2129 case e1000_82575: 2130 /* enable MSI-X support*/ 2131 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2132 tmp |= E1000_CTRL_EXT_PBA_CLR; 2133 /* Auto-Mask interrupts upon ICR read. */ 2134 tmp |= E1000_CTRL_EXT_EIAME; 2135 tmp |= E1000_CTRL_EXT_IRCA; 2136 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2137 2138 /* Queues */ 2139 for (int i = 0; i < adapter->rx_num_queues; i++) { 2140 rx_que = &adapter->rx_queues[i]; 2141 tmp = E1000_EICR_RX_QUEUE0 << i; 2142 tmp |= E1000_EICR_TX_QUEUE0 << i; 2143 rx_que->eims = tmp; 2144 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2145 i, rx_que->eims); 2146 adapter->que_mask |= rx_que->eims; 2147 } 2148 2149 /* Link */ 2150 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2151 E1000_EIMS_OTHER); 2152 adapter->link_mask |= E1000_EIMS_OTHER; 2153 default: 2154 break; 2155 } 2156 2157 /* Set the starting interrupt rate */ 2158 if (em_max_interrupt_rate > 0) 2159 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2160 2161 if (hw->mac.type == e1000_82575) 2162 newitr |= newitr << 16; 2163 else 2164 newitr |= E1000_EITR_CNT_IGNR; 2165 2166 for (int i = 0; i < adapter->rx_num_queues; i++) { 2167 rx_que = &adapter->rx_queues[i]; 2168 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2169 } 2170 2171 return; 2172 } 2173 2174 static void 2175 em_free_pci_resources(if_ctx_t ctx) 2176 { 2177 struct adapter *adapter = iflib_get_softc(ctx); 2178 struct em_rx_queue *que = adapter->rx_queues; 2179 device_t dev = iflib_get_dev(ctx); 2180 2181 /* Release all msix queue resources */ 2182 if (adapter->intr_type == IFLIB_INTR_MSIX) 2183 iflib_irq_free(ctx, &adapter->irq); 2184 2185 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2186 iflib_irq_free(ctx, &que->que_irq); 2187 } 2188 2189 /* First release all the interrupt resources */ 2190 if (adapter->memory != NULL) { 2191 bus_release_resource(dev, SYS_RES_MEMORY, 2192 PCIR_BAR(0), adapter->memory); 2193 adapter->memory = NULL; 2194 } 2195 2196 if (adapter->flash != NULL) { 2197 bus_release_resource(dev, SYS_RES_MEMORY, 2198 EM_FLASH, adapter->flash); 2199 adapter->flash = NULL; 2200 } 2201 if (adapter->ioport != NULL) 2202 bus_release_resource(dev, SYS_RES_IOPORT, 2203 adapter->io_rid, adapter->ioport); 2204 } 2205 2206 /* Setup MSI or MSI/X */ 2207 static int 2208 em_setup_msix(if_ctx_t ctx) 2209 { 2210 struct adapter *adapter = iflib_get_softc(ctx); 2211 2212 if (adapter->hw.mac.type == e1000_82574) { 2213 em_enable_vectors_82574(ctx); 2214 } 2215 return (0); 2216 } 2217 2218 /********************************************************************* 2219 * 2220 * Initialize the hardware to a configuration 2221 * as specified by the adapter structure. 2222 * 2223 **********************************************************************/ 2224 2225 static void 2226 lem_smartspeed(struct adapter *adapter) 2227 { 2228 u16 phy_tmp; 2229 2230 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2231 adapter->hw.mac.autoneg == 0 || 2232 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2233 return; 2234 2235 if (adapter->smartspeed == 0) { 2236 /* If Master/Slave config fault is asserted twice, 2237 * we assume back-to-back */ 2238 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2239 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2240 return; 2241 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2242 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2243 e1000_read_phy_reg(&adapter->hw, 2244 PHY_1000T_CTRL, &phy_tmp); 2245 if(phy_tmp & CR_1000T_MS_ENABLE) { 2246 phy_tmp &= ~CR_1000T_MS_ENABLE; 2247 e1000_write_phy_reg(&adapter->hw, 2248 PHY_1000T_CTRL, phy_tmp); 2249 adapter->smartspeed++; 2250 if(adapter->hw.mac.autoneg && 2251 !e1000_copper_link_autoneg(&adapter->hw) && 2252 !e1000_read_phy_reg(&adapter->hw, 2253 PHY_CONTROL, &phy_tmp)) { 2254 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2255 MII_CR_RESTART_AUTO_NEG); 2256 e1000_write_phy_reg(&adapter->hw, 2257 PHY_CONTROL, phy_tmp); 2258 } 2259 } 2260 } 2261 return; 2262 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2263 /* If still no link, perhaps using 2/3 pair cable */ 2264 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2265 phy_tmp |= CR_1000T_MS_ENABLE; 2266 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2267 if(adapter->hw.mac.autoneg && 2268 !e1000_copper_link_autoneg(&adapter->hw) && 2269 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2270 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2271 MII_CR_RESTART_AUTO_NEG); 2272 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2273 } 2274 } 2275 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2276 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2277 adapter->smartspeed = 0; 2278 } 2279 2280 /********************************************************************* 2281 * 2282 * Initialize the DMA Coalescing feature 2283 * 2284 **********************************************************************/ 2285 static void 2286 igb_init_dmac(struct adapter *adapter, u32 pba) 2287 { 2288 device_t dev = adapter->dev; 2289 struct e1000_hw *hw = &adapter->hw; 2290 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2291 u16 hwm; 2292 u16 max_frame_size; 2293 2294 if (hw->mac.type == e1000_i211) 2295 return; 2296 2297 max_frame_size = adapter->shared->isc_max_frame_size; 2298 if (hw->mac.type > e1000_82580) { 2299 2300 if (adapter->dmac == 0) { /* Disabling it */ 2301 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2302 return; 2303 } else 2304 device_printf(dev, "DMA Coalescing enabled\n"); 2305 2306 /* Set starting threshold */ 2307 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2308 2309 hwm = 64 * pba - max_frame_size / 16; 2310 if (hwm < 64 * (pba - 6)) 2311 hwm = 64 * (pba - 6); 2312 reg = E1000_READ_REG(hw, E1000_FCRTC); 2313 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2314 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2315 & E1000_FCRTC_RTH_COAL_MASK); 2316 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2317 2318 2319 dmac = pba - max_frame_size / 512; 2320 if (dmac < pba - 10) 2321 dmac = pba - 10; 2322 reg = E1000_READ_REG(hw, E1000_DMACR); 2323 reg &= ~E1000_DMACR_DMACTHR_MASK; 2324 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2325 & E1000_DMACR_DMACTHR_MASK); 2326 2327 /* transition to L0x or L1 if available..*/ 2328 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2329 2330 /* Check if status is 2.5Gb backplane connection 2331 * before configuration of watchdog timer, which is 2332 * in msec values in 12.8usec intervals 2333 * watchdog timer= msec values in 32usec intervals 2334 * for non 2.5Gb connection 2335 */ 2336 if (hw->mac.type == e1000_i354) { 2337 int status = E1000_READ_REG(hw, E1000_STATUS); 2338 if ((status & E1000_STATUS_2P5_SKU) && 2339 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2340 reg |= ((adapter->dmac * 5) >> 6); 2341 else 2342 reg |= (adapter->dmac >> 5); 2343 } else { 2344 reg |= (adapter->dmac >> 5); 2345 } 2346 2347 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2348 2349 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2350 2351 /* Set the interval before transition */ 2352 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2353 if (hw->mac.type == e1000_i350) 2354 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2355 /* 2356 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2357 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2358 */ 2359 if (hw->mac.type == e1000_i354) { 2360 int status = E1000_READ_REG(hw, E1000_STATUS); 2361 if ((status & E1000_STATUS_2P5_SKU) && 2362 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2363 reg |= 0xA; 2364 else 2365 reg |= 0x4; 2366 } else { 2367 reg |= 0x4; 2368 } 2369 2370 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2371 2372 /* free space in tx packet buffer to wake from DMA coal */ 2373 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2374 (2 * max_frame_size)) >> 6); 2375 2376 /* make low power state decision controlled by DMA coal */ 2377 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2378 reg &= ~E1000_PCIEMISC_LX_DECISION; 2379 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2380 2381 } else if (hw->mac.type == e1000_82580) { 2382 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2383 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2384 reg & ~E1000_PCIEMISC_LX_DECISION); 2385 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2386 } 2387 } 2388 2389 static void 2390 em_reset(if_ctx_t ctx) 2391 { 2392 device_t dev = iflib_get_dev(ctx); 2393 struct adapter *adapter = iflib_get_softc(ctx); 2394 struct ifnet *ifp = iflib_get_ifp(ctx); 2395 struct e1000_hw *hw = &adapter->hw; 2396 u16 rx_buffer_size; 2397 u32 pba; 2398 2399 INIT_DEBUGOUT("em_reset: begin"); 2400 /* Let the firmware know the OS is in control */ 2401 em_get_hw_control(adapter); 2402 2403 /* Set up smart power down as default off on newer adapters. */ 2404 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2405 hw->mac.type == e1000_82572)) { 2406 u16 phy_tmp = 0; 2407 2408 /* Speed up time to link by disabling smart power down. */ 2409 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2410 phy_tmp &= ~IGP02E1000_PM_SPD; 2411 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2412 } 2413 2414 /* 2415 * Packet Buffer Allocation (PBA) 2416 * Writing PBA sets the receive portion of the buffer 2417 * the remainder is used for the transmit buffer. 2418 */ 2419 switch (hw->mac.type) { 2420 /* Total Packet Buffer on these is 48K */ 2421 case e1000_82571: 2422 case e1000_82572: 2423 case e1000_80003es2lan: 2424 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2425 break; 2426 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2427 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2428 break; 2429 case e1000_82574: 2430 case e1000_82583: 2431 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2432 break; 2433 case e1000_ich8lan: 2434 pba = E1000_PBA_8K; 2435 break; 2436 case e1000_ich9lan: 2437 case e1000_ich10lan: 2438 /* Boost Receive side for jumbo frames */ 2439 if (adapter->hw.mac.max_frame_size > 4096) 2440 pba = E1000_PBA_14K; 2441 else 2442 pba = E1000_PBA_10K; 2443 break; 2444 case e1000_pchlan: 2445 case e1000_pch2lan: 2446 case e1000_pch_lpt: 2447 case e1000_pch_spt: 2448 case e1000_pch_cnp: 2449 pba = E1000_PBA_26K; 2450 break; 2451 case e1000_82575: 2452 pba = E1000_PBA_32K; 2453 break; 2454 case e1000_82576: 2455 case e1000_vfadapt: 2456 pba = E1000_READ_REG(hw, E1000_RXPBS); 2457 pba &= E1000_RXPBS_SIZE_MASK_82576; 2458 break; 2459 case e1000_82580: 2460 case e1000_i350: 2461 case e1000_i354: 2462 case e1000_vfadapt_i350: 2463 pba = E1000_READ_REG(hw, E1000_RXPBS); 2464 pba = e1000_rxpbs_adjust_82580(pba); 2465 break; 2466 case e1000_i210: 2467 case e1000_i211: 2468 pba = E1000_PBA_34K; 2469 break; 2470 default: 2471 if (adapter->hw.mac.max_frame_size > 8192) 2472 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2473 else 2474 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2475 } 2476 2477 /* Special needs in case of Jumbo frames */ 2478 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2479 u32 tx_space, min_tx, min_rx; 2480 pba = E1000_READ_REG(hw, E1000_PBA); 2481 tx_space = pba >> 16; 2482 pba &= 0xffff; 2483 min_tx = (adapter->hw.mac.max_frame_size + 2484 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2485 min_tx = roundup2(min_tx, 1024); 2486 min_tx >>= 10; 2487 min_rx = adapter->hw.mac.max_frame_size; 2488 min_rx = roundup2(min_rx, 1024); 2489 min_rx >>= 10; 2490 if (tx_space < min_tx && 2491 ((min_tx - tx_space) < pba)) { 2492 pba = pba - (min_tx - tx_space); 2493 /* 2494 * if short on rx space, rx wins 2495 * and must trump tx adjustment 2496 */ 2497 if (pba < min_rx) 2498 pba = min_rx; 2499 } 2500 E1000_WRITE_REG(hw, E1000_PBA, pba); 2501 } 2502 2503 if (hw->mac.type < igb_mac_min) 2504 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2505 2506 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2507 2508 /* 2509 * These parameters control the automatic generation (Tx) and 2510 * response (Rx) to Ethernet PAUSE frames. 2511 * - High water mark should allow for at least two frames to be 2512 * received after sending an XOFF. 2513 * - Low water mark works best when it is very near the high water mark. 2514 * This allows the receiver to restart by sending XON when it has 2515 * drained a bit. Here we use an arbitrary value of 1500 which will 2516 * restart after one full frame is pulled from the buffer. There 2517 * could be several smaller frames in the buffer and if so they will 2518 * not trigger the XON until their total number reduces the buffer 2519 * by 1500. 2520 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2521 */ 2522 rx_buffer_size = (pba & 0xffff) << 10; 2523 hw->fc.high_water = rx_buffer_size - 2524 roundup2(adapter->hw.mac.max_frame_size, 1024); 2525 hw->fc.low_water = hw->fc.high_water - 1500; 2526 2527 if (adapter->fc) /* locally set flow control value? */ 2528 hw->fc.requested_mode = adapter->fc; 2529 else 2530 hw->fc.requested_mode = e1000_fc_full; 2531 2532 if (hw->mac.type == e1000_80003es2lan) 2533 hw->fc.pause_time = 0xFFFF; 2534 else 2535 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2536 2537 hw->fc.send_xon = TRUE; 2538 2539 /* Device specific overrides/settings */ 2540 switch (hw->mac.type) { 2541 case e1000_pchlan: 2542 /* Workaround: no TX flow ctrl for PCH */ 2543 hw->fc.requested_mode = e1000_fc_rx_pause; 2544 hw->fc.pause_time = 0xFFFF; /* override */ 2545 if (if_getmtu(ifp) > ETHERMTU) { 2546 hw->fc.high_water = 0x3500; 2547 hw->fc.low_water = 0x1500; 2548 } else { 2549 hw->fc.high_water = 0x5000; 2550 hw->fc.low_water = 0x3000; 2551 } 2552 hw->fc.refresh_time = 0x1000; 2553 break; 2554 case e1000_pch2lan: 2555 case e1000_pch_lpt: 2556 case e1000_pch_spt: 2557 case e1000_pch_cnp: 2558 hw->fc.high_water = 0x5C20; 2559 hw->fc.low_water = 0x5048; 2560 hw->fc.pause_time = 0x0650; 2561 hw->fc.refresh_time = 0x0400; 2562 /* Jumbos need adjusted PBA */ 2563 if (if_getmtu(ifp) > ETHERMTU) 2564 E1000_WRITE_REG(hw, E1000_PBA, 12); 2565 else 2566 E1000_WRITE_REG(hw, E1000_PBA, 26); 2567 break; 2568 case e1000_82575: 2569 case e1000_82576: 2570 /* 8-byte granularity */ 2571 hw->fc.low_water = hw->fc.high_water - 8; 2572 break; 2573 case e1000_82580: 2574 case e1000_i350: 2575 case e1000_i354: 2576 case e1000_i210: 2577 case e1000_i211: 2578 case e1000_vfadapt: 2579 case e1000_vfadapt_i350: 2580 /* 16-byte granularity */ 2581 hw->fc.low_water = hw->fc.high_water - 16; 2582 break; 2583 case e1000_ich9lan: 2584 case e1000_ich10lan: 2585 if (if_getmtu(ifp) > ETHERMTU) { 2586 hw->fc.high_water = 0x2800; 2587 hw->fc.low_water = hw->fc.high_water - 8; 2588 break; 2589 } 2590 /* FALLTHROUGH */ 2591 default: 2592 if (hw->mac.type == e1000_80003es2lan) 2593 hw->fc.pause_time = 0xFFFF; 2594 break; 2595 } 2596 2597 /* Issue a global reset */ 2598 e1000_reset_hw(hw); 2599 if (adapter->hw.mac.type >= igb_mac_min) { 2600 E1000_WRITE_REG(hw, E1000_WUC, 0); 2601 } else { 2602 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2603 em_disable_aspm(adapter); 2604 } 2605 if (adapter->flags & IGB_MEDIA_RESET) { 2606 e1000_setup_init_funcs(hw, TRUE); 2607 e1000_get_bus_info(hw); 2608 adapter->flags &= ~IGB_MEDIA_RESET; 2609 } 2610 /* and a re-init */ 2611 if (e1000_init_hw(hw) < 0) { 2612 device_printf(dev, "Hardware Initialization Failed\n"); 2613 return; 2614 } 2615 if (adapter->hw.mac.type >= igb_mac_min) 2616 igb_init_dmac(adapter, pba); 2617 2618 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2619 e1000_get_phy_info(hw); 2620 e1000_check_for_link(hw); 2621 } 2622 2623 #define RSSKEYLEN 10 2624 static void 2625 em_initialize_rss_mapping(struct adapter *adapter) 2626 { 2627 uint8_t rss_key[4 * RSSKEYLEN]; 2628 uint32_t reta = 0; 2629 struct e1000_hw *hw = &adapter->hw; 2630 int i; 2631 2632 /* 2633 * Configure RSS key 2634 */ 2635 arc4rand(rss_key, sizeof(rss_key), 0); 2636 for (i = 0; i < RSSKEYLEN; ++i) { 2637 uint32_t rssrk = 0; 2638 2639 rssrk = EM_RSSRK_VAL(rss_key, i); 2640 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2641 } 2642 2643 /* 2644 * Configure RSS redirect table in following fashion: 2645 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2646 */ 2647 for (i = 0; i < sizeof(reta); ++i) { 2648 uint32_t q; 2649 2650 q = (i % adapter->rx_num_queues) << 7; 2651 reta |= q << (8 * i); 2652 } 2653 2654 for (i = 0; i < 32; ++i) 2655 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2656 2657 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2658 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2659 E1000_MRQC_RSS_FIELD_IPV4 | 2660 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2661 E1000_MRQC_RSS_FIELD_IPV6_EX | 2662 E1000_MRQC_RSS_FIELD_IPV6); 2663 2664 } 2665 2666 static void 2667 igb_initialize_rss_mapping(struct adapter *adapter) 2668 { 2669 struct e1000_hw *hw = &adapter->hw; 2670 int i; 2671 int queue_id; 2672 u32 reta; 2673 u32 rss_key[10], mrqc, shift = 0; 2674 2675 /* XXX? */ 2676 if (adapter->hw.mac.type == e1000_82575) 2677 shift = 6; 2678 2679 /* 2680 * The redirection table controls which destination 2681 * queue each bucket redirects traffic to. 2682 * Each DWORD represents four queues, with the LSB 2683 * being the first queue in the DWORD. 2684 * 2685 * This just allocates buckets to queues using round-robin 2686 * allocation. 2687 * 2688 * NOTE: It Just Happens to line up with the default 2689 * RSS allocation method. 2690 */ 2691 2692 /* Warning FM follows */ 2693 reta = 0; 2694 for (i = 0; i < 128; i++) { 2695 #ifdef RSS 2696 queue_id = rss_get_indirection_to_bucket(i); 2697 /* 2698 * If we have more queues than buckets, we'll 2699 * end up mapping buckets to a subset of the 2700 * queues. 2701 * 2702 * If we have more buckets than queues, we'll 2703 * end up instead assigning multiple buckets 2704 * to queues. 2705 * 2706 * Both are suboptimal, but we need to handle 2707 * the case so we don't go out of bounds 2708 * indexing arrays and such. 2709 */ 2710 queue_id = queue_id % adapter->rx_num_queues; 2711 #else 2712 queue_id = (i % adapter->rx_num_queues); 2713 #endif 2714 /* Adjust if required */ 2715 queue_id = queue_id << shift; 2716 2717 /* 2718 * The low 8 bits are for hash value (n+0); 2719 * The next 8 bits are for hash value (n+1), etc. 2720 */ 2721 reta = reta >> 8; 2722 reta = reta | ( ((uint32_t) queue_id) << 24); 2723 if ((i & 3) == 3) { 2724 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2725 reta = 0; 2726 } 2727 } 2728 2729 /* Now fill in hash table */ 2730 2731 /* 2732 * MRQC: Multiple Receive Queues Command 2733 * Set queuing to RSS control, number depends on the device. 2734 */ 2735 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2736 2737 #ifdef RSS 2738 /* XXX ew typecasting */ 2739 rss_getkey((uint8_t *) &rss_key); 2740 #else 2741 arc4rand(&rss_key, sizeof(rss_key), 0); 2742 #endif 2743 for (i = 0; i < 10; i++) 2744 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2745 2746 /* 2747 * Configure the RSS fields to hash upon. 2748 */ 2749 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2750 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2751 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2752 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2753 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2754 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2755 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2756 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2757 2758 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2759 } 2760 2761 /********************************************************************* 2762 * 2763 * Setup networking device structure and register an interface. 2764 * 2765 **********************************************************************/ 2766 static int 2767 em_setup_interface(if_ctx_t ctx) 2768 { 2769 struct ifnet *ifp = iflib_get_ifp(ctx); 2770 struct adapter *adapter = iflib_get_softc(ctx); 2771 if_softc_ctx_t scctx = adapter->shared; 2772 2773 INIT_DEBUGOUT("em_setup_interface: begin"); 2774 2775 /* Single Queue */ 2776 if (adapter->tx_num_queues == 1) { 2777 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2778 if_setsendqready(ifp); 2779 } 2780 2781 /* 2782 * Specify the media types supported by this adapter and register 2783 * callbacks to update media and link information 2784 */ 2785 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2786 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2787 u_char fiber_type = IFM_1000_SX; /* default type */ 2788 2789 if (adapter->hw.mac.type == e1000_82545) 2790 fiber_type = IFM_1000_LX; 2791 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2792 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2793 } else { 2794 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2796 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2797 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2798 if (adapter->hw.phy.type != e1000_phy_ife) { 2799 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2800 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2801 } 2802 } 2803 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2804 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2805 return (0); 2806 } 2807 2808 static int 2809 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2810 { 2811 struct adapter *adapter = iflib_get_softc(ctx); 2812 if_softc_ctx_t scctx = adapter->shared; 2813 int error = E1000_SUCCESS; 2814 struct em_tx_queue *que; 2815 int i, j; 2816 2817 MPASS(adapter->tx_num_queues > 0); 2818 MPASS(adapter->tx_num_queues == ntxqsets); 2819 2820 /* First allocate the top level queue structs */ 2821 if (!(adapter->tx_queues = 2822 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2823 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2824 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2825 return(ENOMEM); 2826 } 2827 2828 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2829 /* Set up some basics */ 2830 2831 struct tx_ring *txr = &que->txr; 2832 txr->adapter = que->adapter = adapter; 2833 que->me = txr->me = i; 2834 2835 /* Allocate report status array */ 2836 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2837 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2838 error = ENOMEM; 2839 goto fail; 2840 } 2841 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2842 txr->tx_rsq[j] = QIDX_INVALID; 2843 /* get the virtual and physical address of the hardware queues */ 2844 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2845 txr->tx_paddr = paddrs[i*ntxqs]; 2846 } 2847 2848 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2849 return (0); 2850 fail: 2851 em_if_queues_free(ctx); 2852 return (error); 2853 } 2854 2855 static int 2856 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2857 { 2858 struct adapter *adapter = iflib_get_softc(ctx); 2859 int error = E1000_SUCCESS; 2860 struct em_rx_queue *que; 2861 int i; 2862 2863 MPASS(adapter->rx_num_queues > 0); 2864 MPASS(adapter->rx_num_queues == nrxqsets); 2865 2866 /* First allocate the top level queue structs */ 2867 if (!(adapter->rx_queues = 2868 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2869 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2870 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2871 error = ENOMEM; 2872 goto fail; 2873 } 2874 2875 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2876 /* Set up some basics */ 2877 struct rx_ring *rxr = &que->rxr; 2878 rxr->adapter = que->adapter = adapter; 2879 rxr->que = que; 2880 que->me = rxr->me = i; 2881 2882 /* get the virtual and physical address of the hardware queues */ 2883 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2884 rxr->rx_paddr = paddrs[i*nrxqs]; 2885 } 2886 2887 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2888 2889 return (0); 2890 fail: 2891 em_if_queues_free(ctx); 2892 return (error); 2893 } 2894 2895 static void 2896 em_if_queues_free(if_ctx_t ctx) 2897 { 2898 struct adapter *adapter = iflib_get_softc(ctx); 2899 struct em_tx_queue *tx_que = adapter->tx_queues; 2900 struct em_rx_queue *rx_que = adapter->rx_queues; 2901 2902 if (tx_que != NULL) { 2903 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2904 struct tx_ring *txr = &tx_que->txr; 2905 if (txr->tx_rsq == NULL) 2906 break; 2907 2908 free(txr->tx_rsq, M_DEVBUF); 2909 txr->tx_rsq = NULL; 2910 } 2911 free(adapter->tx_queues, M_DEVBUF); 2912 adapter->tx_queues = NULL; 2913 } 2914 2915 if (rx_que != NULL) { 2916 free(adapter->rx_queues, M_DEVBUF); 2917 adapter->rx_queues = NULL; 2918 } 2919 2920 em_release_hw_control(adapter); 2921 2922 if (adapter->mta != NULL) { 2923 free(adapter->mta, M_DEVBUF); 2924 } 2925 } 2926 2927 /********************************************************************* 2928 * 2929 * Enable transmit unit. 2930 * 2931 **********************************************************************/ 2932 static void 2933 em_initialize_transmit_unit(if_ctx_t ctx) 2934 { 2935 struct adapter *adapter = iflib_get_softc(ctx); 2936 if_softc_ctx_t scctx = adapter->shared; 2937 struct em_tx_queue *que; 2938 struct tx_ring *txr; 2939 struct e1000_hw *hw = &adapter->hw; 2940 u32 tctl, txdctl = 0, tarc, tipg = 0; 2941 2942 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2943 2944 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2945 u64 bus_addr; 2946 caddr_t offp, endp; 2947 2948 que = &adapter->tx_queues[i]; 2949 txr = &que->txr; 2950 bus_addr = txr->tx_paddr; 2951 2952 /* Clear checksum offload context. */ 2953 offp = (caddr_t)&txr->csum_flags; 2954 endp = (caddr_t)(txr + 1); 2955 bzero(offp, endp - offp); 2956 2957 /* Base and Len of TX Ring */ 2958 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2959 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2960 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2961 (u32)(bus_addr >> 32)); 2962 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2963 (u32)bus_addr); 2964 /* Init the HEAD/TAIL indices */ 2965 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2966 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2967 2968 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2969 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2970 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2971 2972 txdctl = 0; /* clear txdctl */ 2973 txdctl |= 0x1f; /* PTHRESH */ 2974 txdctl |= 1 << 8; /* HTHRESH */ 2975 txdctl |= 1 << 16;/* WTHRESH */ 2976 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2977 txdctl |= E1000_TXDCTL_GRAN; 2978 txdctl |= 1 << 25; /* LWTHRESH */ 2979 2980 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2981 } 2982 2983 /* Set the default values for the Tx Inter Packet Gap timer */ 2984 switch (adapter->hw.mac.type) { 2985 case e1000_80003es2lan: 2986 tipg = DEFAULT_82543_TIPG_IPGR1; 2987 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2988 E1000_TIPG_IPGR2_SHIFT; 2989 break; 2990 case e1000_82542: 2991 tipg = DEFAULT_82542_TIPG_IPGT; 2992 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2993 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2994 break; 2995 default: 2996 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2997 (adapter->hw.phy.media_type == 2998 e1000_media_type_internal_serdes)) 2999 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3000 else 3001 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3002 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3003 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3004 } 3005 3006 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3007 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3008 3009 if(adapter->hw.mac.type >= e1000_82540) 3010 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3011 adapter->tx_abs_int_delay.value); 3012 3013 if ((adapter->hw.mac.type == e1000_82571) || 3014 (adapter->hw.mac.type == e1000_82572)) { 3015 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3016 tarc |= TARC_SPEED_MODE_BIT; 3017 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3018 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3019 /* errata: program both queues to unweighted RR */ 3020 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3021 tarc |= 1; 3022 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3023 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3024 tarc |= 1; 3025 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3026 } else if (adapter->hw.mac.type == e1000_82574) { 3027 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3028 tarc |= TARC_ERRATA_BIT; 3029 if ( adapter->tx_num_queues > 1) { 3030 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3031 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3032 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3033 } else 3034 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3035 } 3036 3037 if (adapter->tx_int_delay.value > 0) 3038 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3039 3040 /* Program the Transmit Control Register */ 3041 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3042 tctl &= ~E1000_TCTL_CT; 3043 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3044 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3045 3046 if (adapter->hw.mac.type >= e1000_82571) 3047 tctl |= E1000_TCTL_MULR; 3048 3049 /* This write will effectively turn on the transmit unit. */ 3050 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3051 3052 /* SPT and KBL errata workarounds */ 3053 if (hw->mac.type == e1000_pch_spt) { 3054 u32 reg; 3055 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3056 reg |= E1000_RCTL_RDMTS_HEX; 3057 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3058 /* i218-i219 Specification Update 1.5.4.5 */ 3059 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3060 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3061 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3062 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3063 } 3064 } 3065 3066 /********************************************************************* 3067 * 3068 * Enable receive unit. 3069 * 3070 **********************************************************************/ 3071 3072 static void 3073 em_initialize_receive_unit(if_ctx_t ctx) 3074 { 3075 struct adapter *adapter = iflib_get_softc(ctx); 3076 if_softc_ctx_t scctx = adapter->shared; 3077 struct ifnet *ifp = iflib_get_ifp(ctx); 3078 struct e1000_hw *hw = &adapter->hw; 3079 struct em_rx_queue *que; 3080 int i; 3081 u32 rctl, rxcsum, rfctl; 3082 3083 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3084 3085 /* 3086 * Make sure receives are disabled while setting 3087 * up the descriptor ring 3088 */ 3089 rctl = E1000_READ_REG(hw, E1000_RCTL); 3090 /* Do not disable if ever enabled on this hardware */ 3091 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3092 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3093 3094 /* Setup the Receive Control Register */ 3095 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3096 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3097 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3098 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3099 3100 /* Do not store bad packets */ 3101 rctl &= ~E1000_RCTL_SBP; 3102 3103 /* Enable Long Packet receive */ 3104 if (if_getmtu(ifp) > ETHERMTU) 3105 rctl |= E1000_RCTL_LPE; 3106 else 3107 rctl &= ~E1000_RCTL_LPE; 3108 3109 /* Strip the CRC */ 3110 if (!em_disable_crc_stripping) 3111 rctl |= E1000_RCTL_SECRC; 3112 3113 if (adapter->hw.mac.type >= e1000_82540) { 3114 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3115 adapter->rx_abs_int_delay.value); 3116 3117 /* 3118 * Set the interrupt throttling rate. Value is calculated 3119 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3120 */ 3121 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3122 } 3123 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3124 adapter->rx_int_delay.value); 3125 3126 /* Use extended rx descriptor formats */ 3127 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3128 rfctl |= E1000_RFCTL_EXTEN; 3129 /* 3130 * When using MSIX interrupts we need to throttle 3131 * using the EITR register (82574 only) 3132 */ 3133 if (hw->mac.type == e1000_82574) { 3134 for (int i = 0; i < 4; i++) 3135 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3136 DEFAULT_ITR); 3137 /* Disable accelerated acknowledge */ 3138 rfctl |= E1000_RFCTL_ACK_DIS; 3139 } 3140 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3141 3142 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3143 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3144 adapter->hw.mac.type >= e1000_82543) { 3145 if (adapter->tx_num_queues > 1) { 3146 if (adapter->hw.mac.type >= igb_mac_min) { 3147 rxcsum |= E1000_RXCSUM_PCSD; 3148 if (hw->mac.type != e1000_82575) 3149 rxcsum |= E1000_RXCSUM_CRCOFL; 3150 } else 3151 rxcsum |= E1000_RXCSUM_TUOFL | 3152 E1000_RXCSUM_IPOFL | 3153 E1000_RXCSUM_PCSD; 3154 } else { 3155 if (adapter->hw.mac.type >= igb_mac_min) 3156 rxcsum |= E1000_RXCSUM_IPPCSE; 3157 else 3158 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3159 if (adapter->hw.mac.type > e1000_82575) 3160 rxcsum |= E1000_RXCSUM_CRCOFL; 3161 } 3162 } else 3163 rxcsum &= ~E1000_RXCSUM_TUOFL; 3164 3165 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3166 3167 if (adapter->rx_num_queues > 1) { 3168 if (adapter->hw.mac.type >= igb_mac_min) 3169 igb_initialize_rss_mapping(adapter); 3170 else 3171 em_initialize_rss_mapping(adapter); 3172 } 3173 3174 /* 3175 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3176 * long latencies are observed, like Lenovo X60. This 3177 * change eliminates the problem, but since having positive 3178 * values in RDTR is a known source of problems on other 3179 * platforms another solution is being sought. 3180 */ 3181 if (hw->mac.type == e1000_82573) 3182 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3183 3184 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3185 struct rx_ring *rxr = &que->rxr; 3186 /* Setup the Base and Length of the Rx Descriptor Ring */ 3187 u64 bus_addr = rxr->rx_paddr; 3188 #if 0 3189 u32 rdt = adapter->rx_num_queues -1; /* default */ 3190 #endif 3191 3192 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3193 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3194 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3195 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3196 /* Setup the Head and Tail Descriptor Pointers */ 3197 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3198 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3199 } 3200 3201 /* 3202 * Set PTHRESH for improved jumbo performance 3203 * According to 10.2.5.11 of Intel 82574 Datasheet, 3204 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3205 * Only write to RXDCTL(1) if there is a need for different 3206 * settings. 3207 */ 3208 3209 if (((adapter->hw.mac.type == e1000_ich9lan) || 3210 (adapter->hw.mac.type == e1000_pch2lan) || 3211 (adapter->hw.mac.type == e1000_ich10lan)) && 3212 (if_getmtu(ifp) > ETHERMTU)) { 3213 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3214 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3215 } else if (adapter->hw.mac.type == e1000_82574) { 3216 for (int i = 0; i < adapter->rx_num_queues; i++) { 3217 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3218 rxdctl |= 0x20; /* PTHRESH */ 3219 rxdctl |= 4 << 8; /* HTHRESH */ 3220 rxdctl |= 4 << 16;/* WTHRESH */ 3221 rxdctl |= 1 << 24; /* Switch to granularity */ 3222 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3223 } 3224 } else if (adapter->hw.mac.type >= igb_mac_min) { 3225 u32 psize, srrctl = 0; 3226 3227 if (if_getmtu(ifp) > ETHERMTU) { 3228 /* Set maximum packet len */ 3229 if (adapter->rx_mbuf_sz <= 4096) { 3230 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3231 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3232 } else if (adapter->rx_mbuf_sz > 4096) { 3233 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3234 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3235 } 3236 psize = scctx->isc_max_frame_size; 3237 /* are we on a vlan? */ 3238 if (ifp->if_vlantrunk != NULL) 3239 psize += VLAN_TAG_SIZE; 3240 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3241 } else { 3242 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3243 rctl |= E1000_RCTL_SZ_2048; 3244 } 3245 3246 /* 3247 * If TX flow control is disabled and there's >1 queue defined, 3248 * enable DROP. 3249 * 3250 * This drops frames rather than hanging the RX MAC for all queues. 3251 */ 3252 if ((adapter->rx_num_queues > 1) && 3253 (adapter->fc == e1000_fc_none || 3254 adapter->fc == e1000_fc_rx_pause)) { 3255 srrctl |= E1000_SRRCTL_DROP_EN; 3256 } 3257 /* Setup the Base and Length of the Rx Descriptor Rings */ 3258 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3259 struct rx_ring *rxr = &que->rxr; 3260 u64 bus_addr = rxr->rx_paddr; 3261 u32 rxdctl; 3262 3263 #ifdef notyet 3264 /* Configure for header split? -- ignore for now */ 3265 rxr->hdr_split = igb_header_split; 3266 #else 3267 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3268 #endif 3269 3270 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3271 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3272 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3273 (uint32_t)(bus_addr >> 32)); 3274 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3275 (uint32_t)bus_addr); 3276 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3277 /* Enable this Queue */ 3278 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3279 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3280 rxdctl &= 0xFFF00000; 3281 rxdctl |= IGB_RX_PTHRESH; 3282 rxdctl |= IGB_RX_HTHRESH << 8; 3283 rxdctl |= IGB_RX_WTHRESH << 16; 3284 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3285 } 3286 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3287 if (if_getmtu(ifp) > ETHERMTU) 3288 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3289 else 3290 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3291 } 3292 3293 /* Make sure VLAN Filters are off */ 3294 rctl &= ~E1000_RCTL_VFE; 3295 3296 if (adapter->hw.mac.type < igb_mac_min) { 3297 if (adapter->rx_mbuf_sz == MCLBYTES) 3298 rctl |= E1000_RCTL_SZ_2048; 3299 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3300 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3301 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3302 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3303 3304 /* ensure we clear use DTYPE of 00 here */ 3305 rctl &= ~0x00000C00; 3306 } 3307 3308 /* Write out the settings */ 3309 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3310 3311 return; 3312 } 3313 3314 static void 3315 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3316 { 3317 struct adapter *adapter = iflib_get_softc(ctx); 3318 u32 index, bit; 3319 3320 index = (vtag >> 5) & 0x7F; 3321 bit = vtag & 0x1F; 3322 adapter->shadow_vfta[index] |= (1 << bit); 3323 ++adapter->num_vlans; 3324 } 3325 3326 static void 3327 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3328 { 3329 struct adapter *adapter = iflib_get_softc(ctx); 3330 u32 index, bit; 3331 3332 index = (vtag >> 5) & 0x7F; 3333 bit = vtag & 0x1F; 3334 adapter->shadow_vfta[index] &= ~(1 << bit); 3335 --adapter->num_vlans; 3336 } 3337 3338 static void 3339 em_setup_vlan_hw_support(struct adapter *adapter) 3340 { 3341 struct e1000_hw *hw = &adapter->hw; 3342 u32 reg; 3343 3344 /* 3345 * We get here thru init_locked, meaning 3346 * a soft reset, this has already cleared 3347 * the VFTA and other state, so if there 3348 * have been no vlan's registered do nothing. 3349 */ 3350 if (adapter->num_vlans == 0) 3351 return; 3352 3353 /* 3354 * A soft reset zero's out the VFTA, so 3355 * we need to repopulate it now. 3356 */ 3357 for (int i = 0; i < EM_VFTA_SIZE; i++) 3358 if (adapter->shadow_vfta[i] != 0) 3359 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3360 i, adapter->shadow_vfta[i]); 3361 3362 reg = E1000_READ_REG(hw, E1000_CTRL); 3363 reg |= E1000_CTRL_VME; 3364 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3365 3366 /* Enable the Filter Table */ 3367 reg = E1000_READ_REG(hw, E1000_RCTL); 3368 reg &= ~E1000_RCTL_CFIEN; 3369 reg |= E1000_RCTL_VFE; 3370 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3371 } 3372 3373 static void 3374 em_if_enable_intr(if_ctx_t ctx) 3375 { 3376 struct adapter *adapter = iflib_get_softc(ctx); 3377 struct e1000_hw *hw = &adapter->hw; 3378 u32 ims_mask = IMS_ENABLE_MASK; 3379 3380 if (hw->mac.type == e1000_82574) { 3381 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3382 ims_mask |= adapter->ims; 3383 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3384 u32 mask = (adapter->que_mask | adapter->link_mask); 3385 3386 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3387 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3388 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3389 ims_mask = E1000_IMS_LSC; 3390 } 3391 3392 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3393 } 3394 3395 static void 3396 em_if_disable_intr(if_ctx_t ctx) 3397 { 3398 struct adapter *adapter = iflib_get_softc(ctx); 3399 struct e1000_hw *hw = &adapter->hw; 3400 3401 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3402 if (hw->mac.type >= igb_mac_min) 3403 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3404 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3405 } 3406 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3407 } 3408 3409 /* 3410 * Bit of a misnomer, what this really means is 3411 * to enable OS management of the system... aka 3412 * to disable special hardware management features 3413 */ 3414 static void 3415 em_init_manageability(struct adapter *adapter) 3416 { 3417 /* A shared code workaround */ 3418 #define E1000_82542_MANC2H E1000_MANC2H 3419 if (adapter->has_manage) { 3420 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3421 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3422 3423 /* disable hardware interception of ARP */ 3424 manc &= ~(E1000_MANC_ARP_EN); 3425 3426 /* enable receiving management packets to the host */ 3427 manc |= E1000_MANC_EN_MNG2HOST; 3428 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3429 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3430 manc2h |= E1000_MNG2HOST_PORT_623; 3431 manc2h |= E1000_MNG2HOST_PORT_664; 3432 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3433 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3434 } 3435 } 3436 3437 /* 3438 * Give control back to hardware management 3439 * controller if there is one. 3440 */ 3441 static void 3442 em_release_manageability(struct adapter *adapter) 3443 { 3444 if (adapter->has_manage) { 3445 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3446 3447 /* re-enable hardware interception of ARP */ 3448 manc |= E1000_MANC_ARP_EN; 3449 manc &= ~E1000_MANC_EN_MNG2HOST; 3450 3451 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3452 } 3453 } 3454 3455 /* 3456 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3457 * For ASF and Pass Through versions of f/w this means 3458 * that the driver is loaded. For AMT version type f/w 3459 * this means that the network i/f is open. 3460 */ 3461 static void 3462 em_get_hw_control(struct adapter *adapter) 3463 { 3464 u32 ctrl_ext, swsm; 3465 3466 if (adapter->vf_ifp) 3467 return; 3468 3469 if (adapter->hw.mac.type == e1000_82573) { 3470 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3471 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3472 swsm | E1000_SWSM_DRV_LOAD); 3473 return; 3474 } 3475 /* else */ 3476 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3477 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3478 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3479 } 3480 3481 /* 3482 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3483 * For ASF and Pass Through versions of f/w this means that 3484 * the driver is no longer loaded. For AMT versions of the 3485 * f/w this means that the network i/f is closed. 3486 */ 3487 static void 3488 em_release_hw_control(struct adapter *adapter) 3489 { 3490 u32 ctrl_ext, swsm; 3491 3492 if (!adapter->has_manage) 3493 return; 3494 3495 if (adapter->hw.mac.type == e1000_82573) { 3496 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3497 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3498 swsm & ~E1000_SWSM_DRV_LOAD); 3499 return; 3500 } 3501 /* else */ 3502 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3503 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3504 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3505 return; 3506 } 3507 3508 static int 3509 em_is_valid_ether_addr(u8 *addr) 3510 { 3511 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3512 3513 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3514 return (FALSE); 3515 } 3516 3517 return (TRUE); 3518 } 3519 3520 /* 3521 ** Parse the interface capabilities with regard 3522 ** to both system management and wake-on-lan for 3523 ** later use. 3524 */ 3525 static void 3526 em_get_wakeup(if_ctx_t ctx) 3527 { 3528 struct adapter *adapter = iflib_get_softc(ctx); 3529 device_t dev = iflib_get_dev(ctx); 3530 u16 eeprom_data = 0, device_id, apme_mask; 3531 3532 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3533 apme_mask = EM_EEPROM_APME; 3534 3535 switch (adapter->hw.mac.type) { 3536 case e1000_82542: 3537 case e1000_82543: 3538 break; 3539 case e1000_82544: 3540 e1000_read_nvm(&adapter->hw, 3541 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3542 apme_mask = EM_82544_APME; 3543 break; 3544 case e1000_82546: 3545 case e1000_82546_rev_3: 3546 if (adapter->hw.bus.func == 1) { 3547 e1000_read_nvm(&adapter->hw, 3548 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3549 break; 3550 } else 3551 e1000_read_nvm(&adapter->hw, 3552 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3553 break; 3554 case e1000_82573: 3555 case e1000_82583: 3556 adapter->has_amt = TRUE; 3557 /* FALLTHROUGH */ 3558 case e1000_82571: 3559 case e1000_82572: 3560 case e1000_80003es2lan: 3561 if (adapter->hw.bus.func == 1) { 3562 e1000_read_nvm(&adapter->hw, 3563 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3564 break; 3565 } else 3566 e1000_read_nvm(&adapter->hw, 3567 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3568 break; 3569 case e1000_ich8lan: 3570 case e1000_ich9lan: 3571 case e1000_ich10lan: 3572 case e1000_pchlan: 3573 case e1000_pch2lan: 3574 case e1000_pch_lpt: 3575 case e1000_pch_spt: 3576 case e1000_82575: /* listing all igb devices */ 3577 case e1000_82576: 3578 case e1000_82580: 3579 case e1000_i350: 3580 case e1000_i354: 3581 case e1000_i210: 3582 case e1000_i211: 3583 case e1000_vfadapt: 3584 case e1000_vfadapt_i350: 3585 apme_mask = E1000_WUC_APME; 3586 adapter->has_amt = TRUE; 3587 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3588 break; 3589 default: 3590 e1000_read_nvm(&adapter->hw, 3591 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3592 break; 3593 } 3594 if (eeprom_data & apme_mask) 3595 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3596 /* 3597 * We have the eeprom settings, now apply the special cases 3598 * where the eeprom may be wrong or the board won't support 3599 * wake on lan on a particular port 3600 */ 3601 device_id = pci_get_device(dev); 3602 switch (device_id) { 3603 case E1000_DEV_ID_82546GB_PCIE: 3604 adapter->wol = 0; 3605 break; 3606 case E1000_DEV_ID_82546EB_FIBER: 3607 case E1000_DEV_ID_82546GB_FIBER: 3608 /* Wake events only supported on port A for dual fiber 3609 * regardless of eeprom setting */ 3610 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3611 E1000_STATUS_FUNC_1) 3612 adapter->wol = 0; 3613 break; 3614 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3615 /* if quad port adapter, disable WoL on all but port A */ 3616 if (global_quad_port_a != 0) 3617 adapter->wol = 0; 3618 /* Reset for multiple quad port adapters */ 3619 if (++global_quad_port_a == 4) 3620 global_quad_port_a = 0; 3621 break; 3622 case E1000_DEV_ID_82571EB_FIBER: 3623 /* Wake events only supported on port A for dual fiber 3624 * regardless of eeprom setting */ 3625 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3626 E1000_STATUS_FUNC_1) 3627 adapter->wol = 0; 3628 break; 3629 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3630 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3631 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3632 /* if quad port adapter, disable WoL on all but port A */ 3633 if (global_quad_port_a != 0) 3634 adapter->wol = 0; 3635 /* Reset for multiple quad port adapters */ 3636 if (++global_quad_port_a == 4) 3637 global_quad_port_a = 0; 3638 break; 3639 } 3640 return; 3641 } 3642 3643 3644 /* 3645 * Enable PCI Wake On Lan capability 3646 */ 3647 static void 3648 em_enable_wakeup(if_ctx_t ctx) 3649 { 3650 struct adapter *adapter = iflib_get_softc(ctx); 3651 device_t dev = iflib_get_dev(ctx); 3652 if_t ifp = iflib_get_ifp(ctx); 3653 int error = 0; 3654 u32 pmc, ctrl, ctrl_ext, rctl; 3655 u16 status; 3656 3657 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3658 return; 3659 3660 /* 3661 * Determine type of Wakeup: note that wol 3662 * is set with all bits on by default. 3663 */ 3664 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3665 adapter->wol &= ~E1000_WUFC_MAG; 3666 3667 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3668 adapter->wol &= ~E1000_WUFC_EX; 3669 3670 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3671 adapter->wol &= ~E1000_WUFC_MC; 3672 else { 3673 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3674 rctl |= E1000_RCTL_MPE; 3675 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3676 } 3677 3678 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3679 goto pme; 3680 3681 /* Advertise the wakeup capability */ 3682 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3683 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3684 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3685 3686 /* Keep the laser running on Fiber adapters */ 3687 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3688 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3689 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3690 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3691 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3692 } 3693 3694 if ((adapter->hw.mac.type == e1000_ich8lan) || 3695 (adapter->hw.mac.type == e1000_pchlan) || 3696 (adapter->hw.mac.type == e1000_ich9lan) || 3697 (adapter->hw.mac.type == e1000_ich10lan)) 3698 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3699 3700 if ( adapter->hw.mac.type >= e1000_pchlan) { 3701 error = em_enable_phy_wakeup(adapter); 3702 if (error) 3703 goto pme; 3704 } else { 3705 /* Enable wakeup by the MAC */ 3706 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3707 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3708 } 3709 3710 if (adapter->hw.phy.type == e1000_phy_igp_3) 3711 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3712 3713 pme: 3714 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3715 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3716 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3717 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3718 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3719 3720 return; 3721 } 3722 3723 /* 3724 * WOL in the newer chipset interfaces (pchlan) 3725 * require thing to be copied into the phy 3726 */ 3727 static int 3728 em_enable_phy_wakeup(struct adapter *adapter) 3729 { 3730 struct e1000_hw *hw = &adapter->hw; 3731 u32 mreg, ret = 0; 3732 u16 preg; 3733 3734 /* copy MAC RARs to PHY RARs */ 3735 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3736 3737 /* copy MAC MTA to PHY MTA */ 3738 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3739 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3740 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3741 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3742 (u16)((mreg >> 16) & 0xFFFF)); 3743 } 3744 3745 /* configure PHY Rx Control register */ 3746 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3747 mreg = E1000_READ_REG(hw, E1000_RCTL); 3748 if (mreg & E1000_RCTL_UPE) 3749 preg |= BM_RCTL_UPE; 3750 if (mreg & E1000_RCTL_MPE) 3751 preg |= BM_RCTL_MPE; 3752 preg &= ~(BM_RCTL_MO_MASK); 3753 if (mreg & E1000_RCTL_MO_3) 3754 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3755 << BM_RCTL_MO_SHIFT); 3756 if (mreg & E1000_RCTL_BAM) 3757 preg |= BM_RCTL_BAM; 3758 if (mreg & E1000_RCTL_PMCF) 3759 preg |= BM_RCTL_PMCF; 3760 mreg = E1000_READ_REG(hw, E1000_CTRL); 3761 if (mreg & E1000_CTRL_RFCE) 3762 preg |= BM_RCTL_RFCE; 3763 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3764 3765 /* enable PHY wakeup in MAC register */ 3766 E1000_WRITE_REG(hw, E1000_WUC, 3767 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3768 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3769 3770 /* configure and enable PHY wakeup in PHY registers */ 3771 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3772 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3773 3774 /* activate PHY wakeup */ 3775 ret = hw->phy.ops.acquire(hw); 3776 if (ret) { 3777 printf("Could not acquire PHY\n"); 3778 return ret; 3779 } 3780 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3781 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3782 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3783 if (ret) { 3784 printf("Could not read PHY page 769\n"); 3785 goto out; 3786 } 3787 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3788 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3789 if (ret) 3790 printf("Could not set PHY Host Wakeup bit\n"); 3791 out: 3792 hw->phy.ops.release(hw); 3793 3794 return ret; 3795 } 3796 3797 static void 3798 em_if_led_func(if_ctx_t ctx, int onoff) 3799 { 3800 struct adapter *adapter = iflib_get_softc(ctx); 3801 3802 if (onoff) { 3803 e1000_setup_led(&adapter->hw); 3804 e1000_led_on(&adapter->hw); 3805 } else { 3806 e1000_led_off(&adapter->hw); 3807 e1000_cleanup_led(&adapter->hw); 3808 } 3809 } 3810 3811 /* 3812 * Disable the L0S and L1 LINK states 3813 */ 3814 static void 3815 em_disable_aspm(struct adapter *adapter) 3816 { 3817 int base, reg; 3818 u16 link_cap,link_ctrl; 3819 device_t dev = adapter->dev; 3820 3821 switch (adapter->hw.mac.type) { 3822 case e1000_82573: 3823 case e1000_82574: 3824 case e1000_82583: 3825 break; 3826 default: 3827 return; 3828 } 3829 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3830 return; 3831 reg = base + PCIER_LINK_CAP; 3832 link_cap = pci_read_config(dev, reg, 2); 3833 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3834 return; 3835 reg = base + PCIER_LINK_CTL; 3836 link_ctrl = pci_read_config(dev, reg, 2); 3837 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3838 pci_write_config(dev, reg, link_ctrl, 2); 3839 return; 3840 } 3841 3842 /********************************************************************** 3843 * 3844 * Update the board statistics counters. 3845 * 3846 **********************************************************************/ 3847 static void 3848 em_update_stats_counters(struct adapter *adapter) 3849 { 3850 3851 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3852 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3853 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3854 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3855 } 3856 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3857 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3858 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3859 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3860 3861 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3862 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3863 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3864 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3865 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3866 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3867 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3868 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3869 /* 3870 ** For watchdog management we need to know if we have been 3871 ** paused during the last interval, so capture that here. 3872 */ 3873 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3874 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3875 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3876 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3877 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3878 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3879 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3880 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3881 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3882 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3883 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3884 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3885 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3886 3887 /* For the 64-bit byte counters the low dword must be read first. */ 3888 /* Both registers clear on the read of the high dword */ 3889 3890 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3891 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3892 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3893 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3894 3895 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3896 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3897 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3898 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3899 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3900 3901 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3902 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3903 3904 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3905 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3906 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3907 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3908 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3909 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3910 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3911 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3912 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3913 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3914 3915 /* Interrupt Counts */ 3916 3917 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3918 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3919 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3920 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3921 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3922 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3923 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3924 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3925 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3926 3927 if (adapter->hw.mac.type >= e1000_82543) { 3928 adapter->stats.algnerrc += 3929 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3930 adapter->stats.rxerrc += 3931 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3932 adapter->stats.tncrs += 3933 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3934 adapter->stats.cexterr += 3935 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3936 adapter->stats.tsctc += 3937 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3938 adapter->stats.tsctfc += 3939 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3940 } 3941 } 3942 3943 static uint64_t 3944 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3945 { 3946 struct adapter *adapter = iflib_get_softc(ctx); 3947 struct ifnet *ifp = iflib_get_ifp(ctx); 3948 3949 switch (cnt) { 3950 case IFCOUNTER_COLLISIONS: 3951 return (adapter->stats.colc); 3952 case IFCOUNTER_IERRORS: 3953 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3954 adapter->stats.crcerrs + adapter->stats.algnerrc + 3955 adapter->stats.ruc + adapter->stats.roc + 3956 adapter->stats.mpc + adapter->stats.cexterr); 3957 case IFCOUNTER_OERRORS: 3958 return (adapter->stats.ecol + adapter->stats.latecol + 3959 adapter->watchdog_events); 3960 default: 3961 return (if_get_counter_default(ifp, cnt)); 3962 } 3963 } 3964 3965 /* Export a single 32-bit register via a read-only sysctl. */ 3966 static int 3967 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3968 { 3969 struct adapter *adapter; 3970 u_int val; 3971 3972 adapter = oidp->oid_arg1; 3973 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3974 return (sysctl_handle_int(oidp, &val, 0, req)); 3975 } 3976 3977 /* 3978 * Add sysctl variables, one per statistic, to the system. 3979 */ 3980 static void 3981 em_add_hw_stats(struct adapter *adapter) 3982 { 3983 device_t dev = iflib_get_dev(adapter->ctx); 3984 struct em_tx_queue *tx_que = adapter->tx_queues; 3985 struct em_rx_queue *rx_que = adapter->rx_queues; 3986 3987 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3988 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3989 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3990 struct e1000_hw_stats *stats = &adapter->stats; 3991 3992 struct sysctl_oid *stat_node, *queue_node, *int_node; 3993 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3994 3995 #define QUEUE_NAME_LEN 32 3996 char namebuf[QUEUE_NAME_LEN]; 3997 3998 /* Driver Statistics */ 3999 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4000 CTLFLAG_RD, &adapter->dropped_pkts, 4001 "Driver dropped packets"); 4002 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4003 CTLFLAG_RD, &adapter->link_irq, 4004 "Link MSIX IRQ Handled"); 4005 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4006 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4007 "Defragmenting mbuf chain failed"); 4008 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4009 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4010 "Driver tx dma failure in xmit"); 4011 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4012 CTLFLAG_RD, &adapter->rx_overruns, 4013 "RX overruns"); 4014 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4015 CTLFLAG_RD, &adapter->watchdog_events, 4016 "Watchdog timeouts"); 4017 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4018 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4019 em_sysctl_reg_handler, "IU", 4020 "Device Control Register"); 4021 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4022 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4023 em_sysctl_reg_handler, "IU", 4024 "Receiver Control Register"); 4025 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4026 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4027 "Flow Control High Watermark"); 4028 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4029 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4030 "Flow Control Low Watermark"); 4031 4032 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4033 struct tx_ring *txr = &tx_que->txr; 4034 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4035 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4036 CTLFLAG_RD, NULL, "TX Queue Name"); 4037 queue_list = SYSCTL_CHILDREN(queue_node); 4038 4039 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4040 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4041 E1000_TDH(txr->me), 4042 em_sysctl_reg_handler, "IU", 4043 "Transmit Descriptor Head"); 4044 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4045 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4046 E1000_TDT(txr->me), 4047 em_sysctl_reg_handler, "IU", 4048 "Transmit Descriptor Tail"); 4049 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4050 CTLFLAG_RD, &txr->tx_irq, 4051 "Queue MSI-X Transmit Interrupts"); 4052 } 4053 4054 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4055 struct rx_ring *rxr = &rx_que->rxr; 4056 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4057 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4058 CTLFLAG_RD, NULL, "RX Queue Name"); 4059 queue_list = SYSCTL_CHILDREN(queue_node); 4060 4061 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4062 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4063 E1000_RDH(rxr->me), 4064 em_sysctl_reg_handler, "IU", 4065 "Receive Descriptor Head"); 4066 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4067 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4068 E1000_RDT(rxr->me), 4069 em_sysctl_reg_handler, "IU", 4070 "Receive Descriptor Tail"); 4071 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4072 CTLFLAG_RD, &rxr->rx_irq, 4073 "Queue MSI-X Receive Interrupts"); 4074 } 4075 4076 /* MAC stats get their own sub node */ 4077 4078 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4079 CTLFLAG_RD, NULL, "Statistics"); 4080 stat_list = SYSCTL_CHILDREN(stat_node); 4081 4082 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4083 CTLFLAG_RD, &stats->ecol, 4084 "Excessive collisions"); 4085 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4086 CTLFLAG_RD, &stats->scc, 4087 "Single collisions"); 4088 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4089 CTLFLAG_RD, &stats->mcc, 4090 "Multiple collisions"); 4091 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4092 CTLFLAG_RD, &stats->latecol, 4093 "Late collisions"); 4094 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4095 CTLFLAG_RD, &stats->colc, 4096 "Collision Count"); 4097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4098 CTLFLAG_RD, &adapter->stats.symerrs, 4099 "Symbol Errors"); 4100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4101 CTLFLAG_RD, &adapter->stats.sec, 4102 "Sequence Errors"); 4103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4104 CTLFLAG_RD, &adapter->stats.dc, 4105 "Defer Count"); 4106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4107 CTLFLAG_RD, &adapter->stats.mpc, 4108 "Missed Packets"); 4109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4110 CTLFLAG_RD, &adapter->stats.rnbc, 4111 "Receive No Buffers"); 4112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4113 CTLFLAG_RD, &adapter->stats.ruc, 4114 "Receive Undersize"); 4115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4116 CTLFLAG_RD, &adapter->stats.rfc, 4117 "Fragmented Packets Received "); 4118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4119 CTLFLAG_RD, &adapter->stats.roc, 4120 "Oversized Packets Received"); 4121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4122 CTLFLAG_RD, &adapter->stats.rjc, 4123 "Recevied Jabber"); 4124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4125 CTLFLAG_RD, &adapter->stats.rxerrc, 4126 "Receive Errors"); 4127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4128 CTLFLAG_RD, &adapter->stats.crcerrs, 4129 "CRC errors"); 4130 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4131 CTLFLAG_RD, &adapter->stats.algnerrc, 4132 "Alignment Errors"); 4133 /* On 82575 these are collision counts */ 4134 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4135 CTLFLAG_RD, &adapter->stats.cexterr, 4136 "Collision/Carrier extension errors"); 4137 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4138 CTLFLAG_RD, &adapter->stats.xonrxc, 4139 "XON Received"); 4140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4141 CTLFLAG_RD, &adapter->stats.xontxc, 4142 "XON Transmitted"); 4143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4144 CTLFLAG_RD, &adapter->stats.xoffrxc, 4145 "XOFF Received"); 4146 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4147 CTLFLAG_RD, &adapter->stats.xofftxc, 4148 "XOFF Transmitted"); 4149 4150 /* Packet Reception Stats */ 4151 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4152 CTLFLAG_RD, &adapter->stats.tpr, 4153 "Total Packets Received "); 4154 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4155 CTLFLAG_RD, &adapter->stats.gprc, 4156 "Good Packets Received"); 4157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4158 CTLFLAG_RD, &adapter->stats.bprc, 4159 "Broadcast Packets Received"); 4160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4161 CTLFLAG_RD, &adapter->stats.mprc, 4162 "Multicast Packets Received"); 4163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4164 CTLFLAG_RD, &adapter->stats.prc64, 4165 "64 byte frames received "); 4166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4167 CTLFLAG_RD, &adapter->stats.prc127, 4168 "65-127 byte frames received"); 4169 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4170 CTLFLAG_RD, &adapter->stats.prc255, 4171 "128-255 byte frames received"); 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4173 CTLFLAG_RD, &adapter->stats.prc511, 4174 "256-511 byte frames received"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4176 CTLFLAG_RD, &adapter->stats.prc1023, 4177 "512-1023 byte frames received"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4179 CTLFLAG_RD, &adapter->stats.prc1522, 4180 "1023-1522 byte frames received"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4182 CTLFLAG_RD, &adapter->stats.gorc, 4183 "Good Octets Received"); 4184 4185 /* Packet Transmission Stats */ 4186 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4187 CTLFLAG_RD, &adapter->stats.gotc, 4188 "Good Octets Transmitted"); 4189 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4190 CTLFLAG_RD, &adapter->stats.tpt, 4191 "Total Packets Transmitted"); 4192 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4193 CTLFLAG_RD, &adapter->stats.gptc, 4194 "Good Packets Transmitted"); 4195 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4196 CTLFLAG_RD, &adapter->stats.bptc, 4197 "Broadcast Packets Transmitted"); 4198 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4199 CTLFLAG_RD, &adapter->stats.mptc, 4200 "Multicast Packets Transmitted"); 4201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4202 CTLFLAG_RD, &adapter->stats.ptc64, 4203 "64 byte frames transmitted "); 4204 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4205 CTLFLAG_RD, &adapter->stats.ptc127, 4206 "65-127 byte frames transmitted"); 4207 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4208 CTLFLAG_RD, &adapter->stats.ptc255, 4209 "128-255 byte frames transmitted"); 4210 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4211 CTLFLAG_RD, &adapter->stats.ptc511, 4212 "256-511 byte frames transmitted"); 4213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4214 CTLFLAG_RD, &adapter->stats.ptc1023, 4215 "512-1023 byte frames transmitted"); 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4217 CTLFLAG_RD, &adapter->stats.ptc1522, 4218 "1024-1522 byte frames transmitted"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4220 CTLFLAG_RD, &adapter->stats.tsctc, 4221 "TSO Contexts Transmitted"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4223 CTLFLAG_RD, &adapter->stats.tsctfc, 4224 "TSO Contexts Failed"); 4225 4226 4227 /* Interrupt Stats */ 4228 4229 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4230 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4231 int_list = SYSCTL_CHILDREN(int_node); 4232 4233 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4234 CTLFLAG_RD, &adapter->stats.iac, 4235 "Interrupt Assertion Count"); 4236 4237 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4238 CTLFLAG_RD, &adapter->stats.icrxptc, 4239 "Interrupt Cause Rx Pkt Timer Expire Count"); 4240 4241 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4242 CTLFLAG_RD, &adapter->stats.icrxatc, 4243 "Interrupt Cause Rx Abs Timer Expire Count"); 4244 4245 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4246 CTLFLAG_RD, &adapter->stats.ictxptc, 4247 "Interrupt Cause Tx Pkt Timer Expire Count"); 4248 4249 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4250 CTLFLAG_RD, &adapter->stats.ictxatc, 4251 "Interrupt Cause Tx Abs Timer Expire Count"); 4252 4253 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4254 CTLFLAG_RD, &adapter->stats.ictxqec, 4255 "Interrupt Cause Tx Queue Empty Count"); 4256 4257 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4258 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4259 "Interrupt Cause Tx Queue Min Thresh Count"); 4260 4261 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4262 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4263 "Interrupt Cause Rx Desc Min Thresh Count"); 4264 4265 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4266 CTLFLAG_RD, &adapter->stats.icrxoc, 4267 "Interrupt Cause Receiver Overrun Count"); 4268 } 4269 4270 /********************************************************************** 4271 * 4272 * This routine provides a way to dump out the adapter eeprom, 4273 * often a useful debug/service tool. This only dumps the first 4274 * 32 words, stuff that matters is in that extent. 4275 * 4276 **********************************************************************/ 4277 static int 4278 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4279 { 4280 struct adapter *adapter = (struct adapter *)arg1; 4281 int error; 4282 int result; 4283 4284 result = -1; 4285 error = sysctl_handle_int(oidp, &result, 0, req); 4286 4287 if (error || !req->newptr) 4288 return (error); 4289 4290 /* 4291 * This value will cause a hex dump of the 4292 * first 32 16-bit words of the EEPROM to 4293 * the screen. 4294 */ 4295 if (result == 1) 4296 em_print_nvm_info(adapter); 4297 4298 return (error); 4299 } 4300 4301 static void 4302 em_print_nvm_info(struct adapter *adapter) 4303 { 4304 u16 eeprom_data; 4305 int i, j, row = 0; 4306 4307 /* Its a bit crude, but it gets the job done */ 4308 printf("\nInterface EEPROM Dump:\n"); 4309 printf("Offset\n0x0000 "); 4310 for (i = 0, j = 0; i < 32; i++, j++) { 4311 if (j == 8) { /* Make the offset block */ 4312 j = 0; ++row; 4313 printf("\n0x00%x0 ",row); 4314 } 4315 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4316 printf("%04x ", eeprom_data); 4317 } 4318 printf("\n"); 4319 } 4320 4321 static int 4322 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4323 { 4324 struct em_int_delay_info *info; 4325 struct adapter *adapter; 4326 u32 regval; 4327 int error, usecs, ticks; 4328 4329 info = (struct em_int_delay_info *) arg1; 4330 usecs = info->value; 4331 error = sysctl_handle_int(oidp, &usecs, 0, req); 4332 if (error != 0 || req->newptr == NULL) 4333 return (error); 4334 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4335 return (EINVAL); 4336 info->value = usecs; 4337 ticks = EM_USECS_TO_TICKS(usecs); 4338 if (info->offset == E1000_ITR) /* units are 256ns here */ 4339 ticks *= 4; 4340 4341 adapter = info->adapter; 4342 4343 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4344 regval = (regval & ~0xffff) | (ticks & 0xffff); 4345 /* Handle a few special cases. */ 4346 switch (info->offset) { 4347 case E1000_RDTR: 4348 break; 4349 case E1000_TIDV: 4350 if (ticks == 0) { 4351 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4352 /* Don't write 0 into the TIDV register. */ 4353 regval++; 4354 } else 4355 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4356 break; 4357 } 4358 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4359 return (0); 4360 } 4361 4362 static void 4363 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4364 const char *description, struct em_int_delay_info *info, 4365 int offset, int value) 4366 { 4367 info->adapter = adapter; 4368 info->offset = offset; 4369 info->value = value; 4370 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4371 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4372 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4373 info, 0, em_sysctl_int_delay, "I", description); 4374 } 4375 4376 /* 4377 * Set flow control using sysctl: 4378 * Flow control values: 4379 * 0 - off 4380 * 1 - rx pause 4381 * 2 - tx pause 4382 * 3 - full 4383 */ 4384 static int 4385 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4386 { 4387 int error; 4388 static int input = 3; /* default is full */ 4389 struct adapter *adapter = (struct adapter *) arg1; 4390 4391 error = sysctl_handle_int(oidp, &input, 0, req); 4392 4393 if ((error) || (req->newptr == NULL)) 4394 return (error); 4395 4396 if (input == adapter->fc) /* no change? */ 4397 return (error); 4398 4399 switch (input) { 4400 case e1000_fc_rx_pause: 4401 case e1000_fc_tx_pause: 4402 case e1000_fc_full: 4403 case e1000_fc_none: 4404 adapter->hw.fc.requested_mode = input; 4405 adapter->fc = input; 4406 break; 4407 default: 4408 /* Do nothing */ 4409 return (error); 4410 } 4411 4412 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4413 e1000_force_mac_fc(&adapter->hw); 4414 return (error); 4415 } 4416 4417 /* 4418 * Manage Energy Efficient Ethernet: 4419 * Control values: 4420 * 0/1 - enabled/disabled 4421 */ 4422 static int 4423 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4424 { 4425 struct adapter *adapter = (struct adapter *) arg1; 4426 int error, value; 4427 4428 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4429 error = sysctl_handle_int(oidp, &value, 0, req); 4430 if (error || req->newptr == NULL) 4431 return (error); 4432 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4433 em_if_init(adapter->ctx); 4434 4435 return (0); 4436 } 4437 4438 static int 4439 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4440 { 4441 struct adapter *adapter; 4442 int error; 4443 int result; 4444 4445 result = -1; 4446 error = sysctl_handle_int(oidp, &result, 0, req); 4447 4448 if (error || !req->newptr) 4449 return (error); 4450 4451 if (result == 1) { 4452 adapter = (struct adapter *) arg1; 4453 em_print_debug_info(adapter); 4454 } 4455 4456 return (error); 4457 } 4458 4459 static int 4460 em_get_rs(SYSCTL_HANDLER_ARGS) 4461 { 4462 struct adapter *adapter = (struct adapter *) arg1; 4463 int error; 4464 int result; 4465 4466 result = 0; 4467 error = sysctl_handle_int(oidp, &result, 0, req); 4468 4469 if (error || !req->newptr || result != 1) 4470 return (error); 4471 em_dump_rs(adapter); 4472 4473 return (error); 4474 } 4475 4476 static void 4477 em_if_debug(if_ctx_t ctx) 4478 { 4479 em_dump_rs(iflib_get_softc(ctx)); 4480 } 4481 4482 /* 4483 * This routine is meant to be fluid, add whatever is 4484 * needed for debugging a problem. -jfv 4485 */ 4486 static void 4487 em_print_debug_info(struct adapter *adapter) 4488 { 4489 device_t dev = iflib_get_dev(adapter->ctx); 4490 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4491 struct tx_ring *txr = &adapter->tx_queues->txr; 4492 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4493 4494 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4495 printf("Interface is RUNNING "); 4496 else 4497 printf("Interface is NOT RUNNING\n"); 4498 4499 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4500 printf("and INACTIVE\n"); 4501 else 4502 printf("and ACTIVE\n"); 4503 4504 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4505 device_printf(dev, "TX Queue %d ------\n", i); 4506 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4507 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4508 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4509 4510 } 4511 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4512 device_printf(dev, "RX Queue %d ------\n", j); 4513 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4514 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4515 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4516 } 4517 } 4518 4519 /* 4520 * 82574 only: 4521 * Write a new value to the EEPROM increasing the number of MSIX 4522 * vectors from 3 to 5, for proper multiqueue support. 4523 */ 4524 static void 4525 em_enable_vectors_82574(if_ctx_t ctx) 4526 { 4527 struct adapter *adapter = iflib_get_softc(ctx); 4528 struct e1000_hw *hw = &adapter->hw; 4529 device_t dev = iflib_get_dev(ctx); 4530 u16 edata; 4531 4532 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4533 printf("Current cap: %#06x\n", edata); 4534 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4535 device_printf(dev, "Writing to eeprom: increasing " 4536 "reported MSIX vectors from 3 to 5...\n"); 4537 edata &= ~(EM_NVM_MSIX_N_MASK); 4538 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4539 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4540 e1000_update_nvm_checksum(hw); 4541 device_printf(dev, "Writing to eeprom: done\n"); 4542 } 4543 } 4544