1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static bool em_automask_tso(if_ctx_t); 334 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 335 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 336 const char *, struct em_int_delay_info *, int, int); 337 /* Management and WOL Support */ 338 static void em_init_manageability(struct e1000_softc *); 339 static void em_release_manageability(struct e1000_softc *); 340 static void em_get_hw_control(struct e1000_softc *); 341 static void em_release_hw_control(struct e1000_softc *); 342 static void em_get_wakeup(if_ctx_t); 343 static void em_enable_wakeup(if_ctx_t); 344 static int em_enable_phy_wakeup(struct e1000_softc *); 345 static void em_disable_aspm(struct e1000_softc *); 346 347 int em_intr(void *); 348 349 /* MSI-X handlers */ 350 static int em_if_msix_intr_assign(if_ctx_t, int); 351 static int em_msix_link(void *); 352 static void em_handle_link(void *); 353 354 static void em_enable_vectors_82574(if_ctx_t); 355 356 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 357 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 358 static void em_if_led_func(if_ctx_t, int); 359 360 static int em_get_regs(SYSCTL_HANDLER_ARGS); 361 362 static void lem_smartspeed(struct e1000_softc *); 363 static void igb_configure_queues(struct e1000_softc *); 364 static void em_flush_desc_rings(struct e1000_softc *); 365 366 367 /********************************************************************* 368 * FreeBSD Device Interface Entry Points 369 *********************************************************************/ 370 static device_method_t em_methods[] = { 371 /* Device interface */ 372 DEVMETHOD(device_register, em_register), 373 DEVMETHOD(device_probe, iflib_device_probe), 374 DEVMETHOD(device_attach, iflib_device_attach), 375 DEVMETHOD(device_detach, iflib_device_detach), 376 DEVMETHOD(device_shutdown, iflib_device_shutdown), 377 DEVMETHOD(device_suspend, iflib_device_suspend), 378 DEVMETHOD(device_resume, iflib_device_resume), 379 DEVMETHOD_END 380 }; 381 382 static device_method_t igb_methods[] = { 383 /* Device interface */ 384 DEVMETHOD(device_register, igb_register), 385 DEVMETHOD(device_probe, iflib_device_probe), 386 DEVMETHOD(device_attach, iflib_device_attach), 387 DEVMETHOD(device_detach, iflib_device_detach), 388 DEVMETHOD(device_shutdown, iflib_device_shutdown), 389 DEVMETHOD(device_suspend, iflib_device_suspend), 390 DEVMETHOD(device_resume, iflib_device_resume), 391 DEVMETHOD_END 392 }; 393 394 395 static driver_t em_driver = { 396 "em", em_methods, sizeof(struct e1000_softc), 397 }; 398 399 DRIVER_MODULE(em, pci, em_driver, 0, 0); 400 401 MODULE_DEPEND(em, pci, 1, 1, 1); 402 MODULE_DEPEND(em, ether, 1, 1, 1); 403 MODULE_DEPEND(em, iflib, 1, 1, 1); 404 405 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 406 407 static driver_t igb_driver = { 408 "igb", igb_methods, sizeof(struct e1000_softc), 409 }; 410 411 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 412 413 MODULE_DEPEND(igb, pci, 1, 1, 1); 414 MODULE_DEPEND(igb, ether, 1, 1, 1); 415 MODULE_DEPEND(igb, iflib, 1, 1, 1); 416 417 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 418 419 static device_method_t em_if_methods[] = { 420 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 421 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 422 DEVMETHOD(ifdi_detach, em_if_detach), 423 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 424 DEVMETHOD(ifdi_suspend, em_if_suspend), 425 DEVMETHOD(ifdi_resume, em_if_resume), 426 DEVMETHOD(ifdi_init, em_if_init), 427 DEVMETHOD(ifdi_stop, em_if_stop), 428 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 429 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 430 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 431 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 432 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 433 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 434 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 435 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 436 DEVMETHOD(ifdi_media_status, em_if_media_status), 437 DEVMETHOD(ifdi_media_change, em_if_media_change), 438 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 439 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 440 DEVMETHOD(ifdi_timer, em_if_timer), 441 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 442 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 443 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 444 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 445 DEVMETHOD(ifdi_led_func, em_if_led_func), 446 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 447 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 448 DEVMETHOD(ifdi_debug, em_if_debug), 449 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 450 DEVMETHOD_END 451 }; 452 453 static driver_t em_if_driver = { 454 "em_if", em_if_methods, sizeof(struct e1000_softc) 455 }; 456 457 static device_method_t igb_if_methods[] = { 458 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 459 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 460 DEVMETHOD(ifdi_detach, em_if_detach), 461 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 462 DEVMETHOD(ifdi_suspend, em_if_suspend), 463 DEVMETHOD(ifdi_resume, em_if_resume), 464 DEVMETHOD(ifdi_init, em_if_init), 465 DEVMETHOD(ifdi_stop, em_if_stop), 466 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 467 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 468 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 469 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 470 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 471 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 472 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 473 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 474 DEVMETHOD(ifdi_media_status, em_if_media_status), 475 DEVMETHOD(ifdi_media_change, em_if_media_change), 476 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 477 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 478 DEVMETHOD(ifdi_timer, em_if_timer), 479 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 480 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 481 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 482 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 483 DEVMETHOD(ifdi_led_func, em_if_led_func), 484 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 485 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 486 DEVMETHOD(ifdi_debug, em_if_debug), 487 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 488 DEVMETHOD_END 489 }; 490 491 static driver_t igb_if_driver = { 492 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 493 }; 494 495 /********************************************************************* 496 * Tunable default values. 497 *********************************************************************/ 498 499 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 500 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 501 502 #define MAX_INTS_PER_SEC 8000 503 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 504 505 /* Allow common code without TSO */ 506 #ifndef CSUM_TSO 507 #define CSUM_TSO 0 508 #endif 509 510 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 511 "EM driver parameters"); 512 513 static int em_disable_crc_stripping = 0; 514 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 515 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 516 517 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 518 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 519 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 520 0, "Default transmit interrupt delay in usecs"); 521 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 522 0, "Default receive interrupt delay in usecs"); 523 524 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 525 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 526 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 527 &em_tx_abs_int_delay_dflt, 0, 528 "Default transmit interrupt delay limit in usecs"); 529 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 530 &em_rx_abs_int_delay_dflt, 0, 531 "Default receive interrupt delay limit in usecs"); 532 533 static int em_smart_pwr_down = false; 534 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 535 0, "Set to true to leave smart power down enabled on newer adapters"); 536 537 static bool em_unsupported_tso = false; 538 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 539 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 540 541 /* Controls whether promiscuous also shows bad packets */ 542 static int em_debug_sbp = false; 543 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 544 "Show bad packets in promiscuous mode"); 545 546 /* How many packets rxeof tries to clean at a time */ 547 static int em_rx_process_limit = 100; 548 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 549 &em_rx_process_limit, 0, 550 "Maximum number of received packets to process " 551 "at a time, -1 means unlimited"); 552 553 /* Energy efficient ethernet - default to OFF */ 554 static int eee_setting = 1; 555 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 556 "Enable Energy Efficient Ethernet"); 557 558 /* 559 ** Tuneable Interrupt rate 560 */ 561 static int em_max_interrupt_rate = 8000; 562 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 563 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 564 565 566 567 /* Global used in WOL setup with multiport cards */ 568 static int global_quad_port_a = 0; 569 570 extern struct if_txrx igb_txrx; 571 extern struct if_txrx em_txrx; 572 extern struct if_txrx lem_txrx; 573 574 static struct if_shared_ctx em_sctx_init = { 575 .isc_magic = IFLIB_MAGIC, 576 .isc_q_align = PAGE_SIZE, 577 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 578 .isc_tx_maxsegsize = PAGE_SIZE, 579 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 580 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 581 .isc_rx_maxsize = MJUM9BYTES, 582 .isc_rx_nsegments = 1, 583 .isc_rx_maxsegsize = MJUM9BYTES, 584 .isc_nfl = 1, 585 .isc_nrxqs = 1, 586 .isc_ntxqs = 1, 587 .isc_admin_intrcnt = 1, 588 .isc_vendor_info = em_vendor_info_array, 589 .isc_driver_version = em_driver_version, 590 .isc_driver = &em_if_driver, 591 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 592 593 .isc_nrxd_min = {EM_MIN_RXD}, 594 .isc_ntxd_min = {EM_MIN_TXD}, 595 .isc_nrxd_max = {EM_MAX_RXD}, 596 .isc_ntxd_max = {EM_MAX_TXD}, 597 .isc_nrxd_default = {EM_DEFAULT_RXD}, 598 .isc_ntxd_default = {EM_DEFAULT_TXD}, 599 }; 600 601 static struct if_shared_ctx igb_sctx_init = { 602 .isc_magic = IFLIB_MAGIC, 603 .isc_q_align = PAGE_SIZE, 604 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 605 .isc_tx_maxsegsize = PAGE_SIZE, 606 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 607 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 608 .isc_rx_maxsize = MJUM9BYTES, 609 .isc_rx_nsegments = 1, 610 .isc_rx_maxsegsize = MJUM9BYTES, 611 .isc_nfl = 1, 612 .isc_nrxqs = 1, 613 .isc_ntxqs = 1, 614 .isc_admin_intrcnt = 1, 615 .isc_vendor_info = igb_vendor_info_array, 616 .isc_driver_version = igb_driver_version, 617 .isc_driver = &igb_if_driver, 618 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 619 620 .isc_nrxd_min = {EM_MIN_RXD}, 621 .isc_ntxd_min = {EM_MIN_TXD}, 622 .isc_nrxd_max = {IGB_MAX_RXD}, 623 .isc_ntxd_max = {IGB_MAX_TXD}, 624 .isc_nrxd_default = {EM_DEFAULT_RXD}, 625 .isc_ntxd_default = {EM_DEFAULT_TXD}, 626 }; 627 628 /***************************************************************** 629 * 630 * Dump Registers 631 * 632 ****************************************************************/ 633 #define IGB_REGS_LEN 739 634 635 static int em_get_regs(SYSCTL_HANDLER_ARGS) 636 { 637 struct e1000_softc *sc = (struct e1000_softc *)arg1; 638 struct e1000_hw *hw = &sc->hw; 639 struct sbuf *sb; 640 u32 *regs_buff; 641 int rc; 642 643 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 644 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 645 646 rc = sysctl_wire_old_buffer(req, 0); 647 MPASS(rc == 0); 648 if (rc != 0) { 649 free(regs_buff, M_DEVBUF); 650 return (rc); 651 } 652 653 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 654 MPASS(sb != NULL); 655 if (sb == NULL) { 656 free(regs_buff, M_DEVBUF); 657 return (ENOMEM); 658 } 659 660 /* General Registers */ 661 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 662 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 663 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 664 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 665 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 666 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 667 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 668 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 669 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 670 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 671 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 672 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 673 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 674 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 675 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 676 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 677 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 678 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 679 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 680 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 681 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 682 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 683 684 sbuf_printf(sb, "General Registers\n"); 685 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 686 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 687 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 688 689 sbuf_printf(sb, "Interrupt Registers\n"); 690 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 691 692 sbuf_printf(sb, "RX Registers\n"); 693 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 694 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 695 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 696 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 697 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 698 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 699 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 700 701 sbuf_printf(sb, "TX Registers\n"); 702 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 703 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 704 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 705 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 706 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 707 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 708 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 709 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 710 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 711 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 712 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 713 714 free(regs_buff, M_DEVBUF); 715 716 #ifdef DUMP_DESCS 717 { 718 if_softc_ctx_t scctx = sc->shared; 719 struct rx_ring *rxr = &rx_que->rxr; 720 struct tx_ring *txr = &tx_que->txr; 721 int ntxd = scctx->isc_ntxd[0]; 722 int nrxd = scctx->isc_nrxd[0]; 723 int j; 724 725 for (j = 0; j < nrxd; j++) { 726 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 727 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 728 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 729 } 730 731 for (j = 0; j < min(ntxd, 256); j++) { 732 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 733 734 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 735 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 736 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 737 738 } 739 } 740 #endif 741 742 rc = sbuf_finish(sb); 743 sbuf_delete(sb); 744 return(rc); 745 } 746 747 static void * 748 em_register(device_t dev) 749 { 750 return (&em_sctx_init); 751 } 752 753 static void * 754 igb_register(device_t dev) 755 { 756 return (&igb_sctx_init); 757 } 758 759 static int 760 em_set_num_queues(if_ctx_t ctx) 761 { 762 struct e1000_softc *sc = iflib_get_softc(ctx); 763 int maxqueues; 764 765 /* Sanity check based on HW */ 766 switch (sc->hw.mac.type) { 767 case e1000_82576: 768 case e1000_82580: 769 case e1000_i350: 770 case e1000_i354: 771 maxqueues = 8; 772 break; 773 case e1000_i210: 774 case e1000_82575: 775 maxqueues = 4; 776 break; 777 case e1000_i211: 778 case e1000_82574: 779 maxqueues = 2; 780 break; 781 default: 782 maxqueues = 1; 783 break; 784 } 785 786 return (maxqueues); 787 } 788 789 #define LEM_CAPS \ 790 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 791 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 792 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 793 794 #define EM_CAPS \ 795 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 796 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 797 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 798 IFCAP_TSO6 799 800 #define IGB_CAPS \ 801 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 802 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 803 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 804 IFCAP_TSO6 805 806 /********************************************************************* 807 * Device initialization routine 808 * 809 * The attach entry point is called when the driver is being loaded. 810 * This routine identifies the type of hardware, allocates all resources 811 * and initializes the hardware. 812 * 813 * return 0 on success, positive on failure 814 *********************************************************************/ 815 static int 816 em_if_attach_pre(if_ctx_t ctx) 817 { 818 struct e1000_softc *sc; 819 if_softc_ctx_t scctx; 820 device_t dev; 821 struct e1000_hw *hw; 822 struct sysctl_oid_list *child; 823 struct sysctl_ctx_list *ctx_list; 824 int error = 0; 825 826 INIT_DEBUGOUT("em_if_attach_pre: begin"); 827 dev = iflib_get_dev(ctx); 828 sc = iflib_get_softc(ctx); 829 830 sc->ctx = sc->osdep.ctx = ctx; 831 sc->dev = sc->osdep.dev = dev; 832 scctx = sc->shared = iflib_get_softc_ctx(ctx); 833 sc->media = iflib_get_media(ctx); 834 hw = &sc->hw; 835 836 sc->tx_process_limit = scctx->isc_ntxd[0]; 837 838 /* Determine hardware and mac info */ 839 em_identify_hardware(ctx); 840 841 /* SYSCTL stuff */ 842 ctx_list = device_get_sysctl_ctx(dev); 843 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 844 845 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 846 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 847 em_sysctl_nvm_info, "I", "NVM Information"); 848 849 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 850 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 851 em_sysctl_print_fw_version, "A", 852 "Prints FW/NVM Versions"); 853 854 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 855 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 856 em_sysctl_debug_info, "I", "Debug Information"); 857 858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 859 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 860 em_set_flowcntl, "I", "Flow Control"); 861 862 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 863 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 864 em_get_regs, "A", "Dump Registers"); 865 866 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 867 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 868 em_get_rs, "I", "Dump RS indexes"); 869 870 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 871 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 872 if (bootverbose) 873 device_printf(dev, "attach_pre capping queues at %d\n", 874 scctx->isc_ntxqsets_max); 875 876 if (hw->mac.type >= igb_mac_min) { 877 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 878 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 879 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 880 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 881 scctx->isc_txrx = &igb_txrx; 882 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 883 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 884 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 885 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 886 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 887 CSUM_IP6_TCP | CSUM_IP6_UDP; 888 if (hw->mac.type != e1000_82575) 889 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 890 /* 891 ** Some new devices, as with ixgbe, now may 892 ** use a different BAR, so we need to keep 893 ** track of which is used. 894 */ 895 scctx->isc_msix_bar = pci_msix_table_bar(dev); 896 } else if (hw->mac.type >= em_mac_min) { 897 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 898 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 899 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 900 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 901 scctx->isc_txrx = &em_txrx; 902 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 903 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 904 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 905 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 906 /* 907 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO,TSO6} 908 * by default as we don't have workarounds for all associated 909 * silicon errata. E. g., with several MACs such as 82573E, 910 * TSO only works at Gigabit speed and otherwise can cause the 911 * hardware to hang (which also would be next to impossible to 912 * work around given that already queued TSO-using descriptors 913 * would need to be flushed and vlan(4) reconfigured at runtime 914 * in case of a link speed change). Moreover, MACs like 82579 915 * still can hang at Gigabit even with all publicly documented 916 * TSO workarounds implemented. Generally, the penality of 917 * these workarounds is rather high and may involve copying 918 * mbuf data around so advantages of TSO lapse. Still, TSO may 919 * work for a few MACs of this class - at least when sticking 920 * with Gigabit - in which case users may enable TSO manually. 921 */ 922 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO | IFCAP_TSO6); 923 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 924 CSUM_IP6_TCP | CSUM_IP6_UDP; 925 /* 926 * We support MSI-X with 82574 only, but indicate to iflib(4) 927 * that it shall give MSI at least a try with other devices. 928 */ 929 if (hw->mac.type == e1000_82574) { 930 scctx->isc_msix_bar = pci_msix_table_bar(dev); 931 } else { 932 scctx->isc_msix_bar = -1; 933 scctx->isc_disable_msix = 1; 934 } 935 } else { 936 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 937 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 938 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 939 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 940 scctx->isc_txrx = &lem_txrx; 941 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 942 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 943 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 944 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 945 if (em_unsupported_tso) 946 scctx->isc_capabilities |= IFCAP_TSO6; 947 /* 948 * For LEM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 949 * by default as we don't have workarounds for all associated 950 * silicon errata. TSO4 may work on > 82544 but its status 951 * is unknown by the authors. Please report any success or failures. 952 */ 953 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 954 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 955 CSUM_IP6_TCP | CSUM_IP6_UDP; 956 957 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 958 if (hw->mac.type == e1000_82542 || hw->mac.type == e1000_82547 || 959 hw->mac.type == e1000_82547_rev_2) 960 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 961 IFCAP_HWCSUM_IPV6); 962 /* 82541ER doesn't do HW tagging */ 963 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 964 scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING; 965 /* INTx only */ 966 scctx->isc_msix_bar = 0; 967 } 968 969 /* Setup PCI resources */ 970 if (em_allocate_pci_resources(ctx)) { 971 device_printf(dev, "Allocation of PCI resources failed\n"); 972 error = ENXIO; 973 goto err_pci; 974 } 975 976 /* 977 ** For ICH8 and family we need to 978 ** map the flash memory, and this 979 ** must happen after the MAC is 980 ** identified 981 */ 982 if ((hw->mac.type == e1000_ich8lan) || 983 (hw->mac.type == e1000_ich9lan) || 984 (hw->mac.type == e1000_ich10lan) || 985 (hw->mac.type == e1000_pchlan) || 986 (hw->mac.type == e1000_pch2lan) || 987 (hw->mac.type == e1000_pch_lpt)) { 988 int rid = EM_BAR_TYPE_FLASH; 989 sc->flash = bus_alloc_resource_any(dev, 990 SYS_RES_MEMORY, &rid, RF_ACTIVE); 991 if (sc->flash == NULL) { 992 device_printf(dev, "Mapping of Flash failed\n"); 993 error = ENXIO; 994 goto err_pci; 995 } 996 /* This is used in the shared code */ 997 hw->flash_address = (u8 *)sc->flash; 998 sc->osdep.flash_bus_space_tag = 999 rman_get_bustag(sc->flash); 1000 sc->osdep.flash_bus_space_handle = 1001 rman_get_bushandle(sc->flash); 1002 } 1003 /* 1004 ** In the new SPT device flash is not a 1005 ** separate BAR, rather it is also in BAR0, 1006 ** so use the same tag and an offset handle for the 1007 ** FLASH read/write macros in the shared code. 1008 */ 1009 else if (hw->mac.type >= e1000_pch_spt) { 1010 sc->osdep.flash_bus_space_tag = 1011 sc->osdep.mem_bus_space_tag; 1012 sc->osdep.flash_bus_space_handle = 1013 sc->osdep.mem_bus_space_handle 1014 + E1000_FLASH_BASE_ADDR; 1015 } 1016 1017 /* Do Shared Code initialization */ 1018 error = e1000_setup_init_funcs(hw, true); 1019 if (error) { 1020 device_printf(dev, "Setup of Shared code failed, error %d\n", 1021 error); 1022 error = ENXIO; 1023 goto err_pci; 1024 } 1025 1026 em_setup_msix(ctx); 1027 e1000_get_bus_info(hw); 1028 1029 /* Set up some sysctls for the tunable interrupt delays */ 1030 em_add_int_delay_sysctl(sc, "rx_int_delay", 1031 "receive interrupt delay in usecs", &sc->rx_int_delay, 1032 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1033 em_add_int_delay_sysctl(sc, "tx_int_delay", 1034 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1035 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1036 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1037 "receive interrupt delay limit in usecs", 1038 &sc->rx_abs_int_delay, 1039 E1000_REGISTER(hw, E1000_RADV), 1040 em_rx_abs_int_delay_dflt); 1041 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1042 "transmit interrupt delay limit in usecs", 1043 &sc->tx_abs_int_delay, 1044 E1000_REGISTER(hw, E1000_TADV), 1045 em_tx_abs_int_delay_dflt); 1046 em_add_int_delay_sysctl(sc, "itr", 1047 "interrupt delay limit in usecs/4", 1048 &sc->tx_itr, 1049 E1000_REGISTER(hw, E1000_ITR), 1050 DEFAULT_ITR); 1051 1052 hw->mac.autoneg = DO_AUTO_NEG; 1053 hw->phy.autoneg_wait_to_complete = false; 1054 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1055 1056 if (hw->mac.type < em_mac_min) { 1057 e1000_init_script_state_82541(hw, true); 1058 e1000_set_tbi_compatibility_82543(hw, true); 1059 } 1060 /* Copper options */ 1061 if (hw->phy.media_type == e1000_media_type_copper) { 1062 hw->phy.mdix = AUTO_ALL_MODES; 1063 hw->phy.disable_polarity_correction = false; 1064 hw->phy.ms_type = EM_MASTER_SLAVE; 1065 } 1066 1067 /* 1068 * Set the frame limits assuming 1069 * standard ethernet sized frames. 1070 */ 1071 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1072 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1073 1074 /* 1075 * This controls when hardware reports transmit completion 1076 * status. 1077 */ 1078 hw->mac.report_tx_early = 1; 1079 1080 /* Allocate multicast array memory. */ 1081 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1082 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1083 if (sc->mta == NULL) { 1084 device_printf(dev, "Can not allocate multicast setup array\n"); 1085 error = ENOMEM; 1086 goto err_late; 1087 } 1088 1089 /* Clear the IFCAP_TSO auto mask */ 1090 sc->tso_automasked = 0; 1091 1092 /* Check SOL/IDER usage */ 1093 if (e1000_check_reset_block(hw)) 1094 device_printf(dev, "PHY reset is blocked" 1095 " due to SOL/IDER session.\n"); 1096 1097 /* Sysctl for setting Energy Efficient Ethernet */ 1098 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1099 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1100 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1101 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1102 1103 /* 1104 ** Start from a known state, this is 1105 ** important in reading the nvm and 1106 ** mac from that. 1107 */ 1108 e1000_reset_hw(hw); 1109 1110 /* Make sure we have a good EEPROM before we read from it */ 1111 if (e1000_validate_nvm_checksum(hw) < 0) { 1112 /* 1113 ** Some PCI-E parts fail the first check due to 1114 ** the link being in sleep state, call it again, 1115 ** if it fails a second time its a real issue. 1116 */ 1117 if (e1000_validate_nvm_checksum(hw) < 0) { 1118 device_printf(dev, 1119 "The EEPROM Checksum Is Not Valid\n"); 1120 error = EIO; 1121 goto err_late; 1122 } 1123 } 1124 1125 /* Copy the permanent MAC address out of the EEPROM */ 1126 if (e1000_read_mac_addr(hw) < 0) { 1127 device_printf(dev, "EEPROM read error while reading MAC" 1128 " address\n"); 1129 error = EIO; 1130 goto err_late; 1131 } 1132 1133 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1134 if (sc->vf_ifp) { 1135 ether_gen_addr(iflib_get_ifp(ctx), 1136 (struct ether_addr *)hw->mac.addr); 1137 } else { 1138 device_printf(dev, "Invalid MAC address\n"); 1139 error = EIO; 1140 goto err_late; 1141 } 1142 } 1143 1144 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1145 em_fw_version_locked(ctx); 1146 1147 em_print_fw_version(sc); 1148 1149 /* 1150 * Get Wake-on-Lan and Management info for later use 1151 */ 1152 em_get_wakeup(ctx); 1153 1154 /* Enable only WOL MAGIC by default */ 1155 scctx->isc_capenable &= ~IFCAP_WOL; 1156 if (sc->wol != 0) 1157 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1158 1159 iflib_set_mac(ctx, hw->mac.addr); 1160 1161 return (0); 1162 1163 err_late: 1164 em_release_hw_control(sc); 1165 err_pci: 1166 em_free_pci_resources(ctx); 1167 free(sc->mta, M_DEVBUF); 1168 1169 return (error); 1170 } 1171 1172 static int 1173 em_if_attach_post(if_ctx_t ctx) 1174 { 1175 struct e1000_softc *sc = iflib_get_softc(ctx); 1176 struct e1000_hw *hw = &sc->hw; 1177 int error = 0; 1178 1179 /* Setup OS specific network interface */ 1180 error = em_setup_interface(ctx); 1181 if (error != 0) { 1182 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1183 goto err_late; 1184 } 1185 1186 em_reset(ctx); 1187 1188 /* Initialize statistics */ 1189 em_update_stats_counters(sc); 1190 hw->mac.get_link_status = 1; 1191 em_if_update_admin_status(ctx); 1192 em_add_hw_stats(sc); 1193 1194 /* Non-AMT based hardware can now take control from firmware */ 1195 if (sc->has_manage && !sc->has_amt) 1196 em_get_hw_control(sc); 1197 1198 INIT_DEBUGOUT("em_if_attach_post: end"); 1199 1200 return (0); 1201 1202 err_late: 1203 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1204 return (error); 1205 } 1206 1207 /********************************************************************* 1208 * Device removal routine 1209 * 1210 * The detach entry point is called when the driver is being removed. 1211 * This routine stops the adapter and deallocates all the resources 1212 * that were allocated for driver operation. 1213 * 1214 * return 0 on success, positive on failure 1215 *********************************************************************/ 1216 static int 1217 em_if_detach(if_ctx_t ctx) 1218 { 1219 struct e1000_softc *sc = iflib_get_softc(ctx); 1220 1221 INIT_DEBUGOUT("em_if_detach: begin"); 1222 1223 e1000_phy_hw_reset(&sc->hw); 1224 1225 em_release_manageability(sc); 1226 em_release_hw_control(sc); 1227 em_free_pci_resources(ctx); 1228 free(sc->mta, M_DEVBUF); 1229 sc->mta = NULL; 1230 1231 return (0); 1232 } 1233 1234 /********************************************************************* 1235 * 1236 * Shutdown entry point 1237 * 1238 **********************************************************************/ 1239 1240 static int 1241 em_if_shutdown(if_ctx_t ctx) 1242 { 1243 return em_if_suspend(ctx); 1244 } 1245 1246 /* 1247 * Suspend/resume device methods. 1248 */ 1249 static int 1250 em_if_suspend(if_ctx_t ctx) 1251 { 1252 struct e1000_softc *sc = iflib_get_softc(ctx); 1253 1254 em_release_manageability(sc); 1255 em_release_hw_control(sc); 1256 em_enable_wakeup(ctx); 1257 return (0); 1258 } 1259 1260 static int 1261 em_if_resume(if_ctx_t ctx) 1262 { 1263 struct e1000_softc *sc = iflib_get_softc(ctx); 1264 1265 if (sc->hw.mac.type == e1000_pch2lan) 1266 e1000_resume_workarounds_pchlan(&sc->hw); 1267 em_if_init(ctx); 1268 em_init_manageability(sc); 1269 1270 return(0); 1271 } 1272 1273 static int 1274 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1275 { 1276 int max_frame_size; 1277 struct e1000_softc *sc = iflib_get_softc(ctx); 1278 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1279 1280 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1281 1282 switch (sc->hw.mac.type) { 1283 case e1000_82571: 1284 case e1000_82572: 1285 case e1000_ich9lan: 1286 case e1000_ich10lan: 1287 case e1000_pch2lan: 1288 case e1000_pch_lpt: 1289 case e1000_pch_spt: 1290 case e1000_pch_cnp: 1291 case e1000_pch_tgp: 1292 case e1000_pch_adp: 1293 case e1000_pch_mtp: 1294 case e1000_pch_ptp: 1295 case e1000_82574: 1296 case e1000_82583: 1297 case e1000_80003es2lan: 1298 /* 9K Jumbo Frame size */ 1299 max_frame_size = 9234; 1300 break; 1301 case e1000_pchlan: 1302 max_frame_size = 4096; 1303 break; 1304 case e1000_82542: 1305 case e1000_ich8lan: 1306 /* Adapters that do not support jumbo frames */ 1307 max_frame_size = ETHER_MAX_LEN; 1308 break; 1309 default: 1310 if (sc->hw.mac.type >= igb_mac_min) 1311 max_frame_size = 9234; 1312 else /* lem */ 1313 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1314 } 1315 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1316 return (EINVAL); 1317 } 1318 1319 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1320 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1321 return (0); 1322 } 1323 1324 /********************************************************************* 1325 * Init entry point 1326 * 1327 * This routine is used in two ways. It is used by the stack as 1328 * init entry point in network interface structure. It is also used 1329 * by the driver as a hw/sw initialization routine to get to a 1330 * consistent state. 1331 * 1332 **********************************************************************/ 1333 static void 1334 em_if_init(if_ctx_t ctx) 1335 { 1336 struct e1000_softc *sc = iflib_get_softc(ctx); 1337 if_softc_ctx_t scctx = sc->shared; 1338 if_t ifp = iflib_get_ifp(ctx); 1339 struct em_tx_queue *tx_que; 1340 int i; 1341 1342 INIT_DEBUGOUT("em_if_init: begin"); 1343 1344 /* Get the latest mac address, User can use a LAA */ 1345 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1346 ETHER_ADDR_LEN); 1347 1348 /* Put the address into the Receive Address Array */ 1349 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1350 1351 /* 1352 * With the 82571 adapter, RAR[0] may be overwritten 1353 * when the other port is reset, we make a duplicate 1354 * in RAR[14] for that eventuality, this assures 1355 * the interface continues to function. 1356 */ 1357 if (sc->hw.mac.type == e1000_82571) { 1358 e1000_set_laa_state_82571(&sc->hw, true); 1359 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1360 E1000_RAR_ENTRIES - 1); 1361 } 1362 1363 /* Initialize the hardware */ 1364 em_reset(ctx); 1365 em_if_update_admin_status(ctx); 1366 1367 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1368 struct tx_ring *txr = &tx_que->txr; 1369 1370 txr->tx_rs_cidx = txr->tx_rs_pidx; 1371 1372 /* Initialize the last processed descriptor to be the end of 1373 * the ring, rather than the start, so that we avoid an 1374 * off-by-one error when calculating how many descriptors are 1375 * done in the credits_update function. 1376 */ 1377 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1378 } 1379 1380 /* Setup VLAN support, basic and offload if available */ 1381 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1382 1383 /* Clear bad data from Rx FIFOs */ 1384 if (sc->hw.mac.type >= igb_mac_min) 1385 e1000_rx_fifo_flush_base(&sc->hw); 1386 1387 /* Configure for OS presence */ 1388 em_init_manageability(sc); 1389 1390 /* Prepare transmit descriptors and buffers */ 1391 em_initialize_transmit_unit(ctx); 1392 1393 /* Setup Multicast table */ 1394 em_if_multi_set(ctx); 1395 1396 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1397 em_initialize_receive_unit(ctx); 1398 1399 /* Set up VLAN support and filter */ 1400 em_setup_vlan_hw_support(ctx); 1401 1402 /* Don't lose promiscuous settings */ 1403 em_if_set_promisc(ctx, if_getflags(ifp)); 1404 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1405 1406 /* MSI-X configuration for 82574 */ 1407 if (sc->hw.mac.type == e1000_82574) { 1408 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1409 1410 tmp |= E1000_CTRL_EXT_PBA_CLR; 1411 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1412 /* Set the IVAR - interrupt vector routing. */ 1413 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1414 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1415 igb_configure_queues(sc); 1416 1417 /* this clears any pending interrupts */ 1418 E1000_READ_REG(&sc->hw, E1000_ICR); 1419 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1420 1421 /* AMT based hardware can now take control from firmware */ 1422 if (sc->has_manage && sc->has_amt) 1423 em_get_hw_control(sc); 1424 1425 /* Set Energy Efficient Ethernet */ 1426 if (sc->hw.mac.type >= igb_mac_min && 1427 sc->hw.phy.media_type == e1000_media_type_copper) { 1428 if (sc->hw.mac.type == e1000_i354) 1429 e1000_set_eee_i354(&sc->hw, true, true); 1430 else 1431 e1000_set_eee_i350(&sc->hw, true, true); 1432 } 1433 } 1434 1435 /********************************************************************* 1436 * 1437 * Fast Legacy/MSI Combined Interrupt Service routine 1438 * 1439 *********************************************************************/ 1440 int 1441 em_intr(void *arg) 1442 { 1443 struct e1000_softc *sc = arg; 1444 if_ctx_t ctx = sc->ctx; 1445 u32 reg_icr; 1446 1447 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1448 1449 /* Hot eject? */ 1450 if (reg_icr == 0xffffffff) 1451 return FILTER_STRAY; 1452 1453 /* Definitely not our interrupt. */ 1454 if (reg_icr == 0x0) 1455 return FILTER_STRAY; 1456 1457 /* 1458 * Starting with the 82571 chip, bit 31 should be used to 1459 * determine whether the interrupt belongs to us. 1460 */ 1461 if (sc->hw.mac.type >= e1000_82571 && 1462 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1463 return FILTER_STRAY; 1464 1465 /* 1466 * Only MSI-X interrupts have one-shot behavior by taking advantage 1467 * of the EIAC register. Thus, explicitly disable interrupts. This 1468 * also works around the MSI message reordering errata on certain 1469 * systems. 1470 */ 1471 IFDI_INTR_DISABLE(ctx); 1472 1473 /* Link status change */ 1474 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1475 em_handle_link(ctx); 1476 1477 if (reg_icr & E1000_ICR_RXO) 1478 sc->rx_overruns++; 1479 1480 return (FILTER_SCHEDULE_THREAD); 1481 } 1482 1483 static int 1484 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1485 { 1486 struct e1000_softc *sc = iflib_get_softc(ctx); 1487 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1488 1489 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1490 return (0); 1491 } 1492 1493 static int 1494 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1495 { 1496 struct e1000_softc *sc = iflib_get_softc(ctx); 1497 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1498 1499 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1500 return (0); 1501 } 1502 1503 static int 1504 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1505 { 1506 struct e1000_softc *sc = iflib_get_softc(ctx); 1507 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1508 1509 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1510 return (0); 1511 } 1512 1513 static int 1514 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1515 { 1516 struct e1000_softc *sc = iflib_get_softc(ctx); 1517 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1518 1519 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1520 return (0); 1521 } 1522 1523 /********************************************************************* 1524 * 1525 * MSI-X RX Interrupt Service routine 1526 * 1527 **********************************************************************/ 1528 static int 1529 em_msix_que(void *arg) 1530 { 1531 struct em_rx_queue *que = arg; 1532 1533 ++que->irqs; 1534 1535 return (FILTER_SCHEDULE_THREAD); 1536 } 1537 1538 /********************************************************************* 1539 * 1540 * MSI-X Link Fast Interrupt Service routine 1541 * 1542 **********************************************************************/ 1543 static int 1544 em_msix_link(void *arg) 1545 { 1546 struct e1000_softc *sc = arg; 1547 u32 reg_icr; 1548 1549 ++sc->link_irq; 1550 MPASS(sc->hw.back != NULL); 1551 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1552 1553 if (reg_icr & E1000_ICR_RXO) 1554 sc->rx_overruns++; 1555 1556 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1557 em_handle_link(sc->ctx); 1558 1559 /* Re-arm unconditionally */ 1560 if (sc->hw.mac.type >= igb_mac_min) { 1561 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1562 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1563 } else if (sc->hw.mac.type == e1000_82574) { 1564 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1565 E1000_IMS_OTHER); 1566 /* 1567 * Because we must read the ICR for this interrupt it may 1568 * clear other causes using autoclear, for this reason we 1569 * simply create a soft interrupt for all these vectors. 1570 */ 1571 if (reg_icr) 1572 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1573 } else 1574 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1575 1576 return (FILTER_HANDLED); 1577 } 1578 1579 static void 1580 em_handle_link(void *context) 1581 { 1582 if_ctx_t ctx = context; 1583 struct e1000_softc *sc = iflib_get_softc(ctx); 1584 1585 sc->hw.mac.get_link_status = 1; 1586 iflib_admin_intr_deferred(ctx); 1587 } 1588 1589 /********************************************************************* 1590 * 1591 * Media Ioctl callback 1592 * 1593 * This routine is called whenever the user queries the status of 1594 * the interface using ifconfig. 1595 * 1596 **********************************************************************/ 1597 static void 1598 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1599 { 1600 struct e1000_softc *sc = iflib_get_softc(ctx); 1601 u_char fiber_type = IFM_1000_SX; 1602 1603 INIT_DEBUGOUT("em_if_media_status: begin"); 1604 1605 iflib_admin_intr_deferred(ctx); 1606 1607 ifmr->ifm_status = IFM_AVALID; 1608 ifmr->ifm_active = IFM_ETHER; 1609 1610 if (!sc->link_active) { 1611 return; 1612 } 1613 1614 ifmr->ifm_status |= IFM_ACTIVE; 1615 1616 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1617 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1618 if (sc->hw.mac.type == e1000_82545) 1619 fiber_type = IFM_1000_LX; 1620 ifmr->ifm_active |= fiber_type | IFM_FDX; 1621 } else { 1622 switch (sc->link_speed) { 1623 case 10: 1624 ifmr->ifm_active |= IFM_10_T; 1625 break; 1626 case 100: 1627 ifmr->ifm_active |= IFM_100_TX; 1628 break; 1629 case 1000: 1630 ifmr->ifm_active |= IFM_1000_T; 1631 break; 1632 } 1633 if (sc->link_duplex == FULL_DUPLEX) 1634 ifmr->ifm_active |= IFM_FDX; 1635 else 1636 ifmr->ifm_active |= IFM_HDX; 1637 } 1638 } 1639 1640 /********************************************************************* 1641 * 1642 * Media Ioctl callback 1643 * 1644 * This routine is called when the user changes speed/duplex using 1645 * media/mediopt option with ifconfig. 1646 * 1647 **********************************************************************/ 1648 static int 1649 em_if_media_change(if_ctx_t ctx) 1650 { 1651 struct e1000_softc *sc = iflib_get_softc(ctx); 1652 struct ifmedia *ifm = iflib_get_media(ctx); 1653 1654 INIT_DEBUGOUT("em_if_media_change: begin"); 1655 1656 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1657 return (EINVAL); 1658 1659 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1660 case IFM_AUTO: 1661 sc->hw.mac.autoneg = DO_AUTO_NEG; 1662 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1663 break; 1664 case IFM_1000_LX: 1665 case IFM_1000_SX: 1666 case IFM_1000_T: 1667 sc->hw.mac.autoneg = DO_AUTO_NEG; 1668 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1669 break; 1670 case IFM_100_TX: 1671 sc->hw.mac.autoneg = false; 1672 sc->hw.phy.autoneg_advertised = 0; 1673 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1674 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1675 else 1676 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1677 break; 1678 case IFM_10_T: 1679 sc->hw.mac.autoneg = false; 1680 sc->hw.phy.autoneg_advertised = 0; 1681 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1682 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1683 else 1684 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1685 break; 1686 default: 1687 device_printf(sc->dev, "Unsupported media type\n"); 1688 } 1689 1690 em_if_init(ctx); 1691 1692 return (0); 1693 } 1694 1695 static int 1696 em_if_set_promisc(if_ctx_t ctx, int flags) 1697 { 1698 struct e1000_softc *sc = iflib_get_softc(ctx); 1699 if_t ifp = iflib_get_ifp(ctx); 1700 u32 reg_rctl; 1701 int mcnt = 0; 1702 1703 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1704 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1705 if (flags & IFF_ALLMULTI) 1706 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1707 else 1708 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1709 1710 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1711 reg_rctl &= (~E1000_RCTL_MPE); 1712 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1713 1714 if (flags & IFF_PROMISC) { 1715 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1716 em_if_vlan_filter_disable(sc); 1717 /* Turn this on if you want to see bad packets */ 1718 if (em_debug_sbp) 1719 reg_rctl |= E1000_RCTL_SBP; 1720 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1721 } else { 1722 if (flags & IFF_ALLMULTI) { 1723 reg_rctl |= E1000_RCTL_MPE; 1724 reg_rctl &= ~E1000_RCTL_UPE; 1725 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1726 } 1727 if (em_if_vlan_filter_used(ctx)) 1728 em_if_vlan_filter_enable(sc); 1729 } 1730 return (0); 1731 } 1732 1733 static u_int 1734 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1735 { 1736 u8 *mta = arg; 1737 1738 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1739 return (0); 1740 1741 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1742 1743 return (1); 1744 } 1745 1746 /********************************************************************* 1747 * Multicast Update 1748 * 1749 * This routine is called whenever multicast address list is updated. 1750 * 1751 **********************************************************************/ 1752 static void 1753 em_if_multi_set(if_ctx_t ctx) 1754 { 1755 struct e1000_softc *sc = iflib_get_softc(ctx); 1756 if_t ifp = iflib_get_ifp(ctx); 1757 u8 *mta; /* Multicast array memory */ 1758 u32 reg_rctl = 0; 1759 int mcnt = 0; 1760 1761 IOCTL_DEBUGOUT("em_set_multi: begin"); 1762 1763 mta = sc->mta; 1764 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1765 1766 if (sc->hw.mac.type == e1000_82542 && 1767 sc->hw.revision_id == E1000_REVISION_2) { 1768 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1769 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1770 e1000_pci_clear_mwi(&sc->hw); 1771 reg_rctl |= E1000_RCTL_RST; 1772 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1773 msec_delay(5); 1774 } 1775 1776 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1777 1778 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1779 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1780 1781 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1782 1783 if (if_getflags(ifp) & IFF_PROMISC) 1784 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1785 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1786 if_getflags(ifp) & IFF_ALLMULTI) { 1787 reg_rctl |= E1000_RCTL_MPE; 1788 reg_rctl &= ~E1000_RCTL_UPE; 1789 } else 1790 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1791 1792 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1793 1794 if (sc->hw.mac.type == e1000_82542 && 1795 sc->hw.revision_id == E1000_REVISION_2) { 1796 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1797 reg_rctl &= ~E1000_RCTL_RST; 1798 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1799 msec_delay(5); 1800 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1801 e1000_pci_set_mwi(&sc->hw); 1802 } 1803 } 1804 1805 /********************************************************************* 1806 * Timer routine 1807 * 1808 * This routine schedules em_if_update_admin_status() to check for 1809 * link status and to gather statistics as well as to perform some 1810 * controller-specific hardware patting. 1811 * 1812 **********************************************************************/ 1813 static void 1814 em_if_timer(if_ctx_t ctx, uint16_t qid) 1815 { 1816 1817 if (qid != 0) 1818 return; 1819 1820 iflib_admin_intr_deferred(ctx); 1821 } 1822 1823 static void 1824 em_if_update_admin_status(if_ctx_t ctx) 1825 { 1826 struct e1000_softc *sc = iflib_get_softc(ctx); 1827 struct e1000_hw *hw = &sc->hw; 1828 device_t dev = iflib_get_dev(ctx); 1829 u32 link_check, thstat, ctrl; 1830 bool automasked = false; 1831 1832 link_check = thstat = ctrl = 0; 1833 /* Get the cached link value or read phy for real */ 1834 switch (hw->phy.media_type) { 1835 case e1000_media_type_copper: 1836 if (hw->mac.get_link_status) { 1837 if (hw->mac.type == e1000_pch_spt) 1838 msec_delay(50); 1839 /* Do the work to read phy */ 1840 e1000_check_for_link(hw); 1841 link_check = !hw->mac.get_link_status; 1842 if (link_check) /* ESB2 fix */ 1843 e1000_cfg_on_link_up(hw); 1844 } else { 1845 link_check = true; 1846 } 1847 break; 1848 case e1000_media_type_fiber: 1849 e1000_check_for_link(hw); 1850 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1851 E1000_STATUS_LU); 1852 break; 1853 case e1000_media_type_internal_serdes: 1854 e1000_check_for_link(hw); 1855 link_check = hw->mac.serdes_has_link; 1856 break; 1857 /* VF device is type_unknown */ 1858 case e1000_media_type_unknown: 1859 e1000_check_for_link(hw); 1860 link_check = !hw->mac.get_link_status; 1861 /* FALLTHROUGH */ 1862 default: 1863 break; 1864 } 1865 1866 /* Check for thermal downshift or shutdown */ 1867 if (hw->mac.type == e1000_i350) { 1868 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1869 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1870 } 1871 1872 /* Now check for a transition */ 1873 if (link_check && (sc->link_active == 0)) { 1874 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1875 &sc->link_duplex); 1876 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1877 if ((sc->link_speed != SPEED_1000) && 1878 ((hw->mac.type == e1000_82571) || 1879 (hw->mac.type == e1000_82572))) { 1880 int tarc0; 1881 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1882 tarc0 &= ~TARC_SPEED_MODE_BIT; 1883 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1884 } 1885 if (bootverbose) 1886 device_printf(dev, "Link is up %d Mbps %s\n", 1887 sc->link_speed, 1888 ((sc->link_duplex == FULL_DUPLEX) ? 1889 "Full Duplex" : "Half Duplex")); 1890 sc->link_active = 1; 1891 sc->smartspeed = 0; 1892 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1893 E1000_CTRL_EXT_LINK_MODE_GMII && 1894 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1895 device_printf(dev, "Link: thermal downshift\n"); 1896 /* Delay Link Up for Phy update */ 1897 if (((hw->mac.type == e1000_i210) || 1898 (hw->mac.type == e1000_i211)) && 1899 (hw->phy.id == I210_I_PHY_ID)) 1900 msec_delay(I210_LINK_DELAY); 1901 /* Reset if the media type changed. */ 1902 if (hw->dev_spec._82575.media_changed && 1903 hw->mac.type >= igb_mac_min) { 1904 hw->dev_spec._82575.media_changed = false; 1905 sc->flags |= IGB_MEDIA_RESET; 1906 em_reset(ctx); 1907 } 1908 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 1909 if (hw->mac.type < igb_mac_min) 1910 automasked = em_automask_tso(ctx); 1911 1912 /* Automasking resets the interface, so don't mark it up yet */ 1913 if (!automasked) 1914 iflib_link_state_change(ctx, LINK_STATE_UP, 1915 IF_Mbps(sc->link_speed)); 1916 } else if (!link_check && (sc->link_active == 1)) { 1917 sc->link_speed = 0; 1918 sc->link_duplex = 0; 1919 sc->link_active = 0; 1920 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1921 } 1922 em_update_stats_counters(sc); 1923 1924 /* Reset LAA into RAR[0] on 82571 */ 1925 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1926 e1000_rar_set(hw, hw->mac.addr, 0); 1927 1928 if (hw->mac.type < em_mac_min) 1929 lem_smartspeed(sc); 1930 } 1931 1932 static void 1933 em_if_watchdog_reset(if_ctx_t ctx) 1934 { 1935 struct e1000_softc *sc = iflib_get_softc(ctx); 1936 1937 /* 1938 * Just count the event; iflib(4) will already trigger a 1939 * sufficient reset of the controller. 1940 */ 1941 sc->watchdog_events++; 1942 } 1943 1944 /********************************************************************* 1945 * 1946 * This routine disables all traffic on the adapter by issuing a 1947 * global reset on the MAC. 1948 * 1949 **********************************************************************/ 1950 static void 1951 em_if_stop(if_ctx_t ctx) 1952 { 1953 struct e1000_softc *sc = iflib_get_softc(ctx); 1954 1955 INIT_DEBUGOUT("em_if_stop: begin"); 1956 1957 /* I219 needs special flushing to avoid hangs */ 1958 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1959 em_flush_desc_rings(sc); 1960 1961 e1000_reset_hw(&sc->hw); 1962 if (sc->hw.mac.type >= e1000_82544) 1963 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1964 1965 e1000_led_off(&sc->hw); 1966 e1000_cleanup_led(&sc->hw); 1967 } 1968 1969 /********************************************************************* 1970 * 1971 * Determine hardware revision. 1972 * 1973 **********************************************************************/ 1974 static void 1975 em_identify_hardware(if_ctx_t ctx) 1976 { 1977 device_t dev = iflib_get_dev(ctx); 1978 struct e1000_softc *sc = iflib_get_softc(ctx); 1979 1980 /* Make sure our PCI config space has the necessary stuff set */ 1981 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1982 1983 /* Save off the information about this board */ 1984 sc->hw.vendor_id = pci_get_vendor(dev); 1985 sc->hw.device_id = pci_get_device(dev); 1986 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1987 sc->hw.subsystem_vendor_id = 1988 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1989 sc->hw.subsystem_device_id = 1990 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1991 1992 /* Do Shared Code Init and Setup */ 1993 if (e1000_set_mac_type(&sc->hw)) { 1994 device_printf(dev, "Setup init failure\n"); 1995 return; 1996 } 1997 1998 /* Are we a VF device? */ 1999 if ((sc->hw.mac.type == e1000_vfadapt) || 2000 (sc->hw.mac.type == e1000_vfadapt_i350)) 2001 sc->vf_ifp = 1; 2002 else 2003 sc->vf_ifp = 0; 2004 } 2005 2006 static int 2007 em_allocate_pci_resources(if_ctx_t ctx) 2008 { 2009 struct e1000_softc *sc = iflib_get_softc(ctx); 2010 device_t dev = iflib_get_dev(ctx); 2011 int rid, val; 2012 2013 rid = PCIR_BAR(0); 2014 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2015 &rid, RF_ACTIVE); 2016 if (sc->memory == NULL) { 2017 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2018 return (ENXIO); 2019 } 2020 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2021 sc->osdep.mem_bus_space_handle = 2022 rman_get_bushandle(sc->memory); 2023 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2024 2025 /* Only older adapters use IO mapping */ 2026 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2027 /* Figure our where our IO BAR is ? */ 2028 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2029 val = pci_read_config(dev, rid, 4); 2030 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2031 break; 2032 } 2033 rid += 4; 2034 /* check for 64bit BAR */ 2035 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2036 rid += 4; 2037 } 2038 if (rid >= PCIR_CIS) { 2039 device_printf(dev, "Unable to locate IO BAR\n"); 2040 return (ENXIO); 2041 } 2042 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2043 &rid, RF_ACTIVE); 2044 if (sc->ioport == NULL) { 2045 device_printf(dev, "Unable to allocate bus resource: " 2046 "ioport\n"); 2047 return (ENXIO); 2048 } 2049 sc->hw.io_base = 0; 2050 sc->osdep.io_bus_space_tag = 2051 rman_get_bustag(sc->ioport); 2052 sc->osdep.io_bus_space_handle = 2053 rman_get_bushandle(sc->ioport); 2054 } 2055 2056 sc->hw.back = &sc->osdep; 2057 2058 return (0); 2059 } 2060 2061 /********************************************************************* 2062 * 2063 * Set up the MSI-X Interrupt handlers 2064 * 2065 **********************************************************************/ 2066 static int 2067 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2068 { 2069 struct e1000_softc *sc = iflib_get_softc(ctx); 2070 struct em_rx_queue *rx_que = sc->rx_queues; 2071 struct em_tx_queue *tx_que = sc->tx_queues; 2072 int error, rid, i, vector = 0, rx_vectors; 2073 char buf[16]; 2074 2075 /* First set up ring resources */ 2076 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2077 rid = vector + 1; 2078 snprintf(buf, sizeof(buf), "rxq%d", i); 2079 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2080 if (error) { 2081 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2082 sc->rx_num_queues = i + 1; 2083 goto fail; 2084 } 2085 2086 rx_que->msix = vector; 2087 2088 /* 2089 * Set the bit to enable interrupt 2090 * in E1000_IMS -- bits 20 and 21 2091 * are for RX0 and RX1, note this has 2092 * NOTHING to do with the MSI-X vector 2093 */ 2094 if (sc->hw.mac.type == e1000_82574) { 2095 rx_que->eims = 1 << (20 + i); 2096 sc->ims |= rx_que->eims; 2097 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2098 } else if (sc->hw.mac.type == e1000_82575) 2099 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2100 else 2101 rx_que->eims = 1 << vector; 2102 } 2103 rx_vectors = vector; 2104 2105 vector = 0; 2106 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2107 snprintf(buf, sizeof(buf), "txq%d", i); 2108 tx_que = &sc->tx_queues[i]; 2109 iflib_softirq_alloc_generic(ctx, 2110 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2111 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2112 2113 tx_que->msix = (vector % sc->rx_num_queues); 2114 2115 /* 2116 * Set the bit to enable interrupt 2117 * in E1000_IMS -- bits 22 and 23 2118 * are for TX0 and TX1, note this has 2119 * NOTHING to do with the MSI-X vector 2120 */ 2121 if (sc->hw.mac.type == e1000_82574) { 2122 tx_que->eims = 1 << (22 + i); 2123 sc->ims |= tx_que->eims; 2124 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2125 } else if (sc->hw.mac.type == e1000_82575) { 2126 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2127 } else { 2128 tx_que->eims = 1 << i; 2129 } 2130 } 2131 2132 /* Link interrupt */ 2133 rid = rx_vectors + 1; 2134 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2135 2136 if (error) { 2137 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2138 goto fail; 2139 } 2140 sc->linkvec = rx_vectors; 2141 if (sc->hw.mac.type < igb_mac_min) { 2142 sc->ivars |= (8 | rx_vectors) << 16; 2143 sc->ivars |= 0x80000000; 2144 /* Enable the "Other" interrupt type for link status change */ 2145 sc->ims |= E1000_IMS_OTHER; 2146 } 2147 2148 return (0); 2149 fail: 2150 iflib_irq_free(ctx, &sc->irq); 2151 rx_que = sc->rx_queues; 2152 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2153 iflib_irq_free(ctx, &rx_que->que_irq); 2154 return (error); 2155 } 2156 2157 static void 2158 igb_configure_queues(struct e1000_softc *sc) 2159 { 2160 struct e1000_hw *hw = &sc->hw; 2161 struct em_rx_queue *rx_que; 2162 struct em_tx_queue *tx_que; 2163 u32 tmp, ivar = 0, newitr = 0; 2164 2165 /* First turn on RSS capability */ 2166 if (hw->mac.type != e1000_82575) 2167 E1000_WRITE_REG(hw, E1000_GPIE, 2168 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2169 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2170 2171 /* Turn on MSI-X */ 2172 switch (hw->mac.type) { 2173 case e1000_82580: 2174 case e1000_i350: 2175 case e1000_i354: 2176 case e1000_i210: 2177 case e1000_i211: 2178 case e1000_vfadapt: 2179 case e1000_vfadapt_i350: 2180 /* RX entries */ 2181 for (int i = 0; i < sc->rx_num_queues; i++) { 2182 u32 index = i >> 1; 2183 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2184 rx_que = &sc->rx_queues[i]; 2185 if (i & 1) { 2186 ivar &= 0xFF00FFFF; 2187 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2188 } else { 2189 ivar &= 0xFFFFFF00; 2190 ivar |= rx_que->msix | E1000_IVAR_VALID; 2191 } 2192 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2193 } 2194 /* TX entries */ 2195 for (int i = 0; i < sc->tx_num_queues; i++) { 2196 u32 index = i >> 1; 2197 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2198 tx_que = &sc->tx_queues[i]; 2199 if (i & 1) { 2200 ivar &= 0x00FFFFFF; 2201 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2202 } else { 2203 ivar &= 0xFFFF00FF; 2204 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2205 } 2206 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2207 sc->que_mask |= tx_que->eims; 2208 } 2209 2210 /* And for the link interrupt */ 2211 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2212 sc->link_mask = 1 << sc->linkvec; 2213 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2214 break; 2215 case e1000_82576: 2216 /* RX entries */ 2217 for (int i = 0; i < sc->rx_num_queues; i++) { 2218 u32 index = i & 0x7; /* Each IVAR has two entries */ 2219 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2220 rx_que = &sc->rx_queues[i]; 2221 if (i < 8) { 2222 ivar &= 0xFFFFFF00; 2223 ivar |= rx_que->msix | E1000_IVAR_VALID; 2224 } else { 2225 ivar &= 0xFF00FFFF; 2226 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2227 } 2228 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2229 sc->que_mask |= rx_que->eims; 2230 } 2231 /* TX entries */ 2232 for (int i = 0; i < sc->tx_num_queues; i++) { 2233 u32 index = i & 0x7; /* Each IVAR has two entries */ 2234 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2235 tx_que = &sc->tx_queues[i]; 2236 if (i < 8) { 2237 ivar &= 0xFFFF00FF; 2238 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2239 } else { 2240 ivar &= 0x00FFFFFF; 2241 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2242 } 2243 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2244 sc->que_mask |= tx_que->eims; 2245 } 2246 2247 /* And for the link interrupt */ 2248 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2249 sc->link_mask = 1 << sc->linkvec; 2250 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2251 break; 2252 2253 case e1000_82575: 2254 /* enable MSI-X support*/ 2255 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2256 tmp |= E1000_CTRL_EXT_PBA_CLR; 2257 /* Auto-Mask interrupts upon ICR read. */ 2258 tmp |= E1000_CTRL_EXT_EIAME; 2259 tmp |= E1000_CTRL_EXT_IRCA; 2260 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2261 2262 /* Queues */ 2263 for (int i = 0; i < sc->rx_num_queues; i++) { 2264 rx_que = &sc->rx_queues[i]; 2265 tmp = E1000_EICR_RX_QUEUE0 << i; 2266 tmp |= E1000_EICR_TX_QUEUE0 << i; 2267 rx_que->eims = tmp; 2268 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2269 i, rx_que->eims); 2270 sc->que_mask |= rx_que->eims; 2271 } 2272 2273 /* Link */ 2274 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2275 E1000_EIMS_OTHER); 2276 sc->link_mask |= E1000_EIMS_OTHER; 2277 default: 2278 break; 2279 } 2280 2281 /* Set the starting interrupt rate */ 2282 if (em_max_interrupt_rate > 0) 2283 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2284 2285 if (hw->mac.type == e1000_82575) 2286 newitr |= newitr << 16; 2287 else 2288 newitr |= E1000_EITR_CNT_IGNR; 2289 2290 for (int i = 0; i < sc->rx_num_queues; i++) { 2291 rx_que = &sc->rx_queues[i]; 2292 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2293 } 2294 2295 return; 2296 } 2297 2298 static void 2299 em_free_pci_resources(if_ctx_t ctx) 2300 { 2301 struct e1000_softc *sc = iflib_get_softc(ctx); 2302 struct em_rx_queue *que = sc->rx_queues; 2303 device_t dev = iflib_get_dev(ctx); 2304 2305 /* Release all MSI-X queue resources */ 2306 if (sc->intr_type == IFLIB_INTR_MSIX) 2307 iflib_irq_free(ctx, &sc->irq); 2308 2309 if (que != NULL) { 2310 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2311 iflib_irq_free(ctx, &que->que_irq); 2312 } 2313 } 2314 2315 if (sc->memory != NULL) { 2316 bus_release_resource(dev, SYS_RES_MEMORY, 2317 rman_get_rid(sc->memory), sc->memory); 2318 sc->memory = NULL; 2319 } 2320 2321 if (sc->flash != NULL) { 2322 bus_release_resource(dev, SYS_RES_MEMORY, 2323 rman_get_rid(sc->flash), sc->flash); 2324 sc->flash = NULL; 2325 } 2326 2327 if (sc->ioport != NULL) { 2328 bus_release_resource(dev, SYS_RES_IOPORT, 2329 rman_get_rid(sc->ioport), sc->ioport); 2330 sc->ioport = NULL; 2331 } 2332 } 2333 2334 /* Set up MSI or MSI-X */ 2335 static int 2336 em_setup_msix(if_ctx_t ctx) 2337 { 2338 struct e1000_softc *sc = iflib_get_softc(ctx); 2339 2340 if (sc->hw.mac.type == e1000_82574) { 2341 em_enable_vectors_82574(ctx); 2342 } 2343 return (0); 2344 } 2345 2346 /********************************************************************* 2347 * 2348 * Workaround for SmartSpeed on 82541 and 82547 controllers 2349 * 2350 **********************************************************************/ 2351 static void 2352 lem_smartspeed(struct e1000_softc *sc) 2353 { 2354 u16 phy_tmp; 2355 2356 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2357 sc->hw.mac.autoneg == 0 || 2358 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2359 return; 2360 2361 if (sc->smartspeed == 0) { 2362 /* If Master/Slave config fault is asserted twice, 2363 * we assume back-to-back */ 2364 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2365 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2366 return; 2367 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2368 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2369 e1000_read_phy_reg(&sc->hw, 2370 PHY_1000T_CTRL, &phy_tmp); 2371 if(phy_tmp & CR_1000T_MS_ENABLE) { 2372 phy_tmp &= ~CR_1000T_MS_ENABLE; 2373 e1000_write_phy_reg(&sc->hw, 2374 PHY_1000T_CTRL, phy_tmp); 2375 sc->smartspeed++; 2376 if(sc->hw.mac.autoneg && 2377 !e1000_copper_link_autoneg(&sc->hw) && 2378 !e1000_read_phy_reg(&sc->hw, 2379 PHY_CONTROL, &phy_tmp)) { 2380 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2381 MII_CR_RESTART_AUTO_NEG); 2382 e1000_write_phy_reg(&sc->hw, 2383 PHY_CONTROL, phy_tmp); 2384 } 2385 } 2386 } 2387 return; 2388 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2389 /* If still no link, perhaps using 2/3 pair cable */ 2390 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2391 phy_tmp |= CR_1000T_MS_ENABLE; 2392 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2393 if(sc->hw.mac.autoneg && 2394 !e1000_copper_link_autoneg(&sc->hw) && 2395 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2396 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2397 MII_CR_RESTART_AUTO_NEG); 2398 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2399 } 2400 } 2401 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2402 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2403 sc->smartspeed = 0; 2404 } 2405 2406 /********************************************************************* 2407 * 2408 * Initialize the DMA Coalescing feature 2409 * 2410 **********************************************************************/ 2411 static void 2412 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2413 { 2414 device_t dev = sc->dev; 2415 struct e1000_hw *hw = &sc->hw; 2416 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2417 u16 hwm; 2418 u16 max_frame_size; 2419 2420 if (hw->mac.type == e1000_i211) 2421 return; 2422 2423 max_frame_size = sc->shared->isc_max_frame_size; 2424 if (hw->mac.type > e1000_82580) { 2425 2426 if (sc->dmac == 0) { /* Disabling it */ 2427 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2428 return; 2429 } else 2430 device_printf(dev, "DMA Coalescing enabled\n"); 2431 2432 /* Set starting threshold */ 2433 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2434 2435 hwm = 64 * pba - max_frame_size / 16; 2436 if (hwm < 64 * (pba - 6)) 2437 hwm = 64 * (pba - 6); 2438 reg = E1000_READ_REG(hw, E1000_FCRTC); 2439 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2440 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2441 & E1000_FCRTC_RTH_COAL_MASK); 2442 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2443 2444 2445 dmac = pba - max_frame_size / 512; 2446 if (dmac < pba - 10) 2447 dmac = pba - 10; 2448 reg = E1000_READ_REG(hw, E1000_DMACR); 2449 reg &= ~E1000_DMACR_DMACTHR_MASK; 2450 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2451 & E1000_DMACR_DMACTHR_MASK); 2452 2453 /* transition to L0x or L1 if available..*/ 2454 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2455 2456 /* Check if status is 2.5Gb backplane connection 2457 * before configuration of watchdog timer, which is 2458 * in msec values in 12.8usec intervals 2459 * watchdog timer= msec values in 32usec intervals 2460 * for non 2.5Gb connection 2461 */ 2462 if (hw->mac.type == e1000_i354) { 2463 int status = E1000_READ_REG(hw, E1000_STATUS); 2464 if ((status & E1000_STATUS_2P5_SKU) && 2465 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2466 reg |= ((sc->dmac * 5) >> 6); 2467 else 2468 reg |= (sc->dmac >> 5); 2469 } else { 2470 reg |= (sc->dmac >> 5); 2471 } 2472 2473 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2474 2475 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2476 2477 /* Set the interval before transition */ 2478 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2479 if (hw->mac.type == e1000_i350) 2480 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2481 /* 2482 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2483 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2484 */ 2485 if (hw->mac.type == e1000_i354) { 2486 int status = E1000_READ_REG(hw, E1000_STATUS); 2487 if ((status & E1000_STATUS_2P5_SKU) && 2488 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2489 reg |= 0xA; 2490 else 2491 reg |= 0x4; 2492 } else { 2493 reg |= 0x4; 2494 } 2495 2496 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2497 2498 /* free space in tx packet buffer to wake from DMA coal */ 2499 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2500 (2 * max_frame_size)) >> 6); 2501 2502 /* make low power state decision controlled by DMA coal */ 2503 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2504 reg &= ~E1000_PCIEMISC_LX_DECISION; 2505 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2506 2507 } else if (hw->mac.type == e1000_82580) { 2508 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2509 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2510 reg & ~E1000_PCIEMISC_LX_DECISION); 2511 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2512 } 2513 } 2514 /********************************************************************* 2515 * The 3 following flush routines are used as a workaround in the 2516 * I219 client parts and only for them. 2517 * 2518 * em_flush_tx_ring - remove all descriptors from the tx_ring 2519 * 2520 * We want to clear all pending descriptors from the TX ring. 2521 * zeroing happens when the HW reads the regs. We assign the ring itself as 2522 * the data of the next descriptor. We don't care about the data we are about 2523 * to reset the HW. 2524 **********************************************************************/ 2525 static void 2526 em_flush_tx_ring(struct e1000_softc *sc) 2527 { 2528 struct e1000_hw *hw = &sc->hw; 2529 struct tx_ring *txr = &sc->tx_queues->txr; 2530 struct e1000_tx_desc *txd; 2531 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2532 u16 size = 512; 2533 2534 tctl = E1000_READ_REG(hw, E1000_TCTL); 2535 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2536 2537 txd = &txr->tx_base[txr->tx_cidx_processed]; 2538 2539 /* Just use the ring as a dummy buffer addr */ 2540 txd->buffer_addr = txr->tx_paddr; 2541 txd->lower.data = htole32(txd_lower | size); 2542 txd->upper.data = 0; 2543 2544 /* flush descriptors to memory before notifying the HW */ 2545 wmb(); 2546 2547 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2548 mb(); 2549 usec_delay(250); 2550 } 2551 2552 /********************************************************************* 2553 * em_flush_rx_ring - remove all descriptors from the rx_ring 2554 * 2555 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2556 **********************************************************************/ 2557 static void 2558 em_flush_rx_ring(struct e1000_softc *sc) 2559 { 2560 struct e1000_hw *hw = &sc->hw; 2561 u32 rctl, rxdctl; 2562 2563 rctl = E1000_READ_REG(hw, E1000_RCTL); 2564 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2565 E1000_WRITE_FLUSH(hw); 2566 usec_delay(150); 2567 2568 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2569 /* zero the lower 14 bits (prefetch and host thresholds) */ 2570 rxdctl &= 0xffffc000; 2571 /* 2572 * update thresholds: prefetch threshold to 31, host threshold to 1 2573 * and make sure the granularity is "descriptors" and not "cache lines" 2574 */ 2575 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2576 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2577 2578 /* momentarily enable the RX ring for the changes to take effect */ 2579 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2580 E1000_WRITE_FLUSH(hw); 2581 usec_delay(150); 2582 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2583 } 2584 2585 /********************************************************************* 2586 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2587 * 2588 * In I219, the descriptor rings must be emptied before resetting the HW 2589 * or before changing the device state to D3 during runtime (runtime PM). 2590 * 2591 * Failure to do this will cause the HW to enter a unit hang state which can 2592 * only be released by PCI reset on the device 2593 * 2594 **********************************************************************/ 2595 static void 2596 em_flush_desc_rings(struct e1000_softc *sc) 2597 { 2598 struct e1000_hw *hw = &sc->hw; 2599 device_t dev = sc->dev; 2600 u16 hang_state; 2601 u32 fext_nvm11, tdlen; 2602 2603 /* First, disable MULR fix in FEXTNVM11 */ 2604 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2605 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2606 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2607 2608 /* do nothing if we're not in faulty state, or if the queue is empty */ 2609 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2610 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2611 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2612 return; 2613 em_flush_tx_ring(sc); 2614 2615 /* recheck, maybe the fault is caused by the rx ring */ 2616 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2617 if (hang_state & FLUSH_DESC_REQUIRED) 2618 em_flush_rx_ring(sc); 2619 } 2620 2621 2622 /********************************************************************* 2623 * 2624 * Initialize the hardware to a configuration as specified by the 2625 * sc structure. 2626 * 2627 **********************************************************************/ 2628 static void 2629 em_reset(if_ctx_t ctx) 2630 { 2631 device_t dev = iflib_get_dev(ctx); 2632 struct e1000_softc *sc = iflib_get_softc(ctx); 2633 if_t ifp = iflib_get_ifp(ctx); 2634 struct e1000_hw *hw = &sc->hw; 2635 u32 rx_buffer_size; 2636 u32 pba; 2637 2638 INIT_DEBUGOUT("em_reset: begin"); 2639 /* Let the firmware know the OS is in control */ 2640 em_get_hw_control(sc); 2641 2642 /* Set up smart power down as default off on newer adapters. */ 2643 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2644 hw->mac.type == e1000_82572)) { 2645 u16 phy_tmp = 0; 2646 2647 /* Speed up time to link by disabling smart power down. */ 2648 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2649 phy_tmp &= ~IGP02E1000_PM_SPD; 2650 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2651 } 2652 2653 /* 2654 * Packet Buffer Allocation (PBA) 2655 * Writing PBA sets the receive portion of the buffer 2656 * the remainder is used for the transmit buffer. 2657 */ 2658 switch (hw->mac.type) { 2659 /* 82547: Total Packet Buffer is 40K */ 2660 case e1000_82547: 2661 case e1000_82547_rev_2: 2662 if (hw->mac.max_frame_size > 8192) 2663 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2664 else 2665 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2666 break; 2667 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2668 case e1000_82571: 2669 case e1000_82572: 2670 case e1000_80003es2lan: 2671 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2672 break; 2673 /* 82573: Total Packet Buffer is 32K */ 2674 case e1000_82573: 2675 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2676 break; 2677 case e1000_82574: 2678 case e1000_82583: 2679 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2680 break; 2681 case e1000_ich8lan: 2682 pba = E1000_PBA_8K; 2683 break; 2684 case e1000_ich9lan: 2685 case e1000_ich10lan: 2686 /* Boost Receive side for jumbo frames */ 2687 if (hw->mac.max_frame_size > 4096) 2688 pba = E1000_PBA_14K; 2689 else 2690 pba = E1000_PBA_10K; 2691 break; 2692 case e1000_pchlan: 2693 case e1000_pch2lan: 2694 case e1000_pch_lpt: 2695 case e1000_pch_spt: 2696 case e1000_pch_cnp: 2697 case e1000_pch_tgp: 2698 case e1000_pch_adp: 2699 case e1000_pch_mtp: 2700 case e1000_pch_ptp: 2701 pba = E1000_PBA_26K; 2702 break; 2703 case e1000_82575: 2704 pba = E1000_PBA_32K; 2705 break; 2706 case e1000_82576: 2707 case e1000_vfadapt: 2708 pba = E1000_READ_REG(hw, E1000_RXPBS); 2709 pba &= E1000_RXPBS_SIZE_MASK_82576; 2710 break; 2711 case e1000_82580: 2712 case e1000_i350: 2713 case e1000_i354: 2714 case e1000_vfadapt_i350: 2715 pba = E1000_READ_REG(hw, E1000_RXPBS); 2716 pba = e1000_rxpbs_adjust_82580(pba); 2717 break; 2718 case e1000_i210: 2719 case e1000_i211: 2720 pba = E1000_PBA_34K; 2721 break; 2722 default: 2723 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2724 if (hw->mac.max_frame_size > 8192) 2725 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2726 else 2727 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2728 } 2729 2730 /* Special needs in case of Jumbo frames */ 2731 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2732 u32 tx_space, min_tx, min_rx; 2733 pba = E1000_READ_REG(hw, E1000_PBA); 2734 tx_space = pba >> 16; 2735 pba &= 0xffff; 2736 min_tx = (hw->mac.max_frame_size + 2737 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2738 min_tx = roundup2(min_tx, 1024); 2739 min_tx >>= 10; 2740 min_rx = hw->mac.max_frame_size; 2741 min_rx = roundup2(min_rx, 1024); 2742 min_rx >>= 10; 2743 if (tx_space < min_tx && 2744 ((min_tx - tx_space) < pba)) { 2745 pba = pba - (min_tx - tx_space); 2746 /* 2747 * if short on rx space, rx wins 2748 * and must trump tx adjustment 2749 */ 2750 if (pba < min_rx) 2751 pba = min_rx; 2752 } 2753 E1000_WRITE_REG(hw, E1000_PBA, pba); 2754 } 2755 2756 if (hw->mac.type < igb_mac_min) 2757 E1000_WRITE_REG(hw, E1000_PBA, pba); 2758 2759 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2760 2761 /* 2762 * These parameters control the automatic generation (Tx) and 2763 * response (Rx) to Ethernet PAUSE frames. 2764 * - High water mark should allow for at least two frames to be 2765 * received after sending an XOFF. 2766 * - Low water mark works best when it is very near the high water mark. 2767 * This allows the receiver to restart by sending XON when it has 2768 * drained a bit. Here we use an arbitrary value of 1500 which will 2769 * restart after one full frame is pulled from the buffer. There 2770 * could be several smaller frames in the buffer and if so they will 2771 * not trigger the XON until their total number reduces the buffer 2772 * by 1500. 2773 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2774 */ 2775 rx_buffer_size = (pba & 0xffff) << 10; 2776 hw->fc.high_water = rx_buffer_size - 2777 roundup2(hw->mac.max_frame_size, 1024); 2778 hw->fc.low_water = hw->fc.high_water - 1500; 2779 2780 if (sc->fc) /* locally set flow control value? */ 2781 hw->fc.requested_mode = sc->fc; 2782 else 2783 hw->fc.requested_mode = e1000_fc_full; 2784 2785 if (hw->mac.type == e1000_80003es2lan) 2786 hw->fc.pause_time = 0xFFFF; 2787 else 2788 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2789 2790 hw->fc.send_xon = true; 2791 2792 /* Device specific overrides/settings */ 2793 switch (hw->mac.type) { 2794 case e1000_pchlan: 2795 /* Workaround: no TX flow ctrl for PCH */ 2796 hw->fc.requested_mode = e1000_fc_rx_pause; 2797 hw->fc.pause_time = 0xFFFF; /* override */ 2798 if (if_getmtu(ifp) > ETHERMTU) { 2799 hw->fc.high_water = 0x3500; 2800 hw->fc.low_water = 0x1500; 2801 } else { 2802 hw->fc.high_water = 0x5000; 2803 hw->fc.low_water = 0x3000; 2804 } 2805 hw->fc.refresh_time = 0x1000; 2806 break; 2807 case e1000_pch2lan: 2808 case e1000_pch_lpt: 2809 case e1000_pch_spt: 2810 case e1000_pch_cnp: 2811 case e1000_pch_tgp: 2812 case e1000_pch_adp: 2813 case e1000_pch_mtp: 2814 case e1000_pch_ptp: 2815 hw->fc.high_water = 0x5C20; 2816 hw->fc.low_water = 0x5048; 2817 hw->fc.pause_time = 0x0650; 2818 hw->fc.refresh_time = 0x0400; 2819 /* Jumbos need adjusted PBA */ 2820 if (if_getmtu(ifp) > ETHERMTU) 2821 E1000_WRITE_REG(hw, E1000_PBA, 12); 2822 else 2823 E1000_WRITE_REG(hw, E1000_PBA, 26); 2824 break; 2825 case e1000_82575: 2826 case e1000_82576: 2827 /* 8-byte granularity */ 2828 hw->fc.low_water = hw->fc.high_water - 8; 2829 break; 2830 case e1000_82580: 2831 case e1000_i350: 2832 case e1000_i354: 2833 case e1000_i210: 2834 case e1000_i211: 2835 case e1000_vfadapt: 2836 case e1000_vfadapt_i350: 2837 /* 16-byte granularity */ 2838 hw->fc.low_water = hw->fc.high_water - 16; 2839 break; 2840 case e1000_ich9lan: 2841 case e1000_ich10lan: 2842 if (if_getmtu(ifp) > ETHERMTU) { 2843 hw->fc.high_water = 0x2800; 2844 hw->fc.low_water = hw->fc.high_water - 8; 2845 break; 2846 } 2847 /* FALLTHROUGH */ 2848 default: 2849 if (hw->mac.type == e1000_80003es2lan) 2850 hw->fc.pause_time = 0xFFFF; 2851 break; 2852 } 2853 2854 /* I219 needs some special flushing to avoid hangs */ 2855 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2856 em_flush_desc_rings(sc); 2857 2858 /* Issue a global reset */ 2859 e1000_reset_hw(hw); 2860 if (hw->mac.type >= igb_mac_min) { 2861 E1000_WRITE_REG(hw, E1000_WUC, 0); 2862 } else { 2863 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2864 em_disable_aspm(sc); 2865 } 2866 if (sc->flags & IGB_MEDIA_RESET) { 2867 e1000_setup_init_funcs(hw, true); 2868 e1000_get_bus_info(hw); 2869 sc->flags &= ~IGB_MEDIA_RESET; 2870 } 2871 /* and a re-init */ 2872 if (e1000_init_hw(hw) < 0) { 2873 device_printf(dev, "Hardware Initialization Failed\n"); 2874 return; 2875 } 2876 if (hw->mac.type >= igb_mac_min) 2877 igb_init_dmac(sc, pba); 2878 2879 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2880 e1000_get_phy_info(hw); 2881 e1000_check_for_link(hw); 2882 } 2883 2884 /* 2885 * Initialise the RSS mapping for NICs that support multiple transmit/ 2886 * receive rings. 2887 */ 2888 2889 #define RSSKEYLEN 10 2890 static void 2891 em_initialize_rss_mapping(struct e1000_softc *sc) 2892 { 2893 uint8_t rss_key[4 * RSSKEYLEN]; 2894 uint32_t reta = 0; 2895 struct e1000_hw *hw = &sc->hw; 2896 int i; 2897 2898 /* 2899 * Configure RSS key 2900 */ 2901 arc4rand(rss_key, sizeof(rss_key), 0); 2902 for (i = 0; i < RSSKEYLEN; ++i) { 2903 uint32_t rssrk = 0; 2904 2905 rssrk = EM_RSSRK_VAL(rss_key, i); 2906 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2907 } 2908 2909 /* 2910 * Configure RSS redirect table in following fashion: 2911 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2912 */ 2913 for (i = 0; i < sizeof(reta); ++i) { 2914 uint32_t q; 2915 2916 q = (i % sc->rx_num_queues) << 7; 2917 reta |= q << (8 * i); 2918 } 2919 2920 for (i = 0; i < 32; ++i) 2921 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2922 2923 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2924 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2925 E1000_MRQC_RSS_FIELD_IPV4 | 2926 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2927 E1000_MRQC_RSS_FIELD_IPV6_EX | 2928 E1000_MRQC_RSS_FIELD_IPV6); 2929 } 2930 2931 static void 2932 igb_initialize_rss_mapping(struct e1000_softc *sc) 2933 { 2934 struct e1000_hw *hw = &sc->hw; 2935 int i; 2936 int queue_id; 2937 u32 reta; 2938 u32 rss_key[10], mrqc, shift = 0; 2939 2940 /* XXX? */ 2941 if (hw->mac.type == e1000_82575) 2942 shift = 6; 2943 2944 /* 2945 * The redirection table controls which destination 2946 * queue each bucket redirects traffic to. 2947 * Each DWORD represents four queues, with the LSB 2948 * being the first queue in the DWORD. 2949 * 2950 * This just allocates buckets to queues using round-robin 2951 * allocation. 2952 * 2953 * NOTE: It Just Happens to line up with the default 2954 * RSS allocation method. 2955 */ 2956 2957 /* Warning FM follows */ 2958 reta = 0; 2959 for (i = 0; i < 128; i++) { 2960 #ifdef RSS 2961 queue_id = rss_get_indirection_to_bucket(i); 2962 /* 2963 * If we have more queues than buckets, we'll 2964 * end up mapping buckets to a subset of the 2965 * queues. 2966 * 2967 * If we have more buckets than queues, we'll 2968 * end up instead assigning multiple buckets 2969 * to queues. 2970 * 2971 * Both are suboptimal, but we need to handle 2972 * the case so we don't go out of bounds 2973 * indexing arrays and such. 2974 */ 2975 queue_id = queue_id % sc->rx_num_queues; 2976 #else 2977 queue_id = (i % sc->rx_num_queues); 2978 #endif 2979 /* Adjust if required */ 2980 queue_id = queue_id << shift; 2981 2982 /* 2983 * The low 8 bits are for hash value (n+0); 2984 * The next 8 bits are for hash value (n+1), etc. 2985 */ 2986 reta = reta >> 8; 2987 reta = reta | ( ((uint32_t) queue_id) << 24); 2988 if ((i & 3) == 3) { 2989 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2990 reta = 0; 2991 } 2992 } 2993 2994 /* Now fill in hash table */ 2995 2996 /* 2997 * MRQC: Multiple Receive Queues Command 2998 * Set queuing to RSS control, number depends on the device. 2999 */ 3000 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3001 3002 #ifdef RSS 3003 /* XXX ew typecasting */ 3004 rss_getkey((uint8_t *) &rss_key); 3005 #else 3006 arc4rand(&rss_key, sizeof(rss_key), 0); 3007 #endif 3008 for (i = 0; i < 10; i++) 3009 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3010 3011 /* 3012 * Configure the RSS fields to hash upon. 3013 */ 3014 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3015 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3016 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3017 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3018 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3019 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3020 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3021 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3022 3023 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3024 } 3025 3026 /********************************************************************* 3027 * 3028 * Setup networking device structure and register interface media. 3029 * 3030 **********************************************************************/ 3031 static int 3032 em_setup_interface(if_ctx_t ctx) 3033 { 3034 if_t ifp = iflib_get_ifp(ctx); 3035 struct e1000_softc *sc = iflib_get_softc(ctx); 3036 if_softc_ctx_t scctx = sc->shared; 3037 3038 INIT_DEBUGOUT("em_setup_interface: begin"); 3039 3040 /* Single Queue */ 3041 if (sc->tx_num_queues == 1) { 3042 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3043 if_setsendqready(ifp); 3044 } 3045 3046 /* 3047 * Specify the media types supported by this adapter and register 3048 * callbacks to update media and link information 3049 */ 3050 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3051 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3052 u_char fiber_type = IFM_1000_SX; /* default type */ 3053 3054 if (sc->hw.mac.type == e1000_82545) 3055 fiber_type = IFM_1000_LX; 3056 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3057 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3058 } else { 3059 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3060 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3061 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3062 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3063 if (sc->hw.phy.type != e1000_phy_ife) { 3064 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3065 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3066 } 3067 } 3068 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3069 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3070 return (0); 3071 } 3072 3073 static int 3074 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3075 { 3076 struct e1000_softc *sc = iflib_get_softc(ctx); 3077 if_softc_ctx_t scctx = sc->shared; 3078 int error = E1000_SUCCESS; 3079 struct em_tx_queue *que; 3080 int i, j; 3081 3082 MPASS(sc->tx_num_queues > 0); 3083 MPASS(sc->tx_num_queues == ntxqsets); 3084 3085 /* First allocate the top level queue structs */ 3086 if (!(sc->tx_queues = 3087 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3088 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3089 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3090 return(ENOMEM); 3091 } 3092 3093 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3094 /* Set up some basics */ 3095 3096 struct tx_ring *txr = &que->txr; 3097 txr->sc = que->sc = sc; 3098 que->me = txr->me = i; 3099 3100 /* Allocate report status array */ 3101 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3102 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3103 error = ENOMEM; 3104 goto fail; 3105 } 3106 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3107 txr->tx_rsq[j] = QIDX_INVALID; 3108 /* get the virtual and physical address of the hardware queues */ 3109 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3110 txr->tx_paddr = paddrs[i*ntxqs]; 3111 } 3112 3113 if (bootverbose) 3114 device_printf(iflib_get_dev(ctx), 3115 "allocated for %d tx_queues\n", sc->tx_num_queues); 3116 return (0); 3117 fail: 3118 em_if_queues_free(ctx); 3119 return (error); 3120 } 3121 3122 static int 3123 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3124 { 3125 struct e1000_softc *sc = iflib_get_softc(ctx); 3126 int error = E1000_SUCCESS; 3127 struct em_rx_queue *que; 3128 int i; 3129 3130 MPASS(sc->rx_num_queues > 0); 3131 MPASS(sc->rx_num_queues == nrxqsets); 3132 3133 /* First allocate the top level queue structs */ 3134 if (!(sc->rx_queues = 3135 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3136 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3137 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3138 error = ENOMEM; 3139 goto fail; 3140 } 3141 3142 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3143 /* Set up some basics */ 3144 struct rx_ring *rxr = &que->rxr; 3145 rxr->sc = que->sc = sc; 3146 rxr->que = que; 3147 que->me = rxr->me = i; 3148 3149 /* get the virtual and physical address of the hardware queues */ 3150 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3151 rxr->rx_paddr = paddrs[i*nrxqs]; 3152 } 3153 3154 if (bootverbose) 3155 device_printf(iflib_get_dev(ctx), 3156 "allocated for %d rx_queues\n", sc->rx_num_queues); 3157 3158 return (0); 3159 fail: 3160 em_if_queues_free(ctx); 3161 return (error); 3162 } 3163 3164 static void 3165 em_if_queues_free(if_ctx_t ctx) 3166 { 3167 struct e1000_softc *sc = iflib_get_softc(ctx); 3168 struct em_tx_queue *tx_que = sc->tx_queues; 3169 struct em_rx_queue *rx_que = sc->rx_queues; 3170 3171 if (tx_que != NULL) { 3172 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3173 struct tx_ring *txr = &tx_que->txr; 3174 if (txr->tx_rsq == NULL) 3175 break; 3176 3177 free(txr->tx_rsq, M_DEVBUF); 3178 txr->tx_rsq = NULL; 3179 } 3180 free(sc->tx_queues, M_DEVBUF); 3181 sc->tx_queues = NULL; 3182 } 3183 3184 if (rx_que != NULL) { 3185 free(sc->rx_queues, M_DEVBUF); 3186 sc->rx_queues = NULL; 3187 } 3188 } 3189 3190 /********************************************************************* 3191 * 3192 * Enable transmit unit. 3193 * 3194 **********************************************************************/ 3195 static void 3196 em_initialize_transmit_unit(if_ctx_t ctx) 3197 { 3198 struct e1000_softc *sc = iflib_get_softc(ctx); 3199 if_softc_ctx_t scctx = sc->shared; 3200 struct em_tx_queue *que; 3201 struct tx_ring *txr; 3202 struct e1000_hw *hw = &sc->hw; 3203 u32 tctl, txdctl = 0, tarc, tipg = 0; 3204 3205 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3206 3207 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3208 u64 bus_addr; 3209 caddr_t offp, endp; 3210 3211 que = &sc->tx_queues[i]; 3212 txr = &que->txr; 3213 bus_addr = txr->tx_paddr; 3214 3215 /* Clear checksum offload context. */ 3216 offp = (caddr_t)&txr->csum_flags; 3217 endp = (caddr_t)(txr + 1); 3218 bzero(offp, endp - offp); 3219 3220 /* Base and Len of TX Ring */ 3221 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3222 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3223 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3224 (u32)(bus_addr >> 32)); 3225 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3226 (u32)bus_addr); 3227 /* Init the HEAD/TAIL indices */ 3228 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3229 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3230 3231 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3232 E1000_READ_REG(hw, E1000_TDBAL(i)), 3233 E1000_READ_REG(hw, E1000_TDLEN(i))); 3234 3235 txdctl = 0; /* clear txdctl */ 3236 txdctl |= 0x1f; /* PTHRESH */ 3237 txdctl |= 1 << 8; /* HTHRESH */ 3238 txdctl |= 1 << 16;/* WTHRESH */ 3239 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3240 txdctl |= E1000_TXDCTL_GRAN; 3241 txdctl |= 1 << 25; /* LWTHRESH */ 3242 3243 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3244 } 3245 3246 /* Set the default values for the Tx Inter Packet Gap timer */ 3247 switch (hw->mac.type) { 3248 case e1000_80003es2lan: 3249 tipg = DEFAULT_82543_TIPG_IPGR1; 3250 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3251 E1000_TIPG_IPGR2_SHIFT; 3252 break; 3253 case e1000_82542: 3254 tipg = DEFAULT_82542_TIPG_IPGT; 3255 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3256 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3257 break; 3258 default: 3259 if (hw->phy.media_type == e1000_media_type_fiber || 3260 hw->phy.media_type == e1000_media_type_internal_serdes) 3261 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3262 else 3263 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3264 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3265 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3266 } 3267 3268 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3269 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3270 3271 if(hw->mac.type >= e1000_82540) 3272 E1000_WRITE_REG(hw, E1000_TADV, 3273 sc->tx_abs_int_delay.value); 3274 3275 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3276 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3277 tarc |= TARC_SPEED_MODE_BIT; 3278 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3279 } else if (hw->mac.type == e1000_80003es2lan) { 3280 /* errata: program both queues to unweighted RR */ 3281 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3282 tarc |= 1; 3283 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3284 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3285 tarc |= 1; 3286 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3287 } else if (hw->mac.type == e1000_82574) { 3288 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3289 tarc |= TARC_ERRATA_BIT; 3290 if ( sc->tx_num_queues > 1) { 3291 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3292 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3293 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3294 } else 3295 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3296 } 3297 3298 if (sc->tx_int_delay.value > 0) 3299 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3300 3301 /* Program the Transmit Control Register */ 3302 tctl = E1000_READ_REG(hw, E1000_TCTL); 3303 tctl &= ~E1000_TCTL_CT; 3304 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3305 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3306 3307 if (hw->mac.type >= e1000_82571) 3308 tctl |= E1000_TCTL_MULR; 3309 3310 /* This write will effectively turn on the transmit unit. */ 3311 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3312 3313 /* SPT and KBL errata workarounds */ 3314 if (hw->mac.type == e1000_pch_spt) { 3315 u32 reg; 3316 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3317 reg |= E1000_RCTL_RDMTS_HEX; 3318 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3319 /* i218-i219 Specification Update 1.5.4.5 */ 3320 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3321 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3322 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3323 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3324 } 3325 } 3326 3327 /********************************************************************* 3328 * 3329 * Enable receive unit. 3330 * 3331 **********************************************************************/ 3332 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3333 3334 static void 3335 em_initialize_receive_unit(if_ctx_t ctx) 3336 { 3337 struct e1000_softc *sc = iflib_get_softc(ctx); 3338 if_softc_ctx_t scctx = sc->shared; 3339 if_t ifp = iflib_get_ifp(ctx); 3340 struct e1000_hw *hw = &sc->hw; 3341 struct em_rx_queue *que; 3342 int i; 3343 uint32_t rctl, rxcsum; 3344 3345 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3346 3347 /* 3348 * Make sure receives are disabled while setting 3349 * up the descriptor ring 3350 */ 3351 rctl = E1000_READ_REG(hw, E1000_RCTL); 3352 /* Do not disable if ever enabled on this hardware */ 3353 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3354 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3355 3356 /* Setup the Receive Control Register */ 3357 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3358 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3359 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3360 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3361 3362 /* Do not store bad packets */ 3363 rctl &= ~E1000_RCTL_SBP; 3364 3365 /* Enable Long Packet receive */ 3366 if (if_getmtu(ifp) > ETHERMTU) 3367 rctl |= E1000_RCTL_LPE; 3368 else 3369 rctl &= ~E1000_RCTL_LPE; 3370 3371 /* Strip the CRC */ 3372 if (!em_disable_crc_stripping) 3373 rctl |= E1000_RCTL_SECRC; 3374 3375 if (hw->mac.type >= e1000_82540) { 3376 E1000_WRITE_REG(hw, E1000_RADV, 3377 sc->rx_abs_int_delay.value); 3378 3379 /* 3380 * Set the interrupt throttling rate. Value is calculated 3381 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3382 */ 3383 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3384 } 3385 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3386 3387 if (hw->mac.type >= em_mac_min) { 3388 uint32_t rfctl; 3389 /* Use extended rx descriptor formats */ 3390 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3391 rfctl |= E1000_RFCTL_EXTEN; 3392 3393 /* 3394 * When using MSI-X interrupts we need to throttle 3395 * using the EITR register (82574 only) 3396 */ 3397 if (hw->mac.type == e1000_82574) { 3398 for (int i = 0; i < 4; i++) 3399 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3400 DEFAULT_ITR); 3401 /* Disable accelerated acknowledge */ 3402 rfctl |= E1000_RFCTL_ACK_DIS; 3403 } 3404 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3405 } 3406 3407 /* Set up L3 and L4 csum Rx descriptor offloads */ 3408 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3409 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3410 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3411 if (hw->mac.type > e1000_82575) 3412 rxcsum |= E1000_RXCSUM_CRCOFL; 3413 else if (hw->mac.type < em_mac_min && 3414 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3415 rxcsum |= E1000_RXCSUM_IPV6OFL; 3416 } else { 3417 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3418 if (hw->mac.type > e1000_82575) 3419 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3420 else if (hw->mac.type < em_mac_min) 3421 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3422 } 3423 3424 if (sc->rx_num_queues > 1) { 3425 /* RSS hash needed in the Rx descriptor */ 3426 rxcsum |= E1000_RXCSUM_PCSD; 3427 3428 if (hw->mac.type >= igb_mac_min) 3429 igb_initialize_rss_mapping(sc); 3430 else 3431 em_initialize_rss_mapping(sc); 3432 } 3433 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3434 3435 /* 3436 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3437 * long latencies are observed, like Lenovo X60. This 3438 * change eliminates the problem, but since having positive 3439 * values in RDTR is a known source of problems on other 3440 * platforms another solution is being sought. 3441 */ 3442 if (hw->mac.type == e1000_82573) 3443 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3444 3445 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3446 struct rx_ring *rxr = &que->rxr; 3447 /* Setup the Base and Length of the Rx Descriptor Ring */ 3448 u64 bus_addr = rxr->rx_paddr; 3449 #if 0 3450 u32 rdt = sc->rx_num_queues -1; /* default */ 3451 #endif 3452 3453 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3454 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3455 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3456 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3457 /* Setup the Head and Tail Descriptor Pointers */ 3458 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3459 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3460 } 3461 3462 /* 3463 * Set PTHRESH for improved jumbo performance 3464 * According to 10.2.5.11 of Intel 82574 Datasheet, 3465 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3466 * Only write to RXDCTL(1) if there is a need for different 3467 * settings. 3468 */ 3469 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3470 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3471 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3472 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3473 } else if (hw->mac.type == e1000_82574) { 3474 for (int i = 0; i < sc->rx_num_queues; i++) { 3475 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3476 rxdctl |= 0x20; /* PTHRESH */ 3477 rxdctl |= 4 << 8; /* HTHRESH */ 3478 rxdctl |= 4 << 16;/* WTHRESH */ 3479 rxdctl |= 1 << 24; /* Switch to granularity */ 3480 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3481 } 3482 } else if (hw->mac.type >= igb_mac_min) { 3483 u32 psize, srrctl = 0; 3484 3485 if (if_getmtu(ifp) > ETHERMTU) { 3486 psize = scctx->isc_max_frame_size; 3487 /* are we on a vlan? */ 3488 if (if_vlantrunkinuse(ifp)) 3489 psize += VLAN_TAG_SIZE; 3490 3491 if (sc->vf_ifp) 3492 e1000_rlpml_set_vf(hw, psize); 3493 else 3494 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3495 } 3496 3497 /* Set maximum packet buffer len */ 3498 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3499 E1000_SRRCTL_BSIZEPKT_SHIFT; 3500 3501 /* 3502 * If TX flow control is disabled and there's >1 queue defined, 3503 * enable DROP. 3504 * 3505 * This drops frames rather than hanging the RX MAC for all queues. 3506 */ 3507 if ((sc->rx_num_queues > 1) && 3508 (sc->fc == e1000_fc_none || 3509 sc->fc == e1000_fc_rx_pause)) { 3510 srrctl |= E1000_SRRCTL_DROP_EN; 3511 } 3512 /* Setup the Base and Length of the Rx Descriptor Rings */ 3513 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3514 struct rx_ring *rxr = &que->rxr; 3515 u64 bus_addr = rxr->rx_paddr; 3516 u32 rxdctl; 3517 3518 #ifdef notyet 3519 /* Configure for header split? -- ignore for now */ 3520 rxr->hdr_split = igb_header_split; 3521 #else 3522 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3523 #endif 3524 3525 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3526 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3527 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3528 (uint32_t)(bus_addr >> 32)); 3529 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3530 (uint32_t)bus_addr); 3531 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3532 /* Enable this Queue */ 3533 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3534 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3535 rxdctl &= 0xFFF00000; 3536 rxdctl |= IGB_RX_PTHRESH; 3537 rxdctl |= IGB_RX_HTHRESH << 8; 3538 rxdctl |= IGB_RX_WTHRESH << 16; 3539 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3540 } 3541 } else if (hw->mac.type >= e1000_pch2lan) { 3542 if (if_getmtu(ifp) > ETHERMTU) 3543 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3544 else 3545 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3546 } 3547 3548 /* Make sure VLAN Filters are off */ 3549 rctl &= ~E1000_RCTL_VFE; 3550 3551 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3552 if (hw->mac.type < igb_mac_min) { 3553 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3554 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3555 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3556 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3557 else if (sc->rx_mbuf_sz > 8192) 3558 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3559 else { 3560 rctl |= E1000_RCTL_SZ_2048; 3561 rctl &= ~E1000_RCTL_BSEX; 3562 } 3563 } else 3564 rctl |= E1000_RCTL_SZ_2048; 3565 3566 /* 3567 * rctl bits 11:10 are as follows 3568 * lem: reserved 3569 * em: DTYPE 3570 * igb: reserved 3571 * and should be 00 on all of the above 3572 */ 3573 rctl &= ~0x00000C00; 3574 3575 /* Write out the settings */ 3576 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3577 3578 return; 3579 } 3580 3581 static void 3582 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3583 { 3584 struct e1000_softc *sc = iflib_get_softc(ctx); 3585 u32 index, bit; 3586 3587 index = (vtag >> 5) & 0x7F; 3588 bit = vtag & 0x1F; 3589 sc->shadow_vfta[index] |= (1 << bit); 3590 ++sc->num_vlans; 3591 em_if_vlan_filter_write(sc); 3592 } 3593 3594 static void 3595 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3596 { 3597 struct e1000_softc *sc = iflib_get_softc(ctx); 3598 u32 index, bit; 3599 3600 index = (vtag >> 5) & 0x7F; 3601 bit = vtag & 0x1F; 3602 sc->shadow_vfta[index] &= ~(1 << bit); 3603 --sc->num_vlans; 3604 em_if_vlan_filter_write(sc); 3605 } 3606 3607 static bool 3608 em_if_vlan_filter_capable(if_ctx_t ctx) 3609 { 3610 if_t ifp = iflib_get_ifp(ctx); 3611 3612 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3613 !em_disable_crc_stripping) 3614 return (true); 3615 3616 return (false); 3617 } 3618 3619 static bool 3620 em_if_vlan_filter_used(if_ctx_t ctx) 3621 { 3622 struct e1000_softc *sc = iflib_get_softc(ctx); 3623 3624 if (!em_if_vlan_filter_capable(ctx)) 3625 return (false); 3626 3627 for (int i = 0; i < EM_VFTA_SIZE; i++) 3628 if (sc->shadow_vfta[i] != 0) 3629 return (true); 3630 3631 return (false); 3632 } 3633 3634 static void 3635 em_if_vlan_filter_enable(struct e1000_softc *sc) 3636 { 3637 struct e1000_hw *hw = &sc->hw; 3638 u32 reg; 3639 3640 reg = E1000_READ_REG(hw, E1000_RCTL); 3641 reg &= ~E1000_RCTL_CFIEN; 3642 reg |= E1000_RCTL_VFE; 3643 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3644 } 3645 3646 static void 3647 em_if_vlan_filter_disable(struct e1000_softc *sc) 3648 { 3649 struct e1000_hw *hw = &sc->hw; 3650 u32 reg; 3651 3652 reg = E1000_READ_REG(hw, E1000_RCTL); 3653 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3654 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3655 } 3656 3657 static void 3658 em_if_vlan_filter_write(struct e1000_softc *sc) 3659 { 3660 struct e1000_hw *hw = &sc->hw; 3661 3662 if (sc->vf_ifp) 3663 return; 3664 3665 /* Disable interrupts for lem-class devices during the filter change */ 3666 if (hw->mac.type < em_mac_min) 3667 em_if_intr_disable(sc->ctx); 3668 3669 for (int i = 0; i < EM_VFTA_SIZE; i++) 3670 if (sc->shadow_vfta[i] != 0) { 3671 /* XXXKB: incomplete VF support, we return early above */ 3672 if (sc->vf_ifp) 3673 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3674 else 3675 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3676 } 3677 3678 /* Re-enable interrupts for lem-class devices */ 3679 if (hw->mac.type < em_mac_min) 3680 em_if_intr_enable(sc->ctx); 3681 } 3682 3683 static void 3684 em_setup_vlan_hw_support(if_ctx_t ctx) 3685 { 3686 struct e1000_softc *sc = iflib_get_softc(ctx); 3687 struct e1000_hw *hw = &sc->hw; 3688 if_t ifp = iflib_get_ifp(ctx); 3689 u32 reg; 3690 3691 /* XXXKB: Return early if we are a VF until VF decap and filter management 3692 * is ready and tested. 3693 */ 3694 if (sc->vf_ifp) 3695 return; 3696 3697 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3698 !em_disable_crc_stripping) { 3699 reg = E1000_READ_REG(hw, E1000_CTRL); 3700 reg |= E1000_CTRL_VME; 3701 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3702 } else { 3703 reg = E1000_READ_REG(hw, E1000_CTRL); 3704 reg &= ~E1000_CTRL_VME; 3705 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3706 } 3707 3708 /* If we aren't doing HW filtering, we're done */ 3709 if (!em_if_vlan_filter_capable(ctx)) { 3710 em_if_vlan_filter_disable(sc); 3711 return; 3712 } 3713 3714 /* 3715 * A soft reset zero's out the VFTA, so 3716 * we need to repopulate it now. 3717 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3718 * traffic through. This will write the entire table. 3719 */ 3720 em_if_vlan_register(ctx, 0); 3721 3722 /* Enable the Filter Table */ 3723 em_if_vlan_filter_enable(sc); 3724 } 3725 3726 static void 3727 em_if_intr_enable(if_ctx_t ctx) 3728 { 3729 struct e1000_softc *sc = iflib_get_softc(ctx); 3730 struct e1000_hw *hw = &sc->hw; 3731 u32 ims_mask = IMS_ENABLE_MASK; 3732 3733 if (sc->intr_type == IFLIB_INTR_MSIX) { 3734 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3735 ims_mask |= sc->ims; 3736 } 3737 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3738 E1000_WRITE_FLUSH(hw); 3739 } 3740 3741 static void 3742 em_if_intr_disable(if_ctx_t ctx) 3743 { 3744 struct e1000_softc *sc = iflib_get_softc(ctx); 3745 struct e1000_hw *hw = &sc->hw; 3746 3747 if (sc->intr_type == IFLIB_INTR_MSIX) 3748 E1000_WRITE_REG(hw, EM_EIAC, 0); 3749 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3750 E1000_WRITE_FLUSH(hw); 3751 } 3752 3753 static void 3754 igb_if_intr_enable(if_ctx_t ctx) 3755 { 3756 struct e1000_softc *sc = iflib_get_softc(ctx); 3757 struct e1000_hw *hw = &sc->hw; 3758 u32 mask; 3759 3760 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3761 mask = (sc->que_mask | sc->link_mask); 3762 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3763 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3764 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3765 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3766 } else 3767 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3768 E1000_WRITE_FLUSH(hw); 3769 } 3770 3771 static void 3772 igb_if_intr_disable(if_ctx_t ctx) 3773 { 3774 struct e1000_softc *sc = iflib_get_softc(ctx); 3775 struct e1000_hw *hw = &sc->hw; 3776 3777 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3778 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3779 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3780 } 3781 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3782 E1000_WRITE_FLUSH(hw); 3783 } 3784 3785 /* 3786 * Bit of a misnomer, what this really means is 3787 * to enable OS management of the system... aka 3788 * to disable special hardware management features 3789 */ 3790 static void 3791 em_init_manageability(struct e1000_softc *sc) 3792 { 3793 /* A shared code workaround */ 3794 #define E1000_82542_MANC2H E1000_MANC2H 3795 if (sc->has_manage) { 3796 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3797 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3798 3799 /* disable hardware interception of ARP */ 3800 manc &= ~(E1000_MANC_ARP_EN); 3801 3802 /* enable receiving management packets to the host */ 3803 manc |= E1000_MANC_EN_MNG2HOST; 3804 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3805 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3806 manc2h |= E1000_MNG2HOST_PORT_623; 3807 manc2h |= E1000_MNG2HOST_PORT_664; 3808 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3809 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3810 } 3811 } 3812 3813 /* 3814 * Give control back to hardware management 3815 * controller if there is one. 3816 */ 3817 static void 3818 em_release_manageability(struct e1000_softc *sc) 3819 { 3820 if (sc->has_manage) { 3821 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3822 3823 /* re-enable hardware interception of ARP */ 3824 manc |= E1000_MANC_ARP_EN; 3825 manc &= ~E1000_MANC_EN_MNG2HOST; 3826 3827 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3828 } 3829 } 3830 3831 /* 3832 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3833 * For ASF and Pass Through versions of f/w this means 3834 * that the driver is loaded. For AMT version type f/w 3835 * this means that the network i/f is open. 3836 */ 3837 static void 3838 em_get_hw_control(struct e1000_softc *sc) 3839 { 3840 u32 ctrl_ext, swsm; 3841 3842 if (sc->vf_ifp) 3843 return; 3844 3845 if (sc->hw.mac.type == e1000_82573) { 3846 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3847 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3848 swsm | E1000_SWSM_DRV_LOAD); 3849 return; 3850 } 3851 /* else */ 3852 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3853 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3854 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3855 } 3856 3857 /* 3858 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3859 * For ASF and Pass Through versions of f/w this means that 3860 * the driver is no longer loaded. For AMT versions of the 3861 * f/w this means that the network i/f is closed. 3862 */ 3863 static void 3864 em_release_hw_control(struct e1000_softc *sc) 3865 { 3866 u32 ctrl_ext, swsm; 3867 3868 if (!sc->has_manage) 3869 return; 3870 3871 if (sc->hw.mac.type == e1000_82573) { 3872 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3873 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3874 swsm & ~E1000_SWSM_DRV_LOAD); 3875 return; 3876 } 3877 /* else */ 3878 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3879 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3880 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3881 return; 3882 } 3883 3884 static int 3885 em_is_valid_ether_addr(u8 *addr) 3886 { 3887 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3888 3889 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3890 return (false); 3891 } 3892 3893 return (true); 3894 } 3895 3896 static bool 3897 em_automask_tso(if_ctx_t ctx) 3898 { 3899 struct e1000_softc *sc = iflib_get_softc(ctx); 3900 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 3901 if_t ifp = iflib_get_ifp(ctx); 3902 3903 if (!em_unsupported_tso && sc->link_speed && 3904 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 3905 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 3906 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 3907 scctx->isc_capenable &= ~IFCAP_TSO; 3908 if_setcapenablebit(ifp, 0, IFCAP_TSO); 3909 /* iflib_init_locked handles ifnet hwassistbits */ 3910 iflib_request_reset(ctx); 3911 return true; 3912 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 3913 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 3914 scctx->isc_capenable |= sc->tso_automasked; 3915 if_setcapenablebit(ifp, sc->tso_automasked, 0); 3916 sc->tso_automasked = 0; 3917 /* iflib_init_locked handles ifnet hwassistbits */ 3918 iflib_request_reset(ctx); 3919 return true; 3920 } 3921 3922 return false; 3923 } 3924 3925 /* 3926 ** Parse the interface capabilities with regard 3927 ** to both system management and wake-on-lan for 3928 ** later use. 3929 */ 3930 static void 3931 em_get_wakeup(if_ctx_t ctx) 3932 { 3933 struct e1000_softc *sc = iflib_get_softc(ctx); 3934 device_t dev = iflib_get_dev(ctx); 3935 u16 eeprom_data = 0, device_id, apme_mask; 3936 3937 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3938 apme_mask = EM_EEPROM_APME; 3939 3940 switch (sc->hw.mac.type) { 3941 case e1000_82542: 3942 case e1000_82543: 3943 break; 3944 case e1000_82544: 3945 e1000_read_nvm(&sc->hw, 3946 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3947 apme_mask = EM_82544_APME; 3948 break; 3949 case e1000_82546: 3950 case e1000_82546_rev_3: 3951 if (sc->hw.bus.func == 1) { 3952 e1000_read_nvm(&sc->hw, 3953 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3954 break; 3955 } else 3956 e1000_read_nvm(&sc->hw, 3957 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3958 break; 3959 case e1000_82573: 3960 case e1000_82583: 3961 sc->has_amt = true; 3962 /* FALLTHROUGH */ 3963 case e1000_82571: 3964 case e1000_82572: 3965 case e1000_80003es2lan: 3966 if (sc->hw.bus.func == 1) { 3967 e1000_read_nvm(&sc->hw, 3968 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3969 break; 3970 } else 3971 e1000_read_nvm(&sc->hw, 3972 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3973 break; 3974 case e1000_ich8lan: 3975 case e1000_ich9lan: 3976 case e1000_ich10lan: 3977 case e1000_pchlan: 3978 case e1000_pch2lan: 3979 case e1000_pch_lpt: 3980 case e1000_pch_spt: 3981 case e1000_82575: /* listing all igb devices */ 3982 case e1000_82576: 3983 case e1000_82580: 3984 case e1000_i350: 3985 case e1000_i354: 3986 case e1000_i210: 3987 case e1000_i211: 3988 case e1000_vfadapt: 3989 case e1000_vfadapt_i350: 3990 apme_mask = E1000_WUC_APME; 3991 sc->has_amt = true; 3992 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3993 break; 3994 default: 3995 e1000_read_nvm(&sc->hw, 3996 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3997 break; 3998 } 3999 if (eeprom_data & apme_mask) 4000 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4001 /* 4002 * We have the eeprom settings, now apply the special cases 4003 * where the eeprom may be wrong or the board won't support 4004 * wake on lan on a particular port 4005 */ 4006 device_id = pci_get_device(dev); 4007 switch (device_id) { 4008 case E1000_DEV_ID_82546GB_PCIE: 4009 sc->wol = 0; 4010 break; 4011 case E1000_DEV_ID_82546EB_FIBER: 4012 case E1000_DEV_ID_82546GB_FIBER: 4013 /* Wake events only supported on port A for dual fiber 4014 * regardless of eeprom setting */ 4015 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4016 E1000_STATUS_FUNC_1) 4017 sc->wol = 0; 4018 break; 4019 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4020 /* if quad port adapter, disable WoL on all but port A */ 4021 if (global_quad_port_a != 0) 4022 sc->wol = 0; 4023 /* Reset for multiple quad port adapters */ 4024 if (++global_quad_port_a == 4) 4025 global_quad_port_a = 0; 4026 break; 4027 case E1000_DEV_ID_82571EB_FIBER: 4028 /* Wake events only supported on port A for dual fiber 4029 * regardless of eeprom setting */ 4030 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4031 E1000_STATUS_FUNC_1) 4032 sc->wol = 0; 4033 break; 4034 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4035 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4036 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4037 /* if quad port adapter, disable WoL on all but port A */ 4038 if (global_quad_port_a != 0) 4039 sc->wol = 0; 4040 /* Reset for multiple quad port adapters */ 4041 if (++global_quad_port_a == 4) 4042 global_quad_port_a = 0; 4043 break; 4044 } 4045 return; 4046 } 4047 4048 4049 /* 4050 * Enable PCI Wake On Lan capability 4051 */ 4052 static void 4053 em_enable_wakeup(if_ctx_t ctx) 4054 { 4055 struct e1000_softc *sc = iflib_get_softc(ctx); 4056 device_t dev = iflib_get_dev(ctx); 4057 if_t ifp = iflib_get_ifp(ctx); 4058 int error = 0; 4059 u32 pmc, ctrl, ctrl_ext, rctl; 4060 u16 status; 4061 4062 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4063 return; 4064 4065 /* 4066 * Determine type of Wakeup: note that wol 4067 * is set with all bits on by default. 4068 */ 4069 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4070 sc->wol &= ~E1000_WUFC_MAG; 4071 4072 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4073 sc->wol &= ~E1000_WUFC_EX; 4074 4075 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4076 sc->wol &= ~E1000_WUFC_MC; 4077 else { 4078 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4079 rctl |= E1000_RCTL_MPE; 4080 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4081 } 4082 4083 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4084 goto pme; 4085 4086 /* Advertise the wakeup capability */ 4087 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4088 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4089 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4090 4091 /* Keep the laser running on Fiber adapters */ 4092 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4093 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4094 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4095 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4096 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4097 } 4098 4099 if ((sc->hw.mac.type == e1000_ich8lan) || 4100 (sc->hw.mac.type == e1000_pchlan) || 4101 (sc->hw.mac.type == e1000_ich9lan) || 4102 (sc->hw.mac.type == e1000_ich10lan)) 4103 e1000_suspend_workarounds_ich8lan(&sc->hw); 4104 4105 if ( sc->hw.mac.type >= e1000_pchlan) { 4106 error = em_enable_phy_wakeup(sc); 4107 if (error) 4108 goto pme; 4109 } else { 4110 /* Enable wakeup by the MAC */ 4111 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4112 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4113 } 4114 4115 if (sc->hw.phy.type == e1000_phy_igp_3) 4116 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4117 4118 pme: 4119 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4120 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4121 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4122 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4123 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4124 4125 return; 4126 } 4127 4128 /* 4129 * WOL in the newer chipset interfaces (pchlan) 4130 * require thing to be copied into the phy 4131 */ 4132 static int 4133 em_enable_phy_wakeup(struct e1000_softc *sc) 4134 { 4135 struct e1000_hw *hw = &sc->hw; 4136 u32 mreg, ret = 0; 4137 u16 preg; 4138 4139 /* copy MAC RARs to PHY RARs */ 4140 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4141 4142 /* copy MAC MTA to PHY MTA */ 4143 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4144 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4145 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4146 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4147 (u16)((mreg >> 16) & 0xFFFF)); 4148 } 4149 4150 /* configure PHY Rx Control register */ 4151 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4152 mreg = E1000_READ_REG(hw, E1000_RCTL); 4153 if (mreg & E1000_RCTL_UPE) 4154 preg |= BM_RCTL_UPE; 4155 if (mreg & E1000_RCTL_MPE) 4156 preg |= BM_RCTL_MPE; 4157 preg &= ~(BM_RCTL_MO_MASK); 4158 if (mreg & E1000_RCTL_MO_3) 4159 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4160 << BM_RCTL_MO_SHIFT); 4161 if (mreg & E1000_RCTL_BAM) 4162 preg |= BM_RCTL_BAM; 4163 if (mreg & E1000_RCTL_PMCF) 4164 preg |= BM_RCTL_PMCF; 4165 mreg = E1000_READ_REG(hw, E1000_CTRL); 4166 if (mreg & E1000_CTRL_RFCE) 4167 preg |= BM_RCTL_RFCE; 4168 e1000_write_phy_reg(hw, BM_RCTL, preg); 4169 4170 /* enable PHY wakeup in MAC register */ 4171 E1000_WRITE_REG(hw, E1000_WUC, 4172 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4173 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4174 4175 /* configure and enable PHY wakeup in PHY registers */ 4176 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4177 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4178 4179 /* activate PHY wakeup */ 4180 ret = hw->phy.ops.acquire(hw); 4181 if (ret) { 4182 printf("Could not acquire PHY\n"); 4183 return ret; 4184 } 4185 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4186 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4187 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4188 if (ret) { 4189 printf("Could not read PHY page 769\n"); 4190 goto out; 4191 } 4192 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4193 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4194 if (ret) 4195 printf("Could not set PHY Host Wakeup bit\n"); 4196 out: 4197 hw->phy.ops.release(hw); 4198 4199 return ret; 4200 } 4201 4202 static void 4203 em_if_led_func(if_ctx_t ctx, int onoff) 4204 { 4205 struct e1000_softc *sc = iflib_get_softc(ctx); 4206 4207 if (onoff) { 4208 e1000_setup_led(&sc->hw); 4209 e1000_led_on(&sc->hw); 4210 } else { 4211 e1000_led_off(&sc->hw); 4212 e1000_cleanup_led(&sc->hw); 4213 } 4214 } 4215 4216 /* 4217 * Disable the L0S and L1 LINK states 4218 */ 4219 static void 4220 em_disable_aspm(struct e1000_softc *sc) 4221 { 4222 int base, reg; 4223 u16 link_cap,link_ctrl; 4224 device_t dev = sc->dev; 4225 4226 switch (sc->hw.mac.type) { 4227 case e1000_82573: 4228 case e1000_82574: 4229 case e1000_82583: 4230 break; 4231 default: 4232 return; 4233 } 4234 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4235 return; 4236 reg = base + PCIER_LINK_CAP; 4237 link_cap = pci_read_config(dev, reg, 2); 4238 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4239 return; 4240 reg = base + PCIER_LINK_CTL; 4241 link_ctrl = pci_read_config(dev, reg, 2); 4242 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4243 pci_write_config(dev, reg, link_ctrl, 2); 4244 return; 4245 } 4246 4247 /********************************************************************** 4248 * 4249 * Update the board statistics counters. 4250 * 4251 **********************************************************************/ 4252 static void 4253 em_update_stats_counters(struct e1000_softc *sc) 4254 { 4255 u64 prev_xoffrxc = sc->stats.xoffrxc; 4256 4257 if(sc->hw.phy.media_type == e1000_media_type_copper || 4258 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4259 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4260 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4261 } 4262 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4263 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4264 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4265 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4266 4267 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4268 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4269 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4270 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4271 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4272 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4273 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4274 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4275 /* 4276 ** For watchdog management we need to know if we have been 4277 ** paused during the last interval, so capture that here. 4278 */ 4279 if (sc->stats.xoffrxc != prev_xoffrxc) 4280 sc->shared->isc_pause_frames = 1; 4281 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4282 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4283 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4284 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4285 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4286 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4287 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4288 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4289 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4290 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4291 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4292 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4293 4294 /* For the 64-bit byte counters the low dword must be read first. */ 4295 /* Both registers clear on the read of the high dword */ 4296 4297 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4298 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4299 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4300 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4301 4302 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4303 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4304 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4305 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4306 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4307 4308 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4309 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4310 4311 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4312 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4313 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4314 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4315 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4316 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4317 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4318 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4319 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4320 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4321 4322 /* Interrupt Counts */ 4323 4324 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4325 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4326 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4327 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4328 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4329 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4330 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4331 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4332 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4333 4334 if (sc->hw.mac.type >= e1000_82543) { 4335 sc->stats.algnerrc += 4336 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4337 sc->stats.rxerrc += 4338 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4339 sc->stats.tncrs += 4340 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4341 sc->stats.cexterr += 4342 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4343 sc->stats.tsctc += 4344 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4345 sc->stats.tsctfc += 4346 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4347 } 4348 } 4349 4350 static uint64_t 4351 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4352 { 4353 struct e1000_softc *sc = iflib_get_softc(ctx); 4354 if_t ifp = iflib_get_ifp(ctx); 4355 4356 switch (cnt) { 4357 case IFCOUNTER_COLLISIONS: 4358 return (sc->stats.colc); 4359 case IFCOUNTER_IERRORS: 4360 return (sc->dropped_pkts + sc->stats.rxerrc + 4361 sc->stats.crcerrs + sc->stats.algnerrc + 4362 sc->stats.ruc + sc->stats.roc + 4363 sc->stats.mpc + sc->stats.cexterr); 4364 case IFCOUNTER_OERRORS: 4365 return (sc->stats.ecol + sc->stats.latecol + 4366 sc->watchdog_events); 4367 default: 4368 return (if_get_counter_default(ifp, cnt)); 4369 } 4370 } 4371 4372 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4373 * @ctx: iflib context 4374 * @event: event code to check 4375 * 4376 * Defaults to returning true for unknown events. 4377 * 4378 * @returns true if iflib needs to reinit the interface 4379 */ 4380 static bool 4381 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4382 { 4383 switch (event) { 4384 case IFLIB_RESTART_VLAN_CONFIG: 4385 return (false); 4386 default: 4387 return (true); 4388 } 4389 } 4390 4391 /* Export a single 32-bit register via a read-only sysctl. */ 4392 static int 4393 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4394 { 4395 struct e1000_softc *sc; 4396 u_int val; 4397 4398 sc = oidp->oid_arg1; 4399 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4400 return (sysctl_handle_int(oidp, &val, 0, req)); 4401 } 4402 4403 /* 4404 * Add sysctl variables, one per statistic, to the system. 4405 */ 4406 static void 4407 em_add_hw_stats(struct e1000_softc *sc) 4408 { 4409 device_t dev = iflib_get_dev(sc->ctx); 4410 struct em_tx_queue *tx_que = sc->tx_queues; 4411 struct em_rx_queue *rx_que = sc->rx_queues; 4412 4413 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4414 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4415 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4416 struct e1000_hw_stats *stats = &sc->stats; 4417 4418 struct sysctl_oid *stat_node, *queue_node, *int_node; 4419 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4420 4421 #define QUEUE_NAME_LEN 32 4422 char namebuf[QUEUE_NAME_LEN]; 4423 4424 /* Driver Statistics */ 4425 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4426 CTLFLAG_RD, &sc->dropped_pkts, 4427 "Driver dropped packets"); 4428 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4429 CTLFLAG_RD, &sc->link_irq, 4430 "Link MSI-X IRQ Handled"); 4431 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4432 CTLFLAG_RD, &sc->rx_overruns, 4433 "RX overruns"); 4434 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4435 CTLFLAG_RD, &sc->watchdog_events, 4436 "Watchdog timeouts"); 4437 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4438 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4439 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4440 "Device Control Register"); 4441 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4442 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4443 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4444 "Receiver Control Register"); 4445 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4446 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4447 "Flow Control High Watermark"); 4448 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4449 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4450 "Flow Control Low Watermark"); 4451 4452 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4453 struct tx_ring *txr = &tx_que->txr; 4454 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4455 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4456 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4457 queue_list = SYSCTL_CHILDREN(queue_node); 4458 4459 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4460 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4461 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4462 "Transmit Descriptor Head"); 4463 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4464 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4465 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4466 "Transmit Descriptor Tail"); 4467 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4468 CTLFLAG_RD, &txr->tx_irq, 4469 "Queue MSI-X Transmit Interrupts"); 4470 } 4471 4472 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4473 struct rx_ring *rxr = &rx_que->rxr; 4474 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4475 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4476 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4477 queue_list = SYSCTL_CHILDREN(queue_node); 4478 4479 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4480 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4481 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4482 "Receive Descriptor Head"); 4483 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4484 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4485 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4486 "Receive Descriptor Tail"); 4487 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4488 CTLFLAG_RD, &rxr->rx_irq, 4489 "Queue MSI-X Receive Interrupts"); 4490 } 4491 4492 /* MAC stats get their own sub node */ 4493 4494 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4495 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4496 stat_list = SYSCTL_CHILDREN(stat_node); 4497 4498 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4499 CTLFLAG_RD, &stats->ecol, 4500 "Excessive collisions"); 4501 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4502 CTLFLAG_RD, &stats->scc, 4503 "Single collisions"); 4504 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4505 CTLFLAG_RD, &stats->mcc, 4506 "Multiple collisions"); 4507 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4508 CTLFLAG_RD, &stats->latecol, 4509 "Late collisions"); 4510 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4511 CTLFLAG_RD, &stats->colc, 4512 "Collision Count"); 4513 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4514 CTLFLAG_RD, &sc->stats.symerrs, 4515 "Symbol Errors"); 4516 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4517 CTLFLAG_RD, &sc->stats.sec, 4518 "Sequence Errors"); 4519 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4520 CTLFLAG_RD, &sc->stats.dc, 4521 "Defer Count"); 4522 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4523 CTLFLAG_RD, &sc->stats.mpc, 4524 "Missed Packets"); 4525 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4526 CTLFLAG_RD, &sc->stats.rnbc, 4527 "Receive No Buffers"); 4528 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4529 CTLFLAG_RD, &sc->stats.ruc, 4530 "Receive Undersize"); 4531 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4532 CTLFLAG_RD, &sc->stats.rfc, 4533 "Fragmented Packets Received "); 4534 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4535 CTLFLAG_RD, &sc->stats.roc, 4536 "Oversized Packets Received"); 4537 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4538 CTLFLAG_RD, &sc->stats.rjc, 4539 "Recevied Jabber"); 4540 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4541 CTLFLAG_RD, &sc->stats.rxerrc, 4542 "Receive Errors"); 4543 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4544 CTLFLAG_RD, &sc->stats.crcerrs, 4545 "CRC errors"); 4546 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4547 CTLFLAG_RD, &sc->stats.algnerrc, 4548 "Alignment Errors"); 4549 /* On 82575 these are collision counts */ 4550 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4551 CTLFLAG_RD, &sc->stats.cexterr, 4552 "Collision/Carrier extension errors"); 4553 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4554 CTLFLAG_RD, &sc->stats.xonrxc, 4555 "XON Received"); 4556 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4557 CTLFLAG_RD, &sc->stats.xontxc, 4558 "XON Transmitted"); 4559 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4560 CTLFLAG_RD, &sc->stats.xoffrxc, 4561 "XOFF Received"); 4562 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4563 CTLFLAG_RD, &sc->stats.xofftxc, 4564 "XOFF Transmitted"); 4565 4566 /* Packet Reception Stats */ 4567 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4568 CTLFLAG_RD, &sc->stats.tpr, 4569 "Total Packets Received "); 4570 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4571 CTLFLAG_RD, &sc->stats.gprc, 4572 "Good Packets Received"); 4573 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4574 CTLFLAG_RD, &sc->stats.bprc, 4575 "Broadcast Packets Received"); 4576 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4577 CTLFLAG_RD, &sc->stats.mprc, 4578 "Multicast Packets Received"); 4579 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4580 CTLFLAG_RD, &sc->stats.prc64, 4581 "64 byte frames received "); 4582 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4583 CTLFLAG_RD, &sc->stats.prc127, 4584 "65-127 byte frames received"); 4585 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4586 CTLFLAG_RD, &sc->stats.prc255, 4587 "128-255 byte frames received"); 4588 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4589 CTLFLAG_RD, &sc->stats.prc511, 4590 "256-511 byte frames received"); 4591 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4592 CTLFLAG_RD, &sc->stats.prc1023, 4593 "512-1023 byte frames received"); 4594 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4595 CTLFLAG_RD, &sc->stats.prc1522, 4596 "1023-1522 byte frames received"); 4597 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4598 CTLFLAG_RD, &sc->stats.gorc, 4599 "Good Octets Received"); 4600 4601 /* Packet Transmission Stats */ 4602 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4603 CTLFLAG_RD, &sc->stats.gotc, 4604 "Good Octets Transmitted"); 4605 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4606 CTLFLAG_RD, &sc->stats.tpt, 4607 "Total Packets Transmitted"); 4608 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4609 CTLFLAG_RD, &sc->stats.gptc, 4610 "Good Packets Transmitted"); 4611 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4612 CTLFLAG_RD, &sc->stats.bptc, 4613 "Broadcast Packets Transmitted"); 4614 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4615 CTLFLAG_RD, &sc->stats.mptc, 4616 "Multicast Packets Transmitted"); 4617 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4618 CTLFLAG_RD, &sc->stats.ptc64, 4619 "64 byte frames transmitted "); 4620 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4621 CTLFLAG_RD, &sc->stats.ptc127, 4622 "65-127 byte frames transmitted"); 4623 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4624 CTLFLAG_RD, &sc->stats.ptc255, 4625 "128-255 byte frames transmitted"); 4626 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4627 CTLFLAG_RD, &sc->stats.ptc511, 4628 "256-511 byte frames transmitted"); 4629 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4630 CTLFLAG_RD, &sc->stats.ptc1023, 4631 "512-1023 byte frames transmitted"); 4632 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4633 CTLFLAG_RD, &sc->stats.ptc1522, 4634 "1024-1522 byte frames transmitted"); 4635 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4636 CTLFLAG_RD, &sc->stats.tsctc, 4637 "TSO Contexts Transmitted"); 4638 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4639 CTLFLAG_RD, &sc->stats.tsctfc, 4640 "TSO Contexts Failed"); 4641 4642 4643 /* Interrupt Stats */ 4644 4645 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4646 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4647 int_list = SYSCTL_CHILDREN(int_node); 4648 4649 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4650 CTLFLAG_RD, &sc->stats.iac, 4651 "Interrupt Assertion Count"); 4652 4653 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4654 CTLFLAG_RD, &sc->stats.icrxptc, 4655 "Interrupt Cause Rx Pkt Timer Expire Count"); 4656 4657 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4658 CTLFLAG_RD, &sc->stats.icrxatc, 4659 "Interrupt Cause Rx Abs Timer Expire Count"); 4660 4661 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4662 CTLFLAG_RD, &sc->stats.ictxptc, 4663 "Interrupt Cause Tx Pkt Timer Expire Count"); 4664 4665 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4666 CTLFLAG_RD, &sc->stats.ictxatc, 4667 "Interrupt Cause Tx Abs Timer Expire Count"); 4668 4669 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4670 CTLFLAG_RD, &sc->stats.ictxqec, 4671 "Interrupt Cause Tx Queue Empty Count"); 4672 4673 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4674 CTLFLAG_RD, &sc->stats.ictxqmtc, 4675 "Interrupt Cause Tx Queue Min Thresh Count"); 4676 4677 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4678 CTLFLAG_RD, &sc->stats.icrxdmtc, 4679 "Interrupt Cause Rx Desc Min Thresh Count"); 4680 4681 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4682 CTLFLAG_RD, &sc->stats.icrxoc, 4683 "Interrupt Cause Receiver Overrun Count"); 4684 } 4685 4686 static void 4687 em_fw_version_locked(if_ctx_t ctx) 4688 { 4689 struct e1000_softc *sc = iflib_get_softc(ctx); 4690 struct e1000_hw *hw = &sc->hw; 4691 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4692 uint16_t eep = 0; 4693 4694 /* 4695 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4696 * NVM locking model, so we do it in em_if_attach_pre() and store the 4697 * info in the softc 4698 */ 4699 ASSERT_CTX_LOCK_HELD(hw); 4700 4701 *fw_ver = (struct e1000_fw_version){0}; 4702 4703 if (hw->mac.type >= igb_mac_min) { 4704 /* 4705 * Use the Shared Code for igb(4) 4706 */ 4707 e1000_get_fw_version(hw, fw_ver); 4708 } else { 4709 /* 4710 * Otherwise, EEPROM version should be present on (almost?) all 4711 * devices here 4712 */ 4713 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4714 INIT_DEBUGOUT("can't get EEPROM version"); 4715 return; 4716 } 4717 4718 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4719 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4720 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4721 } 4722 } 4723 4724 static void 4725 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4726 { 4727 const char *space = ""; 4728 4729 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4730 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4731 fw_ver->eep_minor, fw_ver->eep_build); 4732 space = " "; 4733 } 4734 4735 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4736 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4737 space, fw_ver->invm_major, fw_ver->invm_minor, 4738 fw_ver->invm_img_type); 4739 space = " "; 4740 } 4741 4742 if (fw_ver->or_valid) { 4743 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4744 space, fw_ver->or_major, fw_ver->or_build, 4745 fw_ver->or_patch); 4746 space = " "; 4747 } 4748 4749 if (fw_ver->etrack_id) 4750 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4751 } 4752 4753 static void 4754 em_print_fw_version(struct e1000_softc *sc ) 4755 { 4756 device_t dev = sc->dev; 4757 struct sbuf *buf; 4758 int error = 0; 4759 4760 buf = sbuf_new_auto(); 4761 if (!buf) { 4762 device_printf(dev, "Could not allocate sbuf for output.\n"); 4763 return; 4764 } 4765 4766 em_sbuf_fw_version(&sc->fw_ver, buf); 4767 4768 error = sbuf_finish(buf); 4769 if (error) 4770 device_printf(dev, "Error finishing sbuf: %d\n", error); 4771 else if (sbuf_len(buf)) 4772 device_printf(dev, "%s\n", sbuf_data(buf)); 4773 4774 sbuf_delete(buf); 4775 } 4776 4777 static int 4778 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4779 { 4780 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4781 device_t dev = sc->dev; 4782 struct sbuf *buf; 4783 int error = 0; 4784 4785 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4786 if (!buf) { 4787 device_printf(dev, "Could not allocate sbuf for output.\n"); 4788 return (ENOMEM); 4789 } 4790 4791 em_sbuf_fw_version(&sc->fw_ver, buf); 4792 4793 error = sbuf_finish(buf); 4794 if (error) 4795 device_printf(dev, "Error finishing sbuf: %d\n", error); 4796 4797 sbuf_delete(buf); 4798 4799 return (0); 4800 } 4801 4802 /********************************************************************** 4803 * 4804 * This routine provides a way to dump out the adapter eeprom, 4805 * often a useful debug/service tool. This only dumps the first 4806 * 32 words, stuff that matters is in that extent. 4807 * 4808 **********************************************************************/ 4809 static int 4810 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4811 { 4812 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4813 int error; 4814 int result; 4815 4816 result = -1; 4817 error = sysctl_handle_int(oidp, &result, 0, req); 4818 4819 if (error || !req->newptr) 4820 return (error); 4821 4822 /* 4823 * This value will cause a hex dump of the 4824 * first 32 16-bit words of the EEPROM to 4825 * the screen. 4826 */ 4827 if (result == 1) 4828 em_print_nvm_info(sc); 4829 4830 return (error); 4831 } 4832 4833 static void 4834 em_print_nvm_info(struct e1000_softc *sc) 4835 { 4836 struct e1000_hw *hw = &sc->hw; 4837 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4838 u16 eeprom_data; 4839 int i, j, row = 0; 4840 4841 /* Its a bit crude, but it gets the job done */ 4842 printf("\nInterface EEPROM Dump:\n"); 4843 printf("Offset\n0x0000 "); 4844 4845 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4846 sx_xlock(iflib_ctx_lock); 4847 ASSERT_CTX_LOCK_HELD(hw); 4848 for (i = 0, j = 0; i < 32; i++, j++) { 4849 if (j == 8) { /* Make the offset block */ 4850 j = 0; ++row; 4851 printf("\n0x00%x0 ",row); 4852 } 4853 e1000_read_nvm(hw, i, 1, &eeprom_data); 4854 printf("%04x ", eeprom_data); 4855 } 4856 sx_xunlock(iflib_ctx_lock); 4857 printf("\n"); 4858 } 4859 4860 static int 4861 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4862 { 4863 struct em_int_delay_info *info; 4864 struct e1000_softc *sc; 4865 u32 regval; 4866 int error, usecs, ticks; 4867 4868 info = (struct em_int_delay_info *) arg1; 4869 usecs = info->value; 4870 error = sysctl_handle_int(oidp, &usecs, 0, req); 4871 if (error != 0 || req->newptr == NULL) 4872 return (error); 4873 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4874 return (EINVAL); 4875 info->value = usecs; 4876 ticks = EM_USECS_TO_TICKS(usecs); 4877 if (info->offset == E1000_ITR) /* units are 256ns here */ 4878 ticks *= 4; 4879 4880 sc = info->sc; 4881 4882 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4883 regval = (regval & ~0xffff) | (ticks & 0xffff); 4884 /* Handle a few special cases. */ 4885 switch (info->offset) { 4886 case E1000_RDTR: 4887 break; 4888 case E1000_TIDV: 4889 if (ticks == 0) { 4890 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4891 /* Don't write 0 into the TIDV register. */ 4892 regval++; 4893 } else 4894 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4895 break; 4896 } 4897 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4898 return (0); 4899 } 4900 4901 static void 4902 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4903 const char *description, struct em_int_delay_info *info, 4904 int offset, int value) 4905 { 4906 info->sc = sc; 4907 info->offset = offset; 4908 info->value = value; 4909 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4910 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4911 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4912 info, 0, em_sysctl_int_delay, "I", description); 4913 } 4914 4915 /* 4916 * Set flow control using sysctl: 4917 * Flow control values: 4918 * 0 - off 4919 * 1 - rx pause 4920 * 2 - tx pause 4921 * 3 - full 4922 */ 4923 static int 4924 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4925 { 4926 int error; 4927 static int input = 3; /* default is full */ 4928 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4929 4930 error = sysctl_handle_int(oidp, &input, 0, req); 4931 4932 if ((error) || (req->newptr == NULL)) 4933 return (error); 4934 4935 if (input == sc->fc) /* no change? */ 4936 return (error); 4937 4938 switch (input) { 4939 case e1000_fc_rx_pause: 4940 case e1000_fc_tx_pause: 4941 case e1000_fc_full: 4942 case e1000_fc_none: 4943 sc->hw.fc.requested_mode = input; 4944 sc->fc = input; 4945 break; 4946 default: 4947 /* Do nothing */ 4948 return (error); 4949 } 4950 4951 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4952 e1000_force_mac_fc(&sc->hw); 4953 return (error); 4954 } 4955 4956 /* 4957 * Manage Energy Efficient Ethernet: 4958 * Control values: 4959 * 0/1 - enabled/disabled 4960 */ 4961 static int 4962 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4963 { 4964 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4965 int error, value; 4966 4967 value = sc->hw.dev_spec.ich8lan.eee_disable; 4968 error = sysctl_handle_int(oidp, &value, 0, req); 4969 if (error || req->newptr == NULL) 4970 return (error); 4971 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4972 em_if_init(sc->ctx); 4973 4974 return (0); 4975 } 4976 4977 static int 4978 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4979 { 4980 struct e1000_softc *sc; 4981 int error; 4982 int result; 4983 4984 result = -1; 4985 error = sysctl_handle_int(oidp, &result, 0, req); 4986 4987 if (error || !req->newptr) 4988 return (error); 4989 4990 if (result == 1) { 4991 sc = (struct e1000_softc *) arg1; 4992 em_print_debug_info(sc); 4993 } 4994 4995 return (error); 4996 } 4997 4998 static int 4999 em_get_rs(SYSCTL_HANDLER_ARGS) 5000 { 5001 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5002 int error; 5003 int result; 5004 5005 result = 0; 5006 error = sysctl_handle_int(oidp, &result, 0, req); 5007 5008 if (error || !req->newptr || result != 1) 5009 return (error); 5010 em_dump_rs(sc); 5011 5012 return (error); 5013 } 5014 5015 static void 5016 em_if_debug(if_ctx_t ctx) 5017 { 5018 em_dump_rs(iflib_get_softc(ctx)); 5019 } 5020 5021 /* 5022 * This routine is meant to be fluid, add whatever is 5023 * needed for debugging a problem. -jfv 5024 */ 5025 static void 5026 em_print_debug_info(struct e1000_softc *sc) 5027 { 5028 device_t dev = iflib_get_dev(sc->ctx); 5029 if_t ifp = iflib_get_ifp(sc->ctx); 5030 struct tx_ring *txr = &sc->tx_queues->txr; 5031 struct rx_ring *rxr = &sc->rx_queues->rxr; 5032 5033 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5034 printf("Interface is RUNNING "); 5035 else 5036 printf("Interface is NOT RUNNING\n"); 5037 5038 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5039 printf("and INACTIVE\n"); 5040 else 5041 printf("and ACTIVE\n"); 5042 5043 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5044 device_printf(dev, "TX Queue %d ------\n", i); 5045 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5046 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5047 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5048 5049 } 5050 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5051 device_printf(dev, "RX Queue %d ------\n", j); 5052 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5053 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5054 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5055 } 5056 } 5057 5058 /* 5059 * 82574 only: 5060 * Write a new value to the EEPROM increasing the number of MSI-X 5061 * vectors from 3 to 5, for proper multiqueue support. 5062 */ 5063 static void 5064 em_enable_vectors_82574(if_ctx_t ctx) 5065 { 5066 struct e1000_softc *sc = iflib_get_softc(ctx); 5067 struct e1000_hw *hw = &sc->hw; 5068 device_t dev = iflib_get_dev(ctx); 5069 u16 edata; 5070 5071 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5072 if (bootverbose) 5073 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5074 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5075 device_printf(dev, "Writing to eeprom: increasing " 5076 "reported MSI-X vectors from 3 to 5...\n"); 5077 edata &= ~(EM_NVM_MSIX_N_MASK); 5078 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5079 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5080 e1000_update_nvm_checksum(hw); 5081 device_printf(dev, "Writing to eeprom: done\n"); 5082 } 5083 } 5084