1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V10, "Intel(R) PRO/1000 Network Connection"), 178 /* required last entry */ 179 PVID_END 180 }; 181 182 static pci_vendor_info_t igb_vendor_info_array[] = 183 { 184 /* Intel(R) PRO/1000 Network Connection - igb */ 185 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 224 /* required last entry */ 225 PVID_END 226 }; 227 228 /********************************************************************* 229 * Function prototypes 230 *********************************************************************/ 231 static void *em_register(device_t dev); 232 static void *igb_register(device_t dev); 233 static int em_if_attach_pre(if_ctx_t ctx); 234 static int em_if_attach_post(if_ctx_t ctx); 235 static int em_if_detach(if_ctx_t ctx); 236 static int em_if_shutdown(if_ctx_t ctx); 237 static int em_if_suspend(if_ctx_t ctx); 238 static int em_if_resume(if_ctx_t ctx); 239 240 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 241 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 242 static void em_if_queues_free(if_ctx_t ctx); 243 244 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 245 static void em_if_init(if_ctx_t ctx); 246 static void em_if_stop(if_ctx_t ctx); 247 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 248 static int em_if_media_change(if_ctx_t ctx); 249 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 250 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 251 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 252 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 253 static void em_if_watchdog_reset(if_ctx_t ctx); 254 255 static void em_identify_hardware(if_ctx_t ctx); 256 static int em_allocate_pci_resources(if_ctx_t ctx); 257 static void em_free_pci_resources(if_ctx_t ctx); 258 static void em_reset(if_ctx_t ctx); 259 static int em_setup_interface(if_ctx_t ctx); 260 static int em_setup_msix(if_ctx_t ctx); 261 262 static void em_initialize_transmit_unit(if_ctx_t ctx); 263 static void em_initialize_receive_unit(if_ctx_t ctx); 264 265 static void em_if_intr_enable(if_ctx_t ctx); 266 static void em_if_intr_disable(if_ctx_t ctx); 267 static void igb_if_intr_enable(if_ctx_t ctx); 268 static void igb_if_intr_disable(if_ctx_t ctx); 269 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 270 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 271 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 272 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 273 static void em_if_multi_set(if_ctx_t ctx); 274 static void em_if_update_admin_status(if_ctx_t ctx); 275 static void em_if_debug(if_ctx_t ctx); 276 static void em_update_stats_counters(struct adapter *); 277 static void em_add_hw_stats(struct adapter *adapter); 278 static int em_if_set_promisc(if_ctx_t ctx, int flags); 279 static void em_setup_vlan_hw_support(struct adapter *); 280 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 281 static void em_print_nvm_info(struct adapter *); 282 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 283 static int em_get_rs(SYSCTL_HANDLER_ARGS); 284 static void em_print_debug_info(struct adapter *); 285 static int em_is_valid_ether_addr(u8 *); 286 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 287 static void em_add_int_delay_sysctl(struct adapter *, const char *, 288 const char *, struct em_int_delay_info *, int, int); 289 /* Management and WOL Support */ 290 static void em_init_manageability(struct adapter *); 291 static void em_release_manageability(struct adapter *); 292 static void em_get_hw_control(struct adapter *); 293 static void em_release_hw_control(struct adapter *); 294 static void em_get_wakeup(if_ctx_t ctx); 295 static void em_enable_wakeup(if_ctx_t ctx); 296 static int em_enable_phy_wakeup(struct adapter *); 297 static void em_disable_aspm(struct adapter *); 298 299 int em_intr(void *arg); 300 static void em_disable_promisc(if_ctx_t ctx); 301 302 /* MSI-X handlers */ 303 static int em_if_msix_intr_assign(if_ctx_t, int); 304 static int em_msix_link(void *); 305 static void em_handle_link(void *context); 306 307 static void em_enable_vectors_82574(if_ctx_t); 308 309 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 310 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 311 static void em_if_led_func(if_ctx_t ctx, int onoff); 312 313 static int em_get_regs(SYSCTL_HANDLER_ARGS); 314 315 static void lem_smartspeed(struct adapter *adapter); 316 static void igb_configure_queues(struct adapter *adapter); 317 318 319 /********************************************************************* 320 * FreeBSD Device Interface Entry Points 321 *********************************************************************/ 322 static device_method_t em_methods[] = { 323 /* Device interface */ 324 DEVMETHOD(device_register, em_register), 325 DEVMETHOD(device_probe, iflib_device_probe), 326 DEVMETHOD(device_attach, iflib_device_attach), 327 DEVMETHOD(device_detach, iflib_device_detach), 328 DEVMETHOD(device_shutdown, iflib_device_shutdown), 329 DEVMETHOD(device_suspend, iflib_device_suspend), 330 DEVMETHOD(device_resume, iflib_device_resume), 331 DEVMETHOD_END 332 }; 333 334 static device_method_t igb_methods[] = { 335 /* Device interface */ 336 DEVMETHOD(device_register, igb_register), 337 DEVMETHOD(device_probe, iflib_device_probe), 338 DEVMETHOD(device_attach, iflib_device_attach), 339 DEVMETHOD(device_detach, iflib_device_detach), 340 DEVMETHOD(device_shutdown, iflib_device_shutdown), 341 DEVMETHOD(device_suspend, iflib_device_suspend), 342 DEVMETHOD(device_resume, iflib_device_resume), 343 DEVMETHOD_END 344 }; 345 346 347 static driver_t em_driver = { 348 "em", em_methods, sizeof(struct adapter), 349 }; 350 351 static devclass_t em_devclass; 352 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 353 354 MODULE_DEPEND(em, pci, 1, 1, 1); 355 MODULE_DEPEND(em, ether, 1, 1, 1); 356 MODULE_DEPEND(em, iflib, 1, 1, 1); 357 358 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 359 360 static driver_t igb_driver = { 361 "igb", igb_methods, sizeof(struct adapter), 362 }; 363 364 static devclass_t igb_devclass; 365 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 366 367 MODULE_DEPEND(igb, pci, 1, 1, 1); 368 MODULE_DEPEND(igb, ether, 1, 1, 1); 369 MODULE_DEPEND(igb, iflib, 1, 1, 1); 370 371 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 372 373 static device_method_t em_if_methods[] = { 374 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 375 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 376 DEVMETHOD(ifdi_detach, em_if_detach), 377 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 378 DEVMETHOD(ifdi_suspend, em_if_suspend), 379 DEVMETHOD(ifdi_resume, em_if_resume), 380 DEVMETHOD(ifdi_init, em_if_init), 381 DEVMETHOD(ifdi_stop, em_if_stop), 382 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 383 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 384 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 385 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 386 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 387 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 388 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 389 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 390 DEVMETHOD(ifdi_media_status, em_if_media_status), 391 DEVMETHOD(ifdi_media_change, em_if_media_change), 392 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 393 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 394 DEVMETHOD(ifdi_timer, em_if_timer), 395 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 396 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 397 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 398 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 399 DEVMETHOD(ifdi_led_func, em_if_led_func), 400 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 401 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 402 DEVMETHOD(ifdi_debug, em_if_debug), 403 DEVMETHOD_END 404 }; 405 406 static driver_t em_if_driver = { 407 "em_if", em_if_methods, sizeof(struct adapter) 408 }; 409 410 static device_method_t igb_if_methods[] = { 411 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 412 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 413 DEVMETHOD(ifdi_detach, em_if_detach), 414 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 415 DEVMETHOD(ifdi_suspend, em_if_suspend), 416 DEVMETHOD(ifdi_resume, em_if_resume), 417 DEVMETHOD(ifdi_init, em_if_init), 418 DEVMETHOD(ifdi_stop, em_if_stop), 419 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 420 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 421 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 422 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 423 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 424 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 425 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 426 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 427 DEVMETHOD(ifdi_media_status, em_if_media_status), 428 DEVMETHOD(ifdi_media_change, em_if_media_change), 429 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 430 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 431 DEVMETHOD(ifdi_timer, em_if_timer), 432 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 433 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 434 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 435 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 436 DEVMETHOD(ifdi_led_func, em_if_led_func), 437 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 438 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 439 DEVMETHOD(ifdi_debug, em_if_debug), 440 DEVMETHOD_END 441 }; 442 443 static driver_t igb_if_driver = { 444 "igb_if", igb_if_methods, sizeof(struct adapter) 445 }; 446 447 /********************************************************************* 448 * Tunable default values. 449 *********************************************************************/ 450 451 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 452 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 453 454 #define MAX_INTS_PER_SEC 8000 455 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 456 457 /* Allow common code without TSO */ 458 #ifndef CSUM_TSO 459 #define CSUM_TSO 0 460 #endif 461 462 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 463 464 static int em_disable_crc_stripping = 0; 465 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 466 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 467 468 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 469 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 470 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 471 0, "Default transmit interrupt delay in usecs"); 472 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 473 0, "Default receive interrupt delay in usecs"); 474 475 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 476 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 477 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 478 &em_tx_abs_int_delay_dflt, 0, 479 "Default transmit interrupt delay limit in usecs"); 480 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 481 &em_rx_abs_int_delay_dflt, 0, 482 "Default receive interrupt delay limit in usecs"); 483 484 static int em_smart_pwr_down = FALSE; 485 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 486 0, "Set to true to leave smart power down enabled on newer adapters"); 487 488 /* Controls whether promiscuous also shows bad packets */ 489 static int em_debug_sbp = TRUE; 490 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 491 "Show bad packets in promiscuous mode"); 492 493 /* How many packets rxeof tries to clean at a time */ 494 static int em_rx_process_limit = 100; 495 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 496 &em_rx_process_limit, 0, 497 "Maximum number of received packets to process " 498 "at a time, -1 means unlimited"); 499 500 /* Energy efficient ethernet - default to OFF */ 501 static int eee_setting = 1; 502 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 503 "Enable Energy Efficient Ethernet"); 504 505 /* 506 ** Tuneable Interrupt rate 507 */ 508 static int em_max_interrupt_rate = 8000; 509 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 510 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 511 512 513 514 /* Global used in WOL setup with multiport cards */ 515 static int global_quad_port_a = 0; 516 517 extern struct if_txrx igb_txrx; 518 extern struct if_txrx em_txrx; 519 extern struct if_txrx lem_txrx; 520 521 static struct if_shared_ctx em_sctx_init = { 522 .isc_magic = IFLIB_MAGIC, 523 .isc_q_align = PAGE_SIZE, 524 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 525 .isc_tx_maxsegsize = PAGE_SIZE, 526 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 527 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 528 .isc_rx_maxsize = MJUM9BYTES, 529 .isc_rx_nsegments = 1, 530 .isc_rx_maxsegsize = MJUM9BYTES, 531 .isc_nfl = 1, 532 .isc_nrxqs = 1, 533 .isc_ntxqs = 1, 534 .isc_admin_intrcnt = 1, 535 .isc_vendor_info = em_vendor_info_array, 536 .isc_driver_version = em_driver_version, 537 .isc_driver = &em_if_driver, 538 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 539 540 .isc_nrxd_min = {EM_MIN_RXD}, 541 .isc_ntxd_min = {EM_MIN_TXD}, 542 .isc_nrxd_max = {EM_MAX_RXD}, 543 .isc_ntxd_max = {EM_MAX_TXD}, 544 .isc_nrxd_default = {EM_DEFAULT_RXD}, 545 .isc_ntxd_default = {EM_DEFAULT_TXD}, 546 }; 547 548 if_shared_ctx_t em_sctx = &em_sctx_init; 549 550 static struct if_shared_ctx igb_sctx_init = { 551 .isc_magic = IFLIB_MAGIC, 552 .isc_q_align = PAGE_SIZE, 553 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 554 .isc_tx_maxsegsize = PAGE_SIZE, 555 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 556 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 557 .isc_rx_maxsize = MJUM9BYTES, 558 .isc_rx_nsegments = 1, 559 .isc_rx_maxsegsize = MJUM9BYTES, 560 .isc_nfl = 1, 561 .isc_nrxqs = 1, 562 .isc_ntxqs = 1, 563 .isc_admin_intrcnt = 1, 564 .isc_vendor_info = igb_vendor_info_array, 565 .isc_driver_version = em_driver_version, 566 .isc_driver = &igb_if_driver, 567 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 568 569 .isc_nrxd_min = {EM_MIN_RXD}, 570 .isc_ntxd_min = {EM_MIN_TXD}, 571 .isc_nrxd_max = {IGB_MAX_RXD}, 572 .isc_ntxd_max = {IGB_MAX_TXD}, 573 .isc_nrxd_default = {EM_DEFAULT_RXD}, 574 .isc_ntxd_default = {EM_DEFAULT_TXD}, 575 }; 576 577 if_shared_ctx_t igb_sctx = &igb_sctx_init; 578 579 /***************************************************************** 580 * 581 * Dump Registers 582 * 583 ****************************************************************/ 584 #define IGB_REGS_LEN 739 585 586 static int em_get_regs(SYSCTL_HANDLER_ARGS) 587 { 588 struct adapter *adapter = (struct adapter *)arg1; 589 struct e1000_hw *hw = &adapter->hw; 590 struct sbuf *sb; 591 u32 *regs_buff; 592 int rc; 593 594 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 595 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 596 597 rc = sysctl_wire_old_buffer(req, 0); 598 MPASS(rc == 0); 599 if (rc != 0) { 600 free(regs_buff, M_DEVBUF); 601 return (rc); 602 } 603 604 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 605 MPASS(sb != NULL); 606 if (sb == NULL) { 607 free(regs_buff, M_DEVBUF); 608 return (ENOMEM); 609 } 610 611 /* General Registers */ 612 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 613 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 614 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 615 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 616 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 617 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 618 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 619 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 620 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 621 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 622 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 623 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 624 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 625 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 626 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 627 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 628 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 629 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 630 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 631 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 632 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 633 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 634 635 sbuf_printf(sb, "General Registers\n"); 636 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 637 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 638 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 639 640 sbuf_printf(sb, "Interrupt Registers\n"); 641 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 642 643 sbuf_printf(sb, "RX Registers\n"); 644 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 645 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 646 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 647 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 648 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 649 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 650 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 651 652 sbuf_printf(sb, "TX Registers\n"); 653 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 654 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 655 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 656 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 657 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 658 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 659 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 660 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 661 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 662 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 663 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 664 665 free(regs_buff, M_DEVBUF); 666 667 #ifdef DUMP_DESCS 668 { 669 if_softc_ctx_t scctx = adapter->shared; 670 struct rx_ring *rxr = &rx_que->rxr; 671 struct tx_ring *txr = &tx_que->txr; 672 int ntxd = scctx->isc_ntxd[0]; 673 int nrxd = scctx->isc_nrxd[0]; 674 int j; 675 676 for (j = 0; j < nrxd; j++) { 677 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 678 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 679 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 680 } 681 682 for (j = 0; j < min(ntxd, 256); j++) { 683 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 684 685 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 686 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 687 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 688 689 } 690 } 691 #endif 692 693 rc = sbuf_finish(sb); 694 sbuf_delete(sb); 695 return(rc); 696 } 697 698 static void * 699 em_register(device_t dev) 700 { 701 return (em_sctx); 702 } 703 704 static void * 705 igb_register(device_t dev) 706 { 707 return (igb_sctx); 708 } 709 710 static int 711 em_set_num_queues(if_ctx_t ctx) 712 { 713 struct adapter *adapter = iflib_get_softc(ctx); 714 int maxqueues; 715 716 /* Sanity check based on HW */ 717 switch (adapter->hw.mac.type) { 718 case e1000_82576: 719 case e1000_82580: 720 case e1000_i350: 721 case e1000_i354: 722 maxqueues = 8; 723 break; 724 case e1000_i210: 725 case e1000_82575: 726 maxqueues = 4; 727 break; 728 case e1000_i211: 729 case e1000_82574: 730 maxqueues = 2; 731 break; 732 default: 733 maxqueues = 1; 734 break; 735 } 736 737 return (maxqueues); 738 } 739 740 #define LEM_CAPS \ 741 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 742 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 743 744 #define EM_CAPS \ 745 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 746 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 747 IFCAP_LRO | IFCAP_VLAN_HWTSO 748 749 #define IGB_CAPS \ 750 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 751 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 752 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 753 IFCAP_TSO6 754 755 /********************************************************************* 756 * Device initialization routine 757 * 758 * The attach entry point is called when the driver is being loaded. 759 * This routine identifies the type of hardware, allocates all resources 760 * and initializes the hardware. 761 * 762 * return 0 on success, positive on failure 763 *********************************************************************/ 764 static int 765 em_if_attach_pre(if_ctx_t ctx) 766 { 767 struct adapter *adapter; 768 if_softc_ctx_t scctx; 769 device_t dev; 770 struct e1000_hw *hw; 771 int error = 0; 772 773 INIT_DEBUGOUT("em_if_attach_pre: begin"); 774 dev = iflib_get_dev(ctx); 775 adapter = iflib_get_softc(ctx); 776 777 adapter->ctx = adapter->osdep.ctx = ctx; 778 adapter->dev = adapter->osdep.dev = dev; 779 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 780 adapter->media = iflib_get_media(ctx); 781 hw = &adapter->hw; 782 783 adapter->tx_process_limit = scctx->isc_ntxd[0]; 784 785 /* SYSCTL stuff */ 786 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 787 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 788 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 789 em_sysctl_nvm_info, "I", "NVM Information"); 790 791 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 792 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 793 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 794 em_sysctl_debug_info, "I", "Debug Information"); 795 796 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 797 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 798 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 799 em_set_flowcntl, "I", "Flow Control"); 800 801 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 802 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 803 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 804 em_get_regs, "A", "Dump Registers"); 805 806 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 807 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 808 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 809 em_get_rs, "I", "Dump RS indexes"); 810 811 /* Determine hardware and mac info */ 812 em_identify_hardware(ctx); 813 814 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 815 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 816 if (bootverbose) 817 device_printf(dev, "attach_pre capping queues at %d\n", 818 scctx->isc_ntxqsets_max); 819 820 if (adapter->hw.mac.type >= igb_mac_min) { 821 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 822 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 823 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 824 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 825 scctx->isc_txrx = &igb_txrx; 826 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 827 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 828 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 829 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 830 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 831 CSUM_IP6_TCP | CSUM_IP6_UDP; 832 if (adapter->hw.mac.type != e1000_82575) 833 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 834 /* 835 ** Some new devices, as with ixgbe, now may 836 ** use a different BAR, so we need to keep 837 ** track of which is used. 838 */ 839 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 840 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 841 scctx->isc_msix_bar += 4; 842 } else if (adapter->hw.mac.type >= em_mac_min) { 843 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 844 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 845 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 846 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 847 scctx->isc_txrx = &em_txrx; 848 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 849 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 850 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 851 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 852 /* 853 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 854 * by default as we don't have workarounds for all associated 855 * silicon errata. E. g., with several MACs such as 82573E, 856 * TSO only works at Gigabit speed and otherwise can cause the 857 * hardware to hang (which also would be next to impossible to 858 * work around given that already queued TSO-using descriptors 859 * would need to be flushed and vlan(4) reconfigured at runtime 860 * in case of a link speed change). Moreover, MACs like 82579 861 * still can hang at Gigabit even with all publicly documented 862 * TSO workarounds implemented. Generally, the penality of 863 * these workarounds is rather high and may involve copying 864 * mbuf data around so advantages of TSO lapse. Still, TSO may 865 * work for a few MACs of this class - at least when sticking 866 * with Gigabit - in which case users may enable TSO manually. 867 */ 868 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 869 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 870 /* 871 * We support MSI-X with 82574 only, but indicate to iflib(4) 872 * that it shall give MSI at least a try with other devices. 873 */ 874 if (adapter->hw.mac.type == e1000_82574) { 875 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 876 } else { 877 scctx->isc_msix_bar = -1; 878 scctx->isc_disable_msix = 1; 879 } 880 } else { 881 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 882 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 883 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 884 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 885 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 886 scctx->isc_txrx = &lem_txrx; 887 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 888 if (adapter->hw.mac.type < e1000_82543) 889 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 890 /* INTx only */ 891 scctx->isc_msix_bar = 0; 892 } 893 894 /* Setup PCI resources */ 895 if (em_allocate_pci_resources(ctx)) { 896 device_printf(dev, "Allocation of PCI resources failed\n"); 897 error = ENXIO; 898 goto err_pci; 899 } 900 901 /* 902 ** For ICH8 and family we need to 903 ** map the flash memory, and this 904 ** must happen after the MAC is 905 ** identified 906 */ 907 if ((hw->mac.type == e1000_ich8lan) || 908 (hw->mac.type == e1000_ich9lan) || 909 (hw->mac.type == e1000_ich10lan) || 910 (hw->mac.type == e1000_pchlan) || 911 (hw->mac.type == e1000_pch2lan) || 912 (hw->mac.type == e1000_pch_lpt)) { 913 int rid = EM_BAR_TYPE_FLASH; 914 adapter->flash = bus_alloc_resource_any(dev, 915 SYS_RES_MEMORY, &rid, RF_ACTIVE); 916 if (adapter->flash == NULL) { 917 device_printf(dev, "Mapping of Flash failed\n"); 918 error = ENXIO; 919 goto err_pci; 920 } 921 /* This is used in the shared code */ 922 hw->flash_address = (u8 *)adapter->flash; 923 adapter->osdep.flash_bus_space_tag = 924 rman_get_bustag(adapter->flash); 925 adapter->osdep.flash_bus_space_handle = 926 rman_get_bushandle(adapter->flash); 927 } 928 /* 929 ** In the new SPT device flash is not a 930 ** separate BAR, rather it is also in BAR0, 931 ** so use the same tag and an offset handle for the 932 ** FLASH read/write macros in the shared code. 933 */ 934 else if (hw->mac.type >= e1000_pch_spt) { 935 adapter->osdep.flash_bus_space_tag = 936 adapter->osdep.mem_bus_space_tag; 937 adapter->osdep.flash_bus_space_handle = 938 adapter->osdep.mem_bus_space_handle 939 + E1000_FLASH_BASE_ADDR; 940 } 941 942 /* Do Shared Code initialization */ 943 error = e1000_setup_init_funcs(hw, TRUE); 944 if (error) { 945 device_printf(dev, "Setup of Shared code failed, error %d\n", 946 error); 947 error = ENXIO; 948 goto err_pci; 949 } 950 951 em_setup_msix(ctx); 952 e1000_get_bus_info(hw); 953 954 /* Set up some sysctls for the tunable interrupt delays */ 955 em_add_int_delay_sysctl(adapter, "rx_int_delay", 956 "receive interrupt delay in usecs", &adapter->rx_int_delay, 957 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 958 em_add_int_delay_sysctl(adapter, "tx_int_delay", 959 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 960 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 961 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 962 "receive interrupt delay limit in usecs", 963 &adapter->rx_abs_int_delay, 964 E1000_REGISTER(hw, E1000_RADV), 965 em_rx_abs_int_delay_dflt); 966 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 967 "transmit interrupt delay limit in usecs", 968 &adapter->tx_abs_int_delay, 969 E1000_REGISTER(hw, E1000_TADV), 970 em_tx_abs_int_delay_dflt); 971 em_add_int_delay_sysctl(adapter, "itr", 972 "interrupt delay limit in usecs/4", 973 &adapter->tx_itr, 974 E1000_REGISTER(hw, E1000_ITR), 975 DEFAULT_ITR); 976 977 hw->mac.autoneg = DO_AUTO_NEG; 978 hw->phy.autoneg_wait_to_complete = FALSE; 979 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 980 981 if (adapter->hw.mac.type < em_mac_min) { 982 e1000_init_script_state_82541(&adapter->hw, TRUE); 983 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 984 } 985 /* Copper options */ 986 if (hw->phy.media_type == e1000_media_type_copper) { 987 hw->phy.mdix = AUTO_ALL_MODES; 988 hw->phy.disable_polarity_correction = FALSE; 989 hw->phy.ms_type = EM_MASTER_SLAVE; 990 } 991 992 /* 993 * Set the frame limits assuming 994 * standard ethernet sized frames. 995 */ 996 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 997 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 998 999 /* 1000 * This controls when hardware reports transmit completion 1001 * status. 1002 */ 1003 hw->mac.report_tx_early = 1; 1004 1005 /* Allocate multicast array memory. */ 1006 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1007 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1008 if (adapter->mta == NULL) { 1009 device_printf(dev, "Can not allocate multicast setup array\n"); 1010 error = ENOMEM; 1011 goto err_late; 1012 } 1013 1014 /* Check SOL/IDER usage */ 1015 if (e1000_check_reset_block(hw)) 1016 device_printf(dev, "PHY reset is blocked" 1017 " due to SOL/IDER session.\n"); 1018 1019 /* Sysctl for setting Energy Efficient Ethernet */ 1020 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1021 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1022 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1023 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 1024 adapter, 0, em_sysctl_eee, "I", 1025 "Disable Energy Efficient Ethernet"); 1026 1027 /* 1028 ** Start from a known state, this is 1029 ** important in reading the nvm and 1030 ** mac from that. 1031 */ 1032 e1000_reset_hw(hw); 1033 1034 /* Make sure we have a good EEPROM before we read from it */ 1035 if (e1000_validate_nvm_checksum(hw) < 0) { 1036 /* 1037 ** Some PCI-E parts fail the first check due to 1038 ** the link being in sleep state, call it again, 1039 ** if it fails a second time its a real issue. 1040 */ 1041 if (e1000_validate_nvm_checksum(hw) < 0) { 1042 device_printf(dev, 1043 "The EEPROM Checksum Is Not Valid\n"); 1044 error = EIO; 1045 goto err_late; 1046 } 1047 } 1048 1049 /* Copy the permanent MAC address out of the EEPROM */ 1050 if (e1000_read_mac_addr(hw) < 0) { 1051 device_printf(dev, "EEPROM read error while reading MAC" 1052 " address\n"); 1053 error = EIO; 1054 goto err_late; 1055 } 1056 1057 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1058 device_printf(dev, "Invalid MAC address\n"); 1059 error = EIO; 1060 goto err_late; 1061 } 1062 1063 /* Disable ULP support */ 1064 e1000_disable_ulp_lpt_lp(hw, TRUE); 1065 1066 /* 1067 * Get Wake-on-Lan and Management info for later use 1068 */ 1069 em_get_wakeup(ctx); 1070 1071 /* Enable only WOL MAGIC by default */ 1072 scctx->isc_capenable &= ~IFCAP_WOL; 1073 if (adapter->wol != 0) 1074 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1075 1076 iflib_set_mac(ctx, hw->mac.addr); 1077 1078 return (0); 1079 1080 err_late: 1081 em_release_hw_control(adapter); 1082 err_pci: 1083 em_free_pci_resources(ctx); 1084 free(adapter->mta, M_DEVBUF); 1085 1086 return (error); 1087 } 1088 1089 static int 1090 em_if_attach_post(if_ctx_t ctx) 1091 { 1092 struct adapter *adapter = iflib_get_softc(ctx); 1093 struct e1000_hw *hw = &adapter->hw; 1094 int error = 0; 1095 1096 /* Setup OS specific network interface */ 1097 error = em_setup_interface(ctx); 1098 if (error != 0) { 1099 goto err_late; 1100 } 1101 1102 em_reset(ctx); 1103 1104 /* Initialize statistics */ 1105 em_update_stats_counters(adapter); 1106 hw->mac.get_link_status = 1; 1107 em_if_update_admin_status(ctx); 1108 em_add_hw_stats(adapter); 1109 1110 /* Non-AMT based hardware can now take control from firmware */ 1111 if (adapter->has_manage && !adapter->has_amt) 1112 em_get_hw_control(adapter); 1113 1114 INIT_DEBUGOUT("em_if_attach_post: end"); 1115 1116 return (error); 1117 1118 err_late: 1119 em_release_hw_control(adapter); 1120 em_free_pci_resources(ctx); 1121 em_if_queues_free(ctx); 1122 free(adapter->mta, M_DEVBUF); 1123 1124 return (error); 1125 } 1126 1127 /********************************************************************* 1128 * Device removal routine 1129 * 1130 * The detach entry point is called when the driver is being removed. 1131 * This routine stops the adapter and deallocates all the resources 1132 * that were allocated for driver operation. 1133 * 1134 * return 0 on success, positive on failure 1135 *********************************************************************/ 1136 static int 1137 em_if_detach(if_ctx_t ctx) 1138 { 1139 struct adapter *adapter = iflib_get_softc(ctx); 1140 1141 INIT_DEBUGOUT("em_if_detach: begin"); 1142 1143 e1000_phy_hw_reset(&adapter->hw); 1144 1145 em_release_manageability(adapter); 1146 em_release_hw_control(adapter); 1147 em_free_pci_resources(ctx); 1148 1149 return (0); 1150 } 1151 1152 /********************************************************************* 1153 * 1154 * Shutdown entry point 1155 * 1156 **********************************************************************/ 1157 1158 static int 1159 em_if_shutdown(if_ctx_t ctx) 1160 { 1161 return em_if_suspend(ctx); 1162 } 1163 1164 /* 1165 * Suspend/resume device methods. 1166 */ 1167 static int 1168 em_if_suspend(if_ctx_t ctx) 1169 { 1170 struct adapter *adapter = iflib_get_softc(ctx); 1171 1172 em_release_manageability(adapter); 1173 em_release_hw_control(adapter); 1174 em_enable_wakeup(ctx); 1175 return (0); 1176 } 1177 1178 static int 1179 em_if_resume(if_ctx_t ctx) 1180 { 1181 struct adapter *adapter = iflib_get_softc(ctx); 1182 1183 if (adapter->hw.mac.type == e1000_pch2lan) 1184 e1000_resume_workarounds_pchlan(&adapter->hw); 1185 em_if_init(ctx); 1186 em_init_manageability(adapter); 1187 1188 return(0); 1189 } 1190 1191 static int 1192 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1193 { 1194 int max_frame_size; 1195 struct adapter *adapter = iflib_get_softc(ctx); 1196 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1197 1198 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1199 1200 switch (adapter->hw.mac.type) { 1201 case e1000_82571: 1202 case e1000_82572: 1203 case e1000_ich9lan: 1204 case e1000_ich10lan: 1205 case e1000_pch2lan: 1206 case e1000_pch_lpt: 1207 case e1000_pch_spt: 1208 case e1000_pch_cnp: 1209 case e1000_82574: 1210 case e1000_82583: 1211 case e1000_80003es2lan: 1212 /* 9K Jumbo Frame size */ 1213 max_frame_size = 9234; 1214 break; 1215 case e1000_pchlan: 1216 max_frame_size = 4096; 1217 break; 1218 case e1000_82542: 1219 case e1000_ich8lan: 1220 /* Adapters that do not support jumbo frames */ 1221 max_frame_size = ETHER_MAX_LEN; 1222 break; 1223 default: 1224 if (adapter->hw.mac.type >= igb_mac_min) 1225 max_frame_size = 9234; 1226 else /* lem */ 1227 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1228 } 1229 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1230 return (EINVAL); 1231 } 1232 1233 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1234 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1235 return (0); 1236 } 1237 1238 /********************************************************************* 1239 * Init entry point 1240 * 1241 * This routine is used in two ways. It is used by the stack as 1242 * init entry point in network interface structure. It is also used 1243 * by the driver as a hw/sw initialization routine to get to a 1244 * consistent state. 1245 * 1246 **********************************************************************/ 1247 static void 1248 em_if_init(if_ctx_t ctx) 1249 { 1250 struct adapter *adapter = iflib_get_softc(ctx); 1251 if_softc_ctx_t scctx = adapter->shared; 1252 struct ifnet *ifp = iflib_get_ifp(ctx); 1253 struct em_tx_queue *tx_que; 1254 int i; 1255 1256 INIT_DEBUGOUT("em_if_init: begin"); 1257 1258 /* Get the latest mac address, User can use a LAA */ 1259 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1260 ETHER_ADDR_LEN); 1261 1262 /* Put the address into the Receive Address Array */ 1263 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1264 1265 /* 1266 * With the 82571 adapter, RAR[0] may be overwritten 1267 * when the other port is reset, we make a duplicate 1268 * in RAR[14] for that eventuality, this assures 1269 * the interface continues to function. 1270 */ 1271 if (adapter->hw.mac.type == e1000_82571) { 1272 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1273 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1274 E1000_RAR_ENTRIES - 1); 1275 } 1276 1277 1278 /* Initialize the hardware */ 1279 em_reset(ctx); 1280 em_if_update_admin_status(ctx); 1281 1282 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1283 struct tx_ring *txr = &tx_que->txr; 1284 1285 txr->tx_rs_cidx = txr->tx_rs_pidx; 1286 1287 /* Initialize the last processed descriptor to be the end of 1288 * the ring, rather than the start, so that we avoid an 1289 * off-by-one error when calculating how many descriptors are 1290 * done in the credits_update function. 1291 */ 1292 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1293 } 1294 1295 /* Setup VLAN support, basic and offload if available */ 1296 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1297 1298 /* Clear bad data from Rx FIFOs */ 1299 if (adapter->hw.mac.type >= igb_mac_min) 1300 e1000_rx_fifo_flush_82575(&adapter->hw); 1301 1302 /* Configure for OS presence */ 1303 em_init_manageability(adapter); 1304 1305 /* Prepare transmit descriptors and buffers */ 1306 em_initialize_transmit_unit(ctx); 1307 1308 /* Setup Multicast table */ 1309 em_if_multi_set(ctx); 1310 1311 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1312 em_initialize_receive_unit(ctx); 1313 1314 /* Use real VLAN Filter support? */ 1315 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1316 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1317 /* Use real VLAN Filter support */ 1318 em_setup_vlan_hw_support(adapter); 1319 else { 1320 u32 ctrl; 1321 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1322 ctrl |= E1000_CTRL_VME; 1323 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1324 } 1325 } 1326 1327 /* Don't lose promiscuous settings */ 1328 em_if_set_promisc(ctx, IFF_PROMISC); 1329 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1330 1331 /* MSI-X configuration for 82574 */ 1332 if (adapter->hw.mac.type == e1000_82574) { 1333 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1334 1335 tmp |= E1000_CTRL_EXT_PBA_CLR; 1336 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1337 /* Set the IVAR - interrupt vector routing. */ 1338 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1339 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1340 igb_configure_queues(adapter); 1341 1342 /* this clears any pending interrupts */ 1343 E1000_READ_REG(&adapter->hw, E1000_ICR); 1344 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1345 1346 /* AMT based hardware can now take control from firmware */ 1347 if (adapter->has_manage && adapter->has_amt) 1348 em_get_hw_control(adapter); 1349 1350 /* Set Energy Efficient Ethernet */ 1351 if (adapter->hw.mac.type >= igb_mac_min && 1352 adapter->hw.phy.media_type == e1000_media_type_copper) { 1353 if (adapter->hw.mac.type == e1000_i354) 1354 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1355 else 1356 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1357 } 1358 } 1359 1360 /********************************************************************* 1361 * 1362 * Fast Legacy/MSI Combined Interrupt Service routine 1363 * 1364 *********************************************************************/ 1365 int 1366 em_intr(void *arg) 1367 { 1368 struct adapter *adapter = arg; 1369 if_ctx_t ctx = adapter->ctx; 1370 u32 reg_icr; 1371 1372 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1373 1374 /* Hot eject? */ 1375 if (reg_icr == 0xffffffff) 1376 return FILTER_STRAY; 1377 1378 /* Definitely not our interrupt. */ 1379 if (reg_icr == 0x0) 1380 return FILTER_STRAY; 1381 1382 /* 1383 * Starting with the 82571 chip, bit 31 should be used to 1384 * determine whether the interrupt belongs to us. 1385 */ 1386 if (adapter->hw.mac.type >= e1000_82571 && 1387 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1388 return FILTER_STRAY; 1389 1390 /* 1391 * Only MSI-X interrupts have one-shot behavior by taking advantage 1392 * of the EIAC register. Thus, explicitly disable interrupts. This 1393 * also works around the MSI message reordering errata on certain 1394 * systems. 1395 */ 1396 IFDI_INTR_DISABLE(ctx); 1397 1398 /* Link status change */ 1399 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1400 em_handle_link(ctx); 1401 1402 if (reg_icr & E1000_ICR_RXO) 1403 adapter->rx_overruns++; 1404 1405 return (FILTER_SCHEDULE_THREAD); 1406 } 1407 1408 static int 1409 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1410 { 1411 struct adapter *adapter = iflib_get_softc(ctx); 1412 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1413 1414 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1415 return (0); 1416 } 1417 1418 static int 1419 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1420 { 1421 struct adapter *adapter = iflib_get_softc(ctx); 1422 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1423 1424 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1425 return (0); 1426 } 1427 1428 static int 1429 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1430 { 1431 struct adapter *adapter = iflib_get_softc(ctx); 1432 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1433 1434 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1435 return (0); 1436 } 1437 1438 static int 1439 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1440 { 1441 struct adapter *adapter = iflib_get_softc(ctx); 1442 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1443 1444 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1445 return (0); 1446 } 1447 1448 /********************************************************************* 1449 * 1450 * MSI-X RX Interrupt Service routine 1451 * 1452 **********************************************************************/ 1453 static int 1454 em_msix_que(void *arg) 1455 { 1456 struct em_rx_queue *que = arg; 1457 1458 ++que->irqs; 1459 1460 return (FILTER_SCHEDULE_THREAD); 1461 } 1462 1463 /********************************************************************* 1464 * 1465 * MSI-X Link Fast Interrupt Service routine 1466 * 1467 **********************************************************************/ 1468 static int 1469 em_msix_link(void *arg) 1470 { 1471 struct adapter *adapter = arg; 1472 u32 reg_icr; 1473 1474 ++adapter->link_irq; 1475 MPASS(adapter->hw.back != NULL); 1476 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1477 1478 if (reg_icr & E1000_ICR_RXO) 1479 adapter->rx_overruns++; 1480 1481 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1482 em_handle_link(adapter->ctx); 1483 } else if (adapter->hw.mac.type == e1000_82574) { 1484 /* Only re-arm 82574 if em_if_update_admin_status() won't. */ 1485 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | 1486 E1000_IMS_LSC); 1487 } 1488 1489 if (adapter->hw.mac.type == e1000_82574) { 1490 /* 1491 * Because we must read the ICR for this interrupt it may 1492 * clear other causes using autoclear, for this reason we 1493 * simply create a soft interrupt for all these vectors. 1494 */ 1495 if (reg_icr) 1496 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1497 } else { 1498 /* Re-arm unconditionally */ 1499 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1500 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1501 } 1502 1503 return (FILTER_HANDLED); 1504 } 1505 1506 static void 1507 em_handle_link(void *context) 1508 { 1509 if_ctx_t ctx = context; 1510 struct adapter *adapter = iflib_get_softc(ctx); 1511 1512 adapter->hw.mac.get_link_status = 1; 1513 iflib_admin_intr_deferred(ctx); 1514 } 1515 1516 /********************************************************************* 1517 * 1518 * Media Ioctl callback 1519 * 1520 * This routine is called whenever the user queries the status of 1521 * the interface using ifconfig. 1522 * 1523 **********************************************************************/ 1524 static void 1525 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1526 { 1527 struct adapter *adapter = iflib_get_softc(ctx); 1528 u_char fiber_type = IFM_1000_SX; 1529 1530 INIT_DEBUGOUT("em_if_media_status: begin"); 1531 1532 iflib_admin_intr_deferred(ctx); 1533 1534 ifmr->ifm_status = IFM_AVALID; 1535 ifmr->ifm_active = IFM_ETHER; 1536 1537 if (!adapter->link_active) { 1538 return; 1539 } 1540 1541 ifmr->ifm_status |= IFM_ACTIVE; 1542 1543 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1544 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1545 if (adapter->hw.mac.type == e1000_82545) 1546 fiber_type = IFM_1000_LX; 1547 ifmr->ifm_active |= fiber_type | IFM_FDX; 1548 } else { 1549 switch (adapter->link_speed) { 1550 case 10: 1551 ifmr->ifm_active |= IFM_10_T; 1552 break; 1553 case 100: 1554 ifmr->ifm_active |= IFM_100_TX; 1555 break; 1556 case 1000: 1557 ifmr->ifm_active |= IFM_1000_T; 1558 break; 1559 } 1560 if (adapter->link_duplex == FULL_DUPLEX) 1561 ifmr->ifm_active |= IFM_FDX; 1562 else 1563 ifmr->ifm_active |= IFM_HDX; 1564 } 1565 } 1566 1567 /********************************************************************* 1568 * 1569 * Media Ioctl callback 1570 * 1571 * This routine is called when the user changes speed/duplex using 1572 * media/mediopt option with ifconfig. 1573 * 1574 **********************************************************************/ 1575 static int 1576 em_if_media_change(if_ctx_t ctx) 1577 { 1578 struct adapter *adapter = iflib_get_softc(ctx); 1579 struct ifmedia *ifm = iflib_get_media(ctx); 1580 1581 INIT_DEBUGOUT("em_if_media_change: begin"); 1582 1583 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1584 return (EINVAL); 1585 1586 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1587 case IFM_AUTO: 1588 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1589 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1590 break; 1591 case IFM_1000_LX: 1592 case IFM_1000_SX: 1593 case IFM_1000_T: 1594 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1595 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1596 break; 1597 case IFM_100_TX: 1598 adapter->hw.mac.autoneg = FALSE; 1599 adapter->hw.phy.autoneg_advertised = 0; 1600 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1601 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1602 else 1603 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1604 break; 1605 case IFM_10_T: 1606 adapter->hw.mac.autoneg = FALSE; 1607 adapter->hw.phy.autoneg_advertised = 0; 1608 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1609 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1610 else 1611 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1612 break; 1613 default: 1614 device_printf(adapter->dev, "Unsupported media type\n"); 1615 } 1616 1617 em_if_init(ctx); 1618 1619 return (0); 1620 } 1621 1622 static int 1623 em_if_set_promisc(if_ctx_t ctx, int flags) 1624 { 1625 struct adapter *adapter = iflib_get_softc(ctx); 1626 u32 reg_rctl; 1627 1628 em_disable_promisc(ctx); 1629 1630 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1631 1632 if (flags & IFF_PROMISC) { 1633 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1634 /* Turn this on if you want to see bad packets */ 1635 if (em_debug_sbp) 1636 reg_rctl |= E1000_RCTL_SBP; 1637 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1638 } else if (flags & IFF_ALLMULTI) { 1639 reg_rctl |= E1000_RCTL_MPE; 1640 reg_rctl &= ~E1000_RCTL_UPE; 1641 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1642 } 1643 return (0); 1644 } 1645 1646 static void 1647 em_disable_promisc(if_ctx_t ctx) 1648 { 1649 struct adapter *adapter = iflib_get_softc(ctx); 1650 struct ifnet *ifp = iflib_get_ifp(ctx); 1651 u32 reg_rctl; 1652 int mcnt = 0; 1653 1654 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1655 reg_rctl &= (~E1000_RCTL_UPE); 1656 if (if_getflags(ifp) & IFF_ALLMULTI) 1657 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1658 else 1659 mcnt = if_llmaddr_count(ifp); 1660 /* Don't disable if in MAX groups */ 1661 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1662 reg_rctl &= (~E1000_RCTL_MPE); 1663 reg_rctl &= (~E1000_RCTL_SBP); 1664 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1665 } 1666 1667 1668 static u_int 1669 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1670 { 1671 u8 *mta = arg; 1672 1673 if (cnt == MAX_NUM_MULTICAST_ADDRESSES) 1674 return (1); 1675 1676 bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1677 1678 return (1); 1679 } 1680 1681 /********************************************************************* 1682 * Multicast Update 1683 * 1684 * This routine is called whenever multicast address list is updated. 1685 * 1686 **********************************************************************/ 1687 1688 static void 1689 em_if_multi_set(if_ctx_t ctx) 1690 { 1691 struct adapter *adapter = iflib_get_softc(ctx); 1692 struct ifnet *ifp = iflib_get_ifp(ctx); 1693 u32 reg_rctl = 0; 1694 u8 *mta; /* Multicast array memory */ 1695 int mcnt = 0; 1696 1697 IOCTL_DEBUGOUT("em_set_multi: begin"); 1698 1699 mta = adapter->mta; 1700 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1701 1702 if (adapter->hw.mac.type == e1000_82542 && 1703 adapter->hw.revision_id == E1000_REVISION_2) { 1704 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1705 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1706 e1000_pci_clear_mwi(&adapter->hw); 1707 reg_rctl |= E1000_RCTL_RST; 1708 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1709 msec_delay(5); 1710 } 1711 1712 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1713 1714 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1715 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1716 reg_rctl |= E1000_RCTL_MPE; 1717 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1718 } else 1719 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1720 1721 if (adapter->hw.mac.type == e1000_82542 && 1722 adapter->hw.revision_id == E1000_REVISION_2) { 1723 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1724 reg_rctl &= ~E1000_RCTL_RST; 1725 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1726 msec_delay(5); 1727 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1728 e1000_pci_set_mwi(&adapter->hw); 1729 } 1730 } 1731 1732 /********************************************************************* 1733 * Timer routine 1734 * 1735 * This routine schedules em_if_update_admin_status() to check for 1736 * link status and to gather statistics as well as to perform some 1737 * controller-specific hardware patting. 1738 * 1739 **********************************************************************/ 1740 static void 1741 em_if_timer(if_ctx_t ctx, uint16_t qid) 1742 { 1743 1744 if (qid != 0) 1745 return; 1746 1747 iflib_admin_intr_deferred(ctx); 1748 } 1749 1750 static void 1751 em_if_update_admin_status(if_ctx_t ctx) 1752 { 1753 struct adapter *adapter = iflib_get_softc(ctx); 1754 struct e1000_hw *hw = &adapter->hw; 1755 device_t dev = iflib_get_dev(ctx); 1756 u32 link_check, thstat, ctrl; 1757 1758 link_check = thstat = ctrl = 0; 1759 /* Get the cached link value or read phy for real */ 1760 switch (hw->phy.media_type) { 1761 case e1000_media_type_copper: 1762 if (hw->mac.get_link_status) { 1763 if (hw->mac.type == e1000_pch_spt) 1764 msec_delay(50); 1765 /* Do the work to read phy */ 1766 e1000_check_for_link(hw); 1767 link_check = !hw->mac.get_link_status; 1768 if (link_check) /* ESB2 fix */ 1769 e1000_cfg_on_link_up(hw); 1770 } else { 1771 link_check = TRUE; 1772 } 1773 break; 1774 case e1000_media_type_fiber: 1775 e1000_check_for_link(hw); 1776 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1777 E1000_STATUS_LU); 1778 break; 1779 case e1000_media_type_internal_serdes: 1780 e1000_check_for_link(hw); 1781 link_check = adapter->hw.mac.serdes_has_link; 1782 break; 1783 /* VF device is type_unknown */ 1784 case e1000_media_type_unknown: 1785 e1000_check_for_link(hw); 1786 link_check = !hw->mac.get_link_status; 1787 /* FALLTHROUGH */ 1788 default: 1789 break; 1790 } 1791 1792 /* Check for thermal downshift or shutdown */ 1793 if (hw->mac.type == e1000_i350) { 1794 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1795 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1796 } 1797 1798 /* Now check for a transition */ 1799 if (link_check && (adapter->link_active == 0)) { 1800 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1801 &adapter->link_duplex); 1802 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1803 if ((adapter->link_speed != SPEED_1000) && 1804 ((hw->mac.type == e1000_82571) || 1805 (hw->mac.type == e1000_82572))) { 1806 int tarc0; 1807 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1808 tarc0 &= ~TARC_SPEED_MODE_BIT; 1809 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1810 } 1811 if (bootverbose) 1812 device_printf(dev, "Link is up %d Mbps %s\n", 1813 adapter->link_speed, 1814 ((adapter->link_duplex == FULL_DUPLEX) ? 1815 "Full Duplex" : "Half Duplex")); 1816 adapter->link_active = 1; 1817 adapter->smartspeed = 0; 1818 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1819 E1000_CTRL_EXT_LINK_MODE_GMII && 1820 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1821 device_printf(dev, "Link: thermal downshift\n"); 1822 /* Delay Link Up for Phy update */ 1823 if (((hw->mac.type == e1000_i210) || 1824 (hw->mac.type == e1000_i211)) && 1825 (hw->phy.id == I210_I_PHY_ID)) 1826 msec_delay(I210_LINK_DELAY); 1827 /* Reset if the media type changed. */ 1828 if ((hw->dev_spec._82575.media_changed) && 1829 (adapter->hw.mac.type >= igb_mac_min)) { 1830 hw->dev_spec._82575.media_changed = false; 1831 adapter->flags |= IGB_MEDIA_RESET; 1832 em_reset(ctx); 1833 } 1834 iflib_link_state_change(ctx, LINK_STATE_UP, 1835 IF_Mbps(adapter->link_speed)); 1836 } else if (!link_check && (adapter->link_active == 1)) { 1837 adapter->link_speed = 0; 1838 adapter->link_duplex = 0; 1839 adapter->link_active = 0; 1840 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1841 } 1842 em_update_stats_counters(adapter); 1843 1844 /* Reset LAA into RAR[0] on 82571 */ 1845 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1846 e1000_rar_set(hw, hw->mac.addr, 0); 1847 1848 if (hw->mac.type < em_mac_min) 1849 lem_smartspeed(adapter); 1850 else if (hw->mac.type == e1000_82574 && 1851 adapter->intr_type == IFLIB_INTR_MSIX) 1852 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | 1853 E1000_IMS_LSC); 1854 } 1855 1856 static void 1857 em_if_watchdog_reset(if_ctx_t ctx) 1858 { 1859 struct adapter *adapter = iflib_get_softc(ctx); 1860 1861 /* 1862 * Just count the event; iflib(4) will already trigger a 1863 * sufficient reset of the controller. 1864 */ 1865 adapter->watchdog_events++; 1866 } 1867 1868 /********************************************************************* 1869 * 1870 * This routine disables all traffic on the adapter by issuing a 1871 * global reset on the MAC. 1872 * 1873 **********************************************************************/ 1874 static void 1875 em_if_stop(if_ctx_t ctx) 1876 { 1877 struct adapter *adapter = iflib_get_softc(ctx); 1878 1879 INIT_DEBUGOUT("em_if_stop: begin"); 1880 1881 e1000_reset_hw(&adapter->hw); 1882 if (adapter->hw.mac.type >= e1000_82544) 1883 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1884 1885 e1000_led_off(&adapter->hw); 1886 e1000_cleanup_led(&adapter->hw); 1887 } 1888 1889 /********************************************************************* 1890 * 1891 * Determine hardware revision. 1892 * 1893 **********************************************************************/ 1894 static void 1895 em_identify_hardware(if_ctx_t ctx) 1896 { 1897 device_t dev = iflib_get_dev(ctx); 1898 struct adapter *adapter = iflib_get_softc(ctx); 1899 1900 /* Make sure our PCI config space has the necessary stuff set */ 1901 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1902 1903 /* Save off the information about this board */ 1904 adapter->hw.vendor_id = pci_get_vendor(dev); 1905 adapter->hw.device_id = pci_get_device(dev); 1906 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1907 adapter->hw.subsystem_vendor_id = 1908 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1909 adapter->hw.subsystem_device_id = 1910 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1911 1912 /* Do Shared Code Init and Setup */ 1913 if (e1000_set_mac_type(&adapter->hw)) { 1914 device_printf(dev, "Setup init failure\n"); 1915 return; 1916 } 1917 } 1918 1919 static int 1920 em_allocate_pci_resources(if_ctx_t ctx) 1921 { 1922 struct adapter *adapter = iflib_get_softc(ctx); 1923 device_t dev = iflib_get_dev(ctx); 1924 int rid, val; 1925 1926 rid = PCIR_BAR(0); 1927 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1928 &rid, RF_ACTIVE); 1929 if (adapter->memory == NULL) { 1930 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1931 return (ENXIO); 1932 } 1933 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1934 adapter->osdep.mem_bus_space_handle = 1935 rman_get_bushandle(adapter->memory); 1936 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1937 1938 /* Only older adapters use IO mapping */ 1939 if (adapter->hw.mac.type < em_mac_min && 1940 adapter->hw.mac.type > e1000_82543) { 1941 /* Figure our where our IO BAR is ? */ 1942 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1943 val = pci_read_config(dev, rid, 4); 1944 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1945 break; 1946 } 1947 rid += 4; 1948 /* check for 64bit BAR */ 1949 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1950 rid += 4; 1951 } 1952 if (rid >= PCIR_CIS) { 1953 device_printf(dev, "Unable to locate IO BAR\n"); 1954 return (ENXIO); 1955 } 1956 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1957 &rid, RF_ACTIVE); 1958 if (adapter->ioport == NULL) { 1959 device_printf(dev, "Unable to allocate bus resource: " 1960 "ioport\n"); 1961 return (ENXIO); 1962 } 1963 adapter->hw.io_base = 0; 1964 adapter->osdep.io_bus_space_tag = 1965 rman_get_bustag(adapter->ioport); 1966 adapter->osdep.io_bus_space_handle = 1967 rman_get_bushandle(adapter->ioport); 1968 } 1969 1970 adapter->hw.back = &adapter->osdep; 1971 1972 return (0); 1973 } 1974 1975 /********************************************************************* 1976 * 1977 * Set up the MSI-X Interrupt handlers 1978 * 1979 **********************************************************************/ 1980 static int 1981 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1982 { 1983 struct adapter *adapter = iflib_get_softc(ctx); 1984 struct em_rx_queue *rx_que = adapter->rx_queues; 1985 struct em_tx_queue *tx_que = adapter->tx_queues; 1986 int error, rid, i, vector = 0, rx_vectors; 1987 char buf[16]; 1988 1989 /* First set up ring resources */ 1990 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1991 rid = vector + 1; 1992 snprintf(buf, sizeof(buf), "rxq%d", i); 1993 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1994 if (error) { 1995 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1996 adapter->rx_num_queues = i + 1; 1997 goto fail; 1998 } 1999 2000 rx_que->msix = vector; 2001 2002 /* 2003 * Set the bit to enable interrupt 2004 * in E1000_IMS -- bits 20 and 21 2005 * are for RX0 and RX1, note this has 2006 * NOTHING to do with the MSI-X vector 2007 */ 2008 if (adapter->hw.mac.type == e1000_82574) { 2009 rx_que->eims = 1 << (20 + i); 2010 adapter->ims |= rx_que->eims; 2011 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2012 } else if (adapter->hw.mac.type == e1000_82575) 2013 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2014 else 2015 rx_que->eims = 1 << vector; 2016 } 2017 rx_vectors = vector; 2018 2019 vector = 0; 2020 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2021 snprintf(buf, sizeof(buf), "txq%d", i); 2022 tx_que = &adapter->tx_queues[i]; 2023 iflib_softirq_alloc_generic(ctx, 2024 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2025 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2026 2027 tx_que->msix = (vector % adapter->rx_num_queues); 2028 2029 /* 2030 * Set the bit to enable interrupt 2031 * in E1000_IMS -- bits 22 and 23 2032 * are for TX0 and TX1, note this has 2033 * NOTHING to do with the MSI-X vector 2034 */ 2035 if (adapter->hw.mac.type == e1000_82574) { 2036 tx_que->eims = 1 << (22 + i); 2037 adapter->ims |= tx_que->eims; 2038 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2039 } else if (adapter->hw.mac.type == e1000_82575) { 2040 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2041 } else { 2042 tx_que->eims = 1 << i; 2043 } 2044 } 2045 2046 /* Link interrupt */ 2047 rid = rx_vectors + 1; 2048 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2049 2050 if (error) { 2051 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2052 goto fail; 2053 } 2054 adapter->linkvec = rx_vectors; 2055 if (adapter->hw.mac.type < igb_mac_min) { 2056 adapter->ivars |= (8 | rx_vectors) << 16; 2057 adapter->ivars |= 0x80000000; 2058 } 2059 return (0); 2060 fail: 2061 iflib_irq_free(ctx, &adapter->irq); 2062 rx_que = adapter->rx_queues; 2063 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2064 iflib_irq_free(ctx, &rx_que->que_irq); 2065 return (error); 2066 } 2067 2068 static void 2069 igb_configure_queues(struct adapter *adapter) 2070 { 2071 struct e1000_hw *hw = &adapter->hw; 2072 struct em_rx_queue *rx_que; 2073 struct em_tx_queue *tx_que; 2074 u32 tmp, ivar = 0, newitr = 0; 2075 2076 /* First turn on RSS capability */ 2077 if (adapter->hw.mac.type != e1000_82575) 2078 E1000_WRITE_REG(hw, E1000_GPIE, 2079 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2080 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2081 2082 /* Turn on MSI-X */ 2083 switch (adapter->hw.mac.type) { 2084 case e1000_82580: 2085 case e1000_i350: 2086 case e1000_i354: 2087 case e1000_i210: 2088 case e1000_i211: 2089 case e1000_vfadapt: 2090 case e1000_vfadapt_i350: 2091 /* RX entries */ 2092 for (int i = 0; i < adapter->rx_num_queues; i++) { 2093 u32 index = i >> 1; 2094 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2095 rx_que = &adapter->rx_queues[i]; 2096 if (i & 1) { 2097 ivar &= 0xFF00FFFF; 2098 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2099 } else { 2100 ivar &= 0xFFFFFF00; 2101 ivar |= rx_que->msix | E1000_IVAR_VALID; 2102 } 2103 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2104 } 2105 /* TX entries */ 2106 for (int i = 0; i < adapter->tx_num_queues; i++) { 2107 u32 index = i >> 1; 2108 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2109 tx_que = &adapter->tx_queues[i]; 2110 if (i & 1) { 2111 ivar &= 0x00FFFFFF; 2112 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2113 } else { 2114 ivar &= 0xFFFF00FF; 2115 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2116 } 2117 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2118 adapter->que_mask |= tx_que->eims; 2119 } 2120 2121 /* And for the link interrupt */ 2122 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2123 adapter->link_mask = 1 << adapter->linkvec; 2124 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2125 break; 2126 case e1000_82576: 2127 /* RX entries */ 2128 for (int i = 0; i < adapter->rx_num_queues; i++) { 2129 u32 index = i & 0x7; /* Each IVAR has two entries */ 2130 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2131 rx_que = &adapter->rx_queues[i]; 2132 if (i < 8) { 2133 ivar &= 0xFFFFFF00; 2134 ivar |= rx_que->msix | E1000_IVAR_VALID; 2135 } else { 2136 ivar &= 0xFF00FFFF; 2137 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2138 } 2139 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2140 adapter->que_mask |= rx_que->eims; 2141 } 2142 /* TX entries */ 2143 for (int i = 0; i < adapter->tx_num_queues; i++) { 2144 u32 index = i & 0x7; /* Each IVAR has two entries */ 2145 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2146 tx_que = &adapter->tx_queues[i]; 2147 if (i < 8) { 2148 ivar &= 0xFFFF00FF; 2149 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2150 } else { 2151 ivar &= 0x00FFFFFF; 2152 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2153 } 2154 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2155 adapter->que_mask |= tx_que->eims; 2156 } 2157 2158 /* And for the link interrupt */ 2159 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2160 adapter->link_mask = 1 << adapter->linkvec; 2161 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2162 break; 2163 2164 case e1000_82575: 2165 /* enable MSI-X support*/ 2166 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2167 tmp |= E1000_CTRL_EXT_PBA_CLR; 2168 /* Auto-Mask interrupts upon ICR read. */ 2169 tmp |= E1000_CTRL_EXT_EIAME; 2170 tmp |= E1000_CTRL_EXT_IRCA; 2171 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2172 2173 /* Queues */ 2174 for (int i = 0; i < adapter->rx_num_queues; i++) { 2175 rx_que = &adapter->rx_queues[i]; 2176 tmp = E1000_EICR_RX_QUEUE0 << i; 2177 tmp |= E1000_EICR_TX_QUEUE0 << i; 2178 rx_que->eims = tmp; 2179 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2180 i, rx_que->eims); 2181 adapter->que_mask |= rx_que->eims; 2182 } 2183 2184 /* Link */ 2185 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2186 E1000_EIMS_OTHER); 2187 adapter->link_mask |= E1000_EIMS_OTHER; 2188 default: 2189 break; 2190 } 2191 2192 /* Set the starting interrupt rate */ 2193 if (em_max_interrupt_rate > 0) 2194 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2195 2196 if (hw->mac.type == e1000_82575) 2197 newitr |= newitr << 16; 2198 else 2199 newitr |= E1000_EITR_CNT_IGNR; 2200 2201 for (int i = 0; i < adapter->rx_num_queues; i++) { 2202 rx_que = &adapter->rx_queues[i]; 2203 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2204 } 2205 2206 return; 2207 } 2208 2209 static void 2210 em_free_pci_resources(if_ctx_t ctx) 2211 { 2212 struct adapter *adapter = iflib_get_softc(ctx); 2213 struct em_rx_queue *que = adapter->rx_queues; 2214 device_t dev = iflib_get_dev(ctx); 2215 2216 /* Release all MSI-X queue resources */ 2217 if (adapter->intr_type == IFLIB_INTR_MSIX) 2218 iflib_irq_free(ctx, &adapter->irq); 2219 2220 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2221 iflib_irq_free(ctx, &que->que_irq); 2222 } 2223 2224 if (adapter->memory != NULL) { 2225 bus_release_resource(dev, SYS_RES_MEMORY, 2226 rman_get_rid(adapter->memory), adapter->memory); 2227 adapter->memory = NULL; 2228 } 2229 2230 if (adapter->flash != NULL) { 2231 bus_release_resource(dev, SYS_RES_MEMORY, 2232 rman_get_rid(adapter->flash), adapter->flash); 2233 adapter->flash = NULL; 2234 } 2235 2236 if (adapter->ioport != NULL) { 2237 bus_release_resource(dev, SYS_RES_IOPORT, 2238 rman_get_rid(adapter->ioport), adapter->ioport); 2239 adapter->ioport = NULL; 2240 } 2241 } 2242 2243 /* Set up MSI or MSI-X */ 2244 static int 2245 em_setup_msix(if_ctx_t ctx) 2246 { 2247 struct adapter *adapter = iflib_get_softc(ctx); 2248 2249 if (adapter->hw.mac.type == e1000_82574) { 2250 em_enable_vectors_82574(ctx); 2251 } 2252 return (0); 2253 } 2254 2255 /********************************************************************* 2256 * 2257 * Workaround for SmartSpeed on 82541 and 82547 controllers 2258 * 2259 **********************************************************************/ 2260 static void 2261 lem_smartspeed(struct adapter *adapter) 2262 { 2263 u16 phy_tmp; 2264 2265 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2266 adapter->hw.mac.autoneg == 0 || 2267 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2268 return; 2269 2270 if (adapter->smartspeed == 0) { 2271 /* If Master/Slave config fault is asserted twice, 2272 * we assume back-to-back */ 2273 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2274 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2275 return; 2276 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2277 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2278 e1000_read_phy_reg(&adapter->hw, 2279 PHY_1000T_CTRL, &phy_tmp); 2280 if(phy_tmp & CR_1000T_MS_ENABLE) { 2281 phy_tmp &= ~CR_1000T_MS_ENABLE; 2282 e1000_write_phy_reg(&adapter->hw, 2283 PHY_1000T_CTRL, phy_tmp); 2284 adapter->smartspeed++; 2285 if(adapter->hw.mac.autoneg && 2286 !e1000_copper_link_autoneg(&adapter->hw) && 2287 !e1000_read_phy_reg(&adapter->hw, 2288 PHY_CONTROL, &phy_tmp)) { 2289 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2290 MII_CR_RESTART_AUTO_NEG); 2291 e1000_write_phy_reg(&adapter->hw, 2292 PHY_CONTROL, phy_tmp); 2293 } 2294 } 2295 } 2296 return; 2297 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2298 /* If still no link, perhaps using 2/3 pair cable */ 2299 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2300 phy_tmp |= CR_1000T_MS_ENABLE; 2301 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2302 if(adapter->hw.mac.autoneg && 2303 !e1000_copper_link_autoneg(&adapter->hw) && 2304 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2305 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2306 MII_CR_RESTART_AUTO_NEG); 2307 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2308 } 2309 } 2310 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2311 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2312 adapter->smartspeed = 0; 2313 } 2314 2315 /********************************************************************* 2316 * 2317 * Initialize the DMA Coalescing feature 2318 * 2319 **********************************************************************/ 2320 static void 2321 igb_init_dmac(struct adapter *adapter, u32 pba) 2322 { 2323 device_t dev = adapter->dev; 2324 struct e1000_hw *hw = &adapter->hw; 2325 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2326 u16 hwm; 2327 u16 max_frame_size; 2328 2329 if (hw->mac.type == e1000_i211) 2330 return; 2331 2332 max_frame_size = adapter->shared->isc_max_frame_size; 2333 if (hw->mac.type > e1000_82580) { 2334 2335 if (adapter->dmac == 0) { /* Disabling it */ 2336 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2337 return; 2338 } else 2339 device_printf(dev, "DMA Coalescing enabled\n"); 2340 2341 /* Set starting threshold */ 2342 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2343 2344 hwm = 64 * pba - max_frame_size / 16; 2345 if (hwm < 64 * (pba - 6)) 2346 hwm = 64 * (pba - 6); 2347 reg = E1000_READ_REG(hw, E1000_FCRTC); 2348 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2349 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2350 & E1000_FCRTC_RTH_COAL_MASK); 2351 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2352 2353 2354 dmac = pba - max_frame_size / 512; 2355 if (dmac < pba - 10) 2356 dmac = pba - 10; 2357 reg = E1000_READ_REG(hw, E1000_DMACR); 2358 reg &= ~E1000_DMACR_DMACTHR_MASK; 2359 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2360 & E1000_DMACR_DMACTHR_MASK); 2361 2362 /* transition to L0x or L1 if available..*/ 2363 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2364 2365 /* Check if status is 2.5Gb backplane connection 2366 * before configuration of watchdog timer, which is 2367 * in msec values in 12.8usec intervals 2368 * watchdog timer= msec values in 32usec intervals 2369 * for non 2.5Gb connection 2370 */ 2371 if (hw->mac.type == e1000_i354) { 2372 int status = E1000_READ_REG(hw, E1000_STATUS); 2373 if ((status & E1000_STATUS_2P5_SKU) && 2374 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2375 reg |= ((adapter->dmac * 5) >> 6); 2376 else 2377 reg |= (adapter->dmac >> 5); 2378 } else { 2379 reg |= (adapter->dmac >> 5); 2380 } 2381 2382 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2383 2384 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2385 2386 /* Set the interval before transition */ 2387 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2388 if (hw->mac.type == e1000_i350) 2389 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2390 /* 2391 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2392 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2393 */ 2394 if (hw->mac.type == e1000_i354) { 2395 int status = E1000_READ_REG(hw, E1000_STATUS); 2396 if ((status & E1000_STATUS_2P5_SKU) && 2397 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2398 reg |= 0xA; 2399 else 2400 reg |= 0x4; 2401 } else { 2402 reg |= 0x4; 2403 } 2404 2405 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2406 2407 /* free space in tx packet buffer to wake from DMA coal */ 2408 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2409 (2 * max_frame_size)) >> 6); 2410 2411 /* make low power state decision controlled by DMA coal */ 2412 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2413 reg &= ~E1000_PCIEMISC_LX_DECISION; 2414 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2415 2416 } else if (hw->mac.type == e1000_82580) { 2417 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2418 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2419 reg & ~E1000_PCIEMISC_LX_DECISION); 2420 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2421 } 2422 } 2423 2424 /********************************************************************* 2425 * 2426 * Initialize the hardware to a configuration as specified by the 2427 * adapter structure. 2428 * 2429 **********************************************************************/ 2430 static void 2431 em_reset(if_ctx_t ctx) 2432 { 2433 device_t dev = iflib_get_dev(ctx); 2434 struct adapter *adapter = iflib_get_softc(ctx); 2435 struct ifnet *ifp = iflib_get_ifp(ctx); 2436 struct e1000_hw *hw = &adapter->hw; 2437 u16 rx_buffer_size; 2438 u32 pba; 2439 2440 INIT_DEBUGOUT("em_reset: begin"); 2441 /* Let the firmware know the OS is in control */ 2442 em_get_hw_control(adapter); 2443 2444 /* Set up smart power down as default off on newer adapters. */ 2445 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2446 hw->mac.type == e1000_82572)) { 2447 u16 phy_tmp = 0; 2448 2449 /* Speed up time to link by disabling smart power down. */ 2450 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2451 phy_tmp &= ~IGP02E1000_PM_SPD; 2452 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2453 } 2454 2455 /* 2456 * Packet Buffer Allocation (PBA) 2457 * Writing PBA sets the receive portion of the buffer 2458 * the remainder is used for the transmit buffer. 2459 */ 2460 switch (hw->mac.type) { 2461 /* Total Packet Buffer on these is 48K */ 2462 case e1000_82571: 2463 case e1000_82572: 2464 case e1000_80003es2lan: 2465 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2466 break; 2467 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2468 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2469 break; 2470 case e1000_82574: 2471 case e1000_82583: 2472 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2473 break; 2474 case e1000_ich8lan: 2475 pba = E1000_PBA_8K; 2476 break; 2477 case e1000_ich9lan: 2478 case e1000_ich10lan: 2479 /* Boost Receive side for jumbo frames */ 2480 if (adapter->hw.mac.max_frame_size > 4096) 2481 pba = E1000_PBA_14K; 2482 else 2483 pba = E1000_PBA_10K; 2484 break; 2485 case e1000_pchlan: 2486 case e1000_pch2lan: 2487 case e1000_pch_lpt: 2488 case e1000_pch_spt: 2489 case e1000_pch_cnp: 2490 pba = E1000_PBA_26K; 2491 break; 2492 case e1000_82575: 2493 pba = E1000_PBA_32K; 2494 break; 2495 case e1000_82576: 2496 case e1000_vfadapt: 2497 pba = E1000_READ_REG(hw, E1000_RXPBS); 2498 pba &= E1000_RXPBS_SIZE_MASK_82576; 2499 break; 2500 case e1000_82580: 2501 case e1000_i350: 2502 case e1000_i354: 2503 case e1000_vfadapt_i350: 2504 pba = E1000_READ_REG(hw, E1000_RXPBS); 2505 pba = e1000_rxpbs_adjust_82580(pba); 2506 break; 2507 case e1000_i210: 2508 case e1000_i211: 2509 pba = E1000_PBA_34K; 2510 break; 2511 default: 2512 if (adapter->hw.mac.max_frame_size > 8192) 2513 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2514 else 2515 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2516 } 2517 2518 /* Special needs in case of Jumbo frames */ 2519 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2520 u32 tx_space, min_tx, min_rx; 2521 pba = E1000_READ_REG(hw, E1000_PBA); 2522 tx_space = pba >> 16; 2523 pba &= 0xffff; 2524 min_tx = (adapter->hw.mac.max_frame_size + 2525 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2526 min_tx = roundup2(min_tx, 1024); 2527 min_tx >>= 10; 2528 min_rx = adapter->hw.mac.max_frame_size; 2529 min_rx = roundup2(min_rx, 1024); 2530 min_rx >>= 10; 2531 if (tx_space < min_tx && 2532 ((min_tx - tx_space) < pba)) { 2533 pba = pba - (min_tx - tx_space); 2534 /* 2535 * if short on rx space, rx wins 2536 * and must trump tx adjustment 2537 */ 2538 if (pba < min_rx) 2539 pba = min_rx; 2540 } 2541 E1000_WRITE_REG(hw, E1000_PBA, pba); 2542 } 2543 2544 if (hw->mac.type < igb_mac_min) 2545 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2546 2547 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2548 2549 /* 2550 * These parameters control the automatic generation (Tx) and 2551 * response (Rx) to Ethernet PAUSE frames. 2552 * - High water mark should allow for at least two frames to be 2553 * received after sending an XOFF. 2554 * - Low water mark works best when it is very near the high water mark. 2555 * This allows the receiver to restart by sending XON when it has 2556 * drained a bit. Here we use an arbitrary value of 1500 which will 2557 * restart after one full frame is pulled from the buffer. There 2558 * could be several smaller frames in the buffer and if so they will 2559 * not trigger the XON until their total number reduces the buffer 2560 * by 1500. 2561 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2562 */ 2563 rx_buffer_size = (pba & 0xffff) << 10; 2564 hw->fc.high_water = rx_buffer_size - 2565 roundup2(adapter->hw.mac.max_frame_size, 1024); 2566 hw->fc.low_water = hw->fc.high_water - 1500; 2567 2568 if (adapter->fc) /* locally set flow control value? */ 2569 hw->fc.requested_mode = adapter->fc; 2570 else 2571 hw->fc.requested_mode = e1000_fc_full; 2572 2573 if (hw->mac.type == e1000_80003es2lan) 2574 hw->fc.pause_time = 0xFFFF; 2575 else 2576 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2577 2578 hw->fc.send_xon = TRUE; 2579 2580 /* Device specific overrides/settings */ 2581 switch (hw->mac.type) { 2582 case e1000_pchlan: 2583 /* Workaround: no TX flow ctrl for PCH */ 2584 hw->fc.requested_mode = e1000_fc_rx_pause; 2585 hw->fc.pause_time = 0xFFFF; /* override */ 2586 if (if_getmtu(ifp) > ETHERMTU) { 2587 hw->fc.high_water = 0x3500; 2588 hw->fc.low_water = 0x1500; 2589 } else { 2590 hw->fc.high_water = 0x5000; 2591 hw->fc.low_water = 0x3000; 2592 } 2593 hw->fc.refresh_time = 0x1000; 2594 break; 2595 case e1000_pch2lan: 2596 case e1000_pch_lpt: 2597 case e1000_pch_spt: 2598 case e1000_pch_cnp: 2599 hw->fc.high_water = 0x5C20; 2600 hw->fc.low_water = 0x5048; 2601 hw->fc.pause_time = 0x0650; 2602 hw->fc.refresh_time = 0x0400; 2603 /* Jumbos need adjusted PBA */ 2604 if (if_getmtu(ifp) > ETHERMTU) 2605 E1000_WRITE_REG(hw, E1000_PBA, 12); 2606 else 2607 E1000_WRITE_REG(hw, E1000_PBA, 26); 2608 break; 2609 case e1000_82575: 2610 case e1000_82576: 2611 /* 8-byte granularity */ 2612 hw->fc.low_water = hw->fc.high_water - 8; 2613 break; 2614 case e1000_82580: 2615 case e1000_i350: 2616 case e1000_i354: 2617 case e1000_i210: 2618 case e1000_i211: 2619 case e1000_vfadapt: 2620 case e1000_vfadapt_i350: 2621 /* 16-byte granularity */ 2622 hw->fc.low_water = hw->fc.high_water - 16; 2623 break; 2624 case e1000_ich9lan: 2625 case e1000_ich10lan: 2626 if (if_getmtu(ifp) > ETHERMTU) { 2627 hw->fc.high_water = 0x2800; 2628 hw->fc.low_water = hw->fc.high_water - 8; 2629 break; 2630 } 2631 /* FALLTHROUGH */ 2632 default: 2633 if (hw->mac.type == e1000_80003es2lan) 2634 hw->fc.pause_time = 0xFFFF; 2635 break; 2636 } 2637 2638 /* Issue a global reset */ 2639 e1000_reset_hw(hw); 2640 if (adapter->hw.mac.type >= igb_mac_min) { 2641 E1000_WRITE_REG(hw, E1000_WUC, 0); 2642 } else { 2643 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2644 em_disable_aspm(adapter); 2645 } 2646 if (adapter->flags & IGB_MEDIA_RESET) { 2647 e1000_setup_init_funcs(hw, TRUE); 2648 e1000_get_bus_info(hw); 2649 adapter->flags &= ~IGB_MEDIA_RESET; 2650 } 2651 /* and a re-init */ 2652 if (e1000_init_hw(hw) < 0) { 2653 device_printf(dev, "Hardware Initialization Failed\n"); 2654 return; 2655 } 2656 if (adapter->hw.mac.type >= igb_mac_min) 2657 igb_init_dmac(adapter, pba); 2658 2659 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2660 e1000_get_phy_info(hw); 2661 e1000_check_for_link(hw); 2662 } 2663 2664 /* 2665 * Initialise the RSS mapping for NICs that support multiple transmit/ 2666 * receive rings. 2667 */ 2668 2669 #define RSSKEYLEN 10 2670 static void 2671 em_initialize_rss_mapping(struct adapter *adapter) 2672 { 2673 uint8_t rss_key[4 * RSSKEYLEN]; 2674 uint32_t reta = 0; 2675 struct e1000_hw *hw = &adapter->hw; 2676 int i; 2677 2678 /* 2679 * Configure RSS key 2680 */ 2681 arc4rand(rss_key, sizeof(rss_key), 0); 2682 for (i = 0; i < RSSKEYLEN; ++i) { 2683 uint32_t rssrk = 0; 2684 2685 rssrk = EM_RSSRK_VAL(rss_key, i); 2686 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2687 } 2688 2689 /* 2690 * Configure RSS redirect table in following fashion: 2691 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2692 */ 2693 for (i = 0; i < sizeof(reta); ++i) { 2694 uint32_t q; 2695 2696 q = (i % adapter->rx_num_queues) << 7; 2697 reta |= q << (8 * i); 2698 } 2699 2700 for (i = 0; i < 32; ++i) 2701 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2702 2703 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2704 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2705 E1000_MRQC_RSS_FIELD_IPV4 | 2706 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2707 E1000_MRQC_RSS_FIELD_IPV6_EX | 2708 E1000_MRQC_RSS_FIELD_IPV6); 2709 } 2710 2711 static void 2712 igb_initialize_rss_mapping(struct adapter *adapter) 2713 { 2714 struct e1000_hw *hw = &adapter->hw; 2715 int i; 2716 int queue_id; 2717 u32 reta; 2718 u32 rss_key[10], mrqc, shift = 0; 2719 2720 /* XXX? */ 2721 if (adapter->hw.mac.type == e1000_82575) 2722 shift = 6; 2723 2724 /* 2725 * The redirection table controls which destination 2726 * queue each bucket redirects traffic to. 2727 * Each DWORD represents four queues, with the LSB 2728 * being the first queue in the DWORD. 2729 * 2730 * This just allocates buckets to queues using round-robin 2731 * allocation. 2732 * 2733 * NOTE: It Just Happens to line up with the default 2734 * RSS allocation method. 2735 */ 2736 2737 /* Warning FM follows */ 2738 reta = 0; 2739 for (i = 0; i < 128; i++) { 2740 #ifdef RSS 2741 queue_id = rss_get_indirection_to_bucket(i); 2742 /* 2743 * If we have more queues than buckets, we'll 2744 * end up mapping buckets to a subset of the 2745 * queues. 2746 * 2747 * If we have more buckets than queues, we'll 2748 * end up instead assigning multiple buckets 2749 * to queues. 2750 * 2751 * Both are suboptimal, but we need to handle 2752 * the case so we don't go out of bounds 2753 * indexing arrays and such. 2754 */ 2755 queue_id = queue_id % adapter->rx_num_queues; 2756 #else 2757 queue_id = (i % adapter->rx_num_queues); 2758 #endif 2759 /* Adjust if required */ 2760 queue_id = queue_id << shift; 2761 2762 /* 2763 * The low 8 bits are for hash value (n+0); 2764 * The next 8 bits are for hash value (n+1), etc. 2765 */ 2766 reta = reta >> 8; 2767 reta = reta | ( ((uint32_t) queue_id) << 24); 2768 if ((i & 3) == 3) { 2769 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2770 reta = 0; 2771 } 2772 } 2773 2774 /* Now fill in hash table */ 2775 2776 /* 2777 * MRQC: Multiple Receive Queues Command 2778 * Set queuing to RSS control, number depends on the device. 2779 */ 2780 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2781 2782 #ifdef RSS 2783 /* XXX ew typecasting */ 2784 rss_getkey((uint8_t *) &rss_key); 2785 #else 2786 arc4rand(&rss_key, sizeof(rss_key), 0); 2787 #endif 2788 for (i = 0; i < 10; i++) 2789 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2790 2791 /* 2792 * Configure the RSS fields to hash upon. 2793 */ 2794 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2795 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2796 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2797 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2798 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2799 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2800 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2801 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2802 2803 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2804 } 2805 2806 /********************************************************************* 2807 * 2808 * Setup networking device structure and register interface media. 2809 * 2810 **********************************************************************/ 2811 static int 2812 em_setup_interface(if_ctx_t ctx) 2813 { 2814 struct ifnet *ifp = iflib_get_ifp(ctx); 2815 struct adapter *adapter = iflib_get_softc(ctx); 2816 if_softc_ctx_t scctx = adapter->shared; 2817 2818 INIT_DEBUGOUT("em_setup_interface: begin"); 2819 2820 /* Single Queue */ 2821 if (adapter->tx_num_queues == 1) { 2822 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2823 if_setsendqready(ifp); 2824 } 2825 2826 /* 2827 * Specify the media types supported by this adapter and register 2828 * callbacks to update media and link information 2829 */ 2830 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2831 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2832 u_char fiber_type = IFM_1000_SX; /* default type */ 2833 2834 if (adapter->hw.mac.type == e1000_82545) 2835 fiber_type = IFM_1000_LX; 2836 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2837 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2838 } else { 2839 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2840 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2841 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2842 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2843 if (adapter->hw.phy.type != e1000_phy_ife) { 2844 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2845 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2846 } 2847 } 2848 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2849 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2850 return (0); 2851 } 2852 2853 static int 2854 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2855 { 2856 struct adapter *adapter = iflib_get_softc(ctx); 2857 if_softc_ctx_t scctx = adapter->shared; 2858 int error = E1000_SUCCESS; 2859 struct em_tx_queue *que; 2860 int i, j; 2861 2862 MPASS(adapter->tx_num_queues > 0); 2863 MPASS(adapter->tx_num_queues == ntxqsets); 2864 2865 /* First allocate the top level queue structs */ 2866 if (!(adapter->tx_queues = 2867 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2868 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2869 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2870 return(ENOMEM); 2871 } 2872 2873 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2874 /* Set up some basics */ 2875 2876 struct tx_ring *txr = &que->txr; 2877 txr->adapter = que->adapter = adapter; 2878 que->me = txr->me = i; 2879 2880 /* Allocate report status array */ 2881 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2882 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2883 error = ENOMEM; 2884 goto fail; 2885 } 2886 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2887 txr->tx_rsq[j] = QIDX_INVALID; 2888 /* get the virtual and physical address of the hardware queues */ 2889 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2890 txr->tx_paddr = paddrs[i*ntxqs]; 2891 } 2892 2893 if (bootverbose) 2894 device_printf(iflib_get_dev(ctx), 2895 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2896 return (0); 2897 fail: 2898 em_if_queues_free(ctx); 2899 return (error); 2900 } 2901 2902 static int 2903 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2904 { 2905 struct adapter *adapter = iflib_get_softc(ctx); 2906 int error = E1000_SUCCESS; 2907 struct em_rx_queue *que; 2908 int i; 2909 2910 MPASS(adapter->rx_num_queues > 0); 2911 MPASS(adapter->rx_num_queues == nrxqsets); 2912 2913 /* First allocate the top level queue structs */ 2914 if (!(adapter->rx_queues = 2915 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2916 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2917 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2918 error = ENOMEM; 2919 goto fail; 2920 } 2921 2922 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2923 /* Set up some basics */ 2924 struct rx_ring *rxr = &que->rxr; 2925 rxr->adapter = que->adapter = adapter; 2926 rxr->que = que; 2927 que->me = rxr->me = i; 2928 2929 /* get the virtual and physical address of the hardware queues */ 2930 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2931 rxr->rx_paddr = paddrs[i*nrxqs]; 2932 } 2933 2934 if (bootverbose) 2935 device_printf(iflib_get_dev(ctx), 2936 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2937 2938 return (0); 2939 fail: 2940 em_if_queues_free(ctx); 2941 return (error); 2942 } 2943 2944 static void 2945 em_if_queues_free(if_ctx_t ctx) 2946 { 2947 struct adapter *adapter = iflib_get_softc(ctx); 2948 struct em_tx_queue *tx_que = adapter->tx_queues; 2949 struct em_rx_queue *rx_que = adapter->rx_queues; 2950 2951 if (tx_que != NULL) { 2952 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2953 struct tx_ring *txr = &tx_que->txr; 2954 if (txr->tx_rsq == NULL) 2955 break; 2956 2957 free(txr->tx_rsq, M_DEVBUF); 2958 txr->tx_rsq = NULL; 2959 } 2960 free(adapter->tx_queues, M_DEVBUF); 2961 adapter->tx_queues = NULL; 2962 } 2963 2964 if (rx_que != NULL) { 2965 free(adapter->rx_queues, M_DEVBUF); 2966 adapter->rx_queues = NULL; 2967 } 2968 2969 em_release_hw_control(adapter); 2970 2971 if (adapter->mta != NULL) { 2972 free(adapter->mta, M_DEVBUF); 2973 } 2974 } 2975 2976 /********************************************************************* 2977 * 2978 * Enable transmit unit. 2979 * 2980 **********************************************************************/ 2981 static void 2982 em_initialize_transmit_unit(if_ctx_t ctx) 2983 { 2984 struct adapter *adapter = iflib_get_softc(ctx); 2985 if_softc_ctx_t scctx = adapter->shared; 2986 struct em_tx_queue *que; 2987 struct tx_ring *txr; 2988 struct e1000_hw *hw = &adapter->hw; 2989 u32 tctl, txdctl = 0, tarc, tipg = 0; 2990 2991 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2992 2993 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2994 u64 bus_addr; 2995 caddr_t offp, endp; 2996 2997 que = &adapter->tx_queues[i]; 2998 txr = &que->txr; 2999 bus_addr = txr->tx_paddr; 3000 3001 /* Clear checksum offload context. */ 3002 offp = (caddr_t)&txr->csum_flags; 3003 endp = (caddr_t)(txr + 1); 3004 bzero(offp, endp - offp); 3005 3006 /* Base and Len of TX Ring */ 3007 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3008 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3009 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3010 (u32)(bus_addr >> 32)); 3011 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3012 (u32)bus_addr); 3013 /* Init the HEAD/TAIL indices */ 3014 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3015 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3016 3017 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3018 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 3019 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 3020 3021 txdctl = 0; /* clear txdctl */ 3022 txdctl |= 0x1f; /* PTHRESH */ 3023 txdctl |= 1 << 8; /* HTHRESH */ 3024 txdctl |= 1 << 16;/* WTHRESH */ 3025 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3026 txdctl |= E1000_TXDCTL_GRAN; 3027 txdctl |= 1 << 25; /* LWTHRESH */ 3028 3029 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3030 } 3031 3032 /* Set the default values for the Tx Inter Packet Gap timer */ 3033 switch (adapter->hw.mac.type) { 3034 case e1000_80003es2lan: 3035 tipg = DEFAULT_82543_TIPG_IPGR1; 3036 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3037 E1000_TIPG_IPGR2_SHIFT; 3038 break; 3039 case e1000_82542: 3040 tipg = DEFAULT_82542_TIPG_IPGT; 3041 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3042 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3043 break; 3044 default: 3045 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3046 (adapter->hw.phy.media_type == 3047 e1000_media_type_internal_serdes)) 3048 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3049 else 3050 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3051 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3052 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3053 } 3054 3055 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3056 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3057 3058 if(adapter->hw.mac.type >= e1000_82540) 3059 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3060 adapter->tx_abs_int_delay.value); 3061 3062 if ((adapter->hw.mac.type == e1000_82571) || 3063 (adapter->hw.mac.type == e1000_82572)) { 3064 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3065 tarc |= TARC_SPEED_MODE_BIT; 3066 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3067 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3068 /* errata: program both queues to unweighted RR */ 3069 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3070 tarc |= 1; 3071 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3072 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3073 tarc |= 1; 3074 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3075 } else if (adapter->hw.mac.type == e1000_82574) { 3076 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3077 tarc |= TARC_ERRATA_BIT; 3078 if ( adapter->tx_num_queues > 1) { 3079 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3080 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3081 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3082 } else 3083 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3084 } 3085 3086 if (adapter->tx_int_delay.value > 0) 3087 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3088 3089 /* Program the Transmit Control Register */ 3090 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3091 tctl &= ~E1000_TCTL_CT; 3092 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3093 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3094 3095 if (adapter->hw.mac.type >= e1000_82571) 3096 tctl |= E1000_TCTL_MULR; 3097 3098 /* This write will effectively turn on the transmit unit. */ 3099 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3100 3101 /* SPT and KBL errata workarounds */ 3102 if (hw->mac.type == e1000_pch_spt) { 3103 u32 reg; 3104 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3105 reg |= E1000_RCTL_RDMTS_HEX; 3106 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3107 /* i218-i219 Specification Update 1.5.4.5 */ 3108 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3109 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3110 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3111 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3112 } 3113 } 3114 3115 /********************************************************************* 3116 * 3117 * Enable receive unit. 3118 * 3119 **********************************************************************/ 3120 3121 static void 3122 em_initialize_receive_unit(if_ctx_t ctx) 3123 { 3124 struct adapter *adapter = iflib_get_softc(ctx); 3125 if_softc_ctx_t scctx = adapter->shared; 3126 struct ifnet *ifp = iflib_get_ifp(ctx); 3127 struct e1000_hw *hw = &adapter->hw; 3128 struct em_rx_queue *que; 3129 int i; 3130 u32 rctl, rxcsum, rfctl; 3131 3132 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3133 3134 /* 3135 * Make sure receives are disabled while setting 3136 * up the descriptor ring 3137 */ 3138 rctl = E1000_READ_REG(hw, E1000_RCTL); 3139 /* Do not disable if ever enabled on this hardware */ 3140 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3141 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3142 3143 /* Setup the Receive Control Register */ 3144 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3145 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3146 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3147 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3148 3149 /* Do not store bad packets */ 3150 rctl &= ~E1000_RCTL_SBP; 3151 3152 /* Enable Long Packet receive */ 3153 if (if_getmtu(ifp) > ETHERMTU) 3154 rctl |= E1000_RCTL_LPE; 3155 else 3156 rctl &= ~E1000_RCTL_LPE; 3157 3158 /* Strip the CRC */ 3159 if (!em_disable_crc_stripping) 3160 rctl |= E1000_RCTL_SECRC; 3161 3162 if (adapter->hw.mac.type >= e1000_82540) { 3163 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3164 adapter->rx_abs_int_delay.value); 3165 3166 /* 3167 * Set the interrupt throttling rate. Value is calculated 3168 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3169 */ 3170 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3171 } 3172 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3173 adapter->rx_int_delay.value); 3174 3175 /* Use extended rx descriptor formats */ 3176 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3177 rfctl |= E1000_RFCTL_EXTEN; 3178 /* 3179 * When using MSI-X interrupts we need to throttle 3180 * using the EITR register (82574 only) 3181 */ 3182 if (hw->mac.type == e1000_82574) { 3183 for (int i = 0; i < 4; i++) 3184 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3185 DEFAULT_ITR); 3186 /* Disable accelerated acknowledge */ 3187 rfctl |= E1000_RFCTL_ACK_DIS; 3188 } 3189 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3190 3191 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3192 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3193 adapter->hw.mac.type >= e1000_82543) { 3194 if (adapter->tx_num_queues > 1) { 3195 if (adapter->hw.mac.type >= igb_mac_min) { 3196 rxcsum |= E1000_RXCSUM_PCSD; 3197 if (hw->mac.type != e1000_82575) 3198 rxcsum |= E1000_RXCSUM_CRCOFL; 3199 } else 3200 rxcsum |= E1000_RXCSUM_TUOFL | 3201 E1000_RXCSUM_IPOFL | 3202 E1000_RXCSUM_PCSD; 3203 } else { 3204 if (adapter->hw.mac.type >= igb_mac_min) 3205 rxcsum |= E1000_RXCSUM_IPPCSE; 3206 else 3207 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3208 if (adapter->hw.mac.type > e1000_82575) 3209 rxcsum |= E1000_RXCSUM_CRCOFL; 3210 } 3211 } else 3212 rxcsum &= ~E1000_RXCSUM_TUOFL; 3213 3214 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3215 3216 if (adapter->rx_num_queues > 1) { 3217 if (adapter->hw.mac.type >= igb_mac_min) 3218 igb_initialize_rss_mapping(adapter); 3219 else 3220 em_initialize_rss_mapping(adapter); 3221 } 3222 3223 /* 3224 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3225 * long latencies are observed, like Lenovo X60. This 3226 * change eliminates the problem, but since having positive 3227 * values in RDTR is a known source of problems on other 3228 * platforms another solution is being sought. 3229 */ 3230 if (hw->mac.type == e1000_82573) 3231 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3232 3233 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3234 struct rx_ring *rxr = &que->rxr; 3235 /* Setup the Base and Length of the Rx Descriptor Ring */ 3236 u64 bus_addr = rxr->rx_paddr; 3237 #if 0 3238 u32 rdt = adapter->rx_num_queues -1; /* default */ 3239 #endif 3240 3241 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3242 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3243 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3244 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3245 /* Setup the Head and Tail Descriptor Pointers */ 3246 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3247 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3248 } 3249 3250 /* 3251 * Set PTHRESH for improved jumbo performance 3252 * According to 10.2.5.11 of Intel 82574 Datasheet, 3253 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3254 * Only write to RXDCTL(1) if there is a need for different 3255 * settings. 3256 */ 3257 3258 if (((adapter->hw.mac.type == e1000_ich9lan) || 3259 (adapter->hw.mac.type == e1000_pch2lan) || 3260 (adapter->hw.mac.type == e1000_ich10lan)) && 3261 (if_getmtu(ifp) > ETHERMTU)) { 3262 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3263 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3264 } else if (adapter->hw.mac.type == e1000_82574) { 3265 for (int i = 0; i < adapter->rx_num_queues; i++) { 3266 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3267 rxdctl |= 0x20; /* PTHRESH */ 3268 rxdctl |= 4 << 8; /* HTHRESH */ 3269 rxdctl |= 4 << 16;/* WTHRESH */ 3270 rxdctl |= 1 << 24; /* Switch to granularity */ 3271 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3272 } 3273 } else if (adapter->hw.mac.type >= igb_mac_min) { 3274 u32 psize, srrctl = 0; 3275 3276 if (if_getmtu(ifp) > ETHERMTU) { 3277 /* Set maximum packet len */ 3278 if (adapter->rx_mbuf_sz <= 4096) { 3279 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3280 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3281 } else if (adapter->rx_mbuf_sz > 4096) { 3282 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3283 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3284 } 3285 psize = scctx->isc_max_frame_size; 3286 /* are we on a vlan? */ 3287 if (ifp->if_vlantrunk != NULL) 3288 psize += VLAN_TAG_SIZE; 3289 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3290 } else { 3291 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3292 rctl |= E1000_RCTL_SZ_2048; 3293 } 3294 3295 /* 3296 * If TX flow control is disabled and there's >1 queue defined, 3297 * enable DROP. 3298 * 3299 * This drops frames rather than hanging the RX MAC for all queues. 3300 */ 3301 if ((adapter->rx_num_queues > 1) && 3302 (adapter->fc == e1000_fc_none || 3303 adapter->fc == e1000_fc_rx_pause)) { 3304 srrctl |= E1000_SRRCTL_DROP_EN; 3305 } 3306 /* Setup the Base and Length of the Rx Descriptor Rings */ 3307 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3308 struct rx_ring *rxr = &que->rxr; 3309 u64 bus_addr = rxr->rx_paddr; 3310 u32 rxdctl; 3311 3312 #ifdef notyet 3313 /* Configure for header split? -- ignore for now */ 3314 rxr->hdr_split = igb_header_split; 3315 #else 3316 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3317 #endif 3318 3319 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3320 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3321 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3322 (uint32_t)(bus_addr >> 32)); 3323 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3324 (uint32_t)bus_addr); 3325 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3326 /* Enable this Queue */ 3327 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3328 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3329 rxdctl &= 0xFFF00000; 3330 rxdctl |= IGB_RX_PTHRESH; 3331 rxdctl |= IGB_RX_HTHRESH << 8; 3332 rxdctl |= IGB_RX_WTHRESH << 16; 3333 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3334 } 3335 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3336 if (if_getmtu(ifp) > ETHERMTU) 3337 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3338 else 3339 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3340 } 3341 3342 /* Make sure VLAN Filters are off */ 3343 rctl &= ~E1000_RCTL_VFE; 3344 3345 if (adapter->hw.mac.type < igb_mac_min) { 3346 if (adapter->rx_mbuf_sz == MCLBYTES) 3347 rctl |= E1000_RCTL_SZ_2048; 3348 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3349 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3350 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3351 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3352 3353 /* ensure we clear use DTYPE of 00 here */ 3354 rctl &= ~0x00000C00; 3355 } 3356 3357 /* Write out the settings */ 3358 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3359 3360 return; 3361 } 3362 3363 static void 3364 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3365 { 3366 struct adapter *adapter = iflib_get_softc(ctx); 3367 u32 index, bit; 3368 3369 index = (vtag >> 5) & 0x7F; 3370 bit = vtag & 0x1F; 3371 adapter->shadow_vfta[index] |= (1 << bit); 3372 ++adapter->num_vlans; 3373 } 3374 3375 static void 3376 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3377 { 3378 struct adapter *adapter = iflib_get_softc(ctx); 3379 u32 index, bit; 3380 3381 index = (vtag >> 5) & 0x7F; 3382 bit = vtag & 0x1F; 3383 adapter->shadow_vfta[index] &= ~(1 << bit); 3384 --adapter->num_vlans; 3385 } 3386 3387 static void 3388 em_setup_vlan_hw_support(struct adapter *adapter) 3389 { 3390 struct e1000_hw *hw = &adapter->hw; 3391 u32 reg; 3392 3393 /* 3394 * We get here thru init_locked, meaning 3395 * a soft reset, this has already cleared 3396 * the VFTA and other state, so if there 3397 * have been no vlan's registered do nothing. 3398 */ 3399 if (adapter->num_vlans == 0) 3400 return; 3401 3402 /* 3403 * A soft reset zero's out the VFTA, so 3404 * we need to repopulate it now. 3405 */ 3406 for (int i = 0; i < EM_VFTA_SIZE; i++) 3407 if (adapter->shadow_vfta[i] != 0) 3408 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3409 i, adapter->shadow_vfta[i]); 3410 3411 reg = E1000_READ_REG(hw, E1000_CTRL); 3412 reg |= E1000_CTRL_VME; 3413 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3414 3415 /* Enable the Filter Table */ 3416 reg = E1000_READ_REG(hw, E1000_RCTL); 3417 reg &= ~E1000_RCTL_CFIEN; 3418 reg |= E1000_RCTL_VFE; 3419 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3420 } 3421 3422 static void 3423 em_if_intr_enable(if_ctx_t ctx) 3424 { 3425 struct adapter *adapter = iflib_get_softc(ctx); 3426 struct e1000_hw *hw = &adapter->hw; 3427 u32 ims_mask = IMS_ENABLE_MASK; 3428 3429 if (hw->mac.type == e1000_82574) { 3430 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3431 ims_mask |= adapter->ims; 3432 } 3433 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3434 } 3435 3436 static void 3437 em_if_intr_disable(if_ctx_t ctx) 3438 { 3439 struct adapter *adapter = iflib_get_softc(ctx); 3440 struct e1000_hw *hw = &adapter->hw; 3441 3442 if (hw->mac.type == e1000_82574) 3443 E1000_WRITE_REG(hw, EM_EIAC, 0); 3444 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3445 } 3446 3447 static void 3448 igb_if_intr_enable(if_ctx_t ctx) 3449 { 3450 struct adapter *adapter = iflib_get_softc(ctx); 3451 struct e1000_hw *hw = &adapter->hw; 3452 u32 mask; 3453 3454 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3455 mask = (adapter->que_mask | adapter->link_mask); 3456 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3457 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3458 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3459 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3460 } else 3461 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3462 E1000_WRITE_FLUSH(hw); 3463 } 3464 3465 static void 3466 igb_if_intr_disable(if_ctx_t ctx) 3467 { 3468 struct adapter *adapter = iflib_get_softc(ctx); 3469 struct e1000_hw *hw = &adapter->hw; 3470 3471 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3472 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3473 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3474 } 3475 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3476 E1000_WRITE_FLUSH(hw); 3477 } 3478 3479 /* 3480 * Bit of a misnomer, what this really means is 3481 * to enable OS management of the system... aka 3482 * to disable special hardware management features 3483 */ 3484 static void 3485 em_init_manageability(struct adapter *adapter) 3486 { 3487 /* A shared code workaround */ 3488 #define E1000_82542_MANC2H E1000_MANC2H 3489 if (adapter->has_manage) { 3490 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3491 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3492 3493 /* disable hardware interception of ARP */ 3494 manc &= ~(E1000_MANC_ARP_EN); 3495 3496 /* enable receiving management packets to the host */ 3497 manc |= E1000_MANC_EN_MNG2HOST; 3498 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3499 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3500 manc2h |= E1000_MNG2HOST_PORT_623; 3501 manc2h |= E1000_MNG2HOST_PORT_664; 3502 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3503 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3504 } 3505 } 3506 3507 /* 3508 * Give control back to hardware management 3509 * controller if there is one. 3510 */ 3511 static void 3512 em_release_manageability(struct adapter *adapter) 3513 { 3514 if (adapter->has_manage) { 3515 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3516 3517 /* re-enable hardware interception of ARP */ 3518 manc |= E1000_MANC_ARP_EN; 3519 manc &= ~E1000_MANC_EN_MNG2HOST; 3520 3521 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3522 } 3523 } 3524 3525 /* 3526 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3527 * For ASF and Pass Through versions of f/w this means 3528 * that the driver is loaded. For AMT version type f/w 3529 * this means that the network i/f is open. 3530 */ 3531 static void 3532 em_get_hw_control(struct adapter *adapter) 3533 { 3534 u32 ctrl_ext, swsm; 3535 3536 if (adapter->vf_ifp) 3537 return; 3538 3539 if (adapter->hw.mac.type == e1000_82573) { 3540 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3541 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3542 swsm | E1000_SWSM_DRV_LOAD); 3543 return; 3544 } 3545 /* else */ 3546 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3547 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3548 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3549 } 3550 3551 /* 3552 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3553 * For ASF and Pass Through versions of f/w this means that 3554 * the driver is no longer loaded. For AMT versions of the 3555 * f/w this means that the network i/f is closed. 3556 */ 3557 static void 3558 em_release_hw_control(struct adapter *adapter) 3559 { 3560 u32 ctrl_ext, swsm; 3561 3562 if (!adapter->has_manage) 3563 return; 3564 3565 if (adapter->hw.mac.type == e1000_82573) { 3566 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3567 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3568 swsm & ~E1000_SWSM_DRV_LOAD); 3569 return; 3570 } 3571 /* else */ 3572 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3573 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3575 return; 3576 } 3577 3578 static int 3579 em_is_valid_ether_addr(u8 *addr) 3580 { 3581 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3582 3583 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3584 return (FALSE); 3585 } 3586 3587 return (TRUE); 3588 } 3589 3590 /* 3591 ** Parse the interface capabilities with regard 3592 ** to both system management and wake-on-lan for 3593 ** later use. 3594 */ 3595 static void 3596 em_get_wakeup(if_ctx_t ctx) 3597 { 3598 struct adapter *adapter = iflib_get_softc(ctx); 3599 device_t dev = iflib_get_dev(ctx); 3600 u16 eeprom_data = 0, device_id, apme_mask; 3601 3602 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3603 apme_mask = EM_EEPROM_APME; 3604 3605 switch (adapter->hw.mac.type) { 3606 case e1000_82542: 3607 case e1000_82543: 3608 break; 3609 case e1000_82544: 3610 e1000_read_nvm(&adapter->hw, 3611 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3612 apme_mask = EM_82544_APME; 3613 break; 3614 case e1000_82546: 3615 case e1000_82546_rev_3: 3616 if (adapter->hw.bus.func == 1) { 3617 e1000_read_nvm(&adapter->hw, 3618 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3619 break; 3620 } else 3621 e1000_read_nvm(&adapter->hw, 3622 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3623 break; 3624 case e1000_82573: 3625 case e1000_82583: 3626 adapter->has_amt = TRUE; 3627 /* FALLTHROUGH */ 3628 case e1000_82571: 3629 case e1000_82572: 3630 case e1000_80003es2lan: 3631 if (adapter->hw.bus.func == 1) { 3632 e1000_read_nvm(&adapter->hw, 3633 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3634 break; 3635 } else 3636 e1000_read_nvm(&adapter->hw, 3637 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3638 break; 3639 case e1000_ich8lan: 3640 case e1000_ich9lan: 3641 case e1000_ich10lan: 3642 case e1000_pchlan: 3643 case e1000_pch2lan: 3644 case e1000_pch_lpt: 3645 case e1000_pch_spt: 3646 case e1000_82575: /* listing all igb devices */ 3647 case e1000_82576: 3648 case e1000_82580: 3649 case e1000_i350: 3650 case e1000_i354: 3651 case e1000_i210: 3652 case e1000_i211: 3653 case e1000_vfadapt: 3654 case e1000_vfadapt_i350: 3655 apme_mask = E1000_WUC_APME; 3656 adapter->has_amt = TRUE; 3657 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3658 break; 3659 default: 3660 e1000_read_nvm(&adapter->hw, 3661 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3662 break; 3663 } 3664 if (eeprom_data & apme_mask) 3665 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3666 /* 3667 * We have the eeprom settings, now apply the special cases 3668 * where the eeprom may be wrong or the board won't support 3669 * wake on lan on a particular port 3670 */ 3671 device_id = pci_get_device(dev); 3672 switch (device_id) { 3673 case E1000_DEV_ID_82546GB_PCIE: 3674 adapter->wol = 0; 3675 break; 3676 case E1000_DEV_ID_82546EB_FIBER: 3677 case E1000_DEV_ID_82546GB_FIBER: 3678 /* Wake events only supported on port A for dual fiber 3679 * regardless of eeprom setting */ 3680 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3681 E1000_STATUS_FUNC_1) 3682 adapter->wol = 0; 3683 break; 3684 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3685 /* if quad port adapter, disable WoL on all but port A */ 3686 if (global_quad_port_a != 0) 3687 adapter->wol = 0; 3688 /* Reset for multiple quad port adapters */ 3689 if (++global_quad_port_a == 4) 3690 global_quad_port_a = 0; 3691 break; 3692 case E1000_DEV_ID_82571EB_FIBER: 3693 /* Wake events only supported on port A for dual fiber 3694 * regardless of eeprom setting */ 3695 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3696 E1000_STATUS_FUNC_1) 3697 adapter->wol = 0; 3698 break; 3699 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3700 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3701 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3702 /* if quad port adapter, disable WoL on all but port A */ 3703 if (global_quad_port_a != 0) 3704 adapter->wol = 0; 3705 /* Reset for multiple quad port adapters */ 3706 if (++global_quad_port_a == 4) 3707 global_quad_port_a = 0; 3708 break; 3709 } 3710 return; 3711 } 3712 3713 3714 /* 3715 * Enable PCI Wake On Lan capability 3716 */ 3717 static void 3718 em_enable_wakeup(if_ctx_t ctx) 3719 { 3720 struct adapter *adapter = iflib_get_softc(ctx); 3721 device_t dev = iflib_get_dev(ctx); 3722 if_t ifp = iflib_get_ifp(ctx); 3723 int error = 0; 3724 u32 pmc, ctrl, ctrl_ext, rctl; 3725 u16 status; 3726 3727 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3728 return; 3729 3730 /* 3731 * Determine type of Wakeup: note that wol 3732 * is set with all bits on by default. 3733 */ 3734 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3735 adapter->wol &= ~E1000_WUFC_MAG; 3736 3737 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3738 adapter->wol &= ~E1000_WUFC_EX; 3739 3740 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3741 adapter->wol &= ~E1000_WUFC_MC; 3742 else { 3743 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3744 rctl |= E1000_RCTL_MPE; 3745 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3746 } 3747 3748 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3749 goto pme; 3750 3751 /* Advertise the wakeup capability */ 3752 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3753 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3754 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3755 3756 /* Keep the laser running on Fiber adapters */ 3757 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3758 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3759 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3760 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3761 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3762 } 3763 3764 if ((adapter->hw.mac.type == e1000_ich8lan) || 3765 (adapter->hw.mac.type == e1000_pchlan) || 3766 (adapter->hw.mac.type == e1000_ich9lan) || 3767 (adapter->hw.mac.type == e1000_ich10lan)) 3768 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3769 3770 if ( adapter->hw.mac.type >= e1000_pchlan) { 3771 error = em_enable_phy_wakeup(adapter); 3772 if (error) 3773 goto pme; 3774 } else { 3775 /* Enable wakeup by the MAC */ 3776 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3777 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3778 } 3779 3780 if (adapter->hw.phy.type == e1000_phy_igp_3) 3781 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3782 3783 pme: 3784 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3785 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3786 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3787 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3788 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3789 3790 return; 3791 } 3792 3793 /* 3794 * WOL in the newer chipset interfaces (pchlan) 3795 * require thing to be copied into the phy 3796 */ 3797 static int 3798 em_enable_phy_wakeup(struct adapter *adapter) 3799 { 3800 struct e1000_hw *hw = &adapter->hw; 3801 u32 mreg, ret = 0; 3802 u16 preg; 3803 3804 /* copy MAC RARs to PHY RARs */ 3805 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3806 3807 /* copy MAC MTA to PHY MTA */ 3808 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3809 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3810 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3811 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3812 (u16)((mreg >> 16) & 0xFFFF)); 3813 } 3814 3815 /* configure PHY Rx Control register */ 3816 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3817 mreg = E1000_READ_REG(hw, E1000_RCTL); 3818 if (mreg & E1000_RCTL_UPE) 3819 preg |= BM_RCTL_UPE; 3820 if (mreg & E1000_RCTL_MPE) 3821 preg |= BM_RCTL_MPE; 3822 preg &= ~(BM_RCTL_MO_MASK); 3823 if (mreg & E1000_RCTL_MO_3) 3824 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3825 << BM_RCTL_MO_SHIFT); 3826 if (mreg & E1000_RCTL_BAM) 3827 preg |= BM_RCTL_BAM; 3828 if (mreg & E1000_RCTL_PMCF) 3829 preg |= BM_RCTL_PMCF; 3830 mreg = E1000_READ_REG(hw, E1000_CTRL); 3831 if (mreg & E1000_CTRL_RFCE) 3832 preg |= BM_RCTL_RFCE; 3833 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3834 3835 /* enable PHY wakeup in MAC register */ 3836 E1000_WRITE_REG(hw, E1000_WUC, 3837 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3838 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3839 3840 /* configure and enable PHY wakeup in PHY registers */ 3841 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3842 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3843 3844 /* activate PHY wakeup */ 3845 ret = hw->phy.ops.acquire(hw); 3846 if (ret) { 3847 printf("Could not acquire PHY\n"); 3848 return ret; 3849 } 3850 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3851 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3852 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3853 if (ret) { 3854 printf("Could not read PHY page 769\n"); 3855 goto out; 3856 } 3857 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3858 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3859 if (ret) 3860 printf("Could not set PHY Host Wakeup bit\n"); 3861 out: 3862 hw->phy.ops.release(hw); 3863 3864 return ret; 3865 } 3866 3867 static void 3868 em_if_led_func(if_ctx_t ctx, int onoff) 3869 { 3870 struct adapter *adapter = iflib_get_softc(ctx); 3871 3872 if (onoff) { 3873 e1000_setup_led(&adapter->hw); 3874 e1000_led_on(&adapter->hw); 3875 } else { 3876 e1000_led_off(&adapter->hw); 3877 e1000_cleanup_led(&adapter->hw); 3878 } 3879 } 3880 3881 /* 3882 * Disable the L0S and L1 LINK states 3883 */ 3884 static void 3885 em_disable_aspm(struct adapter *adapter) 3886 { 3887 int base, reg; 3888 u16 link_cap,link_ctrl; 3889 device_t dev = adapter->dev; 3890 3891 switch (adapter->hw.mac.type) { 3892 case e1000_82573: 3893 case e1000_82574: 3894 case e1000_82583: 3895 break; 3896 default: 3897 return; 3898 } 3899 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3900 return; 3901 reg = base + PCIER_LINK_CAP; 3902 link_cap = pci_read_config(dev, reg, 2); 3903 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3904 return; 3905 reg = base + PCIER_LINK_CTL; 3906 link_ctrl = pci_read_config(dev, reg, 2); 3907 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3908 pci_write_config(dev, reg, link_ctrl, 2); 3909 return; 3910 } 3911 3912 /********************************************************************** 3913 * 3914 * Update the board statistics counters. 3915 * 3916 **********************************************************************/ 3917 static void 3918 em_update_stats_counters(struct adapter *adapter) 3919 { 3920 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3921 3922 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3923 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3924 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3925 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3926 } 3927 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3928 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3929 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3930 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3931 3932 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3933 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3934 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3935 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3936 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3937 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3938 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3939 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3940 /* 3941 ** For watchdog management we need to know if we have been 3942 ** paused during the last interval, so capture that here. 3943 */ 3944 if (adapter->stats.xoffrxc != prev_xoffrxc) 3945 adapter->shared->isc_pause_frames = 1; 3946 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3947 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3948 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3949 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3950 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3951 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3952 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3953 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3954 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3955 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3956 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3957 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3958 3959 /* For the 64-bit byte counters the low dword must be read first. */ 3960 /* Both registers clear on the read of the high dword */ 3961 3962 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3963 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3964 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3965 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3966 3967 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3968 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3969 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3970 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3971 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3972 3973 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3974 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3975 3976 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3977 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3978 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3979 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3980 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3981 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3982 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3983 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3984 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3985 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3986 3987 /* Interrupt Counts */ 3988 3989 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3990 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3991 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3992 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3993 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3994 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3995 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3996 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3997 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3998 3999 if (adapter->hw.mac.type >= e1000_82543) { 4000 adapter->stats.algnerrc += 4001 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4002 adapter->stats.rxerrc += 4003 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4004 adapter->stats.tncrs += 4005 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4006 adapter->stats.cexterr += 4007 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4008 adapter->stats.tsctc += 4009 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4010 adapter->stats.tsctfc += 4011 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4012 } 4013 } 4014 4015 static uint64_t 4016 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4017 { 4018 struct adapter *adapter = iflib_get_softc(ctx); 4019 struct ifnet *ifp = iflib_get_ifp(ctx); 4020 4021 switch (cnt) { 4022 case IFCOUNTER_COLLISIONS: 4023 return (adapter->stats.colc); 4024 case IFCOUNTER_IERRORS: 4025 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4026 adapter->stats.crcerrs + adapter->stats.algnerrc + 4027 adapter->stats.ruc + adapter->stats.roc + 4028 adapter->stats.mpc + adapter->stats.cexterr); 4029 case IFCOUNTER_OERRORS: 4030 return (adapter->stats.ecol + adapter->stats.latecol + 4031 adapter->watchdog_events); 4032 default: 4033 return (if_get_counter_default(ifp, cnt)); 4034 } 4035 } 4036 4037 /* Export a single 32-bit register via a read-only sysctl. */ 4038 static int 4039 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4040 { 4041 struct adapter *adapter; 4042 u_int val; 4043 4044 adapter = oidp->oid_arg1; 4045 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4046 return (sysctl_handle_int(oidp, &val, 0, req)); 4047 } 4048 4049 /* 4050 * Add sysctl variables, one per statistic, to the system. 4051 */ 4052 static void 4053 em_add_hw_stats(struct adapter *adapter) 4054 { 4055 device_t dev = iflib_get_dev(adapter->ctx); 4056 struct em_tx_queue *tx_que = adapter->tx_queues; 4057 struct em_rx_queue *rx_que = adapter->rx_queues; 4058 4059 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4060 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4061 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4062 struct e1000_hw_stats *stats = &adapter->stats; 4063 4064 struct sysctl_oid *stat_node, *queue_node, *int_node; 4065 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4066 4067 #define QUEUE_NAME_LEN 32 4068 char namebuf[QUEUE_NAME_LEN]; 4069 4070 /* Driver Statistics */ 4071 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4072 CTLFLAG_RD, &adapter->dropped_pkts, 4073 "Driver dropped packets"); 4074 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4075 CTLFLAG_RD, &adapter->link_irq, 4076 "Link MSI-X IRQ Handled"); 4077 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4078 CTLFLAG_RD, &adapter->rx_overruns, 4079 "RX overruns"); 4080 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4081 CTLFLAG_RD, &adapter->watchdog_events, 4082 "Watchdog timeouts"); 4083 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4084 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4085 em_sysctl_reg_handler, "IU", 4086 "Device Control Register"); 4087 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4088 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4089 em_sysctl_reg_handler, "IU", 4090 "Receiver Control Register"); 4091 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4092 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4093 "Flow Control High Watermark"); 4094 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4095 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4096 "Flow Control Low Watermark"); 4097 4098 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4099 struct tx_ring *txr = &tx_que->txr; 4100 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4101 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4102 CTLFLAG_RD, NULL, "TX Queue Name"); 4103 queue_list = SYSCTL_CHILDREN(queue_node); 4104 4105 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4106 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4107 E1000_TDH(txr->me), 4108 em_sysctl_reg_handler, "IU", 4109 "Transmit Descriptor Head"); 4110 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4111 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4112 E1000_TDT(txr->me), 4113 em_sysctl_reg_handler, "IU", 4114 "Transmit Descriptor Tail"); 4115 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4116 CTLFLAG_RD, &txr->tx_irq, 4117 "Queue MSI-X Transmit Interrupts"); 4118 } 4119 4120 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4121 struct rx_ring *rxr = &rx_que->rxr; 4122 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4123 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4124 CTLFLAG_RD, NULL, "RX Queue Name"); 4125 queue_list = SYSCTL_CHILDREN(queue_node); 4126 4127 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4128 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4129 E1000_RDH(rxr->me), 4130 em_sysctl_reg_handler, "IU", 4131 "Receive Descriptor Head"); 4132 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4133 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4134 E1000_RDT(rxr->me), 4135 em_sysctl_reg_handler, "IU", 4136 "Receive Descriptor Tail"); 4137 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4138 CTLFLAG_RD, &rxr->rx_irq, 4139 "Queue MSI-X Receive Interrupts"); 4140 } 4141 4142 /* MAC stats get their own sub node */ 4143 4144 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4145 CTLFLAG_RD, NULL, "Statistics"); 4146 stat_list = SYSCTL_CHILDREN(stat_node); 4147 4148 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4149 CTLFLAG_RD, &stats->ecol, 4150 "Excessive collisions"); 4151 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4152 CTLFLAG_RD, &stats->scc, 4153 "Single collisions"); 4154 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4155 CTLFLAG_RD, &stats->mcc, 4156 "Multiple collisions"); 4157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4158 CTLFLAG_RD, &stats->latecol, 4159 "Late collisions"); 4160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4161 CTLFLAG_RD, &stats->colc, 4162 "Collision Count"); 4163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4164 CTLFLAG_RD, &adapter->stats.symerrs, 4165 "Symbol Errors"); 4166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4167 CTLFLAG_RD, &adapter->stats.sec, 4168 "Sequence Errors"); 4169 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4170 CTLFLAG_RD, &adapter->stats.dc, 4171 "Defer Count"); 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4173 CTLFLAG_RD, &adapter->stats.mpc, 4174 "Missed Packets"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4176 CTLFLAG_RD, &adapter->stats.rnbc, 4177 "Receive No Buffers"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4179 CTLFLAG_RD, &adapter->stats.ruc, 4180 "Receive Undersize"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4182 CTLFLAG_RD, &adapter->stats.rfc, 4183 "Fragmented Packets Received "); 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4185 CTLFLAG_RD, &adapter->stats.roc, 4186 "Oversized Packets Received"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4188 CTLFLAG_RD, &adapter->stats.rjc, 4189 "Recevied Jabber"); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4191 CTLFLAG_RD, &adapter->stats.rxerrc, 4192 "Receive Errors"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4194 CTLFLAG_RD, &adapter->stats.crcerrs, 4195 "CRC errors"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4197 CTLFLAG_RD, &adapter->stats.algnerrc, 4198 "Alignment Errors"); 4199 /* On 82575 these are collision counts */ 4200 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4201 CTLFLAG_RD, &adapter->stats.cexterr, 4202 "Collision/Carrier extension errors"); 4203 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4204 CTLFLAG_RD, &adapter->stats.xonrxc, 4205 "XON Received"); 4206 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4207 CTLFLAG_RD, &adapter->stats.xontxc, 4208 "XON Transmitted"); 4209 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4210 CTLFLAG_RD, &adapter->stats.xoffrxc, 4211 "XOFF Received"); 4212 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4213 CTLFLAG_RD, &adapter->stats.xofftxc, 4214 "XOFF Transmitted"); 4215 4216 /* Packet Reception Stats */ 4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4218 CTLFLAG_RD, &adapter->stats.tpr, 4219 "Total Packets Received "); 4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4221 CTLFLAG_RD, &adapter->stats.gprc, 4222 "Good Packets Received"); 4223 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4224 CTLFLAG_RD, &adapter->stats.bprc, 4225 "Broadcast Packets Received"); 4226 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4227 CTLFLAG_RD, &adapter->stats.mprc, 4228 "Multicast Packets Received"); 4229 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4230 CTLFLAG_RD, &adapter->stats.prc64, 4231 "64 byte frames received "); 4232 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4233 CTLFLAG_RD, &adapter->stats.prc127, 4234 "65-127 byte frames received"); 4235 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4236 CTLFLAG_RD, &adapter->stats.prc255, 4237 "128-255 byte frames received"); 4238 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4239 CTLFLAG_RD, &adapter->stats.prc511, 4240 "256-511 byte frames received"); 4241 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4242 CTLFLAG_RD, &adapter->stats.prc1023, 4243 "512-1023 byte frames received"); 4244 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4245 CTLFLAG_RD, &adapter->stats.prc1522, 4246 "1023-1522 byte frames received"); 4247 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4248 CTLFLAG_RD, &adapter->stats.gorc, 4249 "Good Octets Received"); 4250 4251 /* Packet Transmission Stats */ 4252 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4253 CTLFLAG_RD, &adapter->stats.gotc, 4254 "Good Octets Transmitted"); 4255 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4256 CTLFLAG_RD, &adapter->stats.tpt, 4257 "Total Packets Transmitted"); 4258 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4259 CTLFLAG_RD, &adapter->stats.gptc, 4260 "Good Packets Transmitted"); 4261 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4262 CTLFLAG_RD, &adapter->stats.bptc, 4263 "Broadcast Packets Transmitted"); 4264 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4265 CTLFLAG_RD, &adapter->stats.mptc, 4266 "Multicast Packets Transmitted"); 4267 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4268 CTLFLAG_RD, &adapter->stats.ptc64, 4269 "64 byte frames transmitted "); 4270 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4271 CTLFLAG_RD, &adapter->stats.ptc127, 4272 "65-127 byte frames transmitted"); 4273 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4274 CTLFLAG_RD, &adapter->stats.ptc255, 4275 "128-255 byte frames transmitted"); 4276 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4277 CTLFLAG_RD, &adapter->stats.ptc511, 4278 "256-511 byte frames transmitted"); 4279 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4280 CTLFLAG_RD, &adapter->stats.ptc1023, 4281 "512-1023 byte frames transmitted"); 4282 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4283 CTLFLAG_RD, &adapter->stats.ptc1522, 4284 "1024-1522 byte frames transmitted"); 4285 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4286 CTLFLAG_RD, &adapter->stats.tsctc, 4287 "TSO Contexts Transmitted"); 4288 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4289 CTLFLAG_RD, &adapter->stats.tsctfc, 4290 "TSO Contexts Failed"); 4291 4292 4293 /* Interrupt Stats */ 4294 4295 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4296 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4297 int_list = SYSCTL_CHILDREN(int_node); 4298 4299 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4300 CTLFLAG_RD, &adapter->stats.iac, 4301 "Interrupt Assertion Count"); 4302 4303 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4304 CTLFLAG_RD, &adapter->stats.icrxptc, 4305 "Interrupt Cause Rx Pkt Timer Expire Count"); 4306 4307 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4308 CTLFLAG_RD, &adapter->stats.icrxatc, 4309 "Interrupt Cause Rx Abs Timer Expire Count"); 4310 4311 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4312 CTLFLAG_RD, &adapter->stats.ictxptc, 4313 "Interrupt Cause Tx Pkt Timer Expire Count"); 4314 4315 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4316 CTLFLAG_RD, &adapter->stats.ictxatc, 4317 "Interrupt Cause Tx Abs Timer Expire Count"); 4318 4319 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4320 CTLFLAG_RD, &adapter->stats.ictxqec, 4321 "Interrupt Cause Tx Queue Empty Count"); 4322 4323 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4324 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4325 "Interrupt Cause Tx Queue Min Thresh Count"); 4326 4327 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4328 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4329 "Interrupt Cause Rx Desc Min Thresh Count"); 4330 4331 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4332 CTLFLAG_RD, &adapter->stats.icrxoc, 4333 "Interrupt Cause Receiver Overrun Count"); 4334 } 4335 4336 /********************************************************************** 4337 * 4338 * This routine provides a way to dump out the adapter eeprom, 4339 * often a useful debug/service tool. This only dumps the first 4340 * 32 words, stuff that matters is in that extent. 4341 * 4342 **********************************************************************/ 4343 static int 4344 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4345 { 4346 struct adapter *adapter = (struct adapter *)arg1; 4347 int error; 4348 int result; 4349 4350 result = -1; 4351 error = sysctl_handle_int(oidp, &result, 0, req); 4352 4353 if (error || !req->newptr) 4354 return (error); 4355 4356 /* 4357 * This value will cause a hex dump of the 4358 * first 32 16-bit words of the EEPROM to 4359 * the screen. 4360 */ 4361 if (result == 1) 4362 em_print_nvm_info(adapter); 4363 4364 return (error); 4365 } 4366 4367 static void 4368 em_print_nvm_info(struct adapter *adapter) 4369 { 4370 u16 eeprom_data; 4371 int i, j, row = 0; 4372 4373 /* Its a bit crude, but it gets the job done */ 4374 printf("\nInterface EEPROM Dump:\n"); 4375 printf("Offset\n0x0000 "); 4376 for (i = 0, j = 0; i < 32; i++, j++) { 4377 if (j == 8) { /* Make the offset block */ 4378 j = 0; ++row; 4379 printf("\n0x00%x0 ",row); 4380 } 4381 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4382 printf("%04x ", eeprom_data); 4383 } 4384 printf("\n"); 4385 } 4386 4387 static int 4388 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4389 { 4390 struct em_int_delay_info *info; 4391 struct adapter *adapter; 4392 u32 regval; 4393 int error, usecs, ticks; 4394 4395 info = (struct em_int_delay_info *) arg1; 4396 usecs = info->value; 4397 error = sysctl_handle_int(oidp, &usecs, 0, req); 4398 if (error != 0 || req->newptr == NULL) 4399 return (error); 4400 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4401 return (EINVAL); 4402 info->value = usecs; 4403 ticks = EM_USECS_TO_TICKS(usecs); 4404 if (info->offset == E1000_ITR) /* units are 256ns here */ 4405 ticks *= 4; 4406 4407 adapter = info->adapter; 4408 4409 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4410 regval = (regval & ~0xffff) | (ticks & 0xffff); 4411 /* Handle a few special cases. */ 4412 switch (info->offset) { 4413 case E1000_RDTR: 4414 break; 4415 case E1000_TIDV: 4416 if (ticks == 0) { 4417 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4418 /* Don't write 0 into the TIDV register. */ 4419 regval++; 4420 } else 4421 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4422 break; 4423 } 4424 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4425 return (0); 4426 } 4427 4428 static void 4429 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4430 const char *description, struct em_int_delay_info *info, 4431 int offset, int value) 4432 { 4433 info->adapter = adapter; 4434 info->offset = offset; 4435 info->value = value; 4436 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4437 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4438 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4439 info, 0, em_sysctl_int_delay, "I", description); 4440 } 4441 4442 /* 4443 * Set flow control using sysctl: 4444 * Flow control values: 4445 * 0 - off 4446 * 1 - rx pause 4447 * 2 - tx pause 4448 * 3 - full 4449 */ 4450 static int 4451 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4452 { 4453 int error; 4454 static int input = 3; /* default is full */ 4455 struct adapter *adapter = (struct adapter *) arg1; 4456 4457 error = sysctl_handle_int(oidp, &input, 0, req); 4458 4459 if ((error) || (req->newptr == NULL)) 4460 return (error); 4461 4462 if (input == adapter->fc) /* no change? */ 4463 return (error); 4464 4465 switch (input) { 4466 case e1000_fc_rx_pause: 4467 case e1000_fc_tx_pause: 4468 case e1000_fc_full: 4469 case e1000_fc_none: 4470 adapter->hw.fc.requested_mode = input; 4471 adapter->fc = input; 4472 break; 4473 default: 4474 /* Do nothing */ 4475 return (error); 4476 } 4477 4478 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4479 e1000_force_mac_fc(&adapter->hw); 4480 return (error); 4481 } 4482 4483 /* 4484 * Manage Energy Efficient Ethernet: 4485 * Control values: 4486 * 0/1 - enabled/disabled 4487 */ 4488 static int 4489 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4490 { 4491 struct adapter *adapter = (struct adapter *) arg1; 4492 int error, value; 4493 4494 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4495 error = sysctl_handle_int(oidp, &value, 0, req); 4496 if (error || req->newptr == NULL) 4497 return (error); 4498 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4499 em_if_init(adapter->ctx); 4500 4501 return (0); 4502 } 4503 4504 static int 4505 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4506 { 4507 struct adapter *adapter; 4508 int error; 4509 int result; 4510 4511 result = -1; 4512 error = sysctl_handle_int(oidp, &result, 0, req); 4513 4514 if (error || !req->newptr) 4515 return (error); 4516 4517 if (result == 1) { 4518 adapter = (struct adapter *) arg1; 4519 em_print_debug_info(adapter); 4520 } 4521 4522 return (error); 4523 } 4524 4525 static int 4526 em_get_rs(SYSCTL_HANDLER_ARGS) 4527 { 4528 struct adapter *adapter = (struct adapter *) arg1; 4529 int error; 4530 int result; 4531 4532 result = 0; 4533 error = sysctl_handle_int(oidp, &result, 0, req); 4534 4535 if (error || !req->newptr || result != 1) 4536 return (error); 4537 em_dump_rs(adapter); 4538 4539 return (error); 4540 } 4541 4542 static void 4543 em_if_debug(if_ctx_t ctx) 4544 { 4545 em_dump_rs(iflib_get_softc(ctx)); 4546 } 4547 4548 /* 4549 * This routine is meant to be fluid, add whatever is 4550 * needed for debugging a problem. -jfv 4551 */ 4552 static void 4553 em_print_debug_info(struct adapter *adapter) 4554 { 4555 device_t dev = iflib_get_dev(adapter->ctx); 4556 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4557 struct tx_ring *txr = &adapter->tx_queues->txr; 4558 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4559 4560 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4561 printf("Interface is RUNNING "); 4562 else 4563 printf("Interface is NOT RUNNING\n"); 4564 4565 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4566 printf("and INACTIVE\n"); 4567 else 4568 printf("and ACTIVE\n"); 4569 4570 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4571 device_printf(dev, "TX Queue %d ------\n", i); 4572 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4573 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4574 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4575 4576 } 4577 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4578 device_printf(dev, "RX Queue %d ------\n", j); 4579 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4580 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4581 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4582 } 4583 } 4584 4585 /* 4586 * 82574 only: 4587 * Write a new value to the EEPROM increasing the number of MSI-X 4588 * vectors from 3 to 5, for proper multiqueue support. 4589 */ 4590 static void 4591 em_enable_vectors_82574(if_ctx_t ctx) 4592 { 4593 struct adapter *adapter = iflib_get_softc(ctx); 4594 struct e1000_hw *hw = &adapter->hw; 4595 device_t dev = iflib_get_dev(ctx); 4596 u16 edata; 4597 4598 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4599 if (bootverbose) 4600 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4601 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4602 device_printf(dev, "Writing to eeprom: increasing " 4603 "reported MSI-X vectors from 3 to 5...\n"); 4604 edata &= ~(EM_NVM_MSIX_N_MASK); 4605 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4606 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4607 e1000_update_nvm_checksum(hw); 4608 device_printf(dev, "Writing to eeprom: done\n"); 4609 } 4610 } 4611