xref: /freebsd/sys/dev/e1000/if_em.c (revision 13da84237a37961938e9e237171ac111ddc1897c)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /* $FreeBSD$ */
30 #include "if_em.h"
31 #include <sys/sbuf.h>
32 #include <machine/_inttypes.h>
33 
34 #define em_mac_min e1000_82571
35 #define igb_mac_min e1000_82575
36 
37 /*********************************************************************
38  *  Driver version:
39  *********************************************************************/
40 char em_driver_version[] = "7.7.8-fbsd";
41 char igb_driver_version[] = "2.5.19-fbsd";
42 
43 /*********************************************************************
44  *  PCI Device ID Table
45  *
46  *  Used by probe to select devices to load on
47  *  Last field stores an index into e1000_strings
48  *  Last entry must be all 0s
49  *
50  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
51  *********************************************************************/
52 
53 static pci_vendor_info_t em_vendor_info_array[] =
54 {
55 	/* Intel(R) - lem-class legacy devices */
56 	PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
57 	PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
58 	PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
59 	PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
60 	PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
61 
62 	PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
63 	PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
64 	PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
65 	PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
66 	PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
67 	PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
68 	PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
69 
70 	PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
71 
72 	PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
73 	PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
74 
75 	PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
76 	PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
77 	PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
78 	PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
79 
80 	PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
81 	PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
82 	PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
83 	PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
84 	PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
85 
86 	PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
87 	PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
88 	PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
89 	PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
90 	PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
91 	PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
92 	PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
93 	PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
94 	PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
95 
96 	PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
97 	PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
98 	PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
99 
100 	/* Intel(R) - em-class devices */
101 	PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
102 	PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
103 	PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
104 	PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
105 	PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
106 	PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
107 	PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
108 	PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
109 	PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
110 	PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
111 	PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
112 	PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
113 	PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
114 	PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
115 	PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
116 	PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
117 	PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
118 	PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
119 	PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
120 	PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
121 	PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
122 	PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
123 	PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
124 	PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
125 	PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
126 	PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
127 	PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
128 	PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
129 	PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
130 	PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
131 	PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
132 	PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
133 	PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
134 	PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
135 	PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
136 	PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
137 	PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
138 	PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
139 	PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
140 	PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
141 	PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
142 	PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
143 	PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
144 	PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
145 	PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
146 	PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
147 	PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
148 	PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
149 	PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
150 	PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
151 	PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
152 	PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
153 	PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
154 	PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
155 	PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
156 	PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
157 	PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
158 	PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
159 	PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
160 	PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
161 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
162 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
163 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
164 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
165 	PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
166 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
167 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
168 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
169 	PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
170 	PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
171 	PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
172 	PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
173 	PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
174 	PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
175 	PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
176 	PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
177 	PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
178 	PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
179 	PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
180 	PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
181 	PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
182 	PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
183 	PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
184 	PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
185 	PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
186 	PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
187 	PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
188 	PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
189 	PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
190 	PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
191 	PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
192 	PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
193 	PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
194 	PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
195 	PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
196 	PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
197 	PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
198 	PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"),
199 	PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"),
200 	PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"),
201 	PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"),
202 	PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"),
203 	PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"),
204 	PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"),
205 	PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"),
206 	PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"),
207 	PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"),
208 	PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"),
209 	PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"),
210 	PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"),
211 	PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"),
212 	PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"),
213 	PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"),
214 	/* required last entry */
215 	PVID_END
216 };
217 
218 static pci_vendor_info_t igb_vendor_info_array[] =
219 {
220 	/* Intel(R) - igb-class devices */
221 	PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
222 	PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
223 	PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
224 	PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
225 	PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
226 	PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
227 	PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
228 	PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
229 	PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
230 	PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
231 	PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
232 	PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
233 	PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
234 	PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
235 	PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
236 	PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
237 	PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
238 	PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
239 	PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
240 	PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
241 	PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
242 	PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
243 	PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
244 	PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
245 	PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
246 	PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
247 	PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
248 	PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
249 	PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
250 	PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
251 	PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
252 	PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
253 	PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"),
254 	PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
255 	PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
256 	PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
257 	PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
258 	PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
259 	PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
260 	PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
261 	/* required last entry */
262 	PVID_END
263 };
264 
265 /*********************************************************************
266  *  Function prototypes
267  *********************************************************************/
268 static void	*em_register(device_t);
269 static void	*igb_register(device_t);
270 static int	em_if_attach_pre(if_ctx_t);
271 static int	em_if_attach_post(if_ctx_t);
272 static int	em_if_detach(if_ctx_t);
273 static int	em_if_shutdown(if_ctx_t);
274 static int	em_if_suspend(if_ctx_t);
275 static int	em_if_resume(if_ctx_t);
276 
277 static int	em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
278 static int	em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
279 static void	em_if_queues_free(if_ctx_t);
280 
281 static uint64_t	em_if_get_counter(if_ctx_t, ift_counter);
282 static void	em_if_init(if_ctx_t);
283 static void	em_if_stop(if_ctx_t);
284 static void	em_if_media_status(if_ctx_t, struct ifmediareq *);
285 static int	em_if_media_change(if_ctx_t);
286 static int	em_if_mtu_set(if_ctx_t, uint32_t);
287 static void	em_if_timer(if_ctx_t, uint16_t);
288 static void	em_if_vlan_register(if_ctx_t, u16);
289 static void	em_if_vlan_unregister(if_ctx_t, u16);
290 static void	em_if_watchdog_reset(if_ctx_t);
291 static bool	em_if_needs_restart(if_ctx_t, enum iflib_restart_event);
292 
293 static void	em_identify_hardware(if_ctx_t);
294 static int	em_allocate_pci_resources(if_ctx_t);
295 static void	em_free_pci_resources(if_ctx_t);
296 static void	em_reset(if_ctx_t);
297 static int	em_setup_interface(if_ctx_t);
298 static int	em_setup_msix(if_ctx_t);
299 
300 static void	em_initialize_transmit_unit(if_ctx_t);
301 static void	em_initialize_receive_unit(if_ctx_t);
302 
303 static void	em_if_intr_enable(if_ctx_t);
304 static void	em_if_intr_disable(if_ctx_t);
305 static void	igb_if_intr_enable(if_ctx_t);
306 static void	igb_if_intr_disable(if_ctx_t);
307 static int	em_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
308 static int	em_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
309 static int	igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
310 static int	igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
311 static void	em_if_multi_set(if_ctx_t);
312 static void	em_if_update_admin_status(if_ctx_t);
313 static void	em_if_debug(if_ctx_t);
314 static void	em_update_stats_counters(struct e1000_softc *);
315 static void	em_add_hw_stats(struct e1000_softc *);
316 static int	em_if_set_promisc(if_ctx_t, int);
317 static bool	em_if_vlan_filter_capable(if_ctx_t);
318 static bool	em_if_vlan_filter_used(if_ctx_t);
319 static void	em_if_vlan_filter_enable(struct e1000_softc *);
320 static void	em_if_vlan_filter_disable(struct e1000_softc *);
321 static void	em_if_vlan_filter_write(struct e1000_softc *);
322 static void	em_setup_vlan_hw_support(if_ctx_t ctx);
323 static int	em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
324 static void	em_print_nvm_info(struct e1000_softc *);
325 static void	em_fw_version_locked(if_ctx_t);
326 static void	em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *);
327 static void	em_print_fw_version(struct e1000_softc *);
328 static int	em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
329 static int	em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
330 static int	em_get_rs(SYSCTL_HANDLER_ARGS);
331 static void	em_print_debug_info(struct e1000_softc *);
332 static int 	em_is_valid_ether_addr(u8 *);
333 static bool	em_automask_tso(if_ctx_t);
334 static int	em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
335 static void	em_add_int_delay_sysctl(struct e1000_softc *, const char *,
336 		    const char *, struct em_int_delay_info *, int, int);
337 /* Management and WOL Support */
338 static void	em_init_manageability(struct e1000_softc *);
339 static void	em_release_manageability(struct e1000_softc *);
340 static void	em_get_hw_control(struct e1000_softc *);
341 static void	em_release_hw_control(struct e1000_softc *);
342 static void	em_get_wakeup(if_ctx_t);
343 static void	em_enable_wakeup(if_ctx_t);
344 static int	em_enable_phy_wakeup(struct e1000_softc *);
345 static void	em_disable_aspm(struct e1000_softc *);
346 
347 int		em_intr(void *);
348 
349 /* MSI-X handlers */
350 static int	em_if_msix_intr_assign(if_ctx_t, int);
351 static int	em_msix_link(void *);
352 static void	em_handle_link(void *);
353 
354 static void	em_enable_vectors_82574(if_ctx_t);
355 
356 static int	em_set_flowcntl(SYSCTL_HANDLER_ARGS);
357 static int	em_sysctl_eee(SYSCTL_HANDLER_ARGS);
358 static void	em_if_led_func(if_ctx_t, int);
359 
360 static int	em_get_regs(SYSCTL_HANDLER_ARGS);
361 
362 static void	lem_smartspeed(struct e1000_softc *);
363 static void	igb_configure_queues(struct e1000_softc *);
364 static void	em_flush_desc_rings(struct e1000_softc *);
365 
366 
367 /*********************************************************************
368  *  FreeBSD Device Interface Entry Points
369  *********************************************************************/
370 static device_method_t em_methods[] = {
371 	/* Device interface */
372 	DEVMETHOD(device_register, em_register),
373 	DEVMETHOD(device_probe, iflib_device_probe),
374 	DEVMETHOD(device_attach, iflib_device_attach),
375 	DEVMETHOD(device_detach, iflib_device_detach),
376 	DEVMETHOD(device_shutdown, iflib_device_shutdown),
377 	DEVMETHOD(device_suspend, iflib_device_suspend),
378 	DEVMETHOD(device_resume, iflib_device_resume),
379 	DEVMETHOD_END
380 };
381 
382 static device_method_t igb_methods[] = {
383 	/* Device interface */
384 	DEVMETHOD(device_register, igb_register),
385 	DEVMETHOD(device_probe, iflib_device_probe),
386 	DEVMETHOD(device_attach, iflib_device_attach),
387 	DEVMETHOD(device_detach, iflib_device_detach),
388 	DEVMETHOD(device_shutdown, iflib_device_shutdown),
389 	DEVMETHOD(device_suspend, iflib_device_suspend),
390 	DEVMETHOD(device_resume, iflib_device_resume),
391 	DEVMETHOD_END
392 };
393 
394 
395 static driver_t em_driver = {
396 	"em", em_methods, sizeof(struct e1000_softc),
397 };
398 
399 DRIVER_MODULE(em, pci, em_driver, 0, 0);
400 
401 MODULE_DEPEND(em, pci, 1, 1, 1);
402 MODULE_DEPEND(em, ether, 1, 1, 1);
403 MODULE_DEPEND(em, iflib, 1, 1, 1);
404 
405 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
406 
407 static driver_t igb_driver = {
408 	"igb", igb_methods, sizeof(struct e1000_softc),
409 };
410 
411 DRIVER_MODULE(igb, pci, igb_driver, 0, 0);
412 
413 MODULE_DEPEND(igb, pci, 1, 1, 1);
414 MODULE_DEPEND(igb, ether, 1, 1, 1);
415 MODULE_DEPEND(igb, iflib, 1, 1, 1);
416 
417 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
418 
419 static device_method_t em_if_methods[] = {
420 	DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
421 	DEVMETHOD(ifdi_attach_post, em_if_attach_post),
422 	DEVMETHOD(ifdi_detach, em_if_detach),
423 	DEVMETHOD(ifdi_shutdown, em_if_shutdown),
424 	DEVMETHOD(ifdi_suspend, em_if_suspend),
425 	DEVMETHOD(ifdi_resume, em_if_resume),
426 	DEVMETHOD(ifdi_init, em_if_init),
427 	DEVMETHOD(ifdi_stop, em_if_stop),
428 	DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
429 	DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
430 	DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
431 	DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
432 	DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
433 	DEVMETHOD(ifdi_queues_free, em_if_queues_free),
434 	DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
435 	DEVMETHOD(ifdi_multi_set, em_if_multi_set),
436 	DEVMETHOD(ifdi_media_status, em_if_media_status),
437 	DEVMETHOD(ifdi_media_change, em_if_media_change),
438 	DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
439 	DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
440 	DEVMETHOD(ifdi_timer, em_if_timer),
441 	DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
442 	DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
443 	DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
444 	DEVMETHOD(ifdi_get_counter, em_if_get_counter),
445 	DEVMETHOD(ifdi_led_func, em_if_led_func),
446 	DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
447 	DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
448 	DEVMETHOD(ifdi_debug, em_if_debug),
449 	DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
450 	DEVMETHOD_END
451 };
452 
453 static driver_t em_if_driver = {
454 	"em_if", em_if_methods, sizeof(struct e1000_softc)
455 };
456 
457 static device_method_t igb_if_methods[] = {
458 	DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
459 	DEVMETHOD(ifdi_attach_post, em_if_attach_post),
460 	DEVMETHOD(ifdi_detach, em_if_detach),
461 	DEVMETHOD(ifdi_shutdown, em_if_shutdown),
462 	DEVMETHOD(ifdi_suspend, em_if_suspend),
463 	DEVMETHOD(ifdi_resume, em_if_resume),
464 	DEVMETHOD(ifdi_init, em_if_init),
465 	DEVMETHOD(ifdi_stop, em_if_stop),
466 	DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
467 	DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
468 	DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
469 	DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
470 	DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
471 	DEVMETHOD(ifdi_queues_free, em_if_queues_free),
472 	DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
473 	DEVMETHOD(ifdi_multi_set, em_if_multi_set),
474 	DEVMETHOD(ifdi_media_status, em_if_media_status),
475 	DEVMETHOD(ifdi_media_change, em_if_media_change),
476 	DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
477 	DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
478 	DEVMETHOD(ifdi_timer, em_if_timer),
479 	DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
480 	DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
481 	DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
482 	DEVMETHOD(ifdi_get_counter, em_if_get_counter),
483 	DEVMETHOD(ifdi_led_func, em_if_led_func),
484 	DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
485 	DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
486 	DEVMETHOD(ifdi_debug, em_if_debug),
487 	DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
488 	DEVMETHOD_END
489 };
490 
491 static driver_t igb_if_driver = {
492 	"igb_if", igb_if_methods, sizeof(struct e1000_softc)
493 };
494 
495 /*********************************************************************
496  *  Tunable default values.
497  *********************************************************************/
498 
499 #define EM_TICKS_TO_USECS(ticks)	((1024 * (ticks) + 500) / 1000)
500 #define EM_USECS_TO_TICKS(usecs)	((1000 * (usecs) + 512) / 1024)
501 
502 #define MAX_INTS_PER_SEC	8000
503 #define DEFAULT_ITR		(1000000000/(MAX_INTS_PER_SEC * 256))
504 
505 /* Allow common code without TSO */
506 #ifndef CSUM_TSO
507 #define CSUM_TSO	0
508 #endif
509 
510 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
511     "EM driver parameters");
512 
513 static int em_disable_crc_stripping = 0;
514 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
515     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
516 
517 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
518 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
519 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
520     0, "Default transmit interrupt delay in usecs");
521 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
522     0, "Default receive interrupt delay in usecs");
523 
524 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
525 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
526 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
527     &em_tx_abs_int_delay_dflt, 0,
528     "Default transmit interrupt delay limit in usecs");
529 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
530     &em_rx_abs_int_delay_dflt, 0,
531     "Default receive interrupt delay limit in usecs");
532 
533 static int em_smart_pwr_down = false;
534 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
535     0, "Set to true to leave smart power down enabled on newer adapters");
536 
537 static bool em_unsupported_tso = false;
538 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN,
539     &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations");
540 
541 /* Controls whether promiscuous also shows bad packets */
542 static int em_debug_sbp = false;
543 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
544     "Show bad packets in promiscuous mode");
545 
546 /* How many packets rxeof tries to clean at a time */
547 static int em_rx_process_limit = 100;
548 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
549     &em_rx_process_limit, 0,
550     "Maximum number of received packets to process "
551     "at a time, -1 means unlimited");
552 
553 /* Energy efficient ethernet - default to OFF */
554 static int eee_setting = 1;
555 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
556     "Enable Energy Efficient Ethernet");
557 
558 /*
559 ** Tuneable Interrupt rate
560 */
561 static int em_max_interrupt_rate = 8000;
562 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
563     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
564 
565 
566 
567 /* Global used in WOL setup with multiport cards */
568 static int global_quad_port_a = 0;
569 
570 extern struct if_txrx igb_txrx;
571 extern struct if_txrx em_txrx;
572 extern struct if_txrx lem_txrx;
573 
574 static struct if_shared_ctx em_sctx_init = {
575 	.isc_magic = IFLIB_MAGIC,
576 	.isc_q_align = PAGE_SIZE,
577 	.isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
578 	.isc_tx_maxsegsize = PAGE_SIZE,
579 	.isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
580 	.isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
581 	.isc_rx_maxsize = MJUM9BYTES,
582 	.isc_rx_nsegments = 1,
583 	.isc_rx_maxsegsize = MJUM9BYTES,
584 	.isc_nfl = 1,
585 	.isc_nrxqs = 1,
586 	.isc_ntxqs = 1,
587 	.isc_admin_intrcnt = 1,
588 	.isc_vendor_info = em_vendor_info_array,
589 	.isc_driver_version = em_driver_version,
590 	.isc_driver = &em_if_driver,
591 	.isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
592 
593 	.isc_nrxd_min = {EM_MIN_RXD},
594 	.isc_ntxd_min = {EM_MIN_TXD},
595 	.isc_nrxd_max = {EM_MAX_RXD},
596 	.isc_ntxd_max = {EM_MAX_TXD},
597 	.isc_nrxd_default = {EM_DEFAULT_RXD},
598 	.isc_ntxd_default = {EM_DEFAULT_TXD},
599 };
600 
601 static struct if_shared_ctx igb_sctx_init = {
602 	.isc_magic = IFLIB_MAGIC,
603 	.isc_q_align = PAGE_SIZE,
604 	.isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
605 	.isc_tx_maxsegsize = PAGE_SIZE,
606 	.isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
607 	.isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
608 	.isc_rx_maxsize = MJUM9BYTES,
609 	.isc_rx_nsegments = 1,
610 	.isc_rx_maxsegsize = MJUM9BYTES,
611 	.isc_nfl = 1,
612 	.isc_nrxqs = 1,
613 	.isc_ntxqs = 1,
614 	.isc_admin_intrcnt = 1,
615 	.isc_vendor_info = igb_vendor_info_array,
616 	.isc_driver_version = igb_driver_version,
617 	.isc_driver = &igb_if_driver,
618 	.isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
619 
620 	.isc_nrxd_min = {EM_MIN_RXD},
621 	.isc_ntxd_min = {EM_MIN_TXD},
622 	.isc_nrxd_max = {IGB_MAX_RXD},
623 	.isc_ntxd_max = {IGB_MAX_TXD},
624 	.isc_nrxd_default = {EM_DEFAULT_RXD},
625 	.isc_ntxd_default = {EM_DEFAULT_TXD},
626 };
627 
628 /*****************************************************************
629  *
630  * Dump Registers
631  *
632  ****************************************************************/
633 #define IGB_REGS_LEN 739
634 
635 static int em_get_regs(SYSCTL_HANDLER_ARGS)
636 {
637 	struct e1000_softc *sc = (struct e1000_softc *)arg1;
638 	struct e1000_hw *hw = &sc->hw;
639 	struct sbuf *sb;
640 	u32 *regs_buff;
641 	int rc;
642 
643 	regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
644 	memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
645 
646 	rc = sysctl_wire_old_buffer(req, 0);
647 	MPASS(rc == 0);
648 	if (rc != 0) {
649 		free(regs_buff, M_DEVBUF);
650 		return (rc);
651 	}
652 
653 	sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
654 	MPASS(sb != NULL);
655 	if (sb == NULL) {
656 		free(regs_buff, M_DEVBUF);
657 		return (ENOMEM);
658 	}
659 
660 	/* General Registers */
661 	regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
662 	regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
663 	regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
664 	regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
665 	regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
666 	regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
667 	regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
668 	regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
669 	regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
670 	regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
671 	regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
672 	regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
673 	regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
674 	regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
675 	regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
676 	regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
677 	regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
678 	regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
679 	regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
680 	regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
681 	regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
682 	regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
683 
684 	sbuf_printf(sb, "General Registers\n");
685 	sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
686 	sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
687 	sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
688 
689 	sbuf_printf(sb, "Interrupt Registers\n");
690 	sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
691 
692 	sbuf_printf(sb, "RX Registers\n");
693 	sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
694 	sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
695 	sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
696 	sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
697 	sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
698 	sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
699 	sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
700 
701 	sbuf_printf(sb, "TX Registers\n");
702 	sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
703 	sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
704 	sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
705 	sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
706 	sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
707 	sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
708 	sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
709 	sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
710 	sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
711 	sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
712 	sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
713 
714 	free(regs_buff, M_DEVBUF);
715 
716 #ifdef DUMP_DESCS
717 	{
718 		if_softc_ctx_t scctx = sc->shared;
719 		struct rx_ring *rxr = &rx_que->rxr;
720 		struct tx_ring *txr = &tx_que->txr;
721 		int ntxd = scctx->isc_ntxd[0];
722 		int nrxd = scctx->isc_nrxd[0];
723 		int j;
724 
725 	for (j = 0; j < nrxd; j++) {
726 		u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
727 		u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
728 		sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
729 	}
730 
731 	for (j = 0; j < min(ntxd, 256); j++) {
732 		unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
733 
734 		sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
735 			    j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
736 			    buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
737 
738 	}
739 	}
740 #endif
741 
742 	rc = sbuf_finish(sb);
743 	sbuf_delete(sb);
744 	return(rc);
745 }
746 
747 static void *
748 em_register(device_t dev)
749 {
750 	return (&em_sctx_init);
751 }
752 
753 static void *
754 igb_register(device_t dev)
755 {
756 	return (&igb_sctx_init);
757 }
758 
759 static int
760 em_set_num_queues(if_ctx_t ctx)
761 {
762 	struct e1000_softc *sc = iflib_get_softc(ctx);
763 	int maxqueues;
764 
765 	/* Sanity check based on HW */
766 	switch (sc->hw.mac.type) {
767 	case e1000_82576:
768 	case e1000_82580:
769 	case e1000_i350:
770 	case e1000_i354:
771 		maxqueues = 8;
772 		break;
773 	case e1000_i210:
774 	case e1000_82575:
775 		maxqueues = 4;
776 		break;
777 	case e1000_i211:
778 	case e1000_82574:
779 		maxqueues = 2;
780 		break;
781 	default:
782 		maxqueues = 1;
783 		break;
784 	}
785 
786 	return (maxqueues);
787 }
788 
789 #define LEM_CAPS \
790     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
791     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
792     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6
793 
794 #define EM_CAPS \
795     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
796     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
797     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \
798     IFCAP_TSO6
799 
800 #define IGB_CAPS \
801     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
802     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
803     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \
804     IFCAP_TSO6
805 
806 /*********************************************************************
807  *  Device initialization routine
808  *
809  *  The attach entry point is called when the driver is being loaded.
810  *  This routine identifies the type of hardware, allocates all resources
811  *  and initializes the hardware.
812  *
813  *  return 0 on success, positive on failure
814  *********************************************************************/
815 static int
816 em_if_attach_pre(if_ctx_t ctx)
817 {
818 	struct e1000_softc *sc;
819 	if_softc_ctx_t scctx;
820 	device_t dev;
821 	struct e1000_hw *hw;
822 	struct sysctl_oid_list *child;
823 	struct sysctl_ctx_list *ctx_list;
824 	int error = 0;
825 
826 	INIT_DEBUGOUT("em_if_attach_pre: begin");
827 	dev = iflib_get_dev(ctx);
828 	sc = iflib_get_softc(ctx);
829 
830 	sc->ctx = sc->osdep.ctx = ctx;
831 	sc->dev = sc->osdep.dev = dev;
832 	scctx = sc->shared = iflib_get_softc_ctx(ctx);
833 	sc->media = iflib_get_media(ctx);
834 	hw = &sc->hw;
835 
836 	sc->tx_process_limit = scctx->isc_ntxd[0];
837 
838 	/* Determine hardware and mac info */
839 	em_identify_hardware(ctx);
840 
841 	/* SYSCTL stuff */
842 	ctx_list = device_get_sysctl_ctx(dev);
843 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
844 
845 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm",
846 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
847 	    em_sysctl_nvm_info, "I", "NVM Information");
848 
849 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
850 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
851 	    em_sysctl_print_fw_version, "A",
852 	    "Prints FW/NVM Versions");
853 
854 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug",
855 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
856 	    em_sysctl_debug_info, "I", "Debug Information");
857 
858 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc",
859 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
860 	    em_set_flowcntl, "I", "Flow Control");
861 
862 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump",
863 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
864 	    em_get_regs, "A", "Dump Registers");
865 
866 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump",
867 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
868 	    em_get_rs, "I", "Dump RS indexes");
869 
870 	scctx->isc_tx_nsegments = EM_MAX_SCATTER;
871 	scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
872 	if (bootverbose)
873 		device_printf(dev, "attach_pre capping queues at %d\n",
874 		    scctx->isc_ntxqsets_max);
875 
876 	if (hw->mac.type >= igb_mac_min) {
877 		scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
878 		scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
879 		scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
880 		scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
881 		scctx->isc_txrx = &igb_txrx;
882 		scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
883 		scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
884 		scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
885 		scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
886 		scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
887 		     CSUM_IP6_TCP | CSUM_IP6_UDP;
888 		if (hw->mac.type != e1000_82575)
889 			scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
890 		/*
891 		** Some new devices, as with ixgbe, now may
892 		** use a different BAR, so we need to keep
893 		** track of which is used.
894 		*/
895 		scctx->isc_msix_bar = pci_msix_table_bar(dev);
896 	} else if (hw->mac.type >= em_mac_min) {
897 		scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
898 		scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
899 		scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
900 		scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
901 		scctx->isc_txrx = &em_txrx;
902 		scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
903 		scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
904 		scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
905 		scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
906 		scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
907 		    CSUM_IP6_TCP | CSUM_IP6_UDP;
908 
909 		/*
910 		 * Disable TSO on SPT due to errata that downclocks DMA performance
911 		 * i218-i219 Specification Update 1.5.4.5
912 		 */
913 		if (hw->mac.type == e1000_pch_spt)
914 			scctx->isc_capenable &= ~IFCAP_TSO;
915 
916 		/*
917 		 * We support MSI-X with 82574 only, but indicate to iflib(4)
918 		 * that it shall give MSI at least a try with other devices.
919 		 */
920 		if (hw->mac.type == e1000_82574) {
921 			scctx->isc_msix_bar = pci_msix_table_bar(dev);
922 		} else {
923 			scctx->isc_msix_bar = -1;
924 			scctx->isc_disable_msix = 1;
925 		}
926 	} else {
927 		scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
928 		scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
929 		scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
930 		scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
931 		scctx->isc_txrx = &lem_txrx;
932 		scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
933 		scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
934 		scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
935 		scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
936 		if (em_unsupported_tso)
937 			scctx->isc_capabilities |= IFCAP_TSO6;
938 		scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
939 		    CSUM_IP6_TCP | CSUM_IP6_UDP;
940 
941 		/* 82541ER doesn't do HW tagging */
942 		if (hw->device_id == E1000_DEV_ID_82541ER ||
943 		    hw->device_id == E1000_DEV_ID_82541ER_LOM) {
944 			scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING;
945 			scctx->isc_capenable = scctx->isc_capabilities;
946 		}
947 		/* This is the first e1000 chip and it does not do offloads */
948 		if (hw->mac.type == e1000_82542) {
949 			scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
950 			    IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING |
951 			    IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO);
952 			scctx->isc_capenable = scctx->isc_capabilities;
953 		}
954 		/* These can't do TSO for various reasons */
955 		if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 ||
956 		    hw->mac.type == e1000_82547_rev_2) {
957 			scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO);
958 			scctx->isc_capenable = scctx->isc_capabilities;
959 		}
960 		/* XXXKB: No IPv6 before this? */
961 		if (hw->mac.type < e1000_82545){
962 			scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6;
963 			scctx->isc_capenable = scctx->isc_capabilities;
964 		}
965 		/* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */
966 		if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2)
967 			scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
968 			    IFCAP_HWCSUM_IPV6);
969 
970 		/* INTx only */
971 		scctx->isc_msix_bar = 0;
972 	}
973 
974 	/* Setup PCI resources */
975 	if (em_allocate_pci_resources(ctx)) {
976 		device_printf(dev, "Allocation of PCI resources failed\n");
977 		error = ENXIO;
978 		goto err_pci;
979 	}
980 
981 	/*
982 	** For ICH8 and family we need to
983 	** map the flash memory, and this
984 	** must happen after the MAC is
985 	** identified
986 	*/
987 	if ((hw->mac.type == e1000_ich8lan) ||
988 	    (hw->mac.type == e1000_ich9lan) ||
989 	    (hw->mac.type == e1000_ich10lan) ||
990 	    (hw->mac.type == e1000_pchlan) ||
991 	    (hw->mac.type == e1000_pch2lan) ||
992 	    (hw->mac.type == e1000_pch_lpt)) {
993 		int rid = EM_BAR_TYPE_FLASH;
994 		sc->flash = bus_alloc_resource_any(dev,
995 		    SYS_RES_MEMORY, &rid, RF_ACTIVE);
996 		if (sc->flash == NULL) {
997 			device_printf(dev, "Mapping of Flash failed\n");
998 			error = ENXIO;
999 			goto err_pci;
1000 		}
1001 		/* This is used in the shared code */
1002 		hw->flash_address = (u8 *)sc->flash;
1003 		sc->osdep.flash_bus_space_tag =
1004 		    rman_get_bustag(sc->flash);
1005 		sc->osdep.flash_bus_space_handle =
1006 		    rman_get_bushandle(sc->flash);
1007 	}
1008 	/*
1009 	** In the new SPT device flash is not  a
1010 	** separate BAR, rather it is also in BAR0,
1011 	** so use the same tag and an offset handle for the
1012 	** FLASH read/write macros in the shared code.
1013 	*/
1014 	else if (hw->mac.type >= e1000_pch_spt) {
1015 		sc->osdep.flash_bus_space_tag =
1016 		    sc->osdep.mem_bus_space_tag;
1017 		sc->osdep.flash_bus_space_handle =
1018 		    sc->osdep.mem_bus_space_handle
1019 		    + E1000_FLASH_BASE_ADDR;
1020 	}
1021 
1022 	/* Do Shared Code initialization */
1023 	error = e1000_setup_init_funcs(hw, true);
1024 	if (error) {
1025 		device_printf(dev, "Setup of Shared code failed, error %d\n",
1026 		    error);
1027 		error = ENXIO;
1028 		goto err_pci;
1029 	}
1030 
1031 	em_setup_msix(ctx);
1032 	e1000_get_bus_info(hw);
1033 
1034 	/* Set up some sysctls for the tunable interrupt delays */
1035 	em_add_int_delay_sysctl(sc, "rx_int_delay",
1036 	    "receive interrupt delay in usecs", &sc->rx_int_delay,
1037 	    E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
1038 	em_add_int_delay_sysctl(sc, "tx_int_delay",
1039 	    "transmit interrupt delay in usecs", &sc->tx_int_delay,
1040 	    E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
1041 	em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
1042 	    "receive interrupt delay limit in usecs",
1043 	    &sc->rx_abs_int_delay,
1044 	    E1000_REGISTER(hw, E1000_RADV),
1045 	    em_rx_abs_int_delay_dflt);
1046 	em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
1047 	    "transmit interrupt delay limit in usecs",
1048 	    &sc->tx_abs_int_delay,
1049 	    E1000_REGISTER(hw, E1000_TADV),
1050 	    em_tx_abs_int_delay_dflt);
1051 	em_add_int_delay_sysctl(sc, "itr",
1052 	    "interrupt delay limit in usecs/4",
1053 	    &sc->tx_itr,
1054 	    E1000_REGISTER(hw, E1000_ITR),
1055 	    DEFAULT_ITR);
1056 
1057 	hw->mac.autoneg = DO_AUTO_NEG;
1058 	hw->phy.autoneg_wait_to_complete = false;
1059 	hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1060 
1061 	if (hw->mac.type < em_mac_min) {
1062 		e1000_init_script_state_82541(hw, true);
1063 		e1000_set_tbi_compatibility_82543(hw, true);
1064 	}
1065 	/* Copper options */
1066 	if (hw->phy.media_type == e1000_media_type_copper) {
1067 		hw->phy.mdix = AUTO_ALL_MODES;
1068 		hw->phy.disable_polarity_correction = false;
1069 		hw->phy.ms_type = EM_MASTER_SLAVE;
1070 	}
1071 
1072 	/*
1073 	 * Set the frame limits assuming
1074 	 * standard ethernet sized frames.
1075 	 */
1076 	scctx->isc_max_frame_size = hw->mac.max_frame_size =
1077 	    ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1078 
1079 	/*
1080 	 * This controls when hardware reports transmit completion
1081 	 * status.
1082 	 */
1083 	hw->mac.report_tx_early = 1;
1084 
1085 	/* Allocate multicast array memory. */
1086 	sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1087 	    MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1088 	if (sc->mta == NULL) {
1089 		device_printf(dev, "Can not allocate multicast setup array\n");
1090 		error = ENOMEM;
1091 		goto err_late;
1092 	}
1093 
1094 	/* Clear the IFCAP_TSO auto mask */
1095 	sc->tso_automasked = 0;
1096 
1097 	/* Check SOL/IDER usage */
1098 	if (e1000_check_reset_block(hw))
1099 		device_printf(dev, "PHY reset is blocked"
1100 			      " due to SOL/IDER session.\n");
1101 
1102 	/* Sysctl for setting Energy Efficient Ethernet */
1103 	hw->dev_spec.ich8lan.eee_disable = eee_setting;
1104 	SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control",
1105 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
1106 	    em_sysctl_eee, "I", "Disable Energy Efficient Ethernet");
1107 
1108 	/*
1109 	** Start from a known state, this is
1110 	** important in reading the nvm and
1111 	** mac from that.
1112 	*/
1113 	e1000_reset_hw(hw);
1114 
1115 	/* Make sure we have a good EEPROM before we read from it */
1116 	if (e1000_validate_nvm_checksum(hw) < 0) {
1117 		/*
1118 		** Some PCI-E parts fail the first check due to
1119 		** the link being in sleep state, call it again,
1120 		** if it fails a second time its a real issue.
1121 		*/
1122 		if (e1000_validate_nvm_checksum(hw) < 0) {
1123 			device_printf(dev,
1124 			    "The EEPROM Checksum Is Not Valid\n");
1125 			error = EIO;
1126 			goto err_late;
1127 		}
1128 	}
1129 
1130 	/* Copy the permanent MAC address out of the EEPROM */
1131 	if (e1000_read_mac_addr(hw) < 0) {
1132 		device_printf(dev, "EEPROM read error while reading MAC"
1133 			      " address\n");
1134 		error = EIO;
1135 		goto err_late;
1136 	}
1137 
1138 	if (!em_is_valid_ether_addr(hw->mac.addr)) {
1139 		if (sc->vf_ifp) {
1140 			ether_gen_addr(iflib_get_ifp(ctx),
1141 			    (struct ether_addr *)hw->mac.addr);
1142 		} else {
1143 			device_printf(dev, "Invalid MAC address\n");
1144 			error = EIO;
1145 			goto err_late;
1146 		}
1147 	}
1148 
1149 	/* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */
1150 	em_fw_version_locked(ctx);
1151 
1152 	em_print_fw_version(sc);
1153 
1154 	/*
1155 	 * Get Wake-on-Lan and Management info for later use
1156 	 */
1157 	em_get_wakeup(ctx);
1158 
1159 	/* Enable only WOL MAGIC by default */
1160 	scctx->isc_capenable &= ~IFCAP_WOL;
1161 	if (sc->wol != 0)
1162 		scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1163 
1164 	iflib_set_mac(ctx, hw->mac.addr);
1165 
1166 	return (0);
1167 
1168 err_late:
1169 	em_release_hw_control(sc);
1170 err_pci:
1171 	em_free_pci_resources(ctx);
1172 	free(sc->mta, M_DEVBUF);
1173 
1174 	return (error);
1175 }
1176 
1177 static int
1178 em_if_attach_post(if_ctx_t ctx)
1179 {
1180 	struct e1000_softc *sc = iflib_get_softc(ctx);
1181 	struct e1000_hw *hw = &sc->hw;
1182 	int error = 0;
1183 
1184 	/* Setup OS specific network interface */
1185 	error = em_setup_interface(ctx);
1186 	if (error != 0) {
1187 		device_printf(sc->dev, "Interface setup failed: %d\n", error);
1188 		goto err_late;
1189 	}
1190 
1191 	em_reset(ctx);
1192 
1193 	/* Initialize statistics */
1194 	em_update_stats_counters(sc);
1195 	hw->mac.get_link_status = 1;
1196 	em_if_update_admin_status(ctx);
1197 	em_add_hw_stats(sc);
1198 
1199 	/* Non-AMT based hardware can now take control from firmware */
1200 	if (sc->has_manage && !sc->has_amt)
1201 		em_get_hw_control(sc);
1202 
1203 	INIT_DEBUGOUT("em_if_attach_post: end");
1204 
1205 	return (0);
1206 
1207 err_late:
1208 	/* upon attach_post() error, iflib calls _if_detach() to free resources. */
1209 	return (error);
1210 }
1211 
1212 /*********************************************************************
1213  *  Device removal routine
1214  *
1215  *  The detach entry point is called when the driver is being removed.
1216  *  This routine stops the adapter and deallocates all the resources
1217  *  that were allocated for driver operation.
1218  *
1219  *  return 0 on success, positive on failure
1220  *********************************************************************/
1221 static int
1222 em_if_detach(if_ctx_t ctx)
1223 {
1224 	struct e1000_softc	*sc = iflib_get_softc(ctx);
1225 
1226 	INIT_DEBUGOUT("em_if_detach: begin");
1227 
1228 	e1000_phy_hw_reset(&sc->hw);
1229 
1230 	em_release_manageability(sc);
1231 	em_release_hw_control(sc);
1232 	em_free_pci_resources(ctx);
1233 	free(sc->mta, M_DEVBUF);
1234 	sc->mta = NULL;
1235 
1236 	return (0);
1237 }
1238 
1239 /*********************************************************************
1240  *
1241  *  Shutdown entry point
1242  *
1243  **********************************************************************/
1244 
1245 static int
1246 em_if_shutdown(if_ctx_t ctx)
1247 {
1248 	return em_if_suspend(ctx);
1249 }
1250 
1251 /*
1252  * Suspend/resume device methods.
1253  */
1254 static int
1255 em_if_suspend(if_ctx_t ctx)
1256 {
1257 	struct e1000_softc *sc = iflib_get_softc(ctx);
1258 
1259 	em_release_manageability(sc);
1260 	em_release_hw_control(sc);
1261 	em_enable_wakeup(ctx);
1262 	return (0);
1263 }
1264 
1265 static int
1266 em_if_resume(if_ctx_t ctx)
1267 {
1268 	struct e1000_softc *sc = iflib_get_softc(ctx);
1269 
1270 	if (sc->hw.mac.type == e1000_pch2lan)
1271 		e1000_resume_workarounds_pchlan(&sc->hw);
1272 	em_if_init(ctx);
1273 	em_init_manageability(sc);
1274 
1275 	return(0);
1276 }
1277 
1278 static int
1279 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1280 {
1281 	int max_frame_size;
1282 	struct e1000_softc *sc = iflib_get_softc(ctx);
1283 	if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1284 
1285 	IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1286 
1287 	switch (sc->hw.mac.type) {
1288 	case e1000_82571:
1289 	case e1000_82572:
1290 	case e1000_ich9lan:
1291 	case e1000_ich10lan:
1292 	case e1000_pch2lan:
1293 	case e1000_pch_lpt:
1294 	case e1000_pch_spt:
1295 	case e1000_pch_cnp:
1296 	case e1000_pch_tgp:
1297 	case e1000_pch_adp:
1298 	case e1000_pch_mtp:
1299 	case e1000_pch_ptp:
1300 	case e1000_82574:
1301 	case e1000_82583:
1302 	case e1000_80003es2lan:
1303 		/* 9K Jumbo Frame size */
1304 		max_frame_size = 9234;
1305 		break;
1306 	case e1000_pchlan:
1307 		max_frame_size = 4096;
1308 		break;
1309 	case e1000_82542:
1310 	case e1000_ich8lan:
1311 		/* Adapters that do not support jumbo frames */
1312 		max_frame_size = ETHER_MAX_LEN;
1313 		break;
1314 	default:
1315 		if (sc->hw.mac.type >= igb_mac_min)
1316 			max_frame_size = 9234;
1317 		else /* lem */
1318 			max_frame_size = MAX_JUMBO_FRAME_SIZE;
1319 	}
1320 	if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1321 		return (EINVAL);
1322 	}
1323 
1324 	scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
1325 	    mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1326 	return (0);
1327 }
1328 
1329 /*********************************************************************
1330  *  Init entry point
1331  *
1332  *  This routine is used in two ways. It is used by the stack as
1333  *  init entry point in network interface structure. It is also used
1334  *  by the driver as a hw/sw initialization routine to get to a
1335  *  consistent state.
1336  *
1337  **********************************************************************/
1338 static void
1339 em_if_init(if_ctx_t ctx)
1340 {
1341 	struct e1000_softc *sc = iflib_get_softc(ctx);
1342 	if_softc_ctx_t scctx = sc->shared;
1343 	if_t ifp = iflib_get_ifp(ctx);
1344 	struct em_tx_queue *tx_que;
1345 	int i;
1346 
1347 	INIT_DEBUGOUT("em_if_init: begin");
1348 
1349 	/* Get the latest mac address, User can use a LAA */
1350 	bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
1351 	    ETHER_ADDR_LEN);
1352 
1353 	/* Put the address into the Receive Address Array */
1354 	e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1355 
1356 	/*
1357 	 * With the 82571 adapter, RAR[0] may be overwritten
1358 	 * when the other port is reset, we make a duplicate
1359 	 * in RAR[14] for that eventuality, this assures
1360 	 * the interface continues to function.
1361 	 */
1362 	if (sc->hw.mac.type == e1000_82571) {
1363 		e1000_set_laa_state_82571(&sc->hw, true);
1364 		e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1365 		    E1000_RAR_ENTRIES - 1);
1366 	}
1367 
1368 	/* Initialize the hardware */
1369 	em_reset(ctx);
1370 	em_if_update_admin_status(ctx);
1371 
1372 	for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) {
1373 		struct tx_ring *txr = &tx_que->txr;
1374 
1375 		txr->tx_rs_cidx = txr->tx_rs_pidx;
1376 
1377 		/* Initialize the last processed descriptor to be the end of
1378 		 * the ring, rather than the start, so that we avoid an
1379 		 * off-by-one error when calculating how many descriptors are
1380 		 * done in the credits_update function.
1381 		 */
1382 		txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1383 	}
1384 
1385 	/* Setup VLAN support, basic and offload if available */
1386 	E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1387 
1388 	/* Clear bad data from Rx FIFOs */
1389 	if (sc->hw.mac.type >= igb_mac_min)
1390 		e1000_rx_fifo_flush_base(&sc->hw);
1391 
1392 	/* Configure for OS presence */
1393 	em_init_manageability(sc);
1394 
1395 	/* Prepare transmit descriptors and buffers */
1396 	em_initialize_transmit_unit(ctx);
1397 
1398 	/* Setup Multicast table */
1399 	em_if_multi_set(ctx);
1400 
1401 	sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1402 	em_initialize_receive_unit(ctx);
1403 
1404 	/* Set up VLAN support and filter */
1405 	em_setup_vlan_hw_support(ctx);
1406 
1407 	/* Don't lose promiscuous settings */
1408 	em_if_set_promisc(ctx, if_getflags(ifp));
1409 	e1000_clear_hw_cntrs_base_generic(&sc->hw);
1410 
1411 	/* MSI-X configuration for 82574 */
1412 	if (sc->hw.mac.type == e1000_82574) {
1413 		int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1414 
1415 		tmp |= E1000_CTRL_EXT_PBA_CLR;
1416 		E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1417 		/* Set the IVAR - interrupt vector routing. */
1418 		E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
1419 	} else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1420 		igb_configure_queues(sc);
1421 
1422 	/* this clears any pending interrupts */
1423 	E1000_READ_REG(&sc->hw, E1000_ICR);
1424 	E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1425 
1426 	/* AMT based hardware can now take control from firmware */
1427 	if (sc->has_manage && sc->has_amt)
1428 		em_get_hw_control(sc);
1429 
1430 	/* Set Energy Efficient Ethernet */
1431 	if (sc->hw.mac.type >= igb_mac_min &&
1432 	    sc->hw.phy.media_type == e1000_media_type_copper) {
1433 		if (sc->hw.mac.type == e1000_i354)
1434 			e1000_set_eee_i354(&sc->hw, true, true);
1435 		else
1436 			e1000_set_eee_i350(&sc->hw, true, true);
1437 	}
1438 }
1439 
1440 /*********************************************************************
1441  *
1442  *  Fast Legacy/MSI Combined Interrupt Service routine
1443  *
1444  *********************************************************************/
1445 int
1446 em_intr(void *arg)
1447 {
1448 	struct e1000_softc *sc = arg;
1449 	if_ctx_t ctx = sc->ctx;
1450 	u32 reg_icr;
1451 
1452 	reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1453 
1454 	/* Hot eject? */
1455 	if (reg_icr == 0xffffffff)
1456 		return FILTER_STRAY;
1457 
1458 	/* Definitely not our interrupt. */
1459 	if (reg_icr == 0x0)
1460 		return FILTER_STRAY;
1461 
1462 	/*
1463 	 * Starting with the 82571 chip, bit 31 should be used to
1464 	 * determine whether the interrupt belongs to us.
1465 	 */
1466 	if (sc->hw.mac.type >= e1000_82571 &&
1467 	    (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1468 		return FILTER_STRAY;
1469 
1470 	/*
1471 	 * Only MSI-X interrupts have one-shot behavior by taking advantage
1472 	 * of the EIAC register.  Thus, explicitly disable interrupts.  This
1473 	 * also works around the MSI message reordering errata on certain
1474 	 * systems.
1475 	 */
1476 	IFDI_INTR_DISABLE(ctx);
1477 
1478 	/* Link status change */
1479 	if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1480 		em_handle_link(ctx);
1481 
1482 	if (reg_icr & E1000_ICR_RXO)
1483 		sc->rx_overruns++;
1484 
1485 	return (FILTER_SCHEDULE_THREAD);
1486 }
1487 
1488 static int
1489 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1490 {
1491 	struct e1000_softc *sc = iflib_get_softc(ctx);
1492 	struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1493 
1494 	E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims);
1495 	return (0);
1496 }
1497 
1498 static int
1499 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1500 {
1501 	struct e1000_softc *sc = iflib_get_softc(ctx);
1502 	struct em_tx_queue *txq = &sc->tx_queues[txqid];
1503 
1504 	E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims);
1505 	return (0);
1506 }
1507 
1508 static int
1509 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1510 {
1511 	struct e1000_softc *sc = iflib_get_softc(ctx);
1512 	struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1513 
1514 	E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims);
1515 	return (0);
1516 }
1517 
1518 static int
1519 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1520 {
1521 	struct e1000_softc *sc = iflib_get_softc(ctx);
1522 	struct em_tx_queue *txq = &sc->tx_queues[txqid];
1523 
1524 	E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims);
1525 	return (0);
1526 }
1527 
1528 /*********************************************************************
1529  *
1530  *  MSI-X RX Interrupt Service routine
1531  *
1532  **********************************************************************/
1533 static int
1534 em_msix_que(void *arg)
1535 {
1536 	struct em_rx_queue *que = arg;
1537 
1538 	++que->irqs;
1539 
1540 	return (FILTER_SCHEDULE_THREAD);
1541 }
1542 
1543 /*********************************************************************
1544  *
1545  *  MSI-X Link Fast Interrupt Service routine
1546  *
1547  **********************************************************************/
1548 static int
1549 em_msix_link(void *arg)
1550 {
1551 	struct e1000_softc *sc = arg;
1552 	u32 reg_icr;
1553 
1554 	++sc->link_irq;
1555 	MPASS(sc->hw.back != NULL);
1556 	reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1557 
1558 	if (reg_icr & E1000_ICR_RXO)
1559 		sc->rx_overruns++;
1560 
1561 	if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1562 		em_handle_link(sc->ctx);
1563 
1564 	/* Re-arm unconditionally */
1565 	if (sc->hw.mac.type >= igb_mac_min) {
1566 		E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1567 		E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
1568 	} else if (sc->hw.mac.type == e1000_82574) {
1569 		E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
1570 		    E1000_IMS_OTHER);
1571 		/*
1572 		 * Because we must read the ICR for this interrupt it may
1573 		 * clear other causes using autoclear, for this reason we
1574 		 * simply create a soft interrupt for all these vectors.
1575 		 */
1576 		if (reg_icr)
1577 			E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims);
1578 	} else
1579 		E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1580 
1581 	return (FILTER_HANDLED);
1582 }
1583 
1584 static void
1585 em_handle_link(void *context)
1586 {
1587 	if_ctx_t ctx = context;
1588 	struct e1000_softc *sc = iflib_get_softc(ctx);
1589 
1590 	sc->hw.mac.get_link_status = 1;
1591 	iflib_admin_intr_deferred(ctx);
1592 }
1593 
1594 /*********************************************************************
1595  *
1596  *  Media Ioctl callback
1597  *
1598  *  This routine is called whenever the user queries the status of
1599  *  the interface using ifconfig.
1600  *
1601  **********************************************************************/
1602 static void
1603 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1604 {
1605 	struct e1000_softc *sc = iflib_get_softc(ctx);
1606 	u_char fiber_type = IFM_1000_SX;
1607 
1608 	INIT_DEBUGOUT("em_if_media_status: begin");
1609 
1610 	iflib_admin_intr_deferred(ctx);
1611 
1612 	ifmr->ifm_status = IFM_AVALID;
1613 	ifmr->ifm_active = IFM_ETHER;
1614 
1615 	if (!sc->link_active) {
1616 		return;
1617 	}
1618 
1619 	ifmr->ifm_status |= IFM_ACTIVE;
1620 
1621 	if ((sc->hw.phy.media_type == e1000_media_type_fiber) ||
1622 	    (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1623 		if (sc->hw.mac.type == e1000_82545)
1624 			fiber_type = IFM_1000_LX;
1625 		ifmr->ifm_active |= fiber_type | IFM_FDX;
1626 	} else {
1627 		switch (sc->link_speed) {
1628 		case 10:
1629 			ifmr->ifm_active |= IFM_10_T;
1630 			break;
1631 		case 100:
1632 			ifmr->ifm_active |= IFM_100_TX;
1633 			break;
1634 		case 1000:
1635 			ifmr->ifm_active |= IFM_1000_T;
1636 			break;
1637 		}
1638 		if (sc->link_duplex == FULL_DUPLEX)
1639 			ifmr->ifm_active |= IFM_FDX;
1640 		else
1641 			ifmr->ifm_active |= IFM_HDX;
1642 	}
1643 }
1644 
1645 /*********************************************************************
1646  *
1647  *  Media Ioctl callback
1648  *
1649  *  This routine is called when the user changes speed/duplex using
1650  *  media/mediopt option with ifconfig.
1651  *
1652  **********************************************************************/
1653 static int
1654 em_if_media_change(if_ctx_t ctx)
1655 {
1656 	struct e1000_softc *sc = iflib_get_softc(ctx);
1657 	struct ifmedia *ifm = iflib_get_media(ctx);
1658 
1659 	INIT_DEBUGOUT("em_if_media_change: begin");
1660 
1661 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1662 		return (EINVAL);
1663 
1664 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
1665 	case IFM_AUTO:
1666 		sc->hw.mac.autoneg = DO_AUTO_NEG;
1667 		sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1668 		break;
1669 	case IFM_1000_LX:
1670 	case IFM_1000_SX:
1671 	case IFM_1000_T:
1672 		sc->hw.mac.autoneg = DO_AUTO_NEG;
1673 		sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1674 		break;
1675 	case IFM_100_TX:
1676 		sc->hw.mac.autoneg = false;
1677 		sc->hw.phy.autoneg_advertised = 0;
1678 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1679 			sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1680 		else
1681 			sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1682 		break;
1683 	case IFM_10_T:
1684 		sc->hw.mac.autoneg = false;
1685 		sc->hw.phy.autoneg_advertised = 0;
1686 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1687 			sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1688 		else
1689 			sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1690 		break;
1691 	default:
1692 		device_printf(sc->dev, "Unsupported media type\n");
1693 	}
1694 
1695 	em_if_init(ctx);
1696 
1697 	return (0);
1698 }
1699 
1700 static int
1701 em_if_set_promisc(if_ctx_t ctx, int flags)
1702 {
1703 	struct e1000_softc *sc = iflib_get_softc(ctx);
1704 	if_t ifp = iflib_get_ifp(ctx);
1705 	u32 reg_rctl;
1706 	int mcnt = 0;
1707 
1708 	reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1709 	reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1710 	if (flags & IFF_ALLMULTI)
1711 		mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1712 	else
1713 		mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1714 
1715 	if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1716 		reg_rctl &= (~E1000_RCTL_MPE);
1717 	E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1718 
1719 	if (flags & IFF_PROMISC) {
1720 		reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1721 		em_if_vlan_filter_disable(sc);
1722 		/* Turn this on if you want to see bad packets */
1723 		if (em_debug_sbp)
1724 			reg_rctl |= E1000_RCTL_SBP;
1725 		E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1726 	} else {
1727 		if (flags & IFF_ALLMULTI) {
1728 			reg_rctl |= E1000_RCTL_MPE;
1729 			reg_rctl &= ~E1000_RCTL_UPE;
1730 			E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1731 		}
1732 		if (em_if_vlan_filter_used(ctx))
1733 			em_if_vlan_filter_enable(sc);
1734 	}
1735 	return (0);
1736 }
1737 
1738 static u_int
1739 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1740 {
1741 	u8 *mta = arg;
1742 
1743 	if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1744 		return (0);
1745 
1746 	bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1747 
1748 	return (1);
1749 }
1750 
1751 /*********************************************************************
1752  *  Multicast Update
1753  *
1754  *  This routine is called whenever multicast address list is updated.
1755  *
1756  **********************************************************************/
1757 static void
1758 em_if_multi_set(if_ctx_t ctx)
1759 {
1760 	struct e1000_softc *sc = iflib_get_softc(ctx);
1761 	if_t ifp = iflib_get_ifp(ctx);
1762 	u8  *mta; /* Multicast array memory */
1763 	u32 reg_rctl = 0;
1764 	int mcnt = 0;
1765 
1766 	IOCTL_DEBUGOUT("em_set_multi: begin");
1767 
1768 	mta = sc->mta;
1769 	bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1770 
1771 	if (sc->hw.mac.type == e1000_82542 &&
1772 	    sc->hw.revision_id == E1000_REVISION_2) {
1773 		reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1774 		if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1775 			e1000_pci_clear_mwi(&sc->hw);
1776 		reg_rctl |= E1000_RCTL_RST;
1777 		E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1778 		msec_delay(5);
1779 	}
1780 
1781 	mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1782 
1783 	if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1784 		e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1785 
1786 	reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1787 
1788 	if (if_getflags(ifp) & IFF_PROMISC)
1789 		reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1790 	else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1791 	    if_getflags(ifp) & IFF_ALLMULTI) {
1792 		reg_rctl |= E1000_RCTL_MPE;
1793 		reg_rctl &= ~E1000_RCTL_UPE;
1794 	} else
1795 		reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1796 
1797 	E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1798 
1799 	if (sc->hw.mac.type == e1000_82542 &&
1800 	    sc->hw.revision_id == E1000_REVISION_2) {
1801 		reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1802 		reg_rctl &= ~E1000_RCTL_RST;
1803 		E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1804 		msec_delay(5);
1805 		if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1806 			e1000_pci_set_mwi(&sc->hw);
1807 	}
1808 }
1809 
1810 /*********************************************************************
1811  *  Timer routine
1812  *
1813  *  This routine schedules em_if_update_admin_status() to check for
1814  *  link status and to gather statistics as well as to perform some
1815  *  controller-specific hardware patting.
1816  *
1817  **********************************************************************/
1818 static void
1819 em_if_timer(if_ctx_t ctx, uint16_t qid)
1820 {
1821 
1822 	if (qid != 0)
1823 		return;
1824 
1825 	iflib_admin_intr_deferred(ctx);
1826 }
1827 
1828 static void
1829 em_if_update_admin_status(if_ctx_t ctx)
1830 {
1831 	struct e1000_softc *sc = iflib_get_softc(ctx);
1832 	struct e1000_hw *hw = &sc->hw;
1833 	device_t dev = iflib_get_dev(ctx);
1834 	u32 link_check, thstat, ctrl;
1835 	bool automasked = false;
1836 
1837 	link_check = thstat = ctrl = 0;
1838 	/* Get the cached link value or read phy for real */
1839 	switch (hw->phy.media_type) {
1840 	case e1000_media_type_copper:
1841 		if (hw->mac.get_link_status) {
1842 			if (hw->mac.type == e1000_pch_spt)
1843 				msec_delay(50);
1844 			/* Do the work to read phy */
1845 			e1000_check_for_link(hw);
1846 			link_check = !hw->mac.get_link_status;
1847 			if (link_check) /* ESB2 fix */
1848 				e1000_cfg_on_link_up(hw);
1849 		} else {
1850 			link_check = true;
1851 		}
1852 		break;
1853 	case e1000_media_type_fiber:
1854 		e1000_check_for_link(hw);
1855 		link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1856 			    E1000_STATUS_LU);
1857 		break;
1858 	case e1000_media_type_internal_serdes:
1859 		e1000_check_for_link(hw);
1860 		link_check = hw->mac.serdes_has_link;
1861 		break;
1862 	/* VF device is type_unknown */
1863 	case e1000_media_type_unknown:
1864 		e1000_check_for_link(hw);
1865 		link_check = !hw->mac.get_link_status;
1866 		/* FALLTHROUGH */
1867 	default:
1868 		break;
1869 	}
1870 
1871 	/* Check for thermal downshift or shutdown */
1872 	if (hw->mac.type == e1000_i350) {
1873 		thstat = E1000_READ_REG(hw, E1000_THSTAT);
1874 		ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1875 	}
1876 
1877 	/* Now check for a transition */
1878 	if (link_check && (sc->link_active == 0)) {
1879 		e1000_get_speed_and_duplex(hw, &sc->link_speed,
1880 		    &sc->link_duplex);
1881 		/* Check if we must disable SPEED_MODE bit on PCI-E */
1882 		if ((sc->link_speed != SPEED_1000) &&
1883 		    ((hw->mac.type == e1000_82571) ||
1884 		    (hw->mac.type == e1000_82572))) {
1885 			int tarc0;
1886 			tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1887 			tarc0 &= ~TARC_SPEED_MODE_BIT;
1888 			E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1889 		}
1890 		if (bootverbose)
1891 			device_printf(dev, "Link is up %d Mbps %s\n",
1892 			    sc->link_speed,
1893 			    ((sc->link_duplex == FULL_DUPLEX) ?
1894 			    "Full Duplex" : "Half Duplex"));
1895 		sc->link_active = 1;
1896 		sc->smartspeed = 0;
1897 		if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1898 		    E1000_CTRL_EXT_LINK_MODE_GMII &&
1899 		    (thstat & E1000_THSTAT_LINK_THROTTLE))
1900 			device_printf(dev, "Link: thermal downshift\n");
1901 		/* Delay Link Up for Phy update */
1902 		if (((hw->mac.type == e1000_i210) ||
1903 		    (hw->mac.type == e1000_i211)) &&
1904 		    (hw->phy.id == I210_I_PHY_ID))
1905 			msec_delay(I210_LINK_DELAY);
1906 		/* Reset if the media type changed. */
1907 		if (hw->dev_spec._82575.media_changed &&
1908 		    hw->mac.type >= igb_mac_min) {
1909 			hw->dev_spec._82575.media_changed = false;
1910 			sc->flags |= IGB_MEDIA_RESET;
1911 			em_reset(ctx);
1912 		}
1913 		/* Only do TSO on gigabit Ethernet for older chips due to errata */
1914 		if (hw->mac.type < igb_mac_min)
1915 			automasked = em_automask_tso(ctx);
1916 
1917 		/* Automasking resets the interface, so don't mark it up yet */
1918 		if (!automasked)
1919 			iflib_link_state_change(ctx, LINK_STATE_UP,
1920 			    IF_Mbps(sc->link_speed));
1921 	} else if (!link_check && (sc->link_active == 1)) {
1922 		sc->link_speed = 0;
1923 		sc->link_duplex = 0;
1924 		sc->link_active = 0;
1925 		iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1926 	}
1927 	em_update_stats_counters(sc);
1928 
1929 	/* Reset LAA into RAR[0] on 82571 */
1930 	if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1931 		e1000_rar_set(hw, hw->mac.addr, 0);
1932 
1933 	if (hw->mac.type < em_mac_min)
1934 		lem_smartspeed(sc);
1935 }
1936 
1937 static void
1938 em_if_watchdog_reset(if_ctx_t ctx)
1939 {
1940 	struct e1000_softc *sc = iflib_get_softc(ctx);
1941 
1942 	/*
1943 	 * Just count the event; iflib(4) will already trigger a
1944 	 * sufficient reset of the controller.
1945 	 */
1946 	sc->watchdog_events++;
1947 }
1948 
1949 /*********************************************************************
1950  *
1951  *  This routine disables all traffic on the adapter by issuing a
1952  *  global reset on the MAC.
1953  *
1954  **********************************************************************/
1955 static void
1956 em_if_stop(if_ctx_t ctx)
1957 {
1958 	struct e1000_softc *sc = iflib_get_softc(ctx);
1959 
1960 	INIT_DEBUGOUT("em_if_stop: begin");
1961 
1962 	/* I219 needs special flushing to avoid hangs */
1963 	if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min)
1964 		em_flush_desc_rings(sc);
1965 
1966 	e1000_reset_hw(&sc->hw);
1967 	if (sc->hw.mac.type >= e1000_82544)
1968 		E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0);
1969 
1970 	e1000_led_off(&sc->hw);
1971 	e1000_cleanup_led(&sc->hw);
1972 }
1973 
1974 /*********************************************************************
1975  *
1976  *  Determine hardware revision.
1977  *
1978  **********************************************************************/
1979 static void
1980 em_identify_hardware(if_ctx_t ctx)
1981 {
1982 	device_t dev = iflib_get_dev(ctx);
1983 	struct e1000_softc *sc = iflib_get_softc(ctx);
1984 
1985 	/* Make sure our PCI config space has the necessary stuff set */
1986 	sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1987 
1988 	/* Save off the information about this board */
1989 	sc->hw.vendor_id = pci_get_vendor(dev);
1990 	sc->hw.device_id = pci_get_device(dev);
1991 	sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1992 	sc->hw.subsystem_vendor_id =
1993 	    pci_read_config(dev, PCIR_SUBVEND_0, 2);
1994 	sc->hw.subsystem_device_id =
1995 	    pci_read_config(dev, PCIR_SUBDEV_0, 2);
1996 
1997 	/* Do Shared Code Init and Setup */
1998 	if (e1000_set_mac_type(&sc->hw)) {
1999 		device_printf(dev, "Setup init failure\n");
2000 		return;
2001 	}
2002 
2003 	/* Are we a VF device? */
2004 	if ((sc->hw.mac.type == e1000_vfadapt) ||
2005 	    (sc->hw.mac.type == e1000_vfadapt_i350))
2006 		sc->vf_ifp = 1;
2007 	else
2008 		sc->vf_ifp = 0;
2009 }
2010 
2011 static int
2012 em_allocate_pci_resources(if_ctx_t ctx)
2013 {
2014 	struct e1000_softc *sc = iflib_get_softc(ctx);
2015 	device_t dev = iflib_get_dev(ctx);
2016 	int rid, val;
2017 
2018 	rid = PCIR_BAR(0);
2019 	sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2020 	    &rid, RF_ACTIVE);
2021 	if (sc->memory == NULL) {
2022 		device_printf(dev, "Unable to allocate bus resource: memory\n");
2023 		return (ENXIO);
2024 	}
2025 	sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
2026 	sc->osdep.mem_bus_space_handle =
2027 	    rman_get_bushandle(sc->memory);
2028 	sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
2029 
2030 	/* Only older adapters use IO mapping */
2031 	if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) {
2032 		/* Figure our where our IO BAR is ? */
2033 		for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
2034 			val = pci_read_config(dev, rid, 4);
2035 			if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
2036 				break;
2037 			}
2038 			rid += 4;
2039 			/* check for 64bit BAR */
2040 			if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2041 				rid += 4;
2042 		}
2043 		if (rid >= PCIR_CIS) {
2044 			device_printf(dev, "Unable to locate IO BAR\n");
2045 			return (ENXIO);
2046 		}
2047 		sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2048 		    &rid, RF_ACTIVE);
2049 		if (sc->ioport == NULL) {
2050 			device_printf(dev, "Unable to allocate bus resource: "
2051 			    "ioport\n");
2052 			return (ENXIO);
2053 		}
2054 		sc->hw.io_base = 0;
2055 		sc->osdep.io_bus_space_tag =
2056 		    rman_get_bustag(sc->ioport);
2057 		sc->osdep.io_bus_space_handle =
2058 		    rman_get_bushandle(sc->ioport);
2059 	}
2060 
2061 	sc->hw.back = &sc->osdep;
2062 
2063 	return (0);
2064 }
2065 
2066 /*********************************************************************
2067  *
2068  *  Set up the MSI-X Interrupt handlers
2069  *
2070  **********************************************************************/
2071 static int
2072 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2073 {
2074 	struct e1000_softc *sc = iflib_get_softc(ctx);
2075 	struct em_rx_queue *rx_que = sc->rx_queues;
2076 	struct em_tx_queue *tx_que = sc->tx_queues;
2077 	int error, rid, i, vector = 0, rx_vectors;
2078 	char buf[16];
2079 
2080 	/* First set up ring resources */
2081 	for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
2082 		rid = vector + 1;
2083 		snprintf(buf, sizeof(buf), "rxq%d", i);
2084 		error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2085 		if (error) {
2086 			device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2087 			sc->rx_num_queues = i + 1;
2088 			goto fail;
2089 		}
2090 
2091 		rx_que->msix =  vector;
2092 
2093 		/*
2094 		 * Set the bit to enable interrupt
2095 		 * in E1000_IMS -- bits 20 and 21
2096 		 * are for RX0 and RX1, note this has
2097 		 * NOTHING to do with the MSI-X vector
2098 		 */
2099 		if (sc->hw.mac.type == e1000_82574) {
2100 			rx_que->eims = 1 << (20 + i);
2101 			sc->ims |= rx_que->eims;
2102 			sc->ivars |= (8 | rx_que->msix) << (i * 4);
2103 		} else if (sc->hw.mac.type == e1000_82575)
2104 			rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2105 		else
2106 			rx_que->eims = 1 << vector;
2107 	}
2108 	rx_vectors = vector;
2109 
2110 	vector = 0;
2111 	for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
2112 		snprintf(buf, sizeof(buf), "txq%d", i);
2113 		tx_que = &sc->tx_queues[i];
2114 		iflib_softirq_alloc_generic(ctx,
2115 		    &sc->rx_queues[i % sc->rx_num_queues].que_irq,
2116 		    IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2117 
2118 		tx_que->msix = (vector % sc->rx_num_queues);
2119 
2120 		/*
2121 		 * Set the bit to enable interrupt
2122 		 * in E1000_IMS -- bits 22 and 23
2123 		 * are for TX0 and TX1, note this has
2124 		 * NOTHING to do with the MSI-X vector
2125 		 */
2126 		if (sc->hw.mac.type == e1000_82574) {
2127 			tx_que->eims = 1 << (22 + i);
2128 			sc->ims |= tx_que->eims;
2129 			sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2130 		} else if (sc->hw.mac.type == e1000_82575) {
2131 			tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2132 		} else {
2133 			tx_que->eims = 1 << i;
2134 		}
2135 	}
2136 
2137 	/* Link interrupt */
2138 	rid = rx_vectors + 1;
2139 	error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq");
2140 
2141 	if (error) {
2142 		device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2143 		goto fail;
2144 	}
2145 	sc->linkvec = rx_vectors;
2146 	if (sc->hw.mac.type < igb_mac_min) {
2147 		sc->ivars |=  (8 | rx_vectors) << 16;
2148 		sc->ivars |= 0x80000000;
2149 		/* Enable the "Other" interrupt type for link status change */
2150 		sc->ims |= E1000_IMS_OTHER;
2151 	}
2152 
2153 	return (0);
2154 fail:
2155 	iflib_irq_free(ctx, &sc->irq);
2156 	rx_que = sc->rx_queues;
2157 	for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
2158 		iflib_irq_free(ctx, &rx_que->que_irq);
2159 	return (error);
2160 }
2161 
2162 static void
2163 igb_configure_queues(struct e1000_softc *sc)
2164 {
2165 	struct e1000_hw *hw = &sc->hw;
2166 	struct em_rx_queue *rx_que;
2167 	struct em_tx_queue *tx_que;
2168 	u32 tmp, ivar = 0, newitr = 0;
2169 
2170 	/* First turn on RSS capability */
2171 	if (hw->mac.type != e1000_82575)
2172 		E1000_WRITE_REG(hw, E1000_GPIE,
2173 		    E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2174 		    E1000_GPIE_PBA | E1000_GPIE_NSICR);
2175 
2176 	/* Turn on MSI-X */
2177 	switch (hw->mac.type) {
2178 	case e1000_82580:
2179 	case e1000_i350:
2180 	case e1000_i354:
2181 	case e1000_i210:
2182 	case e1000_i211:
2183 	case e1000_vfadapt:
2184 	case e1000_vfadapt_i350:
2185 		/* RX entries */
2186 		for (int i = 0; i < sc->rx_num_queues; i++) {
2187 			u32 index = i >> 1;
2188 			ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2189 			rx_que = &sc->rx_queues[i];
2190 			if (i & 1) {
2191 				ivar &= 0xFF00FFFF;
2192 				ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2193 			} else {
2194 				ivar &= 0xFFFFFF00;
2195 				ivar |= rx_que->msix | E1000_IVAR_VALID;
2196 			}
2197 			E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2198 		}
2199 		/* TX entries */
2200 		for (int i = 0; i < sc->tx_num_queues; i++) {
2201 			u32 index = i >> 1;
2202 			ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2203 			tx_que = &sc->tx_queues[i];
2204 			if (i & 1) {
2205 				ivar &= 0x00FFFFFF;
2206 				ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2207 			} else {
2208 				ivar &= 0xFFFF00FF;
2209 				ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2210 			}
2211 			E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2212 			sc->que_mask |= tx_que->eims;
2213 		}
2214 
2215 		/* And for the link interrupt */
2216 		ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2217 		sc->link_mask = 1 << sc->linkvec;
2218 		E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2219 		break;
2220 	case e1000_82576:
2221 		/* RX entries */
2222 		for (int i = 0; i < sc->rx_num_queues; i++) {
2223 			u32 index = i & 0x7; /* Each IVAR has two entries */
2224 			ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2225 			rx_que = &sc->rx_queues[i];
2226 			if (i < 8) {
2227 				ivar &= 0xFFFFFF00;
2228 				ivar |= rx_que->msix | E1000_IVAR_VALID;
2229 			} else {
2230 				ivar &= 0xFF00FFFF;
2231 				ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2232 			}
2233 			E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2234 			sc->que_mask |= rx_que->eims;
2235 		}
2236 		/* TX entries */
2237 		for (int i = 0; i < sc->tx_num_queues; i++) {
2238 			u32 index = i & 0x7; /* Each IVAR has two entries */
2239 			ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2240 			tx_que = &sc->tx_queues[i];
2241 			if (i < 8) {
2242 				ivar &= 0xFFFF00FF;
2243 				ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2244 			} else {
2245 				ivar &= 0x00FFFFFF;
2246 				ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2247 			}
2248 			E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2249 			sc->que_mask |= tx_que->eims;
2250 		}
2251 
2252 		/* And for the link interrupt */
2253 		ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2254 		sc->link_mask = 1 << sc->linkvec;
2255 		E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2256 		break;
2257 
2258 	case e1000_82575:
2259 		/* enable MSI-X support*/
2260 		tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2261 		tmp |= E1000_CTRL_EXT_PBA_CLR;
2262 		/* Auto-Mask interrupts upon ICR read. */
2263 		tmp |= E1000_CTRL_EXT_EIAME;
2264 		tmp |= E1000_CTRL_EXT_IRCA;
2265 		E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2266 
2267 		/* Queues */
2268 		for (int i = 0; i < sc->rx_num_queues; i++) {
2269 			rx_que = &sc->rx_queues[i];
2270 			tmp = E1000_EICR_RX_QUEUE0 << i;
2271 			tmp |= E1000_EICR_TX_QUEUE0 << i;
2272 			rx_que->eims = tmp;
2273 			E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2274 			    i, rx_que->eims);
2275 			sc->que_mask |= rx_que->eims;
2276 		}
2277 
2278 		/* Link */
2279 		E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec),
2280 		    E1000_EIMS_OTHER);
2281 		sc->link_mask |= E1000_EIMS_OTHER;
2282 	default:
2283 		break;
2284 	}
2285 
2286 	/* Set the starting interrupt rate */
2287 	if (em_max_interrupt_rate > 0)
2288 		newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2289 
2290 	if (hw->mac.type == e1000_82575)
2291 		newitr |= newitr << 16;
2292 	else
2293 		newitr |= E1000_EITR_CNT_IGNR;
2294 
2295 	for (int i = 0; i < sc->rx_num_queues; i++) {
2296 		rx_que = &sc->rx_queues[i];
2297 		E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2298 	}
2299 
2300 	return;
2301 }
2302 
2303 static void
2304 em_free_pci_resources(if_ctx_t ctx)
2305 {
2306 	struct e1000_softc *sc = iflib_get_softc(ctx);
2307 	struct em_rx_queue *que = sc->rx_queues;
2308 	device_t dev = iflib_get_dev(ctx);
2309 
2310 	/* Release all MSI-X queue resources */
2311 	if (sc->intr_type == IFLIB_INTR_MSIX)
2312 		iflib_irq_free(ctx, &sc->irq);
2313 
2314 	if (que != NULL) {
2315 		for (int i = 0; i < sc->rx_num_queues; i++, que++) {
2316 			iflib_irq_free(ctx, &que->que_irq);
2317 		}
2318 	}
2319 
2320 	if (sc->memory != NULL) {
2321 		bus_release_resource(dev, SYS_RES_MEMORY,
2322 		    rman_get_rid(sc->memory), sc->memory);
2323 		sc->memory = NULL;
2324 	}
2325 
2326 	if (sc->flash != NULL) {
2327 		bus_release_resource(dev, SYS_RES_MEMORY,
2328 		    rman_get_rid(sc->flash), sc->flash);
2329 		sc->flash = NULL;
2330 	}
2331 
2332 	if (sc->ioport != NULL) {
2333 		bus_release_resource(dev, SYS_RES_IOPORT,
2334 		    rman_get_rid(sc->ioport), sc->ioport);
2335 		sc->ioport = NULL;
2336 	}
2337 }
2338 
2339 /* Set up MSI or MSI-X */
2340 static int
2341 em_setup_msix(if_ctx_t ctx)
2342 {
2343 	struct e1000_softc *sc = iflib_get_softc(ctx);
2344 
2345 	if (sc->hw.mac.type == e1000_82574) {
2346 		em_enable_vectors_82574(ctx);
2347 	}
2348 	return (0);
2349 }
2350 
2351 /*********************************************************************
2352  *
2353  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2354  *
2355  **********************************************************************/
2356 static void
2357 lem_smartspeed(struct e1000_softc *sc)
2358 {
2359 	u16 phy_tmp;
2360 
2361 	if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) ||
2362 	    sc->hw.mac.autoneg == 0 ||
2363 	    (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2364 		return;
2365 
2366 	if (sc->smartspeed == 0) {
2367 		/* If Master/Slave config fault is asserted twice,
2368 		 * we assume back-to-back */
2369 		e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2370 		if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2371 			return;
2372 		e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2373 		if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2374 			e1000_read_phy_reg(&sc->hw,
2375 			    PHY_1000T_CTRL, &phy_tmp);
2376 			if(phy_tmp & CR_1000T_MS_ENABLE) {
2377 				phy_tmp &= ~CR_1000T_MS_ENABLE;
2378 				e1000_write_phy_reg(&sc->hw,
2379 				    PHY_1000T_CTRL, phy_tmp);
2380 				sc->smartspeed++;
2381 				if(sc->hw.mac.autoneg &&
2382 				   !e1000_copper_link_autoneg(&sc->hw) &&
2383 				   !e1000_read_phy_reg(&sc->hw,
2384 				    PHY_CONTROL, &phy_tmp)) {
2385 					phy_tmp |= (MII_CR_AUTO_NEG_EN |
2386 						    MII_CR_RESTART_AUTO_NEG);
2387 					e1000_write_phy_reg(&sc->hw,
2388 					    PHY_CONTROL, phy_tmp);
2389 				}
2390 			}
2391 		}
2392 		return;
2393 	} else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2394 		/* If still no link, perhaps using 2/3 pair cable */
2395 		e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2396 		phy_tmp |= CR_1000T_MS_ENABLE;
2397 		e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2398 		if(sc->hw.mac.autoneg &&
2399 		   !e1000_copper_link_autoneg(&sc->hw) &&
2400 		   !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2401 			phy_tmp |= (MII_CR_AUTO_NEG_EN |
2402 				    MII_CR_RESTART_AUTO_NEG);
2403 			e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2404 		}
2405 	}
2406 	/* Restart process after EM_SMARTSPEED_MAX iterations */
2407 	if(sc->smartspeed++ == EM_SMARTSPEED_MAX)
2408 		sc->smartspeed = 0;
2409 }
2410 
2411 /*********************************************************************
2412  *
2413  *  Initialize the DMA Coalescing feature
2414  *
2415  **********************************************************************/
2416 static void
2417 igb_init_dmac(struct e1000_softc *sc, u32 pba)
2418 {
2419 	device_t	dev = sc->dev;
2420 	struct e1000_hw *hw = &sc->hw;
2421 	u32 		dmac, reg = ~E1000_DMACR_DMAC_EN;
2422 	u16		hwm;
2423 	u16		max_frame_size;
2424 
2425 	if (hw->mac.type == e1000_i211)
2426 		return;
2427 
2428 	max_frame_size = sc->shared->isc_max_frame_size;
2429 	if (hw->mac.type > e1000_82580) {
2430 
2431 		if (sc->dmac == 0) { /* Disabling it */
2432 			E1000_WRITE_REG(hw, E1000_DMACR, reg);
2433 			return;
2434 		} else
2435 			device_printf(dev, "DMA Coalescing enabled\n");
2436 
2437 		/* Set starting threshold */
2438 		E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2439 
2440 		hwm = 64 * pba - max_frame_size / 16;
2441 		if (hwm < 64 * (pba - 6))
2442 			hwm = 64 * (pba - 6);
2443 		reg = E1000_READ_REG(hw, E1000_FCRTC);
2444 		reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2445 		reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2446 		    & E1000_FCRTC_RTH_COAL_MASK);
2447 		E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2448 
2449 
2450 		dmac = pba - max_frame_size / 512;
2451 		if (dmac < pba - 10)
2452 			dmac = pba - 10;
2453 		reg = E1000_READ_REG(hw, E1000_DMACR);
2454 		reg &= ~E1000_DMACR_DMACTHR_MASK;
2455 		reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2456 		    & E1000_DMACR_DMACTHR_MASK);
2457 
2458 		/* transition to L0x or L1 if available..*/
2459 		reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2460 
2461 		/* Check if status is 2.5Gb backplane connection
2462 		* before configuration of watchdog timer, which is
2463 		* in msec values in 12.8usec intervals
2464 		* watchdog timer= msec values in 32usec intervals
2465 		* for non 2.5Gb connection
2466 		*/
2467 		if (hw->mac.type == e1000_i354) {
2468 			int status = E1000_READ_REG(hw, E1000_STATUS);
2469 			if ((status & E1000_STATUS_2P5_SKU) &&
2470 			    (!(status & E1000_STATUS_2P5_SKU_OVER)))
2471 				reg |= ((sc->dmac * 5) >> 6);
2472 			else
2473 				reg |= (sc->dmac >> 5);
2474 		} else {
2475 			reg |= (sc->dmac >> 5);
2476 		}
2477 
2478 		E1000_WRITE_REG(hw, E1000_DMACR, reg);
2479 
2480 		E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2481 
2482 		/* Set the interval before transition */
2483 		reg = E1000_READ_REG(hw, E1000_DMCTLX);
2484 		if (hw->mac.type == e1000_i350)
2485 			reg |= IGB_DMCTLX_DCFLUSH_DIS;
2486 		/*
2487 		** in 2.5Gb connection, TTLX unit is 0.4 usec
2488 		** which is 0x4*2 = 0xA. But delay is still 4 usec
2489 		*/
2490 		if (hw->mac.type == e1000_i354) {
2491 			int status = E1000_READ_REG(hw, E1000_STATUS);
2492 			if ((status & E1000_STATUS_2P5_SKU) &&
2493 			    (!(status & E1000_STATUS_2P5_SKU_OVER)))
2494 				reg |= 0xA;
2495 			else
2496 				reg |= 0x4;
2497 		} else {
2498 			reg |= 0x4;
2499 		}
2500 
2501 		E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2502 
2503 		/* free space in tx packet buffer to wake from DMA coal */
2504 		E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2505 		    (2 * max_frame_size)) >> 6);
2506 
2507 		/* make low power state decision controlled by DMA coal */
2508 		reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2509 		reg &= ~E1000_PCIEMISC_LX_DECISION;
2510 		E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2511 
2512 	} else if (hw->mac.type == e1000_82580) {
2513 		u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2514 		E1000_WRITE_REG(hw, E1000_PCIEMISC,
2515 		    reg & ~E1000_PCIEMISC_LX_DECISION);
2516 		E1000_WRITE_REG(hw, E1000_DMACR, 0);
2517 	}
2518 }
2519 /*********************************************************************
2520  * The 3 following flush routines are used as a workaround in the
2521  * I219 client parts and only for them.
2522  *
2523  * em_flush_tx_ring - remove all descriptors from the tx_ring
2524  *
2525  * We want to clear all pending descriptors from the TX ring.
2526  * zeroing happens when the HW reads the regs. We assign the ring itself as
2527  * the data of the next descriptor. We don't care about the data we are about
2528  * to reset the HW.
2529  **********************************************************************/
2530 static void
2531 em_flush_tx_ring(struct e1000_softc *sc)
2532 {
2533 	struct e1000_hw		*hw = &sc->hw;
2534 	struct tx_ring		*txr = &sc->tx_queues->txr;
2535 	struct e1000_tx_desc	*txd;
2536 	u32			tctl, txd_lower = E1000_TXD_CMD_IFCS;
2537 	u16			size = 512;
2538 
2539 	tctl = E1000_READ_REG(hw, E1000_TCTL);
2540 	E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
2541 
2542 	txd = &txr->tx_base[txr->tx_cidx_processed];
2543 
2544 	/* Just use the ring as a dummy buffer addr */
2545 	txd->buffer_addr = txr->tx_paddr;
2546 	txd->lower.data = htole32(txd_lower | size);
2547 	txd->upper.data = 0;
2548 
2549 	/* flush descriptors to memory before notifying the HW */
2550 	wmb();
2551 
2552 	E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed);
2553 	mb();
2554 	usec_delay(250);
2555 }
2556 
2557 /*********************************************************************
2558  * em_flush_rx_ring - remove all descriptors from the rx_ring
2559  *
2560  * Mark all descriptors in the RX ring as consumed and disable the rx ring
2561  **********************************************************************/
2562 static void
2563 em_flush_rx_ring(struct e1000_softc *sc)
2564 {
2565 	struct e1000_hw	*hw = &sc->hw;
2566 	u32		rctl, rxdctl;
2567 
2568 	rctl = E1000_READ_REG(hw, E1000_RCTL);
2569 	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2570 	E1000_WRITE_FLUSH(hw);
2571 	usec_delay(150);
2572 
2573 	rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
2574 	/* zero the lower 14 bits (prefetch and host thresholds) */
2575 	rxdctl &= 0xffffc000;
2576 	/*
2577 	 * update thresholds: prefetch threshold to 31, host threshold to 1
2578 	 * and make sure the granularity is "descriptors" and not "cache lines"
2579 	 */
2580 	rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
2581 	E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);
2582 
2583 	/* momentarily enable the RX ring for the changes to take effect */
2584 	E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
2585 	E1000_WRITE_FLUSH(hw);
2586 	usec_delay(150);
2587 	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2588 }
2589 
2590 /*********************************************************************
2591  * em_flush_desc_rings - remove all descriptors from the descriptor rings
2592  *
2593  * In I219, the descriptor rings must be emptied before resetting the HW
2594  * or before changing the device state to D3 during runtime (runtime PM).
2595  *
2596  * Failure to do this will cause the HW to enter a unit hang state which can
2597  * only be released by PCI reset on the device
2598  *
2599  **********************************************************************/
2600 static void
2601 em_flush_desc_rings(struct e1000_softc *sc)
2602 {
2603 	struct e1000_hw	*hw = &sc->hw;
2604 	device_t dev = sc->dev;
2605 	u16		hang_state;
2606 	u32		fext_nvm11, tdlen;
2607 
2608 	/* First, disable MULR fix in FEXTNVM11 */
2609 	fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
2610 	fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
2611 	E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11);
2612 
2613 	/* do nothing if we're not in faulty state, or if the queue is empty */
2614 	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
2615 	hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
2616 	if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
2617 		return;
2618 	em_flush_tx_ring(sc);
2619 
2620 	/* recheck, maybe the fault is caused by the rx ring */
2621 	hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
2622 	if (hang_state & FLUSH_DESC_REQUIRED)
2623 		em_flush_rx_ring(sc);
2624 }
2625 
2626 
2627 /*********************************************************************
2628  *
2629  *  Initialize the hardware to a configuration as specified by the
2630  *  sc structure.
2631  *
2632  **********************************************************************/
2633 static void
2634 em_reset(if_ctx_t ctx)
2635 {
2636 	device_t dev = iflib_get_dev(ctx);
2637 	struct e1000_softc *sc = iflib_get_softc(ctx);
2638 	if_t ifp = iflib_get_ifp(ctx);
2639 	struct e1000_hw *hw = &sc->hw;
2640 	u32 rx_buffer_size;
2641 	u32 pba;
2642 
2643 	INIT_DEBUGOUT("em_reset: begin");
2644 	/* Let the firmware know the OS is in control */
2645 	em_get_hw_control(sc);
2646 
2647 	/* Set up smart power down as default off on newer adapters. */
2648 	if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2649 	    hw->mac.type == e1000_82572)) {
2650 		u16 phy_tmp = 0;
2651 
2652 		/* Speed up time to link by disabling smart power down. */
2653 		e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2654 		phy_tmp &= ~IGP02E1000_PM_SPD;
2655 		e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2656 	}
2657 
2658 	/*
2659 	 * Packet Buffer Allocation (PBA)
2660 	 * Writing PBA sets the receive portion of the buffer
2661 	 * the remainder is used for the transmit buffer.
2662 	 */
2663 	switch (hw->mac.type) {
2664 	/* 82547: Total Packet Buffer is 40K */
2665 	case e1000_82547:
2666 	case e1000_82547_rev_2:
2667 		if (hw->mac.max_frame_size > 8192)
2668 			pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2669 		else
2670 			pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2671 		break;
2672 	/* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2673 	case e1000_82571:
2674 	case e1000_82572:
2675 	case e1000_80003es2lan:
2676 			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2677 		break;
2678 	/* 82573: Total Packet Buffer is 32K */
2679 	case e1000_82573:
2680 			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2681 		break;
2682 	case e1000_82574:
2683 	case e1000_82583:
2684 			pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2685 		break;
2686 	case e1000_ich8lan:
2687 		pba = E1000_PBA_8K;
2688 		break;
2689 	case e1000_ich9lan:
2690 	case e1000_ich10lan:
2691 		/* Boost Receive side for jumbo frames */
2692 		if (hw->mac.max_frame_size > 4096)
2693 			pba = E1000_PBA_14K;
2694 		else
2695 			pba = E1000_PBA_10K;
2696 		break;
2697 	case e1000_pchlan:
2698 	case e1000_pch2lan:
2699 	case e1000_pch_lpt:
2700 	case e1000_pch_spt:
2701 	case e1000_pch_cnp:
2702 	case e1000_pch_tgp:
2703 	case e1000_pch_adp:
2704 	case e1000_pch_mtp:
2705 	case e1000_pch_ptp:
2706 		pba = E1000_PBA_26K;
2707 		break;
2708 	case e1000_82575:
2709 		pba = E1000_PBA_32K;
2710 		break;
2711 	case e1000_82576:
2712 	case e1000_vfadapt:
2713 		pba = E1000_READ_REG(hw, E1000_RXPBS);
2714 		pba &= E1000_RXPBS_SIZE_MASK_82576;
2715 		break;
2716 	case e1000_82580:
2717 	case e1000_i350:
2718 	case e1000_i354:
2719 	case e1000_vfadapt_i350:
2720 		pba = E1000_READ_REG(hw, E1000_RXPBS);
2721 		pba = e1000_rxpbs_adjust_82580(pba);
2722 		break;
2723 	case e1000_i210:
2724 	case e1000_i211:
2725 		pba = E1000_PBA_34K;
2726 		break;
2727 	default:
2728 		/* Remaining devices assumed to have a Packet Buffer of 64K. */
2729 		if (hw->mac.max_frame_size > 8192)
2730 			pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2731 		else
2732 			pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2733 	}
2734 
2735 	/* Special needs in case of Jumbo frames */
2736 	if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) {
2737 		u32 tx_space, min_tx, min_rx;
2738 		pba = E1000_READ_REG(hw, E1000_PBA);
2739 		tx_space = pba >> 16;
2740 		pba &= 0xffff;
2741 		min_tx = (hw->mac.max_frame_size +
2742 		    sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2743 		min_tx = roundup2(min_tx, 1024);
2744 		min_tx >>= 10;
2745 		min_rx = hw->mac.max_frame_size;
2746 		min_rx = roundup2(min_rx, 1024);
2747 		min_rx >>= 10;
2748 		if (tx_space < min_tx &&
2749 		    ((min_tx - tx_space) < pba)) {
2750 			pba = pba - (min_tx - tx_space);
2751 			/*
2752 			 * if short on rx space, rx wins
2753 			 * and must trump tx adjustment
2754 			 */
2755 			if (pba < min_rx)
2756 				pba = min_rx;
2757 		}
2758 		E1000_WRITE_REG(hw, E1000_PBA, pba);
2759 	}
2760 
2761 	if (hw->mac.type < igb_mac_min)
2762 		E1000_WRITE_REG(hw, E1000_PBA, pba);
2763 
2764 	INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2765 
2766 	/*
2767 	 * These parameters control the automatic generation (Tx) and
2768 	 * response (Rx) to Ethernet PAUSE frames.
2769 	 * - High water mark should allow for at least two frames to be
2770 	 *   received after sending an XOFF.
2771 	 * - Low water mark works best when it is very near the high water mark.
2772 	 *   This allows the receiver to restart by sending XON when it has
2773 	 *   drained a bit. Here we use an arbitrary value of 1500 which will
2774 	 *   restart after one full frame is pulled from the buffer. There
2775 	 *   could be several smaller frames in the buffer and if so they will
2776 	 *   not trigger the XON until their total number reduces the buffer
2777 	 *   by 1500.
2778 	 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2779 	 */
2780 	rx_buffer_size = (pba & 0xffff) << 10;
2781 	hw->fc.high_water = rx_buffer_size -
2782 	    roundup2(hw->mac.max_frame_size, 1024);
2783 	hw->fc.low_water = hw->fc.high_water - 1500;
2784 
2785 	if (sc->fc) /* locally set flow control value? */
2786 		hw->fc.requested_mode = sc->fc;
2787 	else
2788 		hw->fc.requested_mode = e1000_fc_full;
2789 
2790 	if (hw->mac.type == e1000_80003es2lan)
2791 		hw->fc.pause_time = 0xFFFF;
2792 	else
2793 		hw->fc.pause_time = EM_FC_PAUSE_TIME;
2794 
2795 	hw->fc.send_xon = true;
2796 
2797 	/* Device specific overrides/settings */
2798 	switch (hw->mac.type) {
2799 	case e1000_pchlan:
2800 		/* Workaround: no TX flow ctrl for PCH */
2801 		hw->fc.requested_mode = e1000_fc_rx_pause;
2802 		hw->fc.pause_time = 0xFFFF; /* override */
2803 		if (if_getmtu(ifp) > ETHERMTU) {
2804 			hw->fc.high_water = 0x3500;
2805 			hw->fc.low_water = 0x1500;
2806 		} else {
2807 			hw->fc.high_water = 0x5000;
2808 			hw->fc.low_water = 0x3000;
2809 		}
2810 		hw->fc.refresh_time = 0x1000;
2811 		break;
2812 	case e1000_pch2lan:
2813 	case e1000_pch_lpt:
2814 	case e1000_pch_spt:
2815 	case e1000_pch_cnp:
2816 	case e1000_pch_tgp:
2817 	case e1000_pch_adp:
2818 	case e1000_pch_mtp:
2819 	case e1000_pch_ptp:
2820 		hw->fc.high_water = 0x5C20;
2821 		hw->fc.low_water = 0x5048;
2822 		hw->fc.pause_time = 0x0650;
2823 		hw->fc.refresh_time = 0x0400;
2824 		/* Jumbos need adjusted PBA */
2825 		if (if_getmtu(ifp) > ETHERMTU)
2826 			E1000_WRITE_REG(hw, E1000_PBA, 12);
2827 		else
2828 			E1000_WRITE_REG(hw, E1000_PBA, 26);
2829 		break;
2830 	case e1000_82575:
2831 	case e1000_82576:
2832 		/* 8-byte granularity */
2833 		hw->fc.low_water = hw->fc.high_water - 8;
2834 		break;
2835 	case e1000_82580:
2836 	case e1000_i350:
2837 	case e1000_i354:
2838 	case e1000_i210:
2839 	case e1000_i211:
2840 	case e1000_vfadapt:
2841 	case e1000_vfadapt_i350:
2842 		/* 16-byte granularity */
2843 		hw->fc.low_water = hw->fc.high_water - 16;
2844 		break;
2845 	case e1000_ich9lan:
2846 	case e1000_ich10lan:
2847 		if (if_getmtu(ifp) > ETHERMTU) {
2848 			hw->fc.high_water = 0x2800;
2849 			hw->fc.low_water = hw->fc.high_water - 8;
2850 			break;
2851 		}
2852 		/* FALLTHROUGH */
2853 	default:
2854 		if (hw->mac.type == e1000_80003es2lan)
2855 			hw->fc.pause_time = 0xFFFF;
2856 		break;
2857 	}
2858 
2859 	/* I219 needs some special flushing to avoid hangs */
2860 	if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min)
2861 		em_flush_desc_rings(sc);
2862 
2863 	/* Issue a global reset */
2864 	e1000_reset_hw(hw);
2865 	if (hw->mac.type >= igb_mac_min) {
2866 		E1000_WRITE_REG(hw, E1000_WUC, 0);
2867 	} else {
2868 		E1000_WRITE_REG(hw, E1000_WUFC, 0);
2869 		em_disable_aspm(sc);
2870 	}
2871 	if (sc->flags & IGB_MEDIA_RESET) {
2872 		e1000_setup_init_funcs(hw, true);
2873 		e1000_get_bus_info(hw);
2874 		sc->flags &= ~IGB_MEDIA_RESET;
2875 	}
2876 	/* and a re-init */
2877 	if (e1000_init_hw(hw) < 0) {
2878 		device_printf(dev, "Hardware Initialization Failed\n");
2879 		return;
2880 	}
2881 	if (hw->mac.type >= igb_mac_min)
2882 		igb_init_dmac(sc, pba);
2883 
2884 	E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2885 	e1000_get_phy_info(hw);
2886 	e1000_check_for_link(hw);
2887 }
2888 
2889 /*
2890  * Initialise the RSS mapping for NICs that support multiple transmit/
2891  * receive rings.
2892  */
2893 
2894 #define RSSKEYLEN 10
2895 static void
2896 em_initialize_rss_mapping(struct e1000_softc *sc)
2897 {
2898 	uint8_t  rss_key[4 * RSSKEYLEN];
2899 	uint32_t reta = 0;
2900 	struct e1000_hw	*hw = &sc->hw;
2901 	int i;
2902 
2903 	/*
2904 	 * Configure RSS key
2905 	 */
2906 	arc4rand(rss_key, sizeof(rss_key), 0);
2907 	for (i = 0; i < RSSKEYLEN; ++i) {
2908 		uint32_t rssrk = 0;
2909 
2910 		rssrk = EM_RSSRK_VAL(rss_key, i);
2911 		E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2912 	}
2913 
2914 	/*
2915 	 * Configure RSS redirect table in following fashion:
2916 	 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2917 	 */
2918 	for (i = 0; i < sizeof(reta); ++i) {
2919 		uint32_t q;
2920 
2921 		q = (i % sc->rx_num_queues) << 7;
2922 		reta |= q << (8 * i);
2923 	}
2924 
2925 	for (i = 0; i < 32; ++i)
2926 		E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2927 
2928 	E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2929 			E1000_MRQC_RSS_FIELD_IPV4_TCP |
2930 			E1000_MRQC_RSS_FIELD_IPV4 |
2931 			E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2932 			E1000_MRQC_RSS_FIELD_IPV6_EX |
2933 			E1000_MRQC_RSS_FIELD_IPV6);
2934 }
2935 
2936 static void
2937 igb_initialize_rss_mapping(struct e1000_softc *sc)
2938 {
2939 	struct e1000_hw *hw = &sc->hw;
2940 	int i;
2941 	int queue_id;
2942 	u32 reta;
2943 	u32 rss_key[10], mrqc, shift = 0;
2944 
2945 	/* XXX? */
2946 	if (hw->mac.type == e1000_82575)
2947 		shift = 6;
2948 
2949 	/*
2950 	 * The redirection table controls which destination
2951 	 * queue each bucket redirects traffic to.
2952 	 * Each DWORD represents four queues, with the LSB
2953 	 * being the first queue in the DWORD.
2954 	 *
2955 	 * This just allocates buckets to queues using round-robin
2956 	 * allocation.
2957 	 *
2958 	 * NOTE: It Just Happens to line up with the default
2959 	 * RSS allocation method.
2960 	 */
2961 
2962 	/* Warning FM follows */
2963 	reta = 0;
2964 	for (i = 0; i < 128; i++) {
2965 #ifdef RSS
2966 		queue_id = rss_get_indirection_to_bucket(i);
2967 		/*
2968 		 * If we have more queues than buckets, we'll
2969 		 * end up mapping buckets to a subset of the
2970 		 * queues.
2971 		 *
2972 		 * If we have more buckets than queues, we'll
2973 		 * end up instead assigning multiple buckets
2974 		 * to queues.
2975 		 *
2976 		 * Both are suboptimal, but we need to handle
2977 		 * the case so we don't go out of bounds
2978 		 * indexing arrays and such.
2979 		 */
2980 		queue_id = queue_id % sc->rx_num_queues;
2981 #else
2982 		queue_id = (i % sc->rx_num_queues);
2983 #endif
2984 		/* Adjust if required */
2985 		queue_id = queue_id << shift;
2986 
2987 		/*
2988 		 * The low 8 bits are for hash value (n+0);
2989 		 * The next 8 bits are for hash value (n+1), etc.
2990 		 */
2991 		reta = reta >> 8;
2992 		reta = reta | ( ((uint32_t) queue_id) << 24);
2993 		if ((i & 3) == 3) {
2994 			E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2995 			reta = 0;
2996 		}
2997 	}
2998 
2999 	/* Now fill in hash table */
3000 
3001 	/*
3002 	 * MRQC: Multiple Receive Queues Command
3003 	 * Set queuing to RSS control, number depends on the device.
3004 	 */
3005 	mrqc = E1000_MRQC_ENABLE_RSS_MQ;
3006 
3007 #ifdef RSS
3008 	/* XXX ew typecasting */
3009 	rss_getkey((uint8_t *) &rss_key);
3010 #else
3011 	arc4rand(&rss_key, sizeof(rss_key), 0);
3012 #endif
3013 	for (i = 0; i < 10; i++)
3014 		E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
3015 
3016 	/*
3017 	 * Configure the RSS fields to hash upon.
3018 	 */
3019 	mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
3020 	    E1000_MRQC_RSS_FIELD_IPV4_TCP);
3021 	mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
3022 	    E1000_MRQC_RSS_FIELD_IPV6_TCP);
3023 	mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
3024 	    E1000_MRQC_RSS_FIELD_IPV6_UDP);
3025 	mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
3026 	    E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3027 
3028 	E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
3029 }
3030 
3031 /*********************************************************************
3032  *
3033  *  Setup networking device structure and register interface media.
3034  *
3035  **********************************************************************/
3036 static int
3037 em_setup_interface(if_ctx_t ctx)
3038 {
3039 	if_t ifp = iflib_get_ifp(ctx);
3040 	struct e1000_softc *sc = iflib_get_softc(ctx);
3041 	if_softc_ctx_t scctx = sc->shared;
3042 
3043 	INIT_DEBUGOUT("em_setup_interface: begin");
3044 
3045 	/* Single Queue */
3046 	if (sc->tx_num_queues == 1) {
3047 		if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
3048 		if_setsendqready(ifp);
3049 	}
3050 
3051 	/*
3052 	 * Specify the media types supported by this adapter and register
3053 	 * callbacks to update media and link information
3054 	 */
3055 	if (sc->hw.phy.media_type == e1000_media_type_fiber ||
3056 	    sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
3057 		u_char fiber_type = IFM_1000_SX;	/* default type */
3058 
3059 		if (sc->hw.mac.type == e1000_82545)
3060 			fiber_type = IFM_1000_LX;
3061 		ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
3062 		ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL);
3063 	} else {
3064 		ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
3065 		ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
3066 		ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
3067 		ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
3068 		if (sc->hw.phy.type != e1000_phy_ife) {
3069 			ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
3070 			ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
3071 		}
3072 	}
3073 	ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3074 	ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
3075 	return (0);
3076 }
3077 
3078 static int
3079 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
3080 {
3081 	struct e1000_softc *sc = iflib_get_softc(ctx);
3082 	if_softc_ctx_t scctx = sc->shared;
3083 	int error = E1000_SUCCESS;
3084 	struct em_tx_queue *que;
3085 	int i, j;
3086 
3087 	MPASS(sc->tx_num_queues > 0);
3088 	MPASS(sc->tx_num_queues == ntxqsets);
3089 
3090 	/* First allocate the top level queue structs */
3091 	if (!(sc->tx_queues =
3092 	    (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
3093 	    sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
3094 		device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
3095 		return(ENOMEM);
3096 	}
3097 
3098 	for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
3099 		/* Set up some basics */
3100 
3101 		struct tx_ring *txr = &que->txr;
3102 		txr->sc = que->sc = sc;
3103 		que->me = txr->me =  i;
3104 
3105 		/* Allocate report status array */
3106 		if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
3107 			device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
3108 			error = ENOMEM;
3109 			goto fail;
3110 		}
3111 		for (j = 0; j < scctx->isc_ntxd[0]; j++)
3112 			txr->tx_rsq[j] = QIDX_INVALID;
3113 		/* get the virtual and physical address of the hardware queues */
3114 		txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
3115 		txr->tx_paddr = paddrs[i*ntxqs];
3116 	}
3117 
3118 	if (bootverbose)
3119 		device_printf(iflib_get_dev(ctx),
3120 		    "allocated for %d tx_queues\n", sc->tx_num_queues);
3121 	return (0);
3122 fail:
3123 	em_if_queues_free(ctx);
3124 	return (error);
3125 }
3126 
3127 static int
3128 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
3129 {
3130 	struct e1000_softc *sc = iflib_get_softc(ctx);
3131 	int error = E1000_SUCCESS;
3132 	struct em_rx_queue *que;
3133 	int i;
3134 
3135 	MPASS(sc->rx_num_queues > 0);
3136 	MPASS(sc->rx_num_queues == nrxqsets);
3137 
3138 	/* First allocate the top level queue structs */
3139 	if (!(sc->rx_queues =
3140 	    (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
3141 	    sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
3142 		device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
3143 		error = ENOMEM;
3144 		goto fail;
3145 	}
3146 
3147 	for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
3148 		/* Set up some basics */
3149 		struct rx_ring *rxr = &que->rxr;
3150 		rxr->sc = que->sc = sc;
3151 		rxr->que = que;
3152 		que->me = rxr->me =  i;
3153 
3154 		/* get the virtual and physical address of the hardware queues */
3155 		rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
3156 		rxr->rx_paddr = paddrs[i*nrxqs];
3157 	}
3158 
3159 	if (bootverbose)
3160 		device_printf(iflib_get_dev(ctx),
3161 		    "allocated for %d rx_queues\n", sc->rx_num_queues);
3162 
3163 	return (0);
3164 fail:
3165 	em_if_queues_free(ctx);
3166 	return (error);
3167 }
3168 
3169 static void
3170 em_if_queues_free(if_ctx_t ctx)
3171 {
3172 	struct e1000_softc *sc = iflib_get_softc(ctx);
3173 	struct em_tx_queue *tx_que = sc->tx_queues;
3174 	struct em_rx_queue *rx_que = sc->rx_queues;
3175 
3176 	if (tx_que != NULL) {
3177 		for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
3178 			struct tx_ring *txr = &tx_que->txr;
3179 			if (txr->tx_rsq == NULL)
3180 				break;
3181 
3182 			free(txr->tx_rsq, M_DEVBUF);
3183 			txr->tx_rsq = NULL;
3184 		}
3185 		free(sc->tx_queues, M_DEVBUF);
3186 		sc->tx_queues = NULL;
3187 	}
3188 
3189 	if (rx_que != NULL) {
3190 		free(sc->rx_queues, M_DEVBUF);
3191 		sc->rx_queues = NULL;
3192 	}
3193 }
3194 
3195 /*********************************************************************
3196  *
3197  *  Enable transmit unit.
3198  *
3199  **********************************************************************/
3200 static void
3201 em_initialize_transmit_unit(if_ctx_t ctx)
3202 {
3203 	struct e1000_softc *sc = iflib_get_softc(ctx);
3204 	if_softc_ctx_t scctx = sc->shared;
3205 	struct em_tx_queue *que;
3206 	struct tx_ring	*txr;
3207 	struct e1000_hw	*hw = &sc->hw;
3208 	u32 tctl, txdctl = 0, tarc, tipg = 0;
3209 
3210 	INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3211 
3212 	for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3213 		u64 bus_addr;
3214 		caddr_t offp, endp;
3215 
3216 		que = &sc->tx_queues[i];
3217 		txr = &que->txr;
3218 		bus_addr = txr->tx_paddr;
3219 
3220 		/* Clear checksum offload context. */
3221 		offp = (caddr_t)&txr->csum_flags;
3222 		endp = (caddr_t)(txr + 1);
3223 		bzero(offp, endp - offp);
3224 
3225 		/* Base and Len of TX Ring */
3226 		E1000_WRITE_REG(hw, E1000_TDLEN(i),
3227 		    scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3228 		E1000_WRITE_REG(hw, E1000_TDBAH(i),
3229 		    (u32)(bus_addr >> 32));
3230 		E1000_WRITE_REG(hw, E1000_TDBAL(i),
3231 		    (u32)bus_addr);
3232 		/* Init the HEAD/TAIL indices */
3233 		E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3234 		E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3235 
3236 		HW_DEBUGOUT2("Base = %x, Length = %x\n",
3237 		    E1000_READ_REG(hw, E1000_TDBAL(i)),
3238 		    E1000_READ_REG(hw, E1000_TDLEN(i)));
3239 
3240 		txdctl = 0; /* clear txdctl */
3241 		txdctl |= 0x1f; /* PTHRESH */
3242 		txdctl |= 1 << 8; /* HTHRESH */
3243 		txdctl |= 1 << 16;/* WTHRESH */
3244 		txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3245 		txdctl |= E1000_TXDCTL_GRAN;
3246 		txdctl |= 1 << 25; /* LWTHRESH */
3247 
3248 		E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3249 	}
3250 
3251 	/* Set the default values for the Tx Inter Packet Gap timer */
3252 	switch (hw->mac.type) {
3253 	case e1000_80003es2lan:
3254 		tipg = DEFAULT_82543_TIPG_IPGR1;
3255 		tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3256 		    E1000_TIPG_IPGR2_SHIFT;
3257 		break;
3258 	case e1000_82542:
3259 		tipg = DEFAULT_82542_TIPG_IPGT;
3260 		tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3261 		tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3262 		break;
3263 	default:
3264 		if (hw->phy.media_type == e1000_media_type_fiber ||
3265 		    hw->phy.media_type == e1000_media_type_internal_serdes)
3266 			tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3267 		else
3268 			tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3269 		tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3270 		tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3271 	}
3272 
3273 	E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3274 	E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
3275 
3276 	if(hw->mac.type >= e1000_82540)
3277 		E1000_WRITE_REG(hw, E1000_TADV,
3278 		    sc->tx_abs_int_delay.value);
3279 
3280 	if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3281 		tarc = E1000_READ_REG(hw, E1000_TARC(0));
3282 		tarc |= TARC_SPEED_MODE_BIT;
3283 		E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3284 	} else if (hw->mac.type == e1000_80003es2lan) {
3285 		/* errata: program both queues to unweighted RR */
3286 		tarc = E1000_READ_REG(hw, E1000_TARC(0));
3287 		tarc |= 1;
3288 		E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3289 		tarc = E1000_READ_REG(hw, E1000_TARC(1));
3290 		tarc |= 1;
3291 		E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3292 	} else if (hw->mac.type == e1000_82574) {
3293 		tarc = E1000_READ_REG(hw, E1000_TARC(0));
3294 		tarc |= TARC_ERRATA_BIT;
3295 		if ( sc->tx_num_queues > 1) {
3296 			tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3297 			E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3298 			E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3299 		} else
3300 			E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3301 	}
3302 
3303 	if (sc->tx_int_delay.value > 0)
3304 		sc->txd_cmd |= E1000_TXD_CMD_IDE;
3305 
3306 	/* Program the Transmit Control Register */
3307 	tctl = E1000_READ_REG(hw, E1000_TCTL);
3308 	tctl &= ~E1000_TCTL_CT;
3309 	tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3310 		   (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3311 
3312 	if (hw->mac.type >= e1000_82571)
3313 		tctl |= E1000_TCTL_MULR;
3314 
3315 	/* This write will effectively turn on the transmit unit. */
3316 	E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3317 
3318 	/* SPT and KBL errata workarounds */
3319 	if (hw->mac.type == e1000_pch_spt) {
3320 		u32 reg;
3321 		reg = E1000_READ_REG(hw, E1000_IOSFPC);
3322 		reg |= E1000_RCTL_RDMTS_HEX;
3323 		E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3324 		/* i218-i219 Specification Update 1.5.4.5 */
3325 		reg = E1000_READ_REG(hw, E1000_TARC(0));
3326 		reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3327 		reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3328 		E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3329 	}
3330 }
3331 
3332 /*********************************************************************
3333  *
3334  *  Enable receive unit.
3335  *
3336  **********************************************************************/
3337 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3338 
3339 static void
3340 em_initialize_receive_unit(if_ctx_t ctx)
3341 {
3342 	struct e1000_softc *sc = iflib_get_softc(ctx);
3343 	if_softc_ctx_t scctx = sc->shared;
3344 	if_t ifp = iflib_get_ifp(ctx);
3345 	struct e1000_hw	*hw = &sc->hw;
3346 	struct em_rx_queue *que;
3347 	int i;
3348 	uint32_t rctl, rxcsum;
3349 
3350 	INIT_DEBUGOUT("em_initialize_receive_units: begin");
3351 
3352 	/*
3353 	 * Make sure receives are disabled while setting
3354 	 * up the descriptor ring
3355 	 */
3356 	rctl = E1000_READ_REG(hw, E1000_RCTL);
3357 	/* Do not disable if ever enabled on this hardware */
3358 	if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3359 		E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3360 
3361 	/* Setup the Receive Control Register */
3362 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3363 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3364 	    E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3365 	    (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3366 
3367 	/* Do not store bad packets */
3368 	rctl &= ~E1000_RCTL_SBP;
3369 
3370 	/* Enable Long Packet receive */
3371 	if (if_getmtu(ifp) > ETHERMTU)
3372 		rctl |= E1000_RCTL_LPE;
3373 	else
3374 		rctl &= ~E1000_RCTL_LPE;
3375 
3376 	/* Strip the CRC */
3377 	if (!em_disable_crc_stripping)
3378 		rctl |= E1000_RCTL_SECRC;
3379 
3380 	if (hw->mac.type >= e1000_82540) {
3381 		E1000_WRITE_REG(hw, E1000_RADV,
3382 		    sc->rx_abs_int_delay.value);
3383 
3384 		/*
3385 		 * Set the interrupt throttling rate. Value is calculated
3386 		 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3387 		 */
3388 		E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3389 	}
3390 	E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value);
3391 
3392 	if (hw->mac.type >= em_mac_min) {
3393 		uint32_t rfctl;
3394 		/* Use extended rx descriptor formats */
3395 		rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3396 		rfctl |= E1000_RFCTL_EXTEN;
3397 
3398 		/*
3399 		 * When using MSI-X interrupts we need to throttle
3400 		 * using the EITR register (82574 only)
3401 		 */
3402 		if (hw->mac.type == e1000_82574) {
3403 			for (int i = 0; i < 4; i++)
3404 				E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3405 				    DEFAULT_ITR);
3406 			/* Disable accelerated acknowledge */
3407 			rfctl |= E1000_RFCTL_ACK_DIS;
3408 		}
3409 		E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3410 	}
3411 
3412 	/* Set up L3 and L4 csum Rx descriptor offloads */
3413 	rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3414 	if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
3415 		rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3416 		if (hw->mac.type > e1000_82575)
3417 			rxcsum |= E1000_RXCSUM_CRCOFL;
3418 		else if (hw->mac.type < em_mac_min &&
3419 		    if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6)
3420 			rxcsum |= E1000_RXCSUM_IPV6OFL;
3421 	} else {
3422 		rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3423 		if (hw->mac.type > e1000_82575)
3424 			rxcsum &= ~E1000_RXCSUM_CRCOFL;
3425 		else if (hw->mac.type < em_mac_min)
3426 			rxcsum &= ~E1000_RXCSUM_IPV6OFL;
3427 	}
3428 
3429 	if (sc->rx_num_queues > 1) {
3430 		/* RSS hash needed in the Rx descriptor */
3431 		rxcsum |= E1000_RXCSUM_PCSD;
3432 
3433 		if (hw->mac.type >= igb_mac_min)
3434 			igb_initialize_rss_mapping(sc);
3435 		else
3436 			em_initialize_rss_mapping(sc);
3437 	}
3438 	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3439 
3440 	/*
3441 	 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3442 	 * long latencies are observed, like Lenovo X60. This
3443 	 * change eliminates the problem, but since having positive
3444 	 * values in RDTR is a known source of problems on other
3445 	 * platforms another solution is being sought.
3446 	 */
3447 	if (hw->mac.type == e1000_82573)
3448 		E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3449 
3450 	for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3451 		struct rx_ring *rxr = &que->rxr;
3452 		/* Setup the Base and Length of the Rx Descriptor Ring */
3453 		u64 bus_addr = rxr->rx_paddr;
3454 #if 0
3455 		u32 rdt = sc->rx_num_queues -1;  /* default */
3456 #endif
3457 
3458 		E1000_WRITE_REG(hw, E1000_RDLEN(i),
3459 		    scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3460 		E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3461 		E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3462 		/* Setup the Head and Tail Descriptor Pointers */
3463 		E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3464 		E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3465 	}
3466 
3467 	/*
3468 	 * Set PTHRESH for improved jumbo performance
3469 	 * According to 10.2.5.11 of Intel 82574 Datasheet,
3470 	 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3471 	 * Only write to RXDCTL(1) if there is a need for different
3472 	 * settings.
3473 	 */
3474 	if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3475 	    hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3476 		u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3477 		E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3478 	} else if (hw->mac.type == e1000_82574) {
3479 		for (int i = 0; i < sc->rx_num_queues; i++) {
3480 			u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3481 			rxdctl |= 0x20; /* PTHRESH */
3482 			rxdctl |= 4 << 8; /* HTHRESH */
3483 			rxdctl |= 4 << 16;/* WTHRESH */
3484 			rxdctl |= 1 << 24; /* Switch to granularity */
3485 			E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3486 		}
3487 	} else if (hw->mac.type >= igb_mac_min) {
3488 		u32 psize, srrctl = 0;
3489 
3490 		if (if_getmtu(ifp) > ETHERMTU) {
3491 			psize = scctx->isc_max_frame_size;
3492 			/* are we on a vlan? */
3493 			if (if_vlantrunkinuse(ifp))
3494 				psize += VLAN_TAG_SIZE;
3495 
3496 			if (sc->vf_ifp)
3497 				e1000_rlpml_set_vf(hw, psize);
3498 			else
3499 				E1000_WRITE_REG(hw, E1000_RLPML, psize);
3500 		}
3501 
3502 		/* Set maximum packet buffer len */
3503 		srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3504 		    E1000_SRRCTL_BSIZEPKT_SHIFT;
3505 
3506 		/*
3507 		 * If TX flow control is disabled and there's >1 queue defined,
3508 		 * enable DROP.
3509 		 *
3510 		 * This drops frames rather than hanging the RX MAC for all queues.
3511 		 */
3512 		if ((sc->rx_num_queues > 1) &&
3513 		    (sc->fc == e1000_fc_none ||
3514 		     sc->fc == e1000_fc_rx_pause)) {
3515 			srrctl |= E1000_SRRCTL_DROP_EN;
3516 		}
3517 			/* Setup the Base and Length of the Rx Descriptor Rings */
3518 		for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3519 			struct rx_ring *rxr = &que->rxr;
3520 			u64 bus_addr = rxr->rx_paddr;
3521 			u32 rxdctl;
3522 
3523 #ifdef notyet
3524 			/* Configure for header split? -- ignore for now */
3525 			rxr->hdr_split = igb_header_split;
3526 #else
3527 			srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3528 #endif
3529 
3530 			E1000_WRITE_REG(hw, E1000_RDLEN(i),
3531 					scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3532 			E1000_WRITE_REG(hw, E1000_RDBAH(i),
3533 					(uint32_t)(bus_addr >> 32));
3534 			E1000_WRITE_REG(hw, E1000_RDBAL(i),
3535 					(uint32_t)bus_addr);
3536 			E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3537 			/* Enable this Queue */
3538 			rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3539 			rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3540 			rxdctl &= 0xFFF00000;
3541 			rxdctl |= IGB_RX_PTHRESH;
3542 			rxdctl |= IGB_RX_HTHRESH << 8;
3543 			rxdctl |= IGB_RX_WTHRESH << 16;
3544 			E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3545 		}
3546 	} else if (hw->mac.type >= e1000_pch2lan) {
3547 		if (if_getmtu(ifp) > ETHERMTU)
3548 			e1000_lv_jumbo_workaround_ich8lan(hw, true);
3549 		else
3550 			e1000_lv_jumbo_workaround_ich8lan(hw, false);
3551 	}
3552 
3553 	/* Make sure VLAN Filters are off */
3554 	rctl &= ~E1000_RCTL_VFE;
3555 
3556 	/* Set up packet buffer size, overridden by per queue srrctl on igb */
3557 	if (hw->mac.type < igb_mac_min) {
3558 		if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096)
3559 			rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3560 		else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192)
3561 			rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3562 		else if (sc->rx_mbuf_sz > 8192)
3563 			rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
3564 		else {
3565 			rctl |= E1000_RCTL_SZ_2048;
3566 			rctl &= ~E1000_RCTL_BSEX;
3567 		}
3568 	} else
3569 		rctl |= E1000_RCTL_SZ_2048;
3570 
3571 	/*
3572 	 * rctl bits 11:10 are as follows
3573 	 * lem: reserved
3574 	 * em: DTYPE
3575 	 * igb: reserved
3576 	 * and should be 00 on all of the above
3577 	 */
3578 	rctl &= ~0x00000C00;
3579 
3580 	/* Write out the settings */
3581 	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3582 
3583 	return;
3584 }
3585 
3586 static void
3587 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3588 {
3589 	struct e1000_softc *sc = iflib_get_softc(ctx);
3590 	u32 index, bit;
3591 
3592 	index = (vtag >> 5) & 0x7F;
3593 	bit = vtag & 0x1F;
3594 	sc->shadow_vfta[index] |= (1 << bit);
3595 	++sc->num_vlans;
3596 	em_if_vlan_filter_write(sc);
3597 }
3598 
3599 static void
3600 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3601 {
3602 	struct e1000_softc *sc = iflib_get_softc(ctx);
3603 	u32 index, bit;
3604 
3605 	index = (vtag >> 5) & 0x7F;
3606 	bit = vtag & 0x1F;
3607 	sc->shadow_vfta[index] &= ~(1 << bit);
3608 	--sc->num_vlans;
3609 	em_if_vlan_filter_write(sc);
3610 }
3611 
3612 static bool
3613 em_if_vlan_filter_capable(if_ctx_t ctx)
3614 {
3615 	if_t ifp = iflib_get_ifp(ctx);
3616 
3617 	if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) &&
3618 	    !em_disable_crc_stripping)
3619 		return (true);
3620 
3621 	return (false);
3622 }
3623 
3624 static bool
3625 em_if_vlan_filter_used(if_ctx_t ctx)
3626 {
3627 	struct e1000_softc *sc = iflib_get_softc(ctx);
3628 
3629 	if (!em_if_vlan_filter_capable(ctx))
3630 		return (false);
3631 
3632 	for (int i = 0; i < EM_VFTA_SIZE; i++)
3633 		if (sc->shadow_vfta[i] != 0)
3634 			return (true);
3635 
3636 	return (false);
3637 }
3638 
3639 static void
3640 em_if_vlan_filter_enable(struct e1000_softc *sc)
3641 {
3642 	struct e1000_hw *hw = &sc->hw;
3643 	u32 reg;
3644 
3645 	reg = E1000_READ_REG(hw, E1000_RCTL);
3646 	reg &= ~E1000_RCTL_CFIEN;
3647 	reg |= E1000_RCTL_VFE;
3648 	E1000_WRITE_REG(hw, E1000_RCTL, reg);
3649 }
3650 
3651 static void
3652 em_if_vlan_filter_disable(struct e1000_softc *sc)
3653 {
3654 	struct e1000_hw *hw = &sc->hw;
3655 	u32 reg;
3656 
3657 	reg = E1000_READ_REG(hw, E1000_RCTL);
3658 	reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
3659 	E1000_WRITE_REG(hw, E1000_RCTL, reg);
3660 }
3661 
3662 static void
3663 em_if_vlan_filter_write(struct e1000_softc *sc)
3664 {
3665 	struct e1000_hw *hw = &sc->hw;
3666 
3667 	if (sc->vf_ifp)
3668 		return;
3669 
3670 	/* Disable interrupts for lem-class devices during the filter change */
3671 	if (hw->mac.type < em_mac_min)
3672 		em_if_intr_disable(sc->ctx);
3673 
3674 	for (int i = 0; i < EM_VFTA_SIZE; i++)
3675 		if (sc->shadow_vfta[i] != 0) {
3676 			/* XXXKB: incomplete VF support, we return early above */
3677 			if (sc->vf_ifp)
3678 				e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true);
3679 			else
3680 				e1000_write_vfta(hw, i, sc->shadow_vfta[i]);
3681 		}
3682 
3683 	/* Re-enable interrupts for lem-class devices */
3684 	if (hw->mac.type < em_mac_min)
3685 		em_if_intr_enable(sc->ctx);
3686 }
3687 
3688 static void
3689 em_setup_vlan_hw_support(if_ctx_t ctx)
3690 {
3691 	struct e1000_softc *sc = iflib_get_softc(ctx);
3692 	struct e1000_hw *hw = &sc->hw;
3693 	if_t ifp = iflib_get_ifp(ctx);
3694 	u32 reg;
3695 
3696 	/* XXXKB: Return early if we are a VF until VF decap and filter management
3697 	 * is ready and tested.
3698 	 */
3699 	if (sc->vf_ifp)
3700 		return;
3701 
3702 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
3703 	    !em_disable_crc_stripping) {
3704 		reg = E1000_READ_REG(hw, E1000_CTRL);
3705 		reg |= E1000_CTRL_VME;
3706 		E1000_WRITE_REG(hw, E1000_CTRL, reg);
3707 	} else {
3708 		reg = E1000_READ_REG(hw, E1000_CTRL);
3709 		reg &= ~E1000_CTRL_VME;
3710 		E1000_WRITE_REG(hw, E1000_CTRL, reg);
3711 	}
3712 
3713 	/* If we aren't doing HW filtering, we're done */
3714 	if (!em_if_vlan_filter_capable(ctx))  {
3715 		em_if_vlan_filter_disable(sc);
3716 		return;
3717 	}
3718 
3719 	/*
3720 	 * A soft reset zero's out the VFTA, so
3721 	 * we need to repopulate it now.
3722 	 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged
3723 	 * traffic through. This will write the entire table.
3724 	 */
3725 	em_if_vlan_register(ctx, 0);
3726 
3727 	/* Enable the Filter Table */
3728 	em_if_vlan_filter_enable(sc);
3729 }
3730 
3731 static void
3732 em_if_intr_enable(if_ctx_t ctx)
3733 {
3734 	struct e1000_softc *sc = iflib_get_softc(ctx);
3735 	struct e1000_hw *hw = &sc->hw;
3736 	u32 ims_mask = IMS_ENABLE_MASK;
3737 
3738 	if (sc->intr_type == IFLIB_INTR_MSIX) {
3739 		E1000_WRITE_REG(hw, EM_EIAC, sc->ims);
3740 		ims_mask |= sc->ims;
3741 	}
3742 	E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3743 	E1000_WRITE_FLUSH(hw);
3744 }
3745 
3746 static void
3747 em_if_intr_disable(if_ctx_t ctx)
3748 {
3749 	struct e1000_softc *sc = iflib_get_softc(ctx);
3750 	struct e1000_hw *hw = &sc->hw;
3751 
3752 	if (sc->intr_type == IFLIB_INTR_MSIX)
3753 		E1000_WRITE_REG(hw, EM_EIAC, 0);
3754 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3755 	E1000_WRITE_FLUSH(hw);
3756 }
3757 
3758 static void
3759 igb_if_intr_enable(if_ctx_t ctx)
3760 {
3761 	struct e1000_softc *sc = iflib_get_softc(ctx);
3762 	struct e1000_hw *hw = &sc->hw;
3763 	u32 mask;
3764 
3765 	if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
3766 		mask = (sc->que_mask | sc->link_mask);
3767 		E1000_WRITE_REG(hw, E1000_EIAC, mask);
3768 		E1000_WRITE_REG(hw, E1000_EIAM, mask);
3769 		E1000_WRITE_REG(hw, E1000_EIMS, mask);
3770 		E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3771 	} else
3772 		E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3773 	E1000_WRITE_FLUSH(hw);
3774 }
3775 
3776 static void
3777 igb_if_intr_disable(if_ctx_t ctx)
3778 {
3779 	struct e1000_softc *sc = iflib_get_softc(ctx);
3780 	struct e1000_hw *hw = &sc->hw;
3781 
3782 	if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
3783 		E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3784 		E1000_WRITE_REG(hw, E1000_EIAC, 0);
3785 	}
3786 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3787 	E1000_WRITE_FLUSH(hw);
3788 }
3789 
3790 /*
3791  * Bit of a misnomer, what this really means is
3792  * to enable OS management of the system... aka
3793  * to disable special hardware management features
3794  */
3795 static void
3796 em_init_manageability(struct e1000_softc *sc)
3797 {
3798 	/* A shared code workaround */
3799 #define E1000_82542_MANC2H E1000_MANC2H
3800 	if (sc->has_manage) {
3801 		int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3802 		int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3803 
3804 		/* disable hardware interception of ARP */
3805 		manc &= ~(E1000_MANC_ARP_EN);
3806 
3807 		/* enable receiving management packets to the host */
3808 		manc |= E1000_MANC_EN_MNG2HOST;
3809 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3810 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3811 		manc2h |= E1000_MNG2HOST_PORT_623;
3812 		manc2h |= E1000_MNG2HOST_PORT_664;
3813 		E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3814 		E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3815 	}
3816 }
3817 
3818 /*
3819  * Give control back to hardware management
3820  * controller if there is one.
3821  */
3822 static void
3823 em_release_manageability(struct e1000_softc *sc)
3824 {
3825 	if (sc->has_manage) {
3826 		int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3827 
3828 		/* re-enable hardware interception of ARP */
3829 		manc |= E1000_MANC_ARP_EN;
3830 		manc &= ~E1000_MANC_EN_MNG2HOST;
3831 
3832 		E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3833 	}
3834 }
3835 
3836 /*
3837  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3838  * For ASF and Pass Through versions of f/w this means
3839  * that the driver is loaded. For AMT version type f/w
3840  * this means that the network i/f is open.
3841  */
3842 static void
3843 em_get_hw_control(struct e1000_softc *sc)
3844 {
3845 	u32 ctrl_ext, swsm;
3846 
3847 	if (sc->vf_ifp)
3848 		return;
3849 
3850 	if (sc->hw.mac.type == e1000_82573) {
3851 		swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3852 		E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3853 		    swsm | E1000_SWSM_DRV_LOAD);
3854 		return;
3855 	}
3856 	/* else */
3857 	ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3858 	E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3859 	    ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3860 }
3861 
3862 /*
3863  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3864  * For ASF and Pass Through versions of f/w this means that
3865  * the driver is no longer loaded. For AMT versions of the
3866  * f/w this means that the network i/f is closed.
3867  */
3868 static void
3869 em_release_hw_control(struct e1000_softc *sc)
3870 {
3871 	u32 ctrl_ext, swsm;
3872 
3873 	if (!sc->has_manage)
3874 		return;
3875 
3876 	if (sc->hw.mac.type == e1000_82573) {
3877 		swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3878 		E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3879 		    swsm & ~E1000_SWSM_DRV_LOAD);
3880 		return;
3881 	}
3882 	/* else */
3883 	ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3884 	E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3885 	    ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3886 	return;
3887 }
3888 
3889 static int
3890 em_is_valid_ether_addr(u8 *addr)
3891 {
3892 	char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3893 
3894 	if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3895 		return (false);
3896 	}
3897 
3898 	return (true);
3899 }
3900 
3901 static bool
3902 em_automask_tso(if_ctx_t ctx)
3903 {
3904 	struct e1000_softc *sc = iflib_get_softc(ctx);
3905 	if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
3906 	if_t ifp = iflib_get_ifp(ctx);
3907 
3908 	if (!em_unsupported_tso && sc->link_speed &&
3909 	    sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) {
3910 		device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n");
3911 		sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO;
3912 		scctx->isc_capenable &= ~IFCAP_TSO;
3913 		if_setcapenablebit(ifp, 0, IFCAP_TSO);
3914 		/* iflib_init_locked handles ifnet hwassistbits */
3915 		iflib_request_reset(ctx);
3916 		return true;
3917 	} else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) {
3918 		device_printf(sc->dev, "Re-enabling TSO for GbE.\n");
3919 		scctx->isc_capenable |= sc->tso_automasked;
3920 		if_setcapenablebit(ifp, sc->tso_automasked, 0);
3921 		sc->tso_automasked = 0;
3922 		/* iflib_init_locked handles ifnet hwassistbits */
3923 		iflib_request_reset(ctx);
3924 		return true;
3925 	}
3926 
3927 	return false;
3928 }
3929 
3930 /*
3931 ** Parse the interface capabilities with regard
3932 ** to both system management and wake-on-lan for
3933 ** later use.
3934 */
3935 static void
3936 em_get_wakeup(if_ctx_t ctx)
3937 {
3938 	struct e1000_softc *sc = iflib_get_softc(ctx);
3939 	device_t dev = iflib_get_dev(ctx);
3940 	u16 eeprom_data = 0, device_id, apme_mask;
3941 
3942 	sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
3943 	apme_mask = EM_EEPROM_APME;
3944 
3945 	switch (sc->hw.mac.type) {
3946 	case e1000_82542:
3947 	case e1000_82543:
3948 		break;
3949 	case e1000_82544:
3950 		e1000_read_nvm(&sc->hw,
3951 		    NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3952 		apme_mask = EM_82544_APME;
3953 		break;
3954 	case e1000_82546:
3955 	case e1000_82546_rev_3:
3956 		if (sc->hw.bus.func == 1) {
3957 			e1000_read_nvm(&sc->hw,
3958 			    NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3959 			break;
3960 		} else
3961 			e1000_read_nvm(&sc->hw,
3962 			    NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3963 		break;
3964 	case e1000_82573:
3965 	case e1000_82583:
3966 		sc->has_amt = true;
3967 		/* FALLTHROUGH */
3968 	case e1000_82571:
3969 	case e1000_82572:
3970 	case e1000_80003es2lan:
3971 		if (sc->hw.bus.func == 1) {
3972 			e1000_read_nvm(&sc->hw,
3973 			    NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3974 			break;
3975 		} else
3976 			e1000_read_nvm(&sc->hw,
3977 			    NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3978 		break;
3979 	case e1000_ich8lan:
3980 	case e1000_ich9lan:
3981 	case e1000_ich10lan:
3982 	case e1000_pchlan:
3983 	case e1000_pch2lan:
3984 	case e1000_pch_lpt:
3985 	case e1000_pch_spt:
3986 	case e1000_82575:	/* listing all igb devices */
3987 	case e1000_82576:
3988 	case e1000_82580:
3989 	case e1000_i350:
3990 	case e1000_i354:
3991 	case e1000_i210:
3992 	case e1000_i211:
3993 	case e1000_vfadapt:
3994 	case e1000_vfadapt_i350:
3995 		apme_mask = E1000_WUC_APME;
3996 		sc->has_amt = true;
3997 		eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC);
3998 		break;
3999 	default:
4000 		e1000_read_nvm(&sc->hw,
4001 		    NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
4002 		break;
4003 	}
4004 	if (eeprom_data & apme_mask)
4005 		sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
4006 	/*
4007 	 * We have the eeprom settings, now apply the special cases
4008 	 * where the eeprom may be wrong or the board won't support
4009 	 * wake on lan on a particular port
4010 	 */
4011 	device_id = pci_get_device(dev);
4012 	switch (device_id) {
4013 	case E1000_DEV_ID_82546GB_PCIE:
4014 		sc->wol = 0;
4015 		break;
4016 	case E1000_DEV_ID_82546EB_FIBER:
4017 	case E1000_DEV_ID_82546GB_FIBER:
4018 		/* Wake events only supported on port A for dual fiber
4019 		 * regardless of eeprom setting */
4020 		if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
4021 		    E1000_STATUS_FUNC_1)
4022 			sc->wol = 0;
4023 		break;
4024 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
4025 		/* if quad port adapter, disable WoL on all but port A */
4026 		if (global_quad_port_a != 0)
4027 			sc->wol = 0;
4028 		/* Reset for multiple quad port adapters */
4029 		if (++global_quad_port_a == 4)
4030 			global_quad_port_a = 0;
4031 		break;
4032 	case E1000_DEV_ID_82571EB_FIBER:
4033 		/* Wake events only supported on port A for dual fiber
4034 		 * regardless of eeprom setting */
4035 		if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
4036 		    E1000_STATUS_FUNC_1)
4037 			sc->wol = 0;
4038 		break;
4039 	case E1000_DEV_ID_82571EB_QUAD_COPPER:
4040 	case E1000_DEV_ID_82571EB_QUAD_FIBER:
4041 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
4042 		/* if quad port adapter, disable WoL on all but port A */
4043 		if (global_quad_port_a != 0)
4044 			sc->wol = 0;
4045 		/* Reset for multiple quad port adapters */
4046 		if (++global_quad_port_a == 4)
4047 			global_quad_port_a = 0;
4048 		break;
4049 	}
4050 	return;
4051 }
4052 
4053 
4054 /*
4055  * Enable PCI Wake On Lan capability
4056  */
4057 static void
4058 em_enable_wakeup(if_ctx_t ctx)
4059 {
4060 	struct e1000_softc *sc = iflib_get_softc(ctx);
4061 	device_t dev = iflib_get_dev(ctx);
4062 	if_t ifp = iflib_get_ifp(ctx);
4063 	int error = 0;
4064 	u32 pmc, ctrl, ctrl_ext, rctl;
4065 	u16 status;
4066 
4067 	if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
4068 		return;
4069 
4070 	/*
4071 	 * Determine type of Wakeup: note that wol
4072 	 * is set with all bits on by default.
4073 	 */
4074 	if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
4075 		sc->wol &= ~E1000_WUFC_MAG;
4076 
4077 	if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
4078 		sc->wol &= ~E1000_WUFC_EX;
4079 
4080 	if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
4081 		sc->wol &= ~E1000_WUFC_MC;
4082 	else {
4083 		rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
4084 		rctl |= E1000_RCTL_MPE;
4085 		E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
4086 	}
4087 
4088 	if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
4089 		goto pme;
4090 
4091 	/* Advertise the wakeup capability */
4092 	ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
4093 	ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
4094 	E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
4095 
4096 	/* Keep the laser running on Fiber adapters */
4097 	if (sc->hw.phy.media_type == e1000_media_type_fiber ||
4098 	    sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
4099 		ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4100 		ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
4101 		E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext);
4102 	}
4103 
4104 	if ((sc->hw.mac.type == e1000_ich8lan) ||
4105 	    (sc->hw.mac.type == e1000_pchlan) ||
4106 	    (sc->hw.mac.type == e1000_ich9lan) ||
4107 	    (sc->hw.mac.type == e1000_ich10lan))
4108 		e1000_suspend_workarounds_ich8lan(&sc->hw);
4109 
4110 	if ( sc->hw.mac.type >= e1000_pchlan) {
4111 		error = em_enable_phy_wakeup(sc);
4112 		if (error)
4113 			goto pme;
4114 	} else {
4115 		/* Enable wakeup by the MAC */
4116 		E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
4117 		E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
4118 	}
4119 
4120 	if (sc->hw.phy.type == e1000_phy_igp_3)
4121 		e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw);
4122 
4123 pme:
4124 	status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
4125 	status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
4126 	if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
4127 		status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
4128 	pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
4129 
4130 	return;
4131 }
4132 
4133 /*
4134  * WOL in the newer chipset interfaces (pchlan)
4135  * require thing to be copied into the phy
4136  */
4137 static int
4138 em_enable_phy_wakeup(struct e1000_softc *sc)
4139 {
4140 	struct e1000_hw *hw = &sc->hw;
4141 	u32 mreg, ret = 0;
4142 	u16 preg;
4143 
4144 	/* copy MAC RARs to PHY RARs */
4145 	e1000_copy_rx_addrs_to_phy_ich8lan(hw);
4146 
4147 	/* copy MAC MTA to PHY MTA */
4148 	for (int i = 0; i < hw->mac.mta_reg_count; i++) {
4149 		mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
4150 		e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
4151 		e1000_write_phy_reg(hw, BM_MTA(i) + 1,
4152 		    (u16)((mreg >> 16) & 0xFFFF));
4153 	}
4154 
4155 	/* configure PHY Rx Control register */
4156 	e1000_read_phy_reg(hw, BM_RCTL, &preg);
4157 	mreg = E1000_READ_REG(hw, E1000_RCTL);
4158 	if (mreg & E1000_RCTL_UPE)
4159 		preg |= BM_RCTL_UPE;
4160 	if (mreg & E1000_RCTL_MPE)
4161 		preg |= BM_RCTL_MPE;
4162 	preg &= ~(BM_RCTL_MO_MASK);
4163 	if (mreg & E1000_RCTL_MO_3)
4164 		preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
4165 				<< BM_RCTL_MO_SHIFT);
4166 	if (mreg & E1000_RCTL_BAM)
4167 		preg |= BM_RCTL_BAM;
4168 	if (mreg & E1000_RCTL_PMCF)
4169 		preg |= BM_RCTL_PMCF;
4170 	mreg = E1000_READ_REG(hw, E1000_CTRL);
4171 	if (mreg & E1000_CTRL_RFCE)
4172 		preg |= BM_RCTL_RFCE;
4173 	e1000_write_phy_reg(hw, BM_RCTL, preg);
4174 
4175 	/* enable PHY wakeup in MAC register */
4176 	E1000_WRITE_REG(hw, E1000_WUC,
4177 	    E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
4178 	E1000_WRITE_REG(hw, E1000_WUFC, sc->wol);
4179 
4180 	/* configure and enable PHY wakeup in PHY registers */
4181 	e1000_write_phy_reg(hw, BM_WUFC, sc->wol);
4182 	e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
4183 
4184 	/* activate PHY wakeup */
4185 	ret = hw->phy.ops.acquire(hw);
4186 	if (ret) {
4187 		printf("Could not acquire PHY\n");
4188 		return ret;
4189 	}
4190 	e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4191 	                         (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
4192 	ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
4193 	if (ret) {
4194 		printf("Could not read PHY page 769\n");
4195 		goto out;
4196 	}
4197 	preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
4198 	ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
4199 	if (ret)
4200 		printf("Could not set PHY Host Wakeup bit\n");
4201 out:
4202 	hw->phy.ops.release(hw);
4203 
4204 	return ret;
4205 }
4206 
4207 static void
4208 em_if_led_func(if_ctx_t ctx, int onoff)
4209 {
4210 	struct e1000_softc *sc = iflib_get_softc(ctx);
4211 
4212 	if (onoff) {
4213 		e1000_setup_led(&sc->hw);
4214 		e1000_led_on(&sc->hw);
4215 	} else {
4216 		e1000_led_off(&sc->hw);
4217 		e1000_cleanup_led(&sc->hw);
4218 	}
4219 }
4220 
4221 /*
4222  * Disable the L0S and L1 LINK states
4223  */
4224 static void
4225 em_disable_aspm(struct e1000_softc *sc)
4226 {
4227 	int base, reg;
4228 	u16 link_cap,link_ctrl;
4229 	device_t dev = sc->dev;
4230 
4231 	switch (sc->hw.mac.type) {
4232 	case e1000_82573:
4233 	case e1000_82574:
4234 	case e1000_82583:
4235 		break;
4236 	default:
4237 		return;
4238 	}
4239 	if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
4240 		return;
4241 	reg = base + PCIER_LINK_CAP;
4242 	link_cap = pci_read_config(dev, reg, 2);
4243 	if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
4244 		return;
4245 	reg = base + PCIER_LINK_CTL;
4246 	link_ctrl = pci_read_config(dev, reg, 2);
4247 	link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
4248 	pci_write_config(dev, reg, link_ctrl, 2);
4249 	return;
4250 }
4251 
4252 /**********************************************************************
4253  *
4254  *  Update the board statistics counters.
4255  *
4256  **********************************************************************/
4257 static void
4258 em_update_stats_counters(struct e1000_softc *sc)
4259 {
4260 	u64 prev_xoffrxc = sc->stats.xoffrxc;
4261 
4262 	if(sc->hw.phy.media_type == e1000_media_type_copper ||
4263 	   (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4264 		sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
4265 		sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
4266 	}
4267 	sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
4268 	sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
4269 	sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
4270 	sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
4271 
4272 	sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
4273 	sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
4274 	sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
4275 	sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
4276 	sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
4277 	sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
4278 	sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
4279 	sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
4280 	/*
4281 	 ** For watchdog management we need to know if we have been
4282 	 ** paused during the last interval, so capture that here.
4283 	*/
4284 	if (sc->stats.xoffrxc != prev_xoffrxc)
4285 		sc->shared->isc_pause_frames = 1;
4286 	sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
4287 	sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
4288 	sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
4289 	sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
4290 	sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
4291 	sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
4292 	sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
4293 	sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
4294 	sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
4295 	sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
4296 	sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
4297 	sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
4298 
4299 	/* For the 64-bit byte counters the low dword must be read first. */
4300 	/* Both registers clear on the read of the high dword */
4301 
4302 	sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) +
4303 	    ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32);
4304 	sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) +
4305 	    ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32);
4306 
4307 	sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
4308 	sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
4309 	sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
4310 	sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
4311 	sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
4312 
4313 	sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
4314 	sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
4315 
4316 	sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
4317 	sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
4318 	sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
4319 	sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
4320 	sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
4321 	sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
4322 	sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
4323 	sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
4324 	sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
4325 	sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
4326 
4327 	/* Interrupt Counts */
4328 
4329 	sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC);
4330 	sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC);
4331 	sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC);
4332 	sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC);
4333 	sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC);
4334 	sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC);
4335 	sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC);
4336 	sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC);
4337 	sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC);
4338 
4339 	if (sc->hw.mac.type >= e1000_82543) {
4340 		sc->stats.algnerrc +=
4341 		E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
4342 		sc->stats.rxerrc +=
4343 		E1000_READ_REG(&sc->hw, E1000_RXERRC);
4344 		sc->stats.tncrs +=
4345 		E1000_READ_REG(&sc->hw, E1000_TNCRS);
4346 		sc->stats.cexterr +=
4347 		E1000_READ_REG(&sc->hw, E1000_CEXTERR);
4348 		sc->stats.tsctc +=
4349 		E1000_READ_REG(&sc->hw, E1000_TSCTC);
4350 		sc->stats.tsctfc +=
4351 		E1000_READ_REG(&sc->hw, E1000_TSCTFC);
4352 	}
4353 }
4354 
4355 static uint64_t
4356 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4357 {
4358 	struct e1000_softc *sc = iflib_get_softc(ctx);
4359 	if_t ifp = iflib_get_ifp(ctx);
4360 
4361 	switch (cnt) {
4362 	case IFCOUNTER_COLLISIONS:
4363 		return (sc->stats.colc);
4364 	case IFCOUNTER_IERRORS:
4365 		return (sc->dropped_pkts + sc->stats.rxerrc +
4366 		    sc->stats.crcerrs + sc->stats.algnerrc +
4367 		    sc->stats.ruc + sc->stats.roc +
4368 		    sc->stats.mpc + sc->stats.cexterr);
4369 	case IFCOUNTER_OERRORS:
4370 		return (sc->stats.ecol + sc->stats.latecol +
4371 		    sc->watchdog_events);
4372 	default:
4373 		return (if_get_counter_default(ifp, cnt));
4374 	}
4375 }
4376 
4377 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4378  * @ctx: iflib context
4379  * @event: event code to check
4380  *
4381  * Defaults to returning true for unknown events.
4382  *
4383  * @returns true if iflib needs to reinit the interface
4384  */
4385 static bool
4386 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4387 {
4388 	switch (event) {
4389 	case IFLIB_RESTART_VLAN_CONFIG:
4390 		return (false);
4391 	default:
4392 		return (true);
4393 	}
4394 }
4395 
4396 /* Export a single 32-bit register via a read-only sysctl. */
4397 static int
4398 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4399 {
4400 	struct e1000_softc *sc;
4401 	u_int val;
4402 
4403 	sc = oidp->oid_arg1;
4404 	val = E1000_READ_REG(&sc->hw, oidp->oid_arg2);
4405 	return (sysctl_handle_int(oidp, &val, 0, req));
4406 }
4407 
4408 /*
4409  * Add sysctl variables, one per statistic, to the system.
4410  */
4411 static void
4412 em_add_hw_stats(struct e1000_softc *sc)
4413 {
4414 	device_t dev = iflib_get_dev(sc->ctx);
4415 	struct em_tx_queue *tx_que = sc->tx_queues;
4416 	struct em_rx_queue *rx_que = sc->rx_queues;
4417 
4418 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4419 	struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4420 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4421 	struct e1000_hw_stats *stats = &sc->stats;
4422 
4423 	struct sysctl_oid *stat_node, *queue_node, *int_node;
4424 	struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4425 
4426 #define QUEUE_NAME_LEN 32
4427 	char namebuf[QUEUE_NAME_LEN];
4428 
4429 	/* Driver Statistics */
4430 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4431 			CTLFLAG_RD, &sc->dropped_pkts,
4432 			"Driver dropped packets");
4433 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4434 			CTLFLAG_RD, &sc->link_irq,
4435 			"Link MSI-X IRQ Handled");
4436 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4437 			CTLFLAG_RD, &sc->rx_overruns,
4438 			"RX overruns");
4439 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4440 			CTLFLAG_RD, &sc->watchdog_events,
4441 			"Watchdog timeouts");
4442 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4443 	    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4444 	    sc, E1000_CTRL, em_sysctl_reg_handler, "IU",
4445 	    "Device Control Register");
4446 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4447 	    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4448 	    sc, E1000_RCTL, em_sysctl_reg_handler, "IU",
4449 	    "Receiver Control Register");
4450 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4451 			CTLFLAG_RD, &sc->hw.fc.high_water, 0,
4452 			"Flow Control High Watermark");
4453 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4454 			CTLFLAG_RD, &sc->hw.fc.low_water, 0,
4455 			"Flow Control Low Watermark");
4456 
4457 	for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
4458 		struct tx_ring *txr = &tx_que->txr;
4459 		snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4460 		queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4461 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4462 		queue_list = SYSCTL_CHILDREN(queue_node);
4463 
4464 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4465 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4466 		    E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4467 		    "Transmit Descriptor Head");
4468 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4469 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4470 		    E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4471 		    "Transmit Descriptor Tail");
4472 		SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4473 				CTLFLAG_RD, &txr->tx_irq,
4474 				"Queue MSI-X Transmit Interrupts");
4475 	}
4476 
4477 	for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
4478 		struct rx_ring *rxr = &rx_que->rxr;
4479 		snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4480 		queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4481 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4482 		queue_list = SYSCTL_CHILDREN(queue_node);
4483 
4484 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4485 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4486 		    E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4487 		    "Receive Descriptor Head");
4488 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4489 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4490 		    E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4491 		    "Receive Descriptor Tail");
4492 		SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4493 				CTLFLAG_RD, &rxr->rx_irq,
4494 				"Queue MSI-X Receive Interrupts");
4495 	}
4496 
4497 	/* MAC stats get their own sub node */
4498 
4499 	stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4500 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4501 	stat_list = SYSCTL_CHILDREN(stat_node);
4502 
4503 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4504 			CTLFLAG_RD, &stats->ecol,
4505 			"Excessive collisions");
4506 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4507 			CTLFLAG_RD, &stats->scc,
4508 			"Single collisions");
4509 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4510 			CTLFLAG_RD, &stats->mcc,
4511 			"Multiple collisions");
4512 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4513 			CTLFLAG_RD, &stats->latecol,
4514 			"Late collisions");
4515 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4516 			CTLFLAG_RD, &stats->colc,
4517 			"Collision Count");
4518 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4519 			CTLFLAG_RD, &sc->stats.symerrs,
4520 			"Symbol Errors");
4521 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4522 			CTLFLAG_RD, &sc->stats.sec,
4523 			"Sequence Errors");
4524 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4525 			CTLFLAG_RD, &sc->stats.dc,
4526 			"Defer Count");
4527 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4528 			CTLFLAG_RD, &sc->stats.mpc,
4529 			"Missed Packets");
4530 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4531 			CTLFLAG_RD, &sc->stats.rnbc,
4532 			"Receive No Buffers");
4533 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4534 			CTLFLAG_RD, &sc->stats.ruc,
4535 			"Receive Undersize");
4536 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4537 			CTLFLAG_RD, &sc->stats.rfc,
4538 			"Fragmented Packets Received ");
4539 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4540 			CTLFLAG_RD, &sc->stats.roc,
4541 			"Oversized Packets Received");
4542 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4543 			CTLFLAG_RD, &sc->stats.rjc,
4544 			"Recevied Jabber");
4545 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4546 			CTLFLAG_RD, &sc->stats.rxerrc,
4547 			"Receive Errors");
4548 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4549 			CTLFLAG_RD, &sc->stats.crcerrs,
4550 			"CRC errors");
4551 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4552 			CTLFLAG_RD, &sc->stats.algnerrc,
4553 			"Alignment Errors");
4554 	/* On 82575 these are collision counts */
4555 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4556 			CTLFLAG_RD, &sc->stats.cexterr,
4557 			"Collision/Carrier extension errors");
4558 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4559 			CTLFLAG_RD, &sc->stats.xonrxc,
4560 			"XON Received");
4561 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4562 			CTLFLAG_RD, &sc->stats.xontxc,
4563 			"XON Transmitted");
4564 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4565 			CTLFLAG_RD, &sc->stats.xoffrxc,
4566 			"XOFF Received");
4567 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4568 			CTLFLAG_RD, &sc->stats.xofftxc,
4569 			"XOFF Transmitted");
4570 
4571 	/* Packet Reception Stats */
4572 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4573 			CTLFLAG_RD, &sc->stats.tpr,
4574 			"Total Packets Received ");
4575 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4576 			CTLFLAG_RD, &sc->stats.gprc,
4577 			"Good Packets Received");
4578 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4579 			CTLFLAG_RD, &sc->stats.bprc,
4580 			"Broadcast Packets Received");
4581 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4582 			CTLFLAG_RD, &sc->stats.mprc,
4583 			"Multicast Packets Received");
4584 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4585 			CTLFLAG_RD, &sc->stats.prc64,
4586 			"64 byte frames received ");
4587 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4588 			CTLFLAG_RD, &sc->stats.prc127,
4589 			"65-127 byte frames received");
4590 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4591 			CTLFLAG_RD, &sc->stats.prc255,
4592 			"128-255 byte frames received");
4593 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4594 			CTLFLAG_RD, &sc->stats.prc511,
4595 			"256-511 byte frames received");
4596 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4597 			CTLFLAG_RD, &sc->stats.prc1023,
4598 			"512-1023 byte frames received");
4599 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4600 			CTLFLAG_RD, &sc->stats.prc1522,
4601 			"1023-1522 byte frames received");
4602 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4603 			CTLFLAG_RD, &sc->stats.gorc,
4604 			"Good Octets Received");
4605 
4606 	/* Packet Transmission Stats */
4607 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4608 			CTLFLAG_RD, &sc->stats.gotc,
4609 			"Good Octets Transmitted");
4610 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4611 			CTLFLAG_RD, &sc->stats.tpt,
4612 			"Total Packets Transmitted");
4613 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4614 			CTLFLAG_RD, &sc->stats.gptc,
4615 			"Good Packets Transmitted");
4616 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4617 			CTLFLAG_RD, &sc->stats.bptc,
4618 			"Broadcast Packets Transmitted");
4619 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4620 			CTLFLAG_RD, &sc->stats.mptc,
4621 			"Multicast Packets Transmitted");
4622 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4623 			CTLFLAG_RD, &sc->stats.ptc64,
4624 			"64 byte frames transmitted ");
4625 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4626 			CTLFLAG_RD, &sc->stats.ptc127,
4627 			"65-127 byte frames transmitted");
4628 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4629 			CTLFLAG_RD, &sc->stats.ptc255,
4630 			"128-255 byte frames transmitted");
4631 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4632 			CTLFLAG_RD, &sc->stats.ptc511,
4633 			"256-511 byte frames transmitted");
4634 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4635 			CTLFLAG_RD, &sc->stats.ptc1023,
4636 			"512-1023 byte frames transmitted");
4637 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4638 			CTLFLAG_RD, &sc->stats.ptc1522,
4639 			"1024-1522 byte frames transmitted");
4640 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4641 			CTLFLAG_RD, &sc->stats.tsctc,
4642 			"TSO Contexts Transmitted");
4643 	SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4644 			CTLFLAG_RD, &sc->stats.tsctfc,
4645 			"TSO Contexts Failed");
4646 
4647 
4648 	/* Interrupt Stats */
4649 
4650 	int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4651 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4652 	int_list = SYSCTL_CHILDREN(int_node);
4653 
4654 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4655 			CTLFLAG_RD, &sc->stats.iac,
4656 			"Interrupt Assertion Count");
4657 
4658 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4659 			CTLFLAG_RD, &sc->stats.icrxptc,
4660 			"Interrupt Cause Rx Pkt Timer Expire Count");
4661 
4662 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4663 			CTLFLAG_RD, &sc->stats.icrxatc,
4664 			"Interrupt Cause Rx Abs Timer Expire Count");
4665 
4666 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4667 			CTLFLAG_RD, &sc->stats.ictxptc,
4668 			"Interrupt Cause Tx Pkt Timer Expire Count");
4669 
4670 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4671 			CTLFLAG_RD, &sc->stats.ictxatc,
4672 			"Interrupt Cause Tx Abs Timer Expire Count");
4673 
4674 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4675 			CTLFLAG_RD, &sc->stats.ictxqec,
4676 			"Interrupt Cause Tx Queue Empty Count");
4677 
4678 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4679 			CTLFLAG_RD, &sc->stats.ictxqmtc,
4680 			"Interrupt Cause Tx Queue Min Thresh Count");
4681 
4682 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4683 			CTLFLAG_RD, &sc->stats.icrxdmtc,
4684 			"Interrupt Cause Rx Desc Min Thresh Count");
4685 
4686 	SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4687 			CTLFLAG_RD, &sc->stats.icrxoc,
4688 			"Interrupt Cause Receiver Overrun Count");
4689 }
4690 
4691 static void
4692 em_fw_version_locked(if_ctx_t ctx)
4693 {
4694 	struct e1000_softc *sc = iflib_get_softc(ctx);
4695 	struct e1000_hw *hw = &sc->hw;
4696 	struct e1000_fw_version *fw_ver = &sc->fw_ver;
4697 	uint16_t eep = 0;
4698 
4699 	/*
4700 	 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the
4701 	 * NVM locking model, so we do it in em_if_attach_pre() and store the
4702 	 * info in the softc
4703 	 */
4704 	ASSERT_CTX_LOCK_HELD(hw);
4705 
4706 	*fw_ver = (struct e1000_fw_version){0};
4707 
4708 	if (hw->mac.type >= igb_mac_min) {
4709 		/*
4710 		 * Use the Shared Code for igb(4)
4711 		 */
4712 		e1000_get_fw_version(hw, fw_ver);
4713 	} else {
4714 		/*
4715 		 * Otherwise, EEPROM version should be present on (almost?) all
4716 		 * devices here
4717 		 */
4718 		if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) {
4719 			INIT_DEBUGOUT("can't get EEPROM version");
4720 			return;
4721 		}
4722 
4723 		fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
4724 		fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
4725 		fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK);
4726 	}
4727 }
4728 
4729 static void
4730 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf)
4731 {
4732 	const char *space = "";
4733 
4734 	if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) {
4735 		sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major,
4736 			    fw_ver->eep_minor, fw_ver->eep_build);
4737 		space = " ";
4738 	}
4739 
4740 	if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) {
4741 		sbuf_printf(buf, "%sNVM V%d.%d imgtype%d",
4742 			    space, fw_ver->invm_major, fw_ver->invm_minor,
4743 			    fw_ver->invm_img_type);
4744 		space = " ";
4745 	}
4746 
4747 	if (fw_ver->or_valid) {
4748 		sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
4749 			    space, fw_ver->or_major, fw_ver->or_build,
4750 			    fw_ver->or_patch);
4751 		space = " ";
4752 	}
4753 
4754 	if (fw_ver->etrack_id)
4755 		sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id);
4756 }
4757 
4758 static void
4759 em_print_fw_version(struct e1000_softc *sc )
4760 {
4761 	device_t dev = sc->dev;
4762 	struct sbuf *buf;
4763 	int error = 0;
4764 
4765 	buf = sbuf_new_auto();
4766 	if (!buf) {
4767 		device_printf(dev, "Could not allocate sbuf for output.\n");
4768 		return;
4769 	}
4770 
4771 	em_sbuf_fw_version(&sc->fw_ver, buf);
4772 
4773 	error = sbuf_finish(buf);
4774 	if (error)
4775 		device_printf(dev, "Error finishing sbuf: %d\n", error);
4776 	else if (sbuf_len(buf))
4777 		device_printf(dev, "%s\n", sbuf_data(buf));
4778 
4779 	sbuf_delete(buf);
4780 }
4781 
4782 static int
4783 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
4784 {
4785 	struct e1000_softc *sc = (struct e1000_softc *)arg1;
4786 	device_t dev = sc->dev;
4787 	struct sbuf *buf;
4788 	int error = 0;
4789 
4790 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
4791 	if (!buf) {
4792 		device_printf(dev, "Could not allocate sbuf for output.\n");
4793 		return (ENOMEM);
4794 	}
4795 
4796 	em_sbuf_fw_version(&sc->fw_ver, buf);
4797 
4798 	error = sbuf_finish(buf);
4799 	if (error)
4800 		device_printf(dev, "Error finishing sbuf: %d\n", error);
4801 
4802 	sbuf_delete(buf);
4803 
4804 	return (0);
4805 }
4806 
4807 /**********************************************************************
4808  *
4809  *  This routine provides a way to dump out the adapter eeprom,
4810  *  often a useful debug/service tool. This only dumps the first
4811  *  32 words, stuff that matters is in that extent.
4812  *
4813  **********************************************************************/
4814 static int
4815 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4816 {
4817 	struct e1000_softc *sc = (struct e1000_softc *)arg1;
4818 	int error;
4819 	int result;
4820 
4821 	result = -1;
4822 	error = sysctl_handle_int(oidp, &result, 0, req);
4823 
4824 	if (error || !req->newptr)
4825 		return (error);
4826 
4827 	/*
4828 	 * This value will cause a hex dump of the
4829 	 * first 32 16-bit words of the EEPROM to
4830 	 * the screen.
4831 	 */
4832 	if (result == 1)
4833 		em_print_nvm_info(sc);
4834 
4835 	return (error);
4836 }
4837 
4838 static void
4839 em_print_nvm_info(struct e1000_softc *sc)
4840 {
4841 	struct e1000_hw *hw = &sc->hw;
4842 	struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx);
4843 	u16 eeprom_data;
4844 	int i, j, row = 0;
4845 
4846 	/* Its a bit crude, but it gets the job done */
4847 	printf("\nInterface EEPROM Dump:\n");
4848 	printf("Offset\n0x0000  ");
4849 
4850 	/* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */
4851 	sx_xlock(iflib_ctx_lock);
4852 	ASSERT_CTX_LOCK_HELD(hw);
4853 	for (i = 0, j = 0; i < 32; i++, j++) {
4854 		if (j == 8) { /* Make the offset block */
4855 			j = 0; ++row;
4856 			printf("\n0x00%x0  ",row);
4857 		}
4858 		e1000_read_nvm(hw, i, 1, &eeprom_data);
4859 		printf("%04x ", eeprom_data);
4860 	}
4861 	sx_xunlock(iflib_ctx_lock);
4862 	printf("\n");
4863 }
4864 
4865 static int
4866 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4867 {
4868 	struct em_int_delay_info *info;
4869 	struct e1000_softc *sc;
4870 	u32 regval;
4871 	int error, usecs, ticks;
4872 
4873 	info = (struct em_int_delay_info *) arg1;
4874 	usecs = info->value;
4875 	error = sysctl_handle_int(oidp, &usecs, 0, req);
4876 	if (error != 0 || req->newptr == NULL)
4877 		return (error);
4878 	if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4879 		return (EINVAL);
4880 	info->value = usecs;
4881 	ticks = EM_USECS_TO_TICKS(usecs);
4882 	if (info->offset == E1000_ITR)	/* units are 256ns here */
4883 		ticks *= 4;
4884 
4885 	sc = info->sc;
4886 
4887 	regval = E1000_READ_OFFSET(&sc->hw, info->offset);
4888 	regval = (regval & ~0xffff) | (ticks & 0xffff);
4889 	/* Handle a few special cases. */
4890 	switch (info->offset) {
4891 	case E1000_RDTR:
4892 		break;
4893 	case E1000_TIDV:
4894 		if (ticks == 0) {
4895 			sc->txd_cmd &= ~E1000_TXD_CMD_IDE;
4896 			/* Don't write 0 into the TIDV register. */
4897 			regval++;
4898 		} else
4899 			sc->txd_cmd |= E1000_TXD_CMD_IDE;
4900 		break;
4901 	}
4902 	E1000_WRITE_OFFSET(&sc->hw, info->offset, regval);
4903 	return (0);
4904 }
4905 
4906 static void
4907 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name,
4908 	const char *description, struct em_int_delay_info *info,
4909 	int offset, int value)
4910 {
4911 	info->sc = sc;
4912 	info->offset = offset;
4913 	info->value = value;
4914 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
4915 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
4916 	    OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4917 	    info, 0, em_sysctl_int_delay, "I", description);
4918 }
4919 
4920 /*
4921  * Set flow control using sysctl:
4922  * Flow control values:
4923  *      0 - off
4924  *      1 - rx pause
4925  *      2 - tx pause
4926  *      3 - full
4927  */
4928 static int
4929 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4930 {
4931 	int error;
4932 	static int input = 3; /* default is full */
4933 	struct e1000_softc	*sc = (struct e1000_softc *) arg1;
4934 
4935 	error = sysctl_handle_int(oidp, &input, 0, req);
4936 
4937 	if ((error) || (req->newptr == NULL))
4938 		return (error);
4939 
4940 	if (input == sc->fc) /* no change? */
4941 		return (error);
4942 
4943 	switch (input) {
4944 	case e1000_fc_rx_pause:
4945 	case e1000_fc_tx_pause:
4946 	case e1000_fc_full:
4947 	case e1000_fc_none:
4948 		sc->hw.fc.requested_mode = input;
4949 		sc->fc = input;
4950 		break;
4951 	default:
4952 		/* Do nothing */
4953 		return (error);
4954 	}
4955 
4956 	sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
4957 	e1000_force_mac_fc(&sc->hw);
4958 	return (error);
4959 }
4960 
4961 /*
4962  * Manage Energy Efficient Ethernet:
4963  * Control values:
4964  *     0/1 - enabled/disabled
4965  */
4966 static int
4967 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4968 {
4969 	struct e1000_softc *sc = (struct e1000_softc *) arg1;
4970 	int error, value;
4971 
4972 	value = sc->hw.dev_spec.ich8lan.eee_disable;
4973 	error = sysctl_handle_int(oidp, &value, 0, req);
4974 	if (error || req->newptr == NULL)
4975 		return (error);
4976 	sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4977 	em_if_init(sc->ctx);
4978 
4979 	return (0);
4980 }
4981 
4982 static int
4983 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4984 {
4985 	struct e1000_softc *sc;
4986 	int error;
4987 	int result;
4988 
4989 	result = -1;
4990 	error = sysctl_handle_int(oidp, &result, 0, req);
4991 
4992 	if (error || !req->newptr)
4993 		return (error);
4994 
4995 	if (result == 1) {
4996 		sc = (struct e1000_softc *) arg1;
4997 		em_print_debug_info(sc);
4998 	}
4999 
5000 	return (error);
5001 }
5002 
5003 static int
5004 em_get_rs(SYSCTL_HANDLER_ARGS)
5005 {
5006 	struct e1000_softc *sc = (struct e1000_softc *) arg1;
5007 	int error;
5008 	int result;
5009 
5010 	result = 0;
5011 	error = sysctl_handle_int(oidp, &result, 0, req);
5012 
5013 	if (error || !req->newptr || result != 1)
5014 		return (error);
5015 	em_dump_rs(sc);
5016 
5017 	return (error);
5018 }
5019 
5020 static void
5021 em_if_debug(if_ctx_t ctx)
5022 {
5023 	em_dump_rs(iflib_get_softc(ctx));
5024 }
5025 
5026 /*
5027  * This routine is meant to be fluid, add whatever is
5028  * needed for debugging a problem.  -jfv
5029  */
5030 static void
5031 em_print_debug_info(struct e1000_softc *sc)
5032 {
5033 	device_t dev = iflib_get_dev(sc->ctx);
5034 	if_t ifp = iflib_get_ifp(sc->ctx);
5035 	struct tx_ring *txr = &sc->tx_queues->txr;
5036 	struct rx_ring *rxr = &sc->rx_queues->rxr;
5037 
5038 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5039 		printf("Interface is RUNNING ");
5040 	else
5041 		printf("Interface is NOT RUNNING\n");
5042 
5043 	if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
5044 		printf("and INACTIVE\n");
5045 	else
5046 		printf("and ACTIVE\n");
5047 
5048 	for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
5049 		device_printf(dev, "TX Queue %d ------\n", i);
5050 		device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
5051 			E1000_READ_REG(&sc->hw, E1000_TDH(i)),
5052 			E1000_READ_REG(&sc->hw, E1000_TDT(i)));
5053 
5054 	}
5055 	for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
5056 		device_printf(dev, "RX Queue %d ------\n", j);
5057 		device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
5058 			E1000_READ_REG(&sc->hw, E1000_RDH(j)),
5059 			E1000_READ_REG(&sc->hw, E1000_RDT(j)));
5060 	}
5061 }
5062 
5063 /*
5064  * 82574 only:
5065  * Write a new value to the EEPROM increasing the number of MSI-X
5066  * vectors from 3 to 5, for proper multiqueue support.
5067  */
5068 static void
5069 em_enable_vectors_82574(if_ctx_t ctx)
5070 {
5071 	struct e1000_softc *sc = iflib_get_softc(ctx);
5072 	struct e1000_hw *hw = &sc->hw;
5073 	device_t dev = iflib_get_dev(ctx);
5074 	u16 edata;
5075 
5076 	e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
5077 	if (bootverbose)
5078 		device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
5079 	if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
5080 		device_printf(dev, "Writing to eeprom: increasing "
5081 		    "reported MSI-X vectors from 3 to 5...\n");
5082 		edata &= ~(EM_NVM_MSIX_N_MASK);
5083 		edata |= 4 << EM_NVM_MSIX_N_SHIFT;
5084 		e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
5085 		e1000_update_nvm_checksum(hw);
5086 		device_printf(dev, "Writing to eeprom: done\n");
5087 	}
5088 }
5089