1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 167 /* required last entry */ 168 PVID_END 169 }; 170 171 static pci_vendor_info_t igb_vendor_info_array[] = 172 { 173 /* Intel(R) PRO/1000 Network Connection - em */ 174 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 /********************************************************************* 218 * Function prototypes 219 *********************************************************************/ 220 static void *em_register(device_t dev); 221 static void *igb_register(device_t dev); 222 static int em_if_attach_pre(if_ctx_t ctx); 223 static int em_if_attach_post(if_ctx_t ctx); 224 static int em_if_detach(if_ctx_t ctx); 225 static int em_if_shutdown(if_ctx_t ctx); 226 static int em_if_suspend(if_ctx_t ctx); 227 static int em_if_resume(if_ctx_t ctx); 228 229 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 230 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 231 static void em_if_queues_free(if_ctx_t ctx); 232 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 234 static void em_if_init(if_ctx_t ctx); 235 static void em_if_stop(if_ctx_t ctx); 236 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 237 static int em_if_media_change(if_ctx_t ctx); 238 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 239 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 240 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 241 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 242 243 static void em_identify_hardware(if_ctx_t ctx); 244 static int em_allocate_pci_resources(if_ctx_t ctx); 245 static void em_free_pci_resources(if_ctx_t ctx); 246 static void em_reset(if_ctx_t ctx); 247 static int em_setup_interface(if_ctx_t ctx); 248 static int em_setup_msix(if_ctx_t ctx); 249 250 static void em_initialize_transmit_unit(if_ctx_t ctx); 251 static void em_initialize_receive_unit(if_ctx_t ctx); 252 253 static void em_if_enable_intr(if_ctx_t ctx); 254 static void em_if_disable_intr(if_ctx_t ctx); 255 static int em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 256 static void em_if_multi_set(if_ctx_t ctx); 257 static void em_if_update_admin_status(if_ctx_t ctx); 258 static void em_update_stats_counters(struct adapter *); 259 static void em_add_hw_stats(struct adapter *adapter); 260 static int em_if_set_promisc(if_ctx_t ctx, int flags); 261 static void em_setup_vlan_hw_support(struct adapter *); 262 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 263 static void em_print_nvm_info(struct adapter *); 264 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 265 static void em_print_debug_info(struct adapter *); 266 static int em_is_valid_ether_addr(u8 *); 267 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 268 static void em_add_int_delay_sysctl(struct adapter *, const char *, 269 const char *, struct em_int_delay_info *, int, int); 270 /* Management and WOL Support */ 271 static void em_init_manageability(struct adapter *); 272 static void em_release_manageability(struct adapter *); 273 static void em_get_hw_control(struct adapter *); 274 static void em_release_hw_control(struct adapter *); 275 static void em_get_wakeup(if_ctx_t ctx); 276 static void em_enable_wakeup(if_ctx_t ctx); 277 static int em_enable_phy_wakeup(struct adapter *); 278 static void em_disable_aspm(struct adapter *); 279 280 int em_intr(void *arg); 281 static void em_disable_promisc(if_ctx_t ctx); 282 283 /* MSIX handlers */ 284 static int em_if_msix_intr_assign(if_ctx_t, int); 285 static int em_msix_link(void *); 286 static void em_handle_link(void *context); 287 288 static void em_enable_vectors_82574(if_ctx_t); 289 290 static void em_set_sysctl_value(struct adapter *, const char *, 291 const char *, int *, int); 292 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 293 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 294 static void em_if_led_func(if_ctx_t ctx, int onoff); 295 296 static void em_init_tx_ring(struct em_tx_queue *que); 297 static int em_get_regs(SYSCTL_HANDLER_ARGS); 298 299 static void lem_smartspeed(struct adapter *adapter); 300 static void igb_configure_queues(struct adapter *adapter); 301 302 303 /********************************************************************* 304 * FreeBSD Device Interface Entry Points 305 *********************************************************************/ 306 static device_method_t em_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_register, em_register), 309 DEVMETHOD(device_probe, iflib_device_probe), 310 DEVMETHOD(device_attach, iflib_device_attach), 311 DEVMETHOD(device_detach, iflib_device_detach), 312 DEVMETHOD(device_shutdown, iflib_device_shutdown), 313 DEVMETHOD(device_suspend, iflib_device_suspend), 314 DEVMETHOD(device_resume, iflib_device_resume), 315 DEVMETHOD_END 316 }; 317 318 static device_method_t igb_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_register, igb_register), 321 DEVMETHOD(device_probe, iflib_device_probe), 322 DEVMETHOD(device_attach, iflib_device_attach), 323 DEVMETHOD(device_detach, iflib_device_detach), 324 DEVMETHOD(device_shutdown, iflib_device_shutdown), 325 DEVMETHOD(device_suspend, iflib_device_suspend), 326 DEVMETHOD(device_resume, iflib_device_resume), 327 DEVMETHOD_END 328 }; 329 330 331 static driver_t em_driver = { 332 "em", em_methods, sizeof(struct adapter), 333 }; 334 335 static devclass_t em_devclass; 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 337 338 MODULE_DEPEND(em, pci, 1, 1, 1); 339 MODULE_DEPEND(em, ether, 1, 1, 1); 340 MODULE_DEPEND(em, iflib, 1, 1, 1); 341 342 static driver_t igb_driver = { 343 "igb", igb_methods, sizeof(struct adapter), 344 }; 345 346 static devclass_t igb_devclass; 347 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 348 349 MODULE_DEPEND(igb, pci, 1, 1, 1); 350 MODULE_DEPEND(igb, ether, 1, 1, 1); 351 MODULE_DEPEND(igb, iflib, 1, 1, 1); 352 353 354 static device_method_t em_if_methods[] = { 355 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 356 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 357 DEVMETHOD(ifdi_detach, em_if_detach), 358 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 359 DEVMETHOD(ifdi_suspend, em_if_suspend), 360 DEVMETHOD(ifdi_resume, em_if_resume), 361 DEVMETHOD(ifdi_init, em_if_init), 362 DEVMETHOD(ifdi_stop, em_if_stop), 363 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 364 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 365 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 366 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 367 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 368 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 369 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 370 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 371 DEVMETHOD(ifdi_media_status, em_if_media_status), 372 DEVMETHOD(ifdi_media_change, em_if_media_change), 373 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 374 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 375 DEVMETHOD(ifdi_timer, em_if_timer), 376 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 377 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 378 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 379 DEVMETHOD(ifdi_led_func, em_if_led_func), 380 DEVMETHOD(ifdi_queue_intr_enable, em_if_queue_intr_enable), 381 DEVMETHOD_END 382 }; 383 384 /* 385 * note that if (adapter->msix_mem) is replaced by: 386 * if (adapter->intr_type == IFLIB_INTR_MSIX) 387 */ 388 static driver_t em_if_driver = { 389 "em_if", em_if_methods, sizeof(struct adapter) 390 }; 391 392 /********************************************************************* 393 * Tunable default values. 394 *********************************************************************/ 395 396 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 397 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 398 #define M_TSO_LEN 66 399 400 #define MAX_INTS_PER_SEC 8000 401 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 402 403 /* Allow common code without TSO */ 404 #ifndef CSUM_TSO 405 #define CSUM_TSO 0 406 #endif 407 408 #define TSO_WORKAROUND 4 409 410 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 411 412 static int em_disable_crc_stripping = 0; 413 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 414 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 415 416 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 417 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 418 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 419 0, "Default transmit interrupt delay in usecs"); 420 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 421 0, "Default receive interrupt delay in usecs"); 422 423 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 424 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 425 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 426 &em_tx_abs_int_delay_dflt, 0, 427 "Default transmit interrupt delay limit in usecs"); 428 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 429 &em_rx_abs_int_delay_dflt, 0, 430 "Default receive interrupt delay limit in usecs"); 431 432 static int em_smart_pwr_down = FALSE; 433 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 434 0, "Set to true to leave smart power down enabled on newer adapters"); 435 436 /* Controls whether promiscuous also shows bad packets */ 437 static int em_debug_sbp = TRUE; 438 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 439 "Show bad packets in promiscuous mode"); 440 441 /* How many packets rxeof tries to clean at a time */ 442 static int em_rx_process_limit = 100; 443 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 444 &em_rx_process_limit, 0, 445 "Maximum number of received packets to process " 446 "at a time, -1 means unlimited"); 447 448 /* Energy efficient ethernet - default to OFF */ 449 static int eee_setting = 1; 450 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 451 "Enable Energy Efficient Ethernet"); 452 453 /* 454 ** Tuneable Interrupt rate 455 */ 456 static int em_max_interrupt_rate = 8000; 457 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 458 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 459 460 461 462 /* Global used in WOL setup with multiport cards */ 463 static int global_quad_port_a = 0; 464 465 extern struct if_txrx igb_txrx; 466 extern struct if_txrx em_txrx; 467 extern struct if_txrx lem_txrx; 468 469 static struct if_shared_ctx em_sctx_init = { 470 .isc_magic = IFLIB_MAGIC, 471 .isc_q_align = PAGE_SIZE, 472 .isc_tx_maxsize = EM_TSO_SIZE, 473 .isc_tx_maxsegsize = PAGE_SIZE, 474 .isc_rx_maxsize = MJUM9BYTES, 475 .isc_rx_nsegments = 1, 476 .isc_rx_maxsegsize = MJUM9BYTES, 477 .isc_nfl = 1, 478 .isc_nrxqs = 1, 479 .isc_ntxqs = 1, 480 .isc_admin_intrcnt = 1, 481 .isc_vendor_info = em_vendor_info_array, 482 .isc_driver_version = em_driver_version, 483 .isc_driver = &em_if_driver, 484 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 485 486 .isc_nrxd_min = {EM_MIN_RXD}, 487 .isc_ntxd_min = {EM_MIN_TXD}, 488 .isc_nrxd_max = {EM_MAX_RXD}, 489 .isc_ntxd_max = {EM_MAX_TXD}, 490 .isc_nrxd_default = {EM_DEFAULT_RXD}, 491 .isc_ntxd_default = {EM_DEFAULT_TXD}, 492 }; 493 494 if_shared_ctx_t em_sctx = &em_sctx_init; 495 496 497 static struct if_shared_ctx igb_sctx_init = { 498 .isc_magic = IFLIB_MAGIC, 499 .isc_q_align = PAGE_SIZE, 500 .isc_tx_maxsize = EM_TSO_SIZE, 501 .isc_tx_maxsegsize = PAGE_SIZE, 502 .isc_rx_maxsize = MJUM9BYTES, 503 .isc_rx_nsegments = 1, 504 .isc_rx_maxsegsize = MJUM9BYTES, 505 .isc_nfl = 1, 506 .isc_nrxqs = 1, 507 .isc_ntxqs = 1, 508 .isc_admin_intrcnt = 1, 509 .isc_vendor_info = igb_vendor_info_array, 510 .isc_driver_version = em_driver_version, 511 .isc_driver = &em_if_driver, 512 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 513 514 .isc_nrxd_min = {EM_MIN_RXD}, 515 .isc_ntxd_min = {EM_MIN_TXD}, 516 .isc_nrxd_max = {EM_MAX_RXD}, 517 .isc_ntxd_max = {EM_MAX_TXD}, 518 .isc_nrxd_default = {EM_DEFAULT_RXD}, 519 .isc_ntxd_default = {EM_DEFAULT_TXD}, 520 }; 521 522 if_shared_ctx_t igb_sctx = &igb_sctx_init; 523 524 /***************************************************************** 525 * 526 * Dump Registers 527 * 528 ****************************************************************/ 529 #define IGB_REGS_LEN 739 530 531 static int em_get_regs(SYSCTL_HANDLER_ARGS) 532 { 533 struct adapter *adapter = (struct adapter *)arg1; 534 struct e1000_hw *hw = &adapter->hw; 535 536 struct sbuf *sb; 537 u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT); 538 int rc; 539 540 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 541 542 rc = sysctl_wire_old_buffer(req, 0); 543 MPASS(rc == 0); 544 if (rc != 0) 545 return (rc); 546 547 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 548 MPASS(sb != NULL); 549 if (sb == NULL) 550 return (ENOMEM); 551 552 /* General Registers */ 553 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 554 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 555 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 556 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 557 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 558 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 559 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 560 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 561 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 562 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 563 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 564 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 565 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 566 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 567 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 568 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 569 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 570 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 571 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 572 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 573 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 574 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 575 576 sbuf_printf(sb, "General Registers\n"); 577 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 578 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 579 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 580 581 sbuf_printf(sb, "Interrupt Registers\n"); 582 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 583 584 sbuf_printf(sb, "RX Registers\n"); 585 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 586 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 587 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 588 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 589 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 590 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 591 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 592 593 sbuf_printf(sb, "TX Registers\n"); 594 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 595 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 596 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 597 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 598 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 599 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 600 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 601 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 602 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 603 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 604 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 605 606 #ifdef DUMP_DESCS 607 { 608 if_softc_ctx_t scctx = adapter->shared; 609 struct rx_ring *rxr = &rx_que->rxr; 610 struct tx_ring *txr = &tx_que->txr; 611 int ntxd = scctx->isc_ntxd[0]; 612 int nrxd = scctx->isc_nrxd[0]; 613 int j; 614 615 for (j = 0; j < nrxd; j++) { 616 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 617 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 618 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 619 } 620 621 for (j = 0; j < min(ntxd, 256); j++) { 622 struct em_txbuffer *buf = &txr->tx_buffers[j]; 623 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 624 625 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 626 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 627 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 628 629 } 630 } 631 #endif 632 633 rc = sbuf_finish(sb); 634 sbuf_delete(sb); 635 return(rc); 636 } 637 638 static void * 639 em_register(device_t dev) 640 { 641 return (em_sctx); 642 } 643 644 static void * 645 igb_register(device_t dev) 646 { 647 return (igb_sctx); 648 } 649 650 static void 651 em_init_tx_ring(struct em_tx_queue *que) 652 { 653 struct adapter *sc = que->adapter; 654 if_softc_ctx_t scctx = sc->shared; 655 struct tx_ring *txr = &que->txr; 656 struct em_txbuffer *tx_buffer; 657 658 tx_buffer = txr->tx_buffers; 659 for (int i = 0; i < scctx->isc_ntxd[0]; i++, tx_buffer++) { 660 tx_buffer->eop = -1; 661 } 662 } 663 664 static int 665 em_set_num_queues(if_ctx_t ctx) 666 { 667 struct adapter *adapter = iflib_get_softc(ctx); 668 int maxqueues; 669 670 /* Sanity check based on HW */ 671 switch (adapter->hw.mac.type) { 672 case e1000_82576: 673 case e1000_82580: 674 case e1000_i350: 675 case e1000_i354: 676 maxqueues = 8; 677 break; 678 case e1000_i210: 679 case e1000_82575: 680 maxqueues = 4; 681 break; 682 case e1000_i211: 683 case e1000_82574: 684 maxqueues = 2; 685 break; 686 default: 687 maxqueues = 1; 688 break; 689 } 690 691 return (maxqueues); 692 } 693 694 695 #define EM_CAPS \ 696 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 697 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 698 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 699 700 #define IGB_CAPS \ 701 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 702 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 703 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 704 705 /********************************************************************* 706 * Device initialization routine 707 * 708 * The attach entry point is called when the driver is being loaded. 709 * This routine identifies the type of hardware, allocates all resources 710 * and initializes the hardware. 711 * 712 * return 0 on success, positive on failure 713 *********************************************************************/ 714 715 static int 716 em_if_attach_pre(if_ctx_t ctx) 717 { 718 struct adapter *adapter; 719 if_softc_ctx_t scctx; 720 device_t dev; 721 struct e1000_hw *hw; 722 int error = 0; 723 724 INIT_DEBUGOUT("em_if_attach_pre begin"); 725 dev = iflib_get_dev(ctx); 726 adapter = iflib_get_softc(ctx); 727 728 if (resource_disabled("em", device_get_unit(dev))) { 729 device_printf(dev, "Disabled by device hint\n"); 730 return (ENXIO); 731 } 732 733 adapter->ctx = ctx; 734 adapter->dev = adapter->osdep.dev = dev; 735 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 736 adapter->media = iflib_get_media(ctx); 737 hw = &adapter->hw; 738 739 adapter->tx_process_limit = scctx->isc_ntxd[0]; 740 741 /* SYSCTL stuff */ 742 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 743 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 744 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 745 em_sysctl_nvm_info, "I", "NVM Information"); 746 747 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 748 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 749 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 750 em_sysctl_debug_info, "I", "Debug Information"); 751 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 754 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 755 em_set_flowcntl, "I", "Flow Control"); 756 757 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 759 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 760 em_get_regs, "A", "Dump Registers"); 761 762 /* Determine hardware and mac info */ 763 em_identify_hardware(ctx); 764 765 /* Set isc_msix_bar */ 766 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 767 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 768 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 769 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 770 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 771 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 772 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 773 774 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 775 776 777 if (adapter->hw.mac.type >= igb_mac_min) { 778 int try_second_bar; 779 780 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 781 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 782 scctx->isc_txrx = &igb_txrx; 783 scctx->isc_capenable = IGB_CAPS; 784 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 785 | CSUM_IP6_UDP | CSUM_IP6_TCP; 786 if (adapter->hw.mac.type != e1000_82575) 787 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 788 789 /* 790 ** Some new devices, as with ixgbe, now may 791 ** use a different BAR, so we need to keep 792 ** track of which is used. 793 */ 794 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 795 if (try_second_bar == 0) 796 scctx->isc_msix_bar += 4; 797 798 } else if (adapter->hw.mac.type >= em_mac_min) { 799 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 800 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 801 scctx->isc_txrx = &em_txrx; 802 scctx->isc_capenable = EM_CAPS; 803 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 804 } else { 805 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 806 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 807 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 808 scctx->isc_txrx = &lem_txrx; 809 scctx->isc_capenable = EM_CAPS; 810 if (adapter->hw.mac.type < e1000_82543) 811 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 812 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 813 scctx->isc_msix_bar = 0; 814 } 815 816 /* Setup PCI resources */ 817 if (em_allocate_pci_resources(ctx)) { 818 device_printf(dev, "Allocation of PCI resources failed\n"); 819 error = ENXIO; 820 goto err_pci; 821 } 822 823 /* 824 ** For ICH8 and family we need to 825 ** map the flash memory, and this 826 ** must happen after the MAC is 827 ** identified 828 */ 829 if ((hw->mac.type == e1000_ich8lan) || 830 (hw->mac.type == e1000_ich9lan) || 831 (hw->mac.type == e1000_ich10lan) || 832 (hw->mac.type == e1000_pchlan) || 833 (hw->mac.type == e1000_pch2lan) || 834 (hw->mac.type == e1000_pch_lpt)) { 835 int rid = EM_BAR_TYPE_FLASH; 836 adapter->flash = bus_alloc_resource_any(dev, 837 SYS_RES_MEMORY, &rid, RF_ACTIVE); 838 if (adapter->flash == NULL) { 839 device_printf(dev, "Mapping of Flash failed\n"); 840 error = ENXIO; 841 goto err_pci; 842 } 843 /* This is used in the shared code */ 844 hw->flash_address = (u8 *)adapter->flash; 845 adapter->osdep.flash_bus_space_tag = 846 rman_get_bustag(adapter->flash); 847 adapter->osdep.flash_bus_space_handle = 848 rman_get_bushandle(adapter->flash); 849 } 850 /* 851 ** In the new SPT device flash is not a 852 ** separate BAR, rather it is also in BAR0, 853 ** so use the same tag and an offset handle for the 854 ** FLASH read/write macros in the shared code. 855 */ 856 else if (hw->mac.type == e1000_pch_spt) { 857 adapter->osdep.flash_bus_space_tag = 858 adapter->osdep.mem_bus_space_tag; 859 adapter->osdep.flash_bus_space_handle = 860 adapter->osdep.mem_bus_space_handle 861 + E1000_FLASH_BASE_ADDR; 862 } 863 864 /* Do Shared Code initialization */ 865 error = e1000_setup_init_funcs(hw, TRUE); 866 if (error) { 867 device_printf(dev, "Setup of Shared code failed, error %d\n", 868 error); 869 error = ENXIO; 870 goto err_pci; 871 } 872 873 em_setup_msix(ctx); 874 e1000_get_bus_info(hw); 875 876 /* Set up some sysctls for the tunable interrupt delays */ 877 em_add_int_delay_sysctl(adapter, "rx_int_delay", 878 "receive interrupt delay in usecs", &adapter->rx_int_delay, 879 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 880 em_add_int_delay_sysctl(adapter, "tx_int_delay", 881 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 882 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 883 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 884 "receive interrupt delay limit in usecs", 885 &adapter->rx_abs_int_delay, 886 E1000_REGISTER(hw, E1000_RADV), 887 em_rx_abs_int_delay_dflt); 888 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 889 "transmit interrupt delay limit in usecs", 890 &adapter->tx_abs_int_delay, 891 E1000_REGISTER(hw, E1000_TADV), 892 em_tx_abs_int_delay_dflt); 893 em_add_int_delay_sysctl(adapter, "itr", 894 "interrupt delay limit in usecs/4", 895 &adapter->tx_itr, 896 E1000_REGISTER(hw, E1000_ITR), 897 DEFAULT_ITR); 898 899 /* Sysctl for limiting the amount of work done in the taskqueue */ 900 em_set_sysctl_value(adapter, "rx_processing_limit", 901 "max number of rx packets to process", &adapter->rx_process_limit, 902 em_rx_process_limit); 903 904 hw->mac.autoneg = DO_AUTO_NEG; 905 hw->phy.autoneg_wait_to_complete = FALSE; 906 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 907 908 if (adapter->hw.mac.type < em_mac_min) { 909 e1000_init_script_state_82541(&adapter->hw, TRUE); 910 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 911 } 912 /* Copper options */ 913 if (hw->phy.media_type == e1000_media_type_copper) { 914 hw->phy.mdix = AUTO_ALL_MODES; 915 hw->phy.disable_polarity_correction = FALSE; 916 hw->phy.ms_type = EM_MASTER_SLAVE; 917 } 918 919 /* 920 * Set the frame limits assuming 921 * standard ethernet sized frames. 922 */ 923 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 924 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 925 926 /* 927 * This controls when hardware reports transmit completion 928 * status. 929 */ 930 hw->mac.report_tx_early = 1; 931 932 /* Allocate multicast array memory. */ 933 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 934 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 935 if (adapter->mta == NULL) { 936 device_printf(dev, "Can not allocate multicast setup array\n"); 937 error = ENOMEM; 938 goto err_late; 939 } 940 941 /* Check SOL/IDER usage */ 942 if (e1000_check_reset_block(hw)) 943 device_printf(dev, "PHY reset is blocked" 944 " due to SOL/IDER session.\n"); 945 946 /* Sysctl for setting Energy Efficient Ethernet */ 947 hw->dev_spec.ich8lan.eee_disable = eee_setting; 948 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 949 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 950 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 951 adapter, 0, em_sysctl_eee, "I", 952 "Disable Energy Efficient Ethernet"); 953 954 /* 955 ** Start from a known state, this is 956 ** important in reading the nvm and 957 ** mac from that. 958 */ 959 e1000_reset_hw(hw); 960 961 /* Make sure we have a good EEPROM before we read from it */ 962 if (e1000_validate_nvm_checksum(hw) < 0) { 963 /* 964 ** Some PCI-E parts fail the first check due to 965 ** the link being in sleep state, call it again, 966 ** if it fails a second time its a real issue. 967 */ 968 if (e1000_validate_nvm_checksum(hw) < 0) { 969 device_printf(dev, 970 "The EEPROM Checksum Is Not Valid\n"); 971 error = EIO; 972 goto err_late; 973 } 974 } 975 976 /* Copy the permanent MAC address out of the EEPROM */ 977 if (e1000_read_mac_addr(hw) < 0) { 978 device_printf(dev, "EEPROM read error while reading MAC" 979 " address\n"); 980 error = EIO; 981 goto err_late; 982 } 983 984 if (!em_is_valid_ether_addr(hw->mac.addr)) { 985 device_printf(dev, "Invalid MAC address\n"); 986 error = EIO; 987 goto err_late; 988 } 989 990 /* Disable ULP support */ 991 e1000_disable_ulp_lpt_lp(hw, TRUE); 992 993 /* 994 * Get Wake-on-Lan and Management info for later use 995 */ 996 em_get_wakeup(ctx); 997 998 iflib_set_mac(ctx, hw->mac.addr); 999 1000 return (0); 1001 1002 err_late: 1003 em_release_hw_control(adapter); 1004 err_pci: 1005 em_free_pci_resources(ctx); 1006 free(adapter->mta, M_DEVBUF); 1007 1008 return (error); 1009 } 1010 1011 static int 1012 em_if_attach_post(if_ctx_t ctx) 1013 { 1014 struct adapter *adapter = iflib_get_softc(ctx); 1015 struct e1000_hw *hw = &adapter->hw; 1016 int error = 0; 1017 1018 /* Setup OS specific network interface */ 1019 error = em_setup_interface(ctx); 1020 if (error != 0) { 1021 goto err_late; 1022 } 1023 1024 em_reset(ctx); 1025 1026 /* Initialize statistics */ 1027 em_update_stats_counters(adapter); 1028 hw->mac.get_link_status = 1; 1029 em_if_update_admin_status(ctx); 1030 em_add_hw_stats(adapter); 1031 1032 /* Non-AMT based hardware can now take control from firmware */ 1033 if (adapter->has_manage && !adapter->has_amt) 1034 em_get_hw_control(adapter); 1035 1036 INIT_DEBUGOUT("em_if_attach_post: end"); 1037 1038 return (error); 1039 1040 err_late: 1041 em_release_hw_control(adapter); 1042 em_free_pci_resources(ctx); 1043 em_if_queues_free(ctx); 1044 free(adapter->mta, M_DEVBUF); 1045 1046 return (error); 1047 } 1048 1049 /********************************************************************* 1050 * Device removal routine 1051 * 1052 * The detach entry point is called when the driver is being removed. 1053 * This routine stops the adapter and deallocates all the resources 1054 * that were allocated for driver operation. 1055 * 1056 * return 0 on success, positive on failure 1057 *********************************************************************/ 1058 1059 static int 1060 em_if_detach(if_ctx_t ctx) 1061 { 1062 struct adapter *adapter = iflib_get_softc(ctx); 1063 1064 INIT_DEBUGOUT("em_detach: begin"); 1065 1066 e1000_phy_hw_reset(&adapter->hw); 1067 1068 em_release_manageability(adapter); 1069 em_release_hw_control(adapter); 1070 em_free_pci_resources(ctx); 1071 1072 return (0); 1073 } 1074 1075 /********************************************************************* 1076 * 1077 * Shutdown entry point 1078 * 1079 **********************************************************************/ 1080 1081 static int 1082 em_if_shutdown(if_ctx_t ctx) 1083 { 1084 return em_if_suspend(ctx); 1085 } 1086 1087 /* 1088 * Suspend/resume device methods. 1089 */ 1090 static int 1091 em_if_suspend(if_ctx_t ctx) 1092 { 1093 struct adapter *adapter = iflib_get_softc(ctx); 1094 1095 em_release_manageability(adapter); 1096 em_release_hw_control(adapter); 1097 em_enable_wakeup(ctx); 1098 return (0); 1099 } 1100 1101 static int 1102 em_if_resume(if_ctx_t ctx) 1103 { 1104 struct adapter *adapter = iflib_get_softc(ctx); 1105 1106 if (adapter->hw.mac.type == e1000_pch2lan) 1107 e1000_resume_workarounds_pchlan(&adapter->hw); 1108 em_if_init(ctx); 1109 em_init_manageability(adapter); 1110 1111 return(0); 1112 } 1113 1114 static int 1115 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1116 { 1117 int max_frame_size; 1118 struct adapter *adapter = iflib_get_softc(ctx); 1119 struct ifnet *ifp = iflib_get_ifp(ctx); 1120 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1121 1122 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1123 1124 switch (adapter->hw.mac.type) { 1125 case e1000_82571: 1126 case e1000_82572: 1127 case e1000_ich9lan: 1128 case e1000_ich10lan: 1129 case e1000_pch2lan: 1130 case e1000_pch_lpt: 1131 case e1000_pch_spt: 1132 case e1000_82574: 1133 case e1000_82583: 1134 case e1000_80003es2lan: /* 9K Jumbo Frame size */ 1135 max_frame_size = 9234; 1136 break; 1137 case e1000_pchlan: 1138 max_frame_size = 4096; 1139 break; 1140 /* Adapters that do not support jumbo frames */ 1141 case e1000_ich8lan: 1142 max_frame_size = ETHER_MAX_LEN; 1143 break; 1144 default: 1145 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1146 } 1147 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1148 return (EINVAL); 1149 } 1150 1151 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1152 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 1153 return (0); 1154 } 1155 1156 /********************************************************************* 1157 * Init entry point 1158 * 1159 * This routine is used in two ways. It is used by the stack as 1160 * init entry point in network interface structure. It is also used 1161 * by the driver as a hw/sw initialization routine to get to a 1162 * consistent state. 1163 * 1164 * return 0 on success, positive on failure 1165 **********************************************************************/ 1166 1167 static void 1168 em_if_init(if_ctx_t ctx) 1169 { 1170 struct adapter *adapter = iflib_get_softc(ctx); 1171 struct ifnet *ifp = iflib_get_ifp(ctx); 1172 1173 INIT_DEBUGOUT("em_if_init: begin"); 1174 1175 /* Get the latest mac address, User can use a LAA */ 1176 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1177 ETHER_ADDR_LEN); 1178 1179 /* Put the address into the Receive Address Array */ 1180 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1181 1182 /* 1183 * With the 82571 adapter, RAR[0] may be overwritten 1184 * when the other port is reset, we make a duplicate 1185 * in RAR[14] for that eventuality, this assures 1186 * the interface continues to function. 1187 */ 1188 if (adapter->hw.mac.type == e1000_82571) { 1189 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1190 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1191 E1000_RAR_ENTRIES - 1); 1192 } 1193 1194 /* Initialize the hardware */ 1195 em_reset(ctx); 1196 em_if_update_admin_status(ctx); 1197 1198 /* Setup VLAN support, basic and offload if available */ 1199 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1200 1201 /* Clear bad data from Rx FIFOs */ 1202 if (adapter->hw.mac.type >= igb_mac_min) 1203 e1000_rx_fifo_flush_82575(&adapter->hw); 1204 1205 /* Configure for OS presence */ 1206 em_init_manageability(adapter); 1207 1208 /* Prepare transmit descriptors and buffers */ 1209 em_initialize_transmit_unit(ctx); 1210 1211 /* Setup Multicast table */ 1212 em_if_multi_set(ctx); 1213 1214 /* 1215 ** Figure out the desired mbuf 1216 ** pool for doing jumbos 1217 */ 1218 if (adapter->hw.mac.max_frame_size <= 2048) 1219 adapter->rx_mbuf_sz = MCLBYTES; 1220 else if (adapter->hw.mac.max_frame_size <= 4096) 1221 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1222 else 1223 adapter->rx_mbuf_sz = MJUM9BYTES; 1224 1225 em_initialize_receive_unit(ctx); 1226 1227 /* Use real VLAN Filter support? */ 1228 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1229 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1230 /* Use real VLAN Filter support */ 1231 em_setup_vlan_hw_support(adapter); 1232 else { 1233 u32 ctrl; 1234 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1235 ctrl |= E1000_CTRL_VME; 1236 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1237 } 1238 } 1239 1240 /* Don't lose promiscuous settings */ 1241 em_if_set_promisc(ctx, IFF_PROMISC); 1242 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1243 1244 /* MSI/X configuration for 82574 */ 1245 if (adapter->hw.mac.type == e1000_82574) { 1246 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1247 1248 tmp |= E1000_CTRL_EXT_PBA_CLR; 1249 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1250 /* Set the IVAR - interrupt vector routing. */ 1251 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1252 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1253 igb_configure_queues(adapter); 1254 1255 /* this clears any pending interrupts */ 1256 E1000_READ_REG(&adapter->hw, E1000_ICR); 1257 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1258 1259 /* AMT based hardware can now take control from firmware */ 1260 if (adapter->has_manage && adapter->has_amt) 1261 em_get_hw_control(adapter); 1262 1263 /* Set Energy Efficient Ethernet */ 1264 if (adapter->hw.mac.type >= igb_mac_min && 1265 adapter->hw.phy.media_type == e1000_media_type_copper) { 1266 if (adapter->hw.mac.type == e1000_i354) 1267 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1268 else 1269 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1270 } 1271 } 1272 1273 /********************************************************************* 1274 * 1275 * Fast Legacy/MSI Combined Interrupt Service routine 1276 * 1277 *********************************************************************/ 1278 int 1279 em_intr(void *arg) 1280 { 1281 struct adapter *adapter = arg; 1282 if_ctx_t ctx = adapter->ctx; 1283 u32 reg_icr; 1284 1285 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1286 1287 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1288 goto skip_stray; 1289 /* Hot eject? */ 1290 if (reg_icr == 0xffffffff) 1291 return FILTER_STRAY; 1292 1293 /* Definitely not our interrupt. */ 1294 if (reg_icr == 0x0) 1295 return FILTER_STRAY; 1296 1297 /* 1298 * Starting with the 82571 chip, bit 31 should be used to 1299 * determine whether the interrupt belongs to us. 1300 */ 1301 if (adapter->hw.mac.type >= e1000_82571 && 1302 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1303 return FILTER_STRAY; 1304 1305 skip_stray: 1306 /* Link status change */ 1307 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1308 adapter->hw.mac.get_link_status = 1; 1309 iflib_admin_intr_deferred(ctx); 1310 } 1311 1312 if (reg_icr & E1000_ICR_RXO) 1313 adapter->rx_overruns++; 1314 1315 return (FILTER_SCHEDULE_THREAD); 1316 } 1317 1318 static void 1319 igb_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1320 { 1321 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1322 } 1323 1324 static void 1325 em_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1326 { 1327 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1328 } 1329 1330 static int 1331 em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1332 { 1333 struct adapter *adapter = iflib_get_softc(ctx); 1334 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1335 1336 if (adapter->hw.mac.type >= igb_mac_min) 1337 igb_enable_queue(adapter, rxq); 1338 else 1339 em_enable_queue(adapter, rxq); 1340 return (0); 1341 } 1342 1343 /********************************************************************* 1344 * 1345 * MSIX RX Interrupt Service routine 1346 * 1347 **********************************************************************/ 1348 static int 1349 em_msix_que(void *arg) 1350 { 1351 struct em_rx_queue *que = arg; 1352 1353 ++que->irqs; 1354 1355 return (FILTER_SCHEDULE_THREAD); 1356 } 1357 1358 /********************************************************************* 1359 * 1360 * MSIX Link Fast Interrupt Service routine 1361 * 1362 **********************************************************************/ 1363 static int 1364 em_msix_link(void *arg) 1365 { 1366 struct adapter *adapter = arg; 1367 u32 reg_icr; 1368 1369 ++adapter->link_irq; 1370 MPASS(adapter->hw.back != NULL); 1371 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1372 1373 if (reg_icr & E1000_ICR_RXO) 1374 adapter->rx_overruns++; 1375 1376 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1377 em_handle_link(adapter->ctx); 1378 } else { 1379 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1380 EM_MSIX_LINK | E1000_IMS_LSC); 1381 if (adapter->hw.mac.type >= igb_mac_min) 1382 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1383 1384 } 1385 1386 /* 1387 ** Because we must read the ICR for this interrupt 1388 ** it may clear other causes using autoclear, for 1389 ** this reason we simply create a soft interrupt 1390 ** for all these vectors. 1391 */ 1392 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1393 E1000_WRITE_REG(&adapter->hw, 1394 E1000_ICS, adapter->ims); 1395 } 1396 1397 return (FILTER_HANDLED); 1398 } 1399 1400 static void 1401 em_handle_link(void *context) 1402 { 1403 if_ctx_t ctx = context; 1404 struct adapter *adapter = iflib_get_softc(ctx); 1405 1406 adapter->hw.mac.get_link_status = 1; 1407 iflib_admin_intr_deferred(ctx); 1408 } 1409 1410 1411 /********************************************************************* 1412 * 1413 * Media Ioctl callback 1414 * 1415 * This routine is called whenever the user queries the status of 1416 * the interface using ifconfig. 1417 * 1418 **********************************************************************/ 1419 static void 1420 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1421 { 1422 struct adapter *adapter = iflib_get_softc(ctx); 1423 u_char fiber_type = IFM_1000_SX; 1424 1425 INIT_DEBUGOUT("em_if_media_status: begin"); 1426 1427 iflib_admin_intr_deferred(ctx); 1428 1429 ifmr->ifm_status = IFM_AVALID; 1430 ifmr->ifm_active = IFM_ETHER; 1431 1432 if (!adapter->link_active) { 1433 return; 1434 } 1435 1436 ifmr->ifm_status |= IFM_ACTIVE; 1437 1438 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1439 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1440 if (adapter->hw.mac.type == e1000_82545) 1441 fiber_type = IFM_1000_LX; 1442 ifmr->ifm_active |= fiber_type | IFM_FDX; 1443 } else { 1444 switch (adapter->link_speed) { 1445 case 10: 1446 ifmr->ifm_active |= IFM_10_T; 1447 break; 1448 case 100: 1449 ifmr->ifm_active |= IFM_100_TX; 1450 break; 1451 case 1000: 1452 ifmr->ifm_active |= IFM_1000_T; 1453 break; 1454 } 1455 if (adapter->link_duplex == FULL_DUPLEX) 1456 ifmr->ifm_active |= IFM_FDX; 1457 else 1458 ifmr->ifm_active |= IFM_HDX; 1459 } 1460 } 1461 1462 /********************************************************************* 1463 * 1464 * Media Ioctl callback 1465 * 1466 * This routine is called when the user changes speed/duplex using 1467 * media/mediopt option with ifconfig. 1468 * 1469 **********************************************************************/ 1470 static int 1471 em_if_media_change(if_ctx_t ctx) 1472 { 1473 struct adapter *adapter = iflib_get_softc(ctx); 1474 struct ifmedia *ifm = iflib_get_media(ctx); 1475 1476 INIT_DEBUGOUT("em_if_media_change: begin"); 1477 1478 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1479 return (EINVAL); 1480 1481 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1482 case IFM_AUTO: 1483 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1484 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1485 break; 1486 case IFM_1000_LX: 1487 case IFM_1000_SX: 1488 case IFM_1000_T: 1489 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1490 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1491 break; 1492 case IFM_100_TX: 1493 adapter->hw.mac.autoneg = FALSE; 1494 adapter->hw.phy.autoneg_advertised = 0; 1495 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1496 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1497 else 1498 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1499 break; 1500 case IFM_10_T: 1501 adapter->hw.mac.autoneg = FALSE; 1502 adapter->hw.phy.autoneg_advertised = 0; 1503 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1504 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1505 else 1506 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1507 break; 1508 default: 1509 device_printf(adapter->dev, "Unsupported media type\n"); 1510 } 1511 1512 em_if_init(ctx); 1513 1514 return (0); 1515 } 1516 1517 static int 1518 em_if_set_promisc(if_ctx_t ctx, int flags) 1519 { 1520 struct adapter *adapter = iflib_get_softc(ctx); 1521 u32 reg_rctl; 1522 1523 em_disable_promisc(ctx); 1524 1525 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1526 1527 if (flags & IFF_PROMISC) { 1528 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1529 /* Turn this on if you want to see bad packets */ 1530 if (em_debug_sbp) 1531 reg_rctl |= E1000_RCTL_SBP; 1532 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1533 } else if (flags & IFF_ALLMULTI) { 1534 reg_rctl |= E1000_RCTL_MPE; 1535 reg_rctl &= ~E1000_RCTL_UPE; 1536 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1537 } 1538 return (0); 1539 } 1540 1541 static void 1542 em_disable_promisc(if_ctx_t ctx) 1543 { 1544 struct adapter *adapter = iflib_get_softc(ctx); 1545 struct ifnet *ifp = iflib_get_ifp(ctx); 1546 u32 reg_rctl; 1547 int mcnt = 0; 1548 1549 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1550 reg_rctl &= (~E1000_RCTL_UPE); 1551 if (if_getflags(ifp) & IFF_ALLMULTI) 1552 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1553 else 1554 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1555 /* Don't disable if in MAX groups */ 1556 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1557 reg_rctl &= (~E1000_RCTL_MPE); 1558 reg_rctl &= (~E1000_RCTL_SBP); 1559 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1560 } 1561 1562 1563 /********************************************************************* 1564 * Multicast Update 1565 * 1566 * This routine is called whenever multicast address list is updated. 1567 * 1568 **********************************************************************/ 1569 1570 static void 1571 em_if_multi_set(if_ctx_t ctx) 1572 { 1573 struct adapter *adapter = iflib_get_softc(ctx); 1574 struct ifnet *ifp = iflib_get_ifp(ctx); 1575 u32 reg_rctl = 0; 1576 u8 *mta; /* Multicast array memory */ 1577 int mcnt = 0; 1578 1579 IOCTL_DEBUGOUT("em_set_multi: begin"); 1580 1581 mta = adapter->mta; 1582 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1583 1584 if (adapter->hw.mac.type == e1000_82542 && 1585 adapter->hw.revision_id == E1000_REVISION_2) { 1586 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1587 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1588 e1000_pci_clear_mwi(&adapter->hw); 1589 reg_rctl |= E1000_RCTL_RST; 1590 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1591 msec_delay(5); 1592 } 1593 1594 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1595 1596 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1597 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1598 reg_rctl |= E1000_RCTL_MPE; 1599 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1600 } else 1601 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1602 1603 if (adapter->hw.mac.type == e1000_82542 && 1604 adapter->hw.revision_id == E1000_REVISION_2) { 1605 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1606 reg_rctl &= ~E1000_RCTL_RST; 1607 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1608 msec_delay(5); 1609 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1610 e1000_pci_set_mwi(&adapter->hw); 1611 } 1612 } 1613 1614 1615 /********************************************************************* 1616 * Timer routine 1617 * 1618 * This routine checks for link status and updates statistics. 1619 * 1620 **********************************************************************/ 1621 1622 static void 1623 em_if_timer(if_ctx_t ctx, uint16_t qid) 1624 { 1625 struct adapter *adapter = iflib_get_softc(ctx); 1626 struct em_rx_queue *que; 1627 int i; 1628 int trigger = 0; 1629 1630 if (qid != 0) { 1631 /* XXX all this stuff is per-adapter */ 1632 return; 1633 } 1634 1635 em_if_update_admin_status(ctx); 1636 em_update_stats_counters(adapter); 1637 1638 /* Reset LAA into RAR[0] on 82571 */ 1639 if ((adapter->hw.mac.type == e1000_82571) && 1640 e1000_get_laa_state_82571(&adapter->hw)) 1641 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1642 1643 if (adapter->hw.mac.type < em_mac_min) 1644 lem_smartspeed(adapter); 1645 1646 /* Mask to use in the irq trigger */ 1647 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1648 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1649 trigger |= que->eims; 1650 } else { 1651 trigger = E1000_ICS_RXDMT0; 1652 } 1653 } 1654 1655 1656 static void 1657 em_if_update_admin_status(if_ctx_t ctx) 1658 { 1659 struct adapter *adapter = iflib_get_softc(ctx); 1660 struct e1000_hw *hw = &adapter->hw; 1661 struct ifnet *ifp = iflib_get_ifp(ctx); 1662 device_t dev = iflib_get_dev(ctx); 1663 u32 link_check = 0; 1664 1665 /* Get the cached link value or read phy for real */ 1666 switch (hw->phy.media_type) { 1667 case e1000_media_type_copper: 1668 if (hw->mac.get_link_status) { 1669 if (hw->mac.type == e1000_pch_spt) 1670 msec_delay(50); 1671 /* Do the work to read phy */ 1672 e1000_check_for_link(hw); 1673 link_check = !hw->mac.get_link_status; 1674 if (link_check) /* ESB2 fix */ 1675 e1000_cfg_on_link_up(hw); 1676 } else { 1677 link_check = TRUE; 1678 } 1679 break; 1680 case e1000_media_type_fiber: 1681 e1000_check_for_link(hw); 1682 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1683 E1000_STATUS_LU); 1684 break; 1685 case e1000_media_type_internal_serdes: 1686 e1000_check_for_link(hw); 1687 link_check = adapter->hw.mac.serdes_has_link; 1688 break; 1689 default: 1690 case e1000_media_type_unknown: 1691 break; 1692 } 1693 1694 /* Now check for a transition */ 1695 if (link_check && (adapter->link_active == 0)) { 1696 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1697 &adapter->link_duplex); 1698 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1699 if ((adapter->link_speed != SPEED_1000) && 1700 ((hw->mac.type == e1000_82571) || 1701 (hw->mac.type == e1000_82572))) { 1702 int tarc0; 1703 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1704 tarc0 &= ~TARC_SPEED_MODE_BIT; 1705 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1706 } 1707 if (bootverbose) 1708 device_printf(dev, "Link is up %d Mbps %s\n", 1709 adapter->link_speed, 1710 ((adapter->link_duplex == FULL_DUPLEX) ? 1711 "Full Duplex" : "Half Duplex")); 1712 adapter->link_active = 1; 1713 adapter->smartspeed = 0; 1714 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1715 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1716 printf("Link state changed to up\n"); 1717 } else if (!link_check && (adapter->link_active == 1)) { 1718 if_setbaudrate(ifp, 0); 1719 adapter->link_speed = 0; 1720 adapter->link_duplex = 0; 1721 if (bootverbose) 1722 device_printf(dev, "Link is Down\n"); 1723 adapter->link_active = 0; 1724 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1725 printf("link state changed to down\n"); 1726 } 1727 1728 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1729 } 1730 1731 /********************************************************************* 1732 * 1733 * This routine disables all traffic on the adapter by issuing a 1734 * global reset on the MAC and deallocates TX/RX buffers. 1735 * 1736 * This routine should always be called with BOTH the CORE 1737 * and TX locks. 1738 **********************************************************************/ 1739 1740 static void 1741 em_if_stop(if_ctx_t ctx) 1742 { 1743 struct adapter *adapter = iflib_get_softc(ctx); 1744 1745 INIT_DEBUGOUT("em_stop: begin"); 1746 1747 e1000_reset_hw(&adapter->hw); 1748 if (adapter->hw.mac.type >= e1000_82544) 1749 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1750 1751 e1000_led_off(&adapter->hw); 1752 e1000_cleanup_led(&adapter->hw); 1753 } 1754 1755 1756 /********************************************************************* 1757 * 1758 * Determine hardware revision. 1759 * 1760 **********************************************************************/ 1761 static void 1762 em_identify_hardware(if_ctx_t ctx) 1763 { 1764 device_t dev = iflib_get_dev(ctx); 1765 struct adapter *adapter = iflib_get_softc(ctx); 1766 1767 /* Make sure our PCI config space has the necessary stuff set */ 1768 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1769 1770 /* Save off the information about this board */ 1771 adapter->hw.vendor_id = pci_get_vendor(dev); 1772 adapter->hw.device_id = pci_get_device(dev); 1773 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1774 adapter->hw.subsystem_vendor_id = 1775 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1776 adapter->hw.subsystem_device_id = 1777 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1778 1779 /* Do Shared Code Init and Setup */ 1780 if (e1000_set_mac_type(&adapter->hw)) { 1781 device_printf(dev, "Setup init failure\n"); 1782 return; 1783 } 1784 } 1785 1786 static int 1787 em_allocate_pci_resources(if_ctx_t ctx) 1788 { 1789 struct adapter *adapter = iflib_get_softc(ctx); 1790 device_t dev = iflib_get_dev(ctx); 1791 int rid, val; 1792 1793 rid = PCIR_BAR(0); 1794 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1795 &rid, RF_ACTIVE); 1796 if (adapter->memory == NULL) { 1797 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1798 return (ENXIO); 1799 } 1800 adapter->osdep.mem_bus_space_tag = 1801 rman_get_bustag(adapter->memory); 1802 adapter->osdep.mem_bus_space_handle = 1803 rman_get_bushandle(adapter->memory); 1804 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1805 1806 /* Only older adapters use IO mapping */ 1807 if (adapter->hw.mac.type < em_mac_min && 1808 adapter->hw.mac.type > e1000_82543) { 1809 /* Figure our where our IO BAR is ? */ 1810 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1811 val = pci_read_config(dev, rid, 4); 1812 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1813 adapter->io_rid = rid; 1814 break; 1815 } 1816 rid += 4; 1817 /* check for 64bit BAR */ 1818 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1819 rid += 4; 1820 } 1821 if (rid >= PCIR_CIS) { 1822 device_printf(dev, "Unable to locate IO BAR\n"); 1823 return (ENXIO); 1824 } 1825 adapter->ioport = bus_alloc_resource_any(dev, 1826 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1827 if (adapter->ioport == NULL) { 1828 device_printf(dev, "Unable to allocate bus resource: " 1829 "ioport\n"); 1830 return (ENXIO); 1831 } 1832 adapter->hw.io_base = 0; 1833 adapter->osdep.io_bus_space_tag = 1834 rman_get_bustag(adapter->ioport); 1835 adapter->osdep.io_bus_space_handle = 1836 rman_get_bushandle(adapter->ioport); 1837 } 1838 1839 adapter->hw.back = &adapter->osdep; 1840 1841 return (0); 1842 } 1843 1844 /********************************************************************* 1845 * 1846 * Setup the MSIX Interrupt handlers 1847 * 1848 **********************************************************************/ 1849 static int 1850 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1851 { 1852 struct adapter *adapter = iflib_get_softc(ctx); 1853 struct em_rx_queue *rx_que = adapter->rx_queues; 1854 struct em_tx_queue *tx_que = adapter->tx_queues; 1855 int error, rid, i, vector = 0; 1856 char buf[16]; 1857 1858 /* First set up ring resources */ 1859 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1860 rid = vector +1; 1861 snprintf(buf, sizeof(buf), "rxq%d", i); 1862 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RX, em_msix_que, rx_que, rx_que->me, buf); 1863 if (error) { 1864 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1865 adapter->rx_num_queues = i + 1; 1866 goto fail; 1867 } 1868 1869 rx_que->msix = vector; 1870 1871 /* 1872 ** Set the bit to enable interrupt 1873 ** in E1000_IMS -- bits 20 and 21 1874 ** are for RX0 and RX1, note this has 1875 ** NOTHING to do with the MSIX vector 1876 */ 1877 if (adapter->hw.mac.type == e1000_82574) { 1878 rx_que->eims = 1 << (20 + i); 1879 adapter->ims |= rx_que->eims; 1880 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1881 } else if (adapter->hw.mac.type == e1000_82575) 1882 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1883 else 1884 rx_que->eims = 1 << vector; 1885 } 1886 1887 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1888 rid = vector + 1; 1889 snprintf(buf, sizeof(buf), "txq%d", i); 1890 tx_que = &adapter->tx_queues[i]; 1891 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1892 1893 tx_que->msix = vector; 1894 1895 /* 1896 ** Set the bit to enable interrupt 1897 ** in E1000_IMS -- bits 22 and 23 1898 ** are for TX0 and TX1, note this has 1899 ** NOTHING to do with the MSIX vector 1900 */ 1901 if (adapter->hw.mac.type < igb_mac_min) { 1902 tx_que->eims = 1 << (22 + i); 1903 adapter->ims |= tx_que->eims; 1904 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1905 } if (adapter->hw.mac.type == e1000_82575) 1906 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1907 else 1908 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1909 } 1910 1911 /* Link interrupt */ 1912 rid = vector + 1; 1913 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1914 1915 if (error) { 1916 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1917 goto fail; 1918 } 1919 adapter->linkvec = vector; 1920 if (adapter->hw.mac.type < igb_mac_min) { 1921 adapter->ivars |= (8 | vector) << 16; 1922 adapter->ivars |= 0x80000000; 1923 } 1924 return (0); 1925 fail: 1926 iflib_irq_free(ctx, &adapter->irq); 1927 rx_que = adapter->rx_queues; 1928 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1929 iflib_irq_free(ctx, &rx_que->que_irq); 1930 return (error); 1931 } 1932 1933 static void 1934 igb_configure_queues(struct adapter *adapter) 1935 { 1936 struct e1000_hw *hw = &adapter->hw; 1937 struct em_rx_queue *rx_que; 1938 struct em_tx_queue *tx_que; 1939 u32 tmp, ivar = 0, newitr = 0; 1940 1941 /* First turn on RSS capability */ 1942 if (adapter->hw.mac.type != e1000_82575) 1943 E1000_WRITE_REG(hw, E1000_GPIE, 1944 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 1945 E1000_GPIE_PBA | E1000_GPIE_NSICR); 1946 1947 /* Turn on MSIX */ 1948 switch (adapter->hw.mac.type) { 1949 case e1000_82580: 1950 case e1000_i350: 1951 case e1000_i354: 1952 case e1000_i210: 1953 case e1000_i211: 1954 case e1000_vfadapt: 1955 case e1000_vfadapt_i350: 1956 /* RX entries */ 1957 for (int i = 0; i < adapter->rx_num_queues; i++) { 1958 u32 index = i >> 1; 1959 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1960 rx_que = &adapter->rx_queues[i]; 1961 if (i & 1) { 1962 ivar &= 0xFF00FFFF; 1963 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 1964 } else { 1965 ivar &= 0xFFFFFF00; 1966 ivar |= rx_que->msix | E1000_IVAR_VALID; 1967 } 1968 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 1969 } 1970 /* TX entries */ 1971 for (int i = 0; i < adapter->tx_num_queues; i++) { 1972 u32 index = i >> 1; 1973 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1974 tx_que = &adapter->tx_queues[i]; 1975 if (i & 1) { 1976 ivar &= 0x00FFFFFF; 1977 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 1978 } else { 1979 ivar &= 0xFFFF00FF; 1980 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 1981 } 1982 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 1983 adapter->que_mask |= tx_que->eims; 1984 } 1985 1986 /* And for the link interrupt */ 1987 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 1988 adapter->link_mask = 1 << adapter->linkvec; 1989 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 1990 break; 1991 case e1000_82576: 1992 /* RX entries */ 1993 for (int i = 0; i < adapter->rx_num_queues; i++) { 1994 u32 index = i & 0x7; /* Each IVAR has two entries */ 1995 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1996 rx_que = &adapter->rx_queues[i]; 1997 if (i < 8) { 1998 ivar &= 0xFFFFFF00; 1999 ivar |= rx_que->msix | E1000_IVAR_VALID; 2000 } else { 2001 ivar &= 0xFF00FFFF; 2002 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2003 } 2004 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2005 adapter->que_mask |= rx_que->eims; 2006 } 2007 /* TX entries */ 2008 for (int i = 0; i < adapter->tx_num_queues; i++) { 2009 u32 index = i & 0x7; /* Each IVAR has two entries */ 2010 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2011 tx_que = &adapter->tx_queues[i]; 2012 if (i < 8) { 2013 ivar &= 0xFFFF00FF; 2014 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2015 } else { 2016 ivar &= 0x00FFFFFF; 2017 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2018 } 2019 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2020 adapter->que_mask |= tx_que->eims; 2021 } 2022 2023 /* And for the link interrupt */ 2024 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2025 adapter->link_mask = 1 << adapter->linkvec; 2026 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2027 break; 2028 2029 case e1000_82575: 2030 /* enable MSI-X support*/ 2031 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2032 tmp |= E1000_CTRL_EXT_PBA_CLR; 2033 /* Auto-Mask interrupts upon ICR read. */ 2034 tmp |= E1000_CTRL_EXT_EIAME; 2035 tmp |= E1000_CTRL_EXT_IRCA; 2036 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2037 2038 /* Queues */ 2039 for (int i = 0; i < adapter->rx_num_queues; i++) { 2040 rx_que = &adapter->rx_queues[i]; 2041 tmp = E1000_EICR_RX_QUEUE0 << i; 2042 tmp |= E1000_EICR_TX_QUEUE0 << i; 2043 rx_que->eims = tmp; 2044 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2045 i, rx_que->eims); 2046 adapter->que_mask |= rx_que->eims; 2047 } 2048 2049 /* Link */ 2050 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2051 E1000_EIMS_OTHER); 2052 adapter->link_mask |= E1000_EIMS_OTHER; 2053 default: 2054 break; 2055 } 2056 2057 /* Set the starting interrupt rate */ 2058 if (em_max_interrupt_rate > 0) 2059 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2060 2061 if (hw->mac.type == e1000_82575) 2062 newitr |= newitr << 16; 2063 else 2064 newitr |= E1000_EITR_CNT_IGNR; 2065 2066 for (int i = 0; i < adapter->rx_num_queues; i++) { 2067 rx_que = &adapter->rx_queues[i]; 2068 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2069 } 2070 2071 return; 2072 } 2073 2074 static void 2075 em_free_pci_resources(if_ctx_t ctx) 2076 { 2077 struct adapter *adapter = iflib_get_softc(ctx); 2078 struct em_rx_queue *que = adapter->rx_queues; 2079 device_t dev = iflib_get_dev(ctx); 2080 2081 /* Release all msix queue resources */ 2082 if (adapter->intr_type == IFLIB_INTR_MSIX) 2083 iflib_irq_free(ctx, &adapter->irq); 2084 2085 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2086 iflib_irq_free(ctx, &que->que_irq); 2087 } 2088 2089 2090 /* First release all the interrupt resources */ 2091 if (adapter->memory != NULL) { 2092 bus_release_resource(dev, SYS_RES_MEMORY, 2093 PCIR_BAR(0), adapter->memory); 2094 adapter->memory = NULL; 2095 } 2096 2097 if (adapter->flash != NULL) { 2098 bus_release_resource(dev, SYS_RES_MEMORY, 2099 EM_FLASH, adapter->flash); 2100 adapter->flash = NULL; 2101 } 2102 if (adapter->ioport != NULL) 2103 bus_release_resource(dev, SYS_RES_IOPORT, 2104 adapter->io_rid, adapter->ioport); 2105 } 2106 2107 /* Setup MSI or MSI/X */ 2108 static int 2109 em_setup_msix(if_ctx_t ctx) 2110 { 2111 struct adapter *adapter = iflib_get_softc(ctx); 2112 2113 if (adapter->hw.mac.type == e1000_82574) { 2114 em_enable_vectors_82574(ctx); 2115 } 2116 return (0); 2117 } 2118 2119 /********************************************************************* 2120 * 2121 * Initialize the hardware to a configuration 2122 * as specified by the adapter structure. 2123 * 2124 **********************************************************************/ 2125 2126 static void 2127 lem_smartspeed(struct adapter *adapter) 2128 { 2129 u16 phy_tmp; 2130 2131 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2132 adapter->hw.mac.autoneg == 0 || 2133 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2134 return; 2135 2136 if (adapter->smartspeed == 0) { 2137 /* If Master/Slave config fault is asserted twice, 2138 * we assume back-to-back */ 2139 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2140 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2141 return; 2142 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2143 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2144 e1000_read_phy_reg(&adapter->hw, 2145 PHY_1000T_CTRL, &phy_tmp); 2146 if(phy_tmp & CR_1000T_MS_ENABLE) { 2147 phy_tmp &= ~CR_1000T_MS_ENABLE; 2148 e1000_write_phy_reg(&adapter->hw, 2149 PHY_1000T_CTRL, phy_tmp); 2150 adapter->smartspeed++; 2151 if(adapter->hw.mac.autoneg && 2152 !e1000_copper_link_autoneg(&adapter->hw) && 2153 !e1000_read_phy_reg(&adapter->hw, 2154 PHY_CONTROL, &phy_tmp)) { 2155 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2156 MII_CR_RESTART_AUTO_NEG); 2157 e1000_write_phy_reg(&adapter->hw, 2158 PHY_CONTROL, phy_tmp); 2159 } 2160 } 2161 } 2162 return; 2163 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2164 /* If still no link, perhaps using 2/3 pair cable */ 2165 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2166 phy_tmp |= CR_1000T_MS_ENABLE; 2167 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2168 if(adapter->hw.mac.autoneg && 2169 !e1000_copper_link_autoneg(&adapter->hw) && 2170 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2171 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2172 MII_CR_RESTART_AUTO_NEG); 2173 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2174 } 2175 } 2176 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2177 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2178 adapter->smartspeed = 0; 2179 } 2180 2181 2182 static void 2183 em_reset(if_ctx_t ctx) 2184 { 2185 device_t dev = iflib_get_dev(ctx); 2186 struct adapter *adapter = iflib_get_softc(ctx); 2187 struct ifnet *ifp = iflib_get_ifp(ctx); 2188 struct e1000_hw *hw = &adapter->hw; 2189 u16 rx_buffer_size; 2190 u32 pba; 2191 2192 INIT_DEBUGOUT("em_reset: begin"); 2193 2194 /* Set up smart power down as default off on newer adapters. */ 2195 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2196 hw->mac.type == e1000_82572)) { 2197 u16 phy_tmp = 0; 2198 2199 /* Speed up time to link by disabling smart power down. */ 2200 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2201 phy_tmp &= ~IGP02E1000_PM_SPD; 2202 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2203 } 2204 2205 /* 2206 * Packet Buffer Allocation (PBA) 2207 * Writing PBA sets the receive portion of the buffer 2208 * the remainder is used for the transmit buffer. 2209 */ 2210 switch (hw->mac.type) { 2211 /* Total Packet Buffer on these is 48K */ 2212 case e1000_82571: 2213 case e1000_82572: 2214 case e1000_80003es2lan: 2215 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2216 break; 2217 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2218 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2219 break; 2220 case e1000_82574: 2221 case e1000_82583: 2222 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2223 break; 2224 case e1000_ich8lan: 2225 pba = E1000_PBA_8K; 2226 break; 2227 case e1000_ich9lan: 2228 case e1000_ich10lan: 2229 /* Boost Receive side for jumbo frames */ 2230 if (adapter->hw.mac.max_frame_size > 4096) 2231 pba = E1000_PBA_14K; 2232 else 2233 pba = E1000_PBA_10K; 2234 break; 2235 case e1000_pchlan: 2236 case e1000_pch2lan: 2237 case e1000_pch_lpt: 2238 case e1000_pch_spt: 2239 pba = E1000_PBA_26K; 2240 break; 2241 case e1000_82575: 2242 pba = E1000_PBA_32K; 2243 break; 2244 case e1000_82576: 2245 case e1000_vfadapt: 2246 pba = E1000_READ_REG(hw, E1000_RXPBS); 2247 pba &= E1000_RXPBS_SIZE_MASK_82576; 2248 break; 2249 case e1000_82580: 2250 case e1000_i350: 2251 case e1000_i354: 2252 case e1000_vfadapt_i350: 2253 pba = E1000_READ_REG(hw, E1000_RXPBS); 2254 pba = e1000_rxpbs_adjust_82580(pba); 2255 break; 2256 case e1000_i210: 2257 case e1000_i211: 2258 pba = E1000_PBA_34K; 2259 break; 2260 default: 2261 if (adapter->hw.mac.max_frame_size > 8192) 2262 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2263 else 2264 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2265 } 2266 2267 /* Special needs in case of Jumbo frames */ 2268 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2269 u32 tx_space, min_tx, min_rx; 2270 pba = E1000_READ_REG(hw, E1000_PBA); 2271 tx_space = pba >> 16; 2272 pba &= 0xffff; 2273 min_tx = (adapter->hw.mac.max_frame_size + 2274 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2275 min_tx = roundup2(min_tx, 1024); 2276 min_tx >>= 10; 2277 min_rx = adapter->hw.mac.max_frame_size; 2278 min_rx = roundup2(min_rx, 1024); 2279 min_rx >>= 10; 2280 if (tx_space < min_tx && 2281 ((min_tx - tx_space) < pba)) { 2282 pba = pba - (min_tx - tx_space); 2283 /* 2284 * if short on rx space, rx wins 2285 * and must trump tx adjustment 2286 */ 2287 if (pba < min_rx) 2288 pba = min_rx; 2289 } 2290 E1000_WRITE_REG(hw, E1000_PBA, pba); 2291 } 2292 2293 if (hw->mac.type < igb_mac_min) 2294 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2295 2296 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2297 2298 /* 2299 * These parameters control the automatic generation (Tx) and 2300 * response (Rx) to Ethernet PAUSE frames. 2301 * - High water mark should allow for at least two frames to be 2302 * received after sending an XOFF. 2303 * - Low water mark works best when it is very near the high water mark. 2304 * This allows the receiver to restart by sending XON when it has 2305 * drained a bit. Here we use an arbitrary value of 1500 which will 2306 * restart after one full frame is pulled from the buffer. There 2307 * could be several smaller frames in the buffer and if so they will 2308 * not trigger the XON until their total number reduces the buffer 2309 * by 1500. 2310 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2311 */ 2312 rx_buffer_size = (pba & 0xffff) << 10; 2313 hw->fc.high_water = rx_buffer_size - 2314 roundup2(adapter->hw.mac.max_frame_size, 1024); 2315 hw->fc.low_water = hw->fc.high_water - 1500; 2316 2317 if (adapter->fc) /* locally set flow control value? */ 2318 hw->fc.requested_mode = adapter->fc; 2319 else 2320 hw->fc.requested_mode = e1000_fc_full; 2321 2322 if (hw->mac.type == e1000_80003es2lan) 2323 hw->fc.pause_time = 0xFFFF; 2324 else 2325 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2326 2327 hw->fc.send_xon = TRUE; 2328 2329 /* Device specific overrides/settings */ 2330 switch (hw->mac.type) { 2331 case e1000_pchlan: 2332 /* Workaround: no TX flow ctrl for PCH */ 2333 hw->fc.requested_mode = e1000_fc_rx_pause; 2334 hw->fc.pause_time = 0xFFFF; /* override */ 2335 if (if_getmtu(ifp) > ETHERMTU) { 2336 hw->fc.high_water = 0x3500; 2337 hw->fc.low_water = 0x1500; 2338 } else { 2339 hw->fc.high_water = 0x5000; 2340 hw->fc.low_water = 0x3000; 2341 } 2342 hw->fc.refresh_time = 0x1000; 2343 break; 2344 case e1000_pch2lan: 2345 case e1000_pch_lpt: 2346 case e1000_pch_spt: 2347 hw->fc.high_water = 0x5C20; 2348 hw->fc.low_water = 0x5048; 2349 hw->fc.pause_time = 0x0650; 2350 hw->fc.refresh_time = 0x0400; 2351 /* Jumbos need adjusted PBA */ 2352 if (if_getmtu(ifp) > ETHERMTU) 2353 E1000_WRITE_REG(hw, E1000_PBA, 12); 2354 else 2355 E1000_WRITE_REG(hw, E1000_PBA, 26); 2356 break; 2357 case e1000_82575: 2358 case e1000_82576: 2359 /* 8-byte granularity */ 2360 hw->fc.low_water = hw->fc.high_water - 8; 2361 break; 2362 case e1000_82580: 2363 case e1000_i350: 2364 case e1000_i354: 2365 case e1000_i210: 2366 case e1000_i211: 2367 case e1000_vfadapt: 2368 case e1000_vfadapt_i350: 2369 /* 16-byte granularity */ 2370 hw->fc.low_water = hw->fc.high_water - 16; 2371 break; 2372 case e1000_ich9lan: 2373 case e1000_ich10lan: 2374 if (if_getmtu(ifp) > ETHERMTU) { 2375 hw->fc.high_water = 0x2800; 2376 hw->fc.low_water = hw->fc.high_water - 8; 2377 break; 2378 } 2379 /* else fall thru */ 2380 default: 2381 if (hw->mac.type == e1000_80003es2lan) 2382 hw->fc.pause_time = 0xFFFF; 2383 break; 2384 } 2385 2386 /* Issue a global reset */ 2387 e1000_reset_hw(hw); 2388 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2389 em_disable_aspm(adapter); 2390 /* and a re-init */ 2391 if (e1000_init_hw(hw) < 0) { 2392 device_printf(dev, "Hardware Initialization Failed\n"); 2393 return; 2394 } 2395 2396 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2397 e1000_get_phy_info(hw); 2398 e1000_check_for_link(hw); 2399 } 2400 2401 #define RSSKEYLEN 10 2402 static void 2403 em_initialize_rss_mapping(struct adapter *adapter) 2404 { 2405 uint8_t rss_key[4 * RSSKEYLEN]; 2406 uint32_t reta = 0; 2407 struct e1000_hw *hw = &adapter->hw; 2408 int i; 2409 2410 /* 2411 * Configure RSS key 2412 */ 2413 arc4rand(rss_key, sizeof(rss_key), 0); 2414 for (i = 0; i < RSSKEYLEN; ++i) { 2415 uint32_t rssrk = 0; 2416 2417 rssrk = EM_RSSRK_VAL(rss_key, i); 2418 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2419 } 2420 2421 /* 2422 * Configure RSS redirect table in following fashion: 2423 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2424 */ 2425 for (i = 0; i < sizeof(reta); ++i) { 2426 uint32_t q; 2427 2428 q = (i % adapter->rx_num_queues) << 7; 2429 reta |= q << (8 * i); 2430 } 2431 2432 for (i = 0; i < 32; ++i) 2433 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2434 2435 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2436 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2437 E1000_MRQC_RSS_FIELD_IPV4 | 2438 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2439 E1000_MRQC_RSS_FIELD_IPV6_EX | 2440 E1000_MRQC_RSS_FIELD_IPV6); 2441 2442 } 2443 2444 static void 2445 igb_initialize_rss_mapping(struct adapter *adapter) 2446 { 2447 struct e1000_hw *hw = &adapter->hw; 2448 int i; 2449 int queue_id; 2450 u32 reta; 2451 u32 rss_key[10], mrqc, shift = 0; 2452 2453 /* XXX? */ 2454 if (adapter->hw.mac.type == e1000_82575) 2455 shift = 6; 2456 2457 /* 2458 * The redirection table controls which destination 2459 * queue each bucket redirects traffic to. 2460 * Each DWORD represents four queues, with the LSB 2461 * being the first queue in the DWORD. 2462 * 2463 * This just allocates buckets to queues using round-robin 2464 * allocation. 2465 * 2466 * NOTE: It Just Happens to line up with the default 2467 * RSS allocation method. 2468 */ 2469 2470 /* Warning FM follows */ 2471 reta = 0; 2472 for (i = 0; i < 128; i++) { 2473 #ifdef RSS 2474 queue_id = rss_get_indirection_to_bucket(i); 2475 /* 2476 * If we have more queues than buckets, we'll 2477 * end up mapping buckets to a subset of the 2478 * queues. 2479 * 2480 * If we have more buckets than queues, we'll 2481 * end up instead assigning multiple buckets 2482 * to queues. 2483 * 2484 * Both are suboptimal, but we need to handle 2485 * the case so we don't go out of bounds 2486 * indexing arrays and such. 2487 */ 2488 queue_id = queue_id % adapter->rx_num_queues; 2489 #else 2490 queue_id = (i % adapter->rx_num_queues); 2491 #endif 2492 /* Adjust if required */ 2493 queue_id = queue_id << shift; 2494 2495 /* 2496 * The low 8 bits are for hash value (n+0); 2497 * The next 8 bits are for hash value (n+1), etc. 2498 */ 2499 reta = reta >> 8; 2500 reta = reta | ( ((uint32_t) queue_id) << 24); 2501 if ((i & 3) == 3) { 2502 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2503 reta = 0; 2504 } 2505 } 2506 2507 /* Now fill in hash table */ 2508 2509 /* 2510 * MRQC: Multiple Receive Queues Command 2511 * Set queuing to RSS control, number depends on the device. 2512 */ 2513 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2514 2515 #ifdef RSS 2516 /* XXX ew typecasting */ 2517 rss_getkey((uint8_t *) &rss_key); 2518 #else 2519 arc4rand(&rss_key, sizeof(rss_key), 0); 2520 #endif 2521 for (i = 0; i < 10; i++) 2522 E1000_WRITE_REG_ARRAY(hw, 2523 E1000_RSSRK(0), i, rss_key[i]); 2524 2525 /* 2526 * Configure the RSS fields to hash upon. 2527 */ 2528 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2529 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2530 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2531 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2532 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2533 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2534 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2535 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2536 2537 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2538 } 2539 2540 /********************************************************************* 2541 * 2542 * Setup networking device structure and register an interface. 2543 * 2544 **********************************************************************/ 2545 static int 2546 em_setup_interface(if_ctx_t ctx) 2547 { 2548 struct ifnet *ifp = iflib_get_ifp(ctx); 2549 struct adapter *adapter = iflib_get_softc(ctx); 2550 if_softc_ctx_t scctx = adapter->shared; 2551 uint64_t cap = 0; 2552 2553 INIT_DEBUGOUT("em_setup_interface: begin"); 2554 2555 /* TSO parameters */ 2556 if_sethwtsomax(ifp, IP_MAXPACKET); 2557 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2558 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2559 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2560 2561 /* Single Queue */ 2562 if (adapter->tx_num_queues == 1) { 2563 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2564 if_setsendqready(ifp); 2565 } 2566 2567 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2568 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2569 2570 /* 2571 * Tell the upper layer(s) we 2572 * support full VLAN capability 2573 */ 2574 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2575 if_setcapabilitiesbit(ifp, cap, 0); 2576 2577 /* 2578 ** Don't turn this on by default, if vlans are 2579 ** created on another pseudo device (eg. lagg) 2580 ** then vlan events are not passed thru, breaking 2581 ** operation, but with HW FILTER off it works. If 2582 ** using vlans directly on the em driver you can 2583 ** enable this and get full hardware tag filtering. 2584 */ 2585 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2586 2587 /* Enable only WOL MAGIC by default */ 2588 if (adapter->wol) { 2589 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2590 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2591 } else { 2592 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2593 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2594 } 2595 2596 /* 2597 * Specify the media types supported by this adapter and register 2598 * callbacks to update media and link information 2599 */ 2600 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2601 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2602 u_char fiber_type = IFM_1000_SX; /* default type */ 2603 2604 if (adapter->hw.mac.type == e1000_82545) 2605 fiber_type = IFM_1000_LX; 2606 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2607 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2608 } else { 2609 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2610 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2611 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2612 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2613 if (adapter->hw.phy.type != e1000_phy_ife) { 2614 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2615 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2616 } 2617 } 2618 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2619 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2620 return (0); 2621 } 2622 2623 static int 2624 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2625 { 2626 struct adapter *adapter = iflib_get_softc(ctx); 2627 if_softc_ctx_t scctx = adapter->shared; 2628 int error = E1000_SUCCESS; 2629 struct em_tx_queue *que; 2630 int i; 2631 2632 MPASS(adapter->tx_num_queues > 0); 2633 MPASS(adapter->tx_num_queues == ntxqsets); 2634 2635 /* First allocate the top level queue structs */ 2636 if (!(adapter->tx_queues = 2637 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2638 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2639 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2640 return(ENOMEM); 2641 } 2642 2643 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2644 /* Set up some basics */ 2645 struct tx_ring *txr = &que->txr; 2646 txr->adapter = que->adapter = adapter; 2647 txr->que = que; 2648 que->me = txr->me = i; 2649 2650 /* Allocate transmit buffer memory */ 2651 if (!(txr->tx_buffers = (struct em_txbuffer *) malloc(sizeof(struct em_txbuffer) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2652 device_printf(iflib_get_dev(ctx), "failed to allocate tx_buffer memory\n"); 2653 error = ENOMEM; 2654 goto fail; 2655 } 2656 2657 /* get the virtual and physical address of the hardware queues */ 2658 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2659 txr->tx_paddr = paddrs[i*ntxqs]; 2660 2661 } 2662 2663 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2664 return (0); 2665 fail: 2666 em_if_queues_free(ctx); 2667 return (error); 2668 } 2669 2670 static int 2671 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2672 { 2673 struct adapter *adapter = iflib_get_softc(ctx); 2674 int error = E1000_SUCCESS; 2675 struct em_rx_queue *que; 2676 int i; 2677 2678 MPASS(adapter->rx_num_queues > 0); 2679 MPASS(adapter->rx_num_queues == nrxqsets); 2680 2681 /* First allocate the top level queue structs */ 2682 if (!(adapter->rx_queues = 2683 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2684 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2685 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2686 error = ENOMEM; 2687 goto fail; 2688 } 2689 2690 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2691 /* Set up some basics */ 2692 struct rx_ring *rxr = &que->rxr; 2693 rxr->adapter = que->adapter = adapter; 2694 rxr->que = que; 2695 que->me = rxr->me = i; 2696 2697 /* get the virtual and physical address of the hardware queues */ 2698 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2699 rxr->rx_paddr = paddrs[i*nrxqs]; 2700 } 2701 2702 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2703 2704 return (0); 2705 fail: 2706 em_if_queues_free(ctx); 2707 return (error); 2708 } 2709 2710 static void 2711 em_if_queues_free(if_ctx_t ctx) 2712 { 2713 struct adapter *adapter = iflib_get_softc(ctx); 2714 struct em_tx_queue *tx_que = adapter->tx_queues; 2715 struct em_rx_queue *rx_que = adapter->rx_queues; 2716 2717 if (tx_que != NULL) { 2718 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2719 struct tx_ring *txr = &tx_que->txr; 2720 if (txr->tx_buffers == NULL) 2721 break; 2722 2723 free(txr->tx_buffers, M_DEVBUF); 2724 txr->tx_buffers = NULL; 2725 } 2726 free(adapter->tx_queues, M_DEVBUF); 2727 adapter->tx_queues = NULL; 2728 } 2729 2730 if (rx_que != NULL) { 2731 free(adapter->rx_queues, M_DEVBUF); 2732 adapter->rx_queues = NULL; 2733 } 2734 2735 em_release_hw_control(adapter); 2736 2737 if (adapter->mta != NULL) { 2738 free(adapter->mta, M_DEVBUF); 2739 } 2740 } 2741 2742 /********************************************************************* 2743 * 2744 * Enable transmit unit. 2745 * 2746 **********************************************************************/ 2747 static void 2748 em_initialize_transmit_unit(if_ctx_t ctx) 2749 { 2750 struct adapter *adapter = iflib_get_softc(ctx); 2751 if_softc_ctx_t scctx = adapter->shared; 2752 struct em_tx_queue *que; 2753 struct tx_ring *txr; 2754 struct e1000_hw *hw = &adapter->hw; 2755 u32 tctl, txdctl = 0, tarc, tipg = 0; 2756 2757 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2758 2759 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2760 u64 bus_addr; 2761 caddr_t offp, endp; 2762 2763 que = &adapter->tx_queues[i]; 2764 txr = &que->txr; 2765 bus_addr = txr->tx_paddr; 2766 2767 /*Enable all queues */ 2768 em_init_tx_ring(que); 2769 2770 /* Clear checksum offload context. */ 2771 offp = (caddr_t)&txr->csum_flags; 2772 endp = (caddr_t)(txr + 1); 2773 bzero(offp, endp - offp); 2774 2775 /* Base and Len of TX Ring */ 2776 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2777 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2778 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2779 (u32)(bus_addr >> 32)); 2780 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2781 (u32)bus_addr); 2782 /* Init the HEAD/TAIL indices */ 2783 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2784 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2785 2786 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2787 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2788 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2789 2790 txdctl = 0; /* clear txdctl */ 2791 txdctl |= 0x1f; /* PTHRESH */ 2792 txdctl |= 1 << 8; /* HTHRESH */ 2793 txdctl |= 1 << 16;/* WTHRESH */ 2794 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2795 txdctl |= E1000_TXDCTL_GRAN; 2796 txdctl |= 1 << 25; /* LWTHRESH */ 2797 2798 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2799 } 2800 2801 /* Set the default values for the Tx Inter Packet Gap timer */ 2802 switch (adapter->hw.mac.type) { 2803 case e1000_80003es2lan: 2804 tipg = DEFAULT_82543_TIPG_IPGR1; 2805 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2806 E1000_TIPG_IPGR2_SHIFT; 2807 break; 2808 case e1000_82542: 2809 tipg = DEFAULT_82542_TIPG_IPGT; 2810 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2811 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2812 break; 2813 default: 2814 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2815 (adapter->hw.phy.media_type == 2816 e1000_media_type_internal_serdes)) 2817 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2818 else 2819 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2820 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2821 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2822 } 2823 2824 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2825 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 2826 2827 if(adapter->hw.mac.type >= e1000_82540) 2828 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 2829 adapter->tx_abs_int_delay.value); 2830 2831 if ((adapter->hw.mac.type == e1000_82571) || 2832 (adapter->hw.mac.type == e1000_82572)) { 2833 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2834 tarc |= TARC_SPEED_MODE_BIT; 2835 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2836 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2837 /* errata: program both queues to unweighted RR */ 2838 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2839 tarc |= 1; 2840 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2841 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2842 tarc |= 1; 2843 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2844 } else if (adapter->hw.mac.type == e1000_82574) { 2845 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2846 tarc |= TARC_ERRATA_BIT; 2847 if ( adapter->tx_num_queues > 1) { 2848 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 2849 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2850 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2851 } else 2852 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2853 } 2854 2855 if (adapter->tx_int_delay.value > 0) 2856 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2857 2858 /* Program the Transmit Control Register */ 2859 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2860 tctl &= ~E1000_TCTL_CT; 2861 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2862 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 2863 2864 if (adapter->hw.mac.type >= e1000_82571) 2865 tctl |= E1000_TCTL_MULR; 2866 2867 /* This write will effectively turn on the transmit unit. */ 2868 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2869 2870 if (hw->mac.type == e1000_pch_spt) { 2871 u32 reg; 2872 reg = E1000_READ_REG(hw, E1000_IOSFPC); 2873 reg |= E1000_RCTL_RDMTS_HEX; 2874 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 2875 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2876 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 2877 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2878 } 2879 } 2880 2881 /********************************************************************* 2882 * 2883 * Enable receive unit. 2884 * 2885 **********************************************************************/ 2886 2887 static void 2888 em_initialize_receive_unit(if_ctx_t ctx) 2889 { 2890 struct adapter *adapter = iflib_get_softc(ctx); 2891 if_softc_ctx_t scctx = adapter->shared; 2892 struct ifnet *ifp = iflib_get_ifp(ctx); 2893 struct e1000_hw *hw = &adapter->hw; 2894 struct em_rx_queue *que; 2895 int i; 2896 u32 rctl, rxcsum, rfctl; 2897 2898 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 2899 2900 /* 2901 * Make sure receives are disabled while setting 2902 * up the descriptor ring 2903 */ 2904 rctl = E1000_READ_REG(hw, E1000_RCTL); 2905 /* Do not disable if ever enabled on this hardware */ 2906 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 2907 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2908 2909 /* Setup the Receive Control Register */ 2910 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2911 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 2912 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 2913 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2914 2915 /* Do not store bad packets */ 2916 rctl &= ~E1000_RCTL_SBP; 2917 2918 /* Enable Long Packet receive */ 2919 if (if_getmtu(ifp) > ETHERMTU) 2920 rctl |= E1000_RCTL_LPE; 2921 else 2922 rctl &= ~E1000_RCTL_LPE; 2923 2924 /* Strip the CRC */ 2925 if (!em_disable_crc_stripping) 2926 rctl |= E1000_RCTL_SECRC; 2927 2928 if (adapter->hw.mac.type >= e1000_82540) { 2929 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 2930 adapter->rx_abs_int_delay.value); 2931 2932 /* 2933 * Set the interrupt throttling rate. Value is calculated 2934 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2935 */ 2936 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 2937 } 2938 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 2939 adapter->rx_int_delay.value); 2940 2941 /* Use extended rx descriptor formats */ 2942 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2943 rfctl |= E1000_RFCTL_EXTEN; 2944 /* 2945 ** When using MSIX interrupts we need to throttle 2946 ** using the EITR register (82574 only) 2947 */ 2948 if (hw->mac.type == e1000_82574) { 2949 for (int i = 0; i < 4; i++) 2950 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 2951 DEFAULT_ITR); 2952 /* Disable accelerated acknowledge */ 2953 rfctl |= E1000_RFCTL_ACK_DIS; 2954 } 2955 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2956 2957 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2958 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 2959 adapter->hw.mac.type >= e1000_82543) { 2960 if (adapter->tx_num_queues > 1) { 2961 if (adapter->hw.mac.type >= igb_mac_min) { 2962 rxcsum |= E1000_RXCSUM_PCSD; 2963 if (hw->mac.type != e1000_82575) 2964 rxcsum |= E1000_RXCSUM_CRCOFL; 2965 } else 2966 rxcsum |= E1000_RXCSUM_TUOFL | 2967 E1000_RXCSUM_IPOFL | 2968 E1000_RXCSUM_PCSD; 2969 } else { 2970 if (adapter->hw.mac.type >= igb_mac_min) 2971 rxcsum |= E1000_RXCSUM_IPPCSE; 2972 else 2973 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 2974 if (adapter->hw.mac.type > e1000_82575) 2975 rxcsum |= E1000_RXCSUM_CRCOFL; 2976 } 2977 } else 2978 rxcsum &= ~E1000_RXCSUM_TUOFL; 2979 2980 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2981 2982 if (adapter->rx_num_queues > 1) { 2983 if (adapter->hw.mac.type >= igb_mac_min) 2984 igb_initialize_rss_mapping(adapter); 2985 else 2986 em_initialize_rss_mapping(adapter); 2987 } 2988 2989 /* 2990 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 2991 ** long latencies are observed, like Lenovo X60. This 2992 ** change eliminates the problem, but since having positive 2993 ** values in RDTR is a known source of problems on other 2994 ** platforms another solution is being sought. 2995 */ 2996 if (hw->mac.type == e1000_82573) 2997 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 2998 2999 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3000 struct rx_ring *rxr = &que->rxr; 3001 /* Setup the Base and Length of the Rx Descriptor Ring */ 3002 u64 bus_addr = rxr->rx_paddr; 3003 #if 0 3004 u32 rdt = adapter->rx_num_queues -1; /* default */ 3005 #endif 3006 3007 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3008 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3009 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3010 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3011 /* Setup the Head and Tail Descriptor Pointers */ 3012 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3013 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3014 } 3015 3016 /* 3017 * Set PTHRESH for improved jumbo performance 3018 * According to 10.2.5.11 of Intel 82574 Datasheet, 3019 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3020 * Only write to RXDCTL(1) if there is a need for different 3021 * settings. 3022 */ 3023 3024 if (((adapter->hw.mac.type == e1000_ich9lan) || 3025 (adapter->hw.mac.type == e1000_pch2lan) || 3026 (adapter->hw.mac.type == e1000_ich10lan)) && 3027 (if_getmtu(ifp) > ETHERMTU)) { 3028 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3029 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3030 } else if (adapter->hw.mac.type == e1000_82574) { 3031 for (int i = 0; i < adapter->rx_num_queues; i++) { 3032 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3033 rxdctl |= 0x20; /* PTHRESH */ 3034 rxdctl |= 4 << 8; /* HTHRESH */ 3035 rxdctl |= 4 << 16;/* WTHRESH */ 3036 rxdctl |= 1 << 24; /* Switch to granularity */ 3037 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3038 } 3039 } else if (adapter->hw.mac.type >= igb_mac_min) { 3040 u32 psize, srrctl = 0; 3041 3042 if (if_getmtu(ifp) > ETHERMTU) { 3043 /* Set maximum packet len */ 3044 psize = scctx->isc_max_frame_size; 3045 if (psize <= 4096) { 3046 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3047 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3048 } else if (psize > 4096) { 3049 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3050 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3051 } 3052 3053 /* are we on a vlan? */ 3054 if (ifp->if_vlantrunk != NULL) 3055 psize += VLAN_TAG_SIZE; 3056 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3057 } else { 3058 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3059 rctl |= E1000_RCTL_SZ_2048; 3060 } 3061 3062 /* 3063 * If TX flow control is disabled and there's >1 queue defined, 3064 * enable DROP. 3065 * 3066 * This drops frames rather than hanging the RX MAC for all queues. 3067 */ 3068 if ((adapter->rx_num_queues > 1) && 3069 (adapter->fc == e1000_fc_none || 3070 adapter->fc == e1000_fc_rx_pause)) { 3071 srrctl |= E1000_SRRCTL_DROP_EN; 3072 } 3073 /* Setup the Base and Length of the Rx Descriptor Rings */ 3074 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3075 struct rx_ring *rxr = &que->rxr; 3076 u64 bus_addr = rxr->rx_paddr; 3077 u32 rxdctl; 3078 3079 #ifdef notyet 3080 /* Configure for header split? -- ignore for now */ 3081 rxr->hdr_split = igb_header_split; 3082 #else 3083 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3084 #endif 3085 3086 3087 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3088 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3089 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3090 (uint32_t)(bus_addr >> 32)); 3091 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3092 (uint32_t)bus_addr); 3093 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3094 /* Enable this Queue */ 3095 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3096 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3097 rxdctl &= 0xFFF00000; 3098 rxdctl |= IGB_RX_PTHRESH; 3099 rxdctl |= IGB_RX_HTHRESH << 8; 3100 rxdctl |= IGB_RX_WTHRESH << 16; 3101 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3102 } 3103 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3104 if (if_getmtu(ifp) > ETHERMTU) 3105 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3106 else 3107 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3108 } 3109 3110 /* Make sure VLAN Filters are off */ 3111 rctl &= ~E1000_RCTL_VFE; 3112 3113 if (adapter->hw.mac.type < igb_mac_min) { 3114 if (adapter->rx_mbuf_sz == MCLBYTES) 3115 rctl |= E1000_RCTL_SZ_2048; 3116 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3117 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3118 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3119 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3120 3121 /* ensure we clear use DTYPE of 00 here */ 3122 rctl &= ~0x00000C00; 3123 } 3124 3125 /* Write out the settings */ 3126 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3127 3128 return; 3129 } 3130 3131 static void 3132 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3133 { 3134 struct adapter *adapter = iflib_get_softc(ctx); 3135 u32 index, bit; 3136 3137 index = (vtag >> 5) & 0x7F; 3138 bit = vtag & 0x1F; 3139 adapter->shadow_vfta[index] |= (1 << bit); 3140 ++adapter->num_vlans; 3141 } 3142 3143 static void 3144 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3145 { 3146 struct adapter *adapter = iflib_get_softc(ctx); 3147 u32 index, bit; 3148 3149 index = (vtag >> 5) & 0x7F; 3150 bit = vtag & 0x1F; 3151 adapter->shadow_vfta[index] &= ~(1 << bit); 3152 --adapter->num_vlans; 3153 } 3154 3155 static void 3156 em_setup_vlan_hw_support(struct adapter *adapter) 3157 { 3158 struct e1000_hw *hw = &adapter->hw; 3159 u32 reg; 3160 3161 /* 3162 ** We get here thru init_locked, meaning 3163 ** a soft reset, this has already cleared 3164 ** the VFTA and other state, so if there 3165 ** have been no vlan's registered do nothing. 3166 */ 3167 if (adapter->num_vlans == 0) 3168 return; 3169 3170 /* 3171 ** A soft reset zero's out the VFTA, so 3172 ** we need to repopulate it now. 3173 */ 3174 for (int i = 0; i < EM_VFTA_SIZE; i++) 3175 if (adapter->shadow_vfta[i] != 0) 3176 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3177 i, adapter->shadow_vfta[i]); 3178 3179 reg = E1000_READ_REG(hw, E1000_CTRL); 3180 reg |= E1000_CTRL_VME; 3181 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3182 3183 /* Enable the Filter Table */ 3184 reg = E1000_READ_REG(hw, E1000_RCTL); 3185 reg &= ~E1000_RCTL_CFIEN; 3186 reg |= E1000_RCTL_VFE; 3187 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3188 } 3189 3190 static void 3191 em_if_enable_intr(if_ctx_t ctx) 3192 { 3193 struct adapter *adapter = iflib_get_softc(ctx); 3194 struct e1000_hw *hw = &adapter->hw; 3195 u32 ims_mask = IMS_ENABLE_MASK; 3196 3197 if (hw->mac.type == e1000_82574) { 3198 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3199 ims_mask |= adapter->ims; 3200 } if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3201 u32 mask = (adapter->que_mask | adapter->link_mask); 3202 3203 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3204 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3205 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3206 ims_mask = E1000_IMS_LSC; 3207 } 3208 3209 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3210 } 3211 3212 static void 3213 em_if_disable_intr(if_ctx_t ctx) 3214 { 3215 struct adapter *adapter = iflib_get_softc(ctx); 3216 struct e1000_hw *hw = &adapter->hw; 3217 3218 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3219 if (hw->mac.type >= igb_mac_min) 3220 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3221 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3222 } 3223 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3224 } 3225 3226 /* 3227 * Bit of a misnomer, what this really means is 3228 * to enable OS management of the system... aka 3229 * to disable special hardware management features 3230 */ 3231 static void 3232 em_init_manageability(struct adapter *adapter) 3233 { 3234 /* A shared code workaround */ 3235 #define E1000_82542_MANC2H E1000_MANC2H 3236 if (adapter->has_manage) { 3237 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3238 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3239 3240 /* disable hardware interception of ARP */ 3241 manc &= ~(E1000_MANC_ARP_EN); 3242 3243 /* enable receiving management packets to the host */ 3244 manc |= E1000_MANC_EN_MNG2HOST; 3245 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3246 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3247 manc2h |= E1000_MNG2HOST_PORT_623; 3248 manc2h |= E1000_MNG2HOST_PORT_664; 3249 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3250 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3251 } 3252 } 3253 3254 /* 3255 * Give control back to hardware management 3256 * controller if there is one. 3257 */ 3258 static void 3259 em_release_manageability(struct adapter *adapter) 3260 { 3261 if (adapter->has_manage) { 3262 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3263 3264 /* re-enable hardware interception of ARP */ 3265 manc |= E1000_MANC_ARP_EN; 3266 manc &= ~E1000_MANC_EN_MNG2HOST; 3267 3268 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3269 } 3270 } 3271 3272 /* 3273 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3274 * For ASF and Pass Through versions of f/w this means 3275 * that the driver is loaded. For AMT version type f/w 3276 * this means that the network i/f is open. 3277 */ 3278 static void 3279 em_get_hw_control(struct adapter *adapter) 3280 { 3281 u32 ctrl_ext, swsm; 3282 3283 if (adapter->hw.mac.type == e1000_82573) { 3284 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3285 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3286 swsm | E1000_SWSM_DRV_LOAD); 3287 return; 3288 } 3289 /* else */ 3290 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3291 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3292 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3293 return; 3294 } 3295 3296 /* 3297 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3298 * For ASF and Pass Through versions of f/w this means that 3299 * the driver is no longer loaded. For AMT versions of the 3300 * f/w this means that the network i/f is closed. 3301 */ 3302 static void 3303 em_release_hw_control(struct adapter *adapter) 3304 { 3305 u32 ctrl_ext, swsm; 3306 3307 if (!adapter->has_manage) 3308 return; 3309 3310 if (adapter->hw.mac.type == e1000_82573) { 3311 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3312 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3313 swsm & ~E1000_SWSM_DRV_LOAD); 3314 return; 3315 } 3316 /* else */ 3317 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3318 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3319 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3320 return; 3321 } 3322 3323 static int 3324 em_is_valid_ether_addr(u8 *addr) 3325 { 3326 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3327 3328 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3329 return (FALSE); 3330 } 3331 3332 return (TRUE); 3333 } 3334 3335 /* 3336 ** Parse the interface capabilities with regard 3337 ** to both system management and wake-on-lan for 3338 ** later use. 3339 */ 3340 static void 3341 em_get_wakeup(if_ctx_t ctx) 3342 { 3343 struct adapter *adapter = iflib_get_softc(ctx); 3344 device_t dev = iflib_get_dev(ctx); 3345 u16 eeprom_data = 0, device_id, apme_mask; 3346 3347 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3348 apme_mask = EM_EEPROM_APME; 3349 3350 switch (adapter->hw.mac.type) { 3351 case e1000_82542: 3352 case e1000_82543: 3353 break; 3354 case e1000_82544: 3355 e1000_read_nvm(&adapter->hw, 3356 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3357 apme_mask = EM_82544_APME; 3358 break; 3359 case e1000_82546: 3360 case e1000_82546_rev_3: 3361 if (adapter->hw.bus.func == 1) { 3362 e1000_read_nvm(&adapter->hw, 3363 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3364 break; 3365 } else 3366 e1000_read_nvm(&adapter->hw, 3367 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3368 break; 3369 case e1000_82573: 3370 case e1000_82583: 3371 adapter->has_amt = TRUE; 3372 /* Falls thru */ 3373 case e1000_82571: 3374 case e1000_82572: 3375 case e1000_80003es2lan: 3376 if (adapter->hw.bus.func == 1) { 3377 e1000_read_nvm(&adapter->hw, 3378 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3379 break; 3380 } else 3381 e1000_read_nvm(&adapter->hw, 3382 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3383 break; 3384 case e1000_ich8lan: 3385 case e1000_ich9lan: 3386 case e1000_ich10lan: 3387 case e1000_pchlan: 3388 case e1000_pch2lan: 3389 case e1000_pch_lpt: 3390 case e1000_pch_spt: 3391 case e1000_82575: /* listing all igb devices */ 3392 case e1000_82576: 3393 case e1000_82580: 3394 case e1000_i350: 3395 case e1000_i354: 3396 case e1000_i210: 3397 case e1000_i211: 3398 case e1000_vfadapt: 3399 case e1000_vfadapt_i350: 3400 apme_mask = E1000_WUC_APME; 3401 adapter->has_amt = TRUE; 3402 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3403 break; 3404 default: 3405 e1000_read_nvm(&adapter->hw, 3406 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3407 break; 3408 } 3409 if (eeprom_data & apme_mask) 3410 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3411 /* 3412 * We have the eeprom settings, now apply the special cases 3413 * where the eeprom may be wrong or the board won't support 3414 * wake on lan on a particular port 3415 */ 3416 device_id = pci_get_device(dev); 3417 switch (device_id) { 3418 case E1000_DEV_ID_82546GB_PCIE: 3419 adapter->wol = 0; 3420 break; 3421 case E1000_DEV_ID_82546EB_FIBER: 3422 case E1000_DEV_ID_82546GB_FIBER: 3423 /* Wake events only supported on port A for dual fiber 3424 * regardless of eeprom setting */ 3425 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3426 E1000_STATUS_FUNC_1) 3427 adapter->wol = 0; 3428 break; 3429 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3430 /* if quad port adapter, disable WoL on all but port A */ 3431 if (global_quad_port_a != 0) 3432 adapter->wol = 0; 3433 /* Reset for multiple quad port adapters */ 3434 if (++global_quad_port_a == 4) 3435 global_quad_port_a = 0; 3436 break; 3437 case E1000_DEV_ID_82571EB_FIBER: 3438 /* Wake events only supported on port A for dual fiber 3439 * regardless of eeprom setting */ 3440 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3441 E1000_STATUS_FUNC_1) 3442 adapter->wol = 0; 3443 break; 3444 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3445 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3446 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3447 /* if quad port adapter, disable WoL on all but port A */ 3448 if (global_quad_port_a != 0) 3449 adapter->wol = 0; 3450 /* Reset for multiple quad port adapters */ 3451 if (++global_quad_port_a == 4) 3452 global_quad_port_a = 0; 3453 break; 3454 } 3455 return; 3456 } 3457 3458 3459 /* 3460 * Enable PCI Wake On Lan capability 3461 */ 3462 static void 3463 em_enable_wakeup(if_ctx_t ctx) 3464 { 3465 struct adapter *adapter = iflib_get_softc(ctx); 3466 device_t dev = iflib_get_dev(ctx); 3467 if_t ifp = iflib_get_ifp(ctx); 3468 u32 pmc, ctrl, ctrl_ext, rctl, wuc; 3469 u16 status; 3470 3471 if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) 3472 return; 3473 3474 /* Advertise the wakeup capability */ 3475 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3476 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3477 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3478 wuc = E1000_READ_REG(&adapter->hw, E1000_WUC); 3479 wuc |= (E1000_WUC_PME_EN | E1000_WUC_APME); 3480 E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc); 3481 3482 if ((adapter->hw.mac.type == e1000_ich8lan) || 3483 (adapter->hw.mac.type == e1000_pchlan) || 3484 (adapter->hw.mac.type == e1000_ich9lan) || 3485 (adapter->hw.mac.type == e1000_ich10lan)) 3486 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3487 3488 /* Keep the laser running on Fiber adapters */ 3489 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3490 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3491 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3492 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3493 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3494 } 3495 3496 /* 3497 ** Determine type of Wakeup: note that wol 3498 ** is set with all bits on by default. 3499 */ 3500 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3501 adapter->wol &= ~E1000_WUFC_MAG; 3502 3503 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3504 adapter->wol &= ~E1000_WUFC_EX; 3505 3506 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3507 adapter->wol &= ~E1000_WUFC_MC; 3508 else { 3509 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3510 rctl |= E1000_RCTL_MPE; 3511 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3512 } 3513 3514 if ( adapter->hw.mac.type >= e1000_pchlan) { 3515 if (em_enable_phy_wakeup(adapter)) 3516 return; 3517 } else { 3518 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3519 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3520 } 3521 3522 if (adapter->hw.phy.type == e1000_phy_igp_3) 3523 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3524 3525 /* Request PME */ 3526 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3527 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3528 if (if_getcapenable(ifp) & IFCAP_WOL) 3529 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3530 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3531 3532 return; 3533 } 3534 3535 /* 3536 ** WOL in the newer chipset interfaces (pchlan) 3537 ** require thing to be copied into the phy 3538 */ 3539 static int 3540 em_enable_phy_wakeup(struct adapter *adapter) 3541 { 3542 struct e1000_hw *hw = &adapter->hw; 3543 u32 mreg, ret = 0; 3544 u16 preg; 3545 3546 /* copy MAC RARs to PHY RARs */ 3547 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3548 3549 /* copy MAC MTA to PHY MTA */ 3550 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3551 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3552 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3553 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3554 (u16)((mreg >> 16) & 0xFFFF)); 3555 } 3556 3557 /* configure PHY Rx Control register */ 3558 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3559 mreg = E1000_READ_REG(hw, E1000_RCTL); 3560 if (mreg & E1000_RCTL_UPE) 3561 preg |= BM_RCTL_UPE; 3562 if (mreg & E1000_RCTL_MPE) 3563 preg |= BM_RCTL_MPE; 3564 preg &= ~(BM_RCTL_MO_MASK); 3565 if (mreg & E1000_RCTL_MO_3) 3566 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3567 << BM_RCTL_MO_SHIFT); 3568 if (mreg & E1000_RCTL_BAM) 3569 preg |= BM_RCTL_BAM; 3570 if (mreg & E1000_RCTL_PMCF) 3571 preg |= BM_RCTL_PMCF; 3572 mreg = E1000_READ_REG(hw, E1000_CTRL); 3573 if (mreg & E1000_CTRL_RFCE) 3574 preg |= BM_RCTL_RFCE; 3575 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3576 3577 /* enable PHY wakeup in MAC register */ 3578 E1000_WRITE_REG(hw, E1000_WUC, 3579 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3580 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3581 3582 /* configure and enable PHY wakeup in PHY registers */ 3583 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3584 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3585 3586 /* activate PHY wakeup */ 3587 ret = hw->phy.ops.acquire(hw); 3588 if (ret) { 3589 printf("Could not acquire PHY\n"); 3590 return ret; 3591 } 3592 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3593 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3594 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3595 if (ret) { 3596 printf("Could not read PHY page 769\n"); 3597 goto out; 3598 } 3599 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3600 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3601 if (ret) 3602 printf("Could not set PHY Host Wakeup bit\n"); 3603 out: 3604 hw->phy.ops.release(hw); 3605 3606 return ret; 3607 } 3608 3609 static void 3610 em_if_led_func(if_ctx_t ctx, int onoff) 3611 { 3612 struct adapter *adapter = iflib_get_softc(ctx); 3613 3614 if (onoff) { 3615 e1000_setup_led(&adapter->hw); 3616 e1000_led_on(&adapter->hw); 3617 } else { 3618 e1000_led_off(&adapter->hw); 3619 e1000_cleanup_led(&adapter->hw); 3620 } 3621 } 3622 3623 /* 3624 ** Disable the L0S and L1 LINK states 3625 */ 3626 static void 3627 em_disable_aspm(struct adapter *adapter) 3628 { 3629 int base, reg; 3630 u16 link_cap,link_ctrl; 3631 device_t dev = adapter->dev; 3632 3633 switch (adapter->hw.mac.type) { 3634 case e1000_82573: 3635 case e1000_82574: 3636 case e1000_82583: 3637 break; 3638 default: 3639 return; 3640 } 3641 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3642 return; 3643 reg = base + PCIER_LINK_CAP; 3644 link_cap = pci_read_config(dev, reg, 2); 3645 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3646 return; 3647 reg = base + PCIER_LINK_CTL; 3648 link_ctrl = pci_read_config(dev, reg, 2); 3649 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3650 pci_write_config(dev, reg, link_ctrl, 2); 3651 return; 3652 } 3653 3654 /********************************************************************** 3655 * 3656 * Update the board statistics counters. 3657 * 3658 **********************************************************************/ 3659 static void 3660 em_update_stats_counters(struct adapter *adapter) 3661 { 3662 3663 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3664 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3665 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3666 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3667 } 3668 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3669 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3670 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3671 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3672 3673 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3674 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3675 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3676 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3677 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3678 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3679 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3680 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3681 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3682 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3683 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3684 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3685 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3686 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3687 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3688 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3689 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3690 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3691 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3692 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3693 3694 /* For the 64-bit byte counters the low dword must be read first. */ 3695 /* Both registers clear on the read of the high dword */ 3696 3697 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3698 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3699 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3700 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3701 3702 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3703 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3704 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3705 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3706 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3707 3708 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3709 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3710 3711 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3712 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3713 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3714 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3715 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3716 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3717 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3718 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3719 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3720 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3721 3722 /* Interrupt Counts */ 3723 3724 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3725 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3726 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3727 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3728 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3729 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3730 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3731 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3732 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3733 3734 if (adapter->hw.mac.type >= e1000_82543) { 3735 adapter->stats.algnerrc += 3736 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3737 adapter->stats.rxerrc += 3738 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3739 adapter->stats.tncrs += 3740 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3741 adapter->stats.cexterr += 3742 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3743 adapter->stats.tsctc += 3744 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3745 adapter->stats.tsctfc += 3746 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3747 } 3748 } 3749 3750 static uint64_t 3751 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3752 { 3753 struct adapter *adapter = iflib_get_softc(ctx); 3754 struct ifnet *ifp = iflib_get_ifp(ctx); 3755 3756 switch (cnt) { 3757 case IFCOUNTER_COLLISIONS: 3758 return (adapter->stats.colc); 3759 case IFCOUNTER_IERRORS: 3760 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3761 adapter->stats.crcerrs + adapter->stats.algnerrc + 3762 adapter->stats.ruc + adapter->stats.roc + 3763 adapter->stats.mpc + adapter->stats.cexterr); 3764 case IFCOUNTER_OERRORS: 3765 return (adapter->stats.ecol + adapter->stats.latecol + 3766 adapter->watchdog_events); 3767 default: 3768 return (if_get_counter_default(ifp, cnt)); 3769 } 3770 } 3771 3772 /* Export a single 32-bit register via a read-only sysctl. */ 3773 static int 3774 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3775 { 3776 struct adapter *adapter; 3777 u_int val; 3778 3779 adapter = oidp->oid_arg1; 3780 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3781 return (sysctl_handle_int(oidp, &val, 0, req)); 3782 } 3783 3784 /* 3785 * Add sysctl variables, one per statistic, to the system. 3786 */ 3787 static void 3788 em_add_hw_stats(struct adapter *adapter) 3789 { 3790 device_t dev = iflib_get_dev(adapter->ctx); 3791 struct em_tx_queue *tx_que = adapter->tx_queues; 3792 struct em_rx_queue *rx_que = adapter->rx_queues; 3793 3794 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3795 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3796 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3797 struct e1000_hw_stats *stats = &adapter->stats; 3798 3799 struct sysctl_oid *stat_node, *queue_node, *int_node; 3800 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3801 3802 #define QUEUE_NAME_LEN 32 3803 char namebuf[QUEUE_NAME_LEN]; 3804 3805 /* Driver Statistics */ 3806 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3807 CTLFLAG_RD, &adapter->dropped_pkts, 3808 "Driver dropped packets"); 3809 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3810 CTLFLAG_RD, &adapter->link_irq, 3811 "Link MSIX IRQ Handled"); 3812 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 3813 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 3814 "Defragmenting mbuf chain failed"); 3815 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 3816 CTLFLAG_RD, &adapter->no_tx_dma_setup, 3817 "Driver tx dma failure in xmit"); 3818 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3819 CTLFLAG_RD, &adapter->rx_overruns, 3820 "RX overruns"); 3821 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 3822 CTLFLAG_RD, &adapter->watchdog_events, 3823 "Watchdog timeouts"); 3824 3825 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 3826 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 3827 em_sysctl_reg_handler, "IU", 3828 "Device Control Register"); 3829 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 3830 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 3831 em_sysctl_reg_handler, "IU", 3832 "Receiver Control Register"); 3833 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 3834 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 3835 "Flow Control High Watermark"); 3836 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 3837 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 3838 "Flow Control Low Watermark"); 3839 3840 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3841 struct tx_ring *txr = &tx_que->txr; 3842 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 3843 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3844 CTLFLAG_RD, NULL, "TX Queue Name"); 3845 queue_list = SYSCTL_CHILDREN(queue_node); 3846 3847 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 3848 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3849 E1000_TDH(txr->me), 3850 em_sysctl_reg_handler, "IU", 3851 "Transmit Descriptor Head"); 3852 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 3853 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3854 E1000_TDT(txr->me), 3855 em_sysctl_reg_handler, "IU", 3856 "Transmit Descriptor Tail"); 3857 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 3858 CTLFLAG_RD, &txr->tx_irq, 3859 "Queue MSI-X Transmit Interrupts"); 3860 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "no_desc_avail", 3861 CTLFLAG_RD, &txr->no_desc_avail, 3862 "Queue No Descriptor Available"); 3863 } 3864 3865 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 3866 struct rx_ring *rxr = &rx_que->rxr; 3867 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 3868 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3869 CTLFLAG_RD, NULL, "RX Queue Name"); 3870 queue_list = SYSCTL_CHILDREN(queue_node); 3871 3872 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 3873 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3874 E1000_RDH(rxr->me), 3875 em_sysctl_reg_handler, "IU", 3876 "Receive Descriptor Head"); 3877 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 3878 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3879 E1000_RDT(rxr->me), 3880 em_sysctl_reg_handler, "IU", 3881 "Receive Descriptor Tail"); 3882 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 3883 CTLFLAG_RD, &rxr->rx_irq, 3884 "Queue MSI-X Receive Interrupts"); 3885 } 3886 3887 /* MAC stats get their own sub node */ 3888 3889 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 3890 CTLFLAG_RD, NULL, "Statistics"); 3891 stat_list = SYSCTL_CHILDREN(stat_node); 3892 3893 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 3894 CTLFLAG_RD, &stats->ecol, 3895 "Excessive collisions"); 3896 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 3897 CTLFLAG_RD, &stats->scc, 3898 "Single collisions"); 3899 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 3900 CTLFLAG_RD, &stats->mcc, 3901 "Multiple collisions"); 3902 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 3903 CTLFLAG_RD, &stats->latecol, 3904 "Late collisions"); 3905 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 3906 CTLFLAG_RD, &stats->colc, 3907 "Collision Count"); 3908 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 3909 CTLFLAG_RD, &adapter->stats.symerrs, 3910 "Symbol Errors"); 3911 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 3912 CTLFLAG_RD, &adapter->stats.sec, 3913 "Sequence Errors"); 3914 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 3915 CTLFLAG_RD, &adapter->stats.dc, 3916 "Defer Count"); 3917 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 3918 CTLFLAG_RD, &adapter->stats.mpc, 3919 "Missed Packets"); 3920 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 3921 CTLFLAG_RD, &adapter->stats.rnbc, 3922 "Receive No Buffers"); 3923 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 3924 CTLFLAG_RD, &adapter->stats.ruc, 3925 "Receive Undersize"); 3926 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 3927 CTLFLAG_RD, &adapter->stats.rfc, 3928 "Fragmented Packets Received "); 3929 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 3930 CTLFLAG_RD, &adapter->stats.roc, 3931 "Oversized Packets Received"); 3932 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 3933 CTLFLAG_RD, &adapter->stats.rjc, 3934 "Recevied Jabber"); 3935 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 3936 CTLFLAG_RD, &adapter->stats.rxerrc, 3937 "Receive Errors"); 3938 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 3939 CTLFLAG_RD, &adapter->stats.crcerrs, 3940 "CRC errors"); 3941 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 3942 CTLFLAG_RD, &adapter->stats.algnerrc, 3943 "Alignment Errors"); 3944 /* On 82575 these are collision counts */ 3945 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 3946 CTLFLAG_RD, &adapter->stats.cexterr, 3947 "Collision/Carrier extension errors"); 3948 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 3949 CTLFLAG_RD, &adapter->stats.xonrxc, 3950 "XON Received"); 3951 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 3952 CTLFLAG_RD, &adapter->stats.xontxc, 3953 "XON Transmitted"); 3954 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 3955 CTLFLAG_RD, &adapter->stats.xoffrxc, 3956 "XOFF Received"); 3957 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 3958 CTLFLAG_RD, &adapter->stats.xofftxc, 3959 "XOFF Transmitted"); 3960 3961 /* Packet Reception Stats */ 3962 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 3963 CTLFLAG_RD, &adapter->stats.tpr, 3964 "Total Packets Received "); 3965 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 3966 CTLFLAG_RD, &adapter->stats.gprc, 3967 "Good Packets Received"); 3968 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 3969 CTLFLAG_RD, &adapter->stats.bprc, 3970 "Broadcast Packets Received"); 3971 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 3972 CTLFLAG_RD, &adapter->stats.mprc, 3973 "Multicast Packets Received"); 3974 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 3975 CTLFLAG_RD, &adapter->stats.prc64, 3976 "64 byte frames received "); 3977 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 3978 CTLFLAG_RD, &adapter->stats.prc127, 3979 "65-127 byte frames received"); 3980 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 3981 CTLFLAG_RD, &adapter->stats.prc255, 3982 "128-255 byte frames received"); 3983 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 3984 CTLFLAG_RD, &adapter->stats.prc511, 3985 "256-511 byte frames received"); 3986 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 3987 CTLFLAG_RD, &adapter->stats.prc1023, 3988 "512-1023 byte frames received"); 3989 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 3990 CTLFLAG_RD, &adapter->stats.prc1522, 3991 "1023-1522 byte frames received"); 3992 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 3993 CTLFLAG_RD, &adapter->stats.gorc, 3994 "Good Octets Received"); 3995 3996 /* Packet Transmission Stats */ 3997 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 3998 CTLFLAG_RD, &adapter->stats.gotc, 3999 "Good Octets Transmitted"); 4000 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4001 CTLFLAG_RD, &adapter->stats.tpt, 4002 "Total Packets Transmitted"); 4003 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4004 CTLFLAG_RD, &adapter->stats.gptc, 4005 "Good Packets Transmitted"); 4006 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4007 CTLFLAG_RD, &adapter->stats.bptc, 4008 "Broadcast Packets Transmitted"); 4009 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4010 CTLFLAG_RD, &adapter->stats.mptc, 4011 "Multicast Packets Transmitted"); 4012 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4013 CTLFLAG_RD, &adapter->stats.ptc64, 4014 "64 byte frames transmitted "); 4015 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4016 CTLFLAG_RD, &adapter->stats.ptc127, 4017 "65-127 byte frames transmitted"); 4018 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4019 CTLFLAG_RD, &adapter->stats.ptc255, 4020 "128-255 byte frames transmitted"); 4021 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4022 CTLFLAG_RD, &adapter->stats.ptc511, 4023 "256-511 byte frames transmitted"); 4024 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4025 CTLFLAG_RD, &adapter->stats.ptc1023, 4026 "512-1023 byte frames transmitted"); 4027 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4028 CTLFLAG_RD, &adapter->stats.ptc1522, 4029 "1024-1522 byte frames transmitted"); 4030 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4031 CTLFLAG_RD, &adapter->stats.tsctc, 4032 "TSO Contexts Transmitted"); 4033 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4034 CTLFLAG_RD, &adapter->stats.tsctfc, 4035 "TSO Contexts Failed"); 4036 4037 4038 /* Interrupt Stats */ 4039 4040 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4041 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4042 int_list = SYSCTL_CHILDREN(int_node); 4043 4044 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4045 CTLFLAG_RD, &adapter->stats.iac, 4046 "Interrupt Assertion Count"); 4047 4048 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4049 CTLFLAG_RD, &adapter->stats.icrxptc, 4050 "Interrupt Cause Rx Pkt Timer Expire Count"); 4051 4052 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4053 CTLFLAG_RD, &adapter->stats.icrxatc, 4054 "Interrupt Cause Rx Abs Timer Expire Count"); 4055 4056 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4057 CTLFLAG_RD, &adapter->stats.ictxptc, 4058 "Interrupt Cause Tx Pkt Timer Expire Count"); 4059 4060 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4061 CTLFLAG_RD, &adapter->stats.ictxatc, 4062 "Interrupt Cause Tx Abs Timer Expire Count"); 4063 4064 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4065 CTLFLAG_RD, &adapter->stats.ictxqec, 4066 "Interrupt Cause Tx Queue Empty Count"); 4067 4068 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4069 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4070 "Interrupt Cause Tx Queue Min Thresh Count"); 4071 4072 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4073 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4074 "Interrupt Cause Rx Desc Min Thresh Count"); 4075 4076 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4077 CTLFLAG_RD, &adapter->stats.icrxoc, 4078 "Interrupt Cause Receiver Overrun Count"); 4079 } 4080 4081 /********************************************************************** 4082 * 4083 * This routine provides a way to dump out the adapter eeprom, 4084 * often a useful debug/service tool. This only dumps the first 4085 * 32 words, stuff that matters is in that extent. 4086 * 4087 **********************************************************************/ 4088 static int 4089 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4090 { 4091 struct adapter *adapter = (struct adapter *)arg1; 4092 int error; 4093 int result; 4094 4095 result = -1; 4096 error = sysctl_handle_int(oidp, &result, 0, req); 4097 4098 if (error || !req->newptr) 4099 return (error); 4100 4101 /* 4102 * This value will cause a hex dump of the 4103 * first 32 16-bit words of the EEPROM to 4104 * the screen. 4105 */ 4106 if (result == 1) 4107 em_print_nvm_info(adapter); 4108 4109 return (error); 4110 } 4111 4112 static void 4113 em_print_nvm_info(struct adapter *adapter) 4114 { 4115 u16 eeprom_data; 4116 int i, j, row = 0; 4117 4118 /* Its a bit crude, but it gets the job done */ 4119 printf("\nInterface EEPROM Dump:\n"); 4120 printf("Offset\n0x0000 "); 4121 for (i = 0, j = 0; i < 32; i++, j++) { 4122 if (j == 8) { /* Make the offset block */ 4123 j = 0; ++row; 4124 printf("\n0x00%x0 ",row); 4125 } 4126 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4127 printf("%04x ", eeprom_data); 4128 } 4129 printf("\n"); 4130 } 4131 4132 static int 4133 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4134 { 4135 struct em_int_delay_info *info; 4136 struct adapter *adapter; 4137 u32 regval; 4138 int error, usecs, ticks; 4139 4140 info = (struct em_int_delay_info *)arg1; 4141 usecs = info->value; 4142 error = sysctl_handle_int(oidp, &usecs, 0, req); 4143 if (error != 0 || req->newptr == NULL) 4144 return (error); 4145 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4146 return (EINVAL); 4147 info->value = usecs; 4148 ticks = EM_USECS_TO_TICKS(usecs); 4149 if (info->offset == E1000_ITR) /* units are 256ns here */ 4150 ticks *= 4; 4151 4152 adapter = info->adapter; 4153 4154 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4155 regval = (regval & ~0xffff) | (ticks & 0xffff); 4156 /* Handle a few special cases. */ 4157 switch (info->offset) { 4158 case E1000_RDTR: 4159 break; 4160 case E1000_TIDV: 4161 if (ticks == 0) { 4162 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4163 /* Don't write 0 into the TIDV register. */ 4164 regval++; 4165 } else 4166 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4167 break; 4168 } 4169 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4170 return (0); 4171 } 4172 4173 static void 4174 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4175 const char *description, struct em_int_delay_info *info, 4176 int offset, int value) 4177 { 4178 info->adapter = adapter; 4179 info->offset = offset; 4180 info->value = value; 4181 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4182 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4183 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4184 info, 0, em_sysctl_int_delay, "I", description); 4185 } 4186 4187 static void 4188 em_set_sysctl_value(struct adapter *adapter, const char *name, 4189 const char *description, int *limit, int value) 4190 { 4191 *limit = value; 4192 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 4193 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4194 OID_AUTO, name, CTLFLAG_RW, limit, value, description); 4195 } 4196 4197 4198 /* 4199 ** Set flow control using sysctl: 4200 ** Flow control values: 4201 ** 0 - off 4202 ** 1 - rx pause 4203 ** 2 - tx pause 4204 ** 3 - full 4205 */ 4206 static int 4207 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4208 { 4209 int error; 4210 static int input = 3; /* default is full */ 4211 struct adapter *adapter = (struct adapter *) arg1; 4212 4213 error = sysctl_handle_int(oidp, &input, 0, req); 4214 4215 if ((error) || (req->newptr == NULL)) 4216 return (error); 4217 4218 if (input == adapter->fc) /* no change? */ 4219 return (error); 4220 4221 switch (input) { 4222 case e1000_fc_rx_pause: 4223 case e1000_fc_tx_pause: 4224 case e1000_fc_full: 4225 case e1000_fc_none: 4226 adapter->hw.fc.requested_mode = input; 4227 adapter->fc = input; 4228 break; 4229 default: 4230 /* Do nothing */ 4231 return (error); 4232 } 4233 4234 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4235 e1000_force_mac_fc(&adapter->hw); 4236 return (error); 4237 } 4238 4239 /* 4240 ** Manage Energy Efficient Ethernet: 4241 ** Control values: 4242 ** 0/1 - enabled/disabled 4243 */ 4244 static int 4245 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4246 { 4247 struct adapter *adapter = (struct adapter *) arg1; 4248 int error, value; 4249 4250 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4251 error = sysctl_handle_int(oidp, &value, 0, req); 4252 if (error || req->newptr == NULL) 4253 return (error); 4254 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4255 em_if_init(adapter->ctx); 4256 4257 return (0); 4258 } 4259 4260 static int 4261 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4262 { 4263 struct adapter *adapter; 4264 int error; 4265 int result; 4266 4267 result = -1; 4268 error = sysctl_handle_int(oidp, &result, 0, req); 4269 4270 if (error || !req->newptr) 4271 return (error); 4272 4273 if (result == 1) { 4274 adapter = (struct adapter *)arg1; 4275 em_print_debug_info(adapter); 4276 } 4277 4278 return (error); 4279 } 4280 4281 /* 4282 ** This routine is meant to be fluid, add whatever is 4283 ** needed for debugging a problem. -jfv 4284 */ 4285 static void 4286 em_print_debug_info(struct adapter *adapter) 4287 { 4288 device_t dev = adapter->dev; 4289 struct tx_ring *txr = &adapter->tx_queues->txr; 4290 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4291 4292 if (if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) 4293 printf("Interface is RUNNING "); 4294 else 4295 printf("Interface is NOT RUNNING\n"); 4296 4297 if (if_getdrvflags(adapter->ifp) & IFF_DRV_OACTIVE) 4298 printf("and INACTIVE\n"); 4299 else 4300 printf("and ACTIVE\n"); 4301 4302 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4303 device_printf(dev, "TX Queue %d ------\n", i); 4304 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4305 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4306 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4307 4308 } 4309 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4310 device_printf(dev, "RX Queue %d ------\n", j); 4311 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4312 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4313 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4314 } 4315 } 4316 4317 4318 /* 4319 * 82574 only: 4320 * Write a new value to the EEPROM increasing the number of MSIX 4321 * vectors from 3 to 5, for proper multiqueue support. 4322 */ 4323 static void 4324 em_enable_vectors_82574(if_ctx_t ctx) 4325 { 4326 struct adapter *adapter = iflib_get_softc(ctx); 4327 struct e1000_hw *hw = &adapter->hw; 4328 device_t dev = iflib_get_dev(ctx); 4329 u16 edata; 4330 4331 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4332 printf("Current cap: %#06x\n", edata); 4333 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4334 device_printf(dev, "Writing to eeprom: increasing " 4335 "reported MSIX vectors from 3 to 5...\n"); 4336 edata &= ~(EM_NVM_MSIX_N_MASK); 4337 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4338 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4339 e1000_update_nvm_checksum(hw); 4340 device_printf(dev, "Writing to eeprom: done\n"); 4341 } 4342 } 4343 4344 4345 #ifdef DDB 4346 DB_COMMAND(em_reset_dev, em_ddb_reset_dev) 4347 { 4348 devclass_t dc; 4349 int max_em; 4350 4351 dc = devclass_find("em"); 4352 max_em = devclass_get_maxunit(dc); 4353 4354 for (int index = 0; index < (max_em - 1); index++) { 4355 device_t dev; 4356 dev = devclass_get_device(dc, index); 4357 if (device_get_driver(dev) == &em_driver) { 4358 struct adapter *adapter = device_get_softc(dev); 4359 em_if_init(adapter->ctx); 4360 } 4361 } 4362 } 4363 DB_COMMAND(em_dump_queue, em_ddb_dump_queue) 4364 { 4365 devclass_t dc; 4366 int max_em; 4367 4368 dc = devclass_find("em"); 4369 max_em = devclass_get_maxunit(dc); 4370 4371 for (int index = 0; index < (max_em - 1); index++) { 4372 device_t dev; 4373 dev = devclass_get_device(dc, index); 4374 if (device_get_driver(dev) == &em_driver) 4375 em_print_debug_info(device_get_softc(dev)); 4376 } 4377 4378 } 4379 #endif 4380