1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_vf_counter(if_ctx_t, ift_counter); 411 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 412 static void em_if_init(if_ctx_t); 413 static void em_if_stop(if_ctx_t); 414 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 415 static int em_if_media_change(if_ctx_t); 416 static int em_if_mtu_set(if_ctx_t, uint32_t); 417 static void em_if_timer(if_ctx_t, uint16_t); 418 static void em_if_vlan_register(if_ctx_t, u16); 419 static void em_if_vlan_unregister(if_ctx_t, u16); 420 static void em_if_watchdog_reset(if_ctx_t); 421 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 422 423 static void em_identify_hardware(if_ctx_t); 424 static int em_allocate_pci_resources(if_ctx_t); 425 static void em_free_pci_resources(if_ctx_t); 426 static void em_reset(if_ctx_t); 427 static int em_setup_interface(if_ctx_t); 428 static int em_setup_msix(if_ctx_t); 429 430 static void em_initialize_transmit_unit(if_ctx_t); 431 static void em_initialize_receive_unit(if_ctx_t); 432 433 static void em_if_intr_enable(if_ctx_t); 434 static void em_if_intr_disable(if_ctx_t); 435 static void igb_if_intr_enable(if_ctx_t); 436 static void igb_if_intr_disable(if_ctx_t); 437 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 440 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 441 static void em_if_multi_set(if_ctx_t); 442 static void em_if_update_admin_status(if_ctx_t); 443 static void em_if_debug(if_ctx_t); 444 static void em_update_vf_stats_counters(struct e1000_softc *); 445 static void em_update_stats_counters(struct e1000_softc *); 446 static void em_add_hw_stats(struct e1000_softc *); 447 static int em_if_set_promisc(if_ctx_t, int); 448 static bool em_if_vlan_filter_capable(if_ctx_t); 449 static bool em_if_vlan_filter_used(if_ctx_t); 450 static void em_if_vlan_filter_enable(struct e1000_softc *); 451 static void em_if_vlan_filter_disable(struct e1000_softc *); 452 static void em_if_vlan_filter_write(struct e1000_softc *); 453 static void em_setup_vlan_hw_support(if_ctx_t ctx); 454 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 455 static void em_print_nvm_info(struct e1000_softc *); 456 static void em_fw_version_locked(if_ctx_t); 457 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 458 static void em_print_fw_version(struct e1000_softc *); 459 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 460 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 461 static int em_get_rs(SYSCTL_HANDLER_ARGS); 462 static void em_print_debug_info(struct e1000_softc *); 463 static int em_is_valid_ether_addr(u8 *); 464 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 465 struct tx_ring *, struct rx_ring *); 466 static bool em_automask_tso(if_ctx_t); 467 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 468 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 469 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 470 const char *, struct em_int_delay_info *, int, int); 471 /* Management and WOL Support */ 472 static void em_init_manageability(struct e1000_softc *); 473 static void em_release_manageability(struct e1000_softc *); 474 static void em_get_hw_control(struct e1000_softc *); 475 static void em_release_hw_control(struct e1000_softc *); 476 static void em_get_wakeup(if_ctx_t); 477 static void em_enable_wakeup(if_ctx_t); 478 static int em_enable_phy_wakeup(struct e1000_softc *); 479 static void em_disable_aspm(struct e1000_softc *); 480 481 int em_intr(void *); 482 483 /* MSI-X handlers */ 484 static int em_if_msix_intr_assign(if_ctx_t, int); 485 static int em_msix_link(void *); 486 static void em_handle_link(void *); 487 488 static void em_enable_vectors_82574(if_ctx_t); 489 490 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 491 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 492 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 493 static void em_if_led_func(if_ctx_t, int); 494 495 static int em_get_regs(SYSCTL_HANDLER_ARGS); 496 497 static void lem_smartspeed(struct e1000_softc *); 498 static void igb_configure_queues(struct e1000_softc *); 499 static void em_flush_desc_rings(struct e1000_softc *); 500 501 502 /********************************************************************* 503 * FreeBSD Device Interface Entry Points 504 *********************************************************************/ 505 static device_method_t em_methods[] = { 506 /* Device interface */ 507 DEVMETHOD(device_register, em_register), 508 DEVMETHOD(device_probe, iflib_device_probe), 509 DEVMETHOD(device_attach, iflib_device_attach), 510 DEVMETHOD(device_detach, iflib_device_detach), 511 DEVMETHOD(device_shutdown, iflib_device_shutdown), 512 DEVMETHOD(device_suspend, iflib_device_suspend), 513 DEVMETHOD(device_resume, iflib_device_resume), 514 DEVMETHOD_END 515 }; 516 517 static device_method_t igb_methods[] = { 518 /* Device interface */ 519 DEVMETHOD(device_register, igb_register), 520 DEVMETHOD(device_probe, iflib_device_probe), 521 DEVMETHOD(device_attach, iflib_device_attach), 522 DEVMETHOD(device_detach, iflib_device_detach), 523 DEVMETHOD(device_shutdown, iflib_device_shutdown), 524 DEVMETHOD(device_suspend, iflib_device_suspend), 525 DEVMETHOD(device_resume, iflib_device_resume), 526 DEVMETHOD_END 527 }; 528 529 530 static driver_t em_driver = { 531 "em", em_methods, sizeof(struct e1000_softc), 532 }; 533 534 DRIVER_MODULE(em, pci, em_driver, 0, 0); 535 536 MODULE_DEPEND(em, pci, 1, 1, 1); 537 MODULE_DEPEND(em, ether, 1, 1, 1); 538 MODULE_DEPEND(em, iflib, 1, 1, 1); 539 540 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 541 542 static driver_t igb_driver = { 543 "igb", igb_methods, sizeof(struct e1000_softc), 544 }; 545 546 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 547 548 MODULE_DEPEND(igb, pci, 1, 1, 1); 549 MODULE_DEPEND(igb, ether, 1, 1, 1); 550 MODULE_DEPEND(igb, iflib, 1, 1, 1); 551 552 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 553 554 static device_method_t em_if_methods[] = { 555 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 556 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 557 DEVMETHOD(ifdi_detach, em_if_detach), 558 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 559 DEVMETHOD(ifdi_suspend, em_if_suspend), 560 DEVMETHOD(ifdi_resume, em_if_resume), 561 DEVMETHOD(ifdi_init, em_if_init), 562 DEVMETHOD(ifdi_stop, em_if_stop), 563 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 564 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 565 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 566 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 567 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 568 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 569 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 570 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 571 DEVMETHOD(ifdi_media_status, em_if_media_status), 572 DEVMETHOD(ifdi_media_change, em_if_media_change), 573 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 574 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 575 DEVMETHOD(ifdi_timer, em_if_timer), 576 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 577 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 578 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 579 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 580 DEVMETHOD(ifdi_led_func, em_if_led_func), 581 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 582 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 583 DEVMETHOD(ifdi_debug, em_if_debug), 584 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 585 DEVMETHOD_END 586 }; 587 588 static driver_t em_if_driver = { 589 "em_if", em_if_methods, sizeof(struct e1000_softc) 590 }; 591 592 static device_method_t igb_if_methods[] = { 593 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 594 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 595 DEVMETHOD(ifdi_detach, em_if_detach), 596 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 597 DEVMETHOD(ifdi_suspend, em_if_suspend), 598 DEVMETHOD(ifdi_resume, em_if_resume), 599 DEVMETHOD(ifdi_init, em_if_init), 600 DEVMETHOD(ifdi_stop, em_if_stop), 601 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 602 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 603 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 604 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 605 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 606 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 607 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 608 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 609 DEVMETHOD(ifdi_media_status, em_if_media_status), 610 DEVMETHOD(ifdi_media_change, em_if_media_change), 611 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 612 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 613 DEVMETHOD(ifdi_timer, em_if_timer), 614 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 615 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 616 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 617 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 618 DEVMETHOD(ifdi_led_func, em_if_led_func), 619 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 620 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 621 DEVMETHOD(ifdi_debug, em_if_debug), 622 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 623 DEVMETHOD_END 624 }; 625 626 static driver_t igb_if_driver = { 627 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 628 }; 629 630 /********************************************************************* 631 * Tunable default values. 632 *********************************************************************/ 633 634 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 635 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 636 637 /* Allow common code without TSO */ 638 #ifndef CSUM_TSO 639 #define CSUM_TSO 0 640 #endif 641 642 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 643 "EM driver parameters"); 644 645 static int em_disable_crc_stripping = 0; 646 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 647 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 648 649 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 650 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 651 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 652 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 653 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 654 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 655 656 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 657 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 658 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 659 &em_tx_abs_int_delay_dflt, 0, 660 "Default transmit interrupt delay limit in usecs"); 661 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 662 &em_rx_abs_int_delay_dflt, 0, 663 "Default receive interrupt delay limit in usecs"); 664 665 static int em_smart_pwr_down = false; 666 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 667 &em_smart_pwr_down, 668 0, "Set to true to leave smart power down enabled on newer adapters"); 669 670 static bool em_unsupported_tso = false; 671 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 672 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 673 674 /* Controls whether promiscuous also shows bad packets */ 675 static int em_debug_sbp = false; 676 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 677 "Show bad packets in promiscuous mode"); 678 679 /* Energy efficient ethernet - default to OFF */ 680 static int eee_setting = 1; 681 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 682 "Enable Energy Efficient Ethernet"); 683 684 /* 685 * AIM: Adaptive Interrupt Moderation 686 * which means that the interrupt rate is varied over time based on the 687 * traffic for that interrupt vector 688 */ 689 static int em_enable_aim = 1; 690 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 691 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 692 693 /* 694 ** Tuneable Interrupt rate 695 */ 696 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 697 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 698 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 699 700 /* Global used in WOL setup with multiport cards */ 701 static int global_quad_port_a = 0; 702 703 extern struct if_txrx igb_txrx; 704 extern struct if_txrx em_txrx; 705 extern struct if_txrx lem_txrx; 706 707 static struct if_shared_ctx em_sctx_init = { 708 .isc_magic = IFLIB_MAGIC, 709 .isc_q_align = PAGE_SIZE, 710 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 711 .isc_tx_maxsegsize = PAGE_SIZE, 712 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 713 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 714 .isc_rx_maxsize = MJUM9BYTES, 715 .isc_rx_nsegments = 1, 716 .isc_rx_maxsegsize = MJUM9BYTES, 717 .isc_nfl = 1, 718 .isc_nrxqs = 1, 719 .isc_ntxqs = 1, 720 .isc_admin_intrcnt = 1, 721 .isc_vendor_info = em_vendor_info_array, 722 .isc_driver_version = em_driver_version, 723 .isc_driver = &em_if_driver, 724 .isc_flags = 725 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 726 727 .isc_nrxd_min = {EM_MIN_RXD}, 728 .isc_ntxd_min = {EM_MIN_TXD}, 729 .isc_nrxd_max = {EM_MAX_RXD}, 730 .isc_ntxd_max = {EM_MAX_TXD}, 731 .isc_nrxd_default = {EM_DEFAULT_RXD}, 732 .isc_ntxd_default = {EM_DEFAULT_TXD}, 733 }; 734 735 static struct if_shared_ctx igb_sctx_init = { 736 .isc_magic = IFLIB_MAGIC, 737 .isc_q_align = PAGE_SIZE, 738 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 739 .isc_tx_maxsegsize = PAGE_SIZE, 740 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 741 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 742 .isc_rx_maxsize = MJUM9BYTES, 743 .isc_rx_nsegments = 1, 744 .isc_rx_maxsegsize = MJUM9BYTES, 745 .isc_nfl = 1, 746 .isc_nrxqs = 1, 747 .isc_ntxqs = 1, 748 .isc_admin_intrcnt = 1, 749 .isc_vendor_info = igb_vendor_info_array, 750 .isc_driver_version = igb_driver_version, 751 .isc_driver = &igb_if_driver, 752 .isc_flags = 753 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 754 755 .isc_nrxd_min = {EM_MIN_RXD}, 756 .isc_ntxd_min = {EM_MIN_TXD}, 757 .isc_nrxd_max = {IGB_MAX_RXD}, 758 .isc_ntxd_max = {IGB_MAX_TXD}, 759 .isc_nrxd_default = {EM_DEFAULT_RXD}, 760 .isc_ntxd_default = {EM_DEFAULT_TXD}, 761 }; 762 763 /***************************************************************** 764 * 765 * Dump Registers 766 * 767 ****************************************************************/ 768 #define IGB_REGS_LEN 739 769 770 static int em_get_regs(SYSCTL_HANDLER_ARGS) 771 { 772 struct e1000_softc *sc = (struct e1000_softc *)arg1; 773 struct e1000_hw *hw = &sc->hw; 774 struct sbuf *sb; 775 u32 *regs_buff; 776 int rc; 777 778 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 779 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 780 781 rc = sysctl_wire_old_buffer(req, 0); 782 MPASS(rc == 0); 783 if (rc != 0) { 784 free(regs_buff, M_DEVBUF); 785 return (rc); 786 } 787 788 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 789 MPASS(sb != NULL); 790 if (sb == NULL) { 791 free(regs_buff, M_DEVBUF); 792 return (ENOMEM); 793 } 794 795 /* General Registers */ 796 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 797 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 798 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 799 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 800 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 801 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 802 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 803 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 804 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 805 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 806 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 807 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 808 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 809 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 810 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 811 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 812 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 813 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 814 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 815 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 816 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 817 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 818 819 sbuf_printf(sb, "General Registers\n"); 820 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 821 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 822 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 823 824 sbuf_printf(sb, "Interrupt Registers\n"); 825 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 826 827 sbuf_printf(sb, "RX Registers\n"); 828 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 829 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 830 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 831 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 832 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 833 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 834 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 835 836 sbuf_printf(sb, "TX Registers\n"); 837 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 838 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 839 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 840 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 841 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 842 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 843 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 844 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 845 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 846 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 847 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 848 849 free(regs_buff, M_DEVBUF); 850 851 #ifdef DUMP_DESCS 852 { 853 if_softc_ctx_t scctx = sc->shared; 854 struct rx_ring *rxr = &rx_que->rxr; 855 struct tx_ring *txr = &tx_que->txr; 856 int ntxd = scctx->isc_ntxd[0]; 857 int nrxd = scctx->isc_nrxd[0]; 858 int j; 859 860 for (j = 0; j < nrxd; j++) { 861 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 862 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 863 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 864 PRIx64 " Error:%d Length:%d\n", 865 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 866 } 867 868 for (j = 0; j < min(ntxd, 256); j++) { 869 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 870 871 sbuf_printf(sb, 872 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 873 " eop: %d DD=%d\n", 874 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 875 buf->eop != -1 ? 876 txr->tx_base[buf->eop].upper.fields.status & 877 E1000_TXD_STAT_DD : 0); 878 879 } 880 } 881 #endif 882 883 rc = sbuf_finish(sb); 884 sbuf_delete(sb); 885 return(rc); 886 } 887 888 static void * 889 em_register(device_t dev) 890 { 891 return (&em_sctx_init); 892 } 893 894 static void * 895 igb_register(device_t dev) 896 { 897 return (&igb_sctx_init); 898 } 899 900 static int 901 em_set_num_queues(if_ctx_t ctx) 902 { 903 struct e1000_softc *sc = iflib_get_softc(ctx); 904 int maxqueues; 905 906 /* Sanity check based on HW */ 907 switch (sc->hw.mac.type) { 908 case e1000_82576: 909 case e1000_82580: 910 case e1000_i350: 911 case e1000_i354: 912 maxqueues = 8; 913 break; 914 case e1000_i210: 915 case e1000_82575: 916 maxqueues = 4; 917 break; 918 case e1000_i211: 919 case e1000_82574: 920 maxqueues = 2; 921 break; 922 default: 923 maxqueues = 1; 924 break; 925 } 926 927 return (maxqueues); 928 } 929 930 #define LEM_CAPS \ 931 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 932 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 933 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 934 935 #define EM_CAPS \ 936 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 937 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 938 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 939 IFCAP_TSO6 940 941 #define IGB_CAPS \ 942 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 943 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 944 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 945 IFCAP_TSO6 946 947 /********************************************************************* 948 * Device initialization routine 949 * 950 * The attach entry point is called when the driver is being loaded. 951 * This routine identifies the type of hardware, allocates all resources 952 * and initializes the hardware. 953 * 954 * return 0 on success, positive on failure 955 *********************************************************************/ 956 static int 957 em_if_attach_pre(if_ctx_t ctx) 958 { 959 struct e1000_softc *sc; 960 if_softc_ctx_t scctx; 961 device_t dev; 962 struct e1000_hw *hw; 963 struct sysctl_oid_list *child; 964 struct sysctl_ctx_list *ctx_list; 965 int error = 0; 966 967 INIT_DEBUGOUT("em_if_attach_pre: begin"); 968 dev = iflib_get_dev(ctx); 969 sc = iflib_get_softc(ctx); 970 971 sc->ctx = sc->osdep.ctx = ctx; 972 sc->dev = sc->osdep.dev = dev; 973 scctx = sc->shared = iflib_get_softc_ctx(ctx); 974 sc->media = iflib_get_media(ctx); 975 hw = &sc->hw; 976 977 /* Determine hardware and mac info */ 978 em_identify_hardware(ctx); 979 980 /* SYSCTL stuff */ 981 ctx_list = device_get_sysctl_ctx(dev); 982 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 983 984 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 985 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 986 em_sysctl_nvm_info, "I", "NVM Information"); 987 988 sc->enable_aim = em_enable_aim; 989 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 990 CTLFLAG_RW, &sc->enable_aim, 0, 991 "Interrupt Moderation (1=normal, 2=lowlatency)"); 992 993 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 994 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 995 em_sysctl_print_fw_version, "A", 996 "Prints FW/NVM Versions"); 997 998 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 999 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1000 em_sysctl_debug_info, "I", "Debug Information"); 1001 1002 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1003 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1004 em_set_flowcntl, "I", "Flow Control"); 1005 1006 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1007 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1008 em_get_regs, "A", "Dump Registers"); 1009 1010 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1011 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1012 em_get_rs, "I", "Dump RS indexes"); 1013 1014 if (hw->mac.type >= e1000_i350) { 1015 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1016 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1017 igb_sysctl_dmac, "I", "DMA Coalesce"); 1018 } 1019 1020 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1021 "tso_tcp_flags_mask_first_segment", 1022 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1023 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1024 "TSO TCP flags mask for first segment"); 1025 1026 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1027 "tso_tcp_flags_mask_middle_segment", 1028 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1029 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1030 "TSO TCP flags mask for middle segment"); 1031 1032 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1033 "tso_tcp_flags_mask_last_segment", 1034 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1035 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1036 "TSO TCP flags mask for last segment"); 1037 1038 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1039 scctx->isc_nrxqsets_max = 1040 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1041 if (bootverbose) 1042 device_printf(dev, "attach_pre capping queues at %d\n", 1043 scctx->isc_ntxqsets_max); 1044 1045 if (hw->mac.type >= igb_mac_min) { 1046 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1047 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1048 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1049 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1050 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1051 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1052 scctx->isc_txrx = &igb_txrx; 1053 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1054 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1055 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1056 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1057 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1058 CSUM_IP6_TCP | CSUM_IP6_UDP; 1059 if (hw->mac.type != e1000_82575) 1060 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1061 /* 1062 ** Some new devices, as with ixgbe, now may 1063 ** use a different BAR, so we need to keep 1064 ** track of which is used. 1065 */ 1066 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1067 } else if (hw->mac.type >= em_mac_min) { 1068 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1069 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1070 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1071 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1072 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1073 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1074 scctx->isc_txrx = &em_txrx; 1075 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1076 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1077 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1078 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1079 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1080 CSUM_IP6_TCP | CSUM_IP6_UDP; 1081 1082 /* Disable TSO on all em(4) until ring stalls are debugged */ 1083 scctx->isc_capenable &= ~IFCAP_TSO; 1084 1085 /* 1086 * Disable TSO on SPT due to errata that downclocks DMA 1087 * performance 1088 * i218-i219 Specification Update 1.5.4.5 1089 */ 1090 if (hw->mac.type == e1000_pch_spt) 1091 scctx->isc_capenable &= ~IFCAP_TSO; 1092 1093 /* 1094 * We support MSI-X with 82574 only, but indicate to iflib(4) 1095 * that it shall give MSI at least a try with other devices. 1096 */ 1097 if (hw->mac.type == e1000_82574) { 1098 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1099 } else { 1100 scctx->isc_msix_bar = -1; 1101 scctx->isc_disable_msix = 1; 1102 } 1103 } else { 1104 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1105 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1106 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1107 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1108 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1109 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1110 scctx->isc_txrx = &lem_txrx; 1111 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1112 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1113 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1114 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1115 if (em_unsupported_tso) 1116 scctx->isc_capabilities |= IFCAP_TSO6; 1117 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1118 CSUM_IP6_TCP | CSUM_IP6_UDP; 1119 1120 /* Disable TSO on all lem(4) until ring stalls debugged */ 1121 scctx->isc_capenable &= ~IFCAP_TSO; 1122 1123 /* 82541ER doesn't do HW tagging */ 1124 if (hw->device_id == E1000_DEV_ID_82541ER || 1125 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1126 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1127 scctx->isc_capenable = scctx->isc_capabilities; 1128 } 1129 /* This is the first e1000 chip and it does not do offloads */ 1130 if (hw->mac.type == e1000_82542) { 1131 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1132 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1133 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1134 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1135 scctx->isc_capenable = scctx->isc_capabilities; 1136 } 1137 /* These can't do TSO for various reasons */ 1138 if (hw->mac.type < e1000_82544 || 1139 hw->mac.type == e1000_82547 || 1140 hw->mac.type == e1000_82547_rev_2) { 1141 scctx->isc_capabilities &= 1142 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1143 scctx->isc_capenable = scctx->isc_capabilities; 1144 } 1145 /* XXXKB: No IPv6 before this? */ 1146 if (hw->mac.type < e1000_82545){ 1147 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1148 scctx->isc_capenable = scctx->isc_capabilities; 1149 } 1150 /* 1151 * "PCI/PCI-X SDM 4.0" page 33 (b): 1152 * FDX requirement on these chips 1153 */ 1154 if (hw->mac.type == e1000_82547 || 1155 hw->mac.type == e1000_82547_rev_2) 1156 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1157 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1158 1159 /* INTx only */ 1160 scctx->isc_msix_bar = 0; 1161 } 1162 1163 /* Setup PCI resources */ 1164 if (em_allocate_pci_resources(ctx)) { 1165 device_printf(dev, "Allocation of PCI resources failed\n"); 1166 error = ENXIO; 1167 goto err_pci; 1168 } 1169 1170 /* 1171 ** For ICH8 and family we need to 1172 ** map the flash memory, and this 1173 ** must happen after the MAC is 1174 ** identified 1175 */ 1176 if ((hw->mac.type == e1000_ich8lan) || 1177 (hw->mac.type == e1000_ich9lan) || 1178 (hw->mac.type == e1000_ich10lan) || 1179 (hw->mac.type == e1000_pchlan) || 1180 (hw->mac.type == e1000_pch2lan) || 1181 (hw->mac.type == e1000_pch_lpt)) { 1182 int rid = EM_BAR_TYPE_FLASH; 1183 sc->flash = bus_alloc_resource_any(dev, 1184 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1185 if (sc->flash == NULL) { 1186 device_printf(dev, "Mapping of Flash failed\n"); 1187 error = ENXIO; 1188 goto err_pci; 1189 } 1190 /* This is used in the shared code */ 1191 hw->flash_address = (u8 *)sc->flash; 1192 sc->osdep.flash_bus_space_tag = 1193 rman_get_bustag(sc->flash); 1194 sc->osdep.flash_bus_space_handle = 1195 rman_get_bushandle(sc->flash); 1196 } 1197 /* 1198 ** In the new SPT device flash is not a 1199 ** separate BAR, rather it is also in BAR0, 1200 ** so use the same tag and an offset handle for the 1201 ** FLASH read/write macros in the shared code. 1202 */ 1203 else if (hw->mac.type >= e1000_pch_spt) { 1204 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1205 sc->osdep.flash_bus_space_handle = 1206 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1207 } 1208 1209 /* Do Shared Code initialization */ 1210 error = e1000_setup_init_funcs(hw, true); 1211 if (error) { 1212 device_printf(dev, "Setup of Shared code failed, error %d\n", 1213 error); 1214 error = ENXIO; 1215 goto err_pci; 1216 } 1217 1218 em_setup_msix(ctx); 1219 e1000_get_bus_info(hw); 1220 1221 /* Set up some sysctls for the tunable interrupt delays */ 1222 if (hw->mac.type < igb_mac_min) { 1223 em_add_int_delay_sysctl(sc, "rx_int_delay", 1224 "receive interrupt delay in usecs", &sc->rx_int_delay, 1225 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1226 em_add_int_delay_sysctl(sc, "tx_int_delay", 1227 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1228 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1229 } 1230 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1231 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1232 "receive interrupt delay limit in usecs", 1233 &sc->rx_abs_int_delay, 1234 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1235 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1236 "transmit interrupt delay limit in usecs", 1237 &sc->tx_abs_int_delay, 1238 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1239 } 1240 1241 hw->mac.autoneg = DO_AUTO_NEG; 1242 hw->phy.autoneg_wait_to_complete = false; 1243 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1244 1245 if (hw->mac.type < em_mac_min) { 1246 e1000_init_script_state_82541(hw, true); 1247 e1000_set_tbi_compatibility_82543(hw, true); 1248 } 1249 /* Copper options */ 1250 if (hw->phy.media_type == e1000_media_type_copper) { 1251 hw->phy.mdix = AUTO_ALL_MODES; 1252 hw->phy.disable_polarity_correction = false; 1253 hw->phy.ms_type = EM_MASTER_SLAVE; 1254 } 1255 1256 /* 1257 * Set the frame limits assuming 1258 * standard ethernet sized frames. 1259 */ 1260 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1261 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1262 1263 /* 1264 * This controls when hardware reports transmit completion 1265 * status. 1266 */ 1267 hw->mac.report_tx_early = 1; 1268 1269 /* Allocate multicast array memory. */ 1270 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1271 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1272 if (sc->mta == NULL) { 1273 device_printf(dev, 1274 "Can not allocate multicast setup array\n"); 1275 error = ENOMEM; 1276 goto err_late; 1277 } 1278 1279 /* Clear the IFCAP_TSO auto mask */ 1280 sc->tso_automasked = 0; 1281 1282 /* Check SOL/IDER usage */ 1283 if (e1000_check_reset_block(hw)) 1284 device_printf(dev, 1285 "PHY reset is blocked due to SOL/IDER session.\n"); 1286 1287 /* Sysctl for setting Energy Efficient Ethernet */ 1288 if (hw->mac.type < igb_mac_min) 1289 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1290 else 1291 hw->dev_spec._82575.eee_disable = eee_setting; 1292 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1293 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1294 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1295 1296 /* 1297 ** Start from a known state, this is 1298 ** important in reading the nvm and 1299 ** mac from that. 1300 */ 1301 e1000_reset_hw(hw); 1302 1303 /* Make sure we have a good EEPROM before we read from it */ 1304 if (e1000_validate_nvm_checksum(hw) < 0) { 1305 /* 1306 ** Some PCI-E parts fail the first check due to 1307 ** the link being in sleep state, call it again, 1308 ** if it fails a second time its a real issue. 1309 */ 1310 if (e1000_validate_nvm_checksum(hw) < 0) { 1311 device_printf(dev, 1312 "The EEPROM Checksum Is Not Valid\n"); 1313 error = EIO; 1314 goto err_late; 1315 } 1316 } 1317 1318 /* Copy the permanent MAC address out of the EEPROM */ 1319 if (e1000_read_mac_addr(hw) < 0) { 1320 device_printf(dev, 1321 "EEPROM read error while reading MAC address\n"); 1322 error = EIO; 1323 goto err_late; 1324 } 1325 1326 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1327 if (sc->vf_ifp) { 1328 ether_gen_addr(iflib_get_ifp(ctx), 1329 (struct ether_addr *)hw->mac.addr); 1330 } else { 1331 device_printf(dev, "Invalid MAC address\n"); 1332 error = EIO; 1333 goto err_late; 1334 } 1335 } 1336 1337 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1338 em_fw_version_locked(ctx); 1339 1340 em_print_fw_version(sc); 1341 1342 /* 1343 * Get Wake-on-Lan and Management info for later use 1344 */ 1345 em_get_wakeup(ctx); 1346 1347 /* Enable only WOL MAGIC by default */ 1348 scctx->isc_capenable &= ~IFCAP_WOL; 1349 if (sc->wol != 0) 1350 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1351 1352 iflib_set_mac(ctx, hw->mac.addr); 1353 1354 return (0); 1355 1356 err_late: 1357 em_release_hw_control(sc); 1358 err_pci: 1359 em_free_pci_resources(ctx); 1360 free(sc->mta, M_DEVBUF); 1361 1362 return (error); 1363 } 1364 1365 static int 1366 em_if_attach_post(if_ctx_t ctx) 1367 { 1368 struct e1000_softc *sc = iflib_get_softc(ctx); 1369 struct e1000_hw *hw = &sc->hw; 1370 int error = 0; 1371 1372 /* Setup OS specific network interface */ 1373 error = em_setup_interface(ctx); 1374 if (error != 0) { 1375 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1376 goto err_late; 1377 } 1378 1379 em_reset(ctx); 1380 1381 /* Initialize statistics */ 1382 if (sc->vf_ifp) 1383 sc->ustats.vf_stats = (struct e1000_vf_stats){}; 1384 else 1385 sc->ustats.stats = (struct e1000_hw_stats){}; 1386 1387 em_update_stats_counters(sc); 1388 hw->mac.get_link_status = 1; 1389 em_if_update_admin_status(ctx); 1390 em_add_hw_stats(sc); 1391 1392 /* Non-AMT based hardware can now take control from firmware */ 1393 if (sc->has_manage && !sc->has_amt) 1394 em_get_hw_control(sc); 1395 1396 INIT_DEBUGOUT("em_if_attach_post: end"); 1397 1398 return (0); 1399 1400 err_late: 1401 /* 1402 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1403 * free resources 1404 */ 1405 return (error); 1406 } 1407 1408 /********************************************************************* 1409 * Device removal routine 1410 * 1411 * The detach entry point is called when the driver is being removed. 1412 * This routine stops the adapter and deallocates all the resources 1413 * that were allocated for driver operation. 1414 * 1415 * return 0 on success, positive on failure 1416 *********************************************************************/ 1417 static int 1418 em_if_detach(if_ctx_t ctx) 1419 { 1420 struct e1000_softc *sc = iflib_get_softc(ctx); 1421 1422 INIT_DEBUGOUT("em_if_detach: begin"); 1423 1424 e1000_phy_hw_reset(&sc->hw); 1425 1426 em_release_manageability(sc); 1427 em_release_hw_control(sc); 1428 em_free_pci_resources(ctx); 1429 free(sc->mta, M_DEVBUF); 1430 sc->mta = NULL; 1431 1432 return (0); 1433 } 1434 1435 /********************************************************************* 1436 * 1437 * Shutdown entry point 1438 * 1439 **********************************************************************/ 1440 1441 static int 1442 em_if_shutdown(if_ctx_t ctx) 1443 { 1444 return em_if_suspend(ctx); 1445 } 1446 1447 /* 1448 * Suspend/resume device methods. 1449 */ 1450 static int 1451 em_if_suspend(if_ctx_t ctx) 1452 { 1453 struct e1000_softc *sc = iflib_get_softc(ctx); 1454 1455 em_release_manageability(sc); 1456 em_release_hw_control(sc); 1457 em_enable_wakeup(ctx); 1458 return (0); 1459 } 1460 1461 static int 1462 em_if_resume(if_ctx_t ctx) 1463 { 1464 struct e1000_softc *sc = iflib_get_softc(ctx); 1465 1466 if (sc->hw.mac.type == e1000_pch2lan) 1467 e1000_resume_workarounds_pchlan(&sc->hw); 1468 em_if_init(ctx); 1469 em_init_manageability(sc); 1470 1471 return(0); 1472 } 1473 1474 static int 1475 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1476 { 1477 int max_frame_size; 1478 struct e1000_softc *sc = iflib_get_softc(ctx); 1479 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1480 1481 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1482 1483 switch (sc->hw.mac.type) { 1484 case e1000_82571: 1485 case e1000_82572: 1486 case e1000_ich9lan: 1487 case e1000_ich10lan: 1488 case e1000_pch2lan: 1489 case e1000_pch_lpt: 1490 case e1000_pch_spt: 1491 case e1000_pch_cnp: 1492 case e1000_pch_tgp: 1493 case e1000_pch_adp: 1494 case e1000_pch_mtp: 1495 case e1000_pch_ptp: 1496 case e1000_82574: 1497 case e1000_82583: 1498 case e1000_80003es2lan: 1499 /* 9K Jumbo Frame size */ 1500 max_frame_size = 9234; 1501 break; 1502 case e1000_pchlan: 1503 max_frame_size = 4096; 1504 break; 1505 case e1000_82542: 1506 case e1000_ich8lan: 1507 /* Adapters that do not support jumbo frames */ 1508 max_frame_size = ETHER_MAX_LEN; 1509 break; 1510 default: 1511 if (sc->hw.mac.type >= igb_mac_min) 1512 max_frame_size = 9234; 1513 else /* lem */ 1514 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1515 } 1516 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1517 return (EINVAL); 1518 } 1519 1520 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1521 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1522 return (0); 1523 } 1524 1525 /********************************************************************* 1526 * Init entry point 1527 * 1528 * This routine is used in two ways. It is used by the stack as 1529 * init entry point in network interface structure. It is also used 1530 * by the driver as a hw/sw initialization routine to get to a 1531 * consistent state. 1532 * 1533 **********************************************************************/ 1534 static void 1535 em_if_init(if_ctx_t ctx) 1536 { 1537 struct e1000_softc *sc = iflib_get_softc(ctx); 1538 if_softc_ctx_t scctx = sc->shared; 1539 if_t ifp = iflib_get_ifp(ctx); 1540 struct em_tx_queue *tx_que; 1541 int i; 1542 1543 INIT_DEBUGOUT("em_if_init: begin"); 1544 1545 /* Get the latest mac address, User can use a LAA */ 1546 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1547 1548 /* Put the address into the Receive Address Array */ 1549 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1550 1551 /* 1552 * With the 82571 adapter, RAR[0] may be overwritten 1553 * when the other port is reset, we make a duplicate 1554 * in RAR[14] for that eventuality, this assures 1555 * the interface continues to function. 1556 */ 1557 if (sc->hw.mac.type == e1000_82571) { 1558 e1000_set_laa_state_82571(&sc->hw, true); 1559 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1560 E1000_RAR_ENTRIES - 1); 1561 } 1562 1563 /* Initialize the hardware */ 1564 em_reset(ctx); 1565 em_if_update_admin_status(ctx); 1566 1567 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1568 i++, tx_que++) { 1569 struct tx_ring *txr = &tx_que->txr; 1570 1571 txr->tx_rs_cidx = txr->tx_rs_pidx; 1572 1573 /* Initialize the last processed descriptor to be the end of 1574 * the ring, rather than the start, so that we avoid an 1575 * off-by-one error when calculating how many descriptors are 1576 * done in the credits_update function. 1577 */ 1578 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1579 } 1580 1581 /* Setup VLAN support, basic and offload if available */ 1582 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1583 1584 /* Clear bad data from Rx FIFOs */ 1585 if (sc->hw.mac.type >= igb_mac_min) 1586 e1000_rx_fifo_flush_base(&sc->hw); 1587 1588 /* Configure for OS presence */ 1589 em_init_manageability(sc); 1590 1591 /* Prepare transmit descriptors and buffers */ 1592 em_initialize_transmit_unit(ctx); 1593 1594 /* Setup Multicast table */ 1595 em_if_multi_set(ctx); 1596 1597 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1598 em_initialize_receive_unit(ctx); 1599 1600 /* Set up VLAN support and filter */ 1601 em_setup_vlan_hw_support(ctx); 1602 1603 /* Don't lose promiscuous settings */ 1604 em_if_set_promisc(ctx, if_getflags(ifp)); 1605 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1606 1607 /* MSI-X configuration for 82574 */ 1608 if (sc->hw.mac.type == e1000_82574) { 1609 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1610 1611 tmp |= E1000_CTRL_EXT_PBA_CLR; 1612 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1613 /* Set the IVAR - interrupt vector routing. */ 1614 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1615 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1616 /* Set up queue routing */ 1617 igb_configure_queues(sc); 1618 } 1619 1620 /* this clears any pending interrupts */ 1621 E1000_READ_REG(&sc->hw, E1000_ICR); 1622 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1623 1624 /* AMT based hardware can now take control from firmware */ 1625 if (sc->has_manage && sc->has_amt) 1626 em_get_hw_control(sc); 1627 1628 /* Set Energy Efficient Ethernet */ 1629 if (sc->hw.mac.type >= igb_mac_min && 1630 sc->hw.phy.media_type == e1000_media_type_copper) { 1631 if (sc->hw.mac.type == e1000_i354) 1632 e1000_set_eee_i354(&sc->hw, true, true); 1633 else 1634 e1000_set_eee_i350(&sc->hw, true, true); 1635 } 1636 } 1637 1638 enum itr_latency_target { 1639 itr_latency_disabled = 0, 1640 itr_latency_lowest = 1, 1641 itr_latency_low = 2, 1642 itr_latency_bulk = 3 1643 }; 1644 /********************************************************************* 1645 * 1646 * Helper to calculate next (E)ITR value for AIM 1647 * 1648 *********************************************************************/ 1649 static void 1650 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1651 struct tx_ring *txr, struct rx_ring *rxr) 1652 { 1653 struct e1000_hw *hw = &sc->hw; 1654 unsigned long bytes, bytes_per_packet, packets; 1655 unsigned long rxbytes, rxpackets, txbytes, txpackets; 1656 u32 newitr; 1657 u8 nextlatency; 1658 1659 rxbytes = atomic_load_long(&rxr->rx_bytes); 1660 txbytes = atomic_load_long(&txr->tx_bytes); 1661 1662 /* Idle, do nothing */ 1663 if (txbytes == 0 && rxbytes == 0) 1664 return; 1665 1666 newitr = 0; 1667 1668 if (sc->enable_aim) { 1669 nextlatency = rxr->rx_nextlatency; 1670 1671 /* Use half default (4K) ITR if sub-gig */ 1672 if (sc->link_speed != 1000) { 1673 newitr = EM_INTS_4K; 1674 goto em_set_next_itr; 1675 } 1676 /* Want at least enough packet buffer for two frames to AIM */ 1677 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1678 newitr = em_max_interrupt_rate; 1679 sc->enable_aim = 0; 1680 goto em_set_next_itr; 1681 } 1682 1683 bytes = bytes_per_packet = 0; 1684 /* Get largest values from the associated tx and rx ring */ 1685 txpackets = atomic_load_long(&txr->tx_packets); 1686 if (txpackets != 0) { 1687 bytes = txbytes; 1688 bytes_per_packet = txbytes / txpackets; 1689 packets = txpackets; 1690 } 1691 rxpackets = atomic_load_long(&rxr->rx_packets); 1692 if (rxpackets != 0) { 1693 bytes = lmax(bytes, rxbytes); 1694 bytes_per_packet = 1695 lmax(bytes_per_packet, rxbytes / rxpackets); 1696 packets = lmax(packets, rxpackets); 1697 } 1698 1699 /* Latency state machine */ 1700 switch (nextlatency) { 1701 case itr_latency_disabled: /* Bootstrapping */ 1702 nextlatency = itr_latency_low; 1703 break; 1704 case itr_latency_lowest: /* 70k ints/s */ 1705 /* TSO and jumbo frames */ 1706 if (bytes_per_packet > 8000) 1707 nextlatency = itr_latency_bulk; 1708 else if ((packets < 5) && (bytes > 512)) 1709 nextlatency = itr_latency_low; 1710 break; 1711 case itr_latency_low: /* 20k ints/s */ 1712 if (bytes > 10000) { 1713 /* Handle TSO */ 1714 if (bytes_per_packet > 8000) 1715 nextlatency = itr_latency_bulk; 1716 else if ((packets < 10) || 1717 (bytes_per_packet > 1200)) 1718 nextlatency = itr_latency_bulk; 1719 else if (packets > 35) 1720 nextlatency = itr_latency_lowest; 1721 } else if (bytes_per_packet > 2000) { 1722 nextlatency = itr_latency_bulk; 1723 } else if (packets < 3 && bytes < 512) { 1724 nextlatency = itr_latency_lowest; 1725 } 1726 break; 1727 case itr_latency_bulk: /* 4k ints/s */ 1728 if (bytes > 25000) { 1729 if (packets > 35) 1730 nextlatency = itr_latency_low; 1731 } else if (bytes < 1500) 1732 nextlatency = itr_latency_low; 1733 break; 1734 default: 1735 nextlatency = itr_latency_low; 1736 device_printf(sc->dev, 1737 "Unexpected newitr transition %d\n", nextlatency); 1738 break; 1739 } 1740 1741 /* Trim itr_latency_lowest for default AIM setting */ 1742 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1743 nextlatency = itr_latency_low; 1744 1745 /* Request new latency */ 1746 rxr->rx_nextlatency = nextlatency; 1747 } else { 1748 /* We may have toggled to AIM disabled */ 1749 nextlatency = itr_latency_disabled; 1750 rxr->rx_nextlatency = nextlatency; 1751 } 1752 1753 /* ITR state machine */ 1754 switch(nextlatency) { 1755 case itr_latency_lowest: 1756 newitr = EM_INTS_70K; 1757 break; 1758 case itr_latency_low: 1759 newitr = EM_INTS_20K; 1760 break; 1761 case itr_latency_bulk: 1762 newitr = EM_INTS_4K; 1763 break; 1764 case itr_latency_disabled: 1765 default: 1766 newitr = em_max_interrupt_rate; 1767 break; 1768 } 1769 1770 em_set_next_itr: 1771 if (hw->mac.type >= igb_mac_min) { 1772 newitr = IGB_INTS_TO_EITR(newitr); 1773 1774 if (hw->mac.type == e1000_82575) 1775 newitr |= newitr << 16; 1776 else 1777 newitr |= E1000_EITR_CNT_IGNR; 1778 1779 if (newitr != que->itr_setting) { 1780 que->itr_setting = newitr; 1781 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1782 que->itr_setting); 1783 } 1784 } else { 1785 newitr = EM_INTS_TO_ITR(newitr); 1786 1787 if (newitr != que->itr_setting) { 1788 que->itr_setting = newitr; 1789 if (hw->mac.type == e1000_82574 && que->msix) { 1790 E1000_WRITE_REG(hw, 1791 E1000_EITR_82574(que->msix), 1792 que->itr_setting); 1793 } else { 1794 E1000_WRITE_REG(hw, E1000_ITR, 1795 que->itr_setting); 1796 } 1797 } 1798 } 1799 } 1800 1801 /********************************************************************* 1802 * 1803 * Fast Legacy/MSI Combined Interrupt Service routine 1804 * 1805 *********************************************************************/ 1806 int 1807 em_intr(void *arg) 1808 { 1809 struct e1000_softc *sc = arg; 1810 struct e1000_hw *hw = &sc->hw; 1811 struct em_rx_queue *que = &sc->rx_queues[0]; 1812 struct tx_ring *txr = &sc->tx_queues[0].txr; 1813 struct rx_ring *rxr = &que->rxr; 1814 if_ctx_t ctx = sc->ctx; 1815 u32 reg_icr; 1816 1817 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1818 1819 /* Hot eject? */ 1820 if (reg_icr == 0xffffffff) 1821 return FILTER_STRAY; 1822 1823 /* Definitely not our interrupt. */ 1824 if (reg_icr == 0x0) 1825 return FILTER_STRAY; 1826 1827 /* 1828 * Starting with the 82571 chip, bit 31 should be used to 1829 * determine whether the interrupt belongs to us. 1830 */ 1831 if (hw->mac.type >= e1000_82571 && 1832 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1833 return FILTER_STRAY; 1834 1835 /* 1836 * Only MSI-X interrupts have one-shot behavior by taking advantage 1837 * of the EIAC register. Thus, explicitly disable interrupts. This 1838 * also works around the MSI message reordering errata on certain 1839 * systems. 1840 */ 1841 IFDI_INTR_DISABLE(ctx); 1842 1843 /* Link status change */ 1844 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1845 em_handle_link(ctx); 1846 1847 if (reg_icr & E1000_ICR_RXO) 1848 sc->rx_overruns++; 1849 1850 if (hw->mac.type >= e1000_82540) 1851 em_newitr(sc, que, txr, rxr); 1852 1853 /* Reset state */ 1854 txr->tx_bytes = 0; 1855 txr->tx_packets = 0; 1856 rxr->rx_bytes = 0; 1857 rxr->rx_packets = 0; 1858 1859 return (FILTER_SCHEDULE_THREAD); 1860 } 1861 1862 static int 1863 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1864 { 1865 struct e1000_softc *sc = iflib_get_softc(ctx); 1866 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1867 1868 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1869 return (0); 1870 } 1871 1872 static int 1873 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1874 { 1875 struct e1000_softc *sc = iflib_get_softc(ctx); 1876 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1877 1878 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1879 return (0); 1880 } 1881 1882 static int 1883 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1884 { 1885 struct e1000_softc *sc = iflib_get_softc(ctx); 1886 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1887 1888 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1889 return (0); 1890 } 1891 1892 static int 1893 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1894 { 1895 struct e1000_softc *sc = iflib_get_softc(ctx); 1896 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1897 1898 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1899 return (0); 1900 } 1901 1902 /********************************************************************* 1903 * 1904 * MSI-X RX Interrupt Service routine 1905 * 1906 **********************************************************************/ 1907 static int 1908 em_msix_que(void *arg) 1909 { 1910 struct em_rx_queue *que = arg; 1911 struct e1000_softc *sc = que->sc; 1912 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1913 struct rx_ring *rxr = &que->rxr; 1914 1915 ++que->irqs; 1916 1917 em_newitr(sc, que, txr, rxr); 1918 1919 /* Reset state */ 1920 txr->tx_bytes = 0; 1921 txr->tx_packets = 0; 1922 rxr->rx_bytes = 0; 1923 rxr->rx_packets = 0; 1924 1925 return (FILTER_SCHEDULE_THREAD); 1926 } 1927 1928 /********************************************************************* 1929 * 1930 * MSI-X Link Fast Interrupt Service routine 1931 * 1932 **********************************************************************/ 1933 static int 1934 em_msix_link(void *arg) 1935 { 1936 struct e1000_softc *sc = arg; 1937 u32 reg_icr; 1938 1939 ++sc->link_irq; 1940 MPASS(sc->hw.back != NULL); 1941 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1942 1943 if (reg_icr & E1000_ICR_RXO) 1944 sc->rx_overruns++; 1945 1946 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1947 em_handle_link(sc->ctx); 1948 1949 /* Re-arm unconditionally */ 1950 if (sc->hw.mac.type >= igb_mac_min) { 1951 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1952 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1953 } else if (sc->hw.mac.type == e1000_82574) { 1954 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1955 E1000_IMS_LSC | E1000_IMS_OTHER); 1956 /* 1957 * Because we must read the ICR for this interrupt it may 1958 * clear other causes using autoclear, for this reason we 1959 * simply create a soft interrupt for all these vectors. 1960 */ 1961 if (reg_icr) 1962 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1963 } else 1964 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1965 1966 return (FILTER_HANDLED); 1967 } 1968 1969 static void 1970 em_handle_link(void *context) 1971 { 1972 if_ctx_t ctx = context; 1973 struct e1000_softc *sc = iflib_get_softc(ctx); 1974 1975 sc->hw.mac.get_link_status = 1; 1976 iflib_admin_intr_deferred(ctx); 1977 } 1978 1979 /********************************************************************* 1980 * 1981 * Media Ioctl callback 1982 * 1983 * This routine is called whenever the user queries the status of 1984 * the interface using ifconfig. 1985 * 1986 **********************************************************************/ 1987 static void 1988 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1989 { 1990 struct e1000_softc *sc = iflib_get_softc(ctx); 1991 u_char fiber_type = IFM_1000_SX; 1992 1993 INIT_DEBUGOUT("em_if_media_status: begin"); 1994 1995 iflib_admin_intr_deferred(ctx); 1996 1997 ifmr->ifm_status = IFM_AVALID; 1998 ifmr->ifm_active = IFM_ETHER; 1999 2000 if (!sc->link_active) { 2001 return; 2002 } 2003 2004 ifmr->ifm_status |= IFM_ACTIVE; 2005 2006 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 2007 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2008 if (sc->hw.mac.type == e1000_82545) 2009 fiber_type = IFM_1000_LX; 2010 ifmr->ifm_active |= fiber_type | IFM_FDX; 2011 } else { 2012 switch (sc->link_speed) { 2013 case 10: 2014 ifmr->ifm_active |= IFM_10_T; 2015 break; 2016 case 100: 2017 ifmr->ifm_active |= IFM_100_TX; 2018 break; 2019 case 1000: 2020 ifmr->ifm_active |= IFM_1000_T; 2021 break; 2022 } 2023 if (sc->link_duplex == FULL_DUPLEX) 2024 ifmr->ifm_active |= IFM_FDX; 2025 else 2026 ifmr->ifm_active |= IFM_HDX; 2027 } 2028 } 2029 2030 /********************************************************************* 2031 * 2032 * Media Ioctl callback 2033 * 2034 * This routine is called when the user changes speed/duplex using 2035 * media/mediopt option with ifconfig. 2036 * 2037 **********************************************************************/ 2038 static int 2039 em_if_media_change(if_ctx_t ctx) 2040 { 2041 struct e1000_softc *sc = iflib_get_softc(ctx); 2042 struct ifmedia *ifm = iflib_get_media(ctx); 2043 2044 INIT_DEBUGOUT("em_if_media_change: begin"); 2045 2046 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2047 return (EINVAL); 2048 2049 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2050 case IFM_AUTO: 2051 sc->hw.mac.autoneg = DO_AUTO_NEG; 2052 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2053 break; 2054 case IFM_1000_LX: 2055 case IFM_1000_SX: 2056 case IFM_1000_T: 2057 sc->hw.mac.autoneg = DO_AUTO_NEG; 2058 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2059 break; 2060 case IFM_100_TX: 2061 sc->hw.mac.autoneg = false; 2062 sc->hw.phy.autoneg_advertised = 0; 2063 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2064 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2065 else 2066 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2067 break; 2068 case IFM_10_T: 2069 sc->hw.mac.autoneg = false; 2070 sc->hw.phy.autoneg_advertised = 0; 2071 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2072 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2073 else 2074 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2075 break; 2076 default: 2077 device_printf(sc->dev, "Unsupported media type\n"); 2078 } 2079 2080 em_if_init(ctx); 2081 2082 return (0); 2083 } 2084 2085 static int 2086 em_if_set_promisc(if_ctx_t ctx, int flags) 2087 { 2088 struct e1000_softc *sc = iflib_get_softc(ctx); 2089 if_t ifp = iflib_get_ifp(ctx); 2090 u32 reg_rctl; 2091 int mcnt = 0; 2092 2093 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2094 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2095 if (flags & IFF_ALLMULTI) 2096 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2097 else 2098 mcnt = min(if_llmaddr_count(ifp), 2099 MAX_NUM_MULTICAST_ADDRESSES); 2100 2101 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2102 reg_rctl &= (~E1000_RCTL_MPE); 2103 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2104 2105 if (flags & IFF_PROMISC) { 2106 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2107 em_if_vlan_filter_disable(sc); 2108 /* Turn this on if you want to see bad packets */ 2109 if (em_debug_sbp) 2110 reg_rctl |= E1000_RCTL_SBP; 2111 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2112 } else { 2113 if (flags & IFF_ALLMULTI) { 2114 reg_rctl |= E1000_RCTL_MPE; 2115 reg_rctl &= ~E1000_RCTL_UPE; 2116 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2117 } 2118 if (em_if_vlan_filter_used(ctx)) 2119 em_if_vlan_filter_enable(sc); 2120 } 2121 return (0); 2122 } 2123 2124 static u_int 2125 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2126 { 2127 u8 *mta = arg; 2128 2129 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2130 return (0); 2131 2132 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2133 2134 return (1); 2135 } 2136 2137 /********************************************************************* 2138 * Multicast Update 2139 * 2140 * This routine is called whenever multicast address list is updated. 2141 * 2142 **********************************************************************/ 2143 static void 2144 em_if_multi_set(if_ctx_t ctx) 2145 { 2146 struct e1000_softc *sc = iflib_get_softc(ctx); 2147 if_t ifp = iflib_get_ifp(ctx); 2148 u8 *mta; /* Multicast array memory */ 2149 u32 reg_rctl = 0; 2150 int mcnt = 0; 2151 2152 IOCTL_DEBUGOUT("em_set_multi: begin"); 2153 2154 mta = sc->mta; 2155 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2156 2157 if (sc->hw.mac.type == e1000_82542 && 2158 sc->hw.revision_id == E1000_REVISION_2) { 2159 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2160 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2161 e1000_pci_clear_mwi(&sc->hw); 2162 reg_rctl |= E1000_RCTL_RST; 2163 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2164 msec_delay(5); 2165 } 2166 2167 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2168 2169 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2170 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2171 2172 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2173 2174 if (if_getflags(ifp) & IFF_PROMISC) 2175 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2176 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2177 if_getflags(ifp) & IFF_ALLMULTI) { 2178 reg_rctl |= E1000_RCTL_MPE; 2179 reg_rctl &= ~E1000_RCTL_UPE; 2180 } else 2181 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2182 2183 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2184 2185 if (sc->hw.mac.type == e1000_82542 && 2186 sc->hw.revision_id == E1000_REVISION_2) { 2187 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2188 reg_rctl &= ~E1000_RCTL_RST; 2189 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2190 msec_delay(5); 2191 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2192 e1000_pci_set_mwi(&sc->hw); 2193 } 2194 } 2195 2196 /********************************************************************* 2197 * Timer routine 2198 * 2199 * This routine schedules em_if_update_admin_status() to check for 2200 * link status and to gather statistics as well as to perform some 2201 * controller-specific hardware patting. 2202 * 2203 **********************************************************************/ 2204 static void 2205 em_if_timer(if_ctx_t ctx, uint16_t qid) 2206 { 2207 if (qid != 0) 2208 return; 2209 2210 iflib_admin_intr_deferred(ctx); 2211 } 2212 2213 static void 2214 em_if_update_admin_status(if_ctx_t ctx) 2215 { 2216 struct e1000_softc *sc = iflib_get_softc(ctx); 2217 struct e1000_hw *hw = &sc->hw; 2218 device_t dev = iflib_get_dev(ctx); 2219 u32 link_check, thstat, ctrl; 2220 bool automasked = false; 2221 2222 link_check = thstat = ctrl = 0; 2223 /* Get the cached link value or read phy for real */ 2224 switch (hw->phy.media_type) { 2225 case e1000_media_type_copper: 2226 if (hw->mac.get_link_status) { 2227 if (hw->mac.type == e1000_pch_spt) 2228 msec_delay(50); 2229 /* Do the work to read phy */ 2230 e1000_check_for_link(hw); 2231 link_check = !hw->mac.get_link_status; 2232 if (link_check) /* ESB2 fix */ 2233 e1000_cfg_on_link_up(hw); 2234 } else { 2235 link_check = true; 2236 } 2237 break; 2238 case e1000_media_type_fiber: 2239 e1000_check_for_link(hw); 2240 link_check = 2241 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2242 break; 2243 case e1000_media_type_internal_serdes: 2244 e1000_check_for_link(hw); 2245 link_check = hw->mac.serdes_has_link; 2246 break; 2247 /* VF device is type_unknown */ 2248 case e1000_media_type_unknown: 2249 e1000_check_for_link(hw); 2250 link_check = !hw->mac.get_link_status; 2251 /* FALLTHROUGH */ 2252 default: 2253 break; 2254 } 2255 2256 /* Check for thermal downshift or shutdown */ 2257 if (hw->mac.type == e1000_i350) { 2258 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2259 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2260 } 2261 2262 /* Now check for a transition */ 2263 if (link_check && (sc->link_active == 0)) { 2264 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2265 &sc->link_duplex); 2266 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2267 if ((sc->link_speed != SPEED_1000) && 2268 ((hw->mac.type == e1000_82571) || 2269 (hw->mac.type == e1000_82572))) { 2270 int tarc0; 2271 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2272 tarc0 &= ~TARC_SPEED_MODE_BIT; 2273 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2274 } 2275 if (bootverbose) 2276 device_printf(dev, "Link is up %d Mbps %s\n", 2277 sc->link_speed, 2278 ((sc->link_duplex == FULL_DUPLEX) ? 2279 "Full Duplex" : "Half Duplex")); 2280 sc->link_active = 1; 2281 sc->smartspeed = 0; 2282 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2283 E1000_CTRL_EXT_LINK_MODE_GMII && 2284 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2285 device_printf(dev, "Link: thermal downshift\n"); 2286 /* Delay Link Up for Phy update */ 2287 if (((hw->mac.type == e1000_i210) || 2288 (hw->mac.type == e1000_i211)) && 2289 (hw->phy.id == I210_I_PHY_ID)) 2290 msec_delay(I210_LINK_DELAY); 2291 /* Reset if the media type changed. */ 2292 if (hw->dev_spec._82575.media_changed && 2293 hw->mac.type >= igb_mac_min) { 2294 hw->dev_spec._82575.media_changed = false; 2295 sc->flags |= IGB_MEDIA_RESET; 2296 em_reset(ctx); 2297 } 2298 /* Only do TSO on gigabit for older chips due to errata */ 2299 if (hw->mac.type < igb_mac_min) 2300 automasked = em_automask_tso(ctx); 2301 2302 /* Automasking resets the interface so don't mark it up yet */ 2303 if (!automasked) 2304 iflib_link_state_change(ctx, LINK_STATE_UP, 2305 IF_Mbps(sc->link_speed)); 2306 } else if (!link_check && (sc->link_active == 1)) { 2307 sc->link_speed = 0; 2308 sc->link_duplex = 0; 2309 sc->link_active = 0; 2310 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2311 } 2312 em_update_stats_counters(sc); 2313 2314 /* Reset LAA into RAR[0] on 82571 */ 2315 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2316 e1000_rar_set(hw, hw->mac.addr, 0); 2317 2318 if (hw->mac.type < em_mac_min) 2319 lem_smartspeed(sc); 2320 } 2321 2322 static void 2323 em_if_watchdog_reset(if_ctx_t ctx) 2324 { 2325 struct e1000_softc *sc = iflib_get_softc(ctx); 2326 2327 /* 2328 * Just count the event; iflib(4) will already trigger a 2329 * sufficient reset of the controller. 2330 */ 2331 sc->watchdog_events++; 2332 } 2333 2334 /********************************************************************* 2335 * 2336 * This routine disables all traffic on the adapter by issuing a 2337 * global reset on the MAC. 2338 * 2339 **********************************************************************/ 2340 static void 2341 em_if_stop(if_ctx_t ctx) 2342 { 2343 struct e1000_softc *sc = iflib_get_softc(ctx); 2344 2345 INIT_DEBUGOUT("em_if_stop: begin"); 2346 2347 /* I219 needs special flushing to avoid hangs */ 2348 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2349 em_flush_desc_rings(sc); 2350 2351 e1000_reset_hw(&sc->hw); 2352 if (sc->hw.mac.type >= e1000_82544) 2353 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2354 2355 e1000_led_off(&sc->hw); 2356 e1000_cleanup_led(&sc->hw); 2357 } 2358 2359 /********************************************************************* 2360 * 2361 * Determine hardware revision. 2362 * 2363 **********************************************************************/ 2364 static void 2365 em_identify_hardware(if_ctx_t ctx) 2366 { 2367 device_t dev = iflib_get_dev(ctx); 2368 struct e1000_softc *sc = iflib_get_softc(ctx); 2369 2370 /* Make sure our PCI config space has the necessary stuff set */ 2371 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2372 2373 /* Save off the information about this board */ 2374 sc->hw.vendor_id = pci_get_vendor(dev); 2375 sc->hw.device_id = pci_get_device(dev); 2376 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2377 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2378 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2379 2380 /* Do Shared Code Init and Setup */ 2381 if (e1000_set_mac_type(&sc->hw)) { 2382 device_printf(dev, "Setup init failure\n"); 2383 return; 2384 } 2385 2386 /* Are we a VF device? */ 2387 if ((sc->hw.mac.type == e1000_vfadapt) || 2388 (sc->hw.mac.type == e1000_vfadapt_i350)) 2389 sc->vf_ifp = 1; 2390 else 2391 sc->vf_ifp = 0; 2392 } 2393 2394 static int 2395 em_allocate_pci_resources(if_ctx_t ctx) 2396 { 2397 struct e1000_softc *sc = iflib_get_softc(ctx); 2398 device_t dev = iflib_get_dev(ctx); 2399 int rid, val; 2400 2401 rid = PCIR_BAR(0); 2402 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2403 RF_ACTIVE); 2404 if (sc->memory == NULL) { 2405 device_printf(dev, 2406 "Unable to allocate bus resource: memory\n"); 2407 return (ENXIO); 2408 } 2409 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2410 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2411 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2412 2413 /* Only older adapters use IO mapping */ 2414 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2415 /* Figure our where our IO BAR is ? */ 2416 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2417 val = pci_read_config(dev, rid, 4); 2418 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2419 break; 2420 } 2421 rid += 4; 2422 /* check for 64bit BAR */ 2423 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2424 rid += 4; 2425 } 2426 if (rid >= PCIR_CIS) { 2427 device_printf(dev, "Unable to locate IO BAR\n"); 2428 return (ENXIO); 2429 } 2430 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2431 &rid, RF_ACTIVE); 2432 if (sc->ioport == NULL) { 2433 device_printf(dev, 2434 "Unable to allocate bus resource: ioport\n"); 2435 return (ENXIO); 2436 } 2437 sc->hw.io_base = 0; 2438 sc->osdep.io_bus_space_tag = 2439 rman_get_bustag(sc->ioport); 2440 sc->osdep.io_bus_space_handle = 2441 rman_get_bushandle(sc->ioport); 2442 } 2443 2444 sc->hw.back = &sc->osdep; 2445 2446 return (0); 2447 } 2448 2449 /********************************************************************* 2450 * 2451 * Set up the MSI-X Interrupt handlers 2452 * 2453 **********************************************************************/ 2454 static int 2455 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2456 { 2457 struct e1000_softc *sc = iflib_get_softc(ctx); 2458 struct em_rx_queue *rx_que = sc->rx_queues; 2459 struct em_tx_queue *tx_que = sc->tx_queues; 2460 int error, rid, i, vector = 0, rx_vectors; 2461 char buf[16]; 2462 2463 /* First set up ring resources */ 2464 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2465 rid = vector + 1; 2466 snprintf(buf, sizeof(buf), "rxq%d", i); 2467 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2468 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2469 if (error) { 2470 device_printf(iflib_get_dev(ctx), 2471 "Failed to allocate que int %d err: %d", 2472 i, error); 2473 sc->rx_num_queues = i + 1; 2474 goto fail; 2475 } 2476 2477 rx_que->msix = vector; 2478 2479 /* 2480 * Set the bit to enable interrupt 2481 * in E1000_IMS -- bits 20 and 21 2482 * are for RX0 and RX1, note this has 2483 * NOTHING to do with the MSI-X vector 2484 */ 2485 if (sc->hw.mac.type == e1000_82574) { 2486 rx_que->eims = 1 << (20 + i); 2487 sc->ims |= rx_que->eims; 2488 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2489 } else if (sc->hw.mac.type == e1000_82575) 2490 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2491 else 2492 rx_que->eims = 1 << vector; 2493 } 2494 rx_vectors = vector; 2495 2496 vector = 0; 2497 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2498 snprintf(buf, sizeof(buf), "txq%d", i); 2499 tx_que = &sc->tx_queues[i]; 2500 iflib_softirq_alloc_generic(ctx, 2501 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2502 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2503 2504 tx_que->msix = (vector % sc->rx_num_queues); 2505 2506 /* 2507 * Set the bit to enable interrupt 2508 * in E1000_IMS -- bits 22 and 23 2509 * are for TX0 and TX1, note this has 2510 * NOTHING to do with the MSI-X vector 2511 */ 2512 if (sc->hw.mac.type == e1000_82574) { 2513 tx_que->eims = 1 << (22 + i); 2514 sc->ims |= tx_que->eims; 2515 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2516 } else if (sc->hw.mac.type == e1000_82575) { 2517 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2518 } else { 2519 tx_que->eims = 1 << i; 2520 } 2521 } 2522 2523 /* Link interrupt */ 2524 rid = rx_vectors + 1; 2525 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2526 em_msix_link, sc, 0, "aq"); 2527 2528 if (error) { 2529 device_printf(iflib_get_dev(ctx), 2530 "Failed to register admin handler"); 2531 goto fail; 2532 } 2533 sc->linkvec = rx_vectors; 2534 if (sc->hw.mac.type < igb_mac_min) { 2535 sc->ivars |= (8 | rx_vectors) << 16; 2536 sc->ivars |= 0x80000000; 2537 /* Enable the "Other" interrupt type for link status change */ 2538 sc->ims |= E1000_IMS_OTHER; 2539 } 2540 2541 return (0); 2542 fail: 2543 iflib_irq_free(ctx, &sc->irq); 2544 rx_que = sc->rx_queues; 2545 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2546 iflib_irq_free(ctx, &rx_que->que_irq); 2547 return (error); 2548 } 2549 2550 static void 2551 igb_configure_queues(struct e1000_softc *sc) 2552 { 2553 struct e1000_hw *hw = &sc->hw; 2554 struct em_rx_queue *rx_que; 2555 struct em_tx_queue *tx_que; 2556 u32 tmp, ivar = 0, newitr = 0; 2557 2558 /* First turn on RSS capability */ 2559 if (hw->mac.type != e1000_82575) 2560 E1000_WRITE_REG(hw, E1000_GPIE, 2561 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2562 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2563 2564 /* Turn on MSI-X */ 2565 switch (hw->mac.type) { 2566 case e1000_82580: 2567 case e1000_i350: 2568 case e1000_i354: 2569 case e1000_i210: 2570 case e1000_i211: 2571 case e1000_vfadapt: 2572 case e1000_vfadapt_i350: 2573 /* RX entries */ 2574 for (int i = 0; i < sc->rx_num_queues; i++) { 2575 u32 index = i >> 1; 2576 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2577 rx_que = &sc->rx_queues[i]; 2578 if (i & 1) { 2579 ivar &= 0xFF00FFFF; 2580 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2581 16; 2582 } else { 2583 ivar &= 0xFFFFFF00; 2584 ivar |= rx_que->msix | E1000_IVAR_VALID; 2585 } 2586 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2587 } 2588 /* TX entries */ 2589 for (int i = 0; i < sc->tx_num_queues; i++) { 2590 u32 index = i >> 1; 2591 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2592 tx_que = &sc->tx_queues[i]; 2593 if (i & 1) { 2594 ivar &= 0x00FFFFFF; 2595 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2596 24; 2597 } else { 2598 ivar &= 0xFFFF00FF; 2599 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2600 8; 2601 } 2602 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2603 sc->que_mask |= tx_que->eims; 2604 } 2605 2606 /* And for the link interrupt */ 2607 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2608 sc->link_mask = 1 << sc->linkvec; 2609 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2610 break; 2611 case e1000_82576: 2612 /* RX entries */ 2613 for (int i = 0; i < sc->rx_num_queues; i++) { 2614 u32 index = i & 0x7; /* Each IVAR has two entries */ 2615 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2616 rx_que = &sc->rx_queues[i]; 2617 if (i < 8) { 2618 ivar &= 0xFFFFFF00; 2619 ivar |= rx_que->msix | E1000_IVAR_VALID; 2620 } else { 2621 ivar &= 0xFF00FFFF; 2622 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2623 16; 2624 } 2625 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2626 sc->que_mask |= rx_que->eims; 2627 } 2628 /* TX entries */ 2629 for (int i = 0; i < sc->tx_num_queues; i++) { 2630 u32 index = i & 0x7; /* Each IVAR has two entries */ 2631 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2632 tx_que = &sc->tx_queues[i]; 2633 if (i < 8) { 2634 ivar &= 0xFFFF00FF; 2635 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2636 8; 2637 } else { 2638 ivar &= 0x00FFFFFF; 2639 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2640 24; 2641 } 2642 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2643 sc->que_mask |= tx_que->eims; 2644 } 2645 2646 /* And for the link interrupt */ 2647 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2648 sc->link_mask = 1 << sc->linkvec; 2649 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2650 break; 2651 2652 case e1000_82575: 2653 /* enable MSI-X support*/ 2654 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2655 tmp |= E1000_CTRL_EXT_PBA_CLR; 2656 /* Auto-Mask interrupts upon ICR read. */ 2657 tmp |= E1000_CTRL_EXT_EIAME; 2658 tmp |= E1000_CTRL_EXT_IRCA; 2659 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2660 2661 /* Queues */ 2662 for (int i = 0; i < sc->rx_num_queues; i++) { 2663 rx_que = &sc->rx_queues[i]; 2664 tmp = E1000_EICR_RX_QUEUE0 << i; 2665 tmp |= E1000_EICR_TX_QUEUE0 << i; 2666 rx_que->eims = tmp; 2667 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2668 rx_que->eims); 2669 sc->que_mask |= rx_que->eims; 2670 } 2671 2672 /* Link */ 2673 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2674 E1000_EIMS_OTHER); 2675 sc->link_mask |= E1000_EIMS_OTHER; 2676 default: 2677 break; 2678 } 2679 2680 /* Set the igb starting interrupt rate */ 2681 if (em_max_interrupt_rate > 0) { 2682 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2683 2684 if (hw->mac.type == e1000_82575) 2685 newitr |= newitr << 16; 2686 else 2687 newitr |= E1000_EITR_CNT_IGNR; 2688 2689 for (int i = 0; i < sc->rx_num_queues; i++) { 2690 rx_que = &sc->rx_queues[i]; 2691 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2692 } 2693 } 2694 2695 return; 2696 } 2697 2698 static void 2699 em_free_pci_resources(if_ctx_t ctx) 2700 { 2701 struct e1000_softc *sc = iflib_get_softc(ctx); 2702 struct em_rx_queue *que = sc->rx_queues; 2703 device_t dev = iflib_get_dev(ctx); 2704 2705 /* Release all MSI-X queue resources */ 2706 if (sc->intr_type == IFLIB_INTR_MSIX) 2707 iflib_irq_free(ctx, &sc->irq); 2708 2709 if (que != NULL) { 2710 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2711 iflib_irq_free(ctx, &que->que_irq); 2712 } 2713 } 2714 2715 if (sc->memory != NULL) { 2716 bus_release_resource(dev, SYS_RES_MEMORY, 2717 rman_get_rid(sc->memory), sc->memory); 2718 sc->memory = NULL; 2719 } 2720 2721 if (sc->flash != NULL) { 2722 bus_release_resource(dev, SYS_RES_MEMORY, 2723 rman_get_rid(sc->flash), sc->flash); 2724 sc->flash = NULL; 2725 } 2726 2727 if (sc->ioport != NULL) { 2728 bus_release_resource(dev, SYS_RES_IOPORT, 2729 rman_get_rid(sc->ioport), sc->ioport); 2730 sc->ioport = NULL; 2731 } 2732 } 2733 2734 /* Set up MSI or MSI-X */ 2735 static int 2736 em_setup_msix(if_ctx_t ctx) 2737 { 2738 struct e1000_softc *sc = iflib_get_softc(ctx); 2739 2740 if (sc->hw.mac.type == e1000_82574) { 2741 em_enable_vectors_82574(ctx); 2742 } 2743 return (0); 2744 } 2745 2746 /********************************************************************* 2747 * 2748 * Workaround for SmartSpeed on 82541 and 82547 controllers 2749 * 2750 **********************************************************************/ 2751 static void 2752 lem_smartspeed(struct e1000_softc *sc) 2753 { 2754 u16 phy_tmp; 2755 2756 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2757 sc->hw.mac.autoneg == 0 || 2758 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2759 return; 2760 2761 if (sc->smartspeed == 0) { 2762 /* If Master/Slave config fault is asserted twice, 2763 * we assume back-to-back */ 2764 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2765 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2766 return; 2767 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2768 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2769 e1000_read_phy_reg(&sc->hw, 2770 PHY_1000T_CTRL, &phy_tmp); 2771 if(phy_tmp & CR_1000T_MS_ENABLE) { 2772 phy_tmp &= ~CR_1000T_MS_ENABLE; 2773 e1000_write_phy_reg(&sc->hw, 2774 PHY_1000T_CTRL, phy_tmp); 2775 sc->smartspeed++; 2776 if(sc->hw.mac.autoneg && 2777 !e1000_copper_link_autoneg(&sc->hw) && 2778 !e1000_read_phy_reg(&sc->hw, 2779 PHY_CONTROL, &phy_tmp)) { 2780 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2781 MII_CR_RESTART_AUTO_NEG); 2782 e1000_write_phy_reg(&sc->hw, 2783 PHY_CONTROL, phy_tmp); 2784 } 2785 } 2786 } 2787 return; 2788 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2789 /* If still no link, perhaps using 2/3 pair cable */ 2790 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2791 phy_tmp |= CR_1000T_MS_ENABLE; 2792 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2793 if(sc->hw.mac.autoneg && 2794 !e1000_copper_link_autoneg(&sc->hw) && 2795 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2796 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2797 MII_CR_RESTART_AUTO_NEG); 2798 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2799 } 2800 } 2801 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2802 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2803 sc->smartspeed = 0; 2804 } 2805 2806 /********************************************************************* 2807 * 2808 * Initialize the DMA Coalescing feature 2809 * 2810 **********************************************************************/ 2811 static void 2812 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2813 { 2814 device_t dev = sc->dev; 2815 struct e1000_hw *hw = &sc->hw; 2816 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2817 u16 hwm; 2818 u16 max_frame_size; 2819 2820 if (hw->mac.type == e1000_i211) 2821 return; 2822 2823 max_frame_size = sc->shared->isc_max_frame_size; 2824 if (hw->mac.type > e1000_82580) { 2825 2826 if (sc->dmac == 0) { /* Disabling it */ 2827 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2828 return; 2829 } else 2830 device_printf(dev, "DMA Coalescing enabled\n"); 2831 2832 /* Set starting threshold */ 2833 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2834 2835 hwm = 64 * pba - max_frame_size / 16; 2836 if (hwm < 64 * (pba - 6)) 2837 hwm = 64 * (pba - 6); 2838 reg = E1000_READ_REG(hw, E1000_FCRTC); 2839 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2840 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2841 & E1000_FCRTC_RTH_COAL_MASK); 2842 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2843 2844 2845 dmac = pba - max_frame_size / 512; 2846 if (dmac < pba - 10) 2847 dmac = pba - 10; 2848 reg = E1000_READ_REG(hw, E1000_DMACR); 2849 reg &= ~E1000_DMACR_DMACTHR_MASK; 2850 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2851 & E1000_DMACR_DMACTHR_MASK); 2852 2853 /* transition to L0x or L1 if available..*/ 2854 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2855 2856 /* Check if status is 2.5Gb backplane connection 2857 * before configuration of watchdog timer, which is 2858 * in msec values in 12.8usec intervals 2859 * watchdog timer= msec values in 32usec intervals 2860 * for non 2.5Gb connection 2861 */ 2862 if (hw->mac.type == e1000_i354) { 2863 int status = E1000_READ_REG(hw, E1000_STATUS); 2864 if ((status & E1000_STATUS_2P5_SKU) && 2865 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2866 reg |= ((sc->dmac * 5) >> 6); 2867 else 2868 reg |= (sc->dmac >> 5); 2869 } else { 2870 reg |= (sc->dmac >> 5); 2871 } 2872 2873 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2874 2875 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2876 2877 /* Set the interval before transition */ 2878 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2879 if (hw->mac.type == e1000_i350) 2880 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2881 /* 2882 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2883 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2884 */ 2885 if (hw->mac.type == e1000_i354) { 2886 int status = E1000_READ_REG(hw, E1000_STATUS); 2887 if ((status & E1000_STATUS_2P5_SKU) && 2888 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2889 reg |= 0xA; 2890 else 2891 reg |= 0x4; 2892 } else { 2893 reg |= 0x4; 2894 } 2895 2896 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2897 2898 /* free space in tx packet buffer to wake from DMA coal */ 2899 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2900 (2 * max_frame_size)) >> 6); 2901 2902 /* make low power state decision controlled by DMA coal */ 2903 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2904 reg &= ~E1000_PCIEMISC_LX_DECISION; 2905 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2906 2907 } else if (hw->mac.type == e1000_82580) { 2908 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2909 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2910 reg & ~E1000_PCIEMISC_LX_DECISION); 2911 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2912 } 2913 } 2914 /********************************************************************* 2915 * The 3 following flush routines are used as a workaround in the 2916 * I219 client parts and only for them. 2917 * 2918 * em_flush_tx_ring - remove all descriptors from the tx_ring 2919 * 2920 * We want to clear all pending descriptors from the TX ring. 2921 * zeroing happens when the HW reads the regs. We assign the ring itself as 2922 * the data of the next descriptor. We don't care about the data we are about 2923 * to reset the HW. 2924 **********************************************************************/ 2925 static void 2926 em_flush_tx_ring(struct e1000_softc *sc) 2927 { 2928 struct e1000_hw *hw = &sc->hw; 2929 struct tx_ring *txr = &sc->tx_queues->txr; 2930 struct e1000_tx_desc *txd; 2931 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2932 u16 size = 512; 2933 2934 tctl = E1000_READ_REG(hw, E1000_TCTL); 2935 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2936 2937 txd = &txr->tx_base[txr->tx_cidx_processed]; 2938 2939 /* Just use the ring as a dummy buffer addr */ 2940 txd->buffer_addr = txr->tx_paddr; 2941 txd->lower.data = htole32(txd_lower | size); 2942 txd->upper.data = 0; 2943 2944 /* flush descriptors to memory before notifying the HW */ 2945 wmb(); 2946 2947 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2948 mb(); 2949 usec_delay(250); 2950 } 2951 2952 /********************************************************************* 2953 * em_flush_rx_ring - remove all descriptors from the rx_ring 2954 * 2955 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2956 **********************************************************************/ 2957 static void 2958 em_flush_rx_ring(struct e1000_softc *sc) 2959 { 2960 struct e1000_hw *hw = &sc->hw; 2961 u32 rctl, rxdctl; 2962 2963 rctl = E1000_READ_REG(hw, E1000_RCTL); 2964 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2965 E1000_WRITE_FLUSH(hw); 2966 usec_delay(150); 2967 2968 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2969 /* zero the lower 14 bits (prefetch and host thresholds) */ 2970 rxdctl &= 0xffffc000; 2971 /* 2972 * update thresholds: prefetch threshold to 31, host threshold to 1 2973 * and make sure the granularity is "descriptors" and not 2974 * "cache lines" 2975 */ 2976 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2977 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2978 2979 /* momentarily enable the RX ring for the changes to take effect */ 2980 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2981 E1000_WRITE_FLUSH(hw); 2982 usec_delay(150); 2983 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2984 } 2985 2986 /********************************************************************* 2987 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2988 * 2989 * In I219, the descriptor rings must be emptied before resetting the HW 2990 * or before changing the device state to D3 during runtime (runtime PM). 2991 * 2992 * Failure to do this will cause the HW to enter a unit hang state which can 2993 * only be released by PCI reset on the device 2994 * 2995 **********************************************************************/ 2996 static void 2997 em_flush_desc_rings(struct e1000_softc *sc) 2998 { 2999 struct e1000_hw *hw = &sc->hw; 3000 device_t dev = sc->dev; 3001 u16 hang_state; 3002 u32 fext_nvm11, tdlen; 3003 3004 /* First, disable MULR fix in FEXTNVM11 */ 3005 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 3006 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3007 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3008 3009 /* do nothing if we're not in faulty state, or the queue is empty */ 3010 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3011 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3012 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3013 return; 3014 em_flush_tx_ring(sc); 3015 3016 /* recheck, maybe the fault is caused by the rx ring */ 3017 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3018 if (hang_state & FLUSH_DESC_REQUIRED) 3019 em_flush_rx_ring(sc); 3020 } 3021 3022 3023 /********************************************************************* 3024 * 3025 * Initialize the hardware to a configuration as specified by the 3026 * sc structure. 3027 * 3028 **********************************************************************/ 3029 static void 3030 em_reset(if_ctx_t ctx) 3031 { 3032 device_t dev = iflib_get_dev(ctx); 3033 struct e1000_softc *sc = iflib_get_softc(ctx); 3034 if_t ifp = iflib_get_ifp(ctx); 3035 struct e1000_hw *hw = &sc->hw; 3036 u32 rx_buffer_size; 3037 u32 pba; 3038 3039 INIT_DEBUGOUT("em_reset: begin"); 3040 /* Let the firmware know the OS is in control */ 3041 em_get_hw_control(sc); 3042 3043 /* Set up smart power down as default off on newer adapters. */ 3044 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3045 hw->mac.type == e1000_82572)) { 3046 u16 phy_tmp = 0; 3047 3048 /* Speed up time to link by disabling smart power down. */ 3049 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3050 phy_tmp &= ~IGP02E1000_PM_SPD; 3051 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3052 } 3053 3054 /* 3055 * Packet Buffer Allocation (PBA) 3056 * Writing PBA sets the receive portion of the buffer 3057 * the remainder is used for the transmit buffer. 3058 */ 3059 switch (hw->mac.type) { 3060 /* 82547: Total Packet Buffer is 40K */ 3061 case e1000_82547: 3062 case e1000_82547_rev_2: 3063 if (hw->mac.max_frame_size > 8192) 3064 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3065 else 3066 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3067 break; 3068 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3069 case e1000_82571: 3070 case e1000_82572: 3071 case e1000_80003es2lan: 3072 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3073 break; 3074 /* 82573: Total Packet Buffer is 32K */ 3075 case e1000_82573: 3076 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3077 break; 3078 case e1000_82574: 3079 case e1000_82583: 3080 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 3081 break; 3082 case e1000_ich8lan: 3083 pba = E1000_PBA_8K; 3084 break; 3085 case e1000_ich9lan: 3086 case e1000_ich10lan: 3087 /* Boost Receive side for jumbo frames */ 3088 if (hw->mac.max_frame_size > 4096) 3089 pba = E1000_PBA_14K; 3090 else 3091 pba = E1000_PBA_10K; 3092 break; 3093 case e1000_pchlan: 3094 case e1000_pch2lan: 3095 case e1000_pch_lpt: 3096 case e1000_pch_spt: 3097 case e1000_pch_cnp: 3098 case e1000_pch_tgp: 3099 case e1000_pch_adp: 3100 case e1000_pch_mtp: 3101 case e1000_pch_ptp: 3102 pba = E1000_PBA_26K; 3103 break; 3104 case e1000_82575: 3105 pba = E1000_PBA_32K; 3106 break; 3107 case e1000_82576: 3108 case e1000_vfadapt: 3109 pba = E1000_READ_REG(hw, E1000_RXPBS); 3110 pba &= E1000_RXPBS_SIZE_MASK_82576; 3111 break; 3112 case e1000_82580: 3113 case e1000_i350: 3114 case e1000_i354: 3115 case e1000_vfadapt_i350: 3116 pba = E1000_READ_REG(hw, E1000_RXPBS); 3117 pba = e1000_rxpbs_adjust_82580(pba); 3118 break; 3119 case e1000_i210: 3120 case e1000_i211: 3121 pba = E1000_PBA_34K; 3122 break; 3123 default: 3124 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3125 if (hw->mac.max_frame_size > 8192) 3126 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3127 else 3128 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3129 } 3130 3131 /* Special needs in case of Jumbo frames */ 3132 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3133 u32 tx_space, min_tx, min_rx; 3134 pba = E1000_READ_REG(hw, E1000_PBA); 3135 tx_space = pba >> 16; 3136 pba &= 0xffff; 3137 min_tx = (hw->mac.max_frame_size + 3138 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3139 min_tx = roundup2(min_tx, 1024); 3140 min_tx >>= 10; 3141 min_rx = hw->mac.max_frame_size; 3142 min_rx = roundup2(min_rx, 1024); 3143 min_rx >>= 10; 3144 if (tx_space < min_tx && 3145 ((min_tx - tx_space) < pba)) { 3146 pba = pba - (min_tx - tx_space); 3147 /* 3148 * if short on rx space, rx wins 3149 * and must trump tx adjustment 3150 */ 3151 if (pba < min_rx) 3152 pba = min_rx; 3153 } 3154 E1000_WRITE_REG(hw, E1000_PBA, pba); 3155 } 3156 3157 if (hw->mac.type < igb_mac_min) 3158 E1000_WRITE_REG(hw, E1000_PBA, pba); 3159 3160 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3161 3162 /* 3163 * These parameters control the automatic generation (Tx) and 3164 * response (Rx) to Ethernet PAUSE frames. 3165 * - High water mark should allow for at least two frames to be 3166 * received after sending an XOFF. 3167 * - Low water mark works best when it is very near the high water 3168 mark. 3169 * This allows the receiver to restart by sending XON when it has 3170 * drained a bit. Here we use an arbitrary value of 1500 which will 3171 * restart after one full frame is pulled from the buffer. There 3172 * could be several smaller frames in the buffer and if so they will 3173 * not trigger the XON until their total number reduces the buffer 3174 * by 1500. 3175 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3176 */ 3177 rx_buffer_size = (pba & 0xffff) << 10; 3178 hw->fc.high_water = rx_buffer_size - 3179 roundup2(hw->mac.max_frame_size, 1024); 3180 hw->fc.low_water = hw->fc.high_water - 1500; 3181 3182 if (sc->fc) /* locally set flow control value? */ 3183 hw->fc.requested_mode = sc->fc; 3184 else 3185 hw->fc.requested_mode = e1000_fc_full; 3186 3187 if (hw->mac.type == e1000_80003es2lan) 3188 hw->fc.pause_time = 0xFFFF; 3189 else 3190 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3191 3192 hw->fc.send_xon = true; 3193 3194 /* Device specific overrides/settings */ 3195 switch (hw->mac.type) { 3196 case e1000_pchlan: 3197 /* Workaround: no TX flow ctrl for PCH */ 3198 hw->fc.requested_mode = e1000_fc_rx_pause; 3199 hw->fc.pause_time = 0xFFFF; /* override */ 3200 if (if_getmtu(ifp) > ETHERMTU) { 3201 hw->fc.high_water = 0x3500; 3202 hw->fc.low_water = 0x1500; 3203 } else { 3204 hw->fc.high_water = 0x5000; 3205 hw->fc.low_water = 0x3000; 3206 } 3207 hw->fc.refresh_time = 0x1000; 3208 break; 3209 case e1000_pch2lan: 3210 case e1000_pch_lpt: 3211 case e1000_pch_spt: 3212 case e1000_pch_cnp: 3213 case e1000_pch_tgp: 3214 case e1000_pch_adp: 3215 case e1000_pch_mtp: 3216 case e1000_pch_ptp: 3217 hw->fc.high_water = 0x5C20; 3218 hw->fc.low_water = 0x5048; 3219 hw->fc.pause_time = 0x0650; 3220 hw->fc.refresh_time = 0x0400; 3221 /* Jumbos need adjusted PBA */ 3222 if (if_getmtu(ifp) > ETHERMTU) 3223 E1000_WRITE_REG(hw, E1000_PBA, 12); 3224 else 3225 E1000_WRITE_REG(hw, E1000_PBA, 26); 3226 break; 3227 case e1000_82575: 3228 case e1000_82576: 3229 /* 8-byte granularity */ 3230 hw->fc.low_water = hw->fc.high_water - 8; 3231 break; 3232 case e1000_82580: 3233 case e1000_i350: 3234 case e1000_i354: 3235 case e1000_i210: 3236 case e1000_i211: 3237 case e1000_vfadapt: 3238 case e1000_vfadapt_i350: 3239 /* 16-byte granularity */ 3240 hw->fc.low_water = hw->fc.high_water - 16; 3241 break; 3242 case e1000_ich9lan: 3243 case e1000_ich10lan: 3244 if (if_getmtu(ifp) > ETHERMTU) { 3245 hw->fc.high_water = 0x2800; 3246 hw->fc.low_water = hw->fc.high_water - 8; 3247 break; 3248 } 3249 /* FALLTHROUGH */ 3250 default: 3251 if (hw->mac.type == e1000_80003es2lan) 3252 hw->fc.pause_time = 0xFFFF; 3253 break; 3254 } 3255 3256 /* I219 needs some special flushing to avoid hangs */ 3257 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3258 em_flush_desc_rings(sc); 3259 3260 /* Issue a global reset */ 3261 e1000_reset_hw(hw); 3262 if (hw->mac.type >= igb_mac_min) { 3263 E1000_WRITE_REG(hw, E1000_WUC, 0); 3264 } else { 3265 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3266 em_disable_aspm(sc); 3267 } 3268 if (sc->flags & IGB_MEDIA_RESET) { 3269 e1000_setup_init_funcs(hw, true); 3270 e1000_get_bus_info(hw); 3271 sc->flags &= ~IGB_MEDIA_RESET; 3272 } 3273 /* and a re-init */ 3274 if (e1000_init_hw(hw) < 0) { 3275 device_printf(dev, "Hardware Initialization Failed\n"); 3276 return; 3277 } 3278 if (hw->mac.type >= igb_mac_min) 3279 igb_init_dmac(sc, pba); 3280 3281 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3282 sc->pba = pba; 3283 3284 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3285 e1000_get_phy_info(hw); 3286 e1000_check_for_link(hw); 3287 } 3288 3289 /* 3290 * Initialise the RSS mapping for NICs that support multiple transmit/ 3291 * receive rings. 3292 */ 3293 3294 #define RSSKEYLEN 10 3295 static void 3296 em_initialize_rss_mapping(struct e1000_softc *sc) 3297 { 3298 uint8_t rss_key[4 * RSSKEYLEN]; 3299 uint32_t reta = 0; 3300 struct e1000_hw *hw = &sc->hw; 3301 int i; 3302 3303 /* 3304 * Configure RSS key 3305 */ 3306 arc4rand(rss_key, sizeof(rss_key), 0); 3307 for (i = 0; i < RSSKEYLEN; ++i) { 3308 uint32_t rssrk = 0; 3309 3310 rssrk = EM_RSSRK_VAL(rss_key, i); 3311 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3312 } 3313 3314 /* 3315 * Configure RSS redirect table in following fashion: 3316 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3317 */ 3318 for (i = 0; i < sizeof(reta); ++i) { 3319 uint32_t q; 3320 3321 q = (i % sc->rx_num_queues) << 7; 3322 reta |= q << (8 * i); 3323 } 3324 3325 for (i = 0; i < 32; ++i) 3326 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3327 3328 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3329 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3330 E1000_MRQC_RSS_FIELD_IPV4 | 3331 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3332 E1000_MRQC_RSS_FIELD_IPV6_EX | 3333 E1000_MRQC_RSS_FIELD_IPV6); 3334 } 3335 3336 static void 3337 igb_initialize_rss_mapping(struct e1000_softc *sc) 3338 { 3339 struct e1000_hw *hw = &sc->hw; 3340 int i; 3341 int queue_id; 3342 u32 reta; 3343 u32 rss_key[10], mrqc, shift = 0; 3344 3345 /* XXX? */ 3346 if (hw->mac.type == e1000_82575) 3347 shift = 6; 3348 3349 /* 3350 * The redirection table controls which destination 3351 * queue each bucket redirects traffic to. 3352 * Each DWORD represents four queues, with the LSB 3353 * being the first queue in the DWORD. 3354 * 3355 * This just allocates buckets to queues using round-robin 3356 * allocation. 3357 * 3358 * NOTE: It Just Happens to line up with the default 3359 * RSS allocation method. 3360 */ 3361 3362 /* Warning FM follows */ 3363 reta = 0; 3364 for (i = 0; i < 128; i++) { 3365 #ifdef RSS 3366 queue_id = rss_get_indirection_to_bucket(i); 3367 /* 3368 * If we have more queues than buckets, we'll 3369 * end up mapping buckets to a subset of the 3370 * queues. 3371 * 3372 * If we have more buckets than queues, we'll 3373 * end up instead assigning multiple buckets 3374 * to queues. 3375 * 3376 * Both are suboptimal, but we need to handle 3377 * the case so we don't go out of bounds 3378 * indexing arrays and such. 3379 */ 3380 queue_id = queue_id % sc->rx_num_queues; 3381 #else 3382 queue_id = (i % sc->rx_num_queues); 3383 #endif 3384 /* Adjust if required */ 3385 queue_id = queue_id << shift; 3386 3387 /* 3388 * The low 8 bits are for hash value (n+0); 3389 * The next 8 bits are for hash value (n+1), etc. 3390 */ 3391 reta = reta >> 8; 3392 reta = reta | ( ((uint32_t) queue_id) << 24); 3393 if ((i & 3) == 3) { 3394 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3395 reta = 0; 3396 } 3397 } 3398 3399 /* Now fill in hash table */ 3400 3401 /* 3402 * MRQC: Multiple Receive Queues Command 3403 * Set queuing to RSS control, number depends on the device. 3404 */ 3405 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3406 3407 #ifdef RSS 3408 /* XXX ew typecasting */ 3409 rss_getkey((uint8_t *) &rss_key); 3410 #else 3411 arc4rand(&rss_key, sizeof(rss_key), 0); 3412 #endif 3413 for (i = 0; i < 10; i++) 3414 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3415 3416 /* 3417 * Configure the RSS fields to hash upon. 3418 */ 3419 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3420 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3421 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3422 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3423 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3424 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3425 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3426 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3427 3428 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3429 } 3430 3431 /********************************************************************* 3432 * 3433 * Setup networking device structure and register interface media. 3434 * 3435 **********************************************************************/ 3436 static int 3437 em_setup_interface(if_ctx_t ctx) 3438 { 3439 if_t ifp = iflib_get_ifp(ctx); 3440 struct e1000_softc *sc = iflib_get_softc(ctx); 3441 if_softc_ctx_t scctx = sc->shared; 3442 3443 INIT_DEBUGOUT("em_setup_interface: begin"); 3444 3445 /* Single Queue */ 3446 if (sc->tx_num_queues == 1) { 3447 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3448 if_setsendqready(ifp); 3449 } 3450 3451 /* 3452 * Specify the media types supported by this adapter and register 3453 * callbacks to update media and link information 3454 */ 3455 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3456 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3457 u_char fiber_type = IFM_1000_SX; /* default type */ 3458 3459 if (sc->hw.mac.type == e1000_82545) 3460 fiber_type = IFM_1000_LX; 3461 ifmedia_add(sc->media, 3462 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3463 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3464 } else { 3465 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3466 ifmedia_add(sc->media, 3467 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3468 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3469 ifmedia_add(sc->media, 3470 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3471 if (sc->hw.phy.type != e1000_phy_ife) { 3472 ifmedia_add(sc->media, 3473 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3474 ifmedia_add(sc->media, 3475 IFM_ETHER | IFM_1000_T, 0, NULL); 3476 } 3477 } 3478 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3479 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3480 return (0); 3481 } 3482 3483 static int 3484 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3485 int ntxqs, int ntxqsets) 3486 { 3487 struct e1000_softc *sc = iflib_get_softc(ctx); 3488 if_softc_ctx_t scctx = sc->shared; 3489 int error = E1000_SUCCESS; 3490 struct em_tx_queue *que; 3491 int i, j; 3492 3493 MPASS(sc->tx_num_queues > 0); 3494 MPASS(sc->tx_num_queues == ntxqsets); 3495 3496 /* First allocate the top level queue structs */ 3497 if (!(sc->tx_queues = 3498 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3499 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3500 device_printf(iflib_get_dev(ctx), 3501 "Unable to allocate queue memory\n"); 3502 return(ENOMEM); 3503 } 3504 3505 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3506 /* Set up some basics */ 3507 3508 struct tx_ring *txr = &que->txr; 3509 txr->sc = que->sc = sc; 3510 que->me = txr->me = i; 3511 3512 /* Allocate report status array */ 3513 if (!(txr->tx_rsq = 3514 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3515 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3516 device_printf(iflib_get_dev(ctx), 3517 "failed to allocate rs_idxs memory\n"); 3518 error = ENOMEM; 3519 goto fail; 3520 } 3521 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3522 txr->tx_rsq[j] = QIDX_INVALID; 3523 /* get the virtual and physical address of hardware queues */ 3524 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3525 txr->tx_paddr = paddrs[i*ntxqs]; 3526 } 3527 3528 if (bootverbose) 3529 device_printf(iflib_get_dev(ctx), 3530 "allocated for %d tx_queues\n", sc->tx_num_queues); 3531 return (0); 3532 fail: 3533 em_if_queues_free(ctx); 3534 return (error); 3535 } 3536 3537 static int 3538 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3539 int nrxqs, int nrxqsets) 3540 { 3541 struct e1000_softc *sc = iflib_get_softc(ctx); 3542 int error = E1000_SUCCESS; 3543 struct em_rx_queue *que; 3544 int i; 3545 3546 MPASS(sc->rx_num_queues > 0); 3547 MPASS(sc->rx_num_queues == nrxqsets); 3548 3549 /* First allocate the top level queue structs */ 3550 if (!(sc->rx_queues = 3551 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3552 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3553 device_printf(iflib_get_dev(ctx), 3554 "Unable to allocate queue memory\n"); 3555 error = ENOMEM; 3556 goto fail; 3557 } 3558 3559 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3560 /* Set up some basics */ 3561 struct rx_ring *rxr = &que->rxr; 3562 rxr->sc = que->sc = sc; 3563 rxr->que = que; 3564 que->me = rxr->me = i; 3565 3566 /* get the virtual and physical address of hardware queues */ 3567 rxr->rx_base = 3568 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3569 rxr->rx_paddr = paddrs[i*nrxqs]; 3570 } 3571 3572 if (bootverbose) 3573 device_printf(iflib_get_dev(ctx), 3574 "allocated for %d rx_queues\n", sc->rx_num_queues); 3575 3576 return (0); 3577 fail: 3578 em_if_queues_free(ctx); 3579 return (error); 3580 } 3581 3582 static void 3583 em_if_queues_free(if_ctx_t ctx) 3584 { 3585 struct e1000_softc *sc = iflib_get_softc(ctx); 3586 struct em_tx_queue *tx_que = sc->tx_queues; 3587 struct em_rx_queue *rx_que = sc->rx_queues; 3588 3589 if (tx_que != NULL) { 3590 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3591 struct tx_ring *txr = &tx_que->txr; 3592 if (txr->tx_rsq == NULL) 3593 break; 3594 3595 free(txr->tx_rsq, M_DEVBUF); 3596 txr->tx_rsq = NULL; 3597 } 3598 free(sc->tx_queues, M_DEVBUF); 3599 sc->tx_queues = NULL; 3600 } 3601 3602 if (rx_que != NULL) { 3603 free(sc->rx_queues, M_DEVBUF); 3604 sc->rx_queues = NULL; 3605 } 3606 } 3607 3608 /********************************************************************* 3609 * 3610 * Enable transmit unit. 3611 * 3612 **********************************************************************/ 3613 static void 3614 em_initialize_transmit_unit(if_ctx_t ctx) 3615 { 3616 struct e1000_softc *sc = iflib_get_softc(ctx); 3617 if_softc_ctx_t scctx = sc->shared; 3618 struct em_tx_queue *que; 3619 struct tx_ring *txr; 3620 struct e1000_hw *hw = &sc->hw; 3621 u32 tctl, txdctl = 0, tarc, tipg = 0; 3622 3623 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3624 3625 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3626 u64 bus_addr; 3627 caddr_t offp, endp; 3628 3629 que = &sc->tx_queues[i]; 3630 txr = &que->txr; 3631 bus_addr = txr->tx_paddr; 3632 3633 /* Clear checksum offload context. */ 3634 offp = (caddr_t)&txr->csum_flags; 3635 endp = (caddr_t)(txr + 1); 3636 bzero(offp, endp - offp); 3637 3638 /* Base and Len of TX Ring */ 3639 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3640 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3641 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3642 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3643 /* Init the HEAD/TAIL indices */ 3644 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3645 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3646 3647 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3648 E1000_READ_REG(hw, E1000_TDBAL(i)), 3649 E1000_READ_REG(hw, E1000_TDLEN(i))); 3650 3651 txdctl = 0; /* clear txdctl */ 3652 txdctl |= 0x1f; /* PTHRESH */ 3653 txdctl |= 1 << 8; /* HTHRESH */ 3654 txdctl |= 1 << 16;/* WTHRESH */ 3655 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3656 txdctl |= E1000_TXDCTL_GRAN; 3657 txdctl |= 1 << 25; /* LWTHRESH */ 3658 3659 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3660 } 3661 3662 /* Set the default values for the Tx Inter Packet Gap timer */ 3663 switch (hw->mac.type) { 3664 case e1000_80003es2lan: 3665 tipg = DEFAULT_82543_TIPG_IPGR1; 3666 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3667 E1000_TIPG_IPGR2_SHIFT; 3668 break; 3669 case e1000_82542: 3670 tipg = DEFAULT_82542_TIPG_IPGT; 3671 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3672 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3673 break; 3674 default: 3675 if (hw->phy.media_type == e1000_media_type_fiber || 3676 hw->phy.media_type == e1000_media_type_internal_serdes) 3677 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3678 else 3679 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3680 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3681 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3682 } 3683 3684 if (hw->mac.type < igb_mac_min) { 3685 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3686 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3687 3688 if (sc->tx_int_delay.value > 0) 3689 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3690 } 3691 3692 if (hw->mac.type >= e1000_82540) 3693 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3694 3695 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3696 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3697 tarc |= TARC_SPEED_MODE_BIT; 3698 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3699 } else if (hw->mac.type == e1000_80003es2lan) { 3700 /* errata: program both queues to unweighted RR */ 3701 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3702 tarc |= 1; 3703 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3704 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3705 tarc |= 1; 3706 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3707 } else if (hw->mac.type == e1000_82574) { 3708 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3709 tarc |= TARC_ERRATA_BIT; 3710 if ( sc->tx_num_queues > 1) { 3711 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3712 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3713 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3714 } else 3715 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3716 } 3717 3718 /* Program the Transmit Control Register */ 3719 tctl = E1000_READ_REG(hw, E1000_TCTL); 3720 tctl &= ~E1000_TCTL_CT; 3721 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3722 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3723 3724 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3725 tctl |= E1000_TCTL_MULR; 3726 3727 /* This write will effectively turn on the transmit unit. */ 3728 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3729 3730 /* SPT and KBL errata workarounds */ 3731 if (hw->mac.type == e1000_pch_spt) { 3732 u32 reg; 3733 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3734 reg |= E1000_RCTL_RDMTS_HEX; 3735 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3736 /* i218-i219 Specification Update 1.5.4.5 */ 3737 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3738 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3739 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3740 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3741 } 3742 } 3743 3744 /********************************************************************* 3745 * 3746 * Enable receive unit. 3747 * 3748 **********************************************************************/ 3749 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3750 3751 static void 3752 em_initialize_receive_unit(if_ctx_t ctx) 3753 { 3754 struct e1000_softc *sc = iflib_get_softc(ctx); 3755 if_softc_ctx_t scctx = sc->shared; 3756 if_t ifp = iflib_get_ifp(ctx); 3757 struct e1000_hw *hw = &sc->hw; 3758 struct em_rx_queue *que; 3759 int i; 3760 uint32_t rctl, rxcsum; 3761 3762 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3763 3764 /* 3765 * Make sure receives are disabled while setting 3766 * up the descriptor ring 3767 */ 3768 rctl = E1000_READ_REG(hw, E1000_RCTL); 3769 /* Do not disable if ever enabled on this hardware */ 3770 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3771 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3772 3773 /* Setup the Receive Control Register */ 3774 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3775 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3776 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3777 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3778 3779 /* Do not store bad packets */ 3780 rctl &= ~E1000_RCTL_SBP; 3781 3782 /* Enable Long Packet receive */ 3783 if (if_getmtu(ifp) > ETHERMTU) 3784 rctl |= E1000_RCTL_LPE; 3785 else 3786 rctl &= ~E1000_RCTL_LPE; 3787 3788 /* Strip the CRC */ 3789 if (!em_disable_crc_stripping) 3790 rctl |= E1000_RCTL_SECRC; 3791 3792 /* lem/em default interrupt moderation */ 3793 if (hw->mac.type < igb_mac_min) { 3794 if (hw->mac.type >= e1000_82540) { 3795 E1000_WRITE_REG(hw, E1000_RADV, 3796 sc->rx_abs_int_delay.value); 3797 3798 /* Set the default interrupt throttling rate */ 3799 E1000_WRITE_REG(hw, E1000_ITR, 3800 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3801 } 3802 3803 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3804 * long latencies are observed, like Lenovo X60. This 3805 * change eliminates the problem, but since having positive 3806 * values in RDTR is a known source of problems on other 3807 * platforms another solution is being sought. 3808 */ 3809 if (hw->mac.type == e1000_82573) 3810 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3811 else 3812 E1000_WRITE_REG(hw, E1000_RDTR, 3813 sc->rx_int_delay.value); 3814 } 3815 3816 if (hw->mac.type >= em_mac_min) { 3817 uint32_t rfctl; 3818 /* Use extended rx descriptor formats */ 3819 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3820 rfctl |= E1000_RFCTL_EXTEN; 3821 3822 /* 3823 * When using MSI-X interrupts we need to throttle 3824 * using the EITR register (82574 only) 3825 */ 3826 if (hw->mac.type == e1000_82574) { 3827 for (int i = 0; i < 4; i++) 3828 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3829 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3830 /* Disable accelerated acknowledge */ 3831 rfctl |= E1000_RFCTL_ACK_DIS; 3832 } 3833 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3834 } 3835 3836 /* Set up L3 and L4 csum Rx descriptor offloads */ 3837 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3838 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3839 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3840 if (hw->mac.type > e1000_82575) 3841 rxcsum |= E1000_RXCSUM_CRCOFL; 3842 else if (hw->mac.type < em_mac_min && 3843 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3844 rxcsum |= E1000_RXCSUM_IPV6OFL; 3845 } else { 3846 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3847 if (hw->mac.type > e1000_82575) 3848 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3849 else if (hw->mac.type < em_mac_min) 3850 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3851 } 3852 3853 if (sc->rx_num_queues > 1) { 3854 /* RSS hash needed in the Rx descriptor */ 3855 rxcsum |= E1000_RXCSUM_PCSD; 3856 3857 if (hw->mac.type >= igb_mac_min) 3858 igb_initialize_rss_mapping(sc); 3859 else 3860 em_initialize_rss_mapping(sc); 3861 } 3862 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3863 3864 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3865 struct rx_ring *rxr = &que->rxr; 3866 /* Setup the Base and Length of the Rx Descriptor Ring */ 3867 u64 bus_addr = rxr->rx_paddr; 3868 #if 0 3869 u32 rdt = sc->rx_num_queues -1; /* default */ 3870 #endif 3871 3872 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3873 scctx->isc_nrxd[0] * 3874 sizeof(union e1000_rx_desc_extended)); 3875 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3876 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3877 /* Setup the Head and Tail Descriptor Pointers */ 3878 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3879 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3880 } 3881 3882 /* 3883 * Set PTHRESH for improved jumbo performance 3884 * According to 10.2.5.11 of Intel 82574 Datasheet, 3885 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3886 * Only write to RXDCTL(1) if there is a need for different 3887 * settings. 3888 */ 3889 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3890 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3891 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3892 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3893 } else if (hw->mac.type == e1000_82574) { 3894 for (int i = 0; i < sc->rx_num_queues; i++) { 3895 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3896 rxdctl |= 0x20; /* PTHRESH */ 3897 rxdctl |= 4 << 8; /* HTHRESH */ 3898 rxdctl |= 4 << 16;/* WTHRESH */ 3899 rxdctl |= 1 << 24; /* Switch to granularity */ 3900 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3901 } 3902 } else if (hw->mac.type >= igb_mac_min) { 3903 u32 psize, srrctl = 0; 3904 3905 if (if_getmtu(ifp) > ETHERMTU) { 3906 psize = scctx->isc_max_frame_size; 3907 /* are we on a vlan? */ 3908 if (if_vlantrunkinuse(ifp)) 3909 psize += VLAN_TAG_SIZE; 3910 3911 if (sc->vf_ifp) 3912 e1000_rlpml_set_vf(hw, psize); 3913 else 3914 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3915 } 3916 3917 /* Set maximum packet buffer len */ 3918 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3919 E1000_SRRCTL_BSIZEPKT_SHIFT; 3920 3921 /* 3922 * If TX flow control is disabled and there's >1 queue 3923 * defined, enable DROP. 3924 * 3925 * This drops frames rather than hanging the RX MAC for all 3926 * queues. 3927 */ 3928 if ((sc->rx_num_queues > 1) && 3929 (sc->fc == e1000_fc_none || 3930 sc->fc == e1000_fc_rx_pause)) { 3931 srrctl |= E1000_SRRCTL_DROP_EN; 3932 } 3933 /* Setup the Base and Length of the Rx Descriptor Rings */ 3934 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3935 i++, que++) { 3936 struct rx_ring *rxr = &que->rxr; 3937 u64 bus_addr = rxr->rx_paddr; 3938 u32 rxdctl; 3939 3940 #ifdef notyet 3941 /* Configure for header split? -- ignore for now */ 3942 rxr->hdr_split = igb_header_split; 3943 #else 3944 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3945 #endif 3946 3947 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3948 scctx->isc_nrxd[0] * 3949 sizeof(struct e1000_rx_desc)); 3950 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3951 (uint32_t)(bus_addr >> 32)); 3952 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3953 (uint32_t)bus_addr); 3954 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3955 /* Enable this Queue */ 3956 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3957 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3958 rxdctl &= 0xFFF00000; 3959 rxdctl |= IGB_RX_PTHRESH; 3960 rxdctl |= IGB_RX_HTHRESH << 8; 3961 rxdctl |= IGB_RX_WTHRESH << 16; 3962 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3963 } 3964 } else if (hw->mac.type >= e1000_pch2lan) { 3965 if (if_getmtu(ifp) > ETHERMTU) 3966 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3967 else 3968 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3969 } 3970 3971 /* Make sure VLAN Filters are off */ 3972 rctl &= ~E1000_RCTL_VFE; 3973 3974 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3975 if (hw->mac.type < igb_mac_min) { 3976 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3977 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3978 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3979 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3980 else if (sc->rx_mbuf_sz > 8192) 3981 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3982 else { 3983 rctl |= E1000_RCTL_SZ_2048; 3984 rctl &= ~E1000_RCTL_BSEX; 3985 } 3986 } else 3987 rctl |= E1000_RCTL_SZ_2048; 3988 3989 /* 3990 * rctl bits 11:10 are as follows 3991 * lem: reserved 3992 * em: DTYPE 3993 * igb: reserved 3994 * and should be 00 on all of the above 3995 */ 3996 rctl &= ~0x00000C00; 3997 3998 /* Write out the settings */ 3999 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4000 4001 return; 4002 } 4003 4004 static void 4005 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 4006 { 4007 struct e1000_softc *sc = iflib_get_softc(ctx); 4008 u32 index, bit; 4009 4010 index = (vtag >> 5) & 0x7F; 4011 bit = vtag & 0x1F; 4012 sc->shadow_vfta[index] |= (1 << bit); 4013 ++sc->num_vlans; 4014 em_if_vlan_filter_write(sc); 4015 } 4016 4017 static void 4018 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4019 { 4020 struct e1000_softc *sc = iflib_get_softc(ctx); 4021 u32 index, bit; 4022 4023 index = (vtag >> 5) & 0x7F; 4024 bit = vtag & 0x1F; 4025 sc->shadow_vfta[index] &= ~(1 << bit); 4026 --sc->num_vlans; 4027 em_if_vlan_filter_write(sc); 4028 } 4029 4030 static bool 4031 em_if_vlan_filter_capable(if_ctx_t ctx) 4032 { 4033 if_t ifp = iflib_get_ifp(ctx); 4034 4035 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4036 !em_disable_crc_stripping) 4037 return (true); 4038 4039 return (false); 4040 } 4041 4042 static bool 4043 em_if_vlan_filter_used(if_ctx_t ctx) 4044 { 4045 struct e1000_softc *sc = iflib_get_softc(ctx); 4046 4047 if (!em_if_vlan_filter_capable(ctx)) 4048 return (false); 4049 4050 for (int i = 0; i < EM_VFTA_SIZE; i++) 4051 if (sc->shadow_vfta[i] != 0) 4052 return (true); 4053 4054 return (false); 4055 } 4056 4057 static void 4058 em_if_vlan_filter_enable(struct e1000_softc *sc) 4059 { 4060 struct e1000_hw *hw = &sc->hw; 4061 u32 reg; 4062 4063 reg = E1000_READ_REG(hw, E1000_RCTL); 4064 reg &= ~E1000_RCTL_CFIEN; 4065 reg |= E1000_RCTL_VFE; 4066 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4067 } 4068 4069 static void 4070 em_if_vlan_filter_disable(struct e1000_softc *sc) 4071 { 4072 struct e1000_hw *hw = &sc->hw; 4073 u32 reg; 4074 4075 reg = E1000_READ_REG(hw, E1000_RCTL); 4076 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4077 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4078 } 4079 4080 static void 4081 em_if_vlan_filter_write(struct e1000_softc *sc) 4082 { 4083 struct e1000_hw *hw = &sc->hw; 4084 4085 if (sc->vf_ifp) 4086 return; 4087 4088 /* Disable interrupts for lem(4) devices during the filter change */ 4089 if (hw->mac.type < em_mac_min) 4090 em_if_intr_disable(sc->ctx); 4091 4092 for (int i = 0; i < EM_VFTA_SIZE; i++) 4093 if (sc->shadow_vfta[i] != 0) { 4094 /* XXXKB: incomplete VF support, we returned above */ 4095 if (sc->vf_ifp) 4096 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], 4097 true); 4098 else 4099 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4100 } 4101 4102 /* Re-enable interrupts for lem-class devices */ 4103 if (hw->mac.type < em_mac_min) 4104 em_if_intr_enable(sc->ctx); 4105 } 4106 4107 static void 4108 em_setup_vlan_hw_support(if_ctx_t ctx) 4109 { 4110 struct e1000_softc *sc = iflib_get_softc(ctx); 4111 struct e1000_hw *hw = &sc->hw; 4112 if_t ifp = iflib_get_ifp(ctx); 4113 u32 reg; 4114 4115 /* XXXKB: Return early if we are a VF until VF decap and filter 4116 * management is ready and tested. 4117 */ 4118 if (sc->vf_ifp) 4119 return; 4120 4121 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4122 !em_disable_crc_stripping) { 4123 reg = E1000_READ_REG(hw, E1000_CTRL); 4124 reg |= E1000_CTRL_VME; 4125 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4126 } else { 4127 reg = E1000_READ_REG(hw, E1000_CTRL); 4128 reg &= ~E1000_CTRL_VME; 4129 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4130 } 4131 4132 /* If we aren't doing HW filtering, we're done */ 4133 if (!em_if_vlan_filter_capable(ctx)) { 4134 em_if_vlan_filter_disable(sc); 4135 return; 4136 } 4137 4138 /* 4139 * A soft reset zero's out the VFTA, so 4140 * we need to repopulate it now. 4141 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4142 * traffic through. This will write the entire table. 4143 */ 4144 em_if_vlan_register(ctx, 0); 4145 4146 /* Enable the Filter Table */ 4147 em_if_vlan_filter_enable(sc); 4148 } 4149 4150 static void 4151 em_if_intr_enable(if_ctx_t ctx) 4152 { 4153 struct e1000_softc *sc = iflib_get_softc(ctx); 4154 struct e1000_hw *hw = &sc->hw; 4155 u32 ims_mask = IMS_ENABLE_MASK; 4156 4157 if (sc->intr_type == IFLIB_INTR_MSIX) { 4158 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4159 ims_mask |= sc->ims; 4160 } 4161 4162 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4163 E1000_WRITE_FLUSH(hw); 4164 } 4165 4166 static void 4167 em_if_intr_disable(if_ctx_t ctx) 4168 { 4169 struct e1000_softc *sc = iflib_get_softc(ctx); 4170 struct e1000_hw *hw = &sc->hw; 4171 4172 if (sc->intr_type == IFLIB_INTR_MSIX) 4173 E1000_WRITE_REG(hw, EM_EIAC, 0); 4174 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4175 E1000_WRITE_FLUSH(hw); 4176 } 4177 4178 static void 4179 igb_if_intr_enable(if_ctx_t ctx) 4180 { 4181 struct e1000_softc *sc = iflib_get_softc(ctx); 4182 struct e1000_hw *hw = &sc->hw; 4183 u32 mask; 4184 4185 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4186 mask = (sc->que_mask | sc->link_mask); 4187 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4188 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4189 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4190 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4191 } else 4192 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4193 E1000_WRITE_FLUSH(hw); 4194 } 4195 4196 static void 4197 igb_if_intr_disable(if_ctx_t ctx) 4198 { 4199 struct e1000_softc *sc = iflib_get_softc(ctx); 4200 struct e1000_hw *hw = &sc->hw; 4201 4202 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4203 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4204 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4205 } 4206 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4207 E1000_WRITE_FLUSH(hw); 4208 } 4209 4210 /* 4211 * Bit of a misnomer, what this really means is 4212 * to enable OS management of the system... aka 4213 * to disable special hardware management features 4214 */ 4215 static void 4216 em_init_manageability(struct e1000_softc *sc) 4217 { 4218 /* A shared code workaround */ 4219 #define E1000_82542_MANC2H E1000_MANC2H 4220 if (sc->has_manage) { 4221 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4222 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4223 4224 /* disable hardware interception of ARP */ 4225 manc &= ~(E1000_MANC_ARP_EN); 4226 4227 /* enable receiving management packets to the host */ 4228 manc |= E1000_MANC_EN_MNG2HOST; 4229 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4230 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4231 manc2h |= E1000_MNG2HOST_PORT_623; 4232 manc2h |= E1000_MNG2HOST_PORT_664; 4233 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4234 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4235 } 4236 } 4237 4238 /* 4239 * Give control back to hardware management 4240 * controller if there is one. 4241 */ 4242 static void 4243 em_release_manageability(struct e1000_softc *sc) 4244 { 4245 if (sc->has_manage) { 4246 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4247 4248 /* re-enable hardware interception of ARP */ 4249 manc |= E1000_MANC_ARP_EN; 4250 manc &= ~E1000_MANC_EN_MNG2HOST; 4251 4252 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4253 } 4254 } 4255 4256 /* 4257 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4258 * For ASF and Pass Through versions of f/w this means 4259 * that the driver is loaded. For AMT version type f/w 4260 * this means that the network i/f is open. 4261 */ 4262 static void 4263 em_get_hw_control(struct e1000_softc *sc) 4264 { 4265 u32 ctrl_ext, swsm; 4266 4267 if (sc->vf_ifp) 4268 return; 4269 4270 if (sc->hw.mac.type == e1000_82573) { 4271 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4272 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4273 swsm | E1000_SWSM_DRV_LOAD); 4274 return; 4275 } 4276 /* else */ 4277 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4278 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4279 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4280 } 4281 4282 /* 4283 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4284 * For ASF and Pass Through versions of f/w this means that 4285 * the driver is no longer loaded. For AMT versions of the 4286 * f/w this means that the network i/f is closed. 4287 */ 4288 static void 4289 em_release_hw_control(struct e1000_softc *sc) 4290 { 4291 u32 ctrl_ext, swsm; 4292 4293 if (!sc->has_manage) 4294 return; 4295 4296 if (sc->hw.mac.type == e1000_82573) { 4297 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4298 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4299 swsm & ~E1000_SWSM_DRV_LOAD); 4300 return; 4301 } 4302 /* else */ 4303 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4304 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4305 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4306 return; 4307 } 4308 4309 static int 4310 em_is_valid_ether_addr(u8 *addr) 4311 { 4312 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4313 4314 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4315 return (false); 4316 } 4317 4318 return (true); 4319 } 4320 4321 static bool 4322 em_automask_tso(if_ctx_t ctx) 4323 { 4324 struct e1000_softc *sc = iflib_get_softc(ctx); 4325 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4326 if_t ifp = iflib_get_ifp(ctx); 4327 4328 if (!em_unsupported_tso && sc->link_speed && 4329 sc->link_speed != SPEED_1000 && 4330 scctx->isc_capenable & IFCAP_TSO) { 4331 device_printf(sc->dev, 4332 "Disabling TSO for 10/100 Ethernet.\n"); 4333 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4334 scctx->isc_capenable &= ~IFCAP_TSO; 4335 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4336 /* iflib_init_locked handles ifnet hwassistbits */ 4337 iflib_request_reset(ctx); 4338 return true; 4339 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4340 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4341 scctx->isc_capenable |= sc->tso_automasked; 4342 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4343 sc->tso_automasked = 0; 4344 /* iflib_init_locked handles ifnet hwassistbits */ 4345 iflib_request_reset(ctx); 4346 return true; 4347 } 4348 4349 return false; 4350 } 4351 4352 /* 4353 ** Parse the interface capabilities with regard 4354 ** to both system management and wake-on-lan for 4355 ** later use. 4356 */ 4357 static void 4358 em_get_wakeup(if_ctx_t ctx) 4359 { 4360 struct e1000_softc *sc = iflib_get_softc(ctx); 4361 device_t dev = iflib_get_dev(ctx); 4362 u16 eeprom_data = 0, device_id, apme_mask; 4363 4364 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4365 apme_mask = EM_EEPROM_APME; 4366 4367 switch (sc->hw.mac.type) { 4368 case e1000_82542: 4369 case e1000_82543: 4370 break; 4371 case e1000_82544: 4372 e1000_read_nvm(&sc->hw, 4373 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4374 apme_mask = EM_82544_APME; 4375 break; 4376 case e1000_82546: 4377 case e1000_82546_rev_3: 4378 if (sc->hw.bus.func == 1) { 4379 e1000_read_nvm(&sc->hw, 4380 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4381 break; 4382 } else 4383 e1000_read_nvm(&sc->hw, 4384 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4385 break; 4386 case e1000_82573: 4387 case e1000_82583: 4388 sc->has_amt = true; 4389 /* FALLTHROUGH */ 4390 case e1000_82571: 4391 case e1000_82572: 4392 case e1000_80003es2lan: 4393 if (sc->hw.bus.func == 1) { 4394 e1000_read_nvm(&sc->hw, 4395 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4396 break; 4397 } else 4398 e1000_read_nvm(&sc->hw, 4399 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4400 break; 4401 case e1000_ich8lan: 4402 case e1000_ich9lan: 4403 case e1000_ich10lan: 4404 case e1000_pchlan: 4405 case e1000_pch2lan: 4406 case e1000_pch_lpt: 4407 case e1000_pch_spt: 4408 case e1000_82575: /* listing all igb devices */ 4409 case e1000_82576: 4410 case e1000_82580: 4411 case e1000_i350: 4412 case e1000_i354: 4413 case e1000_i210: 4414 case e1000_i211: 4415 case e1000_vfadapt: 4416 case e1000_vfadapt_i350: 4417 apme_mask = E1000_WUC_APME; 4418 sc->has_amt = true; 4419 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4420 break; 4421 default: 4422 e1000_read_nvm(&sc->hw, 4423 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4424 break; 4425 } 4426 if (eeprom_data & apme_mask) 4427 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4428 /* 4429 * We have the eeprom settings, now apply the special cases 4430 * where the eeprom may be wrong or the board won't support 4431 * wake on lan on a particular port 4432 */ 4433 device_id = pci_get_device(dev); 4434 switch (device_id) { 4435 case E1000_DEV_ID_82546GB_PCIE: 4436 sc->wol = 0; 4437 break; 4438 case E1000_DEV_ID_82546EB_FIBER: 4439 case E1000_DEV_ID_82546GB_FIBER: 4440 /* Wake events only supported on port A for dual fiber 4441 * regardless of eeprom setting */ 4442 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4443 E1000_STATUS_FUNC_1) 4444 sc->wol = 0; 4445 break; 4446 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4447 /* if quad port adapter, disable WoL on all but port A */ 4448 if (global_quad_port_a != 0) 4449 sc->wol = 0; 4450 /* Reset for multiple quad port adapters */ 4451 if (++global_quad_port_a == 4) 4452 global_quad_port_a = 0; 4453 break; 4454 case E1000_DEV_ID_82571EB_FIBER: 4455 /* Wake events only supported on port A for dual fiber 4456 * regardless of eeprom setting */ 4457 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4458 E1000_STATUS_FUNC_1) 4459 sc->wol = 0; 4460 break; 4461 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4462 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4463 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4464 /* if quad port adapter, disable WoL on all but port A */ 4465 if (global_quad_port_a != 0) 4466 sc->wol = 0; 4467 /* Reset for multiple quad port adapters */ 4468 if (++global_quad_port_a == 4) 4469 global_quad_port_a = 0; 4470 break; 4471 } 4472 return; 4473 } 4474 4475 4476 /* 4477 * Enable PCI Wake On Lan capability 4478 */ 4479 static void 4480 em_enable_wakeup(if_ctx_t ctx) 4481 { 4482 struct e1000_softc *sc = iflib_get_softc(ctx); 4483 device_t dev = iflib_get_dev(ctx); 4484 if_t ifp = iflib_get_ifp(ctx); 4485 int error = 0; 4486 u32 ctrl, ctrl_ext, rctl; 4487 4488 if (!pci_has_pm(dev)) 4489 return; 4490 4491 /* 4492 * Determine type of Wakeup: note that wol 4493 * is set with all bits on by default. 4494 */ 4495 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4496 sc->wol &= ~E1000_WUFC_MAG; 4497 4498 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4499 sc->wol &= ~E1000_WUFC_EX; 4500 4501 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4502 sc->wol &= ~E1000_WUFC_MC; 4503 else { 4504 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4505 rctl |= E1000_RCTL_MPE; 4506 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4507 } 4508 4509 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4510 goto pme; 4511 4512 /* Advertise the wakeup capability */ 4513 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4514 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4515 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4516 4517 /* Keep the laser running on Fiber adapters */ 4518 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4519 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4520 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4521 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4522 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4523 } 4524 4525 if ((sc->hw.mac.type == e1000_ich8lan) || 4526 (sc->hw.mac.type == e1000_pchlan) || 4527 (sc->hw.mac.type == e1000_ich9lan) || 4528 (sc->hw.mac.type == e1000_ich10lan)) 4529 e1000_suspend_workarounds_ich8lan(&sc->hw); 4530 4531 if ( sc->hw.mac.type >= e1000_pchlan) { 4532 error = em_enable_phy_wakeup(sc); 4533 if (error) 4534 goto pme; 4535 } else { 4536 /* Enable wakeup by the MAC */ 4537 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4538 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4539 } 4540 4541 if (sc->hw.phy.type == e1000_phy_igp_3) 4542 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4543 4544 pme: 4545 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4546 pci_enable_pme(dev); 4547 4548 return; 4549 } 4550 4551 /* 4552 * WOL in the newer chipset interfaces (pchlan) 4553 * require thing to be copied into the phy 4554 */ 4555 static int 4556 em_enable_phy_wakeup(struct e1000_softc *sc) 4557 { 4558 struct e1000_hw *hw = &sc->hw; 4559 u32 mreg, ret = 0; 4560 u16 preg; 4561 4562 /* copy MAC RARs to PHY RARs */ 4563 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4564 4565 /* copy MAC MTA to PHY MTA */ 4566 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4567 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4568 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4569 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4570 (u16)((mreg >> 16) & 0xFFFF)); 4571 } 4572 4573 /* configure PHY Rx Control register */ 4574 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4575 mreg = E1000_READ_REG(hw, E1000_RCTL); 4576 if (mreg & E1000_RCTL_UPE) 4577 preg |= BM_RCTL_UPE; 4578 if (mreg & E1000_RCTL_MPE) 4579 preg |= BM_RCTL_MPE; 4580 preg &= ~(BM_RCTL_MO_MASK); 4581 if (mreg & E1000_RCTL_MO_3) 4582 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4583 << BM_RCTL_MO_SHIFT); 4584 if (mreg & E1000_RCTL_BAM) 4585 preg |= BM_RCTL_BAM; 4586 if (mreg & E1000_RCTL_PMCF) 4587 preg |= BM_RCTL_PMCF; 4588 mreg = E1000_READ_REG(hw, E1000_CTRL); 4589 if (mreg & E1000_CTRL_RFCE) 4590 preg |= BM_RCTL_RFCE; 4591 e1000_write_phy_reg(hw, BM_RCTL, preg); 4592 4593 /* enable PHY wakeup in MAC register */ 4594 E1000_WRITE_REG(hw, E1000_WUC, 4595 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4596 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4597 4598 /* configure and enable PHY wakeup in PHY registers */ 4599 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4600 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4601 4602 /* activate PHY wakeup */ 4603 ret = hw->phy.ops.acquire(hw); 4604 if (ret) { 4605 printf("Could not acquire PHY\n"); 4606 return ret; 4607 } 4608 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4609 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4610 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4611 if (ret) { 4612 printf("Could not read PHY page 769\n"); 4613 goto out; 4614 } 4615 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4616 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4617 if (ret) 4618 printf("Could not set PHY Host Wakeup bit\n"); 4619 out: 4620 hw->phy.ops.release(hw); 4621 4622 return ret; 4623 } 4624 4625 static void 4626 em_if_led_func(if_ctx_t ctx, int onoff) 4627 { 4628 struct e1000_softc *sc = iflib_get_softc(ctx); 4629 4630 if (onoff) { 4631 e1000_setup_led(&sc->hw); 4632 e1000_led_on(&sc->hw); 4633 } else { 4634 e1000_led_off(&sc->hw); 4635 e1000_cleanup_led(&sc->hw); 4636 } 4637 } 4638 4639 /* 4640 * Disable the L0S and L1 LINK states 4641 */ 4642 static void 4643 em_disable_aspm(struct e1000_softc *sc) 4644 { 4645 int base, reg; 4646 u16 link_cap,link_ctrl; 4647 device_t dev = sc->dev; 4648 4649 switch (sc->hw.mac.type) { 4650 case e1000_82573: 4651 case e1000_82574: 4652 case e1000_82583: 4653 break; 4654 default: 4655 return; 4656 } 4657 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4658 return; 4659 reg = base + PCIER_LINK_CAP; 4660 link_cap = pci_read_config(dev, reg, 2); 4661 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4662 return; 4663 reg = base + PCIER_LINK_CTL; 4664 link_ctrl = pci_read_config(dev, reg, 2); 4665 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4666 pci_write_config(dev, reg, link_ctrl, 2); 4667 return; 4668 } 4669 4670 /********************************************************************** 4671 * 4672 * Update the board statistics counters. 4673 * 4674 **********************************************************************/ 4675 static void 4676 em_update_stats_counters(struct e1000_softc *sc) 4677 { 4678 struct e1000_hw_stats *stats; 4679 u64 prev_xoffrxc; 4680 4681 if (sc->vf_ifp) { 4682 em_update_vf_stats_counters(sc); 4683 return; 4684 } 4685 4686 stats = &sc->ustats.stats; 4687 prev_xoffrxc = stats->xoffrxc; 4688 4689 if(sc->hw.phy.media_type == e1000_media_type_copper || 4690 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4691 stats->symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4692 stats->sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4693 } 4694 stats->crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4695 stats->mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4696 stats->scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4697 stats->ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4698 4699 stats->mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4700 stats->latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4701 stats->colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4702 stats->dc += E1000_READ_REG(&sc->hw, E1000_DC); 4703 stats->rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4704 stats->xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4705 stats->xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4706 stats->xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4707 /* 4708 ** For watchdog management we need to know if we have been 4709 ** paused during the last interval, so capture that here. 4710 */ 4711 if (stats->xoffrxc != prev_xoffrxc) 4712 sc->shared->isc_pause_frames = 1; 4713 stats->xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4714 stats->fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4715 stats->prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4716 stats->prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4717 stats->prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4718 stats->prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4719 stats->prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4720 stats->prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4721 stats->gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4722 stats->bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4723 stats->mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4724 stats->gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4725 4726 /* For the 64-bit byte counters the low dword must be read first. */ 4727 /* Both registers clear on the read of the high dword */ 4728 4729 stats->gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4730 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4731 stats->gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4732 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4733 4734 stats->rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4735 stats->ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4736 stats->rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4737 stats->roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4738 stats->rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4739 4740 stats->mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4741 stats->mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4742 stats->mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4743 4744 stats->tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4745 stats->tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4746 4747 stats->tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4748 stats->tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4749 stats->ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4750 stats->ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4751 stats->ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4752 stats->ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4753 stats->ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4754 stats->ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4755 stats->mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4756 stats->bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4757 4758 /* Interrupt Counts */ 4759 4760 stats->iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4761 stats->icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4762 stats->icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4763 stats->ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4764 stats->ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4765 stats->ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4766 stats->ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4767 stats->icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4768 stats->icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4769 4770 if (sc->hw.mac.type >= e1000_82543) { 4771 stats->algnerrc += 4772 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4773 stats->rxerrc += 4774 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4775 stats->tncrs += 4776 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4777 stats->cexterr += 4778 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4779 stats->tsctc += 4780 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4781 stats->tsctfc += 4782 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4783 } 4784 } 4785 4786 static void 4787 em_update_vf_stats_counters(struct e1000_softc *sc) 4788 { 4789 struct e1000_vf_stats *stats; 4790 4791 if (sc->link_speed == 0) 4792 return; 4793 4794 stats = &sc->ustats.vf_stats; 4795 4796 UPDATE_VF_REG(E1000_VFGPRC, 4797 stats->last_gprc, stats->gprc); 4798 UPDATE_VF_REG(E1000_VFGORC, 4799 stats->last_gorc, stats->gorc); 4800 UPDATE_VF_REG(E1000_VFGPTC, 4801 stats->last_gptc, stats->gptc); 4802 UPDATE_VF_REG(E1000_VFGOTC, 4803 stats->last_gotc, stats->gotc); 4804 UPDATE_VF_REG(E1000_VFMPRC, 4805 stats->last_mprc, stats->mprc); 4806 } 4807 4808 static uint64_t 4809 em_if_get_vf_counter(if_ctx_t ctx, ift_counter cnt) 4810 { 4811 struct e1000_softc *sc = iflib_get_softc(ctx); 4812 if_t ifp = iflib_get_ifp(ctx); 4813 4814 switch (cnt) { 4815 case IFCOUNTER_IERRORS: 4816 return sc->dropped_pkts; 4817 case IFCOUNTER_OERRORS: 4818 return (if_get_counter_default(ifp, cnt) + 4819 sc->watchdog_events); 4820 default: 4821 return (if_get_counter_default(ifp, cnt)); 4822 } 4823 } 4824 4825 static uint64_t 4826 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4827 { 4828 struct e1000_softc *sc = iflib_get_softc(ctx); 4829 struct e1000_hw_stats *stats; 4830 if_t ifp = iflib_get_ifp(ctx); 4831 4832 if (sc->vf_ifp) 4833 return (em_if_get_vf_counter(ctx, cnt)); 4834 4835 stats = &sc->ustats.stats; 4836 4837 switch (cnt) { 4838 case IFCOUNTER_COLLISIONS: 4839 return (stats->colc); 4840 case IFCOUNTER_IERRORS: 4841 return (sc->dropped_pkts + stats->rxerrc + 4842 stats->crcerrs + stats->algnerrc + 4843 stats->ruc + stats->roc + 4844 stats->mpc + stats->cexterr); 4845 case IFCOUNTER_OERRORS: 4846 return (if_get_counter_default(ifp, cnt) + 4847 stats->ecol + stats->latecol + sc->watchdog_events); 4848 default: 4849 return (if_get_counter_default(ifp, cnt)); 4850 } 4851 } 4852 4853 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4854 * @ctx: iflib context 4855 * @event: event code to check 4856 * 4857 * Defaults to returning false for unknown events. 4858 * 4859 * @returns true if iflib needs to reinit the interface 4860 */ 4861 static bool 4862 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4863 { 4864 switch (event) { 4865 case IFLIB_RESTART_VLAN_CONFIG: 4866 default: 4867 return (false); 4868 } 4869 } 4870 4871 /* Export a single 32-bit register via a read-only sysctl. */ 4872 static int 4873 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4874 { 4875 struct e1000_softc *sc; 4876 u_int val; 4877 4878 sc = oidp->oid_arg1; 4879 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4880 return (sysctl_handle_int(oidp, &val, 0, req)); 4881 } 4882 4883 /* Per queue holdoff interrupt rate handler */ 4884 static int 4885 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4886 { 4887 struct em_rx_queue *rque; 4888 struct em_tx_queue *tque; 4889 struct e1000_hw *hw; 4890 int error; 4891 u32 reg, usec, rate; 4892 4893 bool tx = oidp->oid_arg2; 4894 4895 if (tx) { 4896 tque = oidp->oid_arg1; 4897 hw = &tque->sc->hw; 4898 if (hw->mac.type >= igb_mac_min) 4899 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4900 else if (hw->mac.type == e1000_82574 && tque->msix) 4901 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4902 else 4903 reg = E1000_READ_REG(hw, E1000_ITR); 4904 } else { 4905 rque = oidp->oid_arg1; 4906 hw = &rque->sc->hw; 4907 if (hw->mac.type >= igb_mac_min) 4908 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4909 else if (hw->mac.type == e1000_82574 && rque->msix) 4910 reg = E1000_READ_REG(hw, 4911 E1000_EITR_82574(rque->msix)); 4912 else 4913 reg = E1000_READ_REG(hw, E1000_ITR); 4914 } 4915 4916 if (hw->mac.type < igb_mac_min) { 4917 if (reg > 0) 4918 rate = EM_INTS_TO_ITR(reg); 4919 else 4920 rate = 0; 4921 } else { 4922 usec = (reg & IGB_QVECTOR_MASK); 4923 if (usec > 0) 4924 rate = IGB_INTS_TO_EITR(usec); 4925 else 4926 rate = 0; 4927 } 4928 4929 error = sysctl_handle_int(oidp, &rate, 0, req); 4930 if (error || !req->newptr) 4931 return error; 4932 return 0; 4933 } 4934 4935 /* 4936 * Add sysctl variables, one per statistic, to the system. 4937 */ 4938 static void 4939 em_add_hw_stats(struct e1000_softc *sc) 4940 { 4941 device_t dev = iflib_get_dev(sc->ctx); 4942 struct em_tx_queue *tx_que = sc->tx_queues; 4943 struct em_rx_queue *rx_que = sc->rx_queues; 4944 4945 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4946 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4947 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4948 struct e1000_hw_stats *stats; 4949 4950 struct sysctl_oid *stat_node, *queue_node, *int_node; 4951 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4952 4953 #define QUEUE_NAME_LEN 32 4954 char namebuf[QUEUE_NAME_LEN]; 4955 4956 /* Driver Statistics */ 4957 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4958 CTLFLAG_RD, &sc->dropped_pkts, 4959 "Driver dropped packets"); 4960 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4961 CTLFLAG_RD, &sc->link_irq, 4962 "Link MSI-X IRQ Handled"); 4963 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4964 CTLFLAG_RD, &sc->rx_overruns, 4965 "RX overruns"); 4966 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4967 CTLFLAG_RD, &sc->watchdog_events, 4968 "Watchdog timeouts"); 4969 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4970 CTLTYPE_UINT | CTLFLAG_RD, 4971 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4972 "Device Control Register"); 4973 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4974 CTLTYPE_UINT | CTLFLAG_RD, 4975 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4976 "Receiver Control Register"); 4977 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4978 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4979 "Flow Control High Watermark"); 4980 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4981 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4982 "Flow Control Low Watermark"); 4983 4984 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4985 struct tx_ring *txr = &tx_que->txr; 4986 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4987 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4988 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4989 queue_list = SYSCTL_CHILDREN(queue_node); 4990 4991 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4992 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4993 true, em_sysctl_interrupt_rate_handler, 4994 "IU", "Interrupt Rate"); 4995 4996 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4997 CTLTYPE_UINT | CTLFLAG_RD, sc, 4998 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4999 "Transmit Descriptor Head"); 5000 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 5001 CTLTYPE_UINT | CTLFLAG_RD, sc, 5002 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 5003 "Transmit Descriptor Tail"); 5004 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 5005 CTLFLAG_RD, &txr->tx_irq, 5006 "Queue MSI-X Transmit Interrupts"); 5007 } 5008 5009 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 5010 struct rx_ring *rxr = &rx_que->rxr; 5011 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 5012 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 5013 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 5014 queue_list = SYSCTL_CHILDREN(queue_node); 5015 5016 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 5017 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 5018 false, em_sysctl_interrupt_rate_handler, 5019 "IU", "Interrupt Rate"); 5020 5021 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 5022 CTLTYPE_UINT | CTLFLAG_RD, sc, 5023 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 5024 "Receive Descriptor Head"); 5025 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 5026 CTLTYPE_UINT | CTLFLAG_RD, sc, 5027 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 5028 "Receive Descriptor Tail"); 5029 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 5030 CTLFLAG_RD, &rxr->rx_irq, 5031 "Queue MSI-X Receive Interrupts"); 5032 } 5033 5034 /* MAC stats get their own sub node */ 5035 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 5036 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 5037 stat_list = SYSCTL_CHILDREN(stat_node); 5038 5039 /* 5040 ** VF adapter has a very limited set of stats 5041 ** since its not managing the metal, so to speak. 5042 */ 5043 if (sc->vf_ifp) { 5044 struct e1000_vf_stats *vfstats = &sc->ustats.vf_stats; 5045 5046 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5047 CTLFLAG_RD, &vfstats->gprc, 5048 "Good Packets Received"); 5049 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5050 CTLFLAG_RD, &vfstats->gptc, 5051 "Good Packets Transmitted"); 5052 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5053 CTLFLAG_RD, &vfstats->gorc, 5054 "Good Octets Received"); 5055 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5056 CTLFLAG_RD, &vfstats->gotc, 5057 "Good Octets Transmitted"); 5058 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5059 CTLFLAG_RD, &vfstats->mprc, 5060 "Multicast Packets Received"); 5061 return; 5062 } 5063 5064 stats = &sc->ustats.stats; 5065 5066 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 5067 CTLFLAG_RD, &stats->ecol, 5068 "Excessive collisions"); 5069 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 5070 CTLFLAG_RD, &stats->scc, 5071 "Single collisions"); 5072 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 5073 CTLFLAG_RD, &stats->mcc, 5074 "Multiple collisions"); 5075 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 5076 CTLFLAG_RD, &stats->latecol, 5077 "Late collisions"); 5078 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 5079 CTLFLAG_RD, &stats->colc, 5080 "Collision Count"); 5081 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 5082 CTLFLAG_RD, &stats->symerrs, 5083 "Symbol Errors"); 5084 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 5085 CTLFLAG_RD, &stats->sec, 5086 "Sequence Errors"); 5087 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5088 CTLFLAG_RD, &stats->dc, 5089 "Defer Count"); 5090 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5091 CTLFLAG_RD, &stats->mpc, 5092 "Missed Packets"); 5093 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5094 CTLFLAG_RD, &stats->rlec, 5095 "Receive Length Errors"); 5096 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5097 CTLFLAG_RD, &stats->rnbc, 5098 "Receive No Buffers"); 5099 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5100 CTLFLAG_RD, &stats->ruc, 5101 "Receive Undersize"); 5102 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5103 CTLFLAG_RD, &stats->rfc, 5104 "Fragmented Packets Received "); 5105 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5106 CTLFLAG_RD, &stats->roc, 5107 "Oversized Packets Received"); 5108 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5109 CTLFLAG_RD, &stats->rjc, 5110 "Recevied Jabber"); 5111 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5112 CTLFLAG_RD, &stats->rxerrc, 5113 "Receive Errors"); 5114 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5115 CTLFLAG_RD, &stats->crcerrs, 5116 "CRC errors"); 5117 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5118 CTLFLAG_RD, &stats->algnerrc, 5119 "Alignment Errors"); 5120 /* On 82575 these are collision counts */ 5121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5122 CTLFLAG_RD, &stats->cexterr, 5123 "Collision/Carrier extension errors"); 5124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5125 CTLFLAG_RD, &stats->xonrxc, 5126 "XON Received"); 5127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5128 CTLFLAG_RD, &stats->xontxc, 5129 "XON Transmitted"); 5130 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5131 CTLFLAG_RD, &stats->xoffrxc, 5132 "XOFF Received"); 5133 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5134 CTLFLAG_RD, &stats->xofftxc, 5135 "XOFF Transmitted"); 5136 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5137 CTLFLAG_RD, &stats->fcruc, 5138 "Unsupported Flow Control Received"); 5139 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5140 CTLFLAG_RD, &stats->mgprc, 5141 "Management Packets Received"); 5142 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5143 CTLFLAG_RD, &stats->mgpdc, 5144 "Management Packets Dropped"); 5145 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5146 CTLFLAG_RD, &stats->mgptc, 5147 "Management Packets Transmitted"); 5148 5149 /* Packet Reception Stats */ 5150 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5151 CTLFLAG_RD, &stats->tpr, 5152 "Total Packets Received "); 5153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5154 CTLFLAG_RD, &stats->gprc, 5155 "Good Packets Received"); 5156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5157 CTLFLAG_RD, &stats->bprc, 5158 "Broadcast Packets Received"); 5159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5160 CTLFLAG_RD, &stats->mprc, 5161 "Multicast Packets Received"); 5162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5163 CTLFLAG_RD, &stats->prc64, 5164 "64 byte frames received "); 5165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5166 CTLFLAG_RD, &stats->prc127, 5167 "65-127 byte frames received"); 5168 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5169 CTLFLAG_RD, &stats->prc255, 5170 "128-255 byte frames received"); 5171 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5172 CTLFLAG_RD, &stats->prc511, 5173 "256-511 byte frames received"); 5174 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5175 CTLFLAG_RD, &stats->prc1023, 5176 "512-1023 byte frames received"); 5177 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5178 CTLFLAG_RD, &stats->prc1522, 5179 "1023-1522 byte frames received"); 5180 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5181 CTLFLAG_RD, &stats->gorc, 5182 "Good Octets Received"); 5183 5184 /* Packet Transmission Stats */ 5185 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5186 CTLFLAG_RD, &stats->gotc, 5187 "Good Octets Transmitted"); 5188 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5189 CTLFLAG_RD, &stats->tpt, 5190 "Total Packets Transmitted"); 5191 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5192 CTLFLAG_RD, &stats->gptc, 5193 "Good Packets Transmitted"); 5194 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5195 CTLFLAG_RD, &stats->bptc, 5196 "Broadcast Packets Transmitted"); 5197 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5198 CTLFLAG_RD, &stats->mptc, 5199 "Multicast Packets Transmitted"); 5200 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5201 CTLFLAG_RD, &stats->ptc64, 5202 "64 byte frames transmitted "); 5203 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5204 CTLFLAG_RD, &stats->ptc127, 5205 "65-127 byte frames transmitted"); 5206 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5207 CTLFLAG_RD, &stats->ptc255, 5208 "128-255 byte frames transmitted"); 5209 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5210 CTLFLAG_RD, &stats->ptc511, 5211 "256-511 byte frames transmitted"); 5212 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5213 CTLFLAG_RD, &stats->ptc1023, 5214 "512-1023 byte frames transmitted"); 5215 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5216 CTLFLAG_RD, &stats->ptc1522, 5217 "1024-1522 byte frames transmitted"); 5218 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5219 CTLFLAG_RD, &stats->tsctc, 5220 "TSO Contexts Transmitted"); 5221 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5222 CTLFLAG_RD, &stats->tsctfc, 5223 "TSO Contexts Failed"); 5224 5225 /* Interrupt Stats */ 5226 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5227 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5228 int_list = SYSCTL_CHILDREN(int_node); 5229 5230 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5231 CTLFLAG_RD, &stats->iac, 5232 "Interrupt Assertion Count"); 5233 5234 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5235 CTLFLAG_RD, &stats->icrxptc, 5236 "Interrupt Cause Rx Pkt Timer Expire Count"); 5237 5238 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5239 CTLFLAG_RD, &stats->icrxatc, 5240 "Interrupt Cause Rx Abs Timer Expire Count"); 5241 5242 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5243 CTLFLAG_RD, &stats->ictxptc, 5244 "Interrupt Cause Tx Pkt Timer Expire Count"); 5245 5246 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5247 CTLFLAG_RD, &stats->ictxatc, 5248 "Interrupt Cause Tx Abs Timer Expire Count"); 5249 5250 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5251 CTLFLAG_RD, &stats->ictxqec, 5252 "Interrupt Cause Tx Queue Empty Count"); 5253 5254 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5255 CTLFLAG_RD, &stats->ictxqmtc, 5256 "Interrupt Cause Tx Queue Min Thresh Count"); 5257 5258 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5259 CTLFLAG_RD, &stats->icrxdmtc, 5260 "Interrupt Cause Rx Desc Min Thresh Count"); 5261 5262 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5263 CTLFLAG_RD, &stats->icrxoc, 5264 "Interrupt Cause Receiver Overrun Count"); 5265 } 5266 5267 static void 5268 em_fw_version_locked(if_ctx_t ctx) 5269 { 5270 struct e1000_softc *sc = iflib_get_softc(ctx); 5271 struct e1000_hw *hw = &sc->hw; 5272 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5273 uint16_t eep = 0; 5274 5275 /* 5276 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5277 * the NVM locking model, so we do it in em_if_attach_pre() and store 5278 * the info in the softc 5279 */ 5280 ASSERT_CTX_LOCK_HELD(hw); 5281 5282 *fw_ver = (struct e1000_fw_version){0}; 5283 5284 if (hw->mac.type >= igb_mac_min) { 5285 /* 5286 * Use the Shared Code for igb(4) 5287 */ 5288 e1000_get_fw_version(hw, fw_ver); 5289 } else { 5290 /* 5291 * Otherwise, EEPROM version should be present on (almost?) 5292 * all devices here 5293 */ 5294 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5295 INIT_DEBUGOUT("can't get EEPROM version"); 5296 return; 5297 } 5298 5299 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5300 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5301 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5302 } 5303 } 5304 5305 static void 5306 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5307 { 5308 const char *space = ""; 5309 5310 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5311 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5312 fw_ver->eep_minor, fw_ver->eep_build); 5313 space = " "; 5314 } 5315 5316 if (fw_ver->invm_major || fw_ver->invm_minor || 5317 fw_ver->invm_img_type) { 5318 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5319 space, fw_ver->invm_major, fw_ver->invm_minor, 5320 fw_ver->invm_img_type); 5321 space = " "; 5322 } 5323 5324 if (fw_ver->or_valid) { 5325 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5326 space, fw_ver->or_major, fw_ver->or_build, 5327 fw_ver->or_patch); 5328 space = " "; 5329 } 5330 5331 if (fw_ver->etrack_id) 5332 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5333 } 5334 5335 static void 5336 em_print_fw_version(struct e1000_softc *sc ) 5337 { 5338 device_t dev = sc->dev; 5339 struct sbuf *buf; 5340 int error = 0; 5341 5342 buf = sbuf_new_auto(); 5343 if (!buf) { 5344 device_printf(dev, "Could not allocate sbuf for output.\n"); 5345 return; 5346 } 5347 5348 em_sbuf_fw_version(&sc->fw_ver, buf); 5349 5350 error = sbuf_finish(buf); 5351 if (error) 5352 device_printf(dev, "Error finishing sbuf: %d\n", error); 5353 else if (sbuf_len(buf)) 5354 device_printf(dev, "%s\n", sbuf_data(buf)); 5355 5356 sbuf_delete(buf); 5357 } 5358 5359 static int 5360 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5361 { 5362 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5363 device_t dev = sc->dev; 5364 struct sbuf *buf; 5365 int error = 0; 5366 5367 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5368 if (!buf) { 5369 device_printf(dev, "Could not allocate sbuf for output.\n"); 5370 return (ENOMEM); 5371 } 5372 5373 em_sbuf_fw_version(&sc->fw_ver, buf); 5374 5375 error = sbuf_finish(buf); 5376 if (error) 5377 device_printf(dev, "Error finishing sbuf: %d\n", error); 5378 5379 sbuf_delete(buf); 5380 5381 return (0); 5382 } 5383 5384 /********************************************************************** 5385 * 5386 * This routine provides a way to dump out the adapter eeprom, 5387 * often a useful debug/service tool. This only dumps the first 5388 * 32 words, stuff that matters is in that extent. 5389 * 5390 **********************************************************************/ 5391 static int 5392 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5393 { 5394 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5395 int error; 5396 int result; 5397 5398 result = -1; 5399 error = sysctl_handle_int(oidp, &result, 0, req); 5400 5401 if (error || !req->newptr) 5402 return (error); 5403 5404 /* 5405 * This value will cause a hex dump of the 5406 * first 32 16-bit words of the EEPROM to 5407 * the screen. 5408 */ 5409 if (result == 1) 5410 em_print_nvm_info(sc); 5411 5412 return (error); 5413 } 5414 5415 static void 5416 em_print_nvm_info(struct e1000_softc *sc) 5417 { 5418 struct e1000_hw *hw = &sc->hw; 5419 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5420 u16 eeprom_data; 5421 int i, j, row = 0; 5422 5423 /* Its a bit crude, but it gets the job done */ 5424 printf("\nInterface EEPROM Dump:\n"); 5425 printf("Offset\n0x0000 "); 5426 5427 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5428 sx_xlock(iflib_ctx_lock); 5429 ASSERT_CTX_LOCK_HELD(hw); 5430 for (i = 0, j = 0; i < 32; i++, j++) { 5431 if (j == 8) { /* Make the offset block */ 5432 j = 0; ++row; 5433 printf("\n0x00%x0 ",row); 5434 } 5435 e1000_read_nvm(hw, i, 1, &eeprom_data); 5436 printf("%04x ", eeprom_data); 5437 } 5438 sx_xunlock(iflib_ctx_lock); 5439 printf("\n"); 5440 } 5441 5442 static int 5443 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5444 { 5445 struct em_int_delay_info *info; 5446 struct e1000_softc *sc; 5447 u32 regval; 5448 int error, usecs, ticks; 5449 5450 info = (struct em_int_delay_info *) arg1; 5451 usecs = info->value; 5452 error = sysctl_handle_int(oidp, &usecs, 0, req); 5453 if (error != 0 || req->newptr == NULL) 5454 return (error); 5455 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5456 return (EINVAL); 5457 info->value = usecs; 5458 ticks = EM_USECS_TO_TICKS(usecs); 5459 5460 sc = info->sc; 5461 5462 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5463 regval = (regval & ~0xffff) | (ticks & 0xffff); 5464 /* Handle a few special cases. */ 5465 switch (info->offset) { 5466 case E1000_RDTR: 5467 break; 5468 case E1000_TIDV: 5469 if (ticks == 0) { 5470 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5471 /* Don't write 0 into the TIDV register. */ 5472 regval++; 5473 } else 5474 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5475 break; 5476 } 5477 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5478 return (0); 5479 } 5480 5481 static int 5482 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5483 { 5484 struct e1000_softc *sc; 5485 u32 reg, val, shift; 5486 int error, mask; 5487 5488 sc = oidp->oid_arg1; 5489 switch (oidp->oid_arg2) { 5490 case 0: 5491 reg = E1000_DTXTCPFLGL; 5492 shift = 0; 5493 break; 5494 case 1: 5495 reg = E1000_DTXTCPFLGL; 5496 shift = 16; 5497 break; 5498 case 2: 5499 reg = E1000_DTXTCPFLGH; 5500 shift = 0; 5501 break; 5502 default: 5503 return (EINVAL); 5504 break; 5505 } 5506 val = E1000_READ_REG(&sc->hw, reg); 5507 mask = (val >> shift) & 0xfff; 5508 error = sysctl_handle_int(oidp, &mask, 0, req); 5509 if (error != 0 || req->newptr == NULL) 5510 return (error); 5511 if (mask < 0 || mask > 0xfff) 5512 return (EINVAL); 5513 val = (val & ~(0xfff << shift)) | (mask << shift); 5514 E1000_WRITE_REG(&sc->hw, reg, val); 5515 return (0); 5516 } 5517 5518 static void 5519 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5520 const char *description, struct em_int_delay_info *info, int offset, 5521 int value) 5522 { 5523 info->sc = sc; 5524 info->offset = offset; 5525 info->value = value; 5526 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5527 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5528 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5529 info, 0, em_sysctl_int_delay, "I", description); 5530 } 5531 5532 /* 5533 * Set flow control using sysctl: 5534 * Flow control values: 5535 * 0 - off 5536 * 1 - rx pause 5537 * 2 - tx pause 5538 * 3 - full 5539 */ 5540 static int 5541 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5542 { 5543 int error; 5544 static int input = 3; /* default is full */ 5545 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5546 5547 error = sysctl_handle_int(oidp, &input, 0, req); 5548 5549 if ((error) || (req->newptr == NULL)) 5550 return (error); 5551 5552 if (input == sc->fc) /* no change? */ 5553 return (error); 5554 5555 switch (input) { 5556 case e1000_fc_rx_pause: 5557 case e1000_fc_tx_pause: 5558 case e1000_fc_full: 5559 case e1000_fc_none: 5560 sc->hw.fc.requested_mode = input; 5561 sc->fc = input; 5562 break; 5563 default: 5564 /* Do nothing */ 5565 return (error); 5566 } 5567 5568 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5569 e1000_force_mac_fc(&sc->hw); 5570 return (error); 5571 } 5572 5573 /* 5574 * Manage DMA Coalesce: 5575 * Control values: 5576 * 0/1 - off/on 5577 * Legal timer values are: 5578 * 250,500,1000-10000 in thousands 5579 */ 5580 static int 5581 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5582 { 5583 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5584 int error; 5585 5586 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5587 5588 if ((error) || (req->newptr == NULL)) 5589 return (error); 5590 5591 switch (sc->dmac) { 5592 case 0: 5593 /* Disabling */ 5594 break; 5595 case 1: /* Just enable and use default */ 5596 sc->dmac = 1000; 5597 break; 5598 case 250: 5599 case 500: 5600 case 1000: 5601 case 2000: 5602 case 3000: 5603 case 4000: 5604 case 5000: 5605 case 6000: 5606 case 7000: 5607 case 8000: 5608 case 9000: 5609 case 10000: 5610 /* Legal values - allow */ 5611 break; 5612 default: 5613 /* Do nothing, illegal value */ 5614 sc->dmac = 0; 5615 return (EINVAL); 5616 } 5617 /* Reinit the interface */ 5618 em_if_init(sc->ctx); 5619 return (error); 5620 } 5621 5622 /* 5623 * Manage Energy Efficient Ethernet: 5624 * Control values: 5625 * 0/1 - enabled/disabled 5626 */ 5627 static int 5628 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5629 { 5630 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5631 int error, value; 5632 5633 if (sc->hw.mac.type < igb_mac_min) 5634 value = sc->hw.dev_spec.ich8lan.eee_disable; 5635 else 5636 value = sc->hw.dev_spec._82575.eee_disable; 5637 error = sysctl_handle_int(oidp, &value, 0, req); 5638 if (error || req->newptr == NULL) 5639 return (error); 5640 if (sc->hw.mac.type < igb_mac_min) 5641 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5642 else 5643 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5644 em_if_init(sc->ctx); 5645 5646 return (0); 5647 } 5648 5649 static int 5650 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5651 { 5652 struct e1000_softc *sc; 5653 int error; 5654 int result; 5655 5656 result = -1; 5657 error = sysctl_handle_int(oidp, &result, 0, req); 5658 5659 if (error || !req->newptr) 5660 return (error); 5661 5662 if (result == 1) { 5663 sc = (struct e1000_softc *) arg1; 5664 em_print_debug_info(sc); 5665 } 5666 5667 return (error); 5668 } 5669 5670 static int 5671 em_get_rs(SYSCTL_HANDLER_ARGS) 5672 { 5673 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5674 int error; 5675 int result; 5676 5677 result = 0; 5678 error = sysctl_handle_int(oidp, &result, 0, req); 5679 5680 if (error || !req->newptr || result != 1) 5681 return (error); 5682 em_dump_rs(sc); 5683 5684 return (error); 5685 } 5686 5687 static void 5688 em_if_debug(if_ctx_t ctx) 5689 { 5690 em_dump_rs(iflib_get_softc(ctx)); 5691 } 5692 5693 /* 5694 * This routine is meant to be fluid, add whatever is 5695 * needed for debugging a problem. -jfv 5696 */ 5697 static void 5698 em_print_debug_info(struct e1000_softc *sc) 5699 { 5700 device_t dev = iflib_get_dev(sc->ctx); 5701 if_t ifp = iflib_get_ifp(sc->ctx); 5702 struct tx_ring *txr = &sc->tx_queues->txr; 5703 struct rx_ring *rxr = &sc->rx_queues->rxr; 5704 5705 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5706 printf("Interface is RUNNING "); 5707 else 5708 printf("Interface is NOT RUNNING\n"); 5709 5710 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5711 printf("and INACTIVE\n"); 5712 else 5713 printf("and ACTIVE\n"); 5714 5715 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5716 device_printf(dev, "TX Queue %d ------\n", i); 5717 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5718 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5719 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5720 5721 } 5722 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5723 device_printf(dev, "RX Queue %d ------\n", j); 5724 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5725 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5726 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5727 } 5728 } 5729 5730 /* 5731 * 82574 only: 5732 * Write a new value to the EEPROM increasing the number of MSI-X 5733 * vectors from 3 to 5, for proper multiqueue support. 5734 */ 5735 static void 5736 em_enable_vectors_82574(if_ctx_t ctx) 5737 { 5738 struct e1000_softc *sc = iflib_get_softc(ctx); 5739 struct e1000_hw *hw = &sc->hw; 5740 device_t dev = iflib_get_dev(ctx); 5741 u16 edata; 5742 5743 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5744 if (bootverbose) 5745 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5746 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5747 device_printf(dev, "Writing to eeprom: increasing " 5748 "reported MSI-X vectors from 3 to 5...\n"); 5749 edata &= ~(EM_NVM_MSIX_N_MASK); 5750 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5751 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5752 e1000_update_nvm_checksum(hw); 5753 device_printf(dev, "Writing to eeprom: done\n"); 5754 } 5755 } 5756