1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 /* required last entry */ 178 PVID_END 179 }; 180 181 static pci_vendor_info_t igb_vendor_info_array[] = 182 { 183 /* Intel(R) PRO/1000 Network Connection - igb */ 184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 /* required last entry */ 224 PVID_END 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 static void *em_register(device_t dev); 231 static void *igb_register(device_t dev); 232 static int em_if_attach_pre(if_ctx_t ctx); 233 static int em_if_attach_post(if_ctx_t ctx); 234 static int em_if_detach(if_ctx_t ctx); 235 static int em_if_shutdown(if_ctx_t ctx); 236 static int em_if_suspend(if_ctx_t ctx); 237 static int em_if_resume(if_ctx_t ctx); 238 239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 241 static void em_if_queues_free(if_ctx_t ctx); 242 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 244 static void em_if_init(if_ctx_t ctx); 245 static void em_if_stop(if_ctx_t ctx); 246 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 247 static int em_if_media_change(if_ctx_t ctx); 248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 249 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 252 static void em_if_watchdog_reset(if_ctx_t ctx); 253 254 static void em_identify_hardware(if_ctx_t ctx); 255 static int em_allocate_pci_resources(if_ctx_t ctx); 256 static void em_free_pci_resources(if_ctx_t ctx); 257 static void em_reset(if_ctx_t ctx); 258 static int em_setup_interface(if_ctx_t ctx); 259 static int em_setup_msix(if_ctx_t ctx); 260 261 static void em_initialize_transmit_unit(if_ctx_t ctx); 262 static void em_initialize_receive_unit(if_ctx_t ctx); 263 264 static void em_if_intr_enable(if_ctx_t ctx); 265 static void em_if_intr_disable(if_ctx_t ctx); 266 static void igb_if_intr_enable(if_ctx_t ctx); 267 static void igb_if_intr_disable(if_ctx_t ctx); 268 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 269 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 270 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 271 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 272 static void em_if_multi_set(if_ctx_t ctx); 273 static void em_if_update_admin_status(if_ctx_t ctx); 274 static void em_if_debug(if_ctx_t ctx); 275 static void em_update_stats_counters(struct adapter *); 276 static void em_add_hw_stats(struct adapter *adapter); 277 static int em_if_set_promisc(if_ctx_t ctx, int flags); 278 static void em_setup_vlan_hw_support(struct adapter *); 279 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 280 static void em_print_nvm_info(struct adapter *); 281 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 282 static int em_get_rs(SYSCTL_HANDLER_ARGS); 283 static void em_print_debug_info(struct adapter *); 284 static int em_is_valid_ether_addr(u8 *); 285 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 286 static void em_add_int_delay_sysctl(struct adapter *, const char *, 287 const char *, struct em_int_delay_info *, int, int); 288 /* Management and WOL Support */ 289 static void em_init_manageability(struct adapter *); 290 static void em_release_manageability(struct adapter *); 291 static void em_get_hw_control(struct adapter *); 292 static void em_release_hw_control(struct adapter *); 293 static void em_get_wakeup(if_ctx_t ctx); 294 static void em_enable_wakeup(if_ctx_t ctx); 295 static int em_enable_phy_wakeup(struct adapter *); 296 static void em_disable_aspm(struct adapter *); 297 298 int em_intr(void *arg); 299 static void em_disable_promisc(if_ctx_t ctx); 300 301 /* MSI-X handlers */ 302 static int em_if_msix_intr_assign(if_ctx_t, int); 303 static int em_msix_link(void *); 304 static void em_handle_link(void *context); 305 306 static void em_enable_vectors_82574(if_ctx_t); 307 308 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 309 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 310 static void em_if_led_func(if_ctx_t ctx, int onoff); 311 312 static int em_get_regs(SYSCTL_HANDLER_ARGS); 313 314 static void lem_smartspeed(struct adapter *adapter); 315 static void igb_configure_queues(struct adapter *adapter); 316 317 318 /********************************************************************* 319 * FreeBSD Device Interface Entry Points 320 *********************************************************************/ 321 static device_method_t em_methods[] = { 322 /* Device interface */ 323 DEVMETHOD(device_register, em_register), 324 DEVMETHOD(device_probe, iflib_device_probe), 325 DEVMETHOD(device_attach, iflib_device_attach), 326 DEVMETHOD(device_detach, iflib_device_detach), 327 DEVMETHOD(device_shutdown, iflib_device_shutdown), 328 DEVMETHOD(device_suspend, iflib_device_suspend), 329 DEVMETHOD(device_resume, iflib_device_resume), 330 DEVMETHOD_END 331 }; 332 333 static device_method_t igb_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_register, igb_register), 336 DEVMETHOD(device_probe, iflib_device_probe), 337 DEVMETHOD(device_attach, iflib_device_attach), 338 DEVMETHOD(device_detach, iflib_device_detach), 339 DEVMETHOD(device_shutdown, iflib_device_shutdown), 340 DEVMETHOD(device_suspend, iflib_device_suspend), 341 DEVMETHOD(device_resume, iflib_device_resume), 342 DEVMETHOD_END 343 }; 344 345 346 static driver_t em_driver = { 347 "em", em_methods, sizeof(struct adapter), 348 }; 349 350 static devclass_t em_devclass; 351 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 352 353 MODULE_DEPEND(em, pci, 1, 1, 1); 354 MODULE_DEPEND(em, ether, 1, 1, 1); 355 MODULE_DEPEND(em, iflib, 1, 1, 1); 356 357 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 358 359 static driver_t igb_driver = { 360 "igb", igb_methods, sizeof(struct adapter), 361 }; 362 363 static devclass_t igb_devclass; 364 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 365 366 MODULE_DEPEND(igb, pci, 1, 1, 1); 367 MODULE_DEPEND(igb, ether, 1, 1, 1); 368 MODULE_DEPEND(igb, iflib, 1, 1, 1); 369 370 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 371 372 static device_method_t em_if_methods[] = { 373 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 374 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 375 DEVMETHOD(ifdi_detach, em_if_detach), 376 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 377 DEVMETHOD(ifdi_suspend, em_if_suspend), 378 DEVMETHOD(ifdi_resume, em_if_resume), 379 DEVMETHOD(ifdi_init, em_if_init), 380 DEVMETHOD(ifdi_stop, em_if_stop), 381 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 382 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 383 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 384 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 385 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 386 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 387 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 388 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 389 DEVMETHOD(ifdi_media_status, em_if_media_status), 390 DEVMETHOD(ifdi_media_change, em_if_media_change), 391 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 392 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 393 DEVMETHOD(ifdi_timer, em_if_timer), 394 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 395 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 396 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 397 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 398 DEVMETHOD(ifdi_led_func, em_if_led_func), 399 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 400 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 401 DEVMETHOD(ifdi_debug, em_if_debug), 402 DEVMETHOD_END 403 }; 404 405 static driver_t em_if_driver = { 406 "em_if", em_if_methods, sizeof(struct adapter) 407 }; 408 409 static device_method_t igb_if_methods[] = { 410 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 411 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 412 DEVMETHOD(ifdi_detach, em_if_detach), 413 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 414 DEVMETHOD(ifdi_suspend, em_if_suspend), 415 DEVMETHOD(ifdi_resume, em_if_resume), 416 DEVMETHOD(ifdi_init, em_if_init), 417 DEVMETHOD(ifdi_stop, em_if_stop), 418 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 419 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 420 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 421 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 422 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 423 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 424 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 425 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 426 DEVMETHOD(ifdi_media_status, em_if_media_status), 427 DEVMETHOD(ifdi_media_change, em_if_media_change), 428 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 429 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 430 DEVMETHOD(ifdi_timer, em_if_timer), 431 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 432 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 433 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 434 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 435 DEVMETHOD(ifdi_led_func, em_if_led_func), 436 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 437 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 438 DEVMETHOD(ifdi_debug, em_if_debug), 439 DEVMETHOD_END 440 }; 441 442 static driver_t igb_if_driver = { 443 "igb_if", igb_if_methods, sizeof(struct adapter) 444 }; 445 446 /********************************************************************* 447 * Tunable default values. 448 *********************************************************************/ 449 450 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 451 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 452 453 #define MAX_INTS_PER_SEC 8000 454 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 455 456 /* Allow common code without TSO */ 457 #ifndef CSUM_TSO 458 #define CSUM_TSO 0 459 #endif 460 461 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 462 463 static int em_disable_crc_stripping = 0; 464 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 465 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 466 467 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 468 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 469 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 470 0, "Default transmit interrupt delay in usecs"); 471 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 472 0, "Default receive interrupt delay in usecs"); 473 474 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 475 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 476 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 477 &em_tx_abs_int_delay_dflt, 0, 478 "Default transmit interrupt delay limit in usecs"); 479 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 480 &em_rx_abs_int_delay_dflt, 0, 481 "Default receive interrupt delay limit in usecs"); 482 483 static int em_smart_pwr_down = FALSE; 484 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 485 0, "Set to true to leave smart power down enabled on newer adapters"); 486 487 /* Controls whether promiscuous also shows bad packets */ 488 static int em_debug_sbp = TRUE; 489 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 490 "Show bad packets in promiscuous mode"); 491 492 /* How many packets rxeof tries to clean at a time */ 493 static int em_rx_process_limit = 100; 494 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 495 &em_rx_process_limit, 0, 496 "Maximum number of received packets to process " 497 "at a time, -1 means unlimited"); 498 499 /* Energy efficient ethernet - default to OFF */ 500 static int eee_setting = 1; 501 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 502 "Enable Energy Efficient Ethernet"); 503 504 /* 505 ** Tuneable Interrupt rate 506 */ 507 static int em_max_interrupt_rate = 8000; 508 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 509 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 510 511 512 513 /* Global used in WOL setup with multiport cards */ 514 static int global_quad_port_a = 0; 515 516 extern struct if_txrx igb_txrx; 517 extern struct if_txrx em_txrx; 518 extern struct if_txrx lem_txrx; 519 520 static struct if_shared_ctx em_sctx_init = { 521 .isc_magic = IFLIB_MAGIC, 522 .isc_q_align = PAGE_SIZE, 523 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 524 .isc_tx_maxsegsize = PAGE_SIZE, 525 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 526 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 527 .isc_rx_maxsize = MJUM9BYTES, 528 .isc_rx_nsegments = 1, 529 .isc_rx_maxsegsize = MJUM9BYTES, 530 .isc_nfl = 1, 531 .isc_nrxqs = 1, 532 .isc_ntxqs = 1, 533 .isc_admin_intrcnt = 1, 534 .isc_vendor_info = em_vendor_info_array, 535 .isc_driver_version = em_driver_version, 536 .isc_driver = &em_if_driver, 537 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 538 539 .isc_nrxd_min = {EM_MIN_RXD}, 540 .isc_ntxd_min = {EM_MIN_TXD}, 541 .isc_nrxd_max = {EM_MAX_RXD}, 542 .isc_ntxd_max = {EM_MAX_TXD}, 543 .isc_nrxd_default = {EM_DEFAULT_RXD}, 544 .isc_ntxd_default = {EM_DEFAULT_TXD}, 545 }; 546 547 if_shared_ctx_t em_sctx = &em_sctx_init; 548 549 static struct if_shared_ctx igb_sctx_init = { 550 .isc_magic = IFLIB_MAGIC, 551 .isc_q_align = PAGE_SIZE, 552 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 553 .isc_tx_maxsegsize = PAGE_SIZE, 554 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 555 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 556 .isc_rx_maxsize = MJUM9BYTES, 557 .isc_rx_nsegments = 1, 558 .isc_rx_maxsegsize = MJUM9BYTES, 559 .isc_nfl = 1, 560 .isc_nrxqs = 1, 561 .isc_ntxqs = 1, 562 .isc_admin_intrcnt = 1, 563 .isc_vendor_info = igb_vendor_info_array, 564 .isc_driver_version = em_driver_version, 565 .isc_driver = &igb_if_driver, 566 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 567 568 .isc_nrxd_min = {EM_MIN_RXD}, 569 .isc_ntxd_min = {EM_MIN_TXD}, 570 .isc_nrxd_max = {IGB_MAX_RXD}, 571 .isc_ntxd_max = {IGB_MAX_TXD}, 572 .isc_nrxd_default = {EM_DEFAULT_RXD}, 573 .isc_ntxd_default = {EM_DEFAULT_TXD}, 574 }; 575 576 if_shared_ctx_t igb_sctx = &igb_sctx_init; 577 578 /***************************************************************** 579 * 580 * Dump Registers 581 * 582 ****************************************************************/ 583 #define IGB_REGS_LEN 739 584 585 static int em_get_regs(SYSCTL_HANDLER_ARGS) 586 { 587 struct adapter *adapter = (struct adapter *)arg1; 588 struct e1000_hw *hw = &adapter->hw; 589 struct sbuf *sb; 590 u32 *regs_buff; 591 int rc; 592 593 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 594 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 595 596 rc = sysctl_wire_old_buffer(req, 0); 597 MPASS(rc == 0); 598 if (rc != 0) { 599 free(regs_buff, M_DEVBUF); 600 return (rc); 601 } 602 603 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 604 MPASS(sb != NULL); 605 if (sb == NULL) { 606 free(regs_buff, M_DEVBUF); 607 return (ENOMEM); 608 } 609 610 /* General Registers */ 611 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 612 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 613 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 614 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 615 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 616 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 617 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 618 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 619 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 620 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 621 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 622 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 623 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 624 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 625 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 626 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 627 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 628 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 629 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 630 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 631 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 632 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 633 634 sbuf_printf(sb, "General Registers\n"); 635 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 636 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 637 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 638 639 sbuf_printf(sb, "Interrupt Registers\n"); 640 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 641 642 sbuf_printf(sb, "RX Registers\n"); 643 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 644 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 645 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 646 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 647 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 648 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 649 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 650 651 sbuf_printf(sb, "TX Registers\n"); 652 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 653 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 654 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 655 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 656 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 657 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 658 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 659 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 660 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 661 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 662 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 663 664 free(regs_buff, M_DEVBUF); 665 666 #ifdef DUMP_DESCS 667 { 668 if_softc_ctx_t scctx = adapter->shared; 669 struct rx_ring *rxr = &rx_que->rxr; 670 struct tx_ring *txr = &tx_que->txr; 671 int ntxd = scctx->isc_ntxd[0]; 672 int nrxd = scctx->isc_nrxd[0]; 673 int j; 674 675 for (j = 0; j < nrxd; j++) { 676 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 677 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 678 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 679 } 680 681 for (j = 0; j < min(ntxd, 256); j++) { 682 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 683 684 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 685 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 686 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 687 688 } 689 } 690 #endif 691 692 rc = sbuf_finish(sb); 693 sbuf_delete(sb); 694 return(rc); 695 } 696 697 static void * 698 em_register(device_t dev) 699 { 700 return (em_sctx); 701 } 702 703 static void * 704 igb_register(device_t dev) 705 { 706 return (igb_sctx); 707 } 708 709 static int 710 em_set_num_queues(if_ctx_t ctx) 711 { 712 struct adapter *adapter = iflib_get_softc(ctx); 713 int maxqueues; 714 715 /* Sanity check based on HW */ 716 switch (adapter->hw.mac.type) { 717 case e1000_82576: 718 case e1000_82580: 719 case e1000_i350: 720 case e1000_i354: 721 maxqueues = 8; 722 break; 723 case e1000_i210: 724 case e1000_82575: 725 maxqueues = 4; 726 break; 727 case e1000_i211: 728 case e1000_82574: 729 maxqueues = 2; 730 break; 731 default: 732 maxqueues = 1; 733 break; 734 } 735 736 return (maxqueues); 737 } 738 739 #define LEM_CAPS \ 740 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 741 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 742 743 #define EM_CAPS \ 744 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 745 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 746 IFCAP_LRO | IFCAP_VLAN_HWTSO 747 748 #define IGB_CAPS \ 749 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 750 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 751 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 752 IFCAP_TSO6 753 754 /********************************************************************* 755 * Device initialization routine 756 * 757 * The attach entry point is called when the driver is being loaded. 758 * This routine identifies the type of hardware, allocates all resources 759 * and initializes the hardware. 760 * 761 * return 0 on success, positive on failure 762 *********************************************************************/ 763 static int 764 em_if_attach_pre(if_ctx_t ctx) 765 { 766 struct adapter *adapter; 767 if_softc_ctx_t scctx; 768 device_t dev; 769 struct e1000_hw *hw; 770 int error = 0; 771 772 INIT_DEBUGOUT("em_if_attach_pre: begin"); 773 dev = iflib_get_dev(ctx); 774 adapter = iflib_get_softc(ctx); 775 776 adapter->ctx = adapter->osdep.ctx = ctx; 777 adapter->dev = adapter->osdep.dev = dev; 778 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 779 adapter->media = iflib_get_media(ctx); 780 hw = &adapter->hw; 781 782 adapter->tx_process_limit = scctx->isc_ntxd[0]; 783 784 /* SYSCTL stuff */ 785 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 786 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 787 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 788 em_sysctl_nvm_info, "I", "NVM Information"); 789 790 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 791 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 792 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 793 em_sysctl_debug_info, "I", "Debug Information"); 794 795 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 796 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 797 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 798 em_set_flowcntl, "I", "Flow Control"); 799 800 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 801 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 802 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 803 em_get_regs, "A", "Dump Registers"); 804 805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 808 em_get_rs, "I", "Dump RS indexes"); 809 810 /* Determine hardware and mac info */ 811 em_identify_hardware(ctx); 812 813 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 814 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 815 if (bootverbose) 816 device_printf(dev, "attach_pre capping queues at %d\n", 817 scctx->isc_ntxqsets_max); 818 819 if (adapter->hw.mac.type >= igb_mac_min) { 820 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 821 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 822 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 823 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 824 scctx->isc_txrx = &igb_txrx; 825 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 826 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 827 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 828 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 829 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 830 CSUM_IP6_TCP | CSUM_IP6_UDP; 831 if (adapter->hw.mac.type != e1000_82575) 832 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 833 /* 834 ** Some new devices, as with ixgbe, now may 835 ** use a different BAR, so we need to keep 836 ** track of which is used. 837 */ 838 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 839 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 840 scctx->isc_msix_bar += 4; 841 } else if (adapter->hw.mac.type >= em_mac_min) { 842 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 843 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 844 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 845 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 846 scctx->isc_txrx = &em_txrx; 847 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 848 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 849 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 850 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 851 /* 852 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 853 * by default as we don't have workarounds for all associated 854 * silicon errata. E. g., with several MACs such as 82573E, 855 * TSO only works at Gigabit speed and otherwise can cause the 856 * hardware to hang (which also would be next to impossible to 857 * work around given that already queued TSO-using descriptors 858 * would need to be flushed and vlan(4) reconfigured at runtime 859 * in case of a link speed change). Moreover, MACs like 82579 860 * still can hang at Gigabit even with all publicly documented 861 * TSO workarounds implemented. Generally, the penality of 862 * these workarounds is rather high and may involve copying 863 * mbuf data around so advantages of TSO lapse. Still, TSO may 864 * work for a few MACs of this class - at least when sticking 865 * with Gigabit - in which case users may enable TSO manually. 866 */ 867 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 868 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 869 /* 870 * We support MSI-X with 82574 only, but indicate to iflib(4) 871 * that it shall give MSI at least a try with other devices. 872 */ 873 if (adapter->hw.mac.type == e1000_82574) { 874 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 875 } else { 876 scctx->isc_msix_bar = -1; 877 scctx->isc_disable_msix = 1; 878 } 879 } else { 880 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 881 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 882 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 883 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 884 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 885 scctx->isc_txrx = &lem_txrx; 886 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 887 if (adapter->hw.mac.type < e1000_82543) 888 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 889 /* INTx only */ 890 scctx->isc_msix_bar = 0; 891 } 892 893 /* Setup PCI resources */ 894 if (em_allocate_pci_resources(ctx)) { 895 device_printf(dev, "Allocation of PCI resources failed\n"); 896 error = ENXIO; 897 goto err_pci; 898 } 899 900 /* 901 ** For ICH8 and family we need to 902 ** map the flash memory, and this 903 ** must happen after the MAC is 904 ** identified 905 */ 906 if ((hw->mac.type == e1000_ich8lan) || 907 (hw->mac.type == e1000_ich9lan) || 908 (hw->mac.type == e1000_ich10lan) || 909 (hw->mac.type == e1000_pchlan) || 910 (hw->mac.type == e1000_pch2lan) || 911 (hw->mac.type == e1000_pch_lpt)) { 912 int rid = EM_BAR_TYPE_FLASH; 913 adapter->flash = bus_alloc_resource_any(dev, 914 SYS_RES_MEMORY, &rid, RF_ACTIVE); 915 if (adapter->flash == NULL) { 916 device_printf(dev, "Mapping of Flash failed\n"); 917 error = ENXIO; 918 goto err_pci; 919 } 920 /* This is used in the shared code */ 921 hw->flash_address = (u8 *)adapter->flash; 922 adapter->osdep.flash_bus_space_tag = 923 rman_get_bustag(adapter->flash); 924 adapter->osdep.flash_bus_space_handle = 925 rman_get_bushandle(adapter->flash); 926 } 927 /* 928 ** In the new SPT device flash is not a 929 ** separate BAR, rather it is also in BAR0, 930 ** so use the same tag and an offset handle for the 931 ** FLASH read/write macros in the shared code. 932 */ 933 else if (hw->mac.type >= e1000_pch_spt) { 934 adapter->osdep.flash_bus_space_tag = 935 adapter->osdep.mem_bus_space_tag; 936 adapter->osdep.flash_bus_space_handle = 937 adapter->osdep.mem_bus_space_handle 938 + E1000_FLASH_BASE_ADDR; 939 } 940 941 /* Do Shared Code initialization */ 942 error = e1000_setup_init_funcs(hw, TRUE); 943 if (error) { 944 device_printf(dev, "Setup of Shared code failed, error %d\n", 945 error); 946 error = ENXIO; 947 goto err_pci; 948 } 949 950 em_setup_msix(ctx); 951 e1000_get_bus_info(hw); 952 953 /* Set up some sysctls for the tunable interrupt delays */ 954 em_add_int_delay_sysctl(adapter, "rx_int_delay", 955 "receive interrupt delay in usecs", &adapter->rx_int_delay, 956 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 957 em_add_int_delay_sysctl(adapter, "tx_int_delay", 958 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 959 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 960 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 961 "receive interrupt delay limit in usecs", 962 &adapter->rx_abs_int_delay, 963 E1000_REGISTER(hw, E1000_RADV), 964 em_rx_abs_int_delay_dflt); 965 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 966 "transmit interrupt delay limit in usecs", 967 &adapter->tx_abs_int_delay, 968 E1000_REGISTER(hw, E1000_TADV), 969 em_tx_abs_int_delay_dflt); 970 em_add_int_delay_sysctl(adapter, "itr", 971 "interrupt delay limit in usecs/4", 972 &adapter->tx_itr, 973 E1000_REGISTER(hw, E1000_ITR), 974 DEFAULT_ITR); 975 976 hw->mac.autoneg = DO_AUTO_NEG; 977 hw->phy.autoneg_wait_to_complete = FALSE; 978 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 979 980 if (adapter->hw.mac.type < em_mac_min) { 981 e1000_init_script_state_82541(&adapter->hw, TRUE); 982 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 983 } 984 /* Copper options */ 985 if (hw->phy.media_type == e1000_media_type_copper) { 986 hw->phy.mdix = AUTO_ALL_MODES; 987 hw->phy.disable_polarity_correction = FALSE; 988 hw->phy.ms_type = EM_MASTER_SLAVE; 989 } 990 991 /* 992 * Set the frame limits assuming 993 * standard ethernet sized frames. 994 */ 995 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 996 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 997 998 /* 999 * This controls when hardware reports transmit completion 1000 * status. 1001 */ 1002 hw->mac.report_tx_early = 1; 1003 1004 /* Allocate multicast array memory. */ 1005 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 1006 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1007 if (adapter->mta == NULL) { 1008 device_printf(dev, "Can not allocate multicast setup array\n"); 1009 error = ENOMEM; 1010 goto err_late; 1011 } 1012 1013 /* Check SOL/IDER usage */ 1014 if (e1000_check_reset_block(hw)) 1015 device_printf(dev, "PHY reset is blocked" 1016 " due to SOL/IDER session.\n"); 1017 1018 /* Sysctl for setting Energy Efficient Ethernet */ 1019 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1020 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1021 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1022 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 1023 adapter, 0, em_sysctl_eee, "I", 1024 "Disable Energy Efficient Ethernet"); 1025 1026 /* 1027 ** Start from a known state, this is 1028 ** important in reading the nvm and 1029 ** mac from that. 1030 */ 1031 e1000_reset_hw(hw); 1032 1033 /* Make sure we have a good EEPROM before we read from it */ 1034 if (e1000_validate_nvm_checksum(hw) < 0) { 1035 /* 1036 ** Some PCI-E parts fail the first check due to 1037 ** the link being in sleep state, call it again, 1038 ** if it fails a second time its a real issue. 1039 */ 1040 if (e1000_validate_nvm_checksum(hw) < 0) { 1041 device_printf(dev, 1042 "The EEPROM Checksum Is Not Valid\n"); 1043 error = EIO; 1044 goto err_late; 1045 } 1046 } 1047 1048 /* Copy the permanent MAC address out of the EEPROM */ 1049 if (e1000_read_mac_addr(hw) < 0) { 1050 device_printf(dev, "EEPROM read error while reading MAC" 1051 " address\n"); 1052 error = EIO; 1053 goto err_late; 1054 } 1055 1056 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1057 device_printf(dev, "Invalid MAC address\n"); 1058 error = EIO; 1059 goto err_late; 1060 } 1061 1062 /* Disable ULP support */ 1063 e1000_disable_ulp_lpt_lp(hw, TRUE); 1064 1065 /* 1066 * Get Wake-on-Lan and Management info for later use 1067 */ 1068 em_get_wakeup(ctx); 1069 1070 /* Enable only WOL MAGIC by default */ 1071 scctx->isc_capenable &= ~IFCAP_WOL; 1072 if (adapter->wol != 0) 1073 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1074 1075 iflib_set_mac(ctx, hw->mac.addr); 1076 1077 return (0); 1078 1079 err_late: 1080 em_release_hw_control(adapter); 1081 err_pci: 1082 em_free_pci_resources(ctx); 1083 free(adapter->mta, M_DEVBUF); 1084 1085 return (error); 1086 } 1087 1088 static int 1089 em_if_attach_post(if_ctx_t ctx) 1090 { 1091 struct adapter *adapter = iflib_get_softc(ctx); 1092 struct e1000_hw *hw = &adapter->hw; 1093 int error = 0; 1094 1095 /* Setup OS specific network interface */ 1096 error = em_setup_interface(ctx); 1097 if (error != 0) { 1098 goto err_late; 1099 } 1100 1101 em_reset(ctx); 1102 1103 /* Initialize statistics */ 1104 em_update_stats_counters(adapter); 1105 hw->mac.get_link_status = 1; 1106 em_if_update_admin_status(ctx); 1107 em_add_hw_stats(adapter); 1108 1109 /* Non-AMT based hardware can now take control from firmware */ 1110 if (adapter->has_manage && !adapter->has_amt) 1111 em_get_hw_control(adapter); 1112 1113 INIT_DEBUGOUT("em_if_attach_post: end"); 1114 1115 return (error); 1116 1117 err_late: 1118 em_release_hw_control(adapter); 1119 em_free_pci_resources(ctx); 1120 em_if_queues_free(ctx); 1121 free(adapter->mta, M_DEVBUF); 1122 1123 return (error); 1124 } 1125 1126 /********************************************************************* 1127 * Device removal routine 1128 * 1129 * The detach entry point is called when the driver is being removed. 1130 * This routine stops the adapter and deallocates all the resources 1131 * that were allocated for driver operation. 1132 * 1133 * return 0 on success, positive on failure 1134 *********************************************************************/ 1135 static int 1136 em_if_detach(if_ctx_t ctx) 1137 { 1138 struct adapter *adapter = iflib_get_softc(ctx); 1139 1140 INIT_DEBUGOUT("em_if_detach: begin"); 1141 1142 e1000_phy_hw_reset(&adapter->hw); 1143 1144 em_release_manageability(adapter); 1145 em_release_hw_control(adapter); 1146 em_free_pci_resources(ctx); 1147 1148 return (0); 1149 } 1150 1151 /********************************************************************* 1152 * 1153 * Shutdown entry point 1154 * 1155 **********************************************************************/ 1156 1157 static int 1158 em_if_shutdown(if_ctx_t ctx) 1159 { 1160 return em_if_suspend(ctx); 1161 } 1162 1163 /* 1164 * Suspend/resume device methods. 1165 */ 1166 static int 1167 em_if_suspend(if_ctx_t ctx) 1168 { 1169 struct adapter *adapter = iflib_get_softc(ctx); 1170 1171 em_release_manageability(adapter); 1172 em_release_hw_control(adapter); 1173 em_enable_wakeup(ctx); 1174 return (0); 1175 } 1176 1177 static int 1178 em_if_resume(if_ctx_t ctx) 1179 { 1180 struct adapter *adapter = iflib_get_softc(ctx); 1181 1182 if (adapter->hw.mac.type == e1000_pch2lan) 1183 e1000_resume_workarounds_pchlan(&adapter->hw); 1184 em_if_init(ctx); 1185 em_init_manageability(adapter); 1186 1187 return(0); 1188 } 1189 1190 static int 1191 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1192 { 1193 int max_frame_size; 1194 struct adapter *adapter = iflib_get_softc(ctx); 1195 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1196 1197 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1198 1199 switch (adapter->hw.mac.type) { 1200 case e1000_82571: 1201 case e1000_82572: 1202 case e1000_ich9lan: 1203 case e1000_ich10lan: 1204 case e1000_pch2lan: 1205 case e1000_pch_lpt: 1206 case e1000_pch_spt: 1207 case e1000_pch_cnp: 1208 case e1000_82574: 1209 case e1000_82583: 1210 case e1000_80003es2lan: 1211 /* 9K Jumbo Frame size */ 1212 max_frame_size = 9234; 1213 break; 1214 case e1000_pchlan: 1215 max_frame_size = 4096; 1216 break; 1217 case e1000_82542: 1218 case e1000_ich8lan: 1219 /* Adapters that do not support jumbo frames */ 1220 max_frame_size = ETHER_MAX_LEN; 1221 break; 1222 default: 1223 if (adapter->hw.mac.type >= igb_mac_min) 1224 max_frame_size = 9234; 1225 else /* lem */ 1226 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1227 } 1228 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1229 return (EINVAL); 1230 } 1231 1232 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1233 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1234 return (0); 1235 } 1236 1237 /********************************************************************* 1238 * Init entry point 1239 * 1240 * This routine is used in two ways. It is used by the stack as 1241 * init entry point in network interface structure. It is also used 1242 * by the driver as a hw/sw initialization routine to get to a 1243 * consistent state. 1244 * 1245 **********************************************************************/ 1246 static void 1247 em_if_init(if_ctx_t ctx) 1248 { 1249 struct adapter *adapter = iflib_get_softc(ctx); 1250 if_softc_ctx_t scctx = adapter->shared; 1251 struct ifnet *ifp = iflib_get_ifp(ctx); 1252 struct em_tx_queue *tx_que; 1253 int i; 1254 1255 INIT_DEBUGOUT("em_if_init: begin"); 1256 1257 /* Get the latest mac address, User can use a LAA */ 1258 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1259 ETHER_ADDR_LEN); 1260 1261 /* Put the address into the Receive Address Array */ 1262 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1263 1264 /* 1265 * With the 82571 adapter, RAR[0] may be overwritten 1266 * when the other port is reset, we make a duplicate 1267 * in RAR[14] for that eventuality, this assures 1268 * the interface continues to function. 1269 */ 1270 if (adapter->hw.mac.type == e1000_82571) { 1271 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1272 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1273 E1000_RAR_ENTRIES - 1); 1274 } 1275 1276 1277 /* Initialize the hardware */ 1278 em_reset(ctx); 1279 em_if_update_admin_status(ctx); 1280 1281 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1282 struct tx_ring *txr = &tx_que->txr; 1283 1284 txr->tx_rs_cidx = txr->tx_rs_pidx; 1285 1286 /* Initialize the last processed descriptor to be the end of 1287 * the ring, rather than the start, so that we avoid an 1288 * off-by-one error when calculating how many descriptors are 1289 * done in the credits_update function. 1290 */ 1291 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1292 } 1293 1294 /* Setup VLAN support, basic and offload if available */ 1295 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1296 1297 /* Clear bad data from Rx FIFOs */ 1298 if (adapter->hw.mac.type >= igb_mac_min) 1299 e1000_rx_fifo_flush_82575(&adapter->hw); 1300 1301 /* Configure for OS presence */ 1302 em_init_manageability(adapter); 1303 1304 /* Prepare transmit descriptors and buffers */ 1305 em_initialize_transmit_unit(ctx); 1306 1307 /* Setup Multicast table */ 1308 em_if_multi_set(ctx); 1309 1310 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1311 em_initialize_receive_unit(ctx); 1312 1313 /* Use real VLAN Filter support? */ 1314 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1315 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1316 /* Use real VLAN Filter support */ 1317 em_setup_vlan_hw_support(adapter); 1318 else { 1319 u32 ctrl; 1320 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1321 ctrl |= E1000_CTRL_VME; 1322 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1323 } 1324 } 1325 1326 /* Don't lose promiscuous settings */ 1327 em_if_set_promisc(ctx, IFF_PROMISC); 1328 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1329 1330 /* MSI-X configuration for 82574 */ 1331 if (adapter->hw.mac.type == e1000_82574) { 1332 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1333 1334 tmp |= E1000_CTRL_EXT_PBA_CLR; 1335 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1336 /* Set the IVAR - interrupt vector routing. */ 1337 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1338 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1339 igb_configure_queues(adapter); 1340 1341 /* this clears any pending interrupts */ 1342 E1000_READ_REG(&adapter->hw, E1000_ICR); 1343 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1344 1345 /* AMT based hardware can now take control from firmware */ 1346 if (adapter->has_manage && adapter->has_amt) 1347 em_get_hw_control(adapter); 1348 1349 /* Set Energy Efficient Ethernet */ 1350 if (adapter->hw.mac.type >= igb_mac_min && 1351 adapter->hw.phy.media_type == e1000_media_type_copper) { 1352 if (adapter->hw.mac.type == e1000_i354) 1353 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1354 else 1355 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1356 } 1357 } 1358 1359 /********************************************************************* 1360 * 1361 * Fast Legacy/MSI Combined Interrupt Service routine 1362 * 1363 *********************************************************************/ 1364 int 1365 em_intr(void *arg) 1366 { 1367 struct adapter *adapter = arg; 1368 if_ctx_t ctx = adapter->ctx; 1369 u32 reg_icr; 1370 1371 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1372 1373 /* Hot eject? */ 1374 if (reg_icr == 0xffffffff) 1375 return FILTER_STRAY; 1376 1377 /* Definitely not our interrupt. */ 1378 if (reg_icr == 0x0) 1379 return FILTER_STRAY; 1380 1381 /* 1382 * Starting with the 82571 chip, bit 31 should be used to 1383 * determine whether the interrupt belongs to us. 1384 */ 1385 if (adapter->hw.mac.type >= e1000_82571 && 1386 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1387 return FILTER_STRAY; 1388 1389 /* 1390 * Only MSI-X interrupts have one-shot behavior by taking advantage 1391 * of the EIAC register. Thus, explicitly disable interrupts. This 1392 * also works around the MSI message reordering errata on certain 1393 * systems. 1394 */ 1395 IFDI_INTR_DISABLE(ctx); 1396 1397 /* Link status change */ 1398 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1399 adapter->hw.mac.get_link_status = 1; 1400 iflib_admin_intr_deferred(ctx); 1401 } 1402 1403 if (reg_icr & E1000_ICR_RXO) 1404 adapter->rx_overruns++; 1405 1406 return (FILTER_SCHEDULE_THREAD); 1407 } 1408 1409 static int 1410 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1411 { 1412 struct adapter *adapter = iflib_get_softc(ctx); 1413 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1414 1415 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1416 return (0); 1417 } 1418 1419 static int 1420 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1421 { 1422 struct adapter *adapter = iflib_get_softc(ctx); 1423 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1424 1425 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1426 return (0); 1427 } 1428 1429 static int 1430 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1431 { 1432 struct adapter *adapter = iflib_get_softc(ctx); 1433 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1434 1435 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1436 return (0); 1437 } 1438 1439 static int 1440 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1441 { 1442 struct adapter *adapter = iflib_get_softc(ctx); 1443 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1444 1445 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1446 return (0); 1447 } 1448 1449 /********************************************************************* 1450 * 1451 * MSI-X RX Interrupt Service routine 1452 * 1453 **********************************************************************/ 1454 static int 1455 em_msix_que(void *arg) 1456 { 1457 struct em_rx_queue *que = arg; 1458 1459 ++que->irqs; 1460 1461 return (FILTER_SCHEDULE_THREAD); 1462 } 1463 1464 /********************************************************************* 1465 * 1466 * MSI-X Link Fast Interrupt Service routine 1467 * 1468 **********************************************************************/ 1469 static int 1470 em_msix_link(void *arg) 1471 { 1472 struct adapter *adapter = arg; 1473 u32 reg_icr; 1474 1475 ++adapter->link_irq; 1476 MPASS(adapter->hw.back != NULL); 1477 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1478 1479 if (reg_icr & E1000_ICR_RXO) 1480 adapter->rx_overruns++; 1481 1482 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1483 em_handle_link(adapter->ctx); 1484 } else { 1485 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1486 EM_MSIX_LINK | E1000_IMS_LSC); 1487 if (adapter->hw.mac.type >= igb_mac_min) 1488 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1489 } 1490 1491 /* 1492 * Because we must read the ICR for this interrupt 1493 * it may clear other causes using autoclear, for 1494 * this reason we simply create a soft interrupt 1495 * for all these vectors. 1496 */ 1497 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1498 E1000_WRITE_REG(&adapter->hw, 1499 E1000_ICS, adapter->ims); 1500 } 1501 1502 return (FILTER_HANDLED); 1503 } 1504 1505 static void 1506 em_handle_link(void *context) 1507 { 1508 if_ctx_t ctx = context; 1509 struct adapter *adapter = iflib_get_softc(ctx); 1510 1511 adapter->hw.mac.get_link_status = 1; 1512 iflib_admin_intr_deferred(ctx); 1513 } 1514 1515 1516 /********************************************************************* 1517 * 1518 * Media Ioctl callback 1519 * 1520 * This routine is called whenever the user queries the status of 1521 * the interface using ifconfig. 1522 * 1523 **********************************************************************/ 1524 static void 1525 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1526 { 1527 struct adapter *adapter = iflib_get_softc(ctx); 1528 u_char fiber_type = IFM_1000_SX; 1529 1530 INIT_DEBUGOUT("em_if_media_status: begin"); 1531 1532 iflib_admin_intr_deferred(ctx); 1533 1534 ifmr->ifm_status = IFM_AVALID; 1535 ifmr->ifm_active = IFM_ETHER; 1536 1537 if (!adapter->link_active) { 1538 return; 1539 } 1540 1541 ifmr->ifm_status |= IFM_ACTIVE; 1542 1543 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1544 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1545 if (adapter->hw.mac.type == e1000_82545) 1546 fiber_type = IFM_1000_LX; 1547 ifmr->ifm_active |= fiber_type | IFM_FDX; 1548 } else { 1549 switch (adapter->link_speed) { 1550 case 10: 1551 ifmr->ifm_active |= IFM_10_T; 1552 break; 1553 case 100: 1554 ifmr->ifm_active |= IFM_100_TX; 1555 break; 1556 case 1000: 1557 ifmr->ifm_active |= IFM_1000_T; 1558 break; 1559 } 1560 if (adapter->link_duplex == FULL_DUPLEX) 1561 ifmr->ifm_active |= IFM_FDX; 1562 else 1563 ifmr->ifm_active |= IFM_HDX; 1564 } 1565 } 1566 1567 /********************************************************************* 1568 * 1569 * Media Ioctl callback 1570 * 1571 * This routine is called when the user changes speed/duplex using 1572 * media/mediopt option with ifconfig. 1573 * 1574 **********************************************************************/ 1575 static int 1576 em_if_media_change(if_ctx_t ctx) 1577 { 1578 struct adapter *adapter = iflib_get_softc(ctx); 1579 struct ifmedia *ifm = iflib_get_media(ctx); 1580 1581 INIT_DEBUGOUT("em_if_media_change: begin"); 1582 1583 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1584 return (EINVAL); 1585 1586 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1587 case IFM_AUTO: 1588 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1589 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1590 break; 1591 case IFM_1000_LX: 1592 case IFM_1000_SX: 1593 case IFM_1000_T: 1594 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1595 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1596 break; 1597 case IFM_100_TX: 1598 adapter->hw.mac.autoneg = FALSE; 1599 adapter->hw.phy.autoneg_advertised = 0; 1600 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1601 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1602 else 1603 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1604 break; 1605 case IFM_10_T: 1606 adapter->hw.mac.autoneg = FALSE; 1607 adapter->hw.phy.autoneg_advertised = 0; 1608 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1609 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1610 else 1611 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1612 break; 1613 default: 1614 device_printf(adapter->dev, "Unsupported media type\n"); 1615 } 1616 1617 em_if_init(ctx); 1618 1619 return (0); 1620 } 1621 1622 static int 1623 em_if_set_promisc(if_ctx_t ctx, int flags) 1624 { 1625 struct adapter *adapter = iflib_get_softc(ctx); 1626 u32 reg_rctl; 1627 1628 em_disable_promisc(ctx); 1629 1630 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1631 1632 if (flags & IFF_PROMISC) { 1633 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1634 /* Turn this on if you want to see bad packets */ 1635 if (em_debug_sbp) 1636 reg_rctl |= E1000_RCTL_SBP; 1637 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1638 } else if (flags & IFF_ALLMULTI) { 1639 reg_rctl |= E1000_RCTL_MPE; 1640 reg_rctl &= ~E1000_RCTL_UPE; 1641 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1642 } 1643 return (0); 1644 } 1645 1646 static void 1647 em_disable_promisc(if_ctx_t ctx) 1648 { 1649 struct adapter *adapter = iflib_get_softc(ctx); 1650 struct ifnet *ifp = iflib_get_ifp(ctx); 1651 u32 reg_rctl; 1652 int mcnt = 0; 1653 1654 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1655 reg_rctl &= (~E1000_RCTL_UPE); 1656 if (if_getflags(ifp) & IFF_ALLMULTI) 1657 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1658 else 1659 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1660 /* Don't disable if in MAX groups */ 1661 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1662 reg_rctl &= (~E1000_RCTL_MPE); 1663 reg_rctl &= (~E1000_RCTL_SBP); 1664 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1665 } 1666 1667 1668 /********************************************************************* 1669 * Multicast Update 1670 * 1671 * This routine is called whenever multicast address list is updated. 1672 * 1673 **********************************************************************/ 1674 1675 static void 1676 em_if_multi_set(if_ctx_t ctx) 1677 { 1678 struct adapter *adapter = iflib_get_softc(ctx); 1679 struct ifnet *ifp = iflib_get_ifp(ctx); 1680 u32 reg_rctl = 0; 1681 u8 *mta; /* Multicast array memory */ 1682 int mcnt = 0; 1683 1684 IOCTL_DEBUGOUT("em_set_multi: begin"); 1685 1686 mta = adapter->mta; 1687 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1688 1689 if (adapter->hw.mac.type == e1000_82542 && 1690 adapter->hw.revision_id == E1000_REVISION_2) { 1691 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1692 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1693 e1000_pci_clear_mwi(&adapter->hw); 1694 reg_rctl |= E1000_RCTL_RST; 1695 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1696 msec_delay(5); 1697 } 1698 1699 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1700 1701 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1702 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1703 reg_rctl |= E1000_RCTL_MPE; 1704 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1705 } else 1706 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1707 1708 if (adapter->hw.mac.type == e1000_82542 && 1709 adapter->hw.revision_id == E1000_REVISION_2) { 1710 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1711 reg_rctl &= ~E1000_RCTL_RST; 1712 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1713 msec_delay(5); 1714 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1715 e1000_pci_set_mwi(&adapter->hw); 1716 } 1717 } 1718 1719 /********************************************************************* 1720 * Timer routine 1721 * 1722 * This routine schedules em_if_update_admin_status() to check for 1723 * link status and to gather statistics as well as to perform some 1724 * controller-specific hardware patting. 1725 * 1726 **********************************************************************/ 1727 static void 1728 em_if_timer(if_ctx_t ctx, uint16_t qid) 1729 { 1730 1731 if (qid != 0) 1732 return; 1733 1734 iflib_admin_intr_deferred(ctx); 1735 } 1736 1737 static void 1738 em_if_update_admin_status(if_ctx_t ctx) 1739 { 1740 struct adapter *adapter = iflib_get_softc(ctx); 1741 struct e1000_hw *hw = &adapter->hw; 1742 device_t dev = iflib_get_dev(ctx); 1743 u32 link_check, thstat, ctrl; 1744 1745 link_check = thstat = ctrl = 0; 1746 /* Get the cached link value or read phy for real */ 1747 switch (hw->phy.media_type) { 1748 case e1000_media_type_copper: 1749 if (hw->mac.get_link_status) { 1750 if (hw->mac.type == e1000_pch_spt) 1751 msec_delay(50); 1752 /* Do the work to read phy */ 1753 e1000_check_for_link(hw); 1754 link_check = !hw->mac.get_link_status; 1755 if (link_check) /* ESB2 fix */ 1756 e1000_cfg_on_link_up(hw); 1757 } else { 1758 link_check = TRUE; 1759 } 1760 break; 1761 case e1000_media_type_fiber: 1762 e1000_check_for_link(hw); 1763 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1764 E1000_STATUS_LU); 1765 break; 1766 case e1000_media_type_internal_serdes: 1767 e1000_check_for_link(hw); 1768 link_check = adapter->hw.mac.serdes_has_link; 1769 break; 1770 /* VF device is type_unknown */ 1771 case e1000_media_type_unknown: 1772 e1000_check_for_link(hw); 1773 link_check = !hw->mac.get_link_status; 1774 /* FALLTHROUGH */ 1775 default: 1776 break; 1777 } 1778 1779 /* Check for thermal downshift or shutdown */ 1780 if (hw->mac.type == e1000_i350) { 1781 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1782 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1783 } 1784 1785 /* Now check for a transition */ 1786 if (link_check && (adapter->link_active == 0)) { 1787 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1788 &adapter->link_duplex); 1789 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1790 if ((adapter->link_speed != SPEED_1000) && 1791 ((hw->mac.type == e1000_82571) || 1792 (hw->mac.type == e1000_82572))) { 1793 int tarc0; 1794 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1795 tarc0 &= ~TARC_SPEED_MODE_BIT; 1796 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1797 } 1798 if (bootverbose) 1799 device_printf(dev, "Link is up %d Mbps %s\n", 1800 adapter->link_speed, 1801 ((adapter->link_duplex == FULL_DUPLEX) ? 1802 "Full Duplex" : "Half Duplex")); 1803 adapter->link_active = 1; 1804 adapter->smartspeed = 0; 1805 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1806 E1000_CTRL_EXT_LINK_MODE_GMII && 1807 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1808 device_printf(dev, "Link: thermal downshift\n"); 1809 /* Delay Link Up for Phy update */ 1810 if (((hw->mac.type == e1000_i210) || 1811 (hw->mac.type == e1000_i211)) && 1812 (hw->phy.id == I210_I_PHY_ID)) 1813 msec_delay(I210_LINK_DELAY); 1814 /* Reset if the media type changed. */ 1815 if ((hw->dev_spec._82575.media_changed) && 1816 (adapter->hw.mac.type >= igb_mac_min)) { 1817 hw->dev_spec._82575.media_changed = false; 1818 adapter->flags |= IGB_MEDIA_RESET; 1819 em_reset(ctx); 1820 } 1821 iflib_link_state_change(ctx, LINK_STATE_UP, 1822 IF_Mbps(adapter->link_speed)); 1823 } else if (!link_check && (adapter->link_active == 1)) { 1824 adapter->link_speed = 0; 1825 adapter->link_duplex = 0; 1826 adapter->link_active = 0; 1827 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1828 } 1829 em_update_stats_counters(adapter); 1830 1831 /* Reset LAA into RAR[0] on 82571 */ 1832 if ((adapter->hw.mac.type == e1000_82571) && 1833 e1000_get_laa_state_82571(&adapter->hw)) 1834 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1835 1836 if (adapter->hw.mac.type < em_mac_min) 1837 lem_smartspeed(adapter); 1838 1839 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1840 } 1841 1842 static void 1843 em_if_watchdog_reset(if_ctx_t ctx) 1844 { 1845 struct adapter *adapter = iflib_get_softc(ctx); 1846 1847 /* 1848 * Just count the event; iflib(4) will already trigger a 1849 * sufficient reset of the controller. 1850 */ 1851 adapter->watchdog_events++; 1852 } 1853 1854 /********************************************************************* 1855 * 1856 * This routine disables all traffic on the adapter by issuing a 1857 * global reset on the MAC. 1858 * 1859 **********************************************************************/ 1860 static void 1861 em_if_stop(if_ctx_t ctx) 1862 { 1863 struct adapter *adapter = iflib_get_softc(ctx); 1864 1865 INIT_DEBUGOUT("em_if_stop: begin"); 1866 1867 e1000_reset_hw(&adapter->hw); 1868 if (adapter->hw.mac.type >= e1000_82544) 1869 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1870 1871 e1000_led_off(&adapter->hw); 1872 e1000_cleanup_led(&adapter->hw); 1873 } 1874 1875 /********************************************************************* 1876 * 1877 * Determine hardware revision. 1878 * 1879 **********************************************************************/ 1880 static void 1881 em_identify_hardware(if_ctx_t ctx) 1882 { 1883 device_t dev = iflib_get_dev(ctx); 1884 struct adapter *adapter = iflib_get_softc(ctx); 1885 1886 /* Make sure our PCI config space has the necessary stuff set */ 1887 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1888 1889 /* Save off the information about this board */ 1890 adapter->hw.vendor_id = pci_get_vendor(dev); 1891 adapter->hw.device_id = pci_get_device(dev); 1892 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1893 adapter->hw.subsystem_vendor_id = 1894 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1895 adapter->hw.subsystem_device_id = 1896 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1897 1898 /* Do Shared Code Init and Setup */ 1899 if (e1000_set_mac_type(&adapter->hw)) { 1900 device_printf(dev, "Setup init failure\n"); 1901 return; 1902 } 1903 } 1904 1905 static int 1906 em_allocate_pci_resources(if_ctx_t ctx) 1907 { 1908 struct adapter *adapter = iflib_get_softc(ctx); 1909 device_t dev = iflib_get_dev(ctx); 1910 int rid, val; 1911 1912 rid = PCIR_BAR(0); 1913 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1914 &rid, RF_ACTIVE); 1915 if (adapter->memory == NULL) { 1916 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1917 return (ENXIO); 1918 } 1919 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1920 adapter->osdep.mem_bus_space_handle = 1921 rman_get_bushandle(adapter->memory); 1922 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1923 1924 /* Only older adapters use IO mapping */ 1925 if (adapter->hw.mac.type < em_mac_min && 1926 adapter->hw.mac.type > e1000_82543) { 1927 /* Figure our where our IO BAR is ? */ 1928 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1929 val = pci_read_config(dev, rid, 4); 1930 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1931 break; 1932 } 1933 rid += 4; 1934 /* check for 64bit BAR */ 1935 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1936 rid += 4; 1937 } 1938 if (rid >= PCIR_CIS) { 1939 device_printf(dev, "Unable to locate IO BAR\n"); 1940 return (ENXIO); 1941 } 1942 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1943 &rid, RF_ACTIVE); 1944 if (adapter->ioport == NULL) { 1945 device_printf(dev, "Unable to allocate bus resource: " 1946 "ioport\n"); 1947 return (ENXIO); 1948 } 1949 adapter->hw.io_base = 0; 1950 adapter->osdep.io_bus_space_tag = 1951 rman_get_bustag(adapter->ioport); 1952 adapter->osdep.io_bus_space_handle = 1953 rman_get_bushandle(adapter->ioport); 1954 } 1955 1956 adapter->hw.back = &adapter->osdep; 1957 1958 return (0); 1959 } 1960 1961 /********************************************************************* 1962 * 1963 * Set up the MSI-X Interrupt handlers 1964 * 1965 **********************************************************************/ 1966 static int 1967 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1968 { 1969 struct adapter *adapter = iflib_get_softc(ctx); 1970 struct em_rx_queue *rx_que = adapter->rx_queues; 1971 struct em_tx_queue *tx_que = adapter->tx_queues; 1972 int error, rid, i, vector = 0, rx_vectors; 1973 char buf[16]; 1974 1975 /* First set up ring resources */ 1976 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1977 rid = vector + 1; 1978 snprintf(buf, sizeof(buf), "rxq%d", i); 1979 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1980 if (error) { 1981 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1982 adapter->rx_num_queues = i + 1; 1983 goto fail; 1984 } 1985 1986 rx_que->msix = vector; 1987 1988 /* 1989 * Set the bit to enable interrupt 1990 * in E1000_IMS -- bits 20 and 21 1991 * are for RX0 and RX1, note this has 1992 * NOTHING to do with the MSI-X vector 1993 */ 1994 if (adapter->hw.mac.type == e1000_82574) { 1995 rx_que->eims = 1 << (20 + i); 1996 adapter->ims |= rx_que->eims; 1997 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1998 } else if (adapter->hw.mac.type == e1000_82575) 1999 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2000 else 2001 rx_que->eims = 1 << vector; 2002 } 2003 rx_vectors = vector; 2004 2005 vector = 0; 2006 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2007 snprintf(buf, sizeof(buf), "txq%d", i); 2008 tx_que = &adapter->tx_queues[i]; 2009 iflib_softirq_alloc_generic(ctx, 2010 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2011 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2012 2013 tx_que->msix = (vector % adapter->rx_num_queues); 2014 2015 /* 2016 * Set the bit to enable interrupt 2017 * in E1000_IMS -- bits 22 and 23 2018 * are for TX0 and TX1, note this has 2019 * NOTHING to do with the MSI-X vector 2020 */ 2021 if (adapter->hw.mac.type == e1000_82574) { 2022 tx_que->eims = 1 << (22 + i); 2023 adapter->ims |= tx_que->eims; 2024 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2025 } else if (adapter->hw.mac.type == e1000_82575) { 2026 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2027 } else { 2028 tx_que->eims = 1 << i; 2029 } 2030 } 2031 2032 /* Link interrupt */ 2033 rid = rx_vectors + 1; 2034 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2035 2036 if (error) { 2037 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2038 goto fail; 2039 } 2040 adapter->linkvec = rx_vectors; 2041 if (adapter->hw.mac.type < igb_mac_min) { 2042 adapter->ivars |= (8 | rx_vectors) << 16; 2043 adapter->ivars |= 0x80000000; 2044 } 2045 return (0); 2046 fail: 2047 iflib_irq_free(ctx, &adapter->irq); 2048 rx_que = adapter->rx_queues; 2049 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2050 iflib_irq_free(ctx, &rx_que->que_irq); 2051 return (error); 2052 } 2053 2054 static void 2055 igb_configure_queues(struct adapter *adapter) 2056 { 2057 struct e1000_hw *hw = &adapter->hw; 2058 struct em_rx_queue *rx_que; 2059 struct em_tx_queue *tx_que; 2060 u32 tmp, ivar = 0, newitr = 0; 2061 2062 /* First turn on RSS capability */ 2063 if (adapter->hw.mac.type != e1000_82575) 2064 E1000_WRITE_REG(hw, E1000_GPIE, 2065 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2066 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2067 2068 /* Turn on MSI-X */ 2069 switch (adapter->hw.mac.type) { 2070 case e1000_82580: 2071 case e1000_i350: 2072 case e1000_i354: 2073 case e1000_i210: 2074 case e1000_i211: 2075 case e1000_vfadapt: 2076 case e1000_vfadapt_i350: 2077 /* RX entries */ 2078 for (int i = 0; i < adapter->rx_num_queues; i++) { 2079 u32 index = i >> 1; 2080 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2081 rx_que = &adapter->rx_queues[i]; 2082 if (i & 1) { 2083 ivar &= 0xFF00FFFF; 2084 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2085 } else { 2086 ivar &= 0xFFFFFF00; 2087 ivar |= rx_que->msix | E1000_IVAR_VALID; 2088 } 2089 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2090 } 2091 /* TX entries */ 2092 for (int i = 0; i < adapter->tx_num_queues; i++) { 2093 u32 index = i >> 1; 2094 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2095 tx_que = &adapter->tx_queues[i]; 2096 if (i & 1) { 2097 ivar &= 0x00FFFFFF; 2098 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2099 } else { 2100 ivar &= 0xFFFF00FF; 2101 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2102 } 2103 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2104 adapter->que_mask |= tx_que->eims; 2105 } 2106 2107 /* And for the link interrupt */ 2108 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2109 adapter->link_mask = 1 << adapter->linkvec; 2110 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2111 break; 2112 case e1000_82576: 2113 /* RX entries */ 2114 for (int i = 0; i < adapter->rx_num_queues; i++) { 2115 u32 index = i & 0x7; /* Each IVAR has two entries */ 2116 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2117 rx_que = &adapter->rx_queues[i]; 2118 if (i < 8) { 2119 ivar &= 0xFFFFFF00; 2120 ivar |= rx_que->msix | E1000_IVAR_VALID; 2121 } else { 2122 ivar &= 0xFF00FFFF; 2123 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2124 } 2125 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2126 adapter->que_mask |= rx_que->eims; 2127 } 2128 /* TX entries */ 2129 for (int i = 0; i < adapter->tx_num_queues; i++) { 2130 u32 index = i & 0x7; /* Each IVAR has two entries */ 2131 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2132 tx_que = &adapter->tx_queues[i]; 2133 if (i < 8) { 2134 ivar &= 0xFFFF00FF; 2135 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2136 } else { 2137 ivar &= 0x00FFFFFF; 2138 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2139 } 2140 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2141 adapter->que_mask |= tx_que->eims; 2142 } 2143 2144 /* And for the link interrupt */ 2145 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2146 adapter->link_mask = 1 << adapter->linkvec; 2147 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2148 break; 2149 2150 case e1000_82575: 2151 /* enable MSI-X support*/ 2152 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2153 tmp |= E1000_CTRL_EXT_PBA_CLR; 2154 /* Auto-Mask interrupts upon ICR read. */ 2155 tmp |= E1000_CTRL_EXT_EIAME; 2156 tmp |= E1000_CTRL_EXT_IRCA; 2157 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2158 2159 /* Queues */ 2160 for (int i = 0; i < adapter->rx_num_queues; i++) { 2161 rx_que = &adapter->rx_queues[i]; 2162 tmp = E1000_EICR_RX_QUEUE0 << i; 2163 tmp |= E1000_EICR_TX_QUEUE0 << i; 2164 rx_que->eims = tmp; 2165 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2166 i, rx_que->eims); 2167 adapter->que_mask |= rx_que->eims; 2168 } 2169 2170 /* Link */ 2171 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2172 E1000_EIMS_OTHER); 2173 adapter->link_mask |= E1000_EIMS_OTHER; 2174 default: 2175 break; 2176 } 2177 2178 /* Set the starting interrupt rate */ 2179 if (em_max_interrupt_rate > 0) 2180 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2181 2182 if (hw->mac.type == e1000_82575) 2183 newitr |= newitr << 16; 2184 else 2185 newitr |= E1000_EITR_CNT_IGNR; 2186 2187 for (int i = 0; i < adapter->rx_num_queues; i++) { 2188 rx_que = &adapter->rx_queues[i]; 2189 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2190 } 2191 2192 return; 2193 } 2194 2195 static void 2196 em_free_pci_resources(if_ctx_t ctx) 2197 { 2198 struct adapter *adapter = iflib_get_softc(ctx); 2199 struct em_rx_queue *que = adapter->rx_queues; 2200 device_t dev = iflib_get_dev(ctx); 2201 2202 /* Release all MSI-X queue resources */ 2203 if (adapter->intr_type == IFLIB_INTR_MSIX) 2204 iflib_irq_free(ctx, &adapter->irq); 2205 2206 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2207 iflib_irq_free(ctx, &que->que_irq); 2208 } 2209 2210 if (adapter->memory != NULL) { 2211 bus_release_resource(dev, SYS_RES_MEMORY, 2212 rman_get_rid(adapter->memory), adapter->memory); 2213 adapter->memory = NULL; 2214 } 2215 2216 if (adapter->flash != NULL) { 2217 bus_release_resource(dev, SYS_RES_MEMORY, 2218 rman_get_rid(adapter->flash), adapter->flash); 2219 adapter->flash = NULL; 2220 } 2221 2222 if (adapter->ioport != NULL) { 2223 bus_release_resource(dev, SYS_RES_IOPORT, 2224 rman_get_rid(adapter->ioport), adapter->ioport); 2225 adapter->ioport = NULL; 2226 } 2227 } 2228 2229 /* Set up MSI or MSI-X */ 2230 static int 2231 em_setup_msix(if_ctx_t ctx) 2232 { 2233 struct adapter *adapter = iflib_get_softc(ctx); 2234 2235 if (adapter->hw.mac.type == e1000_82574) { 2236 em_enable_vectors_82574(ctx); 2237 } 2238 return (0); 2239 } 2240 2241 /********************************************************************* 2242 * 2243 * Workaround for SmartSpeed on 82541 and 82547 controllers 2244 * 2245 **********************************************************************/ 2246 static void 2247 lem_smartspeed(struct adapter *adapter) 2248 { 2249 u16 phy_tmp; 2250 2251 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2252 adapter->hw.mac.autoneg == 0 || 2253 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2254 return; 2255 2256 if (adapter->smartspeed == 0) { 2257 /* If Master/Slave config fault is asserted twice, 2258 * we assume back-to-back */ 2259 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2260 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2261 return; 2262 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2263 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2264 e1000_read_phy_reg(&adapter->hw, 2265 PHY_1000T_CTRL, &phy_tmp); 2266 if(phy_tmp & CR_1000T_MS_ENABLE) { 2267 phy_tmp &= ~CR_1000T_MS_ENABLE; 2268 e1000_write_phy_reg(&adapter->hw, 2269 PHY_1000T_CTRL, phy_tmp); 2270 adapter->smartspeed++; 2271 if(adapter->hw.mac.autoneg && 2272 !e1000_copper_link_autoneg(&adapter->hw) && 2273 !e1000_read_phy_reg(&adapter->hw, 2274 PHY_CONTROL, &phy_tmp)) { 2275 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2276 MII_CR_RESTART_AUTO_NEG); 2277 e1000_write_phy_reg(&adapter->hw, 2278 PHY_CONTROL, phy_tmp); 2279 } 2280 } 2281 } 2282 return; 2283 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2284 /* If still no link, perhaps using 2/3 pair cable */ 2285 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2286 phy_tmp |= CR_1000T_MS_ENABLE; 2287 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2288 if(adapter->hw.mac.autoneg && 2289 !e1000_copper_link_autoneg(&adapter->hw) && 2290 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2291 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2292 MII_CR_RESTART_AUTO_NEG); 2293 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2294 } 2295 } 2296 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2297 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2298 adapter->smartspeed = 0; 2299 } 2300 2301 /********************************************************************* 2302 * 2303 * Initialize the DMA Coalescing feature 2304 * 2305 **********************************************************************/ 2306 static void 2307 igb_init_dmac(struct adapter *adapter, u32 pba) 2308 { 2309 device_t dev = adapter->dev; 2310 struct e1000_hw *hw = &adapter->hw; 2311 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2312 u16 hwm; 2313 u16 max_frame_size; 2314 2315 if (hw->mac.type == e1000_i211) 2316 return; 2317 2318 max_frame_size = adapter->shared->isc_max_frame_size; 2319 if (hw->mac.type > e1000_82580) { 2320 2321 if (adapter->dmac == 0) { /* Disabling it */ 2322 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2323 return; 2324 } else 2325 device_printf(dev, "DMA Coalescing enabled\n"); 2326 2327 /* Set starting threshold */ 2328 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2329 2330 hwm = 64 * pba - max_frame_size / 16; 2331 if (hwm < 64 * (pba - 6)) 2332 hwm = 64 * (pba - 6); 2333 reg = E1000_READ_REG(hw, E1000_FCRTC); 2334 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2335 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2336 & E1000_FCRTC_RTH_COAL_MASK); 2337 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2338 2339 2340 dmac = pba - max_frame_size / 512; 2341 if (dmac < pba - 10) 2342 dmac = pba - 10; 2343 reg = E1000_READ_REG(hw, E1000_DMACR); 2344 reg &= ~E1000_DMACR_DMACTHR_MASK; 2345 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2346 & E1000_DMACR_DMACTHR_MASK); 2347 2348 /* transition to L0x or L1 if available..*/ 2349 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2350 2351 /* Check if status is 2.5Gb backplane connection 2352 * before configuration of watchdog timer, which is 2353 * in msec values in 12.8usec intervals 2354 * watchdog timer= msec values in 32usec intervals 2355 * for non 2.5Gb connection 2356 */ 2357 if (hw->mac.type == e1000_i354) { 2358 int status = E1000_READ_REG(hw, E1000_STATUS); 2359 if ((status & E1000_STATUS_2P5_SKU) && 2360 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2361 reg |= ((adapter->dmac * 5) >> 6); 2362 else 2363 reg |= (adapter->dmac >> 5); 2364 } else { 2365 reg |= (adapter->dmac >> 5); 2366 } 2367 2368 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2369 2370 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2371 2372 /* Set the interval before transition */ 2373 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2374 if (hw->mac.type == e1000_i350) 2375 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2376 /* 2377 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2378 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2379 */ 2380 if (hw->mac.type == e1000_i354) { 2381 int status = E1000_READ_REG(hw, E1000_STATUS); 2382 if ((status & E1000_STATUS_2P5_SKU) && 2383 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2384 reg |= 0xA; 2385 else 2386 reg |= 0x4; 2387 } else { 2388 reg |= 0x4; 2389 } 2390 2391 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2392 2393 /* free space in tx packet buffer to wake from DMA coal */ 2394 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2395 (2 * max_frame_size)) >> 6); 2396 2397 /* make low power state decision controlled by DMA coal */ 2398 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2399 reg &= ~E1000_PCIEMISC_LX_DECISION; 2400 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2401 2402 } else if (hw->mac.type == e1000_82580) { 2403 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2404 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2405 reg & ~E1000_PCIEMISC_LX_DECISION); 2406 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2407 } 2408 } 2409 2410 /********************************************************************* 2411 * 2412 * Initialize the hardware to a configuration as specified by the 2413 * adapter structure. 2414 * 2415 **********************************************************************/ 2416 static void 2417 em_reset(if_ctx_t ctx) 2418 { 2419 device_t dev = iflib_get_dev(ctx); 2420 struct adapter *adapter = iflib_get_softc(ctx); 2421 struct ifnet *ifp = iflib_get_ifp(ctx); 2422 struct e1000_hw *hw = &adapter->hw; 2423 u16 rx_buffer_size; 2424 u32 pba; 2425 2426 INIT_DEBUGOUT("em_reset: begin"); 2427 /* Let the firmware know the OS is in control */ 2428 em_get_hw_control(adapter); 2429 2430 /* Set up smart power down as default off on newer adapters. */ 2431 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2432 hw->mac.type == e1000_82572)) { 2433 u16 phy_tmp = 0; 2434 2435 /* Speed up time to link by disabling smart power down. */ 2436 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2437 phy_tmp &= ~IGP02E1000_PM_SPD; 2438 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2439 } 2440 2441 /* 2442 * Packet Buffer Allocation (PBA) 2443 * Writing PBA sets the receive portion of the buffer 2444 * the remainder is used for the transmit buffer. 2445 */ 2446 switch (hw->mac.type) { 2447 /* Total Packet Buffer on these is 48K */ 2448 case e1000_82571: 2449 case e1000_82572: 2450 case e1000_80003es2lan: 2451 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2452 break; 2453 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2454 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2455 break; 2456 case e1000_82574: 2457 case e1000_82583: 2458 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2459 break; 2460 case e1000_ich8lan: 2461 pba = E1000_PBA_8K; 2462 break; 2463 case e1000_ich9lan: 2464 case e1000_ich10lan: 2465 /* Boost Receive side for jumbo frames */ 2466 if (adapter->hw.mac.max_frame_size > 4096) 2467 pba = E1000_PBA_14K; 2468 else 2469 pba = E1000_PBA_10K; 2470 break; 2471 case e1000_pchlan: 2472 case e1000_pch2lan: 2473 case e1000_pch_lpt: 2474 case e1000_pch_spt: 2475 case e1000_pch_cnp: 2476 pba = E1000_PBA_26K; 2477 break; 2478 case e1000_82575: 2479 pba = E1000_PBA_32K; 2480 break; 2481 case e1000_82576: 2482 case e1000_vfadapt: 2483 pba = E1000_READ_REG(hw, E1000_RXPBS); 2484 pba &= E1000_RXPBS_SIZE_MASK_82576; 2485 break; 2486 case e1000_82580: 2487 case e1000_i350: 2488 case e1000_i354: 2489 case e1000_vfadapt_i350: 2490 pba = E1000_READ_REG(hw, E1000_RXPBS); 2491 pba = e1000_rxpbs_adjust_82580(pba); 2492 break; 2493 case e1000_i210: 2494 case e1000_i211: 2495 pba = E1000_PBA_34K; 2496 break; 2497 default: 2498 if (adapter->hw.mac.max_frame_size > 8192) 2499 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2500 else 2501 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2502 } 2503 2504 /* Special needs in case of Jumbo frames */ 2505 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2506 u32 tx_space, min_tx, min_rx; 2507 pba = E1000_READ_REG(hw, E1000_PBA); 2508 tx_space = pba >> 16; 2509 pba &= 0xffff; 2510 min_tx = (adapter->hw.mac.max_frame_size + 2511 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2512 min_tx = roundup2(min_tx, 1024); 2513 min_tx >>= 10; 2514 min_rx = adapter->hw.mac.max_frame_size; 2515 min_rx = roundup2(min_rx, 1024); 2516 min_rx >>= 10; 2517 if (tx_space < min_tx && 2518 ((min_tx - tx_space) < pba)) { 2519 pba = pba - (min_tx - tx_space); 2520 /* 2521 * if short on rx space, rx wins 2522 * and must trump tx adjustment 2523 */ 2524 if (pba < min_rx) 2525 pba = min_rx; 2526 } 2527 E1000_WRITE_REG(hw, E1000_PBA, pba); 2528 } 2529 2530 if (hw->mac.type < igb_mac_min) 2531 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2532 2533 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2534 2535 /* 2536 * These parameters control the automatic generation (Tx) and 2537 * response (Rx) to Ethernet PAUSE frames. 2538 * - High water mark should allow for at least two frames to be 2539 * received after sending an XOFF. 2540 * - Low water mark works best when it is very near the high water mark. 2541 * This allows the receiver to restart by sending XON when it has 2542 * drained a bit. Here we use an arbitrary value of 1500 which will 2543 * restart after one full frame is pulled from the buffer. There 2544 * could be several smaller frames in the buffer and if so they will 2545 * not trigger the XON until their total number reduces the buffer 2546 * by 1500. 2547 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2548 */ 2549 rx_buffer_size = (pba & 0xffff) << 10; 2550 hw->fc.high_water = rx_buffer_size - 2551 roundup2(adapter->hw.mac.max_frame_size, 1024); 2552 hw->fc.low_water = hw->fc.high_water - 1500; 2553 2554 if (adapter->fc) /* locally set flow control value? */ 2555 hw->fc.requested_mode = adapter->fc; 2556 else 2557 hw->fc.requested_mode = e1000_fc_full; 2558 2559 if (hw->mac.type == e1000_80003es2lan) 2560 hw->fc.pause_time = 0xFFFF; 2561 else 2562 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2563 2564 hw->fc.send_xon = TRUE; 2565 2566 /* Device specific overrides/settings */ 2567 switch (hw->mac.type) { 2568 case e1000_pchlan: 2569 /* Workaround: no TX flow ctrl for PCH */ 2570 hw->fc.requested_mode = e1000_fc_rx_pause; 2571 hw->fc.pause_time = 0xFFFF; /* override */ 2572 if (if_getmtu(ifp) > ETHERMTU) { 2573 hw->fc.high_water = 0x3500; 2574 hw->fc.low_water = 0x1500; 2575 } else { 2576 hw->fc.high_water = 0x5000; 2577 hw->fc.low_water = 0x3000; 2578 } 2579 hw->fc.refresh_time = 0x1000; 2580 break; 2581 case e1000_pch2lan: 2582 case e1000_pch_lpt: 2583 case e1000_pch_spt: 2584 case e1000_pch_cnp: 2585 hw->fc.high_water = 0x5C20; 2586 hw->fc.low_water = 0x5048; 2587 hw->fc.pause_time = 0x0650; 2588 hw->fc.refresh_time = 0x0400; 2589 /* Jumbos need adjusted PBA */ 2590 if (if_getmtu(ifp) > ETHERMTU) 2591 E1000_WRITE_REG(hw, E1000_PBA, 12); 2592 else 2593 E1000_WRITE_REG(hw, E1000_PBA, 26); 2594 break; 2595 case e1000_82575: 2596 case e1000_82576: 2597 /* 8-byte granularity */ 2598 hw->fc.low_water = hw->fc.high_water - 8; 2599 break; 2600 case e1000_82580: 2601 case e1000_i350: 2602 case e1000_i354: 2603 case e1000_i210: 2604 case e1000_i211: 2605 case e1000_vfadapt: 2606 case e1000_vfadapt_i350: 2607 /* 16-byte granularity */ 2608 hw->fc.low_water = hw->fc.high_water - 16; 2609 break; 2610 case e1000_ich9lan: 2611 case e1000_ich10lan: 2612 if (if_getmtu(ifp) > ETHERMTU) { 2613 hw->fc.high_water = 0x2800; 2614 hw->fc.low_water = hw->fc.high_water - 8; 2615 break; 2616 } 2617 /* FALLTHROUGH */ 2618 default: 2619 if (hw->mac.type == e1000_80003es2lan) 2620 hw->fc.pause_time = 0xFFFF; 2621 break; 2622 } 2623 2624 /* Issue a global reset */ 2625 e1000_reset_hw(hw); 2626 if (adapter->hw.mac.type >= igb_mac_min) { 2627 E1000_WRITE_REG(hw, E1000_WUC, 0); 2628 } else { 2629 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2630 em_disable_aspm(adapter); 2631 } 2632 if (adapter->flags & IGB_MEDIA_RESET) { 2633 e1000_setup_init_funcs(hw, TRUE); 2634 e1000_get_bus_info(hw); 2635 adapter->flags &= ~IGB_MEDIA_RESET; 2636 } 2637 /* and a re-init */ 2638 if (e1000_init_hw(hw) < 0) { 2639 device_printf(dev, "Hardware Initialization Failed\n"); 2640 return; 2641 } 2642 if (adapter->hw.mac.type >= igb_mac_min) 2643 igb_init_dmac(adapter, pba); 2644 2645 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2646 e1000_get_phy_info(hw); 2647 e1000_check_for_link(hw); 2648 } 2649 2650 /* 2651 * Initialise the RSS mapping for NICs that support multiple transmit/ 2652 * receive rings. 2653 */ 2654 2655 #define RSSKEYLEN 10 2656 static void 2657 em_initialize_rss_mapping(struct adapter *adapter) 2658 { 2659 uint8_t rss_key[4 * RSSKEYLEN]; 2660 uint32_t reta = 0; 2661 struct e1000_hw *hw = &adapter->hw; 2662 int i; 2663 2664 /* 2665 * Configure RSS key 2666 */ 2667 arc4rand(rss_key, sizeof(rss_key), 0); 2668 for (i = 0; i < RSSKEYLEN; ++i) { 2669 uint32_t rssrk = 0; 2670 2671 rssrk = EM_RSSRK_VAL(rss_key, i); 2672 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2673 } 2674 2675 /* 2676 * Configure RSS redirect table in following fashion: 2677 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2678 */ 2679 for (i = 0; i < sizeof(reta); ++i) { 2680 uint32_t q; 2681 2682 q = (i % adapter->rx_num_queues) << 7; 2683 reta |= q << (8 * i); 2684 } 2685 2686 for (i = 0; i < 32; ++i) 2687 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2688 2689 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2690 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2691 E1000_MRQC_RSS_FIELD_IPV4 | 2692 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2693 E1000_MRQC_RSS_FIELD_IPV6_EX | 2694 E1000_MRQC_RSS_FIELD_IPV6); 2695 } 2696 2697 static void 2698 igb_initialize_rss_mapping(struct adapter *adapter) 2699 { 2700 struct e1000_hw *hw = &adapter->hw; 2701 int i; 2702 int queue_id; 2703 u32 reta; 2704 u32 rss_key[10], mrqc, shift = 0; 2705 2706 /* XXX? */ 2707 if (adapter->hw.mac.type == e1000_82575) 2708 shift = 6; 2709 2710 /* 2711 * The redirection table controls which destination 2712 * queue each bucket redirects traffic to. 2713 * Each DWORD represents four queues, with the LSB 2714 * being the first queue in the DWORD. 2715 * 2716 * This just allocates buckets to queues using round-robin 2717 * allocation. 2718 * 2719 * NOTE: It Just Happens to line up with the default 2720 * RSS allocation method. 2721 */ 2722 2723 /* Warning FM follows */ 2724 reta = 0; 2725 for (i = 0; i < 128; i++) { 2726 #ifdef RSS 2727 queue_id = rss_get_indirection_to_bucket(i); 2728 /* 2729 * If we have more queues than buckets, we'll 2730 * end up mapping buckets to a subset of the 2731 * queues. 2732 * 2733 * If we have more buckets than queues, we'll 2734 * end up instead assigning multiple buckets 2735 * to queues. 2736 * 2737 * Both are suboptimal, but we need to handle 2738 * the case so we don't go out of bounds 2739 * indexing arrays and such. 2740 */ 2741 queue_id = queue_id % adapter->rx_num_queues; 2742 #else 2743 queue_id = (i % adapter->rx_num_queues); 2744 #endif 2745 /* Adjust if required */ 2746 queue_id = queue_id << shift; 2747 2748 /* 2749 * The low 8 bits are for hash value (n+0); 2750 * The next 8 bits are for hash value (n+1), etc. 2751 */ 2752 reta = reta >> 8; 2753 reta = reta | ( ((uint32_t) queue_id) << 24); 2754 if ((i & 3) == 3) { 2755 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2756 reta = 0; 2757 } 2758 } 2759 2760 /* Now fill in hash table */ 2761 2762 /* 2763 * MRQC: Multiple Receive Queues Command 2764 * Set queuing to RSS control, number depends on the device. 2765 */ 2766 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2767 2768 #ifdef RSS 2769 /* XXX ew typecasting */ 2770 rss_getkey((uint8_t *) &rss_key); 2771 #else 2772 arc4rand(&rss_key, sizeof(rss_key), 0); 2773 #endif 2774 for (i = 0; i < 10; i++) 2775 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2776 2777 /* 2778 * Configure the RSS fields to hash upon. 2779 */ 2780 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2781 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2782 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2783 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2784 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2785 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2786 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2787 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2788 2789 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2790 } 2791 2792 /********************************************************************* 2793 * 2794 * Setup networking device structure and register interface media. 2795 * 2796 **********************************************************************/ 2797 static int 2798 em_setup_interface(if_ctx_t ctx) 2799 { 2800 struct ifnet *ifp = iflib_get_ifp(ctx); 2801 struct adapter *adapter = iflib_get_softc(ctx); 2802 if_softc_ctx_t scctx = adapter->shared; 2803 2804 INIT_DEBUGOUT("em_setup_interface: begin"); 2805 2806 /* Single Queue */ 2807 if (adapter->tx_num_queues == 1) { 2808 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2809 if_setsendqready(ifp); 2810 } 2811 2812 /* 2813 * Specify the media types supported by this adapter and register 2814 * callbacks to update media and link information 2815 */ 2816 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2817 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2818 u_char fiber_type = IFM_1000_SX; /* default type */ 2819 2820 if (adapter->hw.mac.type == e1000_82545) 2821 fiber_type = IFM_1000_LX; 2822 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2823 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2824 } else { 2825 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2826 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2827 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2828 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2829 if (adapter->hw.phy.type != e1000_phy_ife) { 2830 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2831 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2832 } 2833 } 2834 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2835 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2836 return (0); 2837 } 2838 2839 static int 2840 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2841 { 2842 struct adapter *adapter = iflib_get_softc(ctx); 2843 if_softc_ctx_t scctx = adapter->shared; 2844 int error = E1000_SUCCESS; 2845 struct em_tx_queue *que; 2846 int i, j; 2847 2848 MPASS(adapter->tx_num_queues > 0); 2849 MPASS(adapter->tx_num_queues == ntxqsets); 2850 2851 /* First allocate the top level queue structs */ 2852 if (!(adapter->tx_queues = 2853 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2854 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2855 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2856 return(ENOMEM); 2857 } 2858 2859 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2860 /* Set up some basics */ 2861 2862 struct tx_ring *txr = &que->txr; 2863 txr->adapter = que->adapter = adapter; 2864 que->me = txr->me = i; 2865 2866 /* Allocate report status array */ 2867 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2868 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2869 error = ENOMEM; 2870 goto fail; 2871 } 2872 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2873 txr->tx_rsq[j] = QIDX_INVALID; 2874 /* get the virtual and physical address of the hardware queues */ 2875 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2876 txr->tx_paddr = paddrs[i*ntxqs]; 2877 } 2878 2879 if (bootverbose) 2880 device_printf(iflib_get_dev(ctx), 2881 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2882 return (0); 2883 fail: 2884 em_if_queues_free(ctx); 2885 return (error); 2886 } 2887 2888 static int 2889 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2890 { 2891 struct adapter *adapter = iflib_get_softc(ctx); 2892 int error = E1000_SUCCESS; 2893 struct em_rx_queue *que; 2894 int i; 2895 2896 MPASS(adapter->rx_num_queues > 0); 2897 MPASS(adapter->rx_num_queues == nrxqsets); 2898 2899 /* First allocate the top level queue structs */ 2900 if (!(adapter->rx_queues = 2901 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2902 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2903 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2904 error = ENOMEM; 2905 goto fail; 2906 } 2907 2908 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2909 /* Set up some basics */ 2910 struct rx_ring *rxr = &que->rxr; 2911 rxr->adapter = que->adapter = adapter; 2912 rxr->que = que; 2913 que->me = rxr->me = i; 2914 2915 /* get the virtual and physical address of the hardware queues */ 2916 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2917 rxr->rx_paddr = paddrs[i*nrxqs]; 2918 } 2919 2920 if (bootverbose) 2921 device_printf(iflib_get_dev(ctx), 2922 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2923 2924 return (0); 2925 fail: 2926 em_if_queues_free(ctx); 2927 return (error); 2928 } 2929 2930 static void 2931 em_if_queues_free(if_ctx_t ctx) 2932 { 2933 struct adapter *adapter = iflib_get_softc(ctx); 2934 struct em_tx_queue *tx_que = adapter->tx_queues; 2935 struct em_rx_queue *rx_que = adapter->rx_queues; 2936 2937 if (tx_que != NULL) { 2938 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2939 struct tx_ring *txr = &tx_que->txr; 2940 if (txr->tx_rsq == NULL) 2941 break; 2942 2943 free(txr->tx_rsq, M_DEVBUF); 2944 txr->tx_rsq = NULL; 2945 } 2946 free(adapter->tx_queues, M_DEVBUF); 2947 adapter->tx_queues = NULL; 2948 } 2949 2950 if (rx_que != NULL) { 2951 free(adapter->rx_queues, M_DEVBUF); 2952 adapter->rx_queues = NULL; 2953 } 2954 2955 em_release_hw_control(adapter); 2956 2957 if (adapter->mta != NULL) { 2958 free(adapter->mta, M_DEVBUF); 2959 } 2960 } 2961 2962 /********************************************************************* 2963 * 2964 * Enable transmit unit. 2965 * 2966 **********************************************************************/ 2967 static void 2968 em_initialize_transmit_unit(if_ctx_t ctx) 2969 { 2970 struct adapter *adapter = iflib_get_softc(ctx); 2971 if_softc_ctx_t scctx = adapter->shared; 2972 struct em_tx_queue *que; 2973 struct tx_ring *txr; 2974 struct e1000_hw *hw = &adapter->hw; 2975 u32 tctl, txdctl = 0, tarc, tipg = 0; 2976 2977 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2978 2979 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2980 u64 bus_addr; 2981 caddr_t offp, endp; 2982 2983 que = &adapter->tx_queues[i]; 2984 txr = &que->txr; 2985 bus_addr = txr->tx_paddr; 2986 2987 /* Clear checksum offload context. */ 2988 offp = (caddr_t)&txr->csum_flags; 2989 endp = (caddr_t)(txr + 1); 2990 bzero(offp, endp - offp); 2991 2992 /* Base and Len of TX Ring */ 2993 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2994 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2995 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2996 (u32)(bus_addr >> 32)); 2997 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2998 (u32)bus_addr); 2999 /* Init the HEAD/TAIL indices */ 3000 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3001 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3002 3003 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3004 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 3005 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 3006 3007 txdctl = 0; /* clear txdctl */ 3008 txdctl |= 0x1f; /* PTHRESH */ 3009 txdctl |= 1 << 8; /* HTHRESH */ 3010 txdctl |= 1 << 16;/* WTHRESH */ 3011 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3012 txdctl |= E1000_TXDCTL_GRAN; 3013 txdctl |= 1 << 25; /* LWTHRESH */ 3014 3015 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3016 } 3017 3018 /* Set the default values for the Tx Inter Packet Gap timer */ 3019 switch (adapter->hw.mac.type) { 3020 case e1000_80003es2lan: 3021 tipg = DEFAULT_82543_TIPG_IPGR1; 3022 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3023 E1000_TIPG_IPGR2_SHIFT; 3024 break; 3025 case e1000_82542: 3026 tipg = DEFAULT_82542_TIPG_IPGT; 3027 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3028 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3029 break; 3030 default: 3031 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3032 (adapter->hw.phy.media_type == 3033 e1000_media_type_internal_serdes)) 3034 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3035 else 3036 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3037 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3038 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3039 } 3040 3041 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3042 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3043 3044 if(adapter->hw.mac.type >= e1000_82540) 3045 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3046 adapter->tx_abs_int_delay.value); 3047 3048 if ((adapter->hw.mac.type == e1000_82571) || 3049 (adapter->hw.mac.type == e1000_82572)) { 3050 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3051 tarc |= TARC_SPEED_MODE_BIT; 3052 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3053 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3054 /* errata: program both queues to unweighted RR */ 3055 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3056 tarc |= 1; 3057 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3058 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3059 tarc |= 1; 3060 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3061 } else if (adapter->hw.mac.type == e1000_82574) { 3062 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3063 tarc |= TARC_ERRATA_BIT; 3064 if ( adapter->tx_num_queues > 1) { 3065 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3066 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3067 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3068 } else 3069 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3070 } 3071 3072 if (adapter->tx_int_delay.value > 0) 3073 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3074 3075 /* Program the Transmit Control Register */ 3076 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3077 tctl &= ~E1000_TCTL_CT; 3078 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3079 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3080 3081 if (adapter->hw.mac.type >= e1000_82571) 3082 tctl |= E1000_TCTL_MULR; 3083 3084 /* This write will effectively turn on the transmit unit. */ 3085 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3086 3087 /* SPT and KBL errata workarounds */ 3088 if (hw->mac.type == e1000_pch_spt) { 3089 u32 reg; 3090 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3091 reg |= E1000_RCTL_RDMTS_HEX; 3092 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3093 /* i218-i219 Specification Update 1.5.4.5 */ 3094 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3095 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3096 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3097 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3098 } 3099 } 3100 3101 /********************************************************************* 3102 * 3103 * Enable receive unit. 3104 * 3105 **********************************************************************/ 3106 3107 static void 3108 em_initialize_receive_unit(if_ctx_t ctx) 3109 { 3110 struct adapter *adapter = iflib_get_softc(ctx); 3111 if_softc_ctx_t scctx = adapter->shared; 3112 struct ifnet *ifp = iflib_get_ifp(ctx); 3113 struct e1000_hw *hw = &adapter->hw; 3114 struct em_rx_queue *que; 3115 int i; 3116 u32 rctl, rxcsum, rfctl; 3117 3118 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3119 3120 /* 3121 * Make sure receives are disabled while setting 3122 * up the descriptor ring 3123 */ 3124 rctl = E1000_READ_REG(hw, E1000_RCTL); 3125 /* Do not disable if ever enabled on this hardware */ 3126 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3127 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3128 3129 /* Setup the Receive Control Register */ 3130 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3131 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3132 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3133 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3134 3135 /* Do not store bad packets */ 3136 rctl &= ~E1000_RCTL_SBP; 3137 3138 /* Enable Long Packet receive */ 3139 if (if_getmtu(ifp) > ETHERMTU) 3140 rctl |= E1000_RCTL_LPE; 3141 else 3142 rctl &= ~E1000_RCTL_LPE; 3143 3144 /* Strip the CRC */ 3145 if (!em_disable_crc_stripping) 3146 rctl |= E1000_RCTL_SECRC; 3147 3148 if (adapter->hw.mac.type >= e1000_82540) { 3149 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3150 adapter->rx_abs_int_delay.value); 3151 3152 /* 3153 * Set the interrupt throttling rate. Value is calculated 3154 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3155 */ 3156 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3157 } 3158 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3159 adapter->rx_int_delay.value); 3160 3161 /* Use extended rx descriptor formats */ 3162 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3163 rfctl |= E1000_RFCTL_EXTEN; 3164 /* 3165 * When using MSI-X interrupts we need to throttle 3166 * using the EITR register (82574 only) 3167 */ 3168 if (hw->mac.type == e1000_82574) { 3169 for (int i = 0; i < 4; i++) 3170 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3171 DEFAULT_ITR); 3172 /* Disable accelerated acknowledge */ 3173 rfctl |= E1000_RFCTL_ACK_DIS; 3174 } 3175 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3176 3177 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3178 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3179 adapter->hw.mac.type >= e1000_82543) { 3180 if (adapter->tx_num_queues > 1) { 3181 if (adapter->hw.mac.type >= igb_mac_min) { 3182 rxcsum |= E1000_RXCSUM_PCSD; 3183 if (hw->mac.type != e1000_82575) 3184 rxcsum |= E1000_RXCSUM_CRCOFL; 3185 } else 3186 rxcsum |= E1000_RXCSUM_TUOFL | 3187 E1000_RXCSUM_IPOFL | 3188 E1000_RXCSUM_PCSD; 3189 } else { 3190 if (adapter->hw.mac.type >= igb_mac_min) 3191 rxcsum |= E1000_RXCSUM_IPPCSE; 3192 else 3193 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3194 if (adapter->hw.mac.type > e1000_82575) 3195 rxcsum |= E1000_RXCSUM_CRCOFL; 3196 } 3197 } else 3198 rxcsum &= ~E1000_RXCSUM_TUOFL; 3199 3200 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3201 3202 if (adapter->rx_num_queues > 1) { 3203 if (adapter->hw.mac.type >= igb_mac_min) 3204 igb_initialize_rss_mapping(adapter); 3205 else 3206 em_initialize_rss_mapping(adapter); 3207 } 3208 3209 /* 3210 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3211 * long latencies are observed, like Lenovo X60. This 3212 * change eliminates the problem, but since having positive 3213 * values in RDTR is a known source of problems on other 3214 * platforms another solution is being sought. 3215 */ 3216 if (hw->mac.type == e1000_82573) 3217 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3218 3219 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3220 struct rx_ring *rxr = &que->rxr; 3221 /* Setup the Base and Length of the Rx Descriptor Ring */ 3222 u64 bus_addr = rxr->rx_paddr; 3223 #if 0 3224 u32 rdt = adapter->rx_num_queues -1; /* default */ 3225 #endif 3226 3227 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3228 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3229 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3230 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3231 /* Setup the Head and Tail Descriptor Pointers */ 3232 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3233 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3234 } 3235 3236 /* 3237 * Set PTHRESH for improved jumbo performance 3238 * According to 10.2.5.11 of Intel 82574 Datasheet, 3239 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3240 * Only write to RXDCTL(1) if there is a need for different 3241 * settings. 3242 */ 3243 3244 if (((adapter->hw.mac.type == e1000_ich9lan) || 3245 (adapter->hw.mac.type == e1000_pch2lan) || 3246 (adapter->hw.mac.type == e1000_ich10lan)) && 3247 (if_getmtu(ifp) > ETHERMTU)) { 3248 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3249 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3250 } else if (adapter->hw.mac.type == e1000_82574) { 3251 for (int i = 0; i < adapter->rx_num_queues; i++) { 3252 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3253 rxdctl |= 0x20; /* PTHRESH */ 3254 rxdctl |= 4 << 8; /* HTHRESH */ 3255 rxdctl |= 4 << 16;/* WTHRESH */ 3256 rxdctl |= 1 << 24; /* Switch to granularity */ 3257 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3258 } 3259 } else if (adapter->hw.mac.type >= igb_mac_min) { 3260 u32 psize, srrctl = 0; 3261 3262 if (if_getmtu(ifp) > ETHERMTU) { 3263 /* Set maximum packet len */ 3264 if (adapter->rx_mbuf_sz <= 4096) { 3265 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3266 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3267 } else if (adapter->rx_mbuf_sz > 4096) { 3268 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3269 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3270 } 3271 psize = scctx->isc_max_frame_size; 3272 /* are we on a vlan? */ 3273 if (ifp->if_vlantrunk != NULL) 3274 psize += VLAN_TAG_SIZE; 3275 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3276 } else { 3277 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3278 rctl |= E1000_RCTL_SZ_2048; 3279 } 3280 3281 /* 3282 * If TX flow control is disabled and there's >1 queue defined, 3283 * enable DROP. 3284 * 3285 * This drops frames rather than hanging the RX MAC for all queues. 3286 */ 3287 if ((adapter->rx_num_queues > 1) && 3288 (adapter->fc == e1000_fc_none || 3289 adapter->fc == e1000_fc_rx_pause)) { 3290 srrctl |= E1000_SRRCTL_DROP_EN; 3291 } 3292 /* Setup the Base and Length of the Rx Descriptor Rings */ 3293 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3294 struct rx_ring *rxr = &que->rxr; 3295 u64 bus_addr = rxr->rx_paddr; 3296 u32 rxdctl; 3297 3298 #ifdef notyet 3299 /* Configure for header split? -- ignore for now */ 3300 rxr->hdr_split = igb_header_split; 3301 #else 3302 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3303 #endif 3304 3305 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3306 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3307 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3308 (uint32_t)(bus_addr >> 32)); 3309 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3310 (uint32_t)bus_addr); 3311 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3312 /* Enable this Queue */ 3313 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3314 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3315 rxdctl &= 0xFFF00000; 3316 rxdctl |= IGB_RX_PTHRESH; 3317 rxdctl |= IGB_RX_HTHRESH << 8; 3318 rxdctl |= IGB_RX_WTHRESH << 16; 3319 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3320 } 3321 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3322 if (if_getmtu(ifp) > ETHERMTU) 3323 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3324 else 3325 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3326 } 3327 3328 /* Make sure VLAN Filters are off */ 3329 rctl &= ~E1000_RCTL_VFE; 3330 3331 if (adapter->hw.mac.type < igb_mac_min) { 3332 if (adapter->rx_mbuf_sz == MCLBYTES) 3333 rctl |= E1000_RCTL_SZ_2048; 3334 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3335 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3336 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3337 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3338 3339 /* ensure we clear use DTYPE of 00 here */ 3340 rctl &= ~0x00000C00; 3341 } 3342 3343 /* Write out the settings */ 3344 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3345 3346 return; 3347 } 3348 3349 static void 3350 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3351 { 3352 struct adapter *adapter = iflib_get_softc(ctx); 3353 u32 index, bit; 3354 3355 index = (vtag >> 5) & 0x7F; 3356 bit = vtag & 0x1F; 3357 adapter->shadow_vfta[index] |= (1 << bit); 3358 ++adapter->num_vlans; 3359 } 3360 3361 static void 3362 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3363 { 3364 struct adapter *adapter = iflib_get_softc(ctx); 3365 u32 index, bit; 3366 3367 index = (vtag >> 5) & 0x7F; 3368 bit = vtag & 0x1F; 3369 adapter->shadow_vfta[index] &= ~(1 << bit); 3370 --adapter->num_vlans; 3371 } 3372 3373 static void 3374 em_setup_vlan_hw_support(struct adapter *adapter) 3375 { 3376 struct e1000_hw *hw = &adapter->hw; 3377 u32 reg; 3378 3379 /* 3380 * We get here thru init_locked, meaning 3381 * a soft reset, this has already cleared 3382 * the VFTA and other state, so if there 3383 * have been no vlan's registered do nothing. 3384 */ 3385 if (adapter->num_vlans == 0) 3386 return; 3387 3388 /* 3389 * A soft reset zero's out the VFTA, so 3390 * we need to repopulate it now. 3391 */ 3392 for (int i = 0; i < EM_VFTA_SIZE; i++) 3393 if (adapter->shadow_vfta[i] != 0) 3394 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3395 i, adapter->shadow_vfta[i]); 3396 3397 reg = E1000_READ_REG(hw, E1000_CTRL); 3398 reg |= E1000_CTRL_VME; 3399 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3400 3401 /* Enable the Filter Table */ 3402 reg = E1000_READ_REG(hw, E1000_RCTL); 3403 reg &= ~E1000_RCTL_CFIEN; 3404 reg |= E1000_RCTL_VFE; 3405 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3406 } 3407 3408 static void 3409 em_if_intr_enable(if_ctx_t ctx) 3410 { 3411 struct adapter *adapter = iflib_get_softc(ctx); 3412 struct e1000_hw *hw = &adapter->hw; 3413 u32 ims_mask = IMS_ENABLE_MASK; 3414 3415 if (hw->mac.type == e1000_82574) { 3416 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3417 ims_mask |= adapter->ims; 3418 } 3419 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3420 } 3421 3422 static void 3423 em_if_intr_disable(if_ctx_t ctx) 3424 { 3425 struct adapter *adapter = iflib_get_softc(ctx); 3426 struct e1000_hw *hw = &adapter->hw; 3427 3428 if (hw->mac.type == e1000_82574) 3429 E1000_WRITE_REG(hw, EM_EIAC, 0); 3430 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3431 } 3432 3433 static void 3434 igb_if_intr_enable(if_ctx_t ctx) 3435 { 3436 struct adapter *adapter = iflib_get_softc(ctx); 3437 struct e1000_hw *hw = &adapter->hw; 3438 u32 mask; 3439 3440 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3441 mask = (adapter->que_mask | adapter->link_mask); 3442 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3443 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3444 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3445 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3446 } else 3447 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3448 E1000_WRITE_FLUSH(hw); 3449 } 3450 3451 static void 3452 igb_if_intr_disable(if_ctx_t ctx) 3453 { 3454 struct adapter *adapter = iflib_get_softc(ctx); 3455 struct e1000_hw *hw = &adapter->hw; 3456 3457 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3458 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3459 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3460 } 3461 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3462 E1000_WRITE_FLUSH(hw); 3463 } 3464 3465 /* 3466 * Bit of a misnomer, what this really means is 3467 * to enable OS management of the system... aka 3468 * to disable special hardware management features 3469 */ 3470 static void 3471 em_init_manageability(struct adapter *adapter) 3472 { 3473 /* A shared code workaround */ 3474 #define E1000_82542_MANC2H E1000_MANC2H 3475 if (adapter->has_manage) { 3476 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3477 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3478 3479 /* disable hardware interception of ARP */ 3480 manc &= ~(E1000_MANC_ARP_EN); 3481 3482 /* enable receiving management packets to the host */ 3483 manc |= E1000_MANC_EN_MNG2HOST; 3484 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3485 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3486 manc2h |= E1000_MNG2HOST_PORT_623; 3487 manc2h |= E1000_MNG2HOST_PORT_664; 3488 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3489 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3490 } 3491 } 3492 3493 /* 3494 * Give control back to hardware management 3495 * controller if there is one. 3496 */ 3497 static void 3498 em_release_manageability(struct adapter *adapter) 3499 { 3500 if (adapter->has_manage) { 3501 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3502 3503 /* re-enable hardware interception of ARP */ 3504 manc |= E1000_MANC_ARP_EN; 3505 manc &= ~E1000_MANC_EN_MNG2HOST; 3506 3507 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3508 } 3509 } 3510 3511 /* 3512 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3513 * For ASF and Pass Through versions of f/w this means 3514 * that the driver is loaded. For AMT version type f/w 3515 * this means that the network i/f is open. 3516 */ 3517 static void 3518 em_get_hw_control(struct adapter *adapter) 3519 { 3520 u32 ctrl_ext, swsm; 3521 3522 if (adapter->vf_ifp) 3523 return; 3524 3525 if (adapter->hw.mac.type == e1000_82573) { 3526 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3527 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3528 swsm | E1000_SWSM_DRV_LOAD); 3529 return; 3530 } 3531 /* else */ 3532 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3533 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3534 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3535 } 3536 3537 /* 3538 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3539 * For ASF and Pass Through versions of f/w this means that 3540 * the driver is no longer loaded. For AMT versions of the 3541 * f/w this means that the network i/f is closed. 3542 */ 3543 static void 3544 em_release_hw_control(struct adapter *adapter) 3545 { 3546 u32 ctrl_ext, swsm; 3547 3548 if (!adapter->has_manage) 3549 return; 3550 3551 if (adapter->hw.mac.type == e1000_82573) { 3552 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3553 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3554 swsm & ~E1000_SWSM_DRV_LOAD); 3555 return; 3556 } 3557 /* else */ 3558 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3559 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3560 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3561 return; 3562 } 3563 3564 static int 3565 em_is_valid_ether_addr(u8 *addr) 3566 { 3567 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3568 3569 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3570 return (FALSE); 3571 } 3572 3573 return (TRUE); 3574 } 3575 3576 /* 3577 ** Parse the interface capabilities with regard 3578 ** to both system management and wake-on-lan for 3579 ** later use. 3580 */ 3581 static void 3582 em_get_wakeup(if_ctx_t ctx) 3583 { 3584 struct adapter *adapter = iflib_get_softc(ctx); 3585 device_t dev = iflib_get_dev(ctx); 3586 u16 eeprom_data = 0, device_id, apme_mask; 3587 3588 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3589 apme_mask = EM_EEPROM_APME; 3590 3591 switch (adapter->hw.mac.type) { 3592 case e1000_82542: 3593 case e1000_82543: 3594 break; 3595 case e1000_82544: 3596 e1000_read_nvm(&adapter->hw, 3597 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3598 apme_mask = EM_82544_APME; 3599 break; 3600 case e1000_82546: 3601 case e1000_82546_rev_3: 3602 if (adapter->hw.bus.func == 1) { 3603 e1000_read_nvm(&adapter->hw, 3604 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3605 break; 3606 } else 3607 e1000_read_nvm(&adapter->hw, 3608 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3609 break; 3610 case e1000_82573: 3611 case e1000_82583: 3612 adapter->has_amt = TRUE; 3613 /* FALLTHROUGH */ 3614 case e1000_82571: 3615 case e1000_82572: 3616 case e1000_80003es2lan: 3617 if (adapter->hw.bus.func == 1) { 3618 e1000_read_nvm(&adapter->hw, 3619 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3620 break; 3621 } else 3622 e1000_read_nvm(&adapter->hw, 3623 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3624 break; 3625 case e1000_ich8lan: 3626 case e1000_ich9lan: 3627 case e1000_ich10lan: 3628 case e1000_pchlan: 3629 case e1000_pch2lan: 3630 case e1000_pch_lpt: 3631 case e1000_pch_spt: 3632 case e1000_82575: /* listing all igb devices */ 3633 case e1000_82576: 3634 case e1000_82580: 3635 case e1000_i350: 3636 case e1000_i354: 3637 case e1000_i210: 3638 case e1000_i211: 3639 case e1000_vfadapt: 3640 case e1000_vfadapt_i350: 3641 apme_mask = E1000_WUC_APME; 3642 adapter->has_amt = TRUE; 3643 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3644 break; 3645 default: 3646 e1000_read_nvm(&adapter->hw, 3647 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3648 break; 3649 } 3650 if (eeprom_data & apme_mask) 3651 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3652 /* 3653 * We have the eeprom settings, now apply the special cases 3654 * where the eeprom may be wrong or the board won't support 3655 * wake on lan on a particular port 3656 */ 3657 device_id = pci_get_device(dev); 3658 switch (device_id) { 3659 case E1000_DEV_ID_82546GB_PCIE: 3660 adapter->wol = 0; 3661 break; 3662 case E1000_DEV_ID_82546EB_FIBER: 3663 case E1000_DEV_ID_82546GB_FIBER: 3664 /* Wake events only supported on port A for dual fiber 3665 * regardless of eeprom setting */ 3666 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3667 E1000_STATUS_FUNC_1) 3668 adapter->wol = 0; 3669 break; 3670 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3671 /* if quad port adapter, disable WoL on all but port A */ 3672 if (global_quad_port_a != 0) 3673 adapter->wol = 0; 3674 /* Reset for multiple quad port adapters */ 3675 if (++global_quad_port_a == 4) 3676 global_quad_port_a = 0; 3677 break; 3678 case E1000_DEV_ID_82571EB_FIBER: 3679 /* Wake events only supported on port A for dual fiber 3680 * regardless of eeprom setting */ 3681 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3682 E1000_STATUS_FUNC_1) 3683 adapter->wol = 0; 3684 break; 3685 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3686 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3687 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3688 /* if quad port adapter, disable WoL on all but port A */ 3689 if (global_quad_port_a != 0) 3690 adapter->wol = 0; 3691 /* Reset for multiple quad port adapters */ 3692 if (++global_quad_port_a == 4) 3693 global_quad_port_a = 0; 3694 break; 3695 } 3696 return; 3697 } 3698 3699 3700 /* 3701 * Enable PCI Wake On Lan capability 3702 */ 3703 static void 3704 em_enable_wakeup(if_ctx_t ctx) 3705 { 3706 struct adapter *adapter = iflib_get_softc(ctx); 3707 device_t dev = iflib_get_dev(ctx); 3708 if_t ifp = iflib_get_ifp(ctx); 3709 int error = 0; 3710 u32 pmc, ctrl, ctrl_ext, rctl; 3711 u16 status; 3712 3713 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3714 return; 3715 3716 /* 3717 * Determine type of Wakeup: note that wol 3718 * is set with all bits on by default. 3719 */ 3720 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3721 adapter->wol &= ~E1000_WUFC_MAG; 3722 3723 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3724 adapter->wol &= ~E1000_WUFC_EX; 3725 3726 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3727 adapter->wol &= ~E1000_WUFC_MC; 3728 else { 3729 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3730 rctl |= E1000_RCTL_MPE; 3731 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3732 } 3733 3734 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3735 goto pme; 3736 3737 /* Advertise the wakeup capability */ 3738 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3739 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3740 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3741 3742 /* Keep the laser running on Fiber adapters */ 3743 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3744 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3745 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3746 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3747 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3748 } 3749 3750 if ((adapter->hw.mac.type == e1000_ich8lan) || 3751 (adapter->hw.mac.type == e1000_pchlan) || 3752 (adapter->hw.mac.type == e1000_ich9lan) || 3753 (adapter->hw.mac.type == e1000_ich10lan)) 3754 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3755 3756 if ( adapter->hw.mac.type >= e1000_pchlan) { 3757 error = em_enable_phy_wakeup(adapter); 3758 if (error) 3759 goto pme; 3760 } else { 3761 /* Enable wakeup by the MAC */ 3762 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3763 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3764 } 3765 3766 if (adapter->hw.phy.type == e1000_phy_igp_3) 3767 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3768 3769 pme: 3770 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3771 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3772 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3773 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3774 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3775 3776 return; 3777 } 3778 3779 /* 3780 * WOL in the newer chipset interfaces (pchlan) 3781 * require thing to be copied into the phy 3782 */ 3783 static int 3784 em_enable_phy_wakeup(struct adapter *adapter) 3785 { 3786 struct e1000_hw *hw = &adapter->hw; 3787 u32 mreg, ret = 0; 3788 u16 preg; 3789 3790 /* copy MAC RARs to PHY RARs */ 3791 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3792 3793 /* copy MAC MTA to PHY MTA */ 3794 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3795 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3796 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3797 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3798 (u16)((mreg >> 16) & 0xFFFF)); 3799 } 3800 3801 /* configure PHY Rx Control register */ 3802 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3803 mreg = E1000_READ_REG(hw, E1000_RCTL); 3804 if (mreg & E1000_RCTL_UPE) 3805 preg |= BM_RCTL_UPE; 3806 if (mreg & E1000_RCTL_MPE) 3807 preg |= BM_RCTL_MPE; 3808 preg &= ~(BM_RCTL_MO_MASK); 3809 if (mreg & E1000_RCTL_MO_3) 3810 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3811 << BM_RCTL_MO_SHIFT); 3812 if (mreg & E1000_RCTL_BAM) 3813 preg |= BM_RCTL_BAM; 3814 if (mreg & E1000_RCTL_PMCF) 3815 preg |= BM_RCTL_PMCF; 3816 mreg = E1000_READ_REG(hw, E1000_CTRL); 3817 if (mreg & E1000_CTRL_RFCE) 3818 preg |= BM_RCTL_RFCE; 3819 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3820 3821 /* enable PHY wakeup in MAC register */ 3822 E1000_WRITE_REG(hw, E1000_WUC, 3823 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3824 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3825 3826 /* configure and enable PHY wakeup in PHY registers */ 3827 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3828 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3829 3830 /* activate PHY wakeup */ 3831 ret = hw->phy.ops.acquire(hw); 3832 if (ret) { 3833 printf("Could not acquire PHY\n"); 3834 return ret; 3835 } 3836 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3837 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3838 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3839 if (ret) { 3840 printf("Could not read PHY page 769\n"); 3841 goto out; 3842 } 3843 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3844 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3845 if (ret) 3846 printf("Could not set PHY Host Wakeup bit\n"); 3847 out: 3848 hw->phy.ops.release(hw); 3849 3850 return ret; 3851 } 3852 3853 static void 3854 em_if_led_func(if_ctx_t ctx, int onoff) 3855 { 3856 struct adapter *adapter = iflib_get_softc(ctx); 3857 3858 if (onoff) { 3859 e1000_setup_led(&adapter->hw); 3860 e1000_led_on(&adapter->hw); 3861 } else { 3862 e1000_led_off(&adapter->hw); 3863 e1000_cleanup_led(&adapter->hw); 3864 } 3865 } 3866 3867 /* 3868 * Disable the L0S and L1 LINK states 3869 */ 3870 static void 3871 em_disable_aspm(struct adapter *adapter) 3872 { 3873 int base, reg; 3874 u16 link_cap,link_ctrl; 3875 device_t dev = adapter->dev; 3876 3877 switch (adapter->hw.mac.type) { 3878 case e1000_82573: 3879 case e1000_82574: 3880 case e1000_82583: 3881 break; 3882 default: 3883 return; 3884 } 3885 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3886 return; 3887 reg = base + PCIER_LINK_CAP; 3888 link_cap = pci_read_config(dev, reg, 2); 3889 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3890 return; 3891 reg = base + PCIER_LINK_CTL; 3892 link_ctrl = pci_read_config(dev, reg, 2); 3893 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3894 pci_write_config(dev, reg, link_ctrl, 2); 3895 return; 3896 } 3897 3898 /********************************************************************** 3899 * 3900 * Update the board statistics counters. 3901 * 3902 **********************************************************************/ 3903 static void 3904 em_update_stats_counters(struct adapter *adapter) 3905 { 3906 3907 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3908 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3909 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3910 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3911 } 3912 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3913 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3914 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3915 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3916 3917 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3918 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3919 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3920 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3921 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3922 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3923 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3924 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3925 /* 3926 ** For watchdog management we need to know if we have been 3927 ** paused during the last interval, so capture that here. 3928 */ 3929 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3930 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3931 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3932 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3933 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3934 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3935 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3936 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3937 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3938 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3939 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3940 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3941 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3942 3943 /* For the 64-bit byte counters the low dword must be read first. */ 3944 /* Both registers clear on the read of the high dword */ 3945 3946 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3947 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3948 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3949 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3950 3951 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3952 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3953 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3954 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3955 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3956 3957 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3958 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3959 3960 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3961 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3962 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3963 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3964 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3965 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3966 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3967 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3968 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3969 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3970 3971 /* Interrupt Counts */ 3972 3973 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3974 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3975 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3976 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3977 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3978 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3979 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3980 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3981 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3982 3983 if (adapter->hw.mac.type >= e1000_82543) { 3984 adapter->stats.algnerrc += 3985 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3986 adapter->stats.rxerrc += 3987 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3988 adapter->stats.tncrs += 3989 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3990 adapter->stats.cexterr += 3991 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3992 adapter->stats.tsctc += 3993 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3994 adapter->stats.tsctfc += 3995 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3996 } 3997 } 3998 3999 static uint64_t 4000 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4001 { 4002 struct adapter *adapter = iflib_get_softc(ctx); 4003 struct ifnet *ifp = iflib_get_ifp(ctx); 4004 4005 switch (cnt) { 4006 case IFCOUNTER_COLLISIONS: 4007 return (adapter->stats.colc); 4008 case IFCOUNTER_IERRORS: 4009 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4010 adapter->stats.crcerrs + adapter->stats.algnerrc + 4011 adapter->stats.ruc + adapter->stats.roc + 4012 adapter->stats.mpc + adapter->stats.cexterr); 4013 case IFCOUNTER_OERRORS: 4014 return (adapter->stats.ecol + adapter->stats.latecol + 4015 adapter->watchdog_events); 4016 default: 4017 return (if_get_counter_default(ifp, cnt)); 4018 } 4019 } 4020 4021 /* Export a single 32-bit register via a read-only sysctl. */ 4022 static int 4023 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4024 { 4025 struct adapter *adapter; 4026 u_int val; 4027 4028 adapter = oidp->oid_arg1; 4029 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4030 return (sysctl_handle_int(oidp, &val, 0, req)); 4031 } 4032 4033 /* 4034 * Add sysctl variables, one per statistic, to the system. 4035 */ 4036 static void 4037 em_add_hw_stats(struct adapter *adapter) 4038 { 4039 device_t dev = iflib_get_dev(adapter->ctx); 4040 struct em_tx_queue *tx_que = adapter->tx_queues; 4041 struct em_rx_queue *rx_que = adapter->rx_queues; 4042 4043 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4044 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4045 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4046 struct e1000_hw_stats *stats = &adapter->stats; 4047 4048 struct sysctl_oid *stat_node, *queue_node, *int_node; 4049 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4050 4051 #define QUEUE_NAME_LEN 32 4052 char namebuf[QUEUE_NAME_LEN]; 4053 4054 /* Driver Statistics */ 4055 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4056 CTLFLAG_RD, &adapter->dropped_pkts, 4057 "Driver dropped packets"); 4058 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4059 CTLFLAG_RD, &adapter->link_irq, 4060 "Link MSI-X IRQ Handled"); 4061 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4062 CTLFLAG_RD, &adapter->rx_overruns, 4063 "RX overruns"); 4064 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4065 CTLFLAG_RD, &adapter->watchdog_events, 4066 "Watchdog timeouts"); 4067 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4068 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4069 em_sysctl_reg_handler, "IU", 4070 "Device Control Register"); 4071 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4072 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4073 em_sysctl_reg_handler, "IU", 4074 "Receiver Control Register"); 4075 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4076 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4077 "Flow Control High Watermark"); 4078 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4079 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4080 "Flow Control Low Watermark"); 4081 4082 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4083 struct tx_ring *txr = &tx_que->txr; 4084 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4085 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4086 CTLFLAG_RD, NULL, "TX Queue Name"); 4087 queue_list = SYSCTL_CHILDREN(queue_node); 4088 4089 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4090 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4091 E1000_TDH(txr->me), 4092 em_sysctl_reg_handler, "IU", 4093 "Transmit Descriptor Head"); 4094 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4095 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4096 E1000_TDT(txr->me), 4097 em_sysctl_reg_handler, "IU", 4098 "Transmit Descriptor Tail"); 4099 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4100 CTLFLAG_RD, &txr->tx_irq, 4101 "Queue MSI-X Transmit Interrupts"); 4102 } 4103 4104 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4105 struct rx_ring *rxr = &rx_que->rxr; 4106 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4107 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4108 CTLFLAG_RD, NULL, "RX Queue Name"); 4109 queue_list = SYSCTL_CHILDREN(queue_node); 4110 4111 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4112 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4113 E1000_RDH(rxr->me), 4114 em_sysctl_reg_handler, "IU", 4115 "Receive Descriptor Head"); 4116 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4117 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4118 E1000_RDT(rxr->me), 4119 em_sysctl_reg_handler, "IU", 4120 "Receive Descriptor Tail"); 4121 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4122 CTLFLAG_RD, &rxr->rx_irq, 4123 "Queue MSI-X Receive Interrupts"); 4124 } 4125 4126 /* MAC stats get their own sub node */ 4127 4128 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4129 CTLFLAG_RD, NULL, "Statistics"); 4130 stat_list = SYSCTL_CHILDREN(stat_node); 4131 4132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4133 CTLFLAG_RD, &stats->ecol, 4134 "Excessive collisions"); 4135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4136 CTLFLAG_RD, &stats->scc, 4137 "Single collisions"); 4138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4139 CTLFLAG_RD, &stats->mcc, 4140 "Multiple collisions"); 4141 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4142 CTLFLAG_RD, &stats->latecol, 4143 "Late collisions"); 4144 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4145 CTLFLAG_RD, &stats->colc, 4146 "Collision Count"); 4147 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4148 CTLFLAG_RD, &adapter->stats.symerrs, 4149 "Symbol Errors"); 4150 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4151 CTLFLAG_RD, &adapter->stats.sec, 4152 "Sequence Errors"); 4153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4154 CTLFLAG_RD, &adapter->stats.dc, 4155 "Defer Count"); 4156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4157 CTLFLAG_RD, &adapter->stats.mpc, 4158 "Missed Packets"); 4159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4160 CTLFLAG_RD, &adapter->stats.rnbc, 4161 "Receive No Buffers"); 4162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4163 CTLFLAG_RD, &adapter->stats.ruc, 4164 "Receive Undersize"); 4165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4166 CTLFLAG_RD, &adapter->stats.rfc, 4167 "Fragmented Packets Received "); 4168 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4169 CTLFLAG_RD, &adapter->stats.roc, 4170 "Oversized Packets Received"); 4171 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4172 CTLFLAG_RD, &adapter->stats.rjc, 4173 "Recevied Jabber"); 4174 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4175 CTLFLAG_RD, &adapter->stats.rxerrc, 4176 "Receive Errors"); 4177 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4178 CTLFLAG_RD, &adapter->stats.crcerrs, 4179 "CRC errors"); 4180 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4181 CTLFLAG_RD, &adapter->stats.algnerrc, 4182 "Alignment Errors"); 4183 /* On 82575 these are collision counts */ 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4185 CTLFLAG_RD, &adapter->stats.cexterr, 4186 "Collision/Carrier extension errors"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4188 CTLFLAG_RD, &adapter->stats.xonrxc, 4189 "XON Received"); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4191 CTLFLAG_RD, &adapter->stats.xontxc, 4192 "XON Transmitted"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4194 CTLFLAG_RD, &adapter->stats.xoffrxc, 4195 "XOFF Received"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4197 CTLFLAG_RD, &adapter->stats.xofftxc, 4198 "XOFF Transmitted"); 4199 4200 /* Packet Reception Stats */ 4201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4202 CTLFLAG_RD, &adapter->stats.tpr, 4203 "Total Packets Received "); 4204 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4205 CTLFLAG_RD, &adapter->stats.gprc, 4206 "Good Packets Received"); 4207 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4208 CTLFLAG_RD, &adapter->stats.bprc, 4209 "Broadcast Packets Received"); 4210 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4211 CTLFLAG_RD, &adapter->stats.mprc, 4212 "Multicast Packets Received"); 4213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4214 CTLFLAG_RD, &adapter->stats.prc64, 4215 "64 byte frames received "); 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4217 CTLFLAG_RD, &adapter->stats.prc127, 4218 "65-127 byte frames received"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4220 CTLFLAG_RD, &adapter->stats.prc255, 4221 "128-255 byte frames received"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4223 CTLFLAG_RD, &adapter->stats.prc511, 4224 "256-511 byte frames received"); 4225 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4226 CTLFLAG_RD, &adapter->stats.prc1023, 4227 "512-1023 byte frames received"); 4228 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4229 CTLFLAG_RD, &adapter->stats.prc1522, 4230 "1023-1522 byte frames received"); 4231 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4232 CTLFLAG_RD, &adapter->stats.gorc, 4233 "Good Octets Received"); 4234 4235 /* Packet Transmission Stats */ 4236 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4237 CTLFLAG_RD, &adapter->stats.gotc, 4238 "Good Octets Transmitted"); 4239 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4240 CTLFLAG_RD, &adapter->stats.tpt, 4241 "Total Packets Transmitted"); 4242 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4243 CTLFLAG_RD, &adapter->stats.gptc, 4244 "Good Packets Transmitted"); 4245 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4246 CTLFLAG_RD, &adapter->stats.bptc, 4247 "Broadcast Packets Transmitted"); 4248 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4249 CTLFLAG_RD, &adapter->stats.mptc, 4250 "Multicast Packets Transmitted"); 4251 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4252 CTLFLAG_RD, &adapter->stats.ptc64, 4253 "64 byte frames transmitted "); 4254 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4255 CTLFLAG_RD, &adapter->stats.ptc127, 4256 "65-127 byte frames transmitted"); 4257 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4258 CTLFLAG_RD, &adapter->stats.ptc255, 4259 "128-255 byte frames transmitted"); 4260 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4261 CTLFLAG_RD, &adapter->stats.ptc511, 4262 "256-511 byte frames transmitted"); 4263 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4264 CTLFLAG_RD, &adapter->stats.ptc1023, 4265 "512-1023 byte frames transmitted"); 4266 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4267 CTLFLAG_RD, &adapter->stats.ptc1522, 4268 "1024-1522 byte frames transmitted"); 4269 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4270 CTLFLAG_RD, &adapter->stats.tsctc, 4271 "TSO Contexts Transmitted"); 4272 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4273 CTLFLAG_RD, &adapter->stats.tsctfc, 4274 "TSO Contexts Failed"); 4275 4276 4277 /* Interrupt Stats */ 4278 4279 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4280 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4281 int_list = SYSCTL_CHILDREN(int_node); 4282 4283 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4284 CTLFLAG_RD, &adapter->stats.iac, 4285 "Interrupt Assertion Count"); 4286 4287 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4288 CTLFLAG_RD, &adapter->stats.icrxptc, 4289 "Interrupt Cause Rx Pkt Timer Expire Count"); 4290 4291 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4292 CTLFLAG_RD, &adapter->stats.icrxatc, 4293 "Interrupt Cause Rx Abs Timer Expire Count"); 4294 4295 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4296 CTLFLAG_RD, &adapter->stats.ictxptc, 4297 "Interrupt Cause Tx Pkt Timer Expire Count"); 4298 4299 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4300 CTLFLAG_RD, &adapter->stats.ictxatc, 4301 "Interrupt Cause Tx Abs Timer Expire Count"); 4302 4303 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4304 CTLFLAG_RD, &adapter->stats.ictxqec, 4305 "Interrupt Cause Tx Queue Empty Count"); 4306 4307 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4308 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4309 "Interrupt Cause Tx Queue Min Thresh Count"); 4310 4311 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4312 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4313 "Interrupt Cause Rx Desc Min Thresh Count"); 4314 4315 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4316 CTLFLAG_RD, &adapter->stats.icrxoc, 4317 "Interrupt Cause Receiver Overrun Count"); 4318 } 4319 4320 /********************************************************************** 4321 * 4322 * This routine provides a way to dump out the adapter eeprom, 4323 * often a useful debug/service tool. This only dumps the first 4324 * 32 words, stuff that matters is in that extent. 4325 * 4326 **********************************************************************/ 4327 static int 4328 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4329 { 4330 struct adapter *adapter = (struct adapter *)arg1; 4331 int error; 4332 int result; 4333 4334 result = -1; 4335 error = sysctl_handle_int(oidp, &result, 0, req); 4336 4337 if (error || !req->newptr) 4338 return (error); 4339 4340 /* 4341 * This value will cause a hex dump of the 4342 * first 32 16-bit words of the EEPROM to 4343 * the screen. 4344 */ 4345 if (result == 1) 4346 em_print_nvm_info(adapter); 4347 4348 return (error); 4349 } 4350 4351 static void 4352 em_print_nvm_info(struct adapter *adapter) 4353 { 4354 u16 eeprom_data; 4355 int i, j, row = 0; 4356 4357 /* Its a bit crude, but it gets the job done */ 4358 printf("\nInterface EEPROM Dump:\n"); 4359 printf("Offset\n0x0000 "); 4360 for (i = 0, j = 0; i < 32; i++, j++) { 4361 if (j == 8) { /* Make the offset block */ 4362 j = 0; ++row; 4363 printf("\n0x00%x0 ",row); 4364 } 4365 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4366 printf("%04x ", eeprom_data); 4367 } 4368 printf("\n"); 4369 } 4370 4371 static int 4372 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4373 { 4374 struct em_int_delay_info *info; 4375 struct adapter *adapter; 4376 u32 regval; 4377 int error, usecs, ticks; 4378 4379 info = (struct em_int_delay_info *) arg1; 4380 usecs = info->value; 4381 error = sysctl_handle_int(oidp, &usecs, 0, req); 4382 if (error != 0 || req->newptr == NULL) 4383 return (error); 4384 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4385 return (EINVAL); 4386 info->value = usecs; 4387 ticks = EM_USECS_TO_TICKS(usecs); 4388 if (info->offset == E1000_ITR) /* units are 256ns here */ 4389 ticks *= 4; 4390 4391 adapter = info->adapter; 4392 4393 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4394 regval = (regval & ~0xffff) | (ticks & 0xffff); 4395 /* Handle a few special cases. */ 4396 switch (info->offset) { 4397 case E1000_RDTR: 4398 break; 4399 case E1000_TIDV: 4400 if (ticks == 0) { 4401 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4402 /* Don't write 0 into the TIDV register. */ 4403 regval++; 4404 } else 4405 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4406 break; 4407 } 4408 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4409 return (0); 4410 } 4411 4412 static void 4413 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4414 const char *description, struct em_int_delay_info *info, 4415 int offset, int value) 4416 { 4417 info->adapter = adapter; 4418 info->offset = offset; 4419 info->value = value; 4420 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4421 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4422 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4423 info, 0, em_sysctl_int_delay, "I", description); 4424 } 4425 4426 /* 4427 * Set flow control using sysctl: 4428 * Flow control values: 4429 * 0 - off 4430 * 1 - rx pause 4431 * 2 - tx pause 4432 * 3 - full 4433 */ 4434 static int 4435 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4436 { 4437 int error; 4438 static int input = 3; /* default is full */ 4439 struct adapter *adapter = (struct adapter *) arg1; 4440 4441 error = sysctl_handle_int(oidp, &input, 0, req); 4442 4443 if ((error) || (req->newptr == NULL)) 4444 return (error); 4445 4446 if (input == adapter->fc) /* no change? */ 4447 return (error); 4448 4449 switch (input) { 4450 case e1000_fc_rx_pause: 4451 case e1000_fc_tx_pause: 4452 case e1000_fc_full: 4453 case e1000_fc_none: 4454 adapter->hw.fc.requested_mode = input; 4455 adapter->fc = input; 4456 break; 4457 default: 4458 /* Do nothing */ 4459 return (error); 4460 } 4461 4462 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4463 e1000_force_mac_fc(&adapter->hw); 4464 return (error); 4465 } 4466 4467 /* 4468 * Manage Energy Efficient Ethernet: 4469 * Control values: 4470 * 0/1 - enabled/disabled 4471 */ 4472 static int 4473 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4474 { 4475 struct adapter *adapter = (struct adapter *) arg1; 4476 int error, value; 4477 4478 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4479 error = sysctl_handle_int(oidp, &value, 0, req); 4480 if (error || req->newptr == NULL) 4481 return (error); 4482 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4483 em_if_init(adapter->ctx); 4484 4485 return (0); 4486 } 4487 4488 static int 4489 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4490 { 4491 struct adapter *adapter; 4492 int error; 4493 int result; 4494 4495 result = -1; 4496 error = sysctl_handle_int(oidp, &result, 0, req); 4497 4498 if (error || !req->newptr) 4499 return (error); 4500 4501 if (result == 1) { 4502 adapter = (struct adapter *) arg1; 4503 em_print_debug_info(adapter); 4504 } 4505 4506 return (error); 4507 } 4508 4509 static int 4510 em_get_rs(SYSCTL_HANDLER_ARGS) 4511 { 4512 struct adapter *adapter = (struct adapter *) arg1; 4513 int error; 4514 int result; 4515 4516 result = 0; 4517 error = sysctl_handle_int(oidp, &result, 0, req); 4518 4519 if (error || !req->newptr || result != 1) 4520 return (error); 4521 em_dump_rs(adapter); 4522 4523 return (error); 4524 } 4525 4526 static void 4527 em_if_debug(if_ctx_t ctx) 4528 { 4529 em_dump_rs(iflib_get_softc(ctx)); 4530 } 4531 4532 /* 4533 * This routine is meant to be fluid, add whatever is 4534 * needed for debugging a problem. -jfv 4535 */ 4536 static void 4537 em_print_debug_info(struct adapter *adapter) 4538 { 4539 device_t dev = iflib_get_dev(adapter->ctx); 4540 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4541 struct tx_ring *txr = &adapter->tx_queues->txr; 4542 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4543 4544 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4545 printf("Interface is RUNNING "); 4546 else 4547 printf("Interface is NOT RUNNING\n"); 4548 4549 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4550 printf("and INACTIVE\n"); 4551 else 4552 printf("and ACTIVE\n"); 4553 4554 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4555 device_printf(dev, "TX Queue %d ------\n", i); 4556 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4557 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4558 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4559 4560 } 4561 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4562 device_printf(dev, "RX Queue %d ------\n", j); 4563 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4564 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4565 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4566 } 4567 } 4568 4569 /* 4570 * 82574 only: 4571 * Write a new value to the EEPROM increasing the number of MSI-X 4572 * vectors from 3 to 5, for proper multiqueue support. 4573 */ 4574 static void 4575 em_enable_vectors_82574(if_ctx_t ctx) 4576 { 4577 struct adapter *adapter = iflib_get_softc(ctx); 4578 struct e1000_hw *hw = &adapter->hw; 4579 device_t dev = iflib_get_dev(ctx); 4580 u16 edata; 4581 4582 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4583 if (bootverbose) 4584 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4585 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4586 device_printf(dev, "Writing to eeprom: increasing " 4587 "reported MSI-X vectors from 3 to 5...\n"); 4588 edata &= ~(EM_NVM_MSIX_N_MASK); 4589 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4590 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4591 e1000_update_nvm_checksum(hw); 4592 device_printf(dev, "Writing to eeprom: done\n"); 4593 } 4594 } 4595