1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, "Intel(R) I219-LM ADL(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, "Intel(R) I219-V ADL(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static const pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 334 struct tx_ring *, struct rx_ring *); 335 static bool em_automask_tso(if_ctx_t); 336 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 337 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 338 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 339 const char *, struct em_int_delay_info *, int, int); 340 /* Management and WOL Support */ 341 static void em_init_manageability(struct e1000_softc *); 342 static void em_release_manageability(struct e1000_softc *); 343 static void em_get_hw_control(struct e1000_softc *); 344 static void em_release_hw_control(struct e1000_softc *); 345 static void em_get_wakeup(if_ctx_t); 346 static void em_enable_wakeup(if_ctx_t); 347 static int em_enable_phy_wakeup(struct e1000_softc *); 348 static void em_disable_aspm(struct e1000_softc *); 349 350 int em_intr(void *); 351 352 /* MSI-X handlers */ 353 static int em_if_msix_intr_assign(if_ctx_t, int); 354 static int em_msix_link(void *); 355 static void em_handle_link(void *); 356 357 static void em_enable_vectors_82574(if_ctx_t); 358 359 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 360 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 361 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 362 static void em_if_led_func(if_ctx_t, int); 363 364 static int em_get_regs(SYSCTL_HANDLER_ARGS); 365 366 static void lem_smartspeed(struct e1000_softc *); 367 static void igb_configure_queues(struct e1000_softc *); 368 static void em_flush_desc_rings(struct e1000_softc *); 369 370 371 /********************************************************************* 372 * FreeBSD Device Interface Entry Points 373 *********************************************************************/ 374 static device_method_t em_methods[] = { 375 /* Device interface */ 376 DEVMETHOD(device_register, em_register), 377 DEVMETHOD(device_probe, iflib_device_probe), 378 DEVMETHOD(device_attach, iflib_device_attach), 379 DEVMETHOD(device_detach, iflib_device_detach), 380 DEVMETHOD(device_shutdown, iflib_device_shutdown), 381 DEVMETHOD(device_suspend, iflib_device_suspend), 382 DEVMETHOD(device_resume, iflib_device_resume), 383 DEVMETHOD_END 384 }; 385 386 static device_method_t igb_methods[] = { 387 /* Device interface */ 388 DEVMETHOD(device_register, igb_register), 389 DEVMETHOD(device_probe, iflib_device_probe), 390 DEVMETHOD(device_attach, iflib_device_attach), 391 DEVMETHOD(device_detach, iflib_device_detach), 392 DEVMETHOD(device_shutdown, iflib_device_shutdown), 393 DEVMETHOD(device_suspend, iflib_device_suspend), 394 DEVMETHOD(device_resume, iflib_device_resume), 395 DEVMETHOD_END 396 }; 397 398 399 static driver_t em_driver = { 400 "em", em_methods, sizeof(struct e1000_softc), 401 }; 402 403 DRIVER_MODULE(em, pci, em_driver, 0, 0); 404 405 MODULE_DEPEND(em, pci, 1, 1, 1); 406 MODULE_DEPEND(em, ether, 1, 1, 1); 407 MODULE_DEPEND(em, iflib, 1, 1, 1); 408 409 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 410 411 static driver_t igb_driver = { 412 "igb", igb_methods, sizeof(struct e1000_softc), 413 }; 414 415 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 416 417 MODULE_DEPEND(igb, pci, 1, 1, 1); 418 MODULE_DEPEND(igb, ether, 1, 1, 1); 419 MODULE_DEPEND(igb, iflib, 1, 1, 1); 420 421 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 422 423 static device_method_t em_if_methods[] = { 424 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 425 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 426 DEVMETHOD(ifdi_detach, em_if_detach), 427 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 428 DEVMETHOD(ifdi_suspend, em_if_suspend), 429 DEVMETHOD(ifdi_resume, em_if_resume), 430 DEVMETHOD(ifdi_init, em_if_init), 431 DEVMETHOD(ifdi_stop, em_if_stop), 432 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 433 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 434 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 435 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 436 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 437 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 438 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 439 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 440 DEVMETHOD(ifdi_media_status, em_if_media_status), 441 DEVMETHOD(ifdi_media_change, em_if_media_change), 442 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 443 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 444 DEVMETHOD(ifdi_timer, em_if_timer), 445 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 446 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 447 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 448 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 449 DEVMETHOD(ifdi_led_func, em_if_led_func), 450 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 451 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 452 DEVMETHOD(ifdi_debug, em_if_debug), 453 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 454 DEVMETHOD_END 455 }; 456 457 static driver_t em_if_driver = { 458 "em_if", em_if_methods, sizeof(struct e1000_softc) 459 }; 460 461 static device_method_t igb_if_methods[] = { 462 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 463 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 464 DEVMETHOD(ifdi_detach, em_if_detach), 465 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 466 DEVMETHOD(ifdi_suspend, em_if_suspend), 467 DEVMETHOD(ifdi_resume, em_if_resume), 468 DEVMETHOD(ifdi_init, em_if_init), 469 DEVMETHOD(ifdi_stop, em_if_stop), 470 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 471 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 472 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 473 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 474 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 475 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 476 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 477 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 478 DEVMETHOD(ifdi_media_status, em_if_media_status), 479 DEVMETHOD(ifdi_media_change, em_if_media_change), 480 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 481 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 482 DEVMETHOD(ifdi_timer, em_if_timer), 483 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 484 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 485 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 486 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 487 DEVMETHOD(ifdi_led_func, em_if_led_func), 488 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 489 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 490 DEVMETHOD(ifdi_debug, em_if_debug), 491 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 492 DEVMETHOD_END 493 }; 494 495 static driver_t igb_if_driver = { 496 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 497 }; 498 499 /********************************************************************* 500 * Tunable default values. 501 *********************************************************************/ 502 503 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 504 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 505 506 /* Allow common code without TSO */ 507 #ifndef CSUM_TSO 508 #define CSUM_TSO 0 509 #endif 510 511 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 512 "EM driver parameters"); 513 514 static int em_disable_crc_stripping = 0; 515 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 516 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 517 518 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 519 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 520 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 521 0, "Default transmit interrupt delay in usecs"); 522 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 523 0, "Default receive interrupt delay in usecs"); 524 525 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 526 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 527 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 528 &em_tx_abs_int_delay_dflt, 0, 529 "Default transmit interrupt delay limit in usecs"); 530 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 531 &em_rx_abs_int_delay_dflt, 0, 532 "Default receive interrupt delay limit in usecs"); 533 534 static int em_smart_pwr_down = false; 535 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 536 0, "Set to true to leave smart power down enabled on newer adapters"); 537 538 static bool em_unsupported_tso = false; 539 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 540 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 541 542 /* Controls whether promiscuous also shows bad packets */ 543 static int em_debug_sbp = false; 544 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 545 "Show bad packets in promiscuous mode"); 546 547 /* Energy efficient ethernet - default to OFF */ 548 static int eee_setting = 1; 549 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 550 "Enable Energy Efficient Ethernet"); 551 552 /* 553 * AIM: Adaptive Interrupt Moderation 554 * which means that the interrupt rate is varied over time based on the 555 * traffic for that interrupt vector 556 */ 557 static int em_enable_aim = 1; 558 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 559 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 560 561 /* 562 ** Tuneable Interrupt rate 563 */ 564 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 565 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 566 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 567 568 /* Global used in WOL setup with multiport cards */ 569 static int global_quad_port_a = 0; 570 571 extern struct if_txrx igb_txrx; 572 extern struct if_txrx em_txrx; 573 extern struct if_txrx lem_txrx; 574 575 static struct if_shared_ctx em_sctx_init = { 576 .isc_magic = IFLIB_MAGIC, 577 .isc_q_align = PAGE_SIZE, 578 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 579 .isc_tx_maxsegsize = PAGE_SIZE, 580 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 581 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 582 .isc_rx_maxsize = MJUM9BYTES, 583 .isc_rx_nsegments = 1, 584 .isc_rx_maxsegsize = MJUM9BYTES, 585 .isc_nfl = 1, 586 .isc_nrxqs = 1, 587 .isc_ntxqs = 1, 588 .isc_admin_intrcnt = 1, 589 .isc_vendor_info = em_vendor_info_array, 590 .isc_driver_version = em_driver_version, 591 .isc_driver = &em_if_driver, 592 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 593 594 .isc_nrxd_min = {EM_MIN_RXD}, 595 .isc_ntxd_min = {EM_MIN_TXD}, 596 .isc_nrxd_max = {EM_MAX_RXD}, 597 .isc_ntxd_max = {EM_MAX_TXD}, 598 .isc_nrxd_default = {EM_DEFAULT_RXD}, 599 .isc_ntxd_default = {EM_DEFAULT_TXD}, 600 }; 601 602 static struct if_shared_ctx igb_sctx_init = { 603 .isc_magic = IFLIB_MAGIC, 604 .isc_q_align = PAGE_SIZE, 605 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 606 .isc_tx_maxsegsize = PAGE_SIZE, 607 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 608 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 609 .isc_rx_maxsize = MJUM9BYTES, 610 .isc_rx_nsegments = 1, 611 .isc_rx_maxsegsize = MJUM9BYTES, 612 .isc_nfl = 1, 613 .isc_nrxqs = 1, 614 .isc_ntxqs = 1, 615 .isc_admin_intrcnt = 1, 616 .isc_vendor_info = igb_vendor_info_array, 617 .isc_driver_version = igb_driver_version, 618 .isc_driver = &igb_if_driver, 619 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 620 621 .isc_nrxd_min = {EM_MIN_RXD}, 622 .isc_ntxd_min = {EM_MIN_TXD}, 623 .isc_nrxd_max = {IGB_MAX_RXD}, 624 .isc_ntxd_max = {IGB_MAX_TXD}, 625 .isc_nrxd_default = {EM_DEFAULT_RXD}, 626 .isc_ntxd_default = {EM_DEFAULT_TXD}, 627 }; 628 629 /***************************************************************** 630 * 631 * Dump Registers 632 * 633 ****************************************************************/ 634 #define IGB_REGS_LEN 739 635 636 static int em_get_regs(SYSCTL_HANDLER_ARGS) 637 { 638 struct e1000_softc *sc = (struct e1000_softc *)arg1; 639 struct e1000_hw *hw = &sc->hw; 640 struct sbuf *sb; 641 u32 *regs_buff; 642 int rc; 643 644 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 645 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 646 647 rc = sysctl_wire_old_buffer(req, 0); 648 MPASS(rc == 0); 649 if (rc != 0) { 650 free(regs_buff, M_DEVBUF); 651 return (rc); 652 } 653 654 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 655 MPASS(sb != NULL); 656 if (sb == NULL) { 657 free(regs_buff, M_DEVBUF); 658 return (ENOMEM); 659 } 660 661 /* General Registers */ 662 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 663 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 664 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 665 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 666 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 667 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 668 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 669 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 670 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 671 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 672 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 673 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 674 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 675 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 676 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 677 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 678 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 679 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 680 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 681 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 682 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 683 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 684 685 sbuf_printf(sb, "General Registers\n"); 686 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 687 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 688 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 689 690 sbuf_printf(sb, "Interrupt Registers\n"); 691 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 692 693 sbuf_printf(sb, "RX Registers\n"); 694 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 695 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 696 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 697 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 698 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 699 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 700 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 701 702 sbuf_printf(sb, "TX Registers\n"); 703 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 704 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 705 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 706 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 707 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 708 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 709 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 710 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 711 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 712 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 713 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 714 715 free(regs_buff, M_DEVBUF); 716 717 #ifdef DUMP_DESCS 718 { 719 if_softc_ctx_t scctx = sc->shared; 720 struct rx_ring *rxr = &rx_que->rxr; 721 struct tx_ring *txr = &tx_que->txr; 722 int ntxd = scctx->isc_ntxd[0]; 723 int nrxd = scctx->isc_nrxd[0]; 724 int j; 725 726 for (j = 0; j < nrxd; j++) { 727 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 728 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 729 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 730 } 731 732 for (j = 0; j < min(ntxd, 256); j++) { 733 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 734 735 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 736 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 737 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 738 739 } 740 } 741 #endif 742 743 rc = sbuf_finish(sb); 744 sbuf_delete(sb); 745 return(rc); 746 } 747 748 static void * 749 em_register(device_t dev) 750 { 751 return (&em_sctx_init); 752 } 753 754 static void * 755 igb_register(device_t dev) 756 { 757 return (&igb_sctx_init); 758 } 759 760 static int 761 em_set_num_queues(if_ctx_t ctx) 762 { 763 struct e1000_softc *sc = iflib_get_softc(ctx); 764 int maxqueues; 765 766 /* Sanity check based on HW */ 767 switch (sc->hw.mac.type) { 768 case e1000_82576: 769 case e1000_82580: 770 case e1000_i350: 771 case e1000_i354: 772 maxqueues = 8; 773 break; 774 case e1000_i210: 775 case e1000_82575: 776 maxqueues = 4; 777 break; 778 case e1000_i211: 779 case e1000_82574: 780 maxqueues = 2; 781 break; 782 default: 783 maxqueues = 1; 784 break; 785 } 786 787 return (maxqueues); 788 } 789 790 #define LEM_CAPS \ 791 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 792 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 793 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 794 795 #define EM_CAPS \ 796 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 797 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 798 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 799 IFCAP_TSO6 800 801 #define IGB_CAPS \ 802 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 803 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 804 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 805 IFCAP_TSO6 806 807 /********************************************************************* 808 * Device initialization routine 809 * 810 * The attach entry point is called when the driver is being loaded. 811 * This routine identifies the type of hardware, allocates all resources 812 * and initializes the hardware. 813 * 814 * return 0 on success, positive on failure 815 *********************************************************************/ 816 static int 817 em_if_attach_pre(if_ctx_t ctx) 818 { 819 struct e1000_softc *sc; 820 if_softc_ctx_t scctx; 821 device_t dev; 822 struct e1000_hw *hw; 823 struct sysctl_oid_list *child; 824 struct sysctl_ctx_list *ctx_list; 825 int error = 0; 826 827 INIT_DEBUGOUT("em_if_attach_pre: begin"); 828 dev = iflib_get_dev(ctx); 829 sc = iflib_get_softc(ctx); 830 831 sc->ctx = sc->osdep.ctx = ctx; 832 sc->dev = sc->osdep.dev = dev; 833 scctx = sc->shared = iflib_get_softc_ctx(ctx); 834 sc->media = iflib_get_media(ctx); 835 hw = &sc->hw; 836 837 /* Determine hardware and mac info */ 838 em_identify_hardware(ctx); 839 840 /* SYSCTL stuff */ 841 ctx_list = device_get_sysctl_ctx(dev); 842 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 843 844 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 845 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 846 em_sysctl_nvm_info, "I", "NVM Information"); 847 848 sc->enable_aim = em_enable_aim; 849 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 850 CTLFLAG_RW, &sc->enable_aim, 0, 851 "Interrupt Moderation (1=normal, 2=lowlatency)"); 852 853 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 854 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 855 em_sysctl_print_fw_version, "A", 856 "Prints FW/NVM Versions"); 857 858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 859 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 860 em_sysctl_debug_info, "I", "Debug Information"); 861 862 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 863 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 864 em_set_flowcntl, "I", "Flow Control"); 865 866 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 867 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 868 em_get_regs, "A", "Dump Registers"); 869 870 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 871 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 872 em_get_rs, "I", "Dump RS indexes"); 873 874 if (hw->mac.type >= e1000_i350) { 875 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 876 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 877 igb_sysctl_dmac, "I", "DMA Coalesce"); 878 } 879 880 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 881 "tso_tcp_flags_mask_first_segment", 882 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 883 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 884 "TSO TCP flags mask for first segment"); 885 886 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 887 "tso_tcp_flags_mask_middle_segment", 888 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 889 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 890 "TSO TCP flags mask for middle segment"); 891 892 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 893 "tso_tcp_flags_mask_last_segment", 894 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 895 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 896 "TSO TCP flags mask for last segment"); 897 898 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 899 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 900 if (bootverbose) 901 device_printf(dev, "attach_pre capping queues at %d\n", 902 scctx->isc_ntxqsets_max); 903 904 if (hw->mac.type >= igb_mac_min) { 905 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 906 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 907 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 908 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 909 scctx->isc_txrx = &igb_txrx; 910 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 911 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 912 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 913 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 914 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 915 CSUM_IP6_TCP | CSUM_IP6_UDP; 916 if (hw->mac.type != e1000_82575) 917 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 918 /* 919 ** Some new devices, as with ixgbe, now may 920 ** use a different BAR, so we need to keep 921 ** track of which is used. 922 */ 923 scctx->isc_msix_bar = pci_msix_table_bar(dev); 924 } else if (hw->mac.type >= em_mac_min) { 925 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 926 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 927 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 928 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 929 scctx->isc_txrx = &em_txrx; 930 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 931 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 932 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 933 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 934 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 935 CSUM_IP6_TCP | CSUM_IP6_UDP; 936 937 /* Disable TSO on all em(4) until ring stalls can be debugged */ 938 scctx->isc_capenable &= ~IFCAP_TSO; 939 940 /* 941 * Disable TSO on SPT due to errata that downclocks DMA performance 942 * i218-i219 Specification Update 1.5.4.5 943 */ 944 if (hw->mac.type == e1000_pch_spt) 945 scctx->isc_capenable &= ~IFCAP_TSO; 946 947 /* 948 * We support MSI-X with 82574 only, but indicate to iflib(4) 949 * that it shall give MSI at least a try with other devices. 950 */ 951 if (hw->mac.type == e1000_82574) { 952 scctx->isc_msix_bar = pci_msix_table_bar(dev); 953 } else { 954 scctx->isc_msix_bar = -1; 955 scctx->isc_disable_msix = 1; 956 } 957 } else { 958 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 959 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 960 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 961 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 962 scctx->isc_txrx = &lem_txrx; 963 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 964 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 965 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 966 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 967 if (em_unsupported_tso) 968 scctx->isc_capabilities |= IFCAP_TSO6; 969 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 970 CSUM_IP6_TCP | CSUM_IP6_UDP; 971 972 /* Disable TSO on all lem(4) until ring stalls can be debugged */ 973 scctx->isc_capenable &= ~IFCAP_TSO; 974 975 /* 82541ER doesn't do HW tagging */ 976 if (hw->device_id == E1000_DEV_ID_82541ER || 977 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 978 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 979 scctx->isc_capenable = scctx->isc_capabilities; 980 } 981 /* This is the first e1000 chip and it does not do offloads */ 982 if (hw->mac.type == e1000_82542) { 983 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 984 IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING | 985 IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO); 986 scctx->isc_capenable = scctx->isc_capabilities; 987 } 988 /* These can't do TSO for various reasons */ 989 if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 || 990 hw->mac.type == e1000_82547_rev_2) { 991 scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 992 scctx->isc_capenable = scctx->isc_capabilities; 993 } 994 /* XXXKB: No IPv6 before this? */ 995 if (hw->mac.type < e1000_82545){ 996 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 997 scctx->isc_capenable = scctx->isc_capabilities; 998 } 999 /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */ 1000 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 1001 scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 1002 IFCAP_HWCSUM_IPV6); 1003 1004 /* INTx only */ 1005 scctx->isc_msix_bar = 0; 1006 } 1007 1008 /* Setup PCI resources */ 1009 if (em_allocate_pci_resources(ctx)) { 1010 device_printf(dev, "Allocation of PCI resources failed\n"); 1011 error = ENXIO; 1012 goto err_pci; 1013 } 1014 1015 /* 1016 ** For ICH8 and family we need to 1017 ** map the flash memory, and this 1018 ** must happen after the MAC is 1019 ** identified 1020 */ 1021 if ((hw->mac.type == e1000_ich8lan) || 1022 (hw->mac.type == e1000_ich9lan) || 1023 (hw->mac.type == e1000_ich10lan) || 1024 (hw->mac.type == e1000_pchlan) || 1025 (hw->mac.type == e1000_pch2lan) || 1026 (hw->mac.type == e1000_pch_lpt)) { 1027 int rid = EM_BAR_TYPE_FLASH; 1028 sc->flash = bus_alloc_resource_any(dev, 1029 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1030 if (sc->flash == NULL) { 1031 device_printf(dev, "Mapping of Flash failed\n"); 1032 error = ENXIO; 1033 goto err_pci; 1034 } 1035 /* This is used in the shared code */ 1036 hw->flash_address = (u8 *)sc->flash; 1037 sc->osdep.flash_bus_space_tag = 1038 rman_get_bustag(sc->flash); 1039 sc->osdep.flash_bus_space_handle = 1040 rman_get_bushandle(sc->flash); 1041 } 1042 /* 1043 ** In the new SPT device flash is not a 1044 ** separate BAR, rather it is also in BAR0, 1045 ** so use the same tag and an offset handle for the 1046 ** FLASH read/write macros in the shared code. 1047 */ 1048 else if (hw->mac.type >= e1000_pch_spt) { 1049 sc->osdep.flash_bus_space_tag = 1050 sc->osdep.mem_bus_space_tag; 1051 sc->osdep.flash_bus_space_handle = 1052 sc->osdep.mem_bus_space_handle 1053 + E1000_FLASH_BASE_ADDR; 1054 } 1055 1056 /* Do Shared Code initialization */ 1057 error = e1000_setup_init_funcs(hw, true); 1058 if (error) { 1059 device_printf(dev, "Setup of Shared code failed, error %d\n", 1060 error); 1061 error = ENXIO; 1062 goto err_pci; 1063 } 1064 1065 em_setup_msix(ctx); 1066 e1000_get_bus_info(hw); 1067 1068 /* Set up some sysctls for the tunable interrupt delays */ 1069 if (hw->mac.type < igb_mac_min) { 1070 em_add_int_delay_sysctl(sc, "rx_int_delay", 1071 "receive interrupt delay in usecs", &sc->rx_int_delay, 1072 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1073 em_add_int_delay_sysctl(sc, "tx_int_delay", 1074 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1075 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1076 } 1077 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1078 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1079 "receive interrupt delay limit in usecs", &sc->rx_abs_int_delay, 1080 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1081 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1082 "transmit interrupt delay limit in usecs", &sc->tx_abs_int_delay, 1083 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1084 em_add_int_delay_sysctl(sc, "itr", 1085 "interrupt delay limit in usecs/4", &sc->tx_itr, 1086 E1000_REGISTER(hw, E1000_ITR), 1087 EM_INTS_TO_ITR(em_max_interrupt_rate)); 1088 } 1089 1090 hw->mac.autoneg = DO_AUTO_NEG; 1091 hw->phy.autoneg_wait_to_complete = false; 1092 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1093 1094 if (hw->mac.type < em_mac_min) { 1095 e1000_init_script_state_82541(hw, true); 1096 e1000_set_tbi_compatibility_82543(hw, true); 1097 } 1098 /* Copper options */ 1099 if (hw->phy.media_type == e1000_media_type_copper) { 1100 hw->phy.mdix = AUTO_ALL_MODES; 1101 hw->phy.disable_polarity_correction = false; 1102 hw->phy.ms_type = EM_MASTER_SLAVE; 1103 } 1104 1105 /* 1106 * Set the frame limits assuming 1107 * standard ethernet sized frames. 1108 */ 1109 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1110 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1111 1112 /* 1113 * This controls when hardware reports transmit completion 1114 * status. 1115 */ 1116 hw->mac.report_tx_early = 1; 1117 1118 /* Allocate multicast array memory. */ 1119 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1120 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1121 if (sc->mta == NULL) { 1122 device_printf(dev, "Can not allocate multicast setup array\n"); 1123 error = ENOMEM; 1124 goto err_late; 1125 } 1126 1127 /* Clear the IFCAP_TSO auto mask */ 1128 sc->tso_automasked = 0; 1129 1130 /* Check SOL/IDER usage */ 1131 if (e1000_check_reset_block(hw)) 1132 device_printf(dev, "PHY reset is blocked" 1133 " due to SOL/IDER session.\n"); 1134 1135 /* Sysctl for setting Energy Efficient Ethernet */ 1136 if (hw->mac.type < igb_mac_min) 1137 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1138 else 1139 hw->dev_spec._82575.eee_disable = eee_setting; 1140 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1141 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1142 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1143 1144 /* 1145 ** Start from a known state, this is 1146 ** important in reading the nvm and 1147 ** mac from that. 1148 */ 1149 e1000_reset_hw(hw); 1150 1151 /* Make sure we have a good EEPROM before we read from it */ 1152 if (e1000_validate_nvm_checksum(hw) < 0) { 1153 /* 1154 ** Some PCI-E parts fail the first check due to 1155 ** the link being in sleep state, call it again, 1156 ** if it fails a second time its a real issue. 1157 */ 1158 if (e1000_validate_nvm_checksum(hw) < 0) { 1159 device_printf(dev, 1160 "The EEPROM Checksum Is Not Valid\n"); 1161 error = EIO; 1162 goto err_late; 1163 } 1164 } 1165 1166 /* Copy the permanent MAC address out of the EEPROM */ 1167 if (e1000_read_mac_addr(hw) < 0) { 1168 device_printf(dev, "EEPROM read error while reading MAC" 1169 " address\n"); 1170 error = EIO; 1171 goto err_late; 1172 } 1173 1174 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1175 if (sc->vf_ifp) { 1176 ether_gen_addr(iflib_get_ifp(ctx), 1177 (struct ether_addr *)hw->mac.addr); 1178 } else { 1179 device_printf(dev, "Invalid MAC address\n"); 1180 error = EIO; 1181 goto err_late; 1182 } 1183 } 1184 1185 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1186 em_fw_version_locked(ctx); 1187 1188 em_print_fw_version(sc); 1189 1190 /* 1191 * Get Wake-on-Lan and Management info for later use 1192 */ 1193 em_get_wakeup(ctx); 1194 1195 /* Enable only WOL MAGIC by default */ 1196 scctx->isc_capenable &= ~IFCAP_WOL; 1197 if (sc->wol != 0) 1198 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1199 1200 iflib_set_mac(ctx, hw->mac.addr); 1201 1202 return (0); 1203 1204 err_late: 1205 em_release_hw_control(sc); 1206 err_pci: 1207 em_free_pci_resources(ctx); 1208 free(sc->mta, M_DEVBUF); 1209 1210 return (error); 1211 } 1212 1213 static int 1214 em_if_attach_post(if_ctx_t ctx) 1215 { 1216 struct e1000_softc *sc = iflib_get_softc(ctx); 1217 struct e1000_hw *hw = &sc->hw; 1218 int error = 0; 1219 1220 /* Setup OS specific network interface */ 1221 error = em_setup_interface(ctx); 1222 if (error != 0) { 1223 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1224 goto err_late; 1225 } 1226 1227 em_reset(ctx); 1228 1229 /* Initialize statistics */ 1230 em_update_stats_counters(sc); 1231 hw->mac.get_link_status = 1; 1232 em_if_update_admin_status(ctx); 1233 em_add_hw_stats(sc); 1234 1235 /* Non-AMT based hardware can now take control from firmware */ 1236 if (sc->has_manage && !sc->has_amt) 1237 em_get_hw_control(sc); 1238 1239 INIT_DEBUGOUT("em_if_attach_post: end"); 1240 1241 return (0); 1242 1243 err_late: 1244 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1245 return (error); 1246 } 1247 1248 /********************************************************************* 1249 * Device removal routine 1250 * 1251 * The detach entry point is called when the driver is being removed. 1252 * This routine stops the adapter and deallocates all the resources 1253 * that were allocated for driver operation. 1254 * 1255 * return 0 on success, positive on failure 1256 *********************************************************************/ 1257 static int 1258 em_if_detach(if_ctx_t ctx) 1259 { 1260 struct e1000_softc *sc = iflib_get_softc(ctx); 1261 1262 INIT_DEBUGOUT("em_if_detach: begin"); 1263 1264 e1000_phy_hw_reset(&sc->hw); 1265 1266 em_release_manageability(sc); 1267 em_release_hw_control(sc); 1268 em_free_pci_resources(ctx); 1269 free(sc->mta, M_DEVBUF); 1270 sc->mta = NULL; 1271 1272 return (0); 1273 } 1274 1275 /********************************************************************* 1276 * 1277 * Shutdown entry point 1278 * 1279 **********************************************************************/ 1280 1281 static int 1282 em_if_shutdown(if_ctx_t ctx) 1283 { 1284 return em_if_suspend(ctx); 1285 } 1286 1287 /* 1288 * Suspend/resume device methods. 1289 */ 1290 static int 1291 em_if_suspend(if_ctx_t ctx) 1292 { 1293 struct e1000_softc *sc = iflib_get_softc(ctx); 1294 1295 em_release_manageability(sc); 1296 em_release_hw_control(sc); 1297 em_enable_wakeup(ctx); 1298 return (0); 1299 } 1300 1301 static int 1302 em_if_resume(if_ctx_t ctx) 1303 { 1304 struct e1000_softc *sc = iflib_get_softc(ctx); 1305 1306 if (sc->hw.mac.type == e1000_pch2lan) 1307 e1000_resume_workarounds_pchlan(&sc->hw); 1308 em_if_init(ctx); 1309 em_init_manageability(sc); 1310 1311 return(0); 1312 } 1313 1314 static int 1315 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1316 { 1317 int max_frame_size; 1318 struct e1000_softc *sc = iflib_get_softc(ctx); 1319 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1320 1321 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1322 1323 switch (sc->hw.mac.type) { 1324 case e1000_82571: 1325 case e1000_82572: 1326 case e1000_ich9lan: 1327 case e1000_ich10lan: 1328 case e1000_pch2lan: 1329 case e1000_pch_lpt: 1330 case e1000_pch_spt: 1331 case e1000_pch_cnp: 1332 case e1000_pch_tgp: 1333 case e1000_pch_adp: 1334 case e1000_pch_mtp: 1335 case e1000_pch_ptp: 1336 case e1000_82574: 1337 case e1000_82583: 1338 case e1000_80003es2lan: 1339 /* 9K Jumbo Frame size */ 1340 max_frame_size = 9234; 1341 break; 1342 case e1000_pchlan: 1343 max_frame_size = 4096; 1344 break; 1345 case e1000_82542: 1346 case e1000_ich8lan: 1347 /* Adapters that do not support jumbo frames */ 1348 max_frame_size = ETHER_MAX_LEN; 1349 break; 1350 default: 1351 if (sc->hw.mac.type >= igb_mac_min) 1352 max_frame_size = 9234; 1353 else /* lem */ 1354 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1355 } 1356 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1357 return (EINVAL); 1358 } 1359 1360 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1361 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1362 return (0); 1363 } 1364 1365 /********************************************************************* 1366 * Init entry point 1367 * 1368 * This routine is used in two ways. It is used by the stack as 1369 * init entry point in network interface structure. It is also used 1370 * by the driver as a hw/sw initialization routine to get to a 1371 * consistent state. 1372 * 1373 **********************************************************************/ 1374 static void 1375 em_if_init(if_ctx_t ctx) 1376 { 1377 struct e1000_softc *sc = iflib_get_softc(ctx); 1378 if_softc_ctx_t scctx = sc->shared; 1379 if_t ifp = iflib_get_ifp(ctx); 1380 struct em_tx_queue *tx_que; 1381 int i; 1382 1383 INIT_DEBUGOUT("em_if_init: begin"); 1384 1385 /* Get the latest mac address, User can use a LAA */ 1386 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1387 ETHER_ADDR_LEN); 1388 1389 /* Put the address into the Receive Address Array */ 1390 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1391 1392 /* 1393 * With the 82571 adapter, RAR[0] may be overwritten 1394 * when the other port is reset, we make a duplicate 1395 * in RAR[14] for that eventuality, this assures 1396 * the interface continues to function. 1397 */ 1398 if (sc->hw.mac.type == e1000_82571) { 1399 e1000_set_laa_state_82571(&sc->hw, true); 1400 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1401 E1000_RAR_ENTRIES - 1); 1402 } 1403 1404 /* Initialize the hardware */ 1405 em_reset(ctx); 1406 em_if_update_admin_status(ctx); 1407 1408 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1409 struct tx_ring *txr = &tx_que->txr; 1410 1411 txr->tx_rs_cidx = txr->tx_rs_pidx; 1412 1413 /* Initialize the last processed descriptor to be the end of 1414 * the ring, rather than the start, so that we avoid an 1415 * off-by-one error when calculating how many descriptors are 1416 * done in the credits_update function. 1417 */ 1418 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1419 } 1420 1421 /* Setup VLAN support, basic and offload if available */ 1422 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1423 1424 /* Clear bad data from Rx FIFOs */ 1425 if (sc->hw.mac.type >= igb_mac_min) 1426 e1000_rx_fifo_flush_base(&sc->hw); 1427 1428 /* Configure for OS presence */ 1429 em_init_manageability(sc); 1430 1431 /* Prepare transmit descriptors and buffers */ 1432 em_initialize_transmit_unit(ctx); 1433 1434 /* Setup Multicast table */ 1435 em_if_multi_set(ctx); 1436 1437 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1438 em_initialize_receive_unit(ctx); 1439 1440 /* Set up VLAN support and filter */ 1441 em_setup_vlan_hw_support(ctx); 1442 1443 /* Don't lose promiscuous settings */ 1444 em_if_set_promisc(ctx, if_getflags(ifp)); 1445 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1446 1447 /* MSI-X configuration for 82574 */ 1448 if (sc->hw.mac.type == e1000_82574) { 1449 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1450 1451 tmp |= E1000_CTRL_EXT_PBA_CLR; 1452 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1453 /* Set the IVAR - interrupt vector routing. */ 1454 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1455 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1456 igb_configure_queues(sc); 1457 1458 /* this clears any pending interrupts */ 1459 E1000_READ_REG(&sc->hw, E1000_ICR); 1460 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1461 1462 /* AMT based hardware can now take control from firmware */ 1463 if (sc->has_manage && sc->has_amt) 1464 em_get_hw_control(sc); 1465 1466 /* Set Energy Efficient Ethernet */ 1467 if (sc->hw.mac.type >= igb_mac_min && 1468 sc->hw.phy.media_type == e1000_media_type_copper) { 1469 if (sc->hw.mac.type == e1000_i354) 1470 e1000_set_eee_i354(&sc->hw, true, true); 1471 else 1472 e1000_set_eee_i350(&sc->hw, true, true); 1473 } 1474 } 1475 1476 enum itr_latency_target { 1477 itr_latency_disabled = 0, 1478 itr_latency_lowest = 1, 1479 itr_latency_low = 2, 1480 itr_latency_bulk = 3 1481 }; 1482 /********************************************************************* 1483 * 1484 * Helper to calculate next (E)ITR value for AIM 1485 * 1486 *********************************************************************/ 1487 static void 1488 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1489 struct tx_ring *txr, struct rx_ring *rxr) 1490 { 1491 struct e1000_hw *hw = &sc->hw; 1492 u32 newitr; 1493 u32 bytes; 1494 u32 bytes_packets; 1495 u32 packets; 1496 u8 nextlatency; 1497 1498 /* Idle, do nothing */ 1499 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0)) 1500 return; 1501 1502 newitr = 0; 1503 1504 if (sc->enable_aim) { 1505 nextlatency = rxr->rx_nextlatency; 1506 1507 /* Use half default (4K) ITR if sub-gig */ 1508 if (sc->link_speed != 1000) { 1509 newitr = EM_INTS_4K; 1510 goto em_set_next_itr; 1511 } 1512 /* Want at least enough packet buffer for two frames to AIM */ 1513 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1514 newitr = em_max_interrupt_rate; 1515 sc->enable_aim = 0; 1516 goto em_set_next_itr; 1517 } 1518 1519 /* Get the largest values from the associated tx and rx ring */ 1520 if (txr->tx_bytes && txr->tx_packets) { 1521 bytes = txr->tx_bytes; 1522 bytes_packets = txr->tx_bytes/txr->tx_packets; 1523 packets = txr->tx_packets; 1524 } 1525 if (rxr->rx_bytes && rxr->rx_packets) { 1526 bytes = max(bytes, rxr->rx_bytes); 1527 bytes_packets = max(bytes_packets, rxr->rx_bytes/rxr->rx_packets); 1528 packets = max(packets, rxr->rx_packets); 1529 } 1530 1531 /* Latency state machine */ 1532 switch (nextlatency) { 1533 case itr_latency_disabled: /* Bootstrapping */ 1534 nextlatency = itr_latency_low; 1535 break; 1536 case itr_latency_lowest: /* 70k ints/s */ 1537 /* TSO and jumbo frames */ 1538 if (bytes_packets > 8000) 1539 nextlatency = itr_latency_bulk; 1540 else if ((packets < 5) && (bytes > 512)) 1541 nextlatency = itr_latency_low; 1542 break; 1543 case itr_latency_low: /* 20k ints/s */ 1544 if (bytes > 10000) { 1545 /* Handle TSO */ 1546 if (bytes_packets > 8000) 1547 nextlatency = itr_latency_bulk; 1548 else if ((packets < 10) || (bytes_packets > 1200)) 1549 nextlatency = itr_latency_bulk; 1550 else if (packets > 35) 1551 nextlatency = itr_latency_lowest; 1552 } else if (bytes_packets > 2000) { 1553 nextlatency = itr_latency_bulk; 1554 } else if (packets < 3 && bytes < 512) { 1555 nextlatency = itr_latency_lowest; 1556 } 1557 break; 1558 case itr_latency_bulk: /* 4k ints/s */ 1559 if (bytes > 25000) { 1560 if (packets > 35) 1561 nextlatency = itr_latency_low; 1562 } else if (bytes < 1500) 1563 nextlatency = itr_latency_low; 1564 break; 1565 default: 1566 nextlatency = itr_latency_low; 1567 device_printf(sc->dev, "Unexpected newitr transition %d\n", 1568 nextlatency); 1569 break; 1570 } 1571 1572 /* Trim itr_latency_lowest for default AIM setting */ 1573 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1574 nextlatency = itr_latency_low; 1575 1576 /* Request new latency */ 1577 rxr->rx_nextlatency = nextlatency; 1578 } else { 1579 /* We may have toggled to AIM disabled */ 1580 nextlatency = itr_latency_disabled; 1581 rxr->rx_nextlatency = nextlatency; 1582 } 1583 1584 /* ITR state machine */ 1585 switch(nextlatency) { 1586 case itr_latency_lowest: 1587 newitr = EM_INTS_70K; 1588 break; 1589 case itr_latency_low: 1590 newitr = EM_INTS_20K; 1591 break; 1592 case itr_latency_bulk: 1593 newitr = EM_INTS_4K; 1594 break; 1595 case itr_latency_disabled: 1596 default: 1597 newitr = em_max_interrupt_rate; 1598 break; 1599 } 1600 1601 em_set_next_itr: 1602 if (hw->mac.type >= igb_mac_min) { 1603 newitr = IGB_INTS_TO_EITR(newitr); 1604 1605 if (hw->mac.type == e1000_82575) 1606 newitr |= newitr << 16; 1607 else 1608 newitr |= E1000_EITR_CNT_IGNR; 1609 1610 if (newitr != que->itr_setting) { 1611 que->itr_setting = newitr; 1612 E1000_WRITE_REG(hw, E1000_EITR(que->msix), que->itr_setting); 1613 } 1614 } else { 1615 newitr = EM_INTS_TO_ITR(newitr); 1616 1617 if (newitr != que->itr_setting) { 1618 que->itr_setting = newitr; 1619 if (hw->mac.type == e1000_82574 && que->msix) { 1620 E1000_WRITE_REG(hw, 1621 E1000_EITR_82574(que->msix), que->itr_setting); 1622 } else { 1623 E1000_WRITE_REG(hw, E1000_ITR, que->itr_setting); 1624 } 1625 } 1626 } 1627 } 1628 1629 /********************************************************************* 1630 * 1631 * Fast Legacy/MSI Combined Interrupt Service routine 1632 * 1633 *********************************************************************/ 1634 int 1635 em_intr(void *arg) 1636 { 1637 struct e1000_softc *sc = arg; 1638 struct e1000_hw *hw = &sc->hw; 1639 struct em_rx_queue *que = &sc->rx_queues[0]; 1640 struct tx_ring *txr = &sc->tx_queues[0].txr; 1641 struct rx_ring *rxr = &que->rxr; 1642 if_ctx_t ctx = sc->ctx; 1643 u32 reg_icr; 1644 1645 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1646 1647 /* Hot eject? */ 1648 if (reg_icr == 0xffffffff) 1649 return FILTER_STRAY; 1650 1651 /* Definitely not our interrupt. */ 1652 if (reg_icr == 0x0) 1653 return FILTER_STRAY; 1654 1655 /* 1656 * Starting with the 82571 chip, bit 31 should be used to 1657 * determine whether the interrupt belongs to us. 1658 */ 1659 if (hw->mac.type >= e1000_82571 && 1660 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1661 return FILTER_STRAY; 1662 1663 /* 1664 * Only MSI-X interrupts have one-shot behavior by taking advantage 1665 * of the EIAC register. Thus, explicitly disable interrupts. This 1666 * also works around the MSI message reordering errata on certain 1667 * systems. 1668 */ 1669 IFDI_INTR_DISABLE(ctx); 1670 1671 /* Link status change */ 1672 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1673 em_handle_link(ctx); 1674 1675 if (reg_icr & E1000_ICR_RXO) 1676 sc->rx_overruns++; 1677 1678 if (hw->mac.type >= e1000_82540) 1679 em_newitr(sc, que, txr, rxr); 1680 1681 /* Reset state */ 1682 txr->tx_bytes = 0; 1683 txr->tx_packets = 0; 1684 rxr->rx_bytes = 0; 1685 rxr->rx_packets = 0; 1686 1687 return (FILTER_SCHEDULE_THREAD); 1688 } 1689 1690 static int 1691 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1692 { 1693 struct e1000_softc *sc = iflib_get_softc(ctx); 1694 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1695 1696 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1697 return (0); 1698 } 1699 1700 static int 1701 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1702 { 1703 struct e1000_softc *sc = iflib_get_softc(ctx); 1704 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1705 1706 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1707 return (0); 1708 } 1709 1710 static int 1711 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1712 { 1713 struct e1000_softc *sc = iflib_get_softc(ctx); 1714 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1715 1716 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1717 return (0); 1718 } 1719 1720 static int 1721 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1722 { 1723 struct e1000_softc *sc = iflib_get_softc(ctx); 1724 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1725 1726 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1727 return (0); 1728 } 1729 1730 /********************************************************************* 1731 * 1732 * MSI-X RX Interrupt Service routine 1733 * 1734 **********************************************************************/ 1735 static int 1736 em_msix_que(void *arg) 1737 { 1738 struct em_rx_queue *que = arg; 1739 struct e1000_softc *sc = que->sc; 1740 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1741 struct rx_ring *rxr = &que->rxr; 1742 1743 ++que->irqs; 1744 1745 em_newitr(sc, que, txr, rxr); 1746 1747 /* Reset state */ 1748 txr->tx_bytes = 0; 1749 txr->tx_packets = 0; 1750 rxr->rx_bytes = 0; 1751 rxr->rx_packets = 0; 1752 1753 return (FILTER_SCHEDULE_THREAD); 1754 } 1755 1756 /********************************************************************* 1757 * 1758 * MSI-X Link Fast Interrupt Service routine 1759 * 1760 **********************************************************************/ 1761 static int 1762 em_msix_link(void *arg) 1763 { 1764 struct e1000_softc *sc = arg; 1765 u32 reg_icr; 1766 1767 ++sc->link_irq; 1768 MPASS(sc->hw.back != NULL); 1769 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1770 1771 if (reg_icr & E1000_ICR_RXO) 1772 sc->rx_overruns++; 1773 1774 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1775 em_handle_link(sc->ctx); 1776 1777 /* Re-arm unconditionally */ 1778 if (sc->hw.mac.type >= igb_mac_min) { 1779 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1780 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1781 } else if (sc->hw.mac.type == e1000_82574) { 1782 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1783 E1000_IMS_OTHER); 1784 /* 1785 * Because we must read the ICR for this interrupt it may 1786 * clear other causes using autoclear, for this reason we 1787 * simply create a soft interrupt for all these vectors. 1788 */ 1789 if (reg_icr) 1790 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1791 } else 1792 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1793 1794 return (FILTER_HANDLED); 1795 } 1796 1797 static void 1798 em_handle_link(void *context) 1799 { 1800 if_ctx_t ctx = context; 1801 struct e1000_softc *sc = iflib_get_softc(ctx); 1802 1803 sc->hw.mac.get_link_status = 1; 1804 iflib_admin_intr_deferred(ctx); 1805 } 1806 1807 /********************************************************************* 1808 * 1809 * Media Ioctl callback 1810 * 1811 * This routine is called whenever the user queries the status of 1812 * the interface using ifconfig. 1813 * 1814 **********************************************************************/ 1815 static void 1816 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1817 { 1818 struct e1000_softc *sc = iflib_get_softc(ctx); 1819 u_char fiber_type = IFM_1000_SX; 1820 1821 INIT_DEBUGOUT("em_if_media_status: begin"); 1822 1823 iflib_admin_intr_deferred(ctx); 1824 1825 ifmr->ifm_status = IFM_AVALID; 1826 ifmr->ifm_active = IFM_ETHER; 1827 1828 if (!sc->link_active) { 1829 return; 1830 } 1831 1832 ifmr->ifm_status |= IFM_ACTIVE; 1833 1834 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1835 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1836 if (sc->hw.mac.type == e1000_82545) 1837 fiber_type = IFM_1000_LX; 1838 ifmr->ifm_active |= fiber_type | IFM_FDX; 1839 } else { 1840 switch (sc->link_speed) { 1841 case 10: 1842 ifmr->ifm_active |= IFM_10_T; 1843 break; 1844 case 100: 1845 ifmr->ifm_active |= IFM_100_TX; 1846 break; 1847 case 1000: 1848 ifmr->ifm_active |= IFM_1000_T; 1849 break; 1850 } 1851 if (sc->link_duplex == FULL_DUPLEX) 1852 ifmr->ifm_active |= IFM_FDX; 1853 else 1854 ifmr->ifm_active |= IFM_HDX; 1855 } 1856 } 1857 1858 /********************************************************************* 1859 * 1860 * Media Ioctl callback 1861 * 1862 * This routine is called when the user changes speed/duplex using 1863 * media/mediopt option with ifconfig. 1864 * 1865 **********************************************************************/ 1866 static int 1867 em_if_media_change(if_ctx_t ctx) 1868 { 1869 struct e1000_softc *sc = iflib_get_softc(ctx); 1870 struct ifmedia *ifm = iflib_get_media(ctx); 1871 1872 INIT_DEBUGOUT("em_if_media_change: begin"); 1873 1874 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1875 return (EINVAL); 1876 1877 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1878 case IFM_AUTO: 1879 sc->hw.mac.autoneg = DO_AUTO_NEG; 1880 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1881 break; 1882 case IFM_1000_LX: 1883 case IFM_1000_SX: 1884 case IFM_1000_T: 1885 sc->hw.mac.autoneg = DO_AUTO_NEG; 1886 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1887 break; 1888 case IFM_100_TX: 1889 sc->hw.mac.autoneg = false; 1890 sc->hw.phy.autoneg_advertised = 0; 1891 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1892 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1893 else 1894 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1895 break; 1896 case IFM_10_T: 1897 sc->hw.mac.autoneg = false; 1898 sc->hw.phy.autoneg_advertised = 0; 1899 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1900 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1901 else 1902 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1903 break; 1904 default: 1905 device_printf(sc->dev, "Unsupported media type\n"); 1906 } 1907 1908 em_if_init(ctx); 1909 1910 return (0); 1911 } 1912 1913 static int 1914 em_if_set_promisc(if_ctx_t ctx, int flags) 1915 { 1916 struct e1000_softc *sc = iflib_get_softc(ctx); 1917 if_t ifp = iflib_get_ifp(ctx); 1918 u32 reg_rctl; 1919 int mcnt = 0; 1920 1921 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1922 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1923 if (flags & IFF_ALLMULTI) 1924 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1925 else 1926 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1927 1928 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1929 reg_rctl &= (~E1000_RCTL_MPE); 1930 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1931 1932 if (flags & IFF_PROMISC) { 1933 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1934 em_if_vlan_filter_disable(sc); 1935 /* Turn this on if you want to see bad packets */ 1936 if (em_debug_sbp) 1937 reg_rctl |= E1000_RCTL_SBP; 1938 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1939 } else { 1940 if (flags & IFF_ALLMULTI) { 1941 reg_rctl |= E1000_RCTL_MPE; 1942 reg_rctl &= ~E1000_RCTL_UPE; 1943 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1944 } 1945 if (em_if_vlan_filter_used(ctx)) 1946 em_if_vlan_filter_enable(sc); 1947 } 1948 return (0); 1949 } 1950 1951 static u_int 1952 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1953 { 1954 u8 *mta = arg; 1955 1956 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1957 return (0); 1958 1959 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1960 1961 return (1); 1962 } 1963 1964 /********************************************************************* 1965 * Multicast Update 1966 * 1967 * This routine is called whenever multicast address list is updated. 1968 * 1969 **********************************************************************/ 1970 static void 1971 em_if_multi_set(if_ctx_t ctx) 1972 { 1973 struct e1000_softc *sc = iflib_get_softc(ctx); 1974 if_t ifp = iflib_get_ifp(ctx); 1975 u8 *mta; /* Multicast array memory */ 1976 u32 reg_rctl = 0; 1977 int mcnt = 0; 1978 1979 IOCTL_DEBUGOUT("em_set_multi: begin"); 1980 1981 mta = sc->mta; 1982 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1983 1984 if (sc->hw.mac.type == e1000_82542 && 1985 sc->hw.revision_id == E1000_REVISION_2) { 1986 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1987 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1988 e1000_pci_clear_mwi(&sc->hw); 1989 reg_rctl |= E1000_RCTL_RST; 1990 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1991 msec_delay(5); 1992 } 1993 1994 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1995 1996 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1997 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1998 1999 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2000 2001 if (if_getflags(ifp) & IFF_PROMISC) 2002 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2003 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2004 if_getflags(ifp) & IFF_ALLMULTI) { 2005 reg_rctl |= E1000_RCTL_MPE; 2006 reg_rctl &= ~E1000_RCTL_UPE; 2007 } else 2008 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2009 2010 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2011 2012 if (sc->hw.mac.type == e1000_82542 && 2013 sc->hw.revision_id == E1000_REVISION_2) { 2014 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2015 reg_rctl &= ~E1000_RCTL_RST; 2016 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2017 msec_delay(5); 2018 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2019 e1000_pci_set_mwi(&sc->hw); 2020 } 2021 } 2022 2023 /********************************************************************* 2024 * Timer routine 2025 * 2026 * This routine schedules em_if_update_admin_status() to check for 2027 * link status and to gather statistics as well as to perform some 2028 * controller-specific hardware patting. 2029 * 2030 **********************************************************************/ 2031 static void 2032 em_if_timer(if_ctx_t ctx, uint16_t qid) 2033 { 2034 2035 if (qid != 0) 2036 return; 2037 2038 iflib_admin_intr_deferred(ctx); 2039 } 2040 2041 static void 2042 em_if_update_admin_status(if_ctx_t ctx) 2043 { 2044 struct e1000_softc *sc = iflib_get_softc(ctx); 2045 struct e1000_hw *hw = &sc->hw; 2046 device_t dev = iflib_get_dev(ctx); 2047 u32 link_check, thstat, ctrl; 2048 bool automasked = false; 2049 2050 link_check = thstat = ctrl = 0; 2051 /* Get the cached link value or read phy for real */ 2052 switch (hw->phy.media_type) { 2053 case e1000_media_type_copper: 2054 if (hw->mac.get_link_status) { 2055 if (hw->mac.type == e1000_pch_spt) 2056 msec_delay(50); 2057 /* Do the work to read phy */ 2058 e1000_check_for_link(hw); 2059 link_check = !hw->mac.get_link_status; 2060 if (link_check) /* ESB2 fix */ 2061 e1000_cfg_on_link_up(hw); 2062 } else { 2063 link_check = true; 2064 } 2065 break; 2066 case e1000_media_type_fiber: 2067 e1000_check_for_link(hw); 2068 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 2069 E1000_STATUS_LU); 2070 break; 2071 case e1000_media_type_internal_serdes: 2072 e1000_check_for_link(hw); 2073 link_check = hw->mac.serdes_has_link; 2074 break; 2075 /* VF device is type_unknown */ 2076 case e1000_media_type_unknown: 2077 e1000_check_for_link(hw); 2078 link_check = !hw->mac.get_link_status; 2079 /* FALLTHROUGH */ 2080 default: 2081 break; 2082 } 2083 2084 /* Check for thermal downshift or shutdown */ 2085 if (hw->mac.type == e1000_i350) { 2086 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2087 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2088 } 2089 2090 /* Now check for a transition */ 2091 if (link_check && (sc->link_active == 0)) { 2092 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2093 &sc->link_duplex); 2094 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2095 if ((sc->link_speed != SPEED_1000) && 2096 ((hw->mac.type == e1000_82571) || 2097 (hw->mac.type == e1000_82572))) { 2098 int tarc0; 2099 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2100 tarc0 &= ~TARC_SPEED_MODE_BIT; 2101 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2102 } 2103 if (bootverbose) 2104 device_printf(dev, "Link is up %d Mbps %s\n", 2105 sc->link_speed, 2106 ((sc->link_duplex == FULL_DUPLEX) ? 2107 "Full Duplex" : "Half Duplex")); 2108 sc->link_active = 1; 2109 sc->smartspeed = 0; 2110 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2111 E1000_CTRL_EXT_LINK_MODE_GMII && 2112 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2113 device_printf(dev, "Link: thermal downshift\n"); 2114 /* Delay Link Up for Phy update */ 2115 if (((hw->mac.type == e1000_i210) || 2116 (hw->mac.type == e1000_i211)) && 2117 (hw->phy.id == I210_I_PHY_ID)) 2118 msec_delay(I210_LINK_DELAY); 2119 /* Reset if the media type changed. */ 2120 if (hw->dev_spec._82575.media_changed && 2121 hw->mac.type >= igb_mac_min) { 2122 hw->dev_spec._82575.media_changed = false; 2123 sc->flags |= IGB_MEDIA_RESET; 2124 em_reset(ctx); 2125 } 2126 /* Only do TSO on gigabit Ethernet for older chips due to errata */ 2127 if (hw->mac.type < igb_mac_min) 2128 automasked = em_automask_tso(ctx); 2129 2130 /* Automasking resets the interface, so don't mark it up yet */ 2131 if (!automasked) 2132 iflib_link_state_change(ctx, LINK_STATE_UP, 2133 IF_Mbps(sc->link_speed)); 2134 } else if (!link_check && (sc->link_active == 1)) { 2135 sc->link_speed = 0; 2136 sc->link_duplex = 0; 2137 sc->link_active = 0; 2138 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2139 } 2140 em_update_stats_counters(sc); 2141 2142 /* Reset LAA into RAR[0] on 82571 */ 2143 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2144 e1000_rar_set(hw, hw->mac.addr, 0); 2145 2146 if (hw->mac.type < em_mac_min) 2147 lem_smartspeed(sc); 2148 } 2149 2150 static void 2151 em_if_watchdog_reset(if_ctx_t ctx) 2152 { 2153 struct e1000_softc *sc = iflib_get_softc(ctx); 2154 2155 /* 2156 * Just count the event; iflib(4) will already trigger a 2157 * sufficient reset of the controller. 2158 */ 2159 sc->watchdog_events++; 2160 } 2161 2162 /********************************************************************* 2163 * 2164 * This routine disables all traffic on the adapter by issuing a 2165 * global reset on the MAC. 2166 * 2167 **********************************************************************/ 2168 static void 2169 em_if_stop(if_ctx_t ctx) 2170 { 2171 struct e1000_softc *sc = iflib_get_softc(ctx); 2172 2173 INIT_DEBUGOUT("em_if_stop: begin"); 2174 2175 /* I219 needs special flushing to avoid hangs */ 2176 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2177 em_flush_desc_rings(sc); 2178 2179 e1000_reset_hw(&sc->hw); 2180 if (sc->hw.mac.type >= e1000_82544) 2181 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2182 2183 e1000_led_off(&sc->hw); 2184 e1000_cleanup_led(&sc->hw); 2185 } 2186 2187 /********************************************************************* 2188 * 2189 * Determine hardware revision. 2190 * 2191 **********************************************************************/ 2192 static void 2193 em_identify_hardware(if_ctx_t ctx) 2194 { 2195 device_t dev = iflib_get_dev(ctx); 2196 struct e1000_softc *sc = iflib_get_softc(ctx); 2197 2198 /* Make sure our PCI config space has the necessary stuff set */ 2199 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2200 2201 /* Save off the information about this board */ 2202 sc->hw.vendor_id = pci_get_vendor(dev); 2203 sc->hw.device_id = pci_get_device(dev); 2204 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2205 sc->hw.subsystem_vendor_id = 2206 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2207 sc->hw.subsystem_device_id = 2208 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2209 2210 /* Do Shared Code Init and Setup */ 2211 if (e1000_set_mac_type(&sc->hw)) { 2212 device_printf(dev, "Setup init failure\n"); 2213 return; 2214 } 2215 2216 /* Are we a VF device? */ 2217 if ((sc->hw.mac.type == e1000_vfadapt) || 2218 (sc->hw.mac.type == e1000_vfadapt_i350)) 2219 sc->vf_ifp = 1; 2220 else 2221 sc->vf_ifp = 0; 2222 } 2223 2224 static int 2225 em_allocate_pci_resources(if_ctx_t ctx) 2226 { 2227 struct e1000_softc *sc = iflib_get_softc(ctx); 2228 device_t dev = iflib_get_dev(ctx); 2229 int rid, val; 2230 2231 rid = PCIR_BAR(0); 2232 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2233 &rid, RF_ACTIVE); 2234 if (sc->memory == NULL) { 2235 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2236 return (ENXIO); 2237 } 2238 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2239 sc->osdep.mem_bus_space_handle = 2240 rman_get_bushandle(sc->memory); 2241 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2242 2243 /* Only older adapters use IO mapping */ 2244 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2245 /* Figure our where our IO BAR is ? */ 2246 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2247 val = pci_read_config(dev, rid, 4); 2248 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2249 break; 2250 } 2251 rid += 4; 2252 /* check for 64bit BAR */ 2253 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2254 rid += 4; 2255 } 2256 if (rid >= PCIR_CIS) { 2257 device_printf(dev, "Unable to locate IO BAR\n"); 2258 return (ENXIO); 2259 } 2260 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2261 &rid, RF_ACTIVE); 2262 if (sc->ioport == NULL) { 2263 device_printf(dev, "Unable to allocate bus resource: " 2264 "ioport\n"); 2265 return (ENXIO); 2266 } 2267 sc->hw.io_base = 0; 2268 sc->osdep.io_bus_space_tag = 2269 rman_get_bustag(sc->ioport); 2270 sc->osdep.io_bus_space_handle = 2271 rman_get_bushandle(sc->ioport); 2272 } 2273 2274 sc->hw.back = &sc->osdep; 2275 2276 return (0); 2277 } 2278 2279 /********************************************************************* 2280 * 2281 * Set up the MSI-X Interrupt handlers 2282 * 2283 **********************************************************************/ 2284 static int 2285 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2286 { 2287 struct e1000_softc *sc = iflib_get_softc(ctx); 2288 struct em_rx_queue *rx_que = sc->rx_queues; 2289 struct em_tx_queue *tx_que = sc->tx_queues; 2290 int error, rid, i, vector = 0, rx_vectors; 2291 char buf[16]; 2292 2293 /* First set up ring resources */ 2294 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2295 rid = vector + 1; 2296 snprintf(buf, sizeof(buf), "rxq%d", i); 2297 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2298 if (error) { 2299 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2300 sc->rx_num_queues = i + 1; 2301 goto fail; 2302 } 2303 2304 rx_que->msix = vector; 2305 2306 /* 2307 * Set the bit to enable interrupt 2308 * in E1000_IMS -- bits 20 and 21 2309 * are for RX0 and RX1, note this has 2310 * NOTHING to do with the MSI-X vector 2311 */ 2312 if (sc->hw.mac.type == e1000_82574) { 2313 rx_que->eims = 1 << (20 + i); 2314 sc->ims |= rx_que->eims; 2315 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2316 } else if (sc->hw.mac.type == e1000_82575) 2317 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2318 else 2319 rx_que->eims = 1 << vector; 2320 } 2321 rx_vectors = vector; 2322 2323 vector = 0; 2324 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2325 snprintf(buf, sizeof(buf), "txq%d", i); 2326 tx_que = &sc->tx_queues[i]; 2327 iflib_softirq_alloc_generic(ctx, 2328 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2329 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2330 2331 tx_que->msix = (vector % sc->rx_num_queues); 2332 2333 /* 2334 * Set the bit to enable interrupt 2335 * in E1000_IMS -- bits 22 and 23 2336 * are for TX0 and TX1, note this has 2337 * NOTHING to do with the MSI-X vector 2338 */ 2339 if (sc->hw.mac.type == e1000_82574) { 2340 tx_que->eims = 1 << (22 + i); 2341 sc->ims |= tx_que->eims; 2342 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2343 } else if (sc->hw.mac.type == e1000_82575) { 2344 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2345 } else { 2346 tx_que->eims = 1 << i; 2347 } 2348 } 2349 2350 /* Link interrupt */ 2351 rid = rx_vectors + 1; 2352 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2353 2354 if (error) { 2355 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2356 goto fail; 2357 } 2358 sc->linkvec = rx_vectors; 2359 if (sc->hw.mac.type < igb_mac_min) { 2360 sc->ivars |= (8 | rx_vectors) << 16; 2361 sc->ivars |= 0x80000000; 2362 /* Enable the "Other" interrupt type for link status change */ 2363 sc->ims |= E1000_IMS_OTHER; 2364 } 2365 2366 return (0); 2367 fail: 2368 iflib_irq_free(ctx, &sc->irq); 2369 rx_que = sc->rx_queues; 2370 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2371 iflib_irq_free(ctx, &rx_que->que_irq); 2372 return (error); 2373 } 2374 2375 static void 2376 igb_configure_queues(struct e1000_softc *sc) 2377 { 2378 struct e1000_hw *hw = &sc->hw; 2379 struct em_rx_queue *rx_que; 2380 struct em_tx_queue *tx_que; 2381 u32 tmp, ivar = 0, newitr = 0; 2382 2383 /* First turn on RSS capability */ 2384 if (hw->mac.type != e1000_82575) 2385 E1000_WRITE_REG(hw, E1000_GPIE, 2386 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2387 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2388 2389 /* Turn on MSI-X */ 2390 switch (hw->mac.type) { 2391 case e1000_82580: 2392 case e1000_i350: 2393 case e1000_i354: 2394 case e1000_i210: 2395 case e1000_i211: 2396 case e1000_vfadapt: 2397 case e1000_vfadapt_i350: 2398 /* RX entries */ 2399 for (int i = 0; i < sc->rx_num_queues; i++) { 2400 u32 index = i >> 1; 2401 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2402 rx_que = &sc->rx_queues[i]; 2403 if (i & 1) { 2404 ivar &= 0xFF00FFFF; 2405 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2406 } else { 2407 ivar &= 0xFFFFFF00; 2408 ivar |= rx_que->msix | E1000_IVAR_VALID; 2409 } 2410 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2411 } 2412 /* TX entries */ 2413 for (int i = 0; i < sc->tx_num_queues; i++) { 2414 u32 index = i >> 1; 2415 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2416 tx_que = &sc->tx_queues[i]; 2417 if (i & 1) { 2418 ivar &= 0x00FFFFFF; 2419 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2420 } else { 2421 ivar &= 0xFFFF00FF; 2422 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2423 } 2424 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2425 sc->que_mask |= tx_que->eims; 2426 } 2427 2428 /* And for the link interrupt */ 2429 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2430 sc->link_mask = 1 << sc->linkvec; 2431 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2432 break; 2433 case e1000_82576: 2434 /* RX entries */ 2435 for (int i = 0; i < sc->rx_num_queues; i++) { 2436 u32 index = i & 0x7; /* Each IVAR has two entries */ 2437 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2438 rx_que = &sc->rx_queues[i]; 2439 if (i < 8) { 2440 ivar &= 0xFFFFFF00; 2441 ivar |= rx_que->msix | E1000_IVAR_VALID; 2442 } else { 2443 ivar &= 0xFF00FFFF; 2444 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2445 } 2446 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2447 sc->que_mask |= rx_que->eims; 2448 } 2449 /* TX entries */ 2450 for (int i = 0; i < sc->tx_num_queues; i++) { 2451 u32 index = i & 0x7; /* Each IVAR has two entries */ 2452 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2453 tx_que = &sc->tx_queues[i]; 2454 if (i < 8) { 2455 ivar &= 0xFFFF00FF; 2456 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2457 } else { 2458 ivar &= 0x00FFFFFF; 2459 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2460 } 2461 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2462 sc->que_mask |= tx_que->eims; 2463 } 2464 2465 /* And for the link interrupt */ 2466 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2467 sc->link_mask = 1 << sc->linkvec; 2468 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2469 break; 2470 2471 case e1000_82575: 2472 /* enable MSI-X support*/ 2473 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2474 tmp |= E1000_CTRL_EXT_PBA_CLR; 2475 /* Auto-Mask interrupts upon ICR read. */ 2476 tmp |= E1000_CTRL_EXT_EIAME; 2477 tmp |= E1000_CTRL_EXT_IRCA; 2478 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2479 2480 /* Queues */ 2481 for (int i = 0; i < sc->rx_num_queues; i++) { 2482 rx_que = &sc->rx_queues[i]; 2483 tmp = E1000_EICR_RX_QUEUE0 << i; 2484 tmp |= E1000_EICR_TX_QUEUE0 << i; 2485 rx_que->eims = tmp; 2486 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2487 i, rx_que->eims); 2488 sc->que_mask |= rx_que->eims; 2489 } 2490 2491 /* Link */ 2492 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2493 E1000_EIMS_OTHER); 2494 sc->link_mask |= E1000_EIMS_OTHER; 2495 default: 2496 break; 2497 } 2498 2499 /* Set the igb starting interrupt rate */ 2500 if (em_max_interrupt_rate > 0) { 2501 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2502 2503 if (hw->mac.type == e1000_82575) 2504 newitr |= newitr << 16; 2505 else 2506 newitr |= E1000_EITR_CNT_IGNR; 2507 2508 for (int i = 0; i < sc->rx_num_queues; i++) { 2509 rx_que = &sc->rx_queues[i]; 2510 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2511 } 2512 } 2513 2514 return; 2515 } 2516 2517 static void 2518 em_free_pci_resources(if_ctx_t ctx) 2519 { 2520 struct e1000_softc *sc = iflib_get_softc(ctx); 2521 struct em_rx_queue *que = sc->rx_queues; 2522 device_t dev = iflib_get_dev(ctx); 2523 2524 /* Release all MSI-X queue resources */ 2525 if (sc->intr_type == IFLIB_INTR_MSIX) 2526 iflib_irq_free(ctx, &sc->irq); 2527 2528 if (que != NULL) { 2529 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2530 iflib_irq_free(ctx, &que->que_irq); 2531 } 2532 } 2533 2534 if (sc->memory != NULL) { 2535 bus_release_resource(dev, SYS_RES_MEMORY, 2536 rman_get_rid(sc->memory), sc->memory); 2537 sc->memory = NULL; 2538 } 2539 2540 if (sc->flash != NULL) { 2541 bus_release_resource(dev, SYS_RES_MEMORY, 2542 rman_get_rid(sc->flash), sc->flash); 2543 sc->flash = NULL; 2544 } 2545 2546 if (sc->ioport != NULL) { 2547 bus_release_resource(dev, SYS_RES_IOPORT, 2548 rman_get_rid(sc->ioport), sc->ioport); 2549 sc->ioport = NULL; 2550 } 2551 } 2552 2553 /* Set up MSI or MSI-X */ 2554 static int 2555 em_setup_msix(if_ctx_t ctx) 2556 { 2557 struct e1000_softc *sc = iflib_get_softc(ctx); 2558 2559 if (sc->hw.mac.type == e1000_82574) { 2560 em_enable_vectors_82574(ctx); 2561 } 2562 return (0); 2563 } 2564 2565 /********************************************************************* 2566 * 2567 * Workaround for SmartSpeed on 82541 and 82547 controllers 2568 * 2569 **********************************************************************/ 2570 static void 2571 lem_smartspeed(struct e1000_softc *sc) 2572 { 2573 u16 phy_tmp; 2574 2575 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2576 sc->hw.mac.autoneg == 0 || 2577 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2578 return; 2579 2580 if (sc->smartspeed == 0) { 2581 /* If Master/Slave config fault is asserted twice, 2582 * we assume back-to-back */ 2583 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2584 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2585 return; 2586 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2587 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2588 e1000_read_phy_reg(&sc->hw, 2589 PHY_1000T_CTRL, &phy_tmp); 2590 if(phy_tmp & CR_1000T_MS_ENABLE) { 2591 phy_tmp &= ~CR_1000T_MS_ENABLE; 2592 e1000_write_phy_reg(&sc->hw, 2593 PHY_1000T_CTRL, phy_tmp); 2594 sc->smartspeed++; 2595 if(sc->hw.mac.autoneg && 2596 !e1000_copper_link_autoneg(&sc->hw) && 2597 !e1000_read_phy_reg(&sc->hw, 2598 PHY_CONTROL, &phy_tmp)) { 2599 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2600 MII_CR_RESTART_AUTO_NEG); 2601 e1000_write_phy_reg(&sc->hw, 2602 PHY_CONTROL, phy_tmp); 2603 } 2604 } 2605 } 2606 return; 2607 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2608 /* If still no link, perhaps using 2/3 pair cable */ 2609 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2610 phy_tmp |= CR_1000T_MS_ENABLE; 2611 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2612 if(sc->hw.mac.autoneg && 2613 !e1000_copper_link_autoneg(&sc->hw) && 2614 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2615 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2616 MII_CR_RESTART_AUTO_NEG); 2617 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2618 } 2619 } 2620 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2621 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2622 sc->smartspeed = 0; 2623 } 2624 2625 /********************************************************************* 2626 * 2627 * Initialize the DMA Coalescing feature 2628 * 2629 **********************************************************************/ 2630 static void 2631 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2632 { 2633 device_t dev = sc->dev; 2634 struct e1000_hw *hw = &sc->hw; 2635 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2636 u16 hwm; 2637 u16 max_frame_size; 2638 2639 if (hw->mac.type == e1000_i211) 2640 return; 2641 2642 max_frame_size = sc->shared->isc_max_frame_size; 2643 if (hw->mac.type > e1000_82580) { 2644 2645 if (sc->dmac == 0) { /* Disabling it */ 2646 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2647 return; 2648 } else 2649 device_printf(dev, "DMA Coalescing enabled\n"); 2650 2651 /* Set starting threshold */ 2652 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2653 2654 hwm = 64 * pba - max_frame_size / 16; 2655 if (hwm < 64 * (pba - 6)) 2656 hwm = 64 * (pba - 6); 2657 reg = E1000_READ_REG(hw, E1000_FCRTC); 2658 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2659 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2660 & E1000_FCRTC_RTH_COAL_MASK); 2661 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2662 2663 2664 dmac = pba - max_frame_size / 512; 2665 if (dmac < pba - 10) 2666 dmac = pba - 10; 2667 reg = E1000_READ_REG(hw, E1000_DMACR); 2668 reg &= ~E1000_DMACR_DMACTHR_MASK; 2669 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2670 & E1000_DMACR_DMACTHR_MASK); 2671 2672 /* transition to L0x or L1 if available..*/ 2673 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2674 2675 /* Check if status is 2.5Gb backplane connection 2676 * before configuration of watchdog timer, which is 2677 * in msec values in 12.8usec intervals 2678 * watchdog timer= msec values in 32usec intervals 2679 * for non 2.5Gb connection 2680 */ 2681 if (hw->mac.type == e1000_i354) { 2682 int status = E1000_READ_REG(hw, E1000_STATUS); 2683 if ((status & E1000_STATUS_2P5_SKU) && 2684 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2685 reg |= ((sc->dmac * 5) >> 6); 2686 else 2687 reg |= (sc->dmac >> 5); 2688 } else { 2689 reg |= (sc->dmac >> 5); 2690 } 2691 2692 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2693 2694 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2695 2696 /* Set the interval before transition */ 2697 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2698 if (hw->mac.type == e1000_i350) 2699 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2700 /* 2701 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2702 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2703 */ 2704 if (hw->mac.type == e1000_i354) { 2705 int status = E1000_READ_REG(hw, E1000_STATUS); 2706 if ((status & E1000_STATUS_2P5_SKU) && 2707 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2708 reg |= 0xA; 2709 else 2710 reg |= 0x4; 2711 } else { 2712 reg |= 0x4; 2713 } 2714 2715 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2716 2717 /* free space in tx packet buffer to wake from DMA coal */ 2718 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2719 (2 * max_frame_size)) >> 6); 2720 2721 /* make low power state decision controlled by DMA coal */ 2722 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2723 reg &= ~E1000_PCIEMISC_LX_DECISION; 2724 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2725 2726 } else if (hw->mac.type == e1000_82580) { 2727 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2728 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2729 reg & ~E1000_PCIEMISC_LX_DECISION); 2730 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2731 } 2732 } 2733 /********************************************************************* 2734 * The 3 following flush routines are used as a workaround in the 2735 * I219 client parts and only for them. 2736 * 2737 * em_flush_tx_ring - remove all descriptors from the tx_ring 2738 * 2739 * We want to clear all pending descriptors from the TX ring. 2740 * zeroing happens when the HW reads the regs. We assign the ring itself as 2741 * the data of the next descriptor. We don't care about the data we are about 2742 * to reset the HW. 2743 **********************************************************************/ 2744 static void 2745 em_flush_tx_ring(struct e1000_softc *sc) 2746 { 2747 struct e1000_hw *hw = &sc->hw; 2748 struct tx_ring *txr = &sc->tx_queues->txr; 2749 struct e1000_tx_desc *txd; 2750 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2751 u16 size = 512; 2752 2753 tctl = E1000_READ_REG(hw, E1000_TCTL); 2754 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2755 2756 txd = &txr->tx_base[txr->tx_cidx_processed]; 2757 2758 /* Just use the ring as a dummy buffer addr */ 2759 txd->buffer_addr = txr->tx_paddr; 2760 txd->lower.data = htole32(txd_lower | size); 2761 txd->upper.data = 0; 2762 2763 /* flush descriptors to memory before notifying the HW */ 2764 wmb(); 2765 2766 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2767 mb(); 2768 usec_delay(250); 2769 } 2770 2771 /********************************************************************* 2772 * em_flush_rx_ring - remove all descriptors from the rx_ring 2773 * 2774 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2775 **********************************************************************/ 2776 static void 2777 em_flush_rx_ring(struct e1000_softc *sc) 2778 { 2779 struct e1000_hw *hw = &sc->hw; 2780 u32 rctl, rxdctl; 2781 2782 rctl = E1000_READ_REG(hw, E1000_RCTL); 2783 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2784 E1000_WRITE_FLUSH(hw); 2785 usec_delay(150); 2786 2787 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2788 /* zero the lower 14 bits (prefetch and host thresholds) */ 2789 rxdctl &= 0xffffc000; 2790 /* 2791 * update thresholds: prefetch threshold to 31, host threshold to 1 2792 * and make sure the granularity is "descriptors" and not "cache lines" 2793 */ 2794 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2795 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2796 2797 /* momentarily enable the RX ring for the changes to take effect */ 2798 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2799 E1000_WRITE_FLUSH(hw); 2800 usec_delay(150); 2801 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2802 } 2803 2804 /********************************************************************* 2805 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2806 * 2807 * In I219, the descriptor rings must be emptied before resetting the HW 2808 * or before changing the device state to D3 during runtime (runtime PM). 2809 * 2810 * Failure to do this will cause the HW to enter a unit hang state which can 2811 * only be released by PCI reset on the device 2812 * 2813 **********************************************************************/ 2814 static void 2815 em_flush_desc_rings(struct e1000_softc *sc) 2816 { 2817 struct e1000_hw *hw = &sc->hw; 2818 device_t dev = sc->dev; 2819 u16 hang_state; 2820 u32 fext_nvm11, tdlen; 2821 2822 /* First, disable MULR fix in FEXTNVM11 */ 2823 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2824 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2825 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2826 2827 /* do nothing if we're not in faulty state, or if the queue is empty */ 2828 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2829 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2830 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2831 return; 2832 em_flush_tx_ring(sc); 2833 2834 /* recheck, maybe the fault is caused by the rx ring */ 2835 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2836 if (hang_state & FLUSH_DESC_REQUIRED) 2837 em_flush_rx_ring(sc); 2838 } 2839 2840 2841 /********************************************************************* 2842 * 2843 * Initialize the hardware to a configuration as specified by the 2844 * sc structure. 2845 * 2846 **********************************************************************/ 2847 static void 2848 em_reset(if_ctx_t ctx) 2849 { 2850 device_t dev = iflib_get_dev(ctx); 2851 struct e1000_softc *sc = iflib_get_softc(ctx); 2852 if_t ifp = iflib_get_ifp(ctx); 2853 struct e1000_hw *hw = &sc->hw; 2854 u32 rx_buffer_size; 2855 u32 pba; 2856 2857 INIT_DEBUGOUT("em_reset: begin"); 2858 /* Let the firmware know the OS is in control */ 2859 em_get_hw_control(sc); 2860 2861 /* Set up smart power down as default off on newer adapters. */ 2862 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2863 hw->mac.type == e1000_82572)) { 2864 u16 phy_tmp = 0; 2865 2866 /* Speed up time to link by disabling smart power down. */ 2867 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2868 phy_tmp &= ~IGP02E1000_PM_SPD; 2869 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2870 } 2871 2872 /* 2873 * Packet Buffer Allocation (PBA) 2874 * Writing PBA sets the receive portion of the buffer 2875 * the remainder is used for the transmit buffer. 2876 */ 2877 switch (hw->mac.type) { 2878 /* 82547: Total Packet Buffer is 40K */ 2879 case e1000_82547: 2880 case e1000_82547_rev_2: 2881 if (hw->mac.max_frame_size > 8192) 2882 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2883 else 2884 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2885 break; 2886 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2887 case e1000_82571: 2888 case e1000_82572: 2889 case e1000_80003es2lan: 2890 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2891 break; 2892 /* 82573: Total Packet Buffer is 32K */ 2893 case e1000_82573: 2894 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2895 break; 2896 case e1000_82574: 2897 case e1000_82583: 2898 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2899 break; 2900 case e1000_ich8lan: 2901 pba = E1000_PBA_8K; 2902 break; 2903 case e1000_ich9lan: 2904 case e1000_ich10lan: 2905 /* Boost Receive side for jumbo frames */ 2906 if (hw->mac.max_frame_size > 4096) 2907 pba = E1000_PBA_14K; 2908 else 2909 pba = E1000_PBA_10K; 2910 break; 2911 case e1000_pchlan: 2912 case e1000_pch2lan: 2913 case e1000_pch_lpt: 2914 case e1000_pch_spt: 2915 case e1000_pch_cnp: 2916 case e1000_pch_tgp: 2917 case e1000_pch_adp: 2918 case e1000_pch_mtp: 2919 case e1000_pch_ptp: 2920 pba = E1000_PBA_26K; 2921 break; 2922 case e1000_82575: 2923 pba = E1000_PBA_32K; 2924 break; 2925 case e1000_82576: 2926 case e1000_vfadapt: 2927 pba = E1000_READ_REG(hw, E1000_RXPBS); 2928 pba &= E1000_RXPBS_SIZE_MASK_82576; 2929 break; 2930 case e1000_82580: 2931 case e1000_i350: 2932 case e1000_i354: 2933 case e1000_vfadapt_i350: 2934 pba = E1000_READ_REG(hw, E1000_RXPBS); 2935 pba = e1000_rxpbs_adjust_82580(pba); 2936 break; 2937 case e1000_i210: 2938 case e1000_i211: 2939 pba = E1000_PBA_34K; 2940 break; 2941 default: 2942 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2943 if (hw->mac.max_frame_size > 8192) 2944 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2945 else 2946 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2947 } 2948 2949 /* Special needs in case of Jumbo frames */ 2950 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2951 u32 tx_space, min_tx, min_rx; 2952 pba = E1000_READ_REG(hw, E1000_PBA); 2953 tx_space = pba >> 16; 2954 pba &= 0xffff; 2955 min_tx = (hw->mac.max_frame_size + 2956 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2957 min_tx = roundup2(min_tx, 1024); 2958 min_tx >>= 10; 2959 min_rx = hw->mac.max_frame_size; 2960 min_rx = roundup2(min_rx, 1024); 2961 min_rx >>= 10; 2962 if (tx_space < min_tx && 2963 ((min_tx - tx_space) < pba)) { 2964 pba = pba - (min_tx - tx_space); 2965 /* 2966 * if short on rx space, rx wins 2967 * and must trump tx adjustment 2968 */ 2969 if (pba < min_rx) 2970 pba = min_rx; 2971 } 2972 E1000_WRITE_REG(hw, E1000_PBA, pba); 2973 } 2974 2975 if (hw->mac.type < igb_mac_min) 2976 E1000_WRITE_REG(hw, E1000_PBA, pba); 2977 2978 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2979 2980 /* 2981 * These parameters control the automatic generation (Tx) and 2982 * response (Rx) to Ethernet PAUSE frames. 2983 * - High water mark should allow for at least two frames to be 2984 * received after sending an XOFF. 2985 * - Low water mark works best when it is very near the high water mark. 2986 * This allows the receiver to restart by sending XON when it has 2987 * drained a bit. Here we use an arbitrary value of 1500 which will 2988 * restart after one full frame is pulled from the buffer. There 2989 * could be several smaller frames in the buffer and if so they will 2990 * not trigger the XON until their total number reduces the buffer 2991 * by 1500. 2992 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2993 */ 2994 rx_buffer_size = (pba & 0xffff) << 10; 2995 hw->fc.high_water = rx_buffer_size - 2996 roundup2(hw->mac.max_frame_size, 1024); 2997 hw->fc.low_water = hw->fc.high_water - 1500; 2998 2999 if (sc->fc) /* locally set flow control value? */ 3000 hw->fc.requested_mode = sc->fc; 3001 else 3002 hw->fc.requested_mode = e1000_fc_full; 3003 3004 if (hw->mac.type == e1000_80003es2lan) 3005 hw->fc.pause_time = 0xFFFF; 3006 else 3007 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3008 3009 hw->fc.send_xon = true; 3010 3011 /* Device specific overrides/settings */ 3012 switch (hw->mac.type) { 3013 case e1000_pchlan: 3014 /* Workaround: no TX flow ctrl for PCH */ 3015 hw->fc.requested_mode = e1000_fc_rx_pause; 3016 hw->fc.pause_time = 0xFFFF; /* override */ 3017 if (if_getmtu(ifp) > ETHERMTU) { 3018 hw->fc.high_water = 0x3500; 3019 hw->fc.low_water = 0x1500; 3020 } else { 3021 hw->fc.high_water = 0x5000; 3022 hw->fc.low_water = 0x3000; 3023 } 3024 hw->fc.refresh_time = 0x1000; 3025 break; 3026 case e1000_pch2lan: 3027 case e1000_pch_lpt: 3028 case e1000_pch_spt: 3029 case e1000_pch_cnp: 3030 case e1000_pch_tgp: 3031 case e1000_pch_adp: 3032 case e1000_pch_mtp: 3033 case e1000_pch_ptp: 3034 hw->fc.high_water = 0x5C20; 3035 hw->fc.low_water = 0x5048; 3036 hw->fc.pause_time = 0x0650; 3037 hw->fc.refresh_time = 0x0400; 3038 /* Jumbos need adjusted PBA */ 3039 if (if_getmtu(ifp) > ETHERMTU) 3040 E1000_WRITE_REG(hw, E1000_PBA, 12); 3041 else 3042 E1000_WRITE_REG(hw, E1000_PBA, 26); 3043 break; 3044 case e1000_82575: 3045 case e1000_82576: 3046 /* 8-byte granularity */ 3047 hw->fc.low_water = hw->fc.high_water - 8; 3048 break; 3049 case e1000_82580: 3050 case e1000_i350: 3051 case e1000_i354: 3052 case e1000_i210: 3053 case e1000_i211: 3054 case e1000_vfadapt: 3055 case e1000_vfadapt_i350: 3056 /* 16-byte granularity */ 3057 hw->fc.low_water = hw->fc.high_water - 16; 3058 break; 3059 case e1000_ich9lan: 3060 case e1000_ich10lan: 3061 if (if_getmtu(ifp) > ETHERMTU) { 3062 hw->fc.high_water = 0x2800; 3063 hw->fc.low_water = hw->fc.high_water - 8; 3064 break; 3065 } 3066 /* FALLTHROUGH */ 3067 default: 3068 if (hw->mac.type == e1000_80003es2lan) 3069 hw->fc.pause_time = 0xFFFF; 3070 break; 3071 } 3072 3073 /* I219 needs some special flushing to avoid hangs */ 3074 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3075 em_flush_desc_rings(sc); 3076 3077 /* Issue a global reset */ 3078 e1000_reset_hw(hw); 3079 if (hw->mac.type >= igb_mac_min) { 3080 E1000_WRITE_REG(hw, E1000_WUC, 0); 3081 } else { 3082 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3083 em_disable_aspm(sc); 3084 } 3085 if (sc->flags & IGB_MEDIA_RESET) { 3086 e1000_setup_init_funcs(hw, true); 3087 e1000_get_bus_info(hw); 3088 sc->flags &= ~IGB_MEDIA_RESET; 3089 } 3090 /* and a re-init */ 3091 if (e1000_init_hw(hw) < 0) { 3092 device_printf(dev, "Hardware Initialization Failed\n"); 3093 return; 3094 } 3095 if (hw->mac.type >= igb_mac_min) 3096 igb_init_dmac(sc, pba); 3097 3098 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3099 sc->pba = pba; 3100 3101 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3102 e1000_get_phy_info(hw); 3103 e1000_check_for_link(hw); 3104 } 3105 3106 /* 3107 * Initialise the RSS mapping for NICs that support multiple transmit/ 3108 * receive rings. 3109 */ 3110 3111 #define RSSKEYLEN 10 3112 static void 3113 em_initialize_rss_mapping(struct e1000_softc *sc) 3114 { 3115 uint8_t rss_key[4 * RSSKEYLEN]; 3116 uint32_t reta = 0; 3117 struct e1000_hw *hw = &sc->hw; 3118 int i; 3119 3120 /* 3121 * Configure RSS key 3122 */ 3123 arc4rand(rss_key, sizeof(rss_key), 0); 3124 for (i = 0; i < RSSKEYLEN; ++i) { 3125 uint32_t rssrk = 0; 3126 3127 rssrk = EM_RSSRK_VAL(rss_key, i); 3128 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3129 } 3130 3131 /* 3132 * Configure RSS redirect table in following fashion: 3133 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3134 */ 3135 for (i = 0; i < sizeof(reta); ++i) { 3136 uint32_t q; 3137 3138 q = (i % sc->rx_num_queues) << 7; 3139 reta |= q << (8 * i); 3140 } 3141 3142 for (i = 0; i < 32; ++i) 3143 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3144 3145 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3146 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3147 E1000_MRQC_RSS_FIELD_IPV4 | 3148 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3149 E1000_MRQC_RSS_FIELD_IPV6_EX | 3150 E1000_MRQC_RSS_FIELD_IPV6); 3151 } 3152 3153 static void 3154 igb_initialize_rss_mapping(struct e1000_softc *sc) 3155 { 3156 struct e1000_hw *hw = &sc->hw; 3157 int i; 3158 int queue_id; 3159 u32 reta; 3160 u32 rss_key[10], mrqc, shift = 0; 3161 3162 /* XXX? */ 3163 if (hw->mac.type == e1000_82575) 3164 shift = 6; 3165 3166 /* 3167 * The redirection table controls which destination 3168 * queue each bucket redirects traffic to. 3169 * Each DWORD represents four queues, with the LSB 3170 * being the first queue in the DWORD. 3171 * 3172 * This just allocates buckets to queues using round-robin 3173 * allocation. 3174 * 3175 * NOTE: It Just Happens to line up with the default 3176 * RSS allocation method. 3177 */ 3178 3179 /* Warning FM follows */ 3180 reta = 0; 3181 for (i = 0; i < 128; i++) { 3182 #ifdef RSS 3183 queue_id = rss_get_indirection_to_bucket(i); 3184 /* 3185 * If we have more queues than buckets, we'll 3186 * end up mapping buckets to a subset of the 3187 * queues. 3188 * 3189 * If we have more buckets than queues, we'll 3190 * end up instead assigning multiple buckets 3191 * to queues. 3192 * 3193 * Both are suboptimal, but we need to handle 3194 * the case so we don't go out of bounds 3195 * indexing arrays and such. 3196 */ 3197 queue_id = queue_id % sc->rx_num_queues; 3198 #else 3199 queue_id = (i % sc->rx_num_queues); 3200 #endif 3201 /* Adjust if required */ 3202 queue_id = queue_id << shift; 3203 3204 /* 3205 * The low 8 bits are for hash value (n+0); 3206 * The next 8 bits are for hash value (n+1), etc. 3207 */ 3208 reta = reta >> 8; 3209 reta = reta | ( ((uint32_t) queue_id) << 24); 3210 if ((i & 3) == 3) { 3211 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3212 reta = 0; 3213 } 3214 } 3215 3216 /* Now fill in hash table */ 3217 3218 /* 3219 * MRQC: Multiple Receive Queues Command 3220 * Set queuing to RSS control, number depends on the device. 3221 */ 3222 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3223 3224 #ifdef RSS 3225 /* XXX ew typecasting */ 3226 rss_getkey((uint8_t *) &rss_key); 3227 #else 3228 arc4rand(&rss_key, sizeof(rss_key), 0); 3229 #endif 3230 for (i = 0; i < 10; i++) 3231 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3232 3233 /* 3234 * Configure the RSS fields to hash upon. 3235 */ 3236 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3237 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3238 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3239 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3240 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3241 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3242 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3243 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3244 3245 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3246 } 3247 3248 /********************************************************************* 3249 * 3250 * Setup networking device structure and register interface media. 3251 * 3252 **********************************************************************/ 3253 static int 3254 em_setup_interface(if_ctx_t ctx) 3255 { 3256 if_t ifp = iflib_get_ifp(ctx); 3257 struct e1000_softc *sc = iflib_get_softc(ctx); 3258 if_softc_ctx_t scctx = sc->shared; 3259 3260 INIT_DEBUGOUT("em_setup_interface: begin"); 3261 3262 /* Single Queue */ 3263 if (sc->tx_num_queues == 1) { 3264 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3265 if_setsendqready(ifp); 3266 } 3267 3268 /* 3269 * Specify the media types supported by this adapter and register 3270 * callbacks to update media and link information 3271 */ 3272 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3273 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3274 u_char fiber_type = IFM_1000_SX; /* default type */ 3275 3276 if (sc->hw.mac.type == e1000_82545) 3277 fiber_type = IFM_1000_LX; 3278 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3279 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3280 } else { 3281 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3282 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3283 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3284 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3285 if (sc->hw.phy.type != e1000_phy_ife) { 3286 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3287 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3288 } 3289 } 3290 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3291 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3292 return (0); 3293 } 3294 3295 static int 3296 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3297 { 3298 struct e1000_softc *sc = iflib_get_softc(ctx); 3299 if_softc_ctx_t scctx = sc->shared; 3300 int error = E1000_SUCCESS; 3301 struct em_tx_queue *que; 3302 int i, j; 3303 3304 MPASS(sc->tx_num_queues > 0); 3305 MPASS(sc->tx_num_queues == ntxqsets); 3306 3307 /* First allocate the top level queue structs */ 3308 if (!(sc->tx_queues = 3309 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3310 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3311 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3312 return(ENOMEM); 3313 } 3314 3315 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3316 /* Set up some basics */ 3317 3318 struct tx_ring *txr = &que->txr; 3319 txr->sc = que->sc = sc; 3320 que->me = txr->me = i; 3321 3322 /* Allocate report status array */ 3323 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3324 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3325 error = ENOMEM; 3326 goto fail; 3327 } 3328 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3329 txr->tx_rsq[j] = QIDX_INVALID; 3330 /* get the virtual and physical address of the hardware queues */ 3331 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3332 txr->tx_paddr = paddrs[i*ntxqs]; 3333 } 3334 3335 if (bootverbose) 3336 device_printf(iflib_get_dev(ctx), 3337 "allocated for %d tx_queues\n", sc->tx_num_queues); 3338 return (0); 3339 fail: 3340 em_if_queues_free(ctx); 3341 return (error); 3342 } 3343 3344 static int 3345 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3346 { 3347 struct e1000_softc *sc = iflib_get_softc(ctx); 3348 int error = E1000_SUCCESS; 3349 struct em_rx_queue *que; 3350 int i; 3351 3352 MPASS(sc->rx_num_queues > 0); 3353 MPASS(sc->rx_num_queues == nrxqsets); 3354 3355 /* First allocate the top level queue structs */ 3356 if (!(sc->rx_queues = 3357 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3358 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3359 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3360 error = ENOMEM; 3361 goto fail; 3362 } 3363 3364 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3365 /* Set up some basics */ 3366 struct rx_ring *rxr = &que->rxr; 3367 rxr->sc = que->sc = sc; 3368 rxr->que = que; 3369 que->me = rxr->me = i; 3370 3371 /* get the virtual and physical address of the hardware queues */ 3372 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3373 rxr->rx_paddr = paddrs[i*nrxqs]; 3374 } 3375 3376 if (bootverbose) 3377 device_printf(iflib_get_dev(ctx), 3378 "allocated for %d rx_queues\n", sc->rx_num_queues); 3379 3380 return (0); 3381 fail: 3382 em_if_queues_free(ctx); 3383 return (error); 3384 } 3385 3386 static void 3387 em_if_queues_free(if_ctx_t ctx) 3388 { 3389 struct e1000_softc *sc = iflib_get_softc(ctx); 3390 struct em_tx_queue *tx_que = sc->tx_queues; 3391 struct em_rx_queue *rx_que = sc->rx_queues; 3392 3393 if (tx_que != NULL) { 3394 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3395 struct tx_ring *txr = &tx_que->txr; 3396 if (txr->tx_rsq == NULL) 3397 break; 3398 3399 free(txr->tx_rsq, M_DEVBUF); 3400 txr->tx_rsq = NULL; 3401 } 3402 free(sc->tx_queues, M_DEVBUF); 3403 sc->tx_queues = NULL; 3404 } 3405 3406 if (rx_que != NULL) { 3407 free(sc->rx_queues, M_DEVBUF); 3408 sc->rx_queues = NULL; 3409 } 3410 } 3411 3412 /********************************************************************* 3413 * 3414 * Enable transmit unit. 3415 * 3416 **********************************************************************/ 3417 static void 3418 em_initialize_transmit_unit(if_ctx_t ctx) 3419 { 3420 struct e1000_softc *sc = iflib_get_softc(ctx); 3421 if_softc_ctx_t scctx = sc->shared; 3422 struct em_tx_queue *que; 3423 struct tx_ring *txr; 3424 struct e1000_hw *hw = &sc->hw; 3425 u32 tctl, txdctl = 0, tarc, tipg = 0; 3426 3427 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3428 3429 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3430 u64 bus_addr; 3431 caddr_t offp, endp; 3432 3433 que = &sc->tx_queues[i]; 3434 txr = &que->txr; 3435 bus_addr = txr->tx_paddr; 3436 3437 /* Clear checksum offload context. */ 3438 offp = (caddr_t)&txr->csum_flags; 3439 endp = (caddr_t)(txr + 1); 3440 bzero(offp, endp - offp); 3441 3442 /* Base and Len of TX Ring */ 3443 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3444 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3445 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3446 (u32)(bus_addr >> 32)); 3447 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3448 (u32)bus_addr); 3449 /* Init the HEAD/TAIL indices */ 3450 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3451 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3452 3453 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3454 E1000_READ_REG(hw, E1000_TDBAL(i)), 3455 E1000_READ_REG(hw, E1000_TDLEN(i))); 3456 3457 txdctl = 0; /* clear txdctl */ 3458 txdctl |= 0x1f; /* PTHRESH */ 3459 txdctl |= 1 << 8; /* HTHRESH */ 3460 txdctl |= 1 << 16;/* WTHRESH */ 3461 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3462 txdctl |= E1000_TXDCTL_GRAN; 3463 txdctl |= 1 << 25; /* LWTHRESH */ 3464 3465 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3466 } 3467 3468 /* Set the default values for the Tx Inter Packet Gap timer */ 3469 switch (hw->mac.type) { 3470 case e1000_80003es2lan: 3471 tipg = DEFAULT_82543_TIPG_IPGR1; 3472 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3473 E1000_TIPG_IPGR2_SHIFT; 3474 break; 3475 case e1000_82542: 3476 tipg = DEFAULT_82542_TIPG_IPGT; 3477 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3478 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3479 break; 3480 default: 3481 if (hw->phy.media_type == e1000_media_type_fiber || 3482 hw->phy.media_type == e1000_media_type_internal_serdes) 3483 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3484 else 3485 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3486 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3487 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3488 } 3489 3490 if (hw->mac.type < igb_mac_min) { 3491 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3492 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3493 3494 if (sc->tx_int_delay.value > 0) 3495 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3496 } 3497 3498 if (hw->mac.type >= e1000_82540) 3499 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3500 3501 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3502 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3503 tarc |= TARC_SPEED_MODE_BIT; 3504 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3505 } else if (hw->mac.type == e1000_80003es2lan) { 3506 /* errata: program both queues to unweighted RR */ 3507 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3508 tarc |= 1; 3509 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3510 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3511 tarc |= 1; 3512 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3513 } else if (hw->mac.type == e1000_82574) { 3514 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3515 tarc |= TARC_ERRATA_BIT; 3516 if ( sc->tx_num_queues > 1) { 3517 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3518 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3519 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3520 } else 3521 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3522 } 3523 3524 /* Program the Transmit Control Register */ 3525 tctl = E1000_READ_REG(hw, E1000_TCTL); 3526 tctl &= ~E1000_TCTL_CT; 3527 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3528 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3529 3530 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3531 tctl |= E1000_TCTL_MULR; 3532 3533 /* This write will effectively turn on the transmit unit. */ 3534 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3535 3536 /* SPT and KBL errata workarounds */ 3537 if (hw->mac.type == e1000_pch_spt) { 3538 u32 reg; 3539 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3540 reg |= E1000_RCTL_RDMTS_HEX; 3541 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3542 /* i218-i219 Specification Update 1.5.4.5 */ 3543 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3544 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3545 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3546 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3547 } 3548 } 3549 3550 /********************************************************************* 3551 * 3552 * Enable receive unit. 3553 * 3554 **********************************************************************/ 3555 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3556 3557 static void 3558 em_initialize_receive_unit(if_ctx_t ctx) 3559 { 3560 struct e1000_softc *sc = iflib_get_softc(ctx); 3561 if_softc_ctx_t scctx = sc->shared; 3562 if_t ifp = iflib_get_ifp(ctx); 3563 struct e1000_hw *hw = &sc->hw; 3564 struct em_rx_queue *que; 3565 int i; 3566 uint32_t rctl, rxcsum; 3567 3568 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3569 3570 /* 3571 * Make sure receives are disabled while setting 3572 * up the descriptor ring 3573 */ 3574 rctl = E1000_READ_REG(hw, E1000_RCTL); 3575 /* Do not disable if ever enabled on this hardware */ 3576 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3577 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3578 3579 /* Setup the Receive Control Register */ 3580 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3581 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3582 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3583 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3584 3585 /* Do not store bad packets */ 3586 rctl &= ~E1000_RCTL_SBP; 3587 3588 /* Enable Long Packet receive */ 3589 if (if_getmtu(ifp) > ETHERMTU) 3590 rctl |= E1000_RCTL_LPE; 3591 else 3592 rctl &= ~E1000_RCTL_LPE; 3593 3594 /* Strip the CRC */ 3595 if (!em_disable_crc_stripping) 3596 rctl |= E1000_RCTL_SECRC; 3597 3598 /* lem/em default interrupt moderation */ 3599 if (hw->mac.type < igb_mac_min) { 3600 if (hw->mac.type >= e1000_82540) { 3601 E1000_WRITE_REG(hw, E1000_RADV, sc->rx_abs_int_delay.value); 3602 3603 /* Set the default interrupt throttling rate */ 3604 E1000_WRITE_REG(hw, E1000_ITR, 3605 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3606 } 3607 3608 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3609 * long latencies are observed, like Lenovo X60. This 3610 * change eliminates the problem, but since having positive 3611 * values in RDTR is a known source of problems on other 3612 * platforms another solution is being sought. 3613 */ 3614 if (hw->mac.type == e1000_82573) 3615 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3616 else 3617 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3618 } 3619 3620 if (hw->mac.type >= em_mac_min) { 3621 uint32_t rfctl; 3622 /* Use extended rx descriptor formats */ 3623 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3624 rfctl |= E1000_RFCTL_EXTEN; 3625 3626 /* 3627 * When using MSI-X interrupts we need to throttle 3628 * using the EITR register (82574 only) 3629 */ 3630 if (hw->mac.type == e1000_82574) { 3631 for (int i = 0; i < 4; i++) 3632 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3633 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3634 /* Disable accelerated acknowledge */ 3635 rfctl |= E1000_RFCTL_ACK_DIS; 3636 } 3637 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3638 } 3639 3640 /* Set up L3 and L4 csum Rx descriptor offloads */ 3641 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3642 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3643 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3644 if (hw->mac.type > e1000_82575) 3645 rxcsum |= E1000_RXCSUM_CRCOFL; 3646 else if (hw->mac.type < em_mac_min && 3647 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3648 rxcsum |= E1000_RXCSUM_IPV6OFL; 3649 } else { 3650 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3651 if (hw->mac.type > e1000_82575) 3652 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3653 else if (hw->mac.type < em_mac_min) 3654 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3655 } 3656 3657 if (sc->rx_num_queues > 1) { 3658 /* RSS hash needed in the Rx descriptor */ 3659 rxcsum |= E1000_RXCSUM_PCSD; 3660 3661 if (hw->mac.type >= igb_mac_min) 3662 igb_initialize_rss_mapping(sc); 3663 else 3664 em_initialize_rss_mapping(sc); 3665 } 3666 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3667 3668 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3669 struct rx_ring *rxr = &que->rxr; 3670 /* Setup the Base and Length of the Rx Descriptor Ring */ 3671 u64 bus_addr = rxr->rx_paddr; 3672 #if 0 3673 u32 rdt = sc->rx_num_queues -1; /* default */ 3674 #endif 3675 3676 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3677 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3678 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3679 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3680 /* Setup the Head and Tail Descriptor Pointers */ 3681 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3682 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3683 } 3684 3685 /* 3686 * Set PTHRESH for improved jumbo performance 3687 * According to 10.2.5.11 of Intel 82574 Datasheet, 3688 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3689 * Only write to RXDCTL(1) if there is a need for different 3690 * settings. 3691 */ 3692 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3693 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3694 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3695 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3696 } else if (hw->mac.type == e1000_82574) { 3697 for (int i = 0; i < sc->rx_num_queues; i++) { 3698 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3699 rxdctl |= 0x20; /* PTHRESH */ 3700 rxdctl |= 4 << 8; /* HTHRESH */ 3701 rxdctl |= 4 << 16;/* WTHRESH */ 3702 rxdctl |= 1 << 24; /* Switch to granularity */ 3703 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3704 } 3705 } else if (hw->mac.type >= igb_mac_min) { 3706 u32 psize, srrctl = 0; 3707 3708 if (if_getmtu(ifp) > ETHERMTU) { 3709 psize = scctx->isc_max_frame_size; 3710 /* are we on a vlan? */ 3711 if (if_vlantrunkinuse(ifp)) 3712 psize += VLAN_TAG_SIZE; 3713 3714 if (sc->vf_ifp) 3715 e1000_rlpml_set_vf(hw, psize); 3716 else 3717 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3718 } 3719 3720 /* Set maximum packet buffer len */ 3721 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3722 E1000_SRRCTL_BSIZEPKT_SHIFT; 3723 3724 /* 3725 * If TX flow control is disabled and there's >1 queue defined, 3726 * enable DROP. 3727 * 3728 * This drops frames rather than hanging the RX MAC for all queues. 3729 */ 3730 if ((sc->rx_num_queues > 1) && 3731 (sc->fc == e1000_fc_none || 3732 sc->fc == e1000_fc_rx_pause)) { 3733 srrctl |= E1000_SRRCTL_DROP_EN; 3734 } 3735 /* Setup the Base and Length of the Rx Descriptor Rings */ 3736 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3737 struct rx_ring *rxr = &que->rxr; 3738 u64 bus_addr = rxr->rx_paddr; 3739 u32 rxdctl; 3740 3741 #ifdef notyet 3742 /* Configure for header split? -- ignore for now */ 3743 rxr->hdr_split = igb_header_split; 3744 #else 3745 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3746 #endif 3747 3748 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3749 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3750 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3751 (uint32_t)(bus_addr >> 32)); 3752 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3753 (uint32_t)bus_addr); 3754 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3755 /* Enable this Queue */ 3756 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3757 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3758 rxdctl &= 0xFFF00000; 3759 rxdctl |= IGB_RX_PTHRESH; 3760 rxdctl |= IGB_RX_HTHRESH << 8; 3761 rxdctl |= IGB_RX_WTHRESH << 16; 3762 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3763 } 3764 } else if (hw->mac.type >= e1000_pch2lan) { 3765 if (if_getmtu(ifp) > ETHERMTU) 3766 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3767 else 3768 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3769 } 3770 3771 /* Make sure VLAN Filters are off */ 3772 rctl &= ~E1000_RCTL_VFE; 3773 3774 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3775 if (hw->mac.type < igb_mac_min) { 3776 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3777 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3778 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3779 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3780 else if (sc->rx_mbuf_sz > 8192) 3781 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3782 else { 3783 rctl |= E1000_RCTL_SZ_2048; 3784 rctl &= ~E1000_RCTL_BSEX; 3785 } 3786 } else 3787 rctl |= E1000_RCTL_SZ_2048; 3788 3789 /* 3790 * rctl bits 11:10 are as follows 3791 * lem: reserved 3792 * em: DTYPE 3793 * igb: reserved 3794 * and should be 00 on all of the above 3795 */ 3796 rctl &= ~0x00000C00; 3797 3798 /* Write out the settings */ 3799 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3800 3801 return; 3802 } 3803 3804 static void 3805 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3806 { 3807 struct e1000_softc *sc = iflib_get_softc(ctx); 3808 u32 index, bit; 3809 3810 index = (vtag >> 5) & 0x7F; 3811 bit = vtag & 0x1F; 3812 sc->shadow_vfta[index] |= (1 << bit); 3813 ++sc->num_vlans; 3814 em_if_vlan_filter_write(sc); 3815 } 3816 3817 static void 3818 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3819 { 3820 struct e1000_softc *sc = iflib_get_softc(ctx); 3821 u32 index, bit; 3822 3823 index = (vtag >> 5) & 0x7F; 3824 bit = vtag & 0x1F; 3825 sc->shadow_vfta[index] &= ~(1 << bit); 3826 --sc->num_vlans; 3827 em_if_vlan_filter_write(sc); 3828 } 3829 3830 static bool 3831 em_if_vlan_filter_capable(if_ctx_t ctx) 3832 { 3833 if_t ifp = iflib_get_ifp(ctx); 3834 3835 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3836 !em_disable_crc_stripping) 3837 return (true); 3838 3839 return (false); 3840 } 3841 3842 static bool 3843 em_if_vlan_filter_used(if_ctx_t ctx) 3844 { 3845 struct e1000_softc *sc = iflib_get_softc(ctx); 3846 3847 if (!em_if_vlan_filter_capable(ctx)) 3848 return (false); 3849 3850 for (int i = 0; i < EM_VFTA_SIZE; i++) 3851 if (sc->shadow_vfta[i] != 0) 3852 return (true); 3853 3854 return (false); 3855 } 3856 3857 static void 3858 em_if_vlan_filter_enable(struct e1000_softc *sc) 3859 { 3860 struct e1000_hw *hw = &sc->hw; 3861 u32 reg; 3862 3863 reg = E1000_READ_REG(hw, E1000_RCTL); 3864 reg &= ~E1000_RCTL_CFIEN; 3865 reg |= E1000_RCTL_VFE; 3866 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3867 } 3868 3869 static void 3870 em_if_vlan_filter_disable(struct e1000_softc *sc) 3871 { 3872 struct e1000_hw *hw = &sc->hw; 3873 u32 reg; 3874 3875 reg = E1000_READ_REG(hw, E1000_RCTL); 3876 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3877 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3878 } 3879 3880 static void 3881 em_if_vlan_filter_write(struct e1000_softc *sc) 3882 { 3883 struct e1000_hw *hw = &sc->hw; 3884 3885 if (sc->vf_ifp) 3886 return; 3887 3888 /* Disable interrupts for lem-class devices during the filter change */ 3889 if (hw->mac.type < em_mac_min) 3890 em_if_intr_disable(sc->ctx); 3891 3892 for (int i = 0; i < EM_VFTA_SIZE; i++) 3893 if (sc->shadow_vfta[i] != 0) { 3894 /* XXXKB: incomplete VF support, we return early above */ 3895 if (sc->vf_ifp) 3896 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3897 else 3898 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3899 } 3900 3901 /* Re-enable interrupts for lem-class devices */ 3902 if (hw->mac.type < em_mac_min) 3903 em_if_intr_enable(sc->ctx); 3904 } 3905 3906 static void 3907 em_setup_vlan_hw_support(if_ctx_t ctx) 3908 { 3909 struct e1000_softc *sc = iflib_get_softc(ctx); 3910 struct e1000_hw *hw = &sc->hw; 3911 if_t ifp = iflib_get_ifp(ctx); 3912 u32 reg; 3913 3914 /* XXXKB: Return early if we are a VF until VF decap and filter management 3915 * is ready and tested. 3916 */ 3917 if (sc->vf_ifp) 3918 return; 3919 3920 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3921 !em_disable_crc_stripping) { 3922 reg = E1000_READ_REG(hw, E1000_CTRL); 3923 reg |= E1000_CTRL_VME; 3924 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3925 } else { 3926 reg = E1000_READ_REG(hw, E1000_CTRL); 3927 reg &= ~E1000_CTRL_VME; 3928 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3929 } 3930 3931 /* If we aren't doing HW filtering, we're done */ 3932 if (!em_if_vlan_filter_capable(ctx)) { 3933 em_if_vlan_filter_disable(sc); 3934 return; 3935 } 3936 3937 /* 3938 * A soft reset zero's out the VFTA, so 3939 * we need to repopulate it now. 3940 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3941 * traffic through. This will write the entire table. 3942 */ 3943 em_if_vlan_register(ctx, 0); 3944 3945 /* Enable the Filter Table */ 3946 em_if_vlan_filter_enable(sc); 3947 } 3948 3949 static void 3950 em_if_intr_enable(if_ctx_t ctx) 3951 { 3952 struct e1000_softc *sc = iflib_get_softc(ctx); 3953 struct e1000_hw *hw = &sc->hw; 3954 u32 ims_mask = IMS_ENABLE_MASK; 3955 3956 if (sc->intr_type == IFLIB_INTR_MSIX) { 3957 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3958 ims_mask |= sc->ims; 3959 } 3960 3961 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3962 E1000_WRITE_FLUSH(hw); 3963 } 3964 3965 static void 3966 em_if_intr_disable(if_ctx_t ctx) 3967 { 3968 struct e1000_softc *sc = iflib_get_softc(ctx); 3969 struct e1000_hw *hw = &sc->hw; 3970 3971 if (sc->intr_type == IFLIB_INTR_MSIX) 3972 E1000_WRITE_REG(hw, EM_EIAC, 0); 3973 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3974 E1000_WRITE_FLUSH(hw); 3975 } 3976 3977 static void 3978 igb_if_intr_enable(if_ctx_t ctx) 3979 { 3980 struct e1000_softc *sc = iflib_get_softc(ctx); 3981 struct e1000_hw *hw = &sc->hw; 3982 u32 mask; 3983 3984 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3985 mask = (sc->que_mask | sc->link_mask); 3986 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3987 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3988 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3989 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3990 } else 3991 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3992 E1000_WRITE_FLUSH(hw); 3993 } 3994 3995 static void 3996 igb_if_intr_disable(if_ctx_t ctx) 3997 { 3998 struct e1000_softc *sc = iflib_get_softc(ctx); 3999 struct e1000_hw *hw = &sc->hw; 4000 4001 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4002 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4003 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4004 } 4005 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4006 E1000_WRITE_FLUSH(hw); 4007 } 4008 4009 /* 4010 * Bit of a misnomer, what this really means is 4011 * to enable OS management of the system... aka 4012 * to disable special hardware management features 4013 */ 4014 static void 4015 em_init_manageability(struct e1000_softc *sc) 4016 { 4017 /* A shared code workaround */ 4018 #define E1000_82542_MANC2H E1000_MANC2H 4019 if (sc->has_manage) { 4020 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4021 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4022 4023 /* disable hardware interception of ARP */ 4024 manc &= ~(E1000_MANC_ARP_EN); 4025 4026 /* enable receiving management packets to the host */ 4027 manc |= E1000_MANC_EN_MNG2HOST; 4028 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4029 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4030 manc2h |= E1000_MNG2HOST_PORT_623; 4031 manc2h |= E1000_MNG2HOST_PORT_664; 4032 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4033 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4034 } 4035 } 4036 4037 /* 4038 * Give control back to hardware management 4039 * controller if there is one. 4040 */ 4041 static void 4042 em_release_manageability(struct e1000_softc *sc) 4043 { 4044 if (sc->has_manage) { 4045 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4046 4047 /* re-enable hardware interception of ARP */ 4048 manc |= E1000_MANC_ARP_EN; 4049 manc &= ~E1000_MANC_EN_MNG2HOST; 4050 4051 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4052 } 4053 } 4054 4055 /* 4056 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4057 * For ASF and Pass Through versions of f/w this means 4058 * that the driver is loaded. For AMT version type f/w 4059 * this means that the network i/f is open. 4060 */ 4061 static void 4062 em_get_hw_control(struct e1000_softc *sc) 4063 { 4064 u32 ctrl_ext, swsm; 4065 4066 if (sc->vf_ifp) 4067 return; 4068 4069 if (sc->hw.mac.type == e1000_82573) { 4070 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4071 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4072 swsm | E1000_SWSM_DRV_LOAD); 4073 return; 4074 } 4075 /* else */ 4076 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4077 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4078 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4079 } 4080 4081 /* 4082 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4083 * For ASF and Pass Through versions of f/w this means that 4084 * the driver is no longer loaded. For AMT versions of the 4085 * f/w this means that the network i/f is closed. 4086 */ 4087 static void 4088 em_release_hw_control(struct e1000_softc *sc) 4089 { 4090 u32 ctrl_ext, swsm; 4091 4092 if (!sc->has_manage) 4093 return; 4094 4095 if (sc->hw.mac.type == e1000_82573) { 4096 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4097 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4098 swsm & ~E1000_SWSM_DRV_LOAD); 4099 return; 4100 } 4101 /* else */ 4102 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4103 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4104 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4105 return; 4106 } 4107 4108 static int 4109 em_is_valid_ether_addr(u8 *addr) 4110 { 4111 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4112 4113 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4114 return (false); 4115 } 4116 4117 return (true); 4118 } 4119 4120 static bool 4121 em_automask_tso(if_ctx_t ctx) 4122 { 4123 struct e1000_softc *sc = iflib_get_softc(ctx); 4124 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4125 if_t ifp = iflib_get_ifp(ctx); 4126 4127 if (!em_unsupported_tso && sc->link_speed && 4128 sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) { 4129 device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n"); 4130 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4131 scctx->isc_capenable &= ~IFCAP_TSO; 4132 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4133 /* iflib_init_locked handles ifnet hwassistbits */ 4134 iflib_request_reset(ctx); 4135 return true; 4136 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4137 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4138 scctx->isc_capenable |= sc->tso_automasked; 4139 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4140 sc->tso_automasked = 0; 4141 /* iflib_init_locked handles ifnet hwassistbits */ 4142 iflib_request_reset(ctx); 4143 return true; 4144 } 4145 4146 return false; 4147 } 4148 4149 /* 4150 ** Parse the interface capabilities with regard 4151 ** to both system management and wake-on-lan for 4152 ** later use. 4153 */ 4154 static void 4155 em_get_wakeup(if_ctx_t ctx) 4156 { 4157 struct e1000_softc *sc = iflib_get_softc(ctx); 4158 device_t dev = iflib_get_dev(ctx); 4159 u16 eeprom_data = 0, device_id, apme_mask; 4160 4161 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4162 apme_mask = EM_EEPROM_APME; 4163 4164 switch (sc->hw.mac.type) { 4165 case e1000_82542: 4166 case e1000_82543: 4167 break; 4168 case e1000_82544: 4169 e1000_read_nvm(&sc->hw, 4170 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4171 apme_mask = EM_82544_APME; 4172 break; 4173 case e1000_82546: 4174 case e1000_82546_rev_3: 4175 if (sc->hw.bus.func == 1) { 4176 e1000_read_nvm(&sc->hw, 4177 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4178 break; 4179 } else 4180 e1000_read_nvm(&sc->hw, 4181 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4182 break; 4183 case e1000_82573: 4184 case e1000_82583: 4185 sc->has_amt = true; 4186 /* FALLTHROUGH */ 4187 case e1000_82571: 4188 case e1000_82572: 4189 case e1000_80003es2lan: 4190 if (sc->hw.bus.func == 1) { 4191 e1000_read_nvm(&sc->hw, 4192 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4193 break; 4194 } else 4195 e1000_read_nvm(&sc->hw, 4196 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4197 break; 4198 case e1000_ich8lan: 4199 case e1000_ich9lan: 4200 case e1000_ich10lan: 4201 case e1000_pchlan: 4202 case e1000_pch2lan: 4203 case e1000_pch_lpt: 4204 case e1000_pch_spt: 4205 case e1000_82575: /* listing all igb devices */ 4206 case e1000_82576: 4207 case e1000_82580: 4208 case e1000_i350: 4209 case e1000_i354: 4210 case e1000_i210: 4211 case e1000_i211: 4212 case e1000_vfadapt: 4213 case e1000_vfadapt_i350: 4214 apme_mask = E1000_WUC_APME; 4215 sc->has_amt = true; 4216 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4217 break; 4218 default: 4219 e1000_read_nvm(&sc->hw, 4220 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4221 break; 4222 } 4223 if (eeprom_data & apme_mask) 4224 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4225 /* 4226 * We have the eeprom settings, now apply the special cases 4227 * where the eeprom may be wrong or the board won't support 4228 * wake on lan on a particular port 4229 */ 4230 device_id = pci_get_device(dev); 4231 switch (device_id) { 4232 case E1000_DEV_ID_82546GB_PCIE: 4233 sc->wol = 0; 4234 break; 4235 case E1000_DEV_ID_82546EB_FIBER: 4236 case E1000_DEV_ID_82546GB_FIBER: 4237 /* Wake events only supported on port A for dual fiber 4238 * regardless of eeprom setting */ 4239 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4240 E1000_STATUS_FUNC_1) 4241 sc->wol = 0; 4242 break; 4243 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4244 /* if quad port adapter, disable WoL on all but port A */ 4245 if (global_quad_port_a != 0) 4246 sc->wol = 0; 4247 /* Reset for multiple quad port adapters */ 4248 if (++global_quad_port_a == 4) 4249 global_quad_port_a = 0; 4250 break; 4251 case E1000_DEV_ID_82571EB_FIBER: 4252 /* Wake events only supported on port A for dual fiber 4253 * regardless of eeprom setting */ 4254 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4255 E1000_STATUS_FUNC_1) 4256 sc->wol = 0; 4257 break; 4258 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4259 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4260 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4261 /* if quad port adapter, disable WoL on all but port A */ 4262 if (global_quad_port_a != 0) 4263 sc->wol = 0; 4264 /* Reset for multiple quad port adapters */ 4265 if (++global_quad_port_a == 4) 4266 global_quad_port_a = 0; 4267 break; 4268 } 4269 return; 4270 } 4271 4272 4273 /* 4274 * Enable PCI Wake On Lan capability 4275 */ 4276 static void 4277 em_enable_wakeup(if_ctx_t ctx) 4278 { 4279 struct e1000_softc *sc = iflib_get_softc(ctx); 4280 device_t dev = iflib_get_dev(ctx); 4281 if_t ifp = iflib_get_ifp(ctx); 4282 int error = 0; 4283 u32 pmc, ctrl, ctrl_ext, rctl; 4284 u16 status; 4285 4286 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4287 return; 4288 4289 /* 4290 * Determine type of Wakeup: note that wol 4291 * is set with all bits on by default. 4292 */ 4293 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4294 sc->wol &= ~E1000_WUFC_MAG; 4295 4296 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4297 sc->wol &= ~E1000_WUFC_EX; 4298 4299 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4300 sc->wol &= ~E1000_WUFC_MC; 4301 else { 4302 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4303 rctl |= E1000_RCTL_MPE; 4304 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4305 } 4306 4307 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4308 goto pme; 4309 4310 /* Advertise the wakeup capability */ 4311 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4312 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4313 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4314 4315 /* Keep the laser running on Fiber adapters */ 4316 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4317 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4318 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4319 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4320 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4321 } 4322 4323 if ((sc->hw.mac.type == e1000_ich8lan) || 4324 (sc->hw.mac.type == e1000_pchlan) || 4325 (sc->hw.mac.type == e1000_ich9lan) || 4326 (sc->hw.mac.type == e1000_ich10lan)) 4327 e1000_suspend_workarounds_ich8lan(&sc->hw); 4328 4329 if ( sc->hw.mac.type >= e1000_pchlan) { 4330 error = em_enable_phy_wakeup(sc); 4331 if (error) 4332 goto pme; 4333 } else { 4334 /* Enable wakeup by the MAC */ 4335 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4336 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4337 } 4338 4339 if (sc->hw.phy.type == e1000_phy_igp_3) 4340 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4341 4342 pme: 4343 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4344 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4345 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4346 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4347 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4348 4349 return; 4350 } 4351 4352 /* 4353 * WOL in the newer chipset interfaces (pchlan) 4354 * require thing to be copied into the phy 4355 */ 4356 static int 4357 em_enable_phy_wakeup(struct e1000_softc *sc) 4358 { 4359 struct e1000_hw *hw = &sc->hw; 4360 u32 mreg, ret = 0; 4361 u16 preg; 4362 4363 /* copy MAC RARs to PHY RARs */ 4364 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4365 4366 /* copy MAC MTA to PHY MTA */ 4367 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4368 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4369 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4370 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4371 (u16)((mreg >> 16) & 0xFFFF)); 4372 } 4373 4374 /* configure PHY Rx Control register */ 4375 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4376 mreg = E1000_READ_REG(hw, E1000_RCTL); 4377 if (mreg & E1000_RCTL_UPE) 4378 preg |= BM_RCTL_UPE; 4379 if (mreg & E1000_RCTL_MPE) 4380 preg |= BM_RCTL_MPE; 4381 preg &= ~(BM_RCTL_MO_MASK); 4382 if (mreg & E1000_RCTL_MO_3) 4383 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4384 << BM_RCTL_MO_SHIFT); 4385 if (mreg & E1000_RCTL_BAM) 4386 preg |= BM_RCTL_BAM; 4387 if (mreg & E1000_RCTL_PMCF) 4388 preg |= BM_RCTL_PMCF; 4389 mreg = E1000_READ_REG(hw, E1000_CTRL); 4390 if (mreg & E1000_CTRL_RFCE) 4391 preg |= BM_RCTL_RFCE; 4392 e1000_write_phy_reg(hw, BM_RCTL, preg); 4393 4394 /* enable PHY wakeup in MAC register */ 4395 E1000_WRITE_REG(hw, E1000_WUC, 4396 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4397 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4398 4399 /* configure and enable PHY wakeup in PHY registers */ 4400 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4401 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4402 4403 /* activate PHY wakeup */ 4404 ret = hw->phy.ops.acquire(hw); 4405 if (ret) { 4406 printf("Could not acquire PHY\n"); 4407 return ret; 4408 } 4409 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4410 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4411 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4412 if (ret) { 4413 printf("Could not read PHY page 769\n"); 4414 goto out; 4415 } 4416 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4417 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4418 if (ret) 4419 printf("Could not set PHY Host Wakeup bit\n"); 4420 out: 4421 hw->phy.ops.release(hw); 4422 4423 return ret; 4424 } 4425 4426 static void 4427 em_if_led_func(if_ctx_t ctx, int onoff) 4428 { 4429 struct e1000_softc *sc = iflib_get_softc(ctx); 4430 4431 if (onoff) { 4432 e1000_setup_led(&sc->hw); 4433 e1000_led_on(&sc->hw); 4434 } else { 4435 e1000_led_off(&sc->hw); 4436 e1000_cleanup_led(&sc->hw); 4437 } 4438 } 4439 4440 /* 4441 * Disable the L0S and L1 LINK states 4442 */ 4443 static void 4444 em_disable_aspm(struct e1000_softc *sc) 4445 { 4446 int base, reg; 4447 u16 link_cap,link_ctrl; 4448 device_t dev = sc->dev; 4449 4450 switch (sc->hw.mac.type) { 4451 case e1000_82573: 4452 case e1000_82574: 4453 case e1000_82583: 4454 break; 4455 default: 4456 return; 4457 } 4458 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4459 return; 4460 reg = base + PCIER_LINK_CAP; 4461 link_cap = pci_read_config(dev, reg, 2); 4462 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4463 return; 4464 reg = base + PCIER_LINK_CTL; 4465 link_ctrl = pci_read_config(dev, reg, 2); 4466 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4467 pci_write_config(dev, reg, link_ctrl, 2); 4468 return; 4469 } 4470 4471 /********************************************************************** 4472 * 4473 * Update the board statistics counters. 4474 * 4475 **********************************************************************/ 4476 static void 4477 em_update_stats_counters(struct e1000_softc *sc) 4478 { 4479 u64 prev_xoffrxc = sc->stats.xoffrxc; 4480 4481 if(sc->hw.phy.media_type == e1000_media_type_copper || 4482 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4483 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4484 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4485 } 4486 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4487 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4488 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4489 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4490 4491 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4492 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4493 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4494 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4495 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4496 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4497 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4498 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4499 /* 4500 ** For watchdog management we need to know if we have been 4501 ** paused during the last interval, so capture that here. 4502 */ 4503 if (sc->stats.xoffrxc != prev_xoffrxc) 4504 sc->shared->isc_pause_frames = 1; 4505 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4506 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4507 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4508 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4509 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4510 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4511 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4512 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4513 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4514 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4515 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4516 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4517 4518 /* For the 64-bit byte counters the low dword must be read first. */ 4519 /* Both registers clear on the read of the high dword */ 4520 4521 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4522 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4523 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4524 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4525 4526 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4527 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4528 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4529 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4530 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4531 4532 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4533 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4534 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4535 4536 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4537 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4538 4539 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4540 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4541 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4542 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4543 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4544 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4545 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4546 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4547 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4548 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4549 4550 /* Interrupt Counts */ 4551 4552 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4553 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4554 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4555 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4556 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4557 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4558 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4559 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4560 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4561 4562 if (sc->hw.mac.type >= e1000_82543) { 4563 sc->stats.algnerrc += 4564 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4565 sc->stats.rxerrc += 4566 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4567 sc->stats.tncrs += 4568 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4569 sc->stats.cexterr += 4570 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4571 sc->stats.tsctc += 4572 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4573 sc->stats.tsctfc += 4574 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4575 } 4576 } 4577 4578 static uint64_t 4579 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4580 { 4581 struct e1000_softc *sc = iflib_get_softc(ctx); 4582 if_t ifp = iflib_get_ifp(ctx); 4583 4584 switch (cnt) { 4585 case IFCOUNTER_COLLISIONS: 4586 return (sc->stats.colc); 4587 case IFCOUNTER_IERRORS: 4588 return (sc->dropped_pkts + sc->stats.rxerrc + 4589 sc->stats.crcerrs + sc->stats.algnerrc + 4590 sc->stats.ruc + sc->stats.roc + 4591 sc->stats.mpc + sc->stats.cexterr); 4592 case IFCOUNTER_OERRORS: 4593 return (sc->stats.ecol + sc->stats.latecol + 4594 sc->watchdog_events); 4595 default: 4596 return (if_get_counter_default(ifp, cnt)); 4597 } 4598 } 4599 4600 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4601 * @ctx: iflib context 4602 * @event: event code to check 4603 * 4604 * Defaults to returning false for unknown events. 4605 * 4606 * @returns true if iflib needs to reinit the interface 4607 */ 4608 static bool 4609 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4610 { 4611 switch (event) { 4612 case IFLIB_RESTART_VLAN_CONFIG: 4613 default: 4614 return (false); 4615 } 4616 } 4617 4618 /* Export a single 32-bit register via a read-only sysctl. */ 4619 static int 4620 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4621 { 4622 struct e1000_softc *sc; 4623 u_int val; 4624 4625 sc = oidp->oid_arg1; 4626 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4627 return (sysctl_handle_int(oidp, &val, 0, req)); 4628 } 4629 4630 /* Per queue holdoff interrupt rate handler */ 4631 static int 4632 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4633 { 4634 struct em_rx_queue *rque; 4635 struct em_tx_queue *tque; 4636 struct e1000_hw *hw; 4637 int error; 4638 u32 reg, usec, rate; 4639 4640 bool tx = oidp->oid_arg2; 4641 4642 if (tx) { 4643 tque = oidp->oid_arg1; 4644 hw = &tque->sc->hw; 4645 if (hw->mac.type >= igb_mac_min) 4646 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4647 else if (hw->mac.type == e1000_82574 && tque->msix) 4648 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4649 else 4650 reg = E1000_READ_REG(hw, E1000_ITR); 4651 } else { 4652 rque = oidp->oid_arg1; 4653 hw = &rque->sc->hw; 4654 if (hw->mac.type >= igb_mac_min) 4655 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4656 else if (hw->mac.type == e1000_82574 && rque->msix) 4657 reg = E1000_READ_REG(hw, E1000_EITR_82574(rque->msix)); 4658 else 4659 reg = E1000_READ_REG(hw, E1000_ITR); 4660 } 4661 4662 if (hw->mac.type < igb_mac_min) { 4663 if (reg > 0) 4664 rate = EM_INTS_TO_ITR(reg); 4665 else 4666 rate = 0; 4667 } else { 4668 usec = (reg & IGB_QVECTOR_MASK); 4669 if (usec > 0) 4670 rate = IGB_INTS_TO_EITR(usec); 4671 else 4672 rate = 0; 4673 } 4674 4675 error = sysctl_handle_int(oidp, &rate, 0, req); 4676 if (error || !req->newptr) 4677 return error; 4678 return 0; 4679 } 4680 4681 /* 4682 * Add sysctl variables, one per statistic, to the system. 4683 */ 4684 static void 4685 em_add_hw_stats(struct e1000_softc *sc) 4686 { 4687 device_t dev = iflib_get_dev(sc->ctx); 4688 struct em_tx_queue *tx_que = sc->tx_queues; 4689 struct em_rx_queue *rx_que = sc->rx_queues; 4690 4691 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4692 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4693 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4694 struct e1000_hw_stats *stats = &sc->stats; 4695 4696 struct sysctl_oid *stat_node, *queue_node, *int_node; 4697 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4698 4699 #define QUEUE_NAME_LEN 32 4700 char namebuf[QUEUE_NAME_LEN]; 4701 4702 /* Driver Statistics */ 4703 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4704 CTLFLAG_RD, &sc->dropped_pkts, 4705 "Driver dropped packets"); 4706 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4707 CTLFLAG_RD, &sc->link_irq, 4708 "Link MSI-X IRQ Handled"); 4709 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4710 CTLFLAG_RD, &sc->rx_overruns, 4711 "RX overruns"); 4712 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4713 CTLFLAG_RD, &sc->watchdog_events, 4714 "Watchdog timeouts"); 4715 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4716 CTLTYPE_UINT | CTLFLAG_RD, 4717 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4718 "Device Control Register"); 4719 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4720 CTLTYPE_UINT | CTLFLAG_RD, 4721 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4722 "Receiver Control Register"); 4723 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4724 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4725 "Flow Control High Watermark"); 4726 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4727 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4728 "Flow Control Low Watermark"); 4729 4730 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4731 struct tx_ring *txr = &tx_que->txr; 4732 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4733 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4734 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4735 queue_list = SYSCTL_CHILDREN(queue_node); 4736 4737 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4738 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4739 true, em_sysctl_interrupt_rate_handler, 4740 "IU", "Interrupt Rate"); 4741 4742 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4743 CTLTYPE_UINT | CTLFLAG_RD, sc, 4744 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4745 "Transmit Descriptor Head"); 4746 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4747 CTLTYPE_UINT | CTLFLAG_RD, sc, 4748 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4749 "Transmit Descriptor Tail"); 4750 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4751 CTLFLAG_RD, &txr->tx_irq, 4752 "Queue MSI-X Transmit Interrupts"); 4753 } 4754 4755 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4756 struct rx_ring *rxr = &rx_que->rxr; 4757 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4758 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4759 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4760 queue_list = SYSCTL_CHILDREN(queue_node); 4761 4762 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4763 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 4764 false, em_sysctl_interrupt_rate_handler, 4765 "IU", "Interrupt Rate"); 4766 4767 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4768 CTLTYPE_UINT | CTLFLAG_RD, sc, 4769 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4770 "Receive Descriptor Head"); 4771 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4772 CTLTYPE_UINT | CTLFLAG_RD, sc, 4773 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4774 "Receive Descriptor Tail"); 4775 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4776 CTLFLAG_RD, &rxr->rx_irq, 4777 "Queue MSI-X Receive Interrupts"); 4778 } 4779 4780 /* MAC stats get their own sub node */ 4781 4782 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4783 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4784 stat_list = SYSCTL_CHILDREN(stat_node); 4785 4786 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4787 CTLFLAG_RD, &stats->ecol, 4788 "Excessive collisions"); 4789 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4790 CTLFLAG_RD, &stats->scc, 4791 "Single collisions"); 4792 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4793 CTLFLAG_RD, &stats->mcc, 4794 "Multiple collisions"); 4795 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4796 CTLFLAG_RD, &stats->latecol, 4797 "Late collisions"); 4798 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4799 CTLFLAG_RD, &stats->colc, 4800 "Collision Count"); 4801 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4802 CTLFLAG_RD, &sc->stats.symerrs, 4803 "Symbol Errors"); 4804 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4805 CTLFLAG_RD, &sc->stats.sec, 4806 "Sequence Errors"); 4807 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4808 CTLFLAG_RD, &sc->stats.dc, 4809 "Defer Count"); 4810 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4811 CTLFLAG_RD, &sc->stats.mpc, 4812 "Missed Packets"); 4813 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 4814 CTLFLAG_RD, &sc->stats.rlec, 4815 "Receive Length Errors"); 4816 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4817 CTLFLAG_RD, &sc->stats.rnbc, 4818 "Receive No Buffers"); 4819 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4820 CTLFLAG_RD, &sc->stats.ruc, 4821 "Receive Undersize"); 4822 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4823 CTLFLAG_RD, &sc->stats.rfc, 4824 "Fragmented Packets Received "); 4825 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4826 CTLFLAG_RD, &sc->stats.roc, 4827 "Oversized Packets Received"); 4828 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4829 CTLFLAG_RD, &sc->stats.rjc, 4830 "Recevied Jabber"); 4831 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4832 CTLFLAG_RD, &sc->stats.rxerrc, 4833 "Receive Errors"); 4834 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4835 CTLFLAG_RD, &sc->stats.crcerrs, 4836 "CRC errors"); 4837 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4838 CTLFLAG_RD, &sc->stats.algnerrc, 4839 "Alignment Errors"); 4840 /* On 82575 these are collision counts */ 4841 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4842 CTLFLAG_RD, &sc->stats.cexterr, 4843 "Collision/Carrier extension errors"); 4844 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4845 CTLFLAG_RD, &sc->stats.xonrxc, 4846 "XON Received"); 4847 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4848 CTLFLAG_RD, &sc->stats.xontxc, 4849 "XON Transmitted"); 4850 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4851 CTLFLAG_RD, &sc->stats.xoffrxc, 4852 "XOFF Received"); 4853 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4854 CTLFLAG_RD, &sc->stats.xofftxc, 4855 "XOFF Transmitted"); 4856 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 4857 CTLFLAG_RD, &sc->stats.fcruc, 4858 "Unsupported Flow Control Received"); 4859 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 4860 CTLFLAG_RD, &sc->stats.mgprc, 4861 "Management Packets Received"); 4862 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 4863 CTLFLAG_RD, &sc->stats.mgpdc, 4864 "Management Packets Dropped"); 4865 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 4866 CTLFLAG_RD, &sc->stats.mgptc, 4867 "Management Packets Transmitted"); 4868 4869 /* Packet Reception Stats */ 4870 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4871 CTLFLAG_RD, &sc->stats.tpr, 4872 "Total Packets Received "); 4873 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4874 CTLFLAG_RD, &sc->stats.gprc, 4875 "Good Packets Received"); 4876 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4877 CTLFLAG_RD, &sc->stats.bprc, 4878 "Broadcast Packets Received"); 4879 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4880 CTLFLAG_RD, &sc->stats.mprc, 4881 "Multicast Packets Received"); 4882 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4883 CTLFLAG_RD, &sc->stats.prc64, 4884 "64 byte frames received "); 4885 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4886 CTLFLAG_RD, &sc->stats.prc127, 4887 "65-127 byte frames received"); 4888 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4889 CTLFLAG_RD, &sc->stats.prc255, 4890 "128-255 byte frames received"); 4891 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4892 CTLFLAG_RD, &sc->stats.prc511, 4893 "256-511 byte frames received"); 4894 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4895 CTLFLAG_RD, &sc->stats.prc1023, 4896 "512-1023 byte frames received"); 4897 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4898 CTLFLAG_RD, &sc->stats.prc1522, 4899 "1023-1522 byte frames received"); 4900 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4901 CTLFLAG_RD, &sc->stats.gorc, 4902 "Good Octets Received"); 4903 4904 /* Packet Transmission Stats */ 4905 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4906 CTLFLAG_RD, &sc->stats.gotc, 4907 "Good Octets Transmitted"); 4908 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4909 CTLFLAG_RD, &sc->stats.tpt, 4910 "Total Packets Transmitted"); 4911 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4912 CTLFLAG_RD, &sc->stats.gptc, 4913 "Good Packets Transmitted"); 4914 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4915 CTLFLAG_RD, &sc->stats.bptc, 4916 "Broadcast Packets Transmitted"); 4917 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4918 CTLFLAG_RD, &sc->stats.mptc, 4919 "Multicast Packets Transmitted"); 4920 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4921 CTLFLAG_RD, &sc->stats.ptc64, 4922 "64 byte frames transmitted "); 4923 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4924 CTLFLAG_RD, &sc->stats.ptc127, 4925 "65-127 byte frames transmitted"); 4926 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4927 CTLFLAG_RD, &sc->stats.ptc255, 4928 "128-255 byte frames transmitted"); 4929 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4930 CTLFLAG_RD, &sc->stats.ptc511, 4931 "256-511 byte frames transmitted"); 4932 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4933 CTLFLAG_RD, &sc->stats.ptc1023, 4934 "512-1023 byte frames transmitted"); 4935 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4936 CTLFLAG_RD, &sc->stats.ptc1522, 4937 "1024-1522 byte frames transmitted"); 4938 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4939 CTLFLAG_RD, &sc->stats.tsctc, 4940 "TSO Contexts Transmitted"); 4941 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4942 CTLFLAG_RD, &sc->stats.tsctfc, 4943 "TSO Contexts Failed"); 4944 4945 4946 /* Interrupt Stats */ 4947 4948 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4949 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4950 int_list = SYSCTL_CHILDREN(int_node); 4951 4952 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4953 CTLFLAG_RD, &sc->stats.iac, 4954 "Interrupt Assertion Count"); 4955 4956 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4957 CTLFLAG_RD, &sc->stats.icrxptc, 4958 "Interrupt Cause Rx Pkt Timer Expire Count"); 4959 4960 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4961 CTLFLAG_RD, &sc->stats.icrxatc, 4962 "Interrupt Cause Rx Abs Timer Expire Count"); 4963 4964 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4965 CTLFLAG_RD, &sc->stats.ictxptc, 4966 "Interrupt Cause Tx Pkt Timer Expire Count"); 4967 4968 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4969 CTLFLAG_RD, &sc->stats.ictxatc, 4970 "Interrupt Cause Tx Abs Timer Expire Count"); 4971 4972 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4973 CTLFLAG_RD, &sc->stats.ictxqec, 4974 "Interrupt Cause Tx Queue Empty Count"); 4975 4976 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4977 CTLFLAG_RD, &sc->stats.ictxqmtc, 4978 "Interrupt Cause Tx Queue Min Thresh Count"); 4979 4980 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4981 CTLFLAG_RD, &sc->stats.icrxdmtc, 4982 "Interrupt Cause Rx Desc Min Thresh Count"); 4983 4984 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4985 CTLFLAG_RD, &sc->stats.icrxoc, 4986 "Interrupt Cause Receiver Overrun Count"); 4987 } 4988 4989 static void 4990 em_fw_version_locked(if_ctx_t ctx) 4991 { 4992 struct e1000_softc *sc = iflib_get_softc(ctx); 4993 struct e1000_hw *hw = &sc->hw; 4994 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4995 uint16_t eep = 0; 4996 4997 /* 4998 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4999 * NVM locking model, so we do it in em_if_attach_pre() and store the 5000 * info in the softc 5001 */ 5002 ASSERT_CTX_LOCK_HELD(hw); 5003 5004 *fw_ver = (struct e1000_fw_version){0}; 5005 5006 if (hw->mac.type >= igb_mac_min) { 5007 /* 5008 * Use the Shared Code for igb(4) 5009 */ 5010 e1000_get_fw_version(hw, fw_ver); 5011 } else { 5012 /* 5013 * Otherwise, EEPROM version should be present on (almost?) all 5014 * devices here 5015 */ 5016 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5017 INIT_DEBUGOUT("can't get EEPROM version"); 5018 return; 5019 } 5020 5021 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5022 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5023 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5024 } 5025 } 5026 5027 static void 5028 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5029 { 5030 const char *space = ""; 5031 5032 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5033 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5034 fw_ver->eep_minor, fw_ver->eep_build); 5035 space = " "; 5036 } 5037 5038 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 5039 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5040 space, fw_ver->invm_major, fw_ver->invm_minor, 5041 fw_ver->invm_img_type); 5042 space = " "; 5043 } 5044 5045 if (fw_ver->or_valid) { 5046 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5047 space, fw_ver->or_major, fw_ver->or_build, 5048 fw_ver->or_patch); 5049 space = " "; 5050 } 5051 5052 if (fw_ver->etrack_id) 5053 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5054 } 5055 5056 static void 5057 em_print_fw_version(struct e1000_softc *sc ) 5058 { 5059 device_t dev = sc->dev; 5060 struct sbuf *buf; 5061 int error = 0; 5062 5063 buf = sbuf_new_auto(); 5064 if (!buf) { 5065 device_printf(dev, "Could not allocate sbuf for output.\n"); 5066 return; 5067 } 5068 5069 em_sbuf_fw_version(&sc->fw_ver, buf); 5070 5071 error = sbuf_finish(buf); 5072 if (error) 5073 device_printf(dev, "Error finishing sbuf: %d\n", error); 5074 else if (sbuf_len(buf)) 5075 device_printf(dev, "%s\n", sbuf_data(buf)); 5076 5077 sbuf_delete(buf); 5078 } 5079 5080 static int 5081 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5082 { 5083 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5084 device_t dev = sc->dev; 5085 struct sbuf *buf; 5086 int error = 0; 5087 5088 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5089 if (!buf) { 5090 device_printf(dev, "Could not allocate sbuf for output.\n"); 5091 return (ENOMEM); 5092 } 5093 5094 em_sbuf_fw_version(&sc->fw_ver, buf); 5095 5096 error = sbuf_finish(buf); 5097 if (error) 5098 device_printf(dev, "Error finishing sbuf: %d\n", error); 5099 5100 sbuf_delete(buf); 5101 5102 return (0); 5103 } 5104 5105 /********************************************************************** 5106 * 5107 * This routine provides a way to dump out the adapter eeprom, 5108 * often a useful debug/service tool. This only dumps the first 5109 * 32 words, stuff that matters is in that extent. 5110 * 5111 **********************************************************************/ 5112 static int 5113 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5114 { 5115 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5116 int error; 5117 int result; 5118 5119 result = -1; 5120 error = sysctl_handle_int(oidp, &result, 0, req); 5121 5122 if (error || !req->newptr) 5123 return (error); 5124 5125 /* 5126 * This value will cause a hex dump of the 5127 * first 32 16-bit words of the EEPROM to 5128 * the screen. 5129 */ 5130 if (result == 1) 5131 em_print_nvm_info(sc); 5132 5133 return (error); 5134 } 5135 5136 static void 5137 em_print_nvm_info(struct e1000_softc *sc) 5138 { 5139 struct e1000_hw *hw = &sc->hw; 5140 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5141 u16 eeprom_data; 5142 int i, j, row = 0; 5143 5144 /* Its a bit crude, but it gets the job done */ 5145 printf("\nInterface EEPROM Dump:\n"); 5146 printf("Offset\n0x0000 "); 5147 5148 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5149 sx_xlock(iflib_ctx_lock); 5150 ASSERT_CTX_LOCK_HELD(hw); 5151 for (i = 0, j = 0; i < 32; i++, j++) { 5152 if (j == 8) { /* Make the offset block */ 5153 j = 0; ++row; 5154 printf("\n0x00%x0 ",row); 5155 } 5156 e1000_read_nvm(hw, i, 1, &eeprom_data); 5157 printf("%04x ", eeprom_data); 5158 } 5159 sx_xunlock(iflib_ctx_lock); 5160 printf("\n"); 5161 } 5162 5163 static int 5164 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5165 { 5166 struct em_int_delay_info *info; 5167 struct e1000_softc *sc; 5168 u32 regval; 5169 int error, usecs, ticks; 5170 5171 info = (struct em_int_delay_info *) arg1; 5172 usecs = info->value; 5173 error = sysctl_handle_int(oidp, &usecs, 0, req); 5174 if (error != 0 || req->newptr == NULL) 5175 return (error); 5176 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5177 return (EINVAL); 5178 info->value = usecs; 5179 ticks = EM_USECS_TO_TICKS(usecs); 5180 if (info->offset == E1000_ITR) /* units are 256ns here */ 5181 ticks *= 4; 5182 5183 sc = info->sc; 5184 5185 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5186 regval = (regval & ~0xffff) | (ticks & 0xffff); 5187 /* Handle a few special cases. */ 5188 switch (info->offset) { 5189 case E1000_RDTR: 5190 break; 5191 case E1000_TIDV: 5192 if (ticks == 0) { 5193 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5194 /* Don't write 0 into the TIDV register. */ 5195 regval++; 5196 } else 5197 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5198 break; 5199 } 5200 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5201 return (0); 5202 } 5203 5204 static int 5205 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5206 { 5207 struct e1000_softc *sc; 5208 u32 reg, val, shift; 5209 int error, mask; 5210 5211 sc = oidp->oid_arg1; 5212 switch (oidp->oid_arg2) { 5213 case 0: 5214 reg = E1000_DTXTCPFLGL; 5215 shift = 0; 5216 break; 5217 case 1: 5218 reg = E1000_DTXTCPFLGL; 5219 shift = 16; 5220 break; 5221 case 2: 5222 reg = E1000_DTXTCPFLGH; 5223 shift = 0; 5224 break; 5225 default: 5226 return (EINVAL); 5227 break; 5228 } 5229 val = E1000_READ_REG(&sc->hw, reg); 5230 mask = (val >> shift) & 0xfff; 5231 error = sysctl_handle_int(oidp, &mask, 0, req); 5232 if (error != 0 || req->newptr == NULL) 5233 return (error); 5234 if (mask < 0 || mask > 0xfff) 5235 return (EINVAL); 5236 val = (val & ~(0xfff << shift)) | (mask << shift); 5237 E1000_WRITE_REG(&sc->hw, reg, val); 5238 return (0); 5239 } 5240 5241 static void 5242 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5243 const char *description, struct em_int_delay_info *info, 5244 int offset, int value) 5245 { 5246 info->sc = sc; 5247 info->offset = offset; 5248 info->value = value; 5249 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5250 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5251 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5252 info, 0, em_sysctl_int_delay, "I", description); 5253 } 5254 5255 /* 5256 * Set flow control using sysctl: 5257 * Flow control values: 5258 * 0 - off 5259 * 1 - rx pause 5260 * 2 - tx pause 5261 * 3 - full 5262 */ 5263 static int 5264 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5265 { 5266 int error; 5267 static int input = 3; /* default is full */ 5268 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5269 5270 error = sysctl_handle_int(oidp, &input, 0, req); 5271 5272 if ((error) || (req->newptr == NULL)) 5273 return (error); 5274 5275 if (input == sc->fc) /* no change? */ 5276 return (error); 5277 5278 switch (input) { 5279 case e1000_fc_rx_pause: 5280 case e1000_fc_tx_pause: 5281 case e1000_fc_full: 5282 case e1000_fc_none: 5283 sc->hw.fc.requested_mode = input; 5284 sc->fc = input; 5285 break; 5286 default: 5287 /* Do nothing */ 5288 return (error); 5289 } 5290 5291 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5292 e1000_force_mac_fc(&sc->hw); 5293 return (error); 5294 } 5295 5296 /* 5297 * Manage DMA Coalesce: 5298 * Control values: 5299 * 0/1 - off/on 5300 * Legal timer values are: 5301 * 250,500,1000-10000 in thousands 5302 */ 5303 static int 5304 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5305 { 5306 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5307 int error; 5308 5309 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5310 5311 if ((error) || (req->newptr == NULL)) 5312 return (error); 5313 5314 switch (sc->dmac) { 5315 case 0: 5316 /* Disabling */ 5317 break; 5318 case 1: /* Just enable and use default */ 5319 sc->dmac = 1000; 5320 break; 5321 case 250: 5322 case 500: 5323 case 1000: 5324 case 2000: 5325 case 3000: 5326 case 4000: 5327 case 5000: 5328 case 6000: 5329 case 7000: 5330 case 8000: 5331 case 9000: 5332 case 10000: 5333 /* Legal values - allow */ 5334 break; 5335 default: 5336 /* Do nothing, illegal value */ 5337 sc->dmac = 0; 5338 return (EINVAL); 5339 } 5340 /* Reinit the interface */ 5341 em_if_init(sc->ctx); 5342 return (error); 5343 } 5344 5345 /* 5346 * Manage Energy Efficient Ethernet: 5347 * Control values: 5348 * 0/1 - enabled/disabled 5349 */ 5350 static int 5351 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5352 { 5353 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5354 int error, value; 5355 5356 if (sc->hw.mac.type < igb_mac_min) 5357 value = sc->hw.dev_spec.ich8lan.eee_disable; 5358 else 5359 value = sc->hw.dev_spec._82575.eee_disable; 5360 error = sysctl_handle_int(oidp, &value, 0, req); 5361 if (error || req->newptr == NULL) 5362 return (error); 5363 if (sc->hw.mac.type < igb_mac_min) 5364 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5365 else 5366 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5367 em_if_init(sc->ctx); 5368 5369 return (0); 5370 } 5371 5372 static int 5373 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5374 { 5375 struct e1000_softc *sc; 5376 int error; 5377 int result; 5378 5379 result = -1; 5380 error = sysctl_handle_int(oidp, &result, 0, req); 5381 5382 if (error || !req->newptr) 5383 return (error); 5384 5385 if (result == 1) { 5386 sc = (struct e1000_softc *) arg1; 5387 em_print_debug_info(sc); 5388 } 5389 5390 return (error); 5391 } 5392 5393 static int 5394 em_get_rs(SYSCTL_HANDLER_ARGS) 5395 { 5396 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5397 int error; 5398 int result; 5399 5400 result = 0; 5401 error = sysctl_handle_int(oidp, &result, 0, req); 5402 5403 if (error || !req->newptr || result != 1) 5404 return (error); 5405 em_dump_rs(sc); 5406 5407 return (error); 5408 } 5409 5410 static void 5411 em_if_debug(if_ctx_t ctx) 5412 { 5413 em_dump_rs(iflib_get_softc(ctx)); 5414 } 5415 5416 /* 5417 * This routine is meant to be fluid, add whatever is 5418 * needed for debugging a problem. -jfv 5419 */ 5420 static void 5421 em_print_debug_info(struct e1000_softc *sc) 5422 { 5423 device_t dev = iflib_get_dev(sc->ctx); 5424 if_t ifp = iflib_get_ifp(sc->ctx); 5425 struct tx_ring *txr = &sc->tx_queues->txr; 5426 struct rx_ring *rxr = &sc->rx_queues->rxr; 5427 5428 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5429 printf("Interface is RUNNING "); 5430 else 5431 printf("Interface is NOT RUNNING\n"); 5432 5433 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5434 printf("and INACTIVE\n"); 5435 else 5436 printf("and ACTIVE\n"); 5437 5438 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5439 device_printf(dev, "TX Queue %d ------\n", i); 5440 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5441 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5442 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5443 5444 } 5445 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5446 device_printf(dev, "RX Queue %d ------\n", j); 5447 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5448 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5449 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5450 } 5451 } 5452 5453 /* 5454 * 82574 only: 5455 * Write a new value to the EEPROM increasing the number of MSI-X 5456 * vectors from 3 to 5, for proper multiqueue support. 5457 */ 5458 static void 5459 em_enable_vectors_82574(if_ctx_t ctx) 5460 { 5461 struct e1000_softc *sc = iflib_get_softc(ctx); 5462 struct e1000_hw *hw = &sc->hw; 5463 device_t dev = iflib_get_dev(ctx); 5464 u16 edata; 5465 5466 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5467 if (bootverbose) 5468 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5469 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5470 device_printf(dev, "Writing to eeprom: increasing " 5471 "reported MSI-X vectors from 3 to 5...\n"); 5472 edata &= ~(EM_NVM_MSIX_N_MASK); 5473 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5474 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5475 e1000_update_nvm_checksum(hw); 5476 device_printf(dev, "Writing to eeprom: done\n"); 5477 } 5478 } 5479