1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 411 static void em_if_init(if_ctx_t); 412 static void em_if_stop(if_ctx_t); 413 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 414 static int em_if_media_change(if_ctx_t); 415 static int em_if_mtu_set(if_ctx_t, uint32_t); 416 static void em_if_timer(if_ctx_t, uint16_t); 417 static void em_if_vlan_register(if_ctx_t, u16); 418 static void em_if_vlan_unregister(if_ctx_t, u16); 419 static void em_if_watchdog_reset(if_ctx_t); 420 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 421 422 static void em_identify_hardware(if_ctx_t); 423 static int em_allocate_pci_resources(if_ctx_t); 424 static void em_free_pci_resources(if_ctx_t); 425 static void em_reset(if_ctx_t); 426 static int em_setup_interface(if_ctx_t); 427 static int em_setup_msix(if_ctx_t); 428 429 static void em_initialize_transmit_unit(if_ctx_t); 430 static void em_initialize_receive_unit(if_ctx_t); 431 432 static void em_if_intr_enable(if_ctx_t); 433 static void em_if_intr_disable(if_ctx_t); 434 static void igb_if_intr_enable(if_ctx_t); 435 static void igb_if_intr_disable(if_ctx_t); 436 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 437 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 440 static void em_if_multi_set(if_ctx_t); 441 static void em_if_update_admin_status(if_ctx_t); 442 static void em_if_debug(if_ctx_t); 443 static void em_update_stats_counters(struct e1000_softc *); 444 static void em_add_hw_stats(struct e1000_softc *); 445 static int em_if_set_promisc(if_ctx_t, int); 446 static bool em_if_vlan_filter_capable(if_ctx_t); 447 static bool em_if_vlan_filter_used(if_ctx_t); 448 static void em_if_vlan_filter_enable(struct e1000_softc *); 449 static void em_if_vlan_filter_disable(struct e1000_softc *); 450 static void em_if_vlan_filter_write(struct e1000_softc *); 451 static void em_setup_vlan_hw_support(if_ctx_t ctx); 452 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 453 static void em_print_nvm_info(struct e1000_softc *); 454 static void em_fw_version_locked(if_ctx_t); 455 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 456 static void em_print_fw_version(struct e1000_softc *); 457 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 458 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 459 static int em_get_rs(SYSCTL_HANDLER_ARGS); 460 static void em_print_debug_info(struct e1000_softc *); 461 static int em_is_valid_ether_addr(u8 *); 462 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 463 struct tx_ring *, struct rx_ring *); 464 static bool em_automask_tso(if_ctx_t); 465 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 466 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 467 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 468 const char *, struct em_int_delay_info *, int, int); 469 /* Management and WOL Support */ 470 static void em_init_manageability(struct e1000_softc *); 471 static void em_release_manageability(struct e1000_softc *); 472 static void em_get_hw_control(struct e1000_softc *); 473 static void em_release_hw_control(struct e1000_softc *); 474 static void em_get_wakeup(if_ctx_t); 475 static void em_enable_wakeup(if_ctx_t); 476 static int em_enable_phy_wakeup(struct e1000_softc *); 477 static void em_disable_aspm(struct e1000_softc *); 478 479 int em_intr(void *); 480 481 /* MSI-X handlers */ 482 static int em_if_msix_intr_assign(if_ctx_t, int); 483 static int em_msix_link(void *); 484 static void em_handle_link(void *); 485 486 static void em_enable_vectors_82574(if_ctx_t); 487 488 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 489 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 490 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 491 static void em_if_led_func(if_ctx_t, int); 492 493 static int em_get_regs(SYSCTL_HANDLER_ARGS); 494 495 static void lem_smartspeed(struct e1000_softc *); 496 static void igb_configure_queues(struct e1000_softc *); 497 static void em_flush_desc_rings(struct e1000_softc *); 498 499 500 /********************************************************************* 501 * FreeBSD Device Interface Entry Points 502 *********************************************************************/ 503 static device_method_t em_methods[] = { 504 /* Device interface */ 505 DEVMETHOD(device_register, em_register), 506 DEVMETHOD(device_probe, iflib_device_probe), 507 DEVMETHOD(device_attach, iflib_device_attach), 508 DEVMETHOD(device_detach, iflib_device_detach), 509 DEVMETHOD(device_shutdown, iflib_device_shutdown), 510 DEVMETHOD(device_suspend, iflib_device_suspend), 511 DEVMETHOD(device_resume, iflib_device_resume), 512 DEVMETHOD_END 513 }; 514 515 static device_method_t igb_methods[] = { 516 /* Device interface */ 517 DEVMETHOD(device_register, igb_register), 518 DEVMETHOD(device_probe, iflib_device_probe), 519 DEVMETHOD(device_attach, iflib_device_attach), 520 DEVMETHOD(device_detach, iflib_device_detach), 521 DEVMETHOD(device_shutdown, iflib_device_shutdown), 522 DEVMETHOD(device_suspend, iflib_device_suspend), 523 DEVMETHOD(device_resume, iflib_device_resume), 524 DEVMETHOD_END 525 }; 526 527 528 static driver_t em_driver = { 529 "em", em_methods, sizeof(struct e1000_softc), 530 }; 531 532 DRIVER_MODULE(em, pci, em_driver, 0, 0); 533 534 MODULE_DEPEND(em, pci, 1, 1, 1); 535 MODULE_DEPEND(em, ether, 1, 1, 1); 536 MODULE_DEPEND(em, iflib, 1, 1, 1); 537 538 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 539 540 static driver_t igb_driver = { 541 "igb", igb_methods, sizeof(struct e1000_softc), 542 }; 543 544 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 545 546 MODULE_DEPEND(igb, pci, 1, 1, 1); 547 MODULE_DEPEND(igb, ether, 1, 1, 1); 548 MODULE_DEPEND(igb, iflib, 1, 1, 1); 549 550 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 551 552 static device_method_t em_if_methods[] = { 553 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 554 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 555 DEVMETHOD(ifdi_detach, em_if_detach), 556 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 557 DEVMETHOD(ifdi_suspend, em_if_suspend), 558 DEVMETHOD(ifdi_resume, em_if_resume), 559 DEVMETHOD(ifdi_init, em_if_init), 560 DEVMETHOD(ifdi_stop, em_if_stop), 561 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 562 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 563 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 564 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 565 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 566 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 567 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 568 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 569 DEVMETHOD(ifdi_media_status, em_if_media_status), 570 DEVMETHOD(ifdi_media_change, em_if_media_change), 571 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 572 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 573 DEVMETHOD(ifdi_timer, em_if_timer), 574 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 575 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 576 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 577 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 578 DEVMETHOD(ifdi_led_func, em_if_led_func), 579 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 580 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 581 DEVMETHOD(ifdi_debug, em_if_debug), 582 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 583 DEVMETHOD_END 584 }; 585 586 static driver_t em_if_driver = { 587 "em_if", em_if_methods, sizeof(struct e1000_softc) 588 }; 589 590 static device_method_t igb_if_methods[] = { 591 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 592 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 593 DEVMETHOD(ifdi_detach, em_if_detach), 594 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 595 DEVMETHOD(ifdi_suspend, em_if_suspend), 596 DEVMETHOD(ifdi_resume, em_if_resume), 597 DEVMETHOD(ifdi_init, em_if_init), 598 DEVMETHOD(ifdi_stop, em_if_stop), 599 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 600 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 601 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 602 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 603 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 604 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 605 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 606 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 607 DEVMETHOD(ifdi_media_status, em_if_media_status), 608 DEVMETHOD(ifdi_media_change, em_if_media_change), 609 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 610 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 611 DEVMETHOD(ifdi_timer, em_if_timer), 612 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 613 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 614 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 615 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 616 DEVMETHOD(ifdi_led_func, em_if_led_func), 617 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 618 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 619 DEVMETHOD(ifdi_debug, em_if_debug), 620 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 621 DEVMETHOD_END 622 }; 623 624 static driver_t igb_if_driver = { 625 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 626 }; 627 628 /********************************************************************* 629 * Tunable default values. 630 *********************************************************************/ 631 632 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 633 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 634 635 /* Allow common code without TSO */ 636 #ifndef CSUM_TSO 637 #define CSUM_TSO 0 638 #endif 639 640 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 641 "EM driver parameters"); 642 643 static int em_disable_crc_stripping = 0; 644 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 645 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 646 647 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 648 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 649 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 650 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 651 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 652 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 653 654 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 655 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 656 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 657 &em_tx_abs_int_delay_dflt, 0, 658 "Default transmit interrupt delay limit in usecs"); 659 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 660 &em_rx_abs_int_delay_dflt, 0, 661 "Default receive interrupt delay limit in usecs"); 662 663 static int em_smart_pwr_down = false; 664 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 665 &em_smart_pwr_down, 666 0, "Set to true to leave smart power down enabled on newer adapters"); 667 668 static bool em_unsupported_tso = false; 669 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 670 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 671 672 /* Controls whether promiscuous also shows bad packets */ 673 static int em_debug_sbp = false; 674 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 675 "Show bad packets in promiscuous mode"); 676 677 /* Energy efficient ethernet - default to OFF */ 678 static int eee_setting = 1; 679 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 680 "Enable Energy Efficient Ethernet"); 681 682 /* 683 * AIM: Adaptive Interrupt Moderation 684 * which means that the interrupt rate is varied over time based on the 685 * traffic for that interrupt vector 686 */ 687 static int em_enable_aim = 1; 688 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 689 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 690 691 /* 692 ** Tuneable Interrupt rate 693 */ 694 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 695 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 696 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 697 698 /* Global used in WOL setup with multiport cards */ 699 static int global_quad_port_a = 0; 700 701 extern struct if_txrx igb_txrx; 702 extern struct if_txrx em_txrx; 703 extern struct if_txrx lem_txrx; 704 705 static struct if_shared_ctx em_sctx_init = { 706 .isc_magic = IFLIB_MAGIC, 707 .isc_q_align = PAGE_SIZE, 708 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 709 .isc_tx_maxsegsize = PAGE_SIZE, 710 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 711 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 712 .isc_rx_maxsize = MJUM9BYTES, 713 .isc_rx_nsegments = 1, 714 .isc_rx_maxsegsize = MJUM9BYTES, 715 .isc_nfl = 1, 716 .isc_nrxqs = 1, 717 .isc_ntxqs = 1, 718 .isc_admin_intrcnt = 1, 719 .isc_vendor_info = em_vendor_info_array, 720 .isc_driver_version = em_driver_version, 721 .isc_driver = &em_if_driver, 722 .isc_flags = 723 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 724 725 .isc_nrxd_min = {EM_MIN_RXD}, 726 .isc_ntxd_min = {EM_MIN_TXD}, 727 .isc_nrxd_max = {EM_MAX_RXD}, 728 .isc_ntxd_max = {EM_MAX_TXD}, 729 .isc_nrxd_default = {EM_DEFAULT_RXD}, 730 .isc_ntxd_default = {EM_DEFAULT_TXD}, 731 }; 732 733 static struct if_shared_ctx igb_sctx_init = { 734 .isc_magic = IFLIB_MAGIC, 735 .isc_q_align = PAGE_SIZE, 736 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 737 .isc_tx_maxsegsize = PAGE_SIZE, 738 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 739 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 740 .isc_rx_maxsize = MJUM9BYTES, 741 .isc_rx_nsegments = 1, 742 .isc_rx_maxsegsize = MJUM9BYTES, 743 .isc_nfl = 1, 744 .isc_nrxqs = 1, 745 .isc_ntxqs = 1, 746 .isc_admin_intrcnt = 1, 747 .isc_vendor_info = igb_vendor_info_array, 748 .isc_driver_version = igb_driver_version, 749 .isc_driver = &igb_if_driver, 750 .isc_flags = 751 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 752 753 .isc_nrxd_min = {EM_MIN_RXD}, 754 .isc_ntxd_min = {EM_MIN_TXD}, 755 .isc_nrxd_max = {IGB_MAX_RXD}, 756 .isc_ntxd_max = {IGB_MAX_TXD}, 757 .isc_nrxd_default = {EM_DEFAULT_RXD}, 758 .isc_ntxd_default = {EM_DEFAULT_TXD}, 759 }; 760 761 /***************************************************************** 762 * 763 * Dump Registers 764 * 765 ****************************************************************/ 766 #define IGB_REGS_LEN 739 767 768 static int em_get_regs(SYSCTL_HANDLER_ARGS) 769 { 770 struct e1000_softc *sc = (struct e1000_softc *)arg1; 771 struct e1000_hw *hw = &sc->hw; 772 struct sbuf *sb; 773 u32 *regs_buff; 774 int rc; 775 776 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 777 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 778 779 rc = sysctl_wire_old_buffer(req, 0); 780 MPASS(rc == 0); 781 if (rc != 0) { 782 free(regs_buff, M_DEVBUF); 783 return (rc); 784 } 785 786 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 787 MPASS(sb != NULL); 788 if (sb == NULL) { 789 free(regs_buff, M_DEVBUF); 790 return (ENOMEM); 791 } 792 793 /* General Registers */ 794 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 795 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 796 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 797 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 798 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 799 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 800 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 801 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 802 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 803 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 804 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 805 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 806 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 807 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 808 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 809 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 810 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 811 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 812 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 813 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 814 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 815 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 816 817 sbuf_printf(sb, "General Registers\n"); 818 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 819 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 820 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 821 822 sbuf_printf(sb, "Interrupt Registers\n"); 823 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 824 825 sbuf_printf(sb, "RX Registers\n"); 826 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 827 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 828 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 829 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 830 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 831 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 832 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 833 834 sbuf_printf(sb, "TX Registers\n"); 835 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 836 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 837 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 838 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 839 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 840 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 841 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 842 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 843 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 844 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 845 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 846 847 free(regs_buff, M_DEVBUF); 848 849 #ifdef DUMP_DESCS 850 { 851 if_softc_ctx_t scctx = sc->shared; 852 struct rx_ring *rxr = &rx_que->rxr; 853 struct tx_ring *txr = &tx_que->txr; 854 int ntxd = scctx->isc_ntxd[0]; 855 int nrxd = scctx->isc_nrxd[0]; 856 int j; 857 858 for (j = 0; j < nrxd; j++) { 859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 861 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 862 PRIx64 " Error:%d Length:%d\n", 863 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 864 } 865 866 for (j = 0; j < min(ntxd, 256); j++) { 867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 868 869 sbuf_printf(sb, 870 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 871 " eop: %d DD=%d\n", 872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 873 buf->eop != -1 ? 874 txr->tx_base[buf->eop].upper.fields.status & 875 E1000_TXD_STAT_DD : 0); 876 877 } 878 } 879 #endif 880 881 rc = sbuf_finish(sb); 882 sbuf_delete(sb); 883 return(rc); 884 } 885 886 static void * 887 em_register(device_t dev) 888 { 889 return (&em_sctx_init); 890 } 891 892 static void * 893 igb_register(device_t dev) 894 { 895 return (&igb_sctx_init); 896 } 897 898 static int 899 em_set_num_queues(if_ctx_t ctx) 900 { 901 struct e1000_softc *sc = iflib_get_softc(ctx); 902 int maxqueues; 903 904 /* Sanity check based on HW */ 905 switch (sc->hw.mac.type) { 906 case e1000_82576: 907 case e1000_82580: 908 case e1000_i350: 909 case e1000_i354: 910 maxqueues = 8; 911 break; 912 case e1000_i210: 913 case e1000_82575: 914 maxqueues = 4; 915 break; 916 case e1000_i211: 917 case e1000_82574: 918 maxqueues = 2; 919 break; 920 default: 921 maxqueues = 1; 922 break; 923 } 924 925 return (maxqueues); 926 } 927 928 #define LEM_CAPS \ 929 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 930 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 931 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 932 933 #define EM_CAPS \ 934 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 935 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 936 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 937 IFCAP_TSO6 938 939 #define IGB_CAPS \ 940 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 941 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 942 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 943 IFCAP_TSO6 944 945 /********************************************************************* 946 * Device initialization routine 947 * 948 * The attach entry point is called when the driver is being loaded. 949 * This routine identifies the type of hardware, allocates all resources 950 * and initializes the hardware. 951 * 952 * return 0 on success, positive on failure 953 *********************************************************************/ 954 static int 955 em_if_attach_pre(if_ctx_t ctx) 956 { 957 struct e1000_softc *sc; 958 if_softc_ctx_t scctx; 959 device_t dev; 960 struct e1000_hw *hw; 961 struct sysctl_oid_list *child; 962 struct sysctl_ctx_list *ctx_list; 963 int error = 0; 964 965 INIT_DEBUGOUT("em_if_attach_pre: begin"); 966 dev = iflib_get_dev(ctx); 967 sc = iflib_get_softc(ctx); 968 969 sc->ctx = sc->osdep.ctx = ctx; 970 sc->dev = sc->osdep.dev = dev; 971 scctx = sc->shared = iflib_get_softc_ctx(ctx); 972 sc->media = iflib_get_media(ctx); 973 hw = &sc->hw; 974 975 /* Determine hardware and mac info */ 976 em_identify_hardware(ctx); 977 978 /* SYSCTL stuff */ 979 ctx_list = device_get_sysctl_ctx(dev); 980 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 981 982 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 983 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 984 em_sysctl_nvm_info, "I", "NVM Information"); 985 986 sc->enable_aim = em_enable_aim; 987 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 988 CTLFLAG_RW, &sc->enable_aim, 0, 989 "Interrupt Moderation (1=normal, 2=lowlatency)"); 990 991 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 992 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 993 em_sysctl_print_fw_version, "A", 994 "Prints FW/NVM Versions"); 995 996 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 997 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 998 em_sysctl_debug_info, "I", "Debug Information"); 999 1000 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1002 em_set_flowcntl, "I", "Flow Control"); 1003 1004 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1006 em_get_regs, "A", "Dump Registers"); 1007 1008 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1009 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1010 em_get_rs, "I", "Dump RS indexes"); 1011 1012 if (hw->mac.type >= e1000_i350) { 1013 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1014 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1015 igb_sysctl_dmac, "I", "DMA Coalesce"); 1016 } 1017 1018 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1019 "tso_tcp_flags_mask_first_segment", 1020 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1021 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1022 "TSO TCP flags mask for first segment"); 1023 1024 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1025 "tso_tcp_flags_mask_middle_segment", 1026 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1027 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1028 "TSO TCP flags mask for middle segment"); 1029 1030 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1031 "tso_tcp_flags_mask_last_segment", 1032 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1033 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1034 "TSO TCP flags mask for last segment"); 1035 1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1037 scctx->isc_nrxqsets_max = 1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1039 if (bootverbose) 1040 device_printf(dev, "attach_pre capping queues at %d\n", 1041 scctx->isc_ntxqsets_max); 1042 1043 if (hw->mac.type >= igb_mac_min) { 1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1045 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1047 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1050 scctx->isc_txrx = &igb_txrx; 1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1056 CSUM_IP6_TCP | CSUM_IP6_UDP; 1057 if (hw->mac.type != e1000_82575) 1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1059 /* 1060 ** Some new devices, as with ixgbe, now may 1061 ** use a different BAR, so we need to keep 1062 ** track of which is used. 1063 */ 1064 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1065 } else if (hw->mac.type >= em_mac_min) { 1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1067 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1069 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1072 scctx->isc_txrx = &em_txrx; 1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1078 CSUM_IP6_TCP | CSUM_IP6_UDP; 1079 1080 /* Disable TSO on all em(4) until ring stalls are debugged */ 1081 scctx->isc_capenable &= ~IFCAP_TSO; 1082 1083 /* 1084 * Disable TSO on SPT due to errata that downclocks DMA 1085 * performance 1086 * i218-i219 Specification Update 1.5.4.5 1087 */ 1088 if (hw->mac.type == e1000_pch_spt) 1089 scctx->isc_capenable &= ~IFCAP_TSO; 1090 1091 /* 1092 * We support MSI-X with 82574 only, but indicate to iflib(4) 1093 * that it shall give MSI at least a try with other devices. 1094 */ 1095 if (hw->mac.type == e1000_82574) { 1096 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1097 } else { 1098 scctx->isc_msix_bar = -1; 1099 scctx->isc_disable_msix = 1; 1100 } 1101 } else { 1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1103 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1105 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1108 scctx->isc_txrx = &lem_txrx; 1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1113 if (em_unsupported_tso) 1114 scctx->isc_capabilities |= IFCAP_TSO6; 1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1116 CSUM_IP6_TCP | CSUM_IP6_UDP; 1117 1118 /* Disable TSO on all lem(4) until ring stalls debugged */ 1119 scctx->isc_capenable &= ~IFCAP_TSO; 1120 1121 /* 82541ER doesn't do HW tagging */ 1122 if (hw->device_id == E1000_DEV_ID_82541ER || 1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1125 scctx->isc_capenable = scctx->isc_capabilities; 1126 } 1127 /* This is the first e1000 chip and it does not do offloads */ 1128 if (hw->mac.type == e1000_82542) { 1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1130 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1131 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1132 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1133 scctx->isc_capenable = scctx->isc_capabilities; 1134 } 1135 /* These can't do TSO for various reasons */ 1136 if (hw->mac.type < e1000_82544 || 1137 hw->mac.type == e1000_82547 || 1138 hw->mac.type == e1000_82547_rev_2) { 1139 scctx->isc_capabilities &= 1140 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1141 scctx->isc_capenable = scctx->isc_capabilities; 1142 } 1143 /* XXXKB: No IPv6 before this? */ 1144 if (hw->mac.type < e1000_82545){ 1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1146 scctx->isc_capenable = scctx->isc_capabilities; 1147 } 1148 /* 1149 * "PCI/PCI-X SDM 4.0" page 33 (b): 1150 * FDX requirement on these chips 1151 */ 1152 if (hw->mac.type == e1000_82547 || 1153 hw->mac.type == e1000_82547_rev_2) 1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1155 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1156 1157 /* INTx only */ 1158 scctx->isc_msix_bar = 0; 1159 } 1160 1161 /* Setup PCI resources */ 1162 if (em_allocate_pci_resources(ctx)) { 1163 device_printf(dev, "Allocation of PCI resources failed\n"); 1164 error = ENXIO; 1165 goto err_pci; 1166 } 1167 1168 /* 1169 ** For ICH8 and family we need to 1170 ** map the flash memory, and this 1171 ** must happen after the MAC is 1172 ** identified 1173 */ 1174 if ((hw->mac.type == e1000_ich8lan) || 1175 (hw->mac.type == e1000_ich9lan) || 1176 (hw->mac.type == e1000_ich10lan) || 1177 (hw->mac.type == e1000_pchlan) || 1178 (hw->mac.type == e1000_pch2lan) || 1179 (hw->mac.type == e1000_pch_lpt)) { 1180 int rid = EM_BAR_TYPE_FLASH; 1181 sc->flash = bus_alloc_resource_any(dev, 1182 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1183 if (sc->flash == NULL) { 1184 device_printf(dev, "Mapping of Flash failed\n"); 1185 error = ENXIO; 1186 goto err_pci; 1187 } 1188 /* This is used in the shared code */ 1189 hw->flash_address = (u8 *)sc->flash; 1190 sc->osdep.flash_bus_space_tag = 1191 rman_get_bustag(sc->flash); 1192 sc->osdep.flash_bus_space_handle = 1193 rman_get_bushandle(sc->flash); 1194 } 1195 /* 1196 ** In the new SPT device flash is not a 1197 ** separate BAR, rather it is also in BAR0, 1198 ** so use the same tag and an offset handle for the 1199 ** FLASH read/write macros in the shared code. 1200 */ 1201 else if (hw->mac.type >= e1000_pch_spt) { 1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1203 sc->osdep.flash_bus_space_handle = 1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1205 } 1206 1207 /* Do Shared Code initialization */ 1208 error = e1000_setup_init_funcs(hw, true); 1209 if (error) { 1210 device_printf(dev, "Setup of Shared code failed, error %d\n", 1211 error); 1212 error = ENXIO; 1213 goto err_pci; 1214 } 1215 1216 em_setup_msix(ctx); 1217 e1000_get_bus_info(hw); 1218 1219 /* Set up some sysctls for the tunable interrupt delays */ 1220 if (hw->mac.type < igb_mac_min) { 1221 em_add_int_delay_sysctl(sc, "rx_int_delay", 1222 "receive interrupt delay in usecs", &sc->rx_int_delay, 1223 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1224 em_add_int_delay_sysctl(sc, "tx_int_delay", 1225 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1226 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1227 } 1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1229 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1230 "receive interrupt delay limit in usecs", 1231 &sc->rx_abs_int_delay, 1232 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1233 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1234 "transmit interrupt delay limit in usecs", 1235 &sc->tx_abs_int_delay, 1236 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1237 } 1238 1239 hw->mac.autoneg = DO_AUTO_NEG; 1240 hw->phy.autoneg_wait_to_complete = false; 1241 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1242 1243 if (hw->mac.type < em_mac_min) { 1244 e1000_init_script_state_82541(hw, true); 1245 e1000_set_tbi_compatibility_82543(hw, true); 1246 } 1247 /* Copper options */ 1248 if (hw->phy.media_type == e1000_media_type_copper) { 1249 hw->phy.mdix = AUTO_ALL_MODES; 1250 hw->phy.disable_polarity_correction = false; 1251 hw->phy.ms_type = EM_MASTER_SLAVE; 1252 } 1253 1254 /* 1255 * Set the frame limits assuming 1256 * standard ethernet sized frames. 1257 */ 1258 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1259 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1260 1261 /* 1262 * This controls when hardware reports transmit completion 1263 * status. 1264 */ 1265 hw->mac.report_tx_early = 1; 1266 1267 /* Allocate multicast array memory. */ 1268 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1269 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1270 if (sc->mta == NULL) { 1271 device_printf(dev, 1272 "Can not allocate multicast setup array\n"); 1273 error = ENOMEM; 1274 goto err_late; 1275 } 1276 1277 /* Clear the IFCAP_TSO auto mask */ 1278 sc->tso_automasked = 0; 1279 1280 /* Check SOL/IDER usage */ 1281 if (e1000_check_reset_block(hw)) 1282 device_printf(dev, 1283 "PHY reset is blocked due to SOL/IDER session.\n"); 1284 1285 /* Sysctl for setting Energy Efficient Ethernet */ 1286 if (hw->mac.type < igb_mac_min) 1287 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1288 else 1289 hw->dev_spec._82575.eee_disable = eee_setting; 1290 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1291 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1292 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1293 1294 /* 1295 ** Start from a known state, this is 1296 ** important in reading the nvm and 1297 ** mac from that. 1298 */ 1299 e1000_reset_hw(hw); 1300 1301 /* Make sure we have a good EEPROM before we read from it */ 1302 if (e1000_validate_nvm_checksum(hw) < 0) { 1303 /* 1304 ** Some PCI-E parts fail the first check due to 1305 ** the link being in sleep state, call it again, 1306 ** if it fails a second time its a real issue. 1307 */ 1308 if (e1000_validate_nvm_checksum(hw) < 0) { 1309 device_printf(dev, 1310 "The EEPROM Checksum Is Not Valid\n"); 1311 error = EIO; 1312 goto err_late; 1313 } 1314 } 1315 1316 /* Copy the permanent MAC address out of the EEPROM */ 1317 if (e1000_read_mac_addr(hw) < 0) { 1318 device_printf(dev, 1319 "EEPROM read error while reading MAC address\n"); 1320 error = EIO; 1321 goto err_late; 1322 } 1323 1324 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1325 if (sc->vf_ifp) { 1326 ether_gen_addr(iflib_get_ifp(ctx), 1327 (struct ether_addr *)hw->mac.addr); 1328 } else { 1329 device_printf(dev, "Invalid MAC address\n"); 1330 error = EIO; 1331 goto err_late; 1332 } 1333 } 1334 1335 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1336 em_fw_version_locked(ctx); 1337 1338 em_print_fw_version(sc); 1339 1340 /* 1341 * Get Wake-on-Lan and Management info for later use 1342 */ 1343 em_get_wakeup(ctx); 1344 1345 /* Enable only WOL MAGIC by default */ 1346 scctx->isc_capenable &= ~IFCAP_WOL; 1347 if (sc->wol != 0) 1348 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1349 1350 iflib_set_mac(ctx, hw->mac.addr); 1351 1352 return (0); 1353 1354 err_late: 1355 em_release_hw_control(sc); 1356 err_pci: 1357 em_free_pci_resources(ctx); 1358 free(sc->mta, M_DEVBUF); 1359 1360 return (error); 1361 } 1362 1363 static int 1364 em_if_attach_post(if_ctx_t ctx) 1365 { 1366 struct e1000_softc *sc = iflib_get_softc(ctx); 1367 struct e1000_hw *hw = &sc->hw; 1368 int error = 0; 1369 1370 /* Setup OS specific network interface */ 1371 error = em_setup_interface(ctx); 1372 if (error != 0) { 1373 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1374 goto err_late; 1375 } 1376 1377 em_reset(ctx); 1378 1379 /* Initialize statistics */ 1380 em_update_stats_counters(sc); 1381 hw->mac.get_link_status = 1; 1382 em_if_update_admin_status(ctx); 1383 em_add_hw_stats(sc); 1384 1385 /* Non-AMT based hardware can now take control from firmware */ 1386 if (sc->has_manage && !sc->has_amt) 1387 em_get_hw_control(sc); 1388 1389 INIT_DEBUGOUT("em_if_attach_post: end"); 1390 1391 return (0); 1392 1393 err_late: 1394 /* 1395 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1396 * free resources 1397 */ 1398 return (error); 1399 } 1400 1401 /********************************************************************* 1402 * Device removal routine 1403 * 1404 * The detach entry point is called when the driver is being removed. 1405 * This routine stops the adapter and deallocates all the resources 1406 * that were allocated for driver operation. 1407 * 1408 * return 0 on success, positive on failure 1409 *********************************************************************/ 1410 static int 1411 em_if_detach(if_ctx_t ctx) 1412 { 1413 struct e1000_softc *sc = iflib_get_softc(ctx); 1414 1415 INIT_DEBUGOUT("em_if_detach: begin"); 1416 1417 e1000_phy_hw_reset(&sc->hw); 1418 1419 em_release_manageability(sc); 1420 em_release_hw_control(sc); 1421 em_free_pci_resources(ctx); 1422 free(sc->mta, M_DEVBUF); 1423 sc->mta = NULL; 1424 1425 return (0); 1426 } 1427 1428 /********************************************************************* 1429 * 1430 * Shutdown entry point 1431 * 1432 **********************************************************************/ 1433 1434 static int 1435 em_if_shutdown(if_ctx_t ctx) 1436 { 1437 return em_if_suspend(ctx); 1438 } 1439 1440 /* 1441 * Suspend/resume device methods. 1442 */ 1443 static int 1444 em_if_suspend(if_ctx_t ctx) 1445 { 1446 struct e1000_softc *sc = iflib_get_softc(ctx); 1447 1448 em_release_manageability(sc); 1449 em_release_hw_control(sc); 1450 em_enable_wakeup(ctx); 1451 return (0); 1452 } 1453 1454 static int 1455 em_if_resume(if_ctx_t ctx) 1456 { 1457 struct e1000_softc *sc = iflib_get_softc(ctx); 1458 1459 if (sc->hw.mac.type == e1000_pch2lan) 1460 e1000_resume_workarounds_pchlan(&sc->hw); 1461 em_if_init(ctx); 1462 em_init_manageability(sc); 1463 1464 return(0); 1465 } 1466 1467 static int 1468 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1469 { 1470 int max_frame_size; 1471 struct e1000_softc *sc = iflib_get_softc(ctx); 1472 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1473 1474 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1475 1476 switch (sc->hw.mac.type) { 1477 case e1000_82571: 1478 case e1000_82572: 1479 case e1000_ich9lan: 1480 case e1000_ich10lan: 1481 case e1000_pch2lan: 1482 case e1000_pch_lpt: 1483 case e1000_pch_spt: 1484 case e1000_pch_cnp: 1485 case e1000_pch_tgp: 1486 case e1000_pch_adp: 1487 case e1000_pch_mtp: 1488 case e1000_pch_ptp: 1489 case e1000_82574: 1490 case e1000_82583: 1491 case e1000_80003es2lan: 1492 /* 9K Jumbo Frame size */ 1493 max_frame_size = 9234; 1494 break; 1495 case e1000_pchlan: 1496 max_frame_size = 4096; 1497 break; 1498 case e1000_82542: 1499 case e1000_ich8lan: 1500 /* Adapters that do not support jumbo frames */ 1501 max_frame_size = ETHER_MAX_LEN; 1502 break; 1503 default: 1504 if (sc->hw.mac.type >= igb_mac_min) 1505 max_frame_size = 9234; 1506 else /* lem */ 1507 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1508 } 1509 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1510 return (EINVAL); 1511 } 1512 1513 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1514 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1515 return (0); 1516 } 1517 1518 /********************************************************************* 1519 * Init entry point 1520 * 1521 * This routine is used in two ways. It is used by the stack as 1522 * init entry point in network interface structure. It is also used 1523 * by the driver as a hw/sw initialization routine to get to a 1524 * consistent state. 1525 * 1526 **********************************************************************/ 1527 static void 1528 em_if_init(if_ctx_t ctx) 1529 { 1530 struct e1000_softc *sc = iflib_get_softc(ctx); 1531 if_softc_ctx_t scctx = sc->shared; 1532 if_t ifp = iflib_get_ifp(ctx); 1533 struct em_tx_queue *tx_que; 1534 int i; 1535 1536 INIT_DEBUGOUT("em_if_init: begin"); 1537 1538 /* Get the latest mac address, User can use a LAA */ 1539 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1540 1541 /* Put the address into the Receive Address Array */ 1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1543 1544 /* 1545 * With the 82571 adapter, RAR[0] may be overwritten 1546 * when the other port is reset, we make a duplicate 1547 * in RAR[14] for that eventuality, this assures 1548 * the interface continues to function. 1549 */ 1550 if (sc->hw.mac.type == e1000_82571) { 1551 e1000_set_laa_state_82571(&sc->hw, true); 1552 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1553 E1000_RAR_ENTRIES - 1); 1554 } 1555 1556 /* Initialize the hardware */ 1557 em_reset(ctx); 1558 em_if_update_admin_status(ctx); 1559 1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1561 i++, tx_que++) { 1562 struct tx_ring *txr = &tx_que->txr; 1563 1564 txr->tx_rs_cidx = txr->tx_rs_pidx; 1565 1566 /* Initialize the last processed descriptor to be the end of 1567 * the ring, rather than the start, so that we avoid an 1568 * off-by-one error when calculating how many descriptors are 1569 * done in the credits_update function. 1570 */ 1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1572 } 1573 1574 /* Setup VLAN support, basic and offload if available */ 1575 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1576 1577 /* Clear bad data from Rx FIFOs */ 1578 if (sc->hw.mac.type >= igb_mac_min) 1579 e1000_rx_fifo_flush_base(&sc->hw); 1580 1581 /* Configure for OS presence */ 1582 em_init_manageability(sc); 1583 1584 /* Prepare transmit descriptors and buffers */ 1585 em_initialize_transmit_unit(ctx); 1586 1587 /* Setup Multicast table */ 1588 em_if_multi_set(ctx); 1589 1590 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1591 em_initialize_receive_unit(ctx); 1592 1593 /* Set up VLAN support and filter */ 1594 em_setup_vlan_hw_support(ctx); 1595 1596 /* Don't lose promiscuous settings */ 1597 em_if_set_promisc(ctx, if_getflags(ifp)); 1598 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1599 1600 /* MSI-X configuration for 82574 */ 1601 if (sc->hw.mac.type == e1000_82574) { 1602 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1603 1604 tmp |= E1000_CTRL_EXT_PBA_CLR; 1605 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1606 /* Set the IVAR - interrupt vector routing. */ 1607 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1608 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1609 /* Set up queue routing */ 1610 igb_configure_queues(sc); 1611 } 1612 1613 /* this clears any pending interrupts */ 1614 E1000_READ_REG(&sc->hw, E1000_ICR); 1615 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1616 1617 /* AMT based hardware can now take control from firmware */ 1618 if (sc->has_manage && sc->has_amt) 1619 em_get_hw_control(sc); 1620 1621 /* Set Energy Efficient Ethernet */ 1622 if (sc->hw.mac.type >= igb_mac_min && 1623 sc->hw.phy.media_type == e1000_media_type_copper) { 1624 if (sc->hw.mac.type == e1000_i354) 1625 e1000_set_eee_i354(&sc->hw, true, true); 1626 else 1627 e1000_set_eee_i350(&sc->hw, true, true); 1628 } 1629 } 1630 1631 enum itr_latency_target { 1632 itr_latency_disabled = 0, 1633 itr_latency_lowest = 1, 1634 itr_latency_low = 2, 1635 itr_latency_bulk = 3 1636 }; 1637 /********************************************************************* 1638 * 1639 * Helper to calculate next (E)ITR value for AIM 1640 * 1641 *********************************************************************/ 1642 static void 1643 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1644 struct tx_ring *txr, struct rx_ring *rxr) 1645 { 1646 struct e1000_hw *hw = &sc->hw; 1647 unsigned long bytes, bytes_per_packet, packets; 1648 unsigned long rxbytes, rxpackets, txbytes, txpackets; 1649 u32 newitr; 1650 u8 nextlatency; 1651 1652 rxbytes = atomic_load_long(&rxr->rx_bytes); 1653 txbytes = atomic_load_long(&txr->tx_bytes); 1654 1655 /* Idle, do nothing */ 1656 if (txbytes == 0 && rxbytes == 0) 1657 return; 1658 1659 newitr = 0; 1660 1661 if (sc->enable_aim) { 1662 nextlatency = rxr->rx_nextlatency; 1663 1664 /* Use half default (4K) ITR if sub-gig */ 1665 if (sc->link_speed != 1000) { 1666 newitr = EM_INTS_4K; 1667 goto em_set_next_itr; 1668 } 1669 /* Want at least enough packet buffer for two frames to AIM */ 1670 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1671 newitr = em_max_interrupt_rate; 1672 sc->enable_aim = 0; 1673 goto em_set_next_itr; 1674 } 1675 1676 bytes = bytes_per_packet = 0; 1677 /* Get largest values from the associated tx and rx ring */ 1678 txpackets = atomic_load_long(&txr->tx_packets); 1679 if (txpackets != 0) { 1680 bytes = txbytes; 1681 bytes_per_packet = txbytes / txpackets; 1682 packets = txpackets; 1683 } 1684 rxpackets = atomic_load_long(&rxr->rx_packets); 1685 if (rxpackets != 0) { 1686 bytes = lmax(bytes, rxbytes); 1687 bytes_per_packet = 1688 lmax(bytes_per_packet, rxbytes / rxpackets); 1689 packets = lmax(packets, rxpackets); 1690 } 1691 1692 /* Latency state machine */ 1693 switch (nextlatency) { 1694 case itr_latency_disabled: /* Bootstrapping */ 1695 nextlatency = itr_latency_low; 1696 break; 1697 case itr_latency_lowest: /* 70k ints/s */ 1698 /* TSO and jumbo frames */ 1699 if (bytes_per_packet > 8000) 1700 nextlatency = itr_latency_bulk; 1701 else if ((packets < 5) && (bytes > 512)) 1702 nextlatency = itr_latency_low; 1703 break; 1704 case itr_latency_low: /* 20k ints/s */ 1705 if (bytes > 10000) { 1706 /* Handle TSO */ 1707 if (bytes_per_packet > 8000) 1708 nextlatency = itr_latency_bulk; 1709 else if ((packets < 10) || 1710 (bytes_per_packet > 1200)) 1711 nextlatency = itr_latency_bulk; 1712 else if (packets > 35) 1713 nextlatency = itr_latency_lowest; 1714 } else if (bytes_per_packet > 2000) { 1715 nextlatency = itr_latency_bulk; 1716 } else if (packets < 3 && bytes < 512) { 1717 nextlatency = itr_latency_lowest; 1718 } 1719 break; 1720 case itr_latency_bulk: /* 4k ints/s */ 1721 if (bytes > 25000) { 1722 if (packets > 35) 1723 nextlatency = itr_latency_low; 1724 } else if (bytes < 1500) 1725 nextlatency = itr_latency_low; 1726 break; 1727 default: 1728 nextlatency = itr_latency_low; 1729 device_printf(sc->dev, 1730 "Unexpected newitr transition %d\n", nextlatency); 1731 break; 1732 } 1733 1734 /* Trim itr_latency_lowest for default AIM setting */ 1735 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1736 nextlatency = itr_latency_low; 1737 1738 /* Request new latency */ 1739 rxr->rx_nextlatency = nextlatency; 1740 } else { 1741 /* We may have toggled to AIM disabled */ 1742 nextlatency = itr_latency_disabled; 1743 rxr->rx_nextlatency = nextlatency; 1744 } 1745 1746 /* ITR state machine */ 1747 switch(nextlatency) { 1748 case itr_latency_lowest: 1749 newitr = EM_INTS_70K; 1750 break; 1751 case itr_latency_low: 1752 newitr = EM_INTS_20K; 1753 break; 1754 case itr_latency_bulk: 1755 newitr = EM_INTS_4K; 1756 break; 1757 case itr_latency_disabled: 1758 default: 1759 newitr = em_max_interrupt_rate; 1760 break; 1761 } 1762 1763 em_set_next_itr: 1764 if (hw->mac.type >= igb_mac_min) { 1765 newitr = IGB_INTS_TO_EITR(newitr); 1766 1767 if (hw->mac.type == e1000_82575) 1768 newitr |= newitr << 16; 1769 else 1770 newitr |= E1000_EITR_CNT_IGNR; 1771 1772 if (newitr != que->itr_setting) { 1773 que->itr_setting = newitr; 1774 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1775 que->itr_setting); 1776 } 1777 } else { 1778 newitr = EM_INTS_TO_ITR(newitr); 1779 1780 if (newitr != que->itr_setting) { 1781 que->itr_setting = newitr; 1782 if (hw->mac.type == e1000_82574 && que->msix) { 1783 E1000_WRITE_REG(hw, 1784 E1000_EITR_82574(que->msix), 1785 que->itr_setting); 1786 } else { 1787 E1000_WRITE_REG(hw, E1000_ITR, 1788 que->itr_setting); 1789 } 1790 } 1791 } 1792 } 1793 1794 /********************************************************************* 1795 * 1796 * Fast Legacy/MSI Combined Interrupt Service routine 1797 * 1798 *********************************************************************/ 1799 int 1800 em_intr(void *arg) 1801 { 1802 struct e1000_softc *sc = arg; 1803 struct e1000_hw *hw = &sc->hw; 1804 struct em_rx_queue *que = &sc->rx_queues[0]; 1805 struct tx_ring *txr = &sc->tx_queues[0].txr; 1806 struct rx_ring *rxr = &que->rxr; 1807 if_ctx_t ctx = sc->ctx; 1808 u32 reg_icr; 1809 1810 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1811 1812 /* Hot eject? */ 1813 if (reg_icr == 0xffffffff) 1814 return FILTER_STRAY; 1815 1816 /* Definitely not our interrupt. */ 1817 if (reg_icr == 0x0) 1818 return FILTER_STRAY; 1819 1820 /* 1821 * Starting with the 82571 chip, bit 31 should be used to 1822 * determine whether the interrupt belongs to us. 1823 */ 1824 if (hw->mac.type >= e1000_82571 && 1825 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1826 return FILTER_STRAY; 1827 1828 /* 1829 * Only MSI-X interrupts have one-shot behavior by taking advantage 1830 * of the EIAC register. Thus, explicitly disable interrupts. This 1831 * also works around the MSI message reordering errata on certain 1832 * systems. 1833 */ 1834 IFDI_INTR_DISABLE(ctx); 1835 1836 /* Link status change */ 1837 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1838 em_handle_link(ctx); 1839 1840 if (reg_icr & E1000_ICR_RXO) 1841 sc->rx_overruns++; 1842 1843 if (hw->mac.type >= e1000_82540) 1844 em_newitr(sc, que, txr, rxr); 1845 1846 /* Reset state */ 1847 txr->tx_bytes = 0; 1848 txr->tx_packets = 0; 1849 rxr->rx_bytes = 0; 1850 rxr->rx_packets = 0; 1851 1852 return (FILTER_SCHEDULE_THREAD); 1853 } 1854 1855 static int 1856 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1857 { 1858 struct e1000_softc *sc = iflib_get_softc(ctx); 1859 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1860 1861 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1862 return (0); 1863 } 1864 1865 static int 1866 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1867 { 1868 struct e1000_softc *sc = iflib_get_softc(ctx); 1869 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1870 1871 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1872 return (0); 1873 } 1874 1875 static int 1876 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1877 { 1878 struct e1000_softc *sc = iflib_get_softc(ctx); 1879 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1880 1881 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1882 return (0); 1883 } 1884 1885 static int 1886 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1887 { 1888 struct e1000_softc *sc = iflib_get_softc(ctx); 1889 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1890 1891 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1892 return (0); 1893 } 1894 1895 /********************************************************************* 1896 * 1897 * MSI-X RX Interrupt Service routine 1898 * 1899 **********************************************************************/ 1900 static int 1901 em_msix_que(void *arg) 1902 { 1903 struct em_rx_queue *que = arg; 1904 struct e1000_softc *sc = que->sc; 1905 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1906 struct rx_ring *rxr = &que->rxr; 1907 1908 ++que->irqs; 1909 1910 em_newitr(sc, que, txr, rxr); 1911 1912 /* Reset state */ 1913 txr->tx_bytes = 0; 1914 txr->tx_packets = 0; 1915 rxr->rx_bytes = 0; 1916 rxr->rx_packets = 0; 1917 1918 return (FILTER_SCHEDULE_THREAD); 1919 } 1920 1921 /********************************************************************* 1922 * 1923 * MSI-X Link Fast Interrupt Service routine 1924 * 1925 **********************************************************************/ 1926 static int 1927 em_msix_link(void *arg) 1928 { 1929 struct e1000_softc *sc = arg; 1930 u32 reg_icr; 1931 1932 ++sc->link_irq; 1933 MPASS(sc->hw.back != NULL); 1934 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1935 1936 if (reg_icr & E1000_ICR_RXO) 1937 sc->rx_overruns++; 1938 1939 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1940 em_handle_link(sc->ctx); 1941 1942 /* Re-arm unconditionally */ 1943 if (sc->hw.mac.type >= igb_mac_min) { 1944 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1945 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1946 } else if (sc->hw.mac.type == e1000_82574) { 1947 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1948 E1000_IMS_LSC | E1000_IMS_OTHER); 1949 /* 1950 * Because we must read the ICR for this interrupt it may 1951 * clear other causes using autoclear, for this reason we 1952 * simply create a soft interrupt for all these vectors. 1953 */ 1954 if (reg_icr) 1955 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1956 } else 1957 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1958 1959 return (FILTER_HANDLED); 1960 } 1961 1962 static void 1963 em_handle_link(void *context) 1964 { 1965 if_ctx_t ctx = context; 1966 struct e1000_softc *sc = iflib_get_softc(ctx); 1967 1968 sc->hw.mac.get_link_status = 1; 1969 iflib_admin_intr_deferred(ctx); 1970 } 1971 1972 /********************************************************************* 1973 * 1974 * Media Ioctl callback 1975 * 1976 * This routine is called whenever the user queries the status of 1977 * the interface using ifconfig. 1978 * 1979 **********************************************************************/ 1980 static void 1981 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1982 { 1983 struct e1000_softc *sc = iflib_get_softc(ctx); 1984 u_char fiber_type = IFM_1000_SX; 1985 1986 INIT_DEBUGOUT("em_if_media_status: begin"); 1987 1988 iflib_admin_intr_deferred(ctx); 1989 1990 ifmr->ifm_status = IFM_AVALID; 1991 ifmr->ifm_active = IFM_ETHER; 1992 1993 if (!sc->link_active) { 1994 return; 1995 } 1996 1997 ifmr->ifm_status |= IFM_ACTIVE; 1998 1999 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 2000 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2001 if (sc->hw.mac.type == e1000_82545) 2002 fiber_type = IFM_1000_LX; 2003 ifmr->ifm_active |= fiber_type | IFM_FDX; 2004 } else { 2005 switch (sc->link_speed) { 2006 case 10: 2007 ifmr->ifm_active |= IFM_10_T; 2008 break; 2009 case 100: 2010 ifmr->ifm_active |= IFM_100_TX; 2011 break; 2012 case 1000: 2013 ifmr->ifm_active |= IFM_1000_T; 2014 break; 2015 } 2016 if (sc->link_duplex == FULL_DUPLEX) 2017 ifmr->ifm_active |= IFM_FDX; 2018 else 2019 ifmr->ifm_active |= IFM_HDX; 2020 } 2021 } 2022 2023 /********************************************************************* 2024 * 2025 * Media Ioctl callback 2026 * 2027 * This routine is called when the user changes speed/duplex using 2028 * media/mediopt option with ifconfig. 2029 * 2030 **********************************************************************/ 2031 static int 2032 em_if_media_change(if_ctx_t ctx) 2033 { 2034 struct e1000_softc *sc = iflib_get_softc(ctx); 2035 struct ifmedia *ifm = iflib_get_media(ctx); 2036 2037 INIT_DEBUGOUT("em_if_media_change: begin"); 2038 2039 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2040 return (EINVAL); 2041 2042 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2043 case IFM_AUTO: 2044 sc->hw.mac.autoneg = DO_AUTO_NEG; 2045 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2046 break; 2047 case IFM_1000_LX: 2048 case IFM_1000_SX: 2049 case IFM_1000_T: 2050 sc->hw.mac.autoneg = DO_AUTO_NEG; 2051 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2052 break; 2053 case IFM_100_TX: 2054 sc->hw.mac.autoneg = false; 2055 sc->hw.phy.autoneg_advertised = 0; 2056 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2057 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2058 else 2059 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2060 break; 2061 case IFM_10_T: 2062 sc->hw.mac.autoneg = false; 2063 sc->hw.phy.autoneg_advertised = 0; 2064 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2065 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2066 else 2067 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2068 break; 2069 default: 2070 device_printf(sc->dev, "Unsupported media type\n"); 2071 } 2072 2073 em_if_init(ctx); 2074 2075 return (0); 2076 } 2077 2078 static int 2079 em_if_set_promisc(if_ctx_t ctx, int flags) 2080 { 2081 struct e1000_softc *sc = iflib_get_softc(ctx); 2082 if_t ifp = iflib_get_ifp(ctx); 2083 u32 reg_rctl; 2084 int mcnt = 0; 2085 2086 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2087 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2088 if (flags & IFF_ALLMULTI) 2089 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2090 else 2091 mcnt = min(if_llmaddr_count(ifp), 2092 MAX_NUM_MULTICAST_ADDRESSES); 2093 2094 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2095 reg_rctl &= (~E1000_RCTL_MPE); 2096 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2097 2098 if (flags & IFF_PROMISC) { 2099 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2100 em_if_vlan_filter_disable(sc); 2101 /* Turn this on if you want to see bad packets */ 2102 if (em_debug_sbp) 2103 reg_rctl |= E1000_RCTL_SBP; 2104 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2105 } else { 2106 if (flags & IFF_ALLMULTI) { 2107 reg_rctl |= E1000_RCTL_MPE; 2108 reg_rctl &= ~E1000_RCTL_UPE; 2109 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2110 } 2111 if (em_if_vlan_filter_used(ctx)) 2112 em_if_vlan_filter_enable(sc); 2113 } 2114 return (0); 2115 } 2116 2117 static u_int 2118 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2119 { 2120 u8 *mta = arg; 2121 2122 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2123 return (0); 2124 2125 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2126 2127 return (1); 2128 } 2129 2130 /********************************************************************* 2131 * Multicast Update 2132 * 2133 * This routine is called whenever multicast address list is updated. 2134 * 2135 **********************************************************************/ 2136 static void 2137 em_if_multi_set(if_ctx_t ctx) 2138 { 2139 struct e1000_softc *sc = iflib_get_softc(ctx); 2140 if_t ifp = iflib_get_ifp(ctx); 2141 u8 *mta; /* Multicast array memory */ 2142 u32 reg_rctl = 0; 2143 int mcnt = 0; 2144 2145 IOCTL_DEBUGOUT("em_set_multi: begin"); 2146 2147 mta = sc->mta; 2148 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2149 2150 if (sc->hw.mac.type == e1000_82542 && 2151 sc->hw.revision_id == E1000_REVISION_2) { 2152 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2153 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2154 e1000_pci_clear_mwi(&sc->hw); 2155 reg_rctl |= E1000_RCTL_RST; 2156 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2157 msec_delay(5); 2158 } 2159 2160 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2161 2162 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2163 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2164 2165 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2166 2167 if (if_getflags(ifp) & IFF_PROMISC) 2168 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2169 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2170 if_getflags(ifp) & IFF_ALLMULTI) { 2171 reg_rctl |= E1000_RCTL_MPE; 2172 reg_rctl &= ~E1000_RCTL_UPE; 2173 } else 2174 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2175 2176 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2177 2178 if (sc->hw.mac.type == e1000_82542 && 2179 sc->hw.revision_id == E1000_REVISION_2) { 2180 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2181 reg_rctl &= ~E1000_RCTL_RST; 2182 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2183 msec_delay(5); 2184 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2185 e1000_pci_set_mwi(&sc->hw); 2186 } 2187 } 2188 2189 /********************************************************************* 2190 * Timer routine 2191 * 2192 * This routine schedules em_if_update_admin_status() to check for 2193 * link status and to gather statistics as well as to perform some 2194 * controller-specific hardware patting. 2195 * 2196 **********************************************************************/ 2197 static void 2198 em_if_timer(if_ctx_t ctx, uint16_t qid) 2199 { 2200 if (qid != 0) 2201 return; 2202 2203 iflib_admin_intr_deferred(ctx); 2204 } 2205 2206 static void 2207 em_if_update_admin_status(if_ctx_t ctx) 2208 { 2209 struct e1000_softc *sc = iflib_get_softc(ctx); 2210 struct e1000_hw *hw = &sc->hw; 2211 device_t dev = iflib_get_dev(ctx); 2212 u32 link_check, thstat, ctrl; 2213 bool automasked = false; 2214 2215 link_check = thstat = ctrl = 0; 2216 /* Get the cached link value or read phy for real */ 2217 switch (hw->phy.media_type) { 2218 case e1000_media_type_copper: 2219 if (hw->mac.get_link_status) { 2220 if (hw->mac.type == e1000_pch_spt) 2221 msec_delay(50); 2222 /* Do the work to read phy */ 2223 e1000_check_for_link(hw); 2224 link_check = !hw->mac.get_link_status; 2225 if (link_check) /* ESB2 fix */ 2226 e1000_cfg_on_link_up(hw); 2227 } else { 2228 link_check = true; 2229 } 2230 break; 2231 case e1000_media_type_fiber: 2232 e1000_check_for_link(hw); 2233 link_check = 2234 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2235 break; 2236 case e1000_media_type_internal_serdes: 2237 e1000_check_for_link(hw); 2238 link_check = hw->mac.serdes_has_link; 2239 break; 2240 /* VF device is type_unknown */ 2241 case e1000_media_type_unknown: 2242 e1000_check_for_link(hw); 2243 link_check = !hw->mac.get_link_status; 2244 /* FALLTHROUGH */ 2245 default: 2246 break; 2247 } 2248 2249 /* Check for thermal downshift or shutdown */ 2250 if (hw->mac.type == e1000_i350) { 2251 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2252 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2253 } 2254 2255 /* Now check for a transition */ 2256 if (link_check && (sc->link_active == 0)) { 2257 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2258 &sc->link_duplex); 2259 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2260 if ((sc->link_speed != SPEED_1000) && 2261 ((hw->mac.type == e1000_82571) || 2262 (hw->mac.type == e1000_82572))) { 2263 int tarc0; 2264 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2265 tarc0 &= ~TARC_SPEED_MODE_BIT; 2266 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2267 } 2268 if (bootverbose) 2269 device_printf(dev, "Link is up %d Mbps %s\n", 2270 sc->link_speed, 2271 ((sc->link_duplex == FULL_DUPLEX) ? 2272 "Full Duplex" : "Half Duplex")); 2273 sc->link_active = 1; 2274 sc->smartspeed = 0; 2275 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2276 E1000_CTRL_EXT_LINK_MODE_GMII && 2277 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2278 device_printf(dev, "Link: thermal downshift\n"); 2279 /* Delay Link Up for Phy update */ 2280 if (((hw->mac.type == e1000_i210) || 2281 (hw->mac.type == e1000_i211)) && 2282 (hw->phy.id == I210_I_PHY_ID)) 2283 msec_delay(I210_LINK_DELAY); 2284 /* Reset if the media type changed. */ 2285 if (hw->dev_spec._82575.media_changed && 2286 hw->mac.type >= igb_mac_min) { 2287 hw->dev_spec._82575.media_changed = false; 2288 sc->flags |= IGB_MEDIA_RESET; 2289 em_reset(ctx); 2290 } 2291 /* Only do TSO on gigabit for older chips due to errata */ 2292 if (hw->mac.type < igb_mac_min) 2293 automasked = em_automask_tso(ctx); 2294 2295 /* Automasking resets the interface so don't mark it up yet */ 2296 if (!automasked) 2297 iflib_link_state_change(ctx, LINK_STATE_UP, 2298 IF_Mbps(sc->link_speed)); 2299 } else if (!link_check && (sc->link_active == 1)) { 2300 sc->link_speed = 0; 2301 sc->link_duplex = 0; 2302 sc->link_active = 0; 2303 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2304 } 2305 em_update_stats_counters(sc); 2306 2307 /* Reset LAA into RAR[0] on 82571 */ 2308 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2309 e1000_rar_set(hw, hw->mac.addr, 0); 2310 2311 if (hw->mac.type < em_mac_min) 2312 lem_smartspeed(sc); 2313 } 2314 2315 static void 2316 em_if_watchdog_reset(if_ctx_t ctx) 2317 { 2318 struct e1000_softc *sc = iflib_get_softc(ctx); 2319 2320 /* 2321 * Just count the event; iflib(4) will already trigger a 2322 * sufficient reset of the controller. 2323 */ 2324 sc->watchdog_events++; 2325 } 2326 2327 /********************************************************************* 2328 * 2329 * This routine disables all traffic on the adapter by issuing a 2330 * global reset on the MAC. 2331 * 2332 **********************************************************************/ 2333 static void 2334 em_if_stop(if_ctx_t ctx) 2335 { 2336 struct e1000_softc *sc = iflib_get_softc(ctx); 2337 2338 INIT_DEBUGOUT("em_if_stop: begin"); 2339 2340 /* I219 needs special flushing to avoid hangs */ 2341 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2342 em_flush_desc_rings(sc); 2343 2344 e1000_reset_hw(&sc->hw); 2345 if (sc->hw.mac.type >= e1000_82544) 2346 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2347 2348 e1000_led_off(&sc->hw); 2349 e1000_cleanup_led(&sc->hw); 2350 } 2351 2352 /********************************************************************* 2353 * 2354 * Determine hardware revision. 2355 * 2356 **********************************************************************/ 2357 static void 2358 em_identify_hardware(if_ctx_t ctx) 2359 { 2360 device_t dev = iflib_get_dev(ctx); 2361 struct e1000_softc *sc = iflib_get_softc(ctx); 2362 2363 /* Make sure our PCI config space has the necessary stuff set */ 2364 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2365 2366 /* Save off the information about this board */ 2367 sc->hw.vendor_id = pci_get_vendor(dev); 2368 sc->hw.device_id = pci_get_device(dev); 2369 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2370 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2371 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2372 2373 /* Do Shared Code Init and Setup */ 2374 if (e1000_set_mac_type(&sc->hw)) { 2375 device_printf(dev, "Setup init failure\n"); 2376 return; 2377 } 2378 2379 /* Are we a VF device? */ 2380 if ((sc->hw.mac.type == e1000_vfadapt) || 2381 (sc->hw.mac.type == e1000_vfadapt_i350)) 2382 sc->vf_ifp = 1; 2383 else 2384 sc->vf_ifp = 0; 2385 } 2386 2387 static int 2388 em_allocate_pci_resources(if_ctx_t ctx) 2389 { 2390 struct e1000_softc *sc = iflib_get_softc(ctx); 2391 device_t dev = iflib_get_dev(ctx); 2392 int rid, val; 2393 2394 rid = PCIR_BAR(0); 2395 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2396 RF_ACTIVE); 2397 if (sc->memory == NULL) { 2398 device_printf(dev, 2399 "Unable to allocate bus resource: memory\n"); 2400 return (ENXIO); 2401 } 2402 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2403 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2404 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2405 2406 /* Only older adapters use IO mapping */ 2407 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2408 /* Figure our where our IO BAR is ? */ 2409 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2410 val = pci_read_config(dev, rid, 4); 2411 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2412 break; 2413 } 2414 rid += 4; 2415 /* check for 64bit BAR */ 2416 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2417 rid += 4; 2418 } 2419 if (rid >= PCIR_CIS) { 2420 device_printf(dev, "Unable to locate IO BAR\n"); 2421 return (ENXIO); 2422 } 2423 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2424 &rid, RF_ACTIVE); 2425 if (sc->ioport == NULL) { 2426 device_printf(dev, 2427 "Unable to allocate bus resource: ioport\n"); 2428 return (ENXIO); 2429 } 2430 sc->hw.io_base = 0; 2431 sc->osdep.io_bus_space_tag = 2432 rman_get_bustag(sc->ioport); 2433 sc->osdep.io_bus_space_handle = 2434 rman_get_bushandle(sc->ioport); 2435 } 2436 2437 sc->hw.back = &sc->osdep; 2438 2439 return (0); 2440 } 2441 2442 /********************************************************************* 2443 * 2444 * Set up the MSI-X Interrupt handlers 2445 * 2446 **********************************************************************/ 2447 static int 2448 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2449 { 2450 struct e1000_softc *sc = iflib_get_softc(ctx); 2451 struct em_rx_queue *rx_que = sc->rx_queues; 2452 struct em_tx_queue *tx_que = sc->tx_queues; 2453 int error, rid, i, vector = 0, rx_vectors; 2454 char buf[16]; 2455 2456 /* First set up ring resources */ 2457 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2458 rid = vector + 1; 2459 snprintf(buf, sizeof(buf), "rxq%d", i); 2460 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2461 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2462 if (error) { 2463 device_printf(iflib_get_dev(ctx), 2464 "Failed to allocate que int %d err: %d", 2465 i, error); 2466 sc->rx_num_queues = i + 1; 2467 goto fail; 2468 } 2469 2470 rx_que->msix = vector; 2471 2472 /* 2473 * Set the bit to enable interrupt 2474 * in E1000_IMS -- bits 20 and 21 2475 * are for RX0 and RX1, note this has 2476 * NOTHING to do with the MSI-X vector 2477 */ 2478 if (sc->hw.mac.type == e1000_82574) { 2479 rx_que->eims = 1 << (20 + i); 2480 sc->ims |= rx_que->eims; 2481 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2482 } else if (sc->hw.mac.type == e1000_82575) 2483 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2484 else 2485 rx_que->eims = 1 << vector; 2486 } 2487 rx_vectors = vector; 2488 2489 vector = 0; 2490 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2491 snprintf(buf, sizeof(buf), "txq%d", i); 2492 tx_que = &sc->tx_queues[i]; 2493 iflib_softirq_alloc_generic(ctx, 2494 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2495 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2496 2497 tx_que->msix = (vector % sc->rx_num_queues); 2498 2499 /* 2500 * Set the bit to enable interrupt 2501 * in E1000_IMS -- bits 22 and 23 2502 * are for TX0 and TX1, note this has 2503 * NOTHING to do with the MSI-X vector 2504 */ 2505 if (sc->hw.mac.type == e1000_82574) { 2506 tx_que->eims = 1 << (22 + i); 2507 sc->ims |= tx_que->eims; 2508 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2509 } else if (sc->hw.mac.type == e1000_82575) { 2510 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2511 } else { 2512 tx_que->eims = 1 << i; 2513 } 2514 } 2515 2516 /* Link interrupt */ 2517 rid = rx_vectors + 1; 2518 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2519 em_msix_link, sc, 0, "aq"); 2520 2521 if (error) { 2522 device_printf(iflib_get_dev(ctx), 2523 "Failed to register admin handler"); 2524 goto fail; 2525 } 2526 sc->linkvec = rx_vectors; 2527 if (sc->hw.mac.type < igb_mac_min) { 2528 sc->ivars |= (8 | rx_vectors) << 16; 2529 sc->ivars |= 0x80000000; 2530 /* Enable the "Other" interrupt type for link status change */ 2531 sc->ims |= E1000_IMS_OTHER; 2532 } 2533 2534 return (0); 2535 fail: 2536 iflib_irq_free(ctx, &sc->irq); 2537 rx_que = sc->rx_queues; 2538 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2539 iflib_irq_free(ctx, &rx_que->que_irq); 2540 return (error); 2541 } 2542 2543 static void 2544 igb_configure_queues(struct e1000_softc *sc) 2545 { 2546 struct e1000_hw *hw = &sc->hw; 2547 struct em_rx_queue *rx_que; 2548 struct em_tx_queue *tx_que; 2549 u32 tmp, ivar = 0, newitr = 0; 2550 2551 /* First turn on RSS capability */ 2552 if (hw->mac.type != e1000_82575) 2553 E1000_WRITE_REG(hw, E1000_GPIE, 2554 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2555 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2556 2557 /* Turn on MSI-X */ 2558 switch (hw->mac.type) { 2559 case e1000_82580: 2560 case e1000_i350: 2561 case e1000_i354: 2562 case e1000_i210: 2563 case e1000_i211: 2564 case e1000_vfadapt: 2565 case e1000_vfadapt_i350: 2566 /* RX entries */ 2567 for (int i = 0; i < sc->rx_num_queues; i++) { 2568 u32 index = i >> 1; 2569 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2570 rx_que = &sc->rx_queues[i]; 2571 if (i & 1) { 2572 ivar &= 0xFF00FFFF; 2573 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2574 16; 2575 } else { 2576 ivar &= 0xFFFFFF00; 2577 ivar |= rx_que->msix | E1000_IVAR_VALID; 2578 } 2579 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2580 } 2581 /* TX entries */ 2582 for (int i = 0; i < sc->tx_num_queues; i++) { 2583 u32 index = i >> 1; 2584 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2585 tx_que = &sc->tx_queues[i]; 2586 if (i & 1) { 2587 ivar &= 0x00FFFFFF; 2588 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2589 24; 2590 } else { 2591 ivar &= 0xFFFF00FF; 2592 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2593 8; 2594 } 2595 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2596 sc->que_mask |= tx_que->eims; 2597 } 2598 2599 /* And for the link interrupt */ 2600 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2601 sc->link_mask = 1 << sc->linkvec; 2602 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2603 break; 2604 case e1000_82576: 2605 /* RX entries */ 2606 for (int i = 0; i < sc->rx_num_queues; i++) { 2607 u32 index = i & 0x7; /* Each IVAR has two entries */ 2608 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2609 rx_que = &sc->rx_queues[i]; 2610 if (i < 8) { 2611 ivar &= 0xFFFFFF00; 2612 ivar |= rx_que->msix | E1000_IVAR_VALID; 2613 } else { 2614 ivar &= 0xFF00FFFF; 2615 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2616 16; 2617 } 2618 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2619 sc->que_mask |= rx_que->eims; 2620 } 2621 /* TX entries */ 2622 for (int i = 0; i < sc->tx_num_queues; i++) { 2623 u32 index = i & 0x7; /* Each IVAR has two entries */ 2624 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2625 tx_que = &sc->tx_queues[i]; 2626 if (i < 8) { 2627 ivar &= 0xFFFF00FF; 2628 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2629 8; 2630 } else { 2631 ivar &= 0x00FFFFFF; 2632 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2633 24; 2634 } 2635 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2636 sc->que_mask |= tx_que->eims; 2637 } 2638 2639 /* And for the link interrupt */ 2640 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2641 sc->link_mask = 1 << sc->linkvec; 2642 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2643 break; 2644 2645 case e1000_82575: 2646 /* enable MSI-X support*/ 2647 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2648 tmp |= E1000_CTRL_EXT_PBA_CLR; 2649 /* Auto-Mask interrupts upon ICR read. */ 2650 tmp |= E1000_CTRL_EXT_EIAME; 2651 tmp |= E1000_CTRL_EXT_IRCA; 2652 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2653 2654 /* Queues */ 2655 for (int i = 0; i < sc->rx_num_queues; i++) { 2656 rx_que = &sc->rx_queues[i]; 2657 tmp = E1000_EICR_RX_QUEUE0 << i; 2658 tmp |= E1000_EICR_TX_QUEUE0 << i; 2659 rx_que->eims = tmp; 2660 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2661 rx_que->eims); 2662 sc->que_mask |= rx_que->eims; 2663 } 2664 2665 /* Link */ 2666 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2667 E1000_EIMS_OTHER); 2668 sc->link_mask |= E1000_EIMS_OTHER; 2669 default: 2670 break; 2671 } 2672 2673 /* Set the igb starting interrupt rate */ 2674 if (em_max_interrupt_rate > 0) { 2675 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2676 2677 if (hw->mac.type == e1000_82575) 2678 newitr |= newitr << 16; 2679 else 2680 newitr |= E1000_EITR_CNT_IGNR; 2681 2682 for (int i = 0; i < sc->rx_num_queues; i++) { 2683 rx_que = &sc->rx_queues[i]; 2684 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2685 } 2686 } 2687 2688 return; 2689 } 2690 2691 static void 2692 em_free_pci_resources(if_ctx_t ctx) 2693 { 2694 struct e1000_softc *sc = iflib_get_softc(ctx); 2695 struct em_rx_queue *que = sc->rx_queues; 2696 device_t dev = iflib_get_dev(ctx); 2697 2698 /* Release all MSI-X queue resources */ 2699 if (sc->intr_type == IFLIB_INTR_MSIX) 2700 iflib_irq_free(ctx, &sc->irq); 2701 2702 if (que != NULL) { 2703 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2704 iflib_irq_free(ctx, &que->que_irq); 2705 } 2706 } 2707 2708 if (sc->memory != NULL) { 2709 bus_release_resource(dev, SYS_RES_MEMORY, 2710 rman_get_rid(sc->memory), sc->memory); 2711 sc->memory = NULL; 2712 } 2713 2714 if (sc->flash != NULL) { 2715 bus_release_resource(dev, SYS_RES_MEMORY, 2716 rman_get_rid(sc->flash), sc->flash); 2717 sc->flash = NULL; 2718 } 2719 2720 if (sc->ioport != NULL) { 2721 bus_release_resource(dev, SYS_RES_IOPORT, 2722 rman_get_rid(sc->ioport), sc->ioport); 2723 sc->ioport = NULL; 2724 } 2725 } 2726 2727 /* Set up MSI or MSI-X */ 2728 static int 2729 em_setup_msix(if_ctx_t ctx) 2730 { 2731 struct e1000_softc *sc = iflib_get_softc(ctx); 2732 2733 if (sc->hw.mac.type == e1000_82574) { 2734 em_enable_vectors_82574(ctx); 2735 } 2736 return (0); 2737 } 2738 2739 /********************************************************************* 2740 * 2741 * Workaround for SmartSpeed on 82541 and 82547 controllers 2742 * 2743 **********************************************************************/ 2744 static void 2745 lem_smartspeed(struct e1000_softc *sc) 2746 { 2747 u16 phy_tmp; 2748 2749 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2750 sc->hw.mac.autoneg == 0 || 2751 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2752 return; 2753 2754 if (sc->smartspeed == 0) { 2755 /* If Master/Slave config fault is asserted twice, 2756 * we assume back-to-back */ 2757 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2758 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2759 return; 2760 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2761 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2762 e1000_read_phy_reg(&sc->hw, 2763 PHY_1000T_CTRL, &phy_tmp); 2764 if(phy_tmp & CR_1000T_MS_ENABLE) { 2765 phy_tmp &= ~CR_1000T_MS_ENABLE; 2766 e1000_write_phy_reg(&sc->hw, 2767 PHY_1000T_CTRL, phy_tmp); 2768 sc->smartspeed++; 2769 if(sc->hw.mac.autoneg && 2770 !e1000_copper_link_autoneg(&sc->hw) && 2771 !e1000_read_phy_reg(&sc->hw, 2772 PHY_CONTROL, &phy_tmp)) { 2773 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2774 MII_CR_RESTART_AUTO_NEG); 2775 e1000_write_phy_reg(&sc->hw, 2776 PHY_CONTROL, phy_tmp); 2777 } 2778 } 2779 } 2780 return; 2781 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2782 /* If still no link, perhaps using 2/3 pair cable */ 2783 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2784 phy_tmp |= CR_1000T_MS_ENABLE; 2785 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2786 if(sc->hw.mac.autoneg && 2787 !e1000_copper_link_autoneg(&sc->hw) && 2788 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2789 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2790 MII_CR_RESTART_AUTO_NEG); 2791 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2792 } 2793 } 2794 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2795 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2796 sc->smartspeed = 0; 2797 } 2798 2799 /********************************************************************* 2800 * 2801 * Initialize the DMA Coalescing feature 2802 * 2803 **********************************************************************/ 2804 static void 2805 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2806 { 2807 device_t dev = sc->dev; 2808 struct e1000_hw *hw = &sc->hw; 2809 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2810 u16 hwm; 2811 u16 max_frame_size; 2812 2813 if (hw->mac.type == e1000_i211) 2814 return; 2815 2816 max_frame_size = sc->shared->isc_max_frame_size; 2817 if (hw->mac.type > e1000_82580) { 2818 2819 if (sc->dmac == 0) { /* Disabling it */ 2820 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2821 return; 2822 } else 2823 device_printf(dev, "DMA Coalescing enabled\n"); 2824 2825 /* Set starting threshold */ 2826 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2827 2828 hwm = 64 * pba - max_frame_size / 16; 2829 if (hwm < 64 * (pba - 6)) 2830 hwm = 64 * (pba - 6); 2831 reg = E1000_READ_REG(hw, E1000_FCRTC); 2832 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2833 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2834 & E1000_FCRTC_RTH_COAL_MASK); 2835 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2836 2837 2838 dmac = pba - max_frame_size / 512; 2839 if (dmac < pba - 10) 2840 dmac = pba - 10; 2841 reg = E1000_READ_REG(hw, E1000_DMACR); 2842 reg &= ~E1000_DMACR_DMACTHR_MASK; 2843 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2844 & E1000_DMACR_DMACTHR_MASK); 2845 2846 /* transition to L0x or L1 if available..*/ 2847 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2848 2849 /* Check if status is 2.5Gb backplane connection 2850 * before configuration of watchdog timer, which is 2851 * in msec values in 12.8usec intervals 2852 * watchdog timer= msec values in 32usec intervals 2853 * for non 2.5Gb connection 2854 */ 2855 if (hw->mac.type == e1000_i354) { 2856 int status = E1000_READ_REG(hw, E1000_STATUS); 2857 if ((status & E1000_STATUS_2P5_SKU) && 2858 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2859 reg |= ((sc->dmac * 5) >> 6); 2860 else 2861 reg |= (sc->dmac >> 5); 2862 } else { 2863 reg |= (sc->dmac >> 5); 2864 } 2865 2866 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2867 2868 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2869 2870 /* Set the interval before transition */ 2871 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2872 if (hw->mac.type == e1000_i350) 2873 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2874 /* 2875 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2876 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2877 */ 2878 if (hw->mac.type == e1000_i354) { 2879 int status = E1000_READ_REG(hw, E1000_STATUS); 2880 if ((status & E1000_STATUS_2P5_SKU) && 2881 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2882 reg |= 0xA; 2883 else 2884 reg |= 0x4; 2885 } else { 2886 reg |= 0x4; 2887 } 2888 2889 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2890 2891 /* free space in tx packet buffer to wake from DMA coal */ 2892 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2893 (2 * max_frame_size)) >> 6); 2894 2895 /* make low power state decision controlled by DMA coal */ 2896 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2897 reg &= ~E1000_PCIEMISC_LX_DECISION; 2898 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2899 2900 } else if (hw->mac.type == e1000_82580) { 2901 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2902 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2903 reg & ~E1000_PCIEMISC_LX_DECISION); 2904 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2905 } 2906 } 2907 /********************************************************************* 2908 * The 3 following flush routines are used as a workaround in the 2909 * I219 client parts and only for them. 2910 * 2911 * em_flush_tx_ring - remove all descriptors from the tx_ring 2912 * 2913 * We want to clear all pending descriptors from the TX ring. 2914 * zeroing happens when the HW reads the regs. We assign the ring itself as 2915 * the data of the next descriptor. We don't care about the data we are about 2916 * to reset the HW. 2917 **********************************************************************/ 2918 static void 2919 em_flush_tx_ring(struct e1000_softc *sc) 2920 { 2921 struct e1000_hw *hw = &sc->hw; 2922 struct tx_ring *txr = &sc->tx_queues->txr; 2923 struct e1000_tx_desc *txd; 2924 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2925 u16 size = 512; 2926 2927 tctl = E1000_READ_REG(hw, E1000_TCTL); 2928 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2929 2930 txd = &txr->tx_base[txr->tx_cidx_processed]; 2931 2932 /* Just use the ring as a dummy buffer addr */ 2933 txd->buffer_addr = txr->tx_paddr; 2934 txd->lower.data = htole32(txd_lower | size); 2935 txd->upper.data = 0; 2936 2937 /* flush descriptors to memory before notifying the HW */ 2938 wmb(); 2939 2940 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2941 mb(); 2942 usec_delay(250); 2943 } 2944 2945 /********************************************************************* 2946 * em_flush_rx_ring - remove all descriptors from the rx_ring 2947 * 2948 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2949 **********************************************************************/ 2950 static void 2951 em_flush_rx_ring(struct e1000_softc *sc) 2952 { 2953 struct e1000_hw *hw = &sc->hw; 2954 u32 rctl, rxdctl; 2955 2956 rctl = E1000_READ_REG(hw, E1000_RCTL); 2957 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2958 E1000_WRITE_FLUSH(hw); 2959 usec_delay(150); 2960 2961 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2962 /* zero the lower 14 bits (prefetch and host thresholds) */ 2963 rxdctl &= 0xffffc000; 2964 /* 2965 * update thresholds: prefetch threshold to 31, host threshold to 1 2966 * and make sure the granularity is "descriptors" and not 2967 * "cache lines" 2968 */ 2969 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2970 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2971 2972 /* momentarily enable the RX ring for the changes to take effect */ 2973 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2974 E1000_WRITE_FLUSH(hw); 2975 usec_delay(150); 2976 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2977 } 2978 2979 /********************************************************************* 2980 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2981 * 2982 * In I219, the descriptor rings must be emptied before resetting the HW 2983 * or before changing the device state to D3 during runtime (runtime PM). 2984 * 2985 * Failure to do this will cause the HW to enter a unit hang state which can 2986 * only be released by PCI reset on the device 2987 * 2988 **********************************************************************/ 2989 static void 2990 em_flush_desc_rings(struct e1000_softc *sc) 2991 { 2992 struct e1000_hw *hw = &sc->hw; 2993 device_t dev = sc->dev; 2994 u16 hang_state; 2995 u32 fext_nvm11, tdlen; 2996 2997 /* First, disable MULR fix in FEXTNVM11 */ 2998 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2999 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3000 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3001 3002 /* do nothing if we're not in faulty state, or the queue is empty */ 3003 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3004 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3005 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3006 return; 3007 em_flush_tx_ring(sc); 3008 3009 /* recheck, maybe the fault is caused by the rx ring */ 3010 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3011 if (hang_state & FLUSH_DESC_REQUIRED) 3012 em_flush_rx_ring(sc); 3013 } 3014 3015 3016 /********************************************************************* 3017 * 3018 * Initialize the hardware to a configuration as specified by the 3019 * sc structure. 3020 * 3021 **********************************************************************/ 3022 static void 3023 em_reset(if_ctx_t ctx) 3024 { 3025 device_t dev = iflib_get_dev(ctx); 3026 struct e1000_softc *sc = iflib_get_softc(ctx); 3027 if_t ifp = iflib_get_ifp(ctx); 3028 struct e1000_hw *hw = &sc->hw; 3029 u32 rx_buffer_size; 3030 u32 pba; 3031 3032 INIT_DEBUGOUT("em_reset: begin"); 3033 /* Let the firmware know the OS is in control */ 3034 em_get_hw_control(sc); 3035 3036 /* Set up smart power down as default off on newer adapters. */ 3037 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3038 hw->mac.type == e1000_82572)) { 3039 u16 phy_tmp = 0; 3040 3041 /* Speed up time to link by disabling smart power down. */ 3042 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3043 phy_tmp &= ~IGP02E1000_PM_SPD; 3044 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3045 } 3046 3047 /* 3048 * Packet Buffer Allocation (PBA) 3049 * Writing PBA sets the receive portion of the buffer 3050 * the remainder is used for the transmit buffer. 3051 */ 3052 switch (hw->mac.type) { 3053 /* 82547: Total Packet Buffer is 40K */ 3054 case e1000_82547: 3055 case e1000_82547_rev_2: 3056 if (hw->mac.max_frame_size > 8192) 3057 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3058 else 3059 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3060 break; 3061 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3062 case e1000_82571: 3063 case e1000_82572: 3064 case e1000_80003es2lan: 3065 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3066 break; 3067 /* 82573: Total Packet Buffer is 32K */ 3068 case e1000_82573: 3069 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3070 break; 3071 case e1000_82574: 3072 case e1000_82583: 3073 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 3074 break; 3075 case e1000_ich8lan: 3076 pba = E1000_PBA_8K; 3077 break; 3078 case e1000_ich9lan: 3079 case e1000_ich10lan: 3080 /* Boost Receive side for jumbo frames */ 3081 if (hw->mac.max_frame_size > 4096) 3082 pba = E1000_PBA_14K; 3083 else 3084 pba = E1000_PBA_10K; 3085 break; 3086 case e1000_pchlan: 3087 case e1000_pch2lan: 3088 case e1000_pch_lpt: 3089 case e1000_pch_spt: 3090 case e1000_pch_cnp: 3091 case e1000_pch_tgp: 3092 case e1000_pch_adp: 3093 case e1000_pch_mtp: 3094 case e1000_pch_ptp: 3095 pba = E1000_PBA_26K; 3096 break; 3097 case e1000_82575: 3098 pba = E1000_PBA_32K; 3099 break; 3100 case e1000_82576: 3101 case e1000_vfadapt: 3102 pba = E1000_READ_REG(hw, E1000_RXPBS); 3103 pba &= E1000_RXPBS_SIZE_MASK_82576; 3104 break; 3105 case e1000_82580: 3106 case e1000_i350: 3107 case e1000_i354: 3108 case e1000_vfadapt_i350: 3109 pba = E1000_READ_REG(hw, E1000_RXPBS); 3110 pba = e1000_rxpbs_adjust_82580(pba); 3111 break; 3112 case e1000_i210: 3113 case e1000_i211: 3114 pba = E1000_PBA_34K; 3115 break; 3116 default: 3117 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3118 if (hw->mac.max_frame_size > 8192) 3119 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3120 else 3121 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3122 } 3123 3124 /* Special needs in case of Jumbo frames */ 3125 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3126 u32 tx_space, min_tx, min_rx; 3127 pba = E1000_READ_REG(hw, E1000_PBA); 3128 tx_space = pba >> 16; 3129 pba &= 0xffff; 3130 min_tx = (hw->mac.max_frame_size + 3131 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3132 min_tx = roundup2(min_tx, 1024); 3133 min_tx >>= 10; 3134 min_rx = hw->mac.max_frame_size; 3135 min_rx = roundup2(min_rx, 1024); 3136 min_rx >>= 10; 3137 if (tx_space < min_tx && 3138 ((min_tx - tx_space) < pba)) { 3139 pba = pba - (min_tx - tx_space); 3140 /* 3141 * if short on rx space, rx wins 3142 * and must trump tx adjustment 3143 */ 3144 if (pba < min_rx) 3145 pba = min_rx; 3146 } 3147 E1000_WRITE_REG(hw, E1000_PBA, pba); 3148 } 3149 3150 if (hw->mac.type < igb_mac_min) 3151 E1000_WRITE_REG(hw, E1000_PBA, pba); 3152 3153 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3154 3155 /* 3156 * These parameters control the automatic generation (Tx) and 3157 * response (Rx) to Ethernet PAUSE frames. 3158 * - High water mark should allow for at least two frames to be 3159 * received after sending an XOFF. 3160 * - Low water mark works best when it is very near the high water 3161 mark. 3162 * This allows the receiver to restart by sending XON when it has 3163 * drained a bit. Here we use an arbitrary value of 1500 which will 3164 * restart after one full frame is pulled from the buffer. There 3165 * could be several smaller frames in the buffer and if so they will 3166 * not trigger the XON until their total number reduces the buffer 3167 * by 1500. 3168 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3169 */ 3170 rx_buffer_size = (pba & 0xffff) << 10; 3171 hw->fc.high_water = rx_buffer_size - 3172 roundup2(hw->mac.max_frame_size, 1024); 3173 hw->fc.low_water = hw->fc.high_water - 1500; 3174 3175 if (sc->fc) /* locally set flow control value? */ 3176 hw->fc.requested_mode = sc->fc; 3177 else 3178 hw->fc.requested_mode = e1000_fc_full; 3179 3180 if (hw->mac.type == e1000_80003es2lan) 3181 hw->fc.pause_time = 0xFFFF; 3182 else 3183 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3184 3185 hw->fc.send_xon = true; 3186 3187 /* Device specific overrides/settings */ 3188 switch (hw->mac.type) { 3189 case e1000_pchlan: 3190 /* Workaround: no TX flow ctrl for PCH */ 3191 hw->fc.requested_mode = e1000_fc_rx_pause; 3192 hw->fc.pause_time = 0xFFFF; /* override */ 3193 if (if_getmtu(ifp) > ETHERMTU) { 3194 hw->fc.high_water = 0x3500; 3195 hw->fc.low_water = 0x1500; 3196 } else { 3197 hw->fc.high_water = 0x5000; 3198 hw->fc.low_water = 0x3000; 3199 } 3200 hw->fc.refresh_time = 0x1000; 3201 break; 3202 case e1000_pch2lan: 3203 case e1000_pch_lpt: 3204 case e1000_pch_spt: 3205 case e1000_pch_cnp: 3206 case e1000_pch_tgp: 3207 case e1000_pch_adp: 3208 case e1000_pch_mtp: 3209 case e1000_pch_ptp: 3210 hw->fc.high_water = 0x5C20; 3211 hw->fc.low_water = 0x5048; 3212 hw->fc.pause_time = 0x0650; 3213 hw->fc.refresh_time = 0x0400; 3214 /* Jumbos need adjusted PBA */ 3215 if (if_getmtu(ifp) > ETHERMTU) 3216 E1000_WRITE_REG(hw, E1000_PBA, 12); 3217 else 3218 E1000_WRITE_REG(hw, E1000_PBA, 26); 3219 break; 3220 case e1000_82575: 3221 case e1000_82576: 3222 /* 8-byte granularity */ 3223 hw->fc.low_water = hw->fc.high_water - 8; 3224 break; 3225 case e1000_82580: 3226 case e1000_i350: 3227 case e1000_i354: 3228 case e1000_i210: 3229 case e1000_i211: 3230 case e1000_vfadapt: 3231 case e1000_vfadapt_i350: 3232 /* 16-byte granularity */ 3233 hw->fc.low_water = hw->fc.high_water - 16; 3234 break; 3235 case e1000_ich9lan: 3236 case e1000_ich10lan: 3237 if (if_getmtu(ifp) > ETHERMTU) { 3238 hw->fc.high_water = 0x2800; 3239 hw->fc.low_water = hw->fc.high_water - 8; 3240 break; 3241 } 3242 /* FALLTHROUGH */ 3243 default: 3244 if (hw->mac.type == e1000_80003es2lan) 3245 hw->fc.pause_time = 0xFFFF; 3246 break; 3247 } 3248 3249 /* I219 needs some special flushing to avoid hangs */ 3250 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3251 em_flush_desc_rings(sc); 3252 3253 /* Issue a global reset */ 3254 e1000_reset_hw(hw); 3255 if (hw->mac.type >= igb_mac_min) { 3256 E1000_WRITE_REG(hw, E1000_WUC, 0); 3257 } else { 3258 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3259 em_disable_aspm(sc); 3260 } 3261 if (sc->flags & IGB_MEDIA_RESET) { 3262 e1000_setup_init_funcs(hw, true); 3263 e1000_get_bus_info(hw); 3264 sc->flags &= ~IGB_MEDIA_RESET; 3265 } 3266 /* and a re-init */ 3267 if (e1000_init_hw(hw) < 0) { 3268 device_printf(dev, "Hardware Initialization Failed\n"); 3269 return; 3270 } 3271 if (hw->mac.type >= igb_mac_min) 3272 igb_init_dmac(sc, pba); 3273 3274 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3275 sc->pba = pba; 3276 3277 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3278 e1000_get_phy_info(hw); 3279 e1000_check_for_link(hw); 3280 } 3281 3282 /* 3283 * Initialise the RSS mapping for NICs that support multiple transmit/ 3284 * receive rings. 3285 */ 3286 3287 #define RSSKEYLEN 10 3288 static void 3289 em_initialize_rss_mapping(struct e1000_softc *sc) 3290 { 3291 uint8_t rss_key[4 * RSSKEYLEN]; 3292 uint32_t reta = 0; 3293 struct e1000_hw *hw = &sc->hw; 3294 int i; 3295 3296 /* 3297 * Configure RSS key 3298 */ 3299 arc4rand(rss_key, sizeof(rss_key), 0); 3300 for (i = 0; i < RSSKEYLEN; ++i) { 3301 uint32_t rssrk = 0; 3302 3303 rssrk = EM_RSSRK_VAL(rss_key, i); 3304 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3305 } 3306 3307 /* 3308 * Configure RSS redirect table in following fashion: 3309 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3310 */ 3311 for (i = 0; i < sizeof(reta); ++i) { 3312 uint32_t q; 3313 3314 q = (i % sc->rx_num_queues) << 7; 3315 reta |= q << (8 * i); 3316 } 3317 3318 for (i = 0; i < 32; ++i) 3319 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3320 3321 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3322 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3323 E1000_MRQC_RSS_FIELD_IPV4 | 3324 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3325 E1000_MRQC_RSS_FIELD_IPV6_EX | 3326 E1000_MRQC_RSS_FIELD_IPV6); 3327 } 3328 3329 static void 3330 igb_initialize_rss_mapping(struct e1000_softc *sc) 3331 { 3332 struct e1000_hw *hw = &sc->hw; 3333 int i; 3334 int queue_id; 3335 u32 reta; 3336 u32 rss_key[10], mrqc, shift = 0; 3337 3338 /* XXX? */ 3339 if (hw->mac.type == e1000_82575) 3340 shift = 6; 3341 3342 /* 3343 * The redirection table controls which destination 3344 * queue each bucket redirects traffic to. 3345 * Each DWORD represents four queues, with the LSB 3346 * being the first queue in the DWORD. 3347 * 3348 * This just allocates buckets to queues using round-robin 3349 * allocation. 3350 * 3351 * NOTE: It Just Happens to line up with the default 3352 * RSS allocation method. 3353 */ 3354 3355 /* Warning FM follows */ 3356 reta = 0; 3357 for (i = 0; i < 128; i++) { 3358 #ifdef RSS 3359 queue_id = rss_get_indirection_to_bucket(i); 3360 /* 3361 * If we have more queues than buckets, we'll 3362 * end up mapping buckets to a subset of the 3363 * queues. 3364 * 3365 * If we have more buckets than queues, we'll 3366 * end up instead assigning multiple buckets 3367 * to queues. 3368 * 3369 * Both are suboptimal, but we need to handle 3370 * the case so we don't go out of bounds 3371 * indexing arrays and such. 3372 */ 3373 queue_id = queue_id % sc->rx_num_queues; 3374 #else 3375 queue_id = (i % sc->rx_num_queues); 3376 #endif 3377 /* Adjust if required */ 3378 queue_id = queue_id << shift; 3379 3380 /* 3381 * The low 8 bits are for hash value (n+0); 3382 * The next 8 bits are for hash value (n+1), etc. 3383 */ 3384 reta = reta >> 8; 3385 reta = reta | ( ((uint32_t) queue_id) << 24); 3386 if ((i & 3) == 3) { 3387 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3388 reta = 0; 3389 } 3390 } 3391 3392 /* Now fill in hash table */ 3393 3394 /* 3395 * MRQC: Multiple Receive Queues Command 3396 * Set queuing to RSS control, number depends on the device. 3397 */ 3398 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3399 3400 #ifdef RSS 3401 /* XXX ew typecasting */ 3402 rss_getkey((uint8_t *) &rss_key); 3403 #else 3404 arc4rand(&rss_key, sizeof(rss_key), 0); 3405 #endif 3406 for (i = 0; i < 10; i++) 3407 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3408 3409 /* 3410 * Configure the RSS fields to hash upon. 3411 */ 3412 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3413 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3414 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3415 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3416 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3417 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3418 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3419 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3420 3421 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3422 } 3423 3424 /********************************************************************* 3425 * 3426 * Setup networking device structure and register interface media. 3427 * 3428 **********************************************************************/ 3429 static int 3430 em_setup_interface(if_ctx_t ctx) 3431 { 3432 if_t ifp = iflib_get_ifp(ctx); 3433 struct e1000_softc *sc = iflib_get_softc(ctx); 3434 if_softc_ctx_t scctx = sc->shared; 3435 3436 INIT_DEBUGOUT("em_setup_interface: begin"); 3437 3438 /* Single Queue */ 3439 if (sc->tx_num_queues == 1) { 3440 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3441 if_setsendqready(ifp); 3442 } 3443 3444 /* 3445 * Specify the media types supported by this adapter and register 3446 * callbacks to update media and link information 3447 */ 3448 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3449 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3450 u_char fiber_type = IFM_1000_SX; /* default type */ 3451 3452 if (sc->hw.mac.type == e1000_82545) 3453 fiber_type = IFM_1000_LX; 3454 ifmedia_add(sc->media, 3455 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3456 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3457 } else { 3458 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3459 ifmedia_add(sc->media, 3460 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3461 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3462 ifmedia_add(sc->media, 3463 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3464 if (sc->hw.phy.type != e1000_phy_ife) { 3465 ifmedia_add(sc->media, 3466 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3467 ifmedia_add(sc->media, 3468 IFM_ETHER | IFM_1000_T, 0, NULL); 3469 } 3470 } 3471 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3472 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3473 return (0); 3474 } 3475 3476 static int 3477 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3478 int ntxqs, int ntxqsets) 3479 { 3480 struct e1000_softc *sc = iflib_get_softc(ctx); 3481 if_softc_ctx_t scctx = sc->shared; 3482 int error = E1000_SUCCESS; 3483 struct em_tx_queue *que; 3484 int i, j; 3485 3486 MPASS(sc->tx_num_queues > 0); 3487 MPASS(sc->tx_num_queues == ntxqsets); 3488 3489 /* First allocate the top level queue structs */ 3490 if (!(sc->tx_queues = 3491 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3492 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3493 device_printf(iflib_get_dev(ctx), 3494 "Unable to allocate queue memory\n"); 3495 return(ENOMEM); 3496 } 3497 3498 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3499 /* Set up some basics */ 3500 3501 struct tx_ring *txr = &que->txr; 3502 txr->sc = que->sc = sc; 3503 que->me = txr->me = i; 3504 3505 /* Allocate report status array */ 3506 if (!(txr->tx_rsq = 3507 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3508 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3509 device_printf(iflib_get_dev(ctx), 3510 "failed to allocate rs_idxs memory\n"); 3511 error = ENOMEM; 3512 goto fail; 3513 } 3514 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3515 txr->tx_rsq[j] = QIDX_INVALID; 3516 /* get the virtual and physical address of hardware queues */ 3517 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3518 txr->tx_paddr = paddrs[i*ntxqs]; 3519 } 3520 3521 if (bootverbose) 3522 device_printf(iflib_get_dev(ctx), 3523 "allocated for %d tx_queues\n", sc->tx_num_queues); 3524 return (0); 3525 fail: 3526 em_if_queues_free(ctx); 3527 return (error); 3528 } 3529 3530 static int 3531 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3532 int nrxqs, int nrxqsets) 3533 { 3534 struct e1000_softc *sc = iflib_get_softc(ctx); 3535 int error = E1000_SUCCESS; 3536 struct em_rx_queue *que; 3537 int i; 3538 3539 MPASS(sc->rx_num_queues > 0); 3540 MPASS(sc->rx_num_queues == nrxqsets); 3541 3542 /* First allocate the top level queue structs */ 3543 if (!(sc->rx_queues = 3544 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3545 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3546 device_printf(iflib_get_dev(ctx), 3547 "Unable to allocate queue memory\n"); 3548 error = ENOMEM; 3549 goto fail; 3550 } 3551 3552 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3553 /* Set up some basics */ 3554 struct rx_ring *rxr = &que->rxr; 3555 rxr->sc = que->sc = sc; 3556 rxr->que = que; 3557 que->me = rxr->me = i; 3558 3559 /* get the virtual and physical address of hardware queues */ 3560 rxr->rx_base = 3561 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3562 rxr->rx_paddr = paddrs[i*nrxqs]; 3563 } 3564 3565 if (bootverbose) 3566 device_printf(iflib_get_dev(ctx), 3567 "allocated for %d rx_queues\n", sc->rx_num_queues); 3568 3569 return (0); 3570 fail: 3571 em_if_queues_free(ctx); 3572 return (error); 3573 } 3574 3575 static void 3576 em_if_queues_free(if_ctx_t ctx) 3577 { 3578 struct e1000_softc *sc = iflib_get_softc(ctx); 3579 struct em_tx_queue *tx_que = sc->tx_queues; 3580 struct em_rx_queue *rx_que = sc->rx_queues; 3581 3582 if (tx_que != NULL) { 3583 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3584 struct tx_ring *txr = &tx_que->txr; 3585 if (txr->tx_rsq == NULL) 3586 break; 3587 3588 free(txr->tx_rsq, M_DEVBUF); 3589 txr->tx_rsq = NULL; 3590 } 3591 free(sc->tx_queues, M_DEVBUF); 3592 sc->tx_queues = NULL; 3593 } 3594 3595 if (rx_que != NULL) { 3596 free(sc->rx_queues, M_DEVBUF); 3597 sc->rx_queues = NULL; 3598 } 3599 } 3600 3601 /********************************************************************* 3602 * 3603 * Enable transmit unit. 3604 * 3605 **********************************************************************/ 3606 static void 3607 em_initialize_transmit_unit(if_ctx_t ctx) 3608 { 3609 struct e1000_softc *sc = iflib_get_softc(ctx); 3610 if_softc_ctx_t scctx = sc->shared; 3611 struct em_tx_queue *que; 3612 struct tx_ring *txr; 3613 struct e1000_hw *hw = &sc->hw; 3614 u32 tctl, txdctl = 0, tarc, tipg = 0; 3615 3616 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3617 3618 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3619 u64 bus_addr; 3620 caddr_t offp, endp; 3621 3622 que = &sc->tx_queues[i]; 3623 txr = &que->txr; 3624 bus_addr = txr->tx_paddr; 3625 3626 /* Clear checksum offload context. */ 3627 offp = (caddr_t)&txr->csum_flags; 3628 endp = (caddr_t)(txr + 1); 3629 bzero(offp, endp - offp); 3630 3631 /* Base and Len of TX Ring */ 3632 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3633 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3634 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3635 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3636 /* Init the HEAD/TAIL indices */ 3637 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3638 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3639 3640 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3641 E1000_READ_REG(hw, E1000_TDBAL(i)), 3642 E1000_READ_REG(hw, E1000_TDLEN(i))); 3643 3644 txdctl = 0; /* clear txdctl */ 3645 txdctl |= 0x1f; /* PTHRESH */ 3646 txdctl |= 1 << 8; /* HTHRESH */ 3647 txdctl |= 1 << 16;/* WTHRESH */ 3648 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3649 txdctl |= E1000_TXDCTL_GRAN; 3650 txdctl |= 1 << 25; /* LWTHRESH */ 3651 3652 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3653 } 3654 3655 /* Set the default values for the Tx Inter Packet Gap timer */ 3656 switch (hw->mac.type) { 3657 case e1000_80003es2lan: 3658 tipg = DEFAULT_82543_TIPG_IPGR1; 3659 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3660 E1000_TIPG_IPGR2_SHIFT; 3661 break; 3662 case e1000_82542: 3663 tipg = DEFAULT_82542_TIPG_IPGT; 3664 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3665 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3666 break; 3667 default: 3668 if (hw->phy.media_type == e1000_media_type_fiber || 3669 hw->phy.media_type == e1000_media_type_internal_serdes) 3670 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3671 else 3672 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3673 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3674 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3675 } 3676 3677 if (hw->mac.type < igb_mac_min) { 3678 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3679 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3680 3681 if (sc->tx_int_delay.value > 0) 3682 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3683 } 3684 3685 if (hw->mac.type >= e1000_82540) 3686 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3687 3688 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3689 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3690 tarc |= TARC_SPEED_MODE_BIT; 3691 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3692 } else if (hw->mac.type == e1000_80003es2lan) { 3693 /* errata: program both queues to unweighted RR */ 3694 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3695 tarc |= 1; 3696 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3697 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3698 tarc |= 1; 3699 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3700 } else if (hw->mac.type == e1000_82574) { 3701 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3702 tarc |= TARC_ERRATA_BIT; 3703 if ( sc->tx_num_queues > 1) { 3704 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3705 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3706 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3707 } else 3708 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3709 } 3710 3711 /* Program the Transmit Control Register */ 3712 tctl = E1000_READ_REG(hw, E1000_TCTL); 3713 tctl &= ~E1000_TCTL_CT; 3714 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3715 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3716 3717 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3718 tctl |= E1000_TCTL_MULR; 3719 3720 /* This write will effectively turn on the transmit unit. */ 3721 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3722 3723 /* SPT and KBL errata workarounds */ 3724 if (hw->mac.type == e1000_pch_spt) { 3725 u32 reg; 3726 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3727 reg |= E1000_RCTL_RDMTS_HEX; 3728 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3729 /* i218-i219 Specification Update 1.5.4.5 */ 3730 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3731 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3732 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3733 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3734 } 3735 } 3736 3737 /********************************************************************* 3738 * 3739 * Enable receive unit. 3740 * 3741 **********************************************************************/ 3742 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3743 3744 static void 3745 em_initialize_receive_unit(if_ctx_t ctx) 3746 { 3747 struct e1000_softc *sc = iflib_get_softc(ctx); 3748 if_softc_ctx_t scctx = sc->shared; 3749 if_t ifp = iflib_get_ifp(ctx); 3750 struct e1000_hw *hw = &sc->hw; 3751 struct em_rx_queue *que; 3752 int i; 3753 uint32_t rctl, rxcsum; 3754 3755 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3756 3757 /* 3758 * Make sure receives are disabled while setting 3759 * up the descriptor ring 3760 */ 3761 rctl = E1000_READ_REG(hw, E1000_RCTL); 3762 /* Do not disable if ever enabled on this hardware */ 3763 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3764 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3765 3766 /* Setup the Receive Control Register */ 3767 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3768 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3769 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3770 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3771 3772 /* Do not store bad packets */ 3773 rctl &= ~E1000_RCTL_SBP; 3774 3775 /* Enable Long Packet receive */ 3776 if (if_getmtu(ifp) > ETHERMTU) 3777 rctl |= E1000_RCTL_LPE; 3778 else 3779 rctl &= ~E1000_RCTL_LPE; 3780 3781 /* Strip the CRC */ 3782 if (!em_disable_crc_stripping) 3783 rctl |= E1000_RCTL_SECRC; 3784 3785 /* lem/em default interrupt moderation */ 3786 if (hw->mac.type < igb_mac_min) { 3787 if (hw->mac.type >= e1000_82540) { 3788 E1000_WRITE_REG(hw, E1000_RADV, 3789 sc->rx_abs_int_delay.value); 3790 3791 /* Set the default interrupt throttling rate */ 3792 E1000_WRITE_REG(hw, E1000_ITR, 3793 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3794 } 3795 3796 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3797 * long latencies are observed, like Lenovo X60. This 3798 * change eliminates the problem, but since having positive 3799 * values in RDTR is a known source of problems on other 3800 * platforms another solution is being sought. 3801 */ 3802 if (hw->mac.type == e1000_82573) 3803 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3804 else 3805 E1000_WRITE_REG(hw, E1000_RDTR, 3806 sc->rx_int_delay.value); 3807 } 3808 3809 if (hw->mac.type >= em_mac_min) { 3810 uint32_t rfctl; 3811 /* Use extended rx descriptor formats */ 3812 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3813 rfctl |= E1000_RFCTL_EXTEN; 3814 3815 /* 3816 * When using MSI-X interrupts we need to throttle 3817 * using the EITR register (82574 only) 3818 */ 3819 if (hw->mac.type == e1000_82574) { 3820 for (int i = 0; i < 4; i++) 3821 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3822 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3823 /* Disable accelerated acknowledge */ 3824 rfctl |= E1000_RFCTL_ACK_DIS; 3825 } 3826 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3827 } 3828 3829 /* Set up L3 and L4 csum Rx descriptor offloads */ 3830 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3831 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3832 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3833 if (hw->mac.type > e1000_82575) 3834 rxcsum |= E1000_RXCSUM_CRCOFL; 3835 else if (hw->mac.type < em_mac_min && 3836 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3837 rxcsum |= E1000_RXCSUM_IPV6OFL; 3838 } else { 3839 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3840 if (hw->mac.type > e1000_82575) 3841 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3842 else if (hw->mac.type < em_mac_min) 3843 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3844 } 3845 3846 if (sc->rx_num_queues > 1) { 3847 /* RSS hash needed in the Rx descriptor */ 3848 rxcsum |= E1000_RXCSUM_PCSD; 3849 3850 if (hw->mac.type >= igb_mac_min) 3851 igb_initialize_rss_mapping(sc); 3852 else 3853 em_initialize_rss_mapping(sc); 3854 } 3855 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3856 3857 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3858 struct rx_ring *rxr = &que->rxr; 3859 /* Setup the Base and Length of the Rx Descriptor Ring */ 3860 u64 bus_addr = rxr->rx_paddr; 3861 #if 0 3862 u32 rdt = sc->rx_num_queues -1; /* default */ 3863 #endif 3864 3865 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3866 scctx->isc_nrxd[0] * 3867 sizeof(union e1000_rx_desc_extended)); 3868 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3869 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3870 /* Setup the Head and Tail Descriptor Pointers */ 3871 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3872 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3873 } 3874 3875 /* 3876 * Set PTHRESH for improved jumbo performance 3877 * According to 10.2.5.11 of Intel 82574 Datasheet, 3878 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3879 * Only write to RXDCTL(1) if there is a need for different 3880 * settings. 3881 */ 3882 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3883 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3884 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3885 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3886 } else if (hw->mac.type == e1000_82574) { 3887 for (int i = 0; i < sc->rx_num_queues; i++) { 3888 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3889 rxdctl |= 0x20; /* PTHRESH */ 3890 rxdctl |= 4 << 8; /* HTHRESH */ 3891 rxdctl |= 4 << 16;/* WTHRESH */ 3892 rxdctl |= 1 << 24; /* Switch to granularity */ 3893 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3894 } 3895 } else if (hw->mac.type >= igb_mac_min) { 3896 u32 psize, srrctl = 0; 3897 3898 if (if_getmtu(ifp) > ETHERMTU) { 3899 psize = scctx->isc_max_frame_size; 3900 /* are we on a vlan? */ 3901 if (if_vlantrunkinuse(ifp)) 3902 psize += VLAN_TAG_SIZE; 3903 3904 if (sc->vf_ifp) 3905 e1000_rlpml_set_vf(hw, psize); 3906 else 3907 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3908 } 3909 3910 /* Set maximum packet buffer len */ 3911 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3912 E1000_SRRCTL_BSIZEPKT_SHIFT; 3913 3914 /* 3915 * If TX flow control is disabled and there's >1 queue 3916 * defined, enable DROP. 3917 * 3918 * This drops frames rather than hanging the RX MAC for all 3919 * queues. 3920 */ 3921 if ((sc->rx_num_queues > 1) && 3922 (sc->fc == e1000_fc_none || 3923 sc->fc == e1000_fc_rx_pause)) { 3924 srrctl |= E1000_SRRCTL_DROP_EN; 3925 } 3926 /* Setup the Base and Length of the Rx Descriptor Rings */ 3927 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3928 i++, que++) { 3929 struct rx_ring *rxr = &que->rxr; 3930 u64 bus_addr = rxr->rx_paddr; 3931 u32 rxdctl; 3932 3933 #ifdef notyet 3934 /* Configure for header split? -- ignore for now */ 3935 rxr->hdr_split = igb_header_split; 3936 #else 3937 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3938 #endif 3939 3940 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3941 scctx->isc_nrxd[0] * 3942 sizeof(struct e1000_rx_desc)); 3943 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3944 (uint32_t)(bus_addr >> 32)); 3945 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3946 (uint32_t)bus_addr); 3947 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3948 /* Enable this Queue */ 3949 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3950 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3951 rxdctl &= 0xFFF00000; 3952 rxdctl |= IGB_RX_PTHRESH; 3953 rxdctl |= IGB_RX_HTHRESH << 8; 3954 rxdctl |= IGB_RX_WTHRESH << 16; 3955 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3956 } 3957 } else if (hw->mac.type >= e1000_pch2lan) { 3958 if (if_getmtu(ifp) > ETHERMTU) 3959 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3960 else 3961 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3962 } 3963 3964 /* Make sure VLAN Filters are off */ 3965 rctl &= ~E1000_RCTL_VFE; 3966 3967 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3968 if (hw->mac.type < igb_mac_min) { 3969 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3970 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3971 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3972 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3973 else if (sc->rx_mbuf_sz > 8192) 3974 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3975 else { 3976 rctl |= E1000_RCTL_SZ_2048; 3977 rctl &= ~E1000_RCTL_BSEX; 3978 } 3979 } else 3980 rctl |= E1000_RCTL_SZ_2048; 3981 3982 /* 3983 * rctl bits 11:10 are as follows 3984 * lem: reserved 3985 * em: DTYPE 3986 * igb: reserved 3987 * and should be 00 on all of the above 3988 */ 3989 rctl &= ~0x00000C00; 3990 3991 /* Write out the settings */ 3992 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3993 3994 return; 3995 } 3996 3997 static void 3998 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3999 { 4000 struct e1000_softc *sc = iflib_get_softc(ctx); 4001 u32 index, bit; 4002 4003 index = (vtag >> 5) & 0x7F; 4004 bit = vtag & 0x1F; 4005 sc->shadow_vfta[index] |= (1 << bit); 4006 ++sc->num_vlans; 4007 em_if_vlan_filter_write(sc); 4008 } 4009 4010 static void 4011 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4012 { 4013 struct e1000_softc *sc = iflib_get_softc(ctx); 4014 u32 index, bit; 4015 4016 index = (vtag >> 5) & 0x7F; 4017 bit = vtag & 0x1F; 4018 sc->shadow_vfta[index] &= ~(1 << bit); 4019 --sc->num_vlans; 4020 em_if_vlan_filter_write(sc); 4021 } 4022 4023 static bool 4024 em_if_vlan_filter_capable(if_ctx_t ctx) 4025 { 4026 if_t ifp = iflib_get_ifp(ctx); 4027 4028 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4029 !em_disable_crc_stripping) 4030 return (true); 4031 4032 return (false); 4033 } 4034 4035 static bool 4036 em_if_vlan_filter_used(if_ctx_t ctx) 4037 { 4038 struct e1000_softc *sc = iflib_get_softc(ctx); 4039 4040 if (!em_if_vlan_filter_capable(ctx)) 4041 return (false); 4042 4043 for (int i = 0; i < EM_VFTA_SIZE; i++) 4044 if (sc->shadow_vfta[i] != 0) 4045 return (true); 4046 4047 return (false); 4048 } 4049 4050 static void 4051 em_if_vlan_filter_enable(struct e1000_softc *sc) 4052 { 4053 struct e1000_hw *hw = &sc->hw; 4054 u32 reg; 4055 4056 reg = E1000_READ_REG(hw, E1000_RCTL); 4057 reg &= ~E1000_RCTL_CFIEN; 4058 reg |= E1000_RCTL_VFE; 4059 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4060 } 4061 4062 static void 4063 em_if_vlan_filter_disable(struct e1000_softc *sc) 4064 { 4065 struct e1000_hw *hw = &sc->hw; 4066 u32 reg; 4067 4068 reg = E1000_READ_REG(hw, E1000_RCTL); 4069 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4070 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4071 } 4072 4073 static void 4074 em_if_vlan_filter_write(struct e1000_softc *sc) 4075 { 4076 struct e1000_hw *hw = &sc->hw; 4077 4078 if (sc->vf_ifp) 4079 return; 4080 4081 /* Disable interrupts for lem(4) devices during the filter change */ 4082 if (hw->mac.type < em_mac_min) 4083 em_if_intr_disable(sc->ctx); 4084 4085 for (int i = 0; i < EM_VFTA_SIZE; i++) 4086 if (sc->shadow_vfta[i] != 0) { 4087 /* XXXKB: incomplete VF support, we returned above */ 4088 if (sc->vf_ifp) 4089 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], 4090 true); 4091 else 4092 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4093 } 4094 4095 /* Re-enable interrupts for lem-class devices */ 4096 if (hw->mac.type < em_mac_min) 4097 em_if_intr_enable(sc->ctx); 4098 } 4099 4100 static void 4101 em_setup_vlan_hw_support(if_ctx_t ctx) 4102 { 4103 struct e1000_softc *sc = iflib_get_softc(ctx); 4104 struct e1000_hw *hw = &sc->hw; 4105 if_t ifp = iflib_get_ifp(ctx); 4106 u32 reg; 4107 4108 /* XXXKB: Return early if we are a VF until VF decap and filter 4109 * management is ready and tested. 4110 */ 4111 if (sc->vf_ifp) 4112 return; 4113 4114 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4115 !em_disable_crc_stripping) { 4116 reg = E1000_READ_REG(hw, E1000_CTRL); 4117 reg |= E1000_CTRL_VME; 4118 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4119 } else { 4120 reg = E1000_READ_REG(hw, E1000_CTRL); 4121 reg &= ~E1000_CTRL_VME; 4122 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4123 } 4124 4125 /* If we aren't doing HW filtering, we're done */ 4126 if (!em_if_vlan_filter_capable(ctx)) { 4127 em_if_vlan_filter_disable(sc); 4128 return; 4129 } 4130 4131 /* 4132 * A soft reset zero's out the VFTA, so 4133 * we need to repopulate it now. 4134 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4135 * traffic through. This will write the entire table. 4136 */ 4137 em_if_vlan_register(ctx, 0); 4138 4139 /* Enable the Filter Table */ 4140 em_if_vlan_filter_enable(sc); 4141 } 4142 4143 static void 4144 em_if_intr_enable(if_ctx_t ctx) 4145 { 4146 struct e1000_softc *sc = iflib_get_softc(ctx); 4147 struct e1000_hw *hw = &sc->hw; 4148 u32 ims_mask = IMS_ENABLE_MASK; 4149 4150 if (sc->intr_type == IFLIB_INTR_MSIX) { 4151 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4152 ims_mask |= sc->ims; 4153 } 4154 4155 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4156 E1000_WRITE_FLUSH(hw); 4157 } 4158 4159 static void 4160 em_if_intr_disable(if_ctx_t ctx) 4161 { 4162 struct e1000_softc *sc = iflib_get_softc(ctx); 4163 struct e1000_hw *hw = &sc->hw; 4164 4165 if (sc->intr_type == IFLIB_INTR_MSIX) 4166 E1000_WRITE_REG(hw, EM_EIAC, 0); 4167 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4168 E1000_WRITE_FLUSH(hw); 4169 } 4170 4171 static void 4172 igb_if_intr_enable(if_ctx_t ctx) 4173 { 4174 struct e1000_softc *sc = iflib_get_softc(ctx); 4175 struct e1000_hw *hw = &sc->hw; 4176 u32 mask; 4177 4178 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4179 mask = (sc->que_mask | sc->link_mask); 4180 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4181 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4182 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4183 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4184 } else 4185 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4186 E1000_WRITE_FLUSH(hw); 4187 } 4188 4189 static void 4190 igb_if_intr_disable(if_ctx_t ctx) 4191 { 4192 struct e1000_softc *sc = iflib_get_softc(ctx); 4193 struct e1000_hw *hw = &sc->hw; 4194 4195 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4196 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4197 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4198 } 4199 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4200 E1000_WRITE_FLUSH(hw); 4201 } 4202 4203 /* 4204 * Bit of a misnomer, what this really means is 4205 * to enable OS management of the system... aka 4206 * to disable special hardware management features 4207 */ 4208 static void 4209 em_init_manageability(struct e1000_softc *sc) 4210 { 4211 /* A shared code workaround */ 4212 #define E1000_82542_MANC2H E1000_MANC2H 4213 if (sc->has_manage) { 4214 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4215 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4216 4217 /* disable hardware interception of ARP */ 4218 manc &= ~(E1000_MANC_ARP_EN); 4219 4220 /* enable receiving management packets to the host */ 4221 manc |= E1000_MANC_EN_MNG2HOST; 4222 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4223 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4224 manc2h |= E1000_MNG2HOST_PORT_623; 4225 manc2h |= E1000_MNG2HOST_PORT_664; 4226 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4227 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4228 } 4229 } 4230 4231 /* 4232 * Give control back to hardware management 4233 * controller if there is one. 4234 */ 4235 static void 4236 em_release_manageability(struct e1000_softc *sc) 4237 { 4238 if (sc->has_manage) { 4239 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4240 4241 /* re-enable hardware interception of ARP */ 4242 manc |= E1000_MANC_ARP_EN; 4243 manc &= ~E1000_MANC_EN_MNG2HOST; 4244 4245 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4246 } 4247 } 4248 4249 /* 4250 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4251 * For ASF and Pass Through versions of f/w this means 4252 * that the driver is loaded. For AMT version type f/w 4253 * this means that the network i/f is open. 4254 */ 4255 static void 4256 em_get_hw_control(struct e1000_softc *sc) 4257 { 4258 u32 ctrl_ext, swsm; 4259 4260 if (sc->vf_ifp) 4261 return; 4262 4263 if (sc->hw.mac.type == e1000_82573) { 4264 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4265 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4266 swsm | E1000_SWSM_DRV_LOAD); 4267 return; 4268 } 4269 /* else */ 4270 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4271 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4272 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4273 } 4274 4275 /* 4276 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4277 * For ASF and Pass Through versions of f/w this means that 4278 * the driver is no longer loaded. For AMT versions of the 4279 * f/w this means that the network i/f is closed. 4280 */ 4281 static void 4282 em_release_hw_control(struct e1000_softc *sc) 4283 { 4284 u32 ctrl_ext, swsm; 4285 4286 if (!sc->has_manage) 4287 return; 4288 4289 if (sc->hw.mac.type == e1000_82573) { 4290 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4291 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4292 swsm & ~E1000_SWSM_DRV_LOAD); 4293 return; 4294 } 4295 /* else */ 4296 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4297 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4298 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4299 return; 4300 } 4301 4302 static int 4303 em_is_valid_ether_addr(u8 *addr) 4304 { 4305 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4306 4307 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4308 return (false); 4309 } 4310 4311 return (true); 4312 } 4313 4314 static bool 4315 em_automask_tso(if_ctx_t ctx) 4316 { 4317 struct e1000_softc *sc = iflib_get_softc(ctx); 4318 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4319 if_t ifp = iflib_get_ifp(ctx); 4320 4321 if (!em_unsupported_tso && sc->link_speed && 4322 sc->link_speed != SPEED_1000 && 4323 scctx->isc_capenable & IFCAP_TSO) { 4324 device_printf(sc->dev, 4325 "Disabling TSO for 10/100 Ethernet.\n"); 4326 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4327 scctx->isc_capenable &= ~IFCAP_TSO; 4328 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4329 /* iflib_init_locked handles ifnet hwassistbits */ 4330 iflib_request_reset(ctx); 4331 return true; 4332 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4333 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4334 scctx->isc_capenable |= sc->tso_automasked; 4335 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4336 sc->tso_automasked = 0; 4337 /* iflib_init_locked handles ifnet hwassistbits */ 4338 iflib_request_reset(ctx); 4339 return true; 4340 } 4341 4342 return false; 4343 } 4344 4345 /* 4346 ** Parse the interface capabilities with regard 4347 ** to both system management and wake-on-lan for 4348 ** later use. 4349 */ 4350 static void 4351 em_get_wakeup(if_ctx_t ctx) 4352 { 4353 struct e1000_softc *sc = iflib_get_softc(ctx); 4354 device_t dev = iflib_get_dev(ctx); 4355 u16 eeprom_data = 0, device_id, apme_mask; 4356 4357 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4358 apme_mask = EM_EEPROM_APME; 4359 4360 switch (sc->hw.mac.type) { 4361 case e1000_82542: 4362 case e1000_82543: 4363 break; 4364 case e1000_82544: 4365 e1000_read_nvm(&sc->hw, 4366 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4367 apme_mask = EM_82544_APME; 4368 break; 4369 case e1000_82546: 4370 case e1000_82546_rev_3: 4371 if (sc->hw.bus.func == 1) { 4372 e1000_read_nvm(&sc->hw, 4373 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4374 break; 4375 } else 4376 e1000_read_nvm(&sc->hw, 4377 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4378 break; 4379 case e1000_82573: 4380 case e1000_82583: 4381 sc->has_amt = true; 4382 /* FALLTHROUGH */ 4383 case e1000_82571: 4384 case e1000_82572: 4385 case e1000_80003es2lan: 4386 if (sc->hw.bus.func == 1) { 4387 e1000_read_nvm(&sc->hw, 4388 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4389 break; 4390 } else 4391 e1000_read_nvm(&sc->hw, 4392 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4393 break; 4394 case e1000_ich8lan: 4395 case e1000_ich9lan: 4396 case e1000_ich10lan: 4397 case e1000_pchlan: 4398 case e1000_pch2lan: 4399 case e1000_pch_lpt: 4400 case e1000_pch_spt: 4401 case e1000_82575: /* listing all igb devices */ 4402 case e1000_82576: 4403 case e1000_82580: 4404 case e1000_i350: 4405 case e1000_i354: 4406 case e1000_i210: 4407 case e1000_i211: 4408 case e1000_vfadapt: 4409 case e1000_vfadapt_i350: 4410 apme_mask = E1000_WUC_APME; 4411 sc->has_amt = true; 4412 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4413 break; 4414 default: 4415 e1000_read_nvm(&sc->hw, 4416 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4417 break; 4418 } 4419 if (eeprom_data & apme_mask) 4420 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4421 /* 4422 * We have the eeprom settings, now apply the special cases 4423 * where the eeprom may be wrong or the board won't support 4424 * wake on lan on a particular port 4425 */ 4426 device_id = pci_get_device(dev); 4427 switch (device_id) { 4428 case E1000_DEV_ID_82546GB_PCIE: 4429 sc->wol = 0; 4430 break; 4431 case E1000_DEV_ID_82546EB_FIBER: 4432 case E1000_DEV_ID_82546GB_FIBER: 4433 /* Wake events only supported on port A for dual fiber 4434 * regardless of eeprom setting */ 4435 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4436 E1000_STATUS_FUNC_1) 4437 sc->wol = 0; 4438 break; 4439 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4440 /* if quad port adapter, disable WoL on all but port A */ 4441 if (global_quad_port_a != 0) 4442 sc->wol = 0; 4443 /* Reset for multiple quad port adapters */ 4444 if (++global_quad_port_a == 4) 4445 global_quad_port_a = 0; 4446 break; 4447 case E1000_DEV_ID_82571EB_FIBER: 4448 /* Wake events only supported on port A for dual fiber 4449 * regardless of eeprom setting */ 4450 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4451 E1000_STATUS_FUNC_1) 4452 sc->wol = 0; 4453 break; 4454 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4455 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4456 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4457 /* if quad port adapter, disable WoL on all but port A */ 4458 if (global_quad_port_a != 0) 4459 sc->wol = 0; 4460 /* Reset for multiple quad port adapters */ 4461 if (++global_quad_port_a == 4) 4462 global_quad_port_a = 0; 4463 break; 4464 } 4465 return; 4466 } 4467 4468 4469 /* 4470 * Enable PCI Wake On Lan capability 4471 */ 4472 static void 4473 em_enable_wakeup(if_ctx_t ctx) 4474 { 4475 struct e1000_softc *sc = iflib_get_softc(ctx); 4476 device_t dev = iflib_get_dev(ctx); 4477 if_t ifp = iflib_get_ifp(ctx); 4478 int error = 0; 4479 u32 ctrl, ctrl_ext, rctl; 4480 4481 if (!pci_has_pm(dev)) 4482 return; 4483 4484 /* 4485 * Determine type of Wakeup: note that wol 4486 * is set with all bits on by default. 4487 */ 4488 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4489 sc->wol &= ~E1000_WUFC_MAG; 4490 4491 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4492 sc->wol &= ~E1000_WUFC_EX; 4493 4494 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4495 sc->wol &= ~E1000_WUFC_MC; 4496 else { 4497 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4498 rctl |= E1000_RCTL_MPE; 4499 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4500 } 4501 4502 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4503 goto pme; 4504 4505 /* Advertise the wakeup capability */ 4506 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4507 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4508 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4509 4510 /* Keep the laser running on Fiber adapters */ 4511 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4512 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4513 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4514 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4515 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4516 } 4517 4518 if ((sc->hw.mac.type == e1000_ich8lan) || 4519 (sc->hw.mac.type == e1000_pchlan) || 4520 (sc->hw.mac.type == e1000_ich9lan) || 4521 (sc->hw.mac.type == e1000_ich10lan)) 4522 e1000_suspend_workarounds_ich8lan(&sc->hw); 4523 4524 if ( sc->hw.mac.type >= e1000_pchlan) { 4525 error = em_enable_phy_wakeup(sc); 4526 if (error) 4527 goto pme; 4528 } else { 4529 /* Enable wakeup by the MAC */ 4530 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4531 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4532 } 4533 4534 if (sc->hw.phy.type == e1000_phy_igp_3) 4535 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4536 4537 pme: 4538 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4539 pci_enable_pme(dev); 4540 4541 return; 4542 } 4543 4544 /* 4545 * WOL in the newer chipset interfaces (pchlan) 4546 * require thing to be copied into the phy 4547 */ 4548 static int 4549 em_enable_phy_wakeup(struct e1000_softc *sc) 4550 { 4551 struct e1000_hw *hw = &sc->hw; 4552 u32 mreg, ret = 0; 4553 u16 preg; 4554 4555 /* copy MAC RARs to PHY RARs */ 4556 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4557 4558 /* copy MAC MTA to PHY MTA */ 4559 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4560 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4561 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4562 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4563 (u16)((mreg >> 16) & 0xFFFF)); 4564 } 4565 4566 /* configure PHY Rx Control register */ 4567 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4568 mreg = E1000_READ_REG(hw, E1000_RCTL); 4569 if (mreg & E1000_RCTL_UPE) 4570 preg |= BM_RCTL_UPE; 4571 if (mreg & E1000_RCTL_MPE) 4572 preg |= BM_RCTL_MPE; 4573 preg &= ~(BM_RCTL_MO_MASK); 4574 if (mreg & E1000_RCTL_MO_3) 4575 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4576 << BM_RCTL_MO_SHIFT); 4577 if (mreg & E1000_RCTL_BAM) 4578 preg |= BM_RCTL_BAM; 4579 if (mreg & E1000_RCTL_PMCF) 4580 preg |= BM_RCTL_PMCF; 4581 mreg = E1000_READ_REG(hw, E1000_CTRL); 4582 if (mreg & E1000_CTRL_RFCE) 4583 preg |= BM_RCTL_RFCE; 4584 e1000_write_phy_reg(hw, BM_RCTL, preg); 4585 4586 /* enable PHY wakeup in MAC register */ 4587 E1000_WRITE_REG(hw, E1000_WUC, 4588 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4589 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4590 4591 /* configure and enable PHY wakeup in PHY registers */ 4592 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4593 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4594 4595 /* activate PHY wakeup */ 4596 ret = hw->phy.ops.acquire(hw); 4597 if (ret) { 4598 printf("Could not acquire PHY\n"); 4599 return ret; 4600 } 4601 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4602 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4603 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4604 if (ret) { 4605 printf("Could not read PHY page 769\n"); 4606 goto out; 4607 } 4608 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4609 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4610 if (ret) 4611 printf("Could not set PHY Host Wakeup bit\n"); 4612 out: 4613 hw->phy.ops.release(hw); 4614 4615 return ret; 4616 } 4617 4618 static void 4619 em_if_led_func(if_ctx_t ctx, int onoff) 4620 { 4621 struct e1000_softc *sc = iflib_get_softc(ctx); 4622 4623 if (onoff) { 4624 e1000_setup_led(&sc->hw); 4625 e1000_led_on(&sc->hw); 4626 } else { 4627 e1000_led_off(&sc->hw); 4628 e1000_cleanup_led(&sc->hw); 4629 } 4630 } 4631 4632 /* 4633 * Disable the L0S and L1 LINK states 4634 */ 4635 static void 4636 em_disable_aspm(struct e1000_softc *sc) 4637 { 4638 int base, reg; 4639 u16 link_cap,link_ctrl; 4640 device_t dev = sc->dev; 4641 4642 switch (sc->hw.mac.type) { 4643 case e1000_82573: 4644 case e1000_82574: 4645 case e1000_82583: 4646 break; 4647 default: 4648 return; 4649 } 4650 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4651 return; 4652 reg = base + PCIER_LINK_CAP; 4653 link_cap = pci_read_config(dev, reg, 2); 4654 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4655 return; 4656 reg = base + PCIER_LINK_CTL; 4657 link_ctrl = pci_read_config(dev, reg, 2); 4658 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4659 pci_write_config(dev, reg, link_ctrl, 2); 4660 return; 4661 } 4662 4663 /********************************************************************** 4664 * 4665 * Update the board statistics counters. 4666 * 4667 **********************************************************************/ 4668 static void 4669 em_update_stats_counters(struct e1000_softc *sc) 4670 { 4671 u64 prev_xoffrxc = sc->stats.xoffrxc; 4672 4673 if(sc->hw.phy.media_type == e1000_media_type_copper || 4674 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4675 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4676 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4677 } 4678 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4679 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4680 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4681 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4682 4683 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4684 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4685 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4686 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4687 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4688 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4689 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4690 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4691 /* 4692 ** For watchdog management we need to know if we have been 4693 ** paused during the last interval, so capture that here. 4694 */ 4695 if (sc->stats.xoffrxc != prev_xoffrxc) 4696 sc->shared->isc_pause_frames = 1; 4697 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4698 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4699 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4700 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4701 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4702 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4703 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4704 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4705 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4706 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4707 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4708 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4709 4710 /* For the 64-bit byte counters the low dword must be read first. */ 4711 /* Both registers clear on the read of the high dword */ 4712 4713 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4714 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4715 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4716 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4717 4718 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4719 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4720 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4721 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4722 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4723 4724 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4725 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4726 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4727 4728 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4729 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4730 4731 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4732 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4733 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4734 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4735 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4736 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4737 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4738 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4739 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4740 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4741 4742 /* Interrupt Counts */ 4743 4744 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4745 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4746 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4747 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4748 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4749 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4750 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4751 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4752 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4753 4754 if (sc->hw.mac.type >= e1000_82543) { 4755 sc->stats.algnerrc += 4756 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4757 sc->stats.rxerrc += 4758 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4759 sc->stats.tncrs += 4760 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4761 sc->stats.cexterr += 4762 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4763 sc->stats.tsctc += 4764 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4765 sc->stats.tsctfc += 4766 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4767 } 4768 } 4769 4770 static uint64_t 4771 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4772 { 4773 struct e1000_softc *sc = iflib_get_softc(ctx); 4774 if_t ifp = iflib_get_ifp(ctx); 4775 4776 switch (cnt) { 4777 case IFCOUNTER_COLLISIONS: 4778 return (sc->stats.colc); 4779 case IFCOUNTER_IERRORS: 4780 return (sc->dropped_pkts + sc->stats.rxerrc + 4781 sc->stats.crcerrs + sc->stats.algnerrc + 4782 sc->stats.ruc + sc->stats.roc + 4783 sc->stats.mpc + sc->stats.cexterr); 4784 case IFCOUNTER_OERRORS: 4785 return (sc->stats.ecol + sc->stats.latecol + 4786 sc->watchdog_events); 4787 default: 4788 return (if_get_counter_default(ifp, cnt)); 4789 } 4790 } 4791 4792 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4793 * @ctx: iflib context 4794 * @event: event code to check 4795 * 4796 * Defaults to returning false for unknown events. 4797 * 4798 * @returns true if iflib needs to reinit the interface 4799 */ 4800 static bool 4801 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4802 { 4803 switch (event) { 4804 case IFLIB_RESTART_VLAN_CONFIG: 4805 default: 4806 return (false); 4807 } 4808 } 4809 4810 /* Export a single 32-bit register via a read-only sysctl. */ 4811 static int 4812 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4813 { 4814 struct e1000_softc *sc; 4815 u_int val; 4816 4817 sc = oidp->oid_arg1; 4818 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4819 return (sysctl_handle_int(oidp, &val, 0, req)); 4820 } 4821 4822 /* Per queue holdoff interrupt rate handler */ 4823 static int 4824 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4825 { 4826 struct em_rx_queue *rque; 4827 struct em_tx_queue *tque; 4828 struct e1000_hw *hw; 4829 int error; 4830 u32 reg, usec, rate; 4831 4832 bool tx = oidp->oid_arg2; 4833 4834 if (tx) { 4835 tque = oidp->oid_arg1; 4836 hw = &tque->sc->hw; 4837 if (hw->mac.type >= igb_mac_min) 4838 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4839 else if (hw->mac.type == e1000_82574 && tque->msix) 4840 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4841 else 4842 reg = E1000_READ_REG(hw, E1000_ITR); 4843 } else { 4844 rque = oidp->oid_arg1; 4845 hw = &rque->sc->hw; 4846 if (hw->mac.type >= igb_mac_min) 4847 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4848 else if (hw->mac.type == e1000_82574 && rque->msix) 4849 reg = E1000_READ_REG(hw, 4850 E1000_EITR_82574(rque->msix)); 4851 else 4852 reg = E1000_READ_REG(hw, E1000_ITR); 4853 } 4854 4855 if (hw->mac.type < igb_mac_min) { 4856 if (reg > 0) 4857 rate = EM_INTS_TO_ITR(reg); 4858 else 4859 rate = 0; 4860 } else { 4861 usec = (reg & IGB_QVECTOR_MASK); 4862 if (usec > 0) 4863 rate = IGB_INTS_TO_EITR(usec); 4864 else 4865 rate = 0; 4866 } 4867 4868 error = sysctl_handle_int(oidp, &rate, 0, req); 4869 if (error || !req->newptr) 4870 return error; 4871 return 0; 4872 } 4873 4874 /* 4875 * Add sysctl variables, one per statistic, to the system. 4876 */ 4877 static void 4878 em_add_hw_stats(struct e1000_softc *sc) 4879 { 4880 device_t dev = iflib_get_dev(sc->ctx); 4881 struct em_tx_queue *tx_que = sc->tx_queues; 4882 struct em_rx_queue *rx_que = sc->rx_queues; 4883 4884 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4885 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4886 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4887 struct e1000_hw_stats *stats = &sc->stats; 4888 4889 struct sysctl_oid *stat_node, *queue_node, *int_node; 4890 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4891 4892 #define QUEUE_NAME_LEN 32 4893 char namebuf[QUEUE_NAME_LEN]; 4894 4895 /* Driver Statistics */ 4896 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4897 CTLFLAG_RD, &sc->dropped_pkts, 4898 "Driver dropped packets"); 4899 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4900 CTLFLAG_RD, &sc->link_irq, 4901 "Link MSI-X IRQ Handled"); 4902 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4903 CTLFLAG_RD, &sc->rx_overruns, 4904 "RX overruns"); 4905 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4906 CTLFLAG_RD, &sc->watchdog_events, 4907 "Watchdog timeouts"); 4908 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4909 CTLTYPE_UINT | CTLFLAG_RD, 4910 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4911 "Device Control Register"); 4912 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4913 CTLTYPE_UINT | CTLFLAG_RD, 4914 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4915 "Receiver Control Register"); 4916 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4917 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4918 "Flow Control High Watermark"); 4919 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4920 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4921 "Flow Control Low Watermark"); 4922 4923 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4924 struct tx_ring *txr = &tx_que->txr; 4925 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4926 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4927 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4928 queue_list = SYSCTL_CHILDREN(queue_node); 4929 4930 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4931 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4932 true, em_sysctl_interrupt_rate_handler, 4933 "IU", "Interrupt Rate"); 4934 4935 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4936 CTLTYPE_UINT | CTLFLAG_RD, sc, 4937 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4938 "Transmit Descriptor Head"); 4939 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4940 CTLTYPE_UINT | CTLFLAG_RD, sc, 4941 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4942 "Transmit Descriptor Tail"); 4943 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4944 CTLFLAG_RD, &txr->tx_irq, 4945 "Queue MSI-X Transmit Interrupts"); 4946 } 4947 4948 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4949 struct rx_ring *rxr = &rx_que->rxr; 4950 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4951 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4952 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4953 queue_list = SYSCTL_CHILDREN(queue_node); 4954 4955 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4956 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 4957 false, em_sysctl_interrupt_rate_handler, 4958 "IU", "Interrupt Rate"); 4959 4960 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4961 CTLTYPE_UINT | CTLFLAG_RD, sc, 4962 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4963 "Receive Descriptor Head"); 4964 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4965 CTLTYPE_UINT | CTLFLAG_RD, sc, 4966 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4967 "Receive Descriptor Tail"); 4968 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4969 CTLFLAG_RD, &rxr->rx_irq, 4970 "Queue MSI-X Receive Interrupts"); 4971 } 4972 4973 /* MAC stats get their own sub node */ 4974 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4975 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4976 stat_list = SYSCTL_CHILDREN(stat_node); 4977 4978 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4979 CTLFLAG_RD, &stats->ecol, 4980 "Excessive collisions"); 4981 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4982 CTLFLAG_RD, &stats->scc, 4983 "Single collisions"); 4984 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4985 CTLFLAG_RD, &stats->mcc, 4986 "Multiple collisions"); 4987 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4988 CTLFLAG_RD, &stats->latecol, 4989 "Late collisions"); 4990 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4991 CTLFLAG_RD, &stats->colc, 4992 "Collision Count"); 4993 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4994 CTLFLAG_RD, &sc->stats.symerrs, 4995 "Symbol Errors"); 4996 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4997 CTLFLAG_RD, &sc->stats.sec, 4998 "Sequence Errors"); 4999 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5000 CTLFLAG_RD, &sc->stats.dc, 5001 "Defer Count"); 5002 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5003 CTLFLAG_RD, &sc->stats.mpc, 5004 "Missed Packets"); 5005 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5006 CTLFLAG_RD, &sc->stats.rlec, 5007 "Receive Length Errors"); 5008 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5009 CTLFLAG_RD, &sc->stats.rnbc, 5010 "Receive No Buffers"); 5011 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5012 CTLFLAG_RD, &sc->stats.ruc, 5013 "Receive Undersize"); 5014 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5015 CTLFLAG_RD, &sc->stats.rfc, 5016 "Fragmented Packets Received "); 5017 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5018 CTLFLAG_RD, &sc->stats.roc, 5019 "Oversized Packets Received"); 5020 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5021 CTLFLAG_RD, &sc->stats.rjc, 5022 "Recevied Jabber"); 5023 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5024 CTLFLAG_RD, &sc->stats.rxerrc, 5025 "Receive Errors"); 5026 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5027 CTLFLAG_RD, &sc->stats.crcerrs, 5028 "CRC errors"); 5029 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5030 CTLFLAG_RD, &sc->stats.algnerrc, 5031 "Alignment Errors"); 5032 /* On 82575 these are collision counts */ 5033 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5034 CTLFLAG_RD, &sc->stats.cexterr, 5035 "Collision/Carrier extension errors"); 5036 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5037 CTLFLAG_RD, &sc->stats.xonrxc, 5038 "XON Received"); 5039 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5040 CTLFLAG_RD, &sc->stats.xontxc, 5041 "XON Transmitted"); 5042 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5043 CTLFLAG_RD, &sc->stats.xoffrxc, 5044 "XOFF Received"); 5045 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5046 CTLFLAG_RD, &sc->stats.xofftxc, 5047 "XOFF Transmitted"); 5048 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5049 CTLFLAG_RD, &sc->stats.fcruc, 5050 "Unsupported Flow Control Received"); 5051 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5052 CTLFLAG_RD, &sc->stats.mgprc, 5053 "Management Packets Received"); 5054 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5055 CTLFLAG_RD, &sc->stats.mgpdc, 5056 "Management Packets Dropped"); 5057 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5058 CTLFLAG_RD, &sc->stats.mgptc, 5059 "Management Packets Transmitted"); 5060 5061 /* Packet Reception Stats */ 5062 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5063 CTLFLAG_RD, &sc->stats.tpr, 5064 "Total Packets Received "); 5065 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5066 CTLFLAG_RD, &sc->stats.gprc, 5067 "Good Packets Received"); 5068 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5069 CTLFLAG_RD, &sc->stats.bprc, 5070 "Broadcast Packets Received"); 5071 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5072 CTLFLAG_RD, &sc->stats.mprc, 5073 "Multicast Packets Received"); 5074 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5075 CTLFLAG_RD, &sc->stats.prc64, 5076 "64 byte frames received "); 5077 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5078 CTLFLAG_RD, &sc->stats.prc127, 5079 "65-127 byte frames received"); 5080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5081 CTLFLAG_RD, &sc->stats.prc255, 5082 "128-255 byte frames received"); 5083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5084 CTLFLAG_RD, &sc->stats.prc511, 5085 "256-511 byte frames received"); 5086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5087 CTLFLAG_RD, &sc->stats.prc1023, 5088 "512-1023 byte frames received"); 5089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5090 CTLFLAG_RD, &sc->stats.prc1522, 5091 "1023-1522 byte frames received"); 5092 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5093 CTLFLAG_RD, &sc->stats.gorc, 5094 "Good Octets Received"); 5095 5096 /* Packet Transmission Stats */ 5097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5098 CTLFLAG_RD, &sc->stats.gotc, 5099 "Good Octets Transmitted"); 5100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5101 CTLFLAG_RD, &sc->stats.tpt, 5102 "Total Packets Transmitted"); 5103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5104 CTLFLAG_RD, &sc->stats.gptc, 5105 "Good Packets Transmitted"); 5106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5107 CTLFLAG_RD, &sc->stats.bptc, 5108 "Broadcast Packets Transmitted"); 5109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5110 CTLFLAG_RD, &sc->stats.mptc, 5111 "Multicast Packets Transmitted"); 5112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5113 CTLFLAG_RD, &sc->stats.ptc64, 5114 "64 byte frames transmitted "); 5115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5116 CTLFLAG_RD, &sc->stats.ptc127, 5117 "65-127 byte frames transmitted"); 5118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5119 CTLFLAG_RD, &sc->stats.ptc255, 5120 "128-255 byte frames transmitted"); 5121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5122 CTLFLAG_RD, &sc->stats.ptc511, 5123 "256-511 byte frames transmitted"); 5124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5125 CTLFLAG_RD, &sc->stats.ptc1023, 5126 "512-1023 byte frames transmitted"); 5127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5128 CTLFLAG_RD, &sc->stats.ptc1522, 5129 "1024-1522 byte frames transmitted"); 5130 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5131 CTLFLAG_RD, &sc->stats.tsctc, 5132 "TSO Contexts Transmitted"); 5133 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5134 CTLFLAG_RD, &sc->stats.tsctfc, 5135 "TSO Contexts Failed"); 5136 5137 /* Interrupt Stats */ 5138 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5139 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5140 int_list = SYSCTL_CHILDREN(int_node); 5141 5142 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5143 CTLFLAG_RD, &sc->stats.iac, 5144 "Interrupt Assertion Count"); 5145 5146 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5147 CTLFLAG_RD, &sc->stats.icrxptc, 5148 "Interrupt Cause Rx Pkt Timer Expire Count"); 5149 5150 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5151 CTLFLAG_RD, &sc->stats.icrxatc, 5152 "Interrupt Cause Rx Abs Timer Expire Count"); 5153 5154 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5155 CTLFLAG_RD, &sc->stats.ictxptc, 5156 "Interrupt Cause Tx Pkt Timer Expire Count"); 5157 5158 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5159 CTLFLAG_RD, &sc->stats.ictxatc, 5160 "Interrupt Cause Tx Abs Timer Expire Count"); 5161 5162 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5163 CTLFLAG_RD, &sc->stats.ictxqec, 5164 "Interrupt Cause Tx Queue Empty Count"); 5165 5166 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5167 CTLFLAG_RD, &sc->stats.ictxqmtc, 5168 "Interrupt Cause Tx Queue Min Thresh Count"); 5169 5170 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5171 CTLFLAG_RD, &sc->stats.icrxdmtc, 5172 "Interrupt Cause Rx Desc Min Thresh Count"); 5173 5174 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5175 CTLFLAG_RD, &sc->stats.icrxoc, 5176 "Interrupt Cause Receiver Overrun Count"); 5177 } 5178 5179 static void 5180 em_fw_version_locked(if_ctx_t ctx) 5181 { 5182 struct e1000_softc *sc = iflib_get_softc(ctx); 5183 struct e1000_hw *hw = &sc->hw; 5184 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5185 uint16_t eep = 0; 5186 5187 /* 5188 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5189 * the NVM locking model, so we do it in em_if_attach_pre() and store 5190 * the info in the softc 5191 */ 5192 ASSERT_CTX_LOCK_HELD(hw); 5193 5194 *fw_ver = (struct e1000_fw_version){0}; 5195 5196 if (hw->mac.type >= igb_mac_min) { 5197 /* 5198 * Use the Shared Code for igb(4) 5199 */ 5200 e1000_get_fw_version(hw, fw_ver); 5201 } else { 5202 /* 5203 * Otherwise, EEPROM version should be present on (almost?) 5204 * all devices here 5205 */ 5206 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5207 INIT_DEBUGOUT("can't get EEPROM version"); 5208 return; 5209 } 5210 5211 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5212 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5213 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5214 } 5215 } 5216 5217 static void 5218 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5219 { 5220 const char *space = ""; 5221 5222 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5223 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5224 fw_ver->eep_minor, fw_ver->eep_build); 5225 space = " "; 5226 } 5227 5228 if (fw_ver->invm_major || fw_ver->invm_minor || 5229 fw_ver->invm_img_type) { 5230 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5231 space, fw_ver->invm_major, fw_ver->invm_minor, 5232 fw_ver->invm_img_type); 5233 space = " "; 5234 } 5235 5236 if (fw_ver->or_valid) { 5237 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5238 space, fw_ver->or_major, fw_ver->or_build, 5239 fw_ver->or_patch); 5240 space = " "; 5241 } 5242 5243 if (fw_ver->etrack_id) 5244 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5245 } 5246 5247 static void 5248 em_print_fw_version(struct e1000_softc *sc ) 5249 { 5250 device_t dev = sc->dev; 5251 struct sbuf *buf; 5252 int error = 0; 5253 5254 buf = sbuf_new_auto(); 5255 if (!buf) { 5256 device_printf(dev, "Could not allocate sbuf for output.\n"); 5257 return; 5258 } 5259 5260 em_sbuf_fw_version(&sc->fw_ver, buf); 5261 5262 error = sbuf_finish(buf); 5263 if (error) 5264 device_printf(dev, "Error finishing sbuf: %d\n", error); 5265 else if (sbuf_len(buf)) 5266 device_printf(dev, "%s\n", sbuf_data(buf)); 5267 5268 sbuf_delete(buf); 5269 } 5270 5271 static int 5272 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5273 { 5274 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5275 device_t dev = sc->dev; 5276 struct sbuf *buf; 5277 int error = 0; 5278 5279 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5280 if (!buf) { 5281 device_printf(dev, "Could not allocate sbuf for output.\n"); 5282 return (ENOMEM); 5283 } 5284 5285 em_sbuf_fw_version(&sc->fw_ver, buf); 5286 5287 error = sbuf_finish(buf); 5288 if (error) 5289 device_printf(dev, "Error finishing sbuf: %d\n", error); 5290 5291 sbuf_delete(buf); 5292 5293 return (0); 5294 } 5295 5296 /********************************************************************** 5297 * 5298 * This routine provides a way to dump out the adapter eeprom, 5299 * often a useful debug/service tool. This only dumps the first 5300 * 32 words, stuff that matters is in that extent. 5301 * 5302 **********************************************************************/ 5303 static int 5304 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5305 { 5306 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5307 int error; 5308 int result; 5309 5310 result = -1; 5311 error = sysctl_handle_int(oidp, &result, 0, req); 5312 5313 if (error || !req->newptr) 5314 return (error); 5315 5316 /* 5317 * This value will cause a hex dump of the 5318 * first 32 16-bit words of the EEPROM to 5319 * the screen. 5320 */ 5321 if (result == 1) 5322 em_print_nvm_info(sc); 5323 5324 return (error); 5325 } 5326 5327 static void 5328 em_print_nvm_info(struct e1000_softc *sc) 5329 { 5330 struct e1000_hw *hw = &sc->hw; 5331 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5332 u16 eeprom_data; 5333 int i, j, row = 0; 5334 5335 /* Its a bit crude, but it gets the job done */ 5336 printf("\nInterface EEPROM Dump:\n"); 5337 printf("Offset\n0x0000 "); 5338 5339 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5340 sx_xlock(iflib_ctx_lock); 5341 ASSERT_CTX_LOCK_HELD(hw); 5342 for (i = 0, j = 0; i < 32; i++, j++) { 5343 if (j == 8) { /* Make the offset block */ 5344 j = 0; ++row; 5345 printf("\n0x00%x0 ",row); 5346 } 5347 e1000_read_nvm(hw, i, 1, &eeprom_data); 5348 printf("%04x ", eeprom_data); 5349 } 5350 sx_xunlock(iflib_ctx_lock); 5351 printf("\n"); 5352 } 5353 5354 static int 5355 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5356 { 5357 struct em_int_delay_info *info; 5358 struct e1000_softc *sc; 5359 u32 regval; 5360 int error, usecs, ticks; 5361 5362 info = (struct em_int_delay_info *) arg1; 5363 usecs = info->value; 5364 error = sysctl_handle_int(oidp, &usecs, 0, req); 5365 if (error != 0 || req->newptr == NULL) 5366 return (error); 5367 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5368 return (EINVAL); 5369 info->value = usecs; 5370 ticks = EM_USECS_TO_TICKS(usecs); 5371 5372 sc = info->sc; 5373 5374 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5375 regval = (regval & ~0xffff) | (ticks & 0xffff); 5376 /* Handle a few special cases. */ 5377 switch (info->offset) { 5378 case E1000_RDTR: 5379 break; 5380 case E1000_TIDV: 5381 if (ticks == 0) { 5382 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5383 /* Don't write 0 into the TIDV register. */ 5384 regval++; 5385 } else 5386 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5387 break; 5388 } 5389 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5390 return (0); 5391 } 5392 5393 static int 5394 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5395 { 5396 struct e1000_softc *sc; 5397 u32 reg, val, shift; 5398 int error, mask; 5399 5400 sc = oidp->oid_arg1; 5401 switch (oidp->oid_arg2) { 5402 case 0: 5403 reg = E1000_DTXTCPFLGL; 5404 shift = 0; 5405 break; 5406 case 1: 5407 reg = E1000_DTXTCPFLGL; 5408 shift = 16; 5409 break; 5410 case 2: 5411 reg = E1000_DTXTCPFLGH; 5412 shift = 0; 5413 break; 5414 default: 5415 return (EINVAL); 5416 break; 5417 } 5418 val = E1000_READ_REG(&sc->hw, reg); 5419 mask = (val >> shift) & 0xfff; 5420 error = sysctl_handle_int(oidp, &mask, 0, req); 5421 if (error != 0 || req->newptr == NULL) 5422 return (error); 5423 if (mask < 0 || mask > 0xfff) 5424 return (EINVAL); 5425 val = (val & ~(0xfff << shift)) | (mask << shift); 5426 E1000_WRITE_REG(&sc->hw, reg, val); 5427 return (0); 5428 } 5429 5430 static void 5431 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5432 const char *description, struct em_int_delay_info *info, int offset, 5433 int value) 5434 { 5435 info->sc = sc; 5436 info->offset = offset; 5437 info->value = value; 5438 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5439 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5440 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5441 info, 0, em_sysctl_int_delay, "I", description); 5442 } 5443 5444 /* 5445 * Set flow control using sysctl: 5446 * Flow control values: 5447 * 0 - off 5448 * 1 - rx pause 5449 * 2 - tx pause 5450 * 3 - full 5451 */ 5452 static int 5453 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5454 { 5455 int error; 5456 static int input = 3; /* default is full */ 5457 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5458 5459 error = sysctl_handle_int(oidp, &input, 0, req); 5460 5461 if ((error) || (req->newptr == NULL)) 5462 return (error); 5463 5464 if (input == sc->fc) /* no change? */ 5465 return (error); 5466 5467 switch (input) { 5468 case e1000_fc_rx_pause: 5469 case e1000_fc_tx_pause: 5470 case e1000_fc_full: 5471 case e1000_fc_none: 5472 sc->hw.fc.requested_mode = input; 5473 sc->fc = input; 5474 break; 5475 default: 5476 /* Do nothing */ 5477 return (error); 5478 } 5479 5480 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5481 e1000_force_mac_fc(&sc->hw); 5482 return (error); 5483 } 5484 5485 /* 5486 * Manage DMA Coalesce: 5487 * Control values: 5488 * 0/1 - off/on 5489 * Legal timer values are: 5490 * 250,500,1000-10000 in thousands 5491 */ 5492 static int 5493 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5494 { 5495 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5496 int error; 5497 5498 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5499 5500 if ((error) || (req->newptr == NULL)) 5501 return (error); 5502 5503 switch (sc->dmac) { 5504 case 0: 5505 /* Disabling */ 5506 break; 5507 case 1: /* Just enable and use default */ 5508 sc->dmac = 1000; 5509 break; 5510 case 250: 5511 case 500: 5512 case 1000: 5513 case 2000: 5514 case 3000: 5515 case 4000: 5516 case 5000: 5517 case 6000: 5518 case 7000: 5519 case 8000: 5520 case 9000: 5521 case 10000: 5522 /* Legal values - allow */ 5523 break; 5524 default: 5525 /* Do nothing, illegal value */ 5526 sc->dmac = 0; 5527 return (EINVAL); 5528 } 5529 /* Reinit the interface */ 5530 em_if_init(sc->ctx); 5531 return (error); 5532 } 5533 5534 /* 5535 * Manage Energy Efficient Ethernet: 5536 * Control values: 5537 * 0/1 - enabled/disabled 5538 */ 5539 static int 5540 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5541 { 5542 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5543 int error, value; 5544 5545 if (sc->hw.mac.type < igb_mac_min) 5546 value = sc->hw.dev_spec.ich8lan.eee_disable; 5547 else 5548 value = sc->hw.dev_spec._82575.eee_disable; 5549 error = sysctl_handle_int(oidp, &value, 0, req); 5550 if (error || req->newptr == NULL) 5551 return (error); 5552 if (sc->hw.mac.type < igb_mac_min) 5553 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5554 else 5555 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5556 em_if_init(sc->ctx); 5557 5558 return (0); 5559 } 5560 5561 static int 5562 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5563 { 5564 struct e1000_softc *sc; 5565 int error; 5566 int result; 5567 5568 result = -1; 5569 error = sysctl_handle_int(oidp, &result, 0, req); 5570 5571 if (error || !req->newptr) 5572 return (error); 5573 5574 if (result == 1) { 5575 sc = (struct e1000_softc *) arg1; 5576 em_print_debug_info(sc); 5577 } 5578 5579 return (error); 5580 } 5581 5582 static int 5583 em_get_rs(SYSCTL_HANDLER_ARGS) 5584 { 5585 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5586 int error; 5587 int result; 5588 5589 result = 0; 5590 error = sysctl_handle_int(oidp, &result, 0, req); 5591 5592 if (error || !req->newptr || result != 1) 5593 return (error); 5594 em_dump_rs(sc); 5595 5596 return (error); 5597 } 5598 5599 static void 5600 em_if_debug(if_ctx_t ctx) 5601 { 5602 em_dump_rs(iflib_get_softc(ctx)); 5603 } 5604 5605 /* 5606 * This routine is meant to be fluid, add whatever is 5607 * needed for debugging a problem. -jfv 5608 */ 5609 static void 5610 em_print_debug_info(struct e1000_softc *sc) 5611 { 5612 device_t dev = iflib_get_dev(sc->ctx); 5613 if_t ifp = iflib_get_ifp(sc->ctx); 5614 struct tx_ring *txr = &sc->tx_queues->txr; 5615 struct rx_ring *rxr = &sc->rx_queues->rxr; 5616 5617 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5618 printf("Interface is RUNNING "); 5619 else 5620 printf("Interface is NOT RUNNING\n"); 5621 5622 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5623 printf("and INACTIVE\n"); 5624 else 5625 printf("and ACTIVE\n"); 5626 5627 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5628 device_printf(dev, "TX Queue %d ------\n", i); 5629 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5630 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5631 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5632 5633 } 5634 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5635 device_printf(dev, "RX Queue %d ------\n", j); 5636 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5637 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5638 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5639 } 5640 } 5641 5642 /* 5643 * 82574 only: 5644 * Write a new value to the EEPROM increasing the number of MSI-X 5645 * vectors from 3 to 5, for proper multiqueue support. 5646 */ 5647 static void 5648 em_enable_vectors_82574(if_ctx_t ctx) 5649 { 5650 struct e1000_softc *sc = iflib_get_softc(ctx); 5651 struct e1000_hw *hw = &sc->hw; 5652 device_t dev = iflib_get_dev(ctx); 5653 u16 edata; 5654 5655 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5656 if (bootverbose) 5657 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5658 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5659 device_printf(dev, "Writing to eeprom: increasing " 5660 "reported MSI-X vectors from 3 to 5...\n"); 5661 edata &= ~(EM_NVM_MSIX_N_MASK); 5662 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5663 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5664 e1000_update_nvm_checksum(hw); 5665 device_printf(dev, "Writing to eeprom: done\n"); 5666 } 5667 } 5668