1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_VF_H_ 36 #define _E1000_VF_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82576_VF 0x10CA 45 46 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 47 48 /* Additional Descriptor Control definitions */ 49 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 50 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 51 52 /* SRRCTL bit definitions */ 53 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 54 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 55 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 56 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 57 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 58 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 59 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 60 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 61 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 62 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 63 #define E1000_SRRCTL_DROP_EN 0x80000000 64 65 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 66 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 67 68 /* Interrupt Defines */ 69 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 70 #define E1000_EITR(_n) (0x01680 + ((_n) << 2)) 71 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 72 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 73 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 74 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 75 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 76 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 77 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 78 #define E1000_IVAR_VALID 0x80 79 80 /* Receive Descriptor - Advanced */ 81 union e1000_adv_rx_desc { 82 struct { 83 u64 pkt_addr; /* Packet buffer address */ 84 u64 hdr_addr; /* Header buffer address */ 85 } read; 86 struct { 87 struct { 88 union { 89 u32 data; 90 struct { 91 u16 pkt_info; /* RSS type, Packet type */ 92 u16 hdr_info; /* Split Header, 93 * header buffer length */ 94 } hs_rss; 95 } lo_dword; 96 union { 97 u32 rss; /* RSS Hash */ 98 struct { 99 u16 ip_id; /* IP id */ 100 u16 csum; /* Packet Checksum */ 101 } csum_ip; 102 } hi_dword; 103 } lower; 104 struct { 105 u32 status_error; /* ext status/error */ 106 u16 length; /* Packet length */ 107 u16 vlan; /* VLAN tag */ 108 } upper; 109 } wb; /* writeback */ 110 }; 111 112 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 113 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 114 115 /* Transmit Descriptor - Advanced */ 116 union e1000_adv_tx_desc { 117 struct { 118 u64 buffer_addr; /* Address of descriptor's data buf */ 119 u32 cmd_type_len; 120 u32 olinfo_status; 121 } read; 122 struct { 123 u64 rsvd; /* Reserved */ 124 u32 nxtseq_seed; 125 u32 status; 126 } wb; 127 }; 128 129 /* Adv Transmit Descriptor Config Masks */ 130 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 131 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 132 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 133 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 134 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 135 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 136 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 137 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 138 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 139 140 /* Context descriptors */ 141 struct e1000_adv_tx_context_desc { 142 u32 vlan_macip_lens; 143 u32 seqnum_seed; 144 u32 type_tucmd_mlhl; 145 u32 mss_l4len_idx; 146 }; 147 148 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 149 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 150 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 151 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 152 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 153 154 enum e1000_mac_type { 155 e1000_undefined = 0, 156 e1000_vfadapt, 157 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 158 }; 159 160 struct e1000_vf_stats { 161 u64 base_gprc; 162 u64 base_gptc; 163 u64 base_gorc; 164 u64 base_gotc; 165 u64 base_mprc; 166 u64 base_gotlbc; 167 u64 base_gptlbc; 168 u64 base_gorlbc; 169 u64 base_gprlbc; 170 171 u32 last_gprc; 172 u32 last_gptc; 173 u32 last_gorc; 174 u32 last_gotc; 175 u32 last_mprc; 176 u32 last_gotlbc; 177 u32 last_gptlbc; 178 u32 last_gorlbc; 179 u32 last_gprlbc; 180 181 u64 gprc; 182 u64 gptc; 183 u64 gorc; 184 u64 gotc; 185 u64 mprc; 186 u64 gotlbc; 187 u64 gptlbc; 188 u64 gorlbc; 189 u64 gprlbc; 190 }; 191 192 #include "e1000_mbx.h" 193 194 struct e1000_mac_operations { 195 /* Function pointers for the MAC. */ 196 s32 (*init_params)(struct e1000_hw *); 197 s32 (*check_for_link)(struct e1000_hw *); 198 void (*clear_vfta)(struct e1000_hw *); 199 s32 (*get_bus_info)(struct e1000_hw *); 200 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 201 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 202 s32 (*reset_hw)(struct e1000_hw *); 203 s32 (*init_hw)(struct e1000_hw *); 204 s32 (*setup_link)(struct e1000_hw *); 205 void (*write_vfta)(struct e1000_hw *, u32, u32); 206 void (*rar_set)(struct e1000_hw *, u8*, u32); 207 s32 (*read_mac_addr)(struct e1000_hw *); 208 }; 209 210 struct e1000_mac_info { 211 struct e1000_mac_operations ops; 212 u8 addr[6]; 213 u8 perm_addr[6]; 214 215 enum e1000_mac_type type; 216 217 u16 mta_reg_count; 218 u16 rar_entry_count; 219 220 bool get_link_status; 221 }; 222 223 struct e1000_mbx_operations { 224 s32 (*init_params)(struct e1000_hw *hw); 225 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 226 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 227 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 228 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 229 s32 (*check_for_msg)(struct e1000_hw *, u16); 230 s32 (*check_for_ack)(struct e1000_hw *, u16); 231 s32 (*check_for_rst)(struct e1000_hw *, u16); 232 }; 233 234 struct e1000_mbx_stats { 235 u32 msgs_tx; 236 u32 msgs_rx; 237 238 u32 acks; 239 u32 reqs; 240 u32 rsts; 241 }; 242 243 struct e1000_mbx_info { 244 struct e1000_mbx_operations ops; 245 struct e1000_mbx_stats stats; 246 u32 timeout; 247 u32 usec_delay; 248 u16 size; 249 }; 250 251 struct e1000_dev_spec_vf { 252 u32 vf_number; 253 u32 v2p_mailbox; 254 }; 255 256 struct e1000_hw { 257 void *back; 258 259 u8 *hw_addr; 260 u8 *flash_address; 261 unsigned long io_base; 262 263 struct e1000_mac_info mac; 264 struct e1000_mbx_info mbx; 265 266 union { 267 struct e1000_dev_spec_vf vf; 268 } dev_spec; 269 270 u16 device_id; 271 u16 subsystem_vendor_id; 272 u16 subsystem_device_id; 273 u16 vendor_id; 274 275 u8 revision_id; 276 }; 277 278 enum e1000_promisc_type { 279 e1000_promisc_disabled = 0, /* all promisc modes disabled */ 280 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 281 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 282 e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 283 e1000_num_promisc_types 284 }; 285 286 /* These functions must be implemented by drivers */ 287 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 288 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 289 void e1000_rlpml_set_vf(struct e1000_hw *, u16); 290 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type); 291 #endif /* _E1000_VF_H_ */ 292