xref: /freebsd/sys/dev/e1000/e1000_phy.h (revision 6472ac3d8a86336899b6cfb789a4cd9897e3fab5)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2010, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _E1000_PHY_H_
36 #define _E1000_PHY_H_
37 
38 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
39 s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
40 void e1000_null_phy_generic(struct e1000_hw *hw);
41 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
42 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
43 s32  e1000_check_downshift_generic(struct e1000_hw *hw);
44 s32  e1000_check_polarity_m88(struct e1000_hw *hw);
45 s32  e1000_check_polarity_igp(struct e1000_hw *hw);
46 s32  e1000_check_polarity_ife(struct e1000_hw *hw);
47 s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
48 s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
49 s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
50 s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
51 s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
52 s32  e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);
53 s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
54 s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
55 s32  e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
56 s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
57 s32  e1000_get_cable_length_m88_gen2(struct e1000_hw *hw);
58 s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
59 s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
60 s32  e1000_get_phy_id(struct e1000_hw *hw);
61 s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
62 s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
63 s32  e1000_get_phy_info_ife(struct e1000_hw *hw);
64 s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
65 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
66 s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
67 s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
68 s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
69 s32  e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
70 s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
71 s32  e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
72 s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
73 s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
74 s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
75 s32  e1000_wait_autoneg_generic(struct e1000_hw *hw);
76 s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
77 s32  e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
78 s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
79 s32  e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
80 s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
81 s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
82 s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
83                                 u32 usec_interval, bool *success);
84 s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
85 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
86 s32  e1000_determine_phy_address(struct e1000_hw *hw);
87 s32  e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
88 s32  e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
89 s32  e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
90 s32  e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
91 void e1000_power_up_phy_copper(struct e1000_hw *hw);
92 void e1000_power_down_phy_copper(struct e1000_hw *hw);
93 s32  e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
94 s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
95 s32  e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
96 s32  e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
97 s32  e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
98 s32  e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
99 s32  e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
100 s32  e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
101 s32  e1000_link_stall_workaround_hv(struct e1000_hw *hw);
102 s32  e1000_copper_link_setup_82577(struct e1000_hw *hw);
103 s32  e1000_check_polarity_82577(struct e1000_hw *hw);
104 s32  e1000_get_phy_info_82577(struct e1000_hw *hw);
105 s32  e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
106 s32  e1000_get_cable_length_82577(struct e1000_hw *hw);
107 
108 #define E1000_MAX_PHY_ADDR                4
109 
110 /* IGP01E1000 Specific Registers */
111 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
112 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
113 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
114 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
115 #define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
116 #define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
117 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
118 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
119 #define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
120 #define IGP_PAGE_SHIFT                    5
121 #define PHY_REG_MASK                      0x1F
122 
123 /* BM/HV Specific Registers */
124 #define BM_PORT_CTRL_PAGE                 769
125 #define BM_PORT_GEN_CFG_REG               PHY_REG(BM_PORT_CTRL_PAGE, 17)
126 #define BM_PCIE_PAGE                      770
127 #define BM_WUC_PAGE                       800
128 #define BM_WUC_ADDRESS_OPCODE             0x11
129 #define BM_WUC_DATA_OPCODE                0x12
130 #define BM_WUC_ENABLE_PAGE                BM_PORT_CTRL_PAGE
131 #define BM_WUC_ENABLE_REG                 17
132 #define BM_WUC_ENABLE_BIT                 (1 << 2)
133 #define BM_WUC_HOST_WU_BIT                (1 << 4)
134 
135 #define PHY_UPPER_SHIFT                   21
136 #define BM_PHY_REG(page, reg) \
137 	(((reg) & MAX_PHY_REG_ADDRESS) |\
138 	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
139 	 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
140 #define BM_PHY_REG_PAGE(offset) \
141 	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
142 #define BM_PHY_REG_NUM(offset) \
143 	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
144 	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
145 		~MAX_PHY_REG_ADDRESS)))
146 
147 #define HV_INTC_FC_PAGE_START             768
148 #define I82578_ADDR_REG                   29
149 #define I82577_ADDR_REG                   16
150 #define I82577_CFG_REG                    22
151 #define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
152 #define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
153 #define I82577_CTRL_REG                   23
154 
155 /* 82577 specific PHY registers */
156 #define I82577_PHY_CTRL_2            18
157 #define I82577_PHY_LBK_CTRL          19
158 #define I82577_PHY_STATUS_2          26
159 #define I82577_PHY_DIAG_STATUS       31
160 
161 /* I82577 PHY Status 2 */
162 #define I82577_PHY_STATUS2_REV_POLARITY   0x0400
163 #define I82577_PHY_STATUS2_MDIX           0x0800
164 #define I82577_PHY_STATUS2_SPEED_MASK     0x0300
165 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
166 #define I82577_PHY_STATUS2_SPEED_100MBPS  0x0100
167 
168 /* I82577 PHY Control 2 */
169 #define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
170 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
171 
172 /* I82577 PHY Diagnostics Status */
173 #define I82577_DSTATUS_CABLE_LENGTH       0x03FC
174 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
175 
176 /* 82580 PHY Power Management */
177 #define E1000_82580_PHY_POWER_MGMT        0xE14
178 #define E1000_82580_PM_SPD                0x0001 /* Smart Power Down */
179 #define E1000_82580_PM_D0_LPLU            0x0002 /* For D0a states */
180 #define E1000_82580_PM_D3_LPLU            0x0004 /* For all other states */
181 
182 /* BM PHY Copper Specific Control 1 */
183 #define BM_CS_CTRL1                       16
184 #define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
185 
186 /* BM PHY Copper Specific Status */
187 #define BM_CS_STATUS                      17
188 #define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
189 #define BM_CS_STATUS_LINK_UP              0x0400
190 #define BM_CS_STATUS_RESOLVED             0x0800
191 #define BM_CS_STATUS_SPEED_MASK           0xC000
192 #define BM_CS_STATUS_SPEED_1000           0x8000
193 
194 /* 82577 Mobile Phy Status Register */
195 #define HV_M_STATUS                       26
196 #define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
197 #define HV_M_STATUS_SPEED_MASK            0x0300
198 #define HV_M_STATUS_SPEED_1000            0x0200
199 #define HV_M_STATUS_LINK_UP               0x0040
200 
201 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
202 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
203 
204 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
205 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
206 
207 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
208 
209 /* Enable flexible speed on link-up */
210 #define IGP01E1000_GMII_FLEX_SPD          0x0010
211 #define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
212 
213 #define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
214 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
215 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
216 
217 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
218 
219 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
220 #define IGP01E1000_PSSR_MDIX              0x0800
221 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
222 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
223 
224 #define IGP02E1000_PHY_CHANNEL_NUM        4
225 #define IGP02E1000_PHY_AGC_A              0x11B1
226 #define IGP02E1000_PHY_AGC_B              0x12B1
227 #define IGP02E1000_PHY_AGC_C              0x14B1
228 #define IGP02E1000_PHY_AGC_D              0x18B1
229 
230 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
231 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
232 #define IGP02E1000_AGC_RANGE              15
233 
234 #define IGP03E1000_PHY_MISC_CTRL          0x1B
235 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
236 
237 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
238 
239 #define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
240 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
241 #define E1000_KMRNCTRLSTA_REN             0x00200000
242 #define E1000_KMRNCTRLSTA_CTRL_OFFSET     0x1    /* Kumeran Control */
243 #define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
244 #define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
245 #define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
246 #define E1000_KMRNCTRLSTA_IBIST_DISABLE   0x0200 /* Kumeran IBIST Disable */
247 #define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
248 #define E1000_KMRNCTRLSTA_K1_CONFIG        0x7
249 #define E1000_KMRNCTRLSTA_K1_ENABLE        0x0002
250 #define E1000_KMRNCTRLSTA_HD_CTRL         0x10   /* Kumeran HD Control */
251 
252 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
253 #define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
254 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
255 #define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
256 
257 /* IFE PHY Extended Status Control */
258 #define IFE_PESC_POLARITY_REVERSED    0x0100
259 
260 /* IFE PHY Special Control */
261 #define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
262 #define IFE_PSC_FORCE_POLARITY             0x0020
263 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
264 
265 /* IFE PHY Special Control and LED Control */
266 #define IFE_PSCL_PROBE_MODE            0x0020
267 #define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
268 #define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
269 
270 /* IFE PHY MDIX Control */
271 #define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
272 #define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
273 #define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
274 
275 #endif
276