1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = 46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = 52 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 53 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 54 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 55 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 56 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 57 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 58 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 59 104, 109, 114, 118, 121, 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.read_reg = e1000_null_read_reg; 86 phy->ops.read_reg_locked = e1000_null_read_reg; 87 phy->ops.release = e1000_null_phy_generic; 88 phy->ops.reset = e1000_null_ops_generic; 89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 91 phy->ops.write_reg = e1000_null_write_reg; 92 phy->ops.write_reg_locked = e1000_null_write_reg; 93 phy->ops.power_up = e1000_null_phy_generic; 94 phy->ops.power_down = e1000_null_phy_generic; 95 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 96 } 97 98 /** 99 * e1000_null_read_reg - No-op function, return 0 100 * @hw: pointer to the HW structure 101 **/ 102 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 103 { 104 DEBUGFUNC("e1000_null_read_reg"); 105 return E1000_SUCCESS; 106 } 107 108 /** 109 * e1000_null_phy_generic - No-op function, return void 110 * @hw: pointer to the HW structure 111 **/ 112 void e1000_null_phy_generic(struct e1000_hw *hw) 113 { 114 DEBUGFUNC("e1000_null_phy_generic"); 115 return; 116 } 117 118 /** 119 * e1000_null_lplu_state - No-op function, return 0 120 * @hw: pointer to the HW structure 121 **/ 122 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 123 { 124 DEBUGFUNC("e1000_null_lplu_state"); 125 return E1000_SUCCESS; 126 } 127 128 /** 129 * e1000_null_write_reg - No-op function, return 0 130 * @hw: pointer to the HW structure 131 **/ 132 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 133 { 134 DEBUGFUNC("e1000_null_write_reg"); 135 return E1000_SUCCESS; 136 } 137 138 /** 139 * e1000_check_reset_block_generic - Check if PHY reset is blocked 140 * @hw: pointer to the HW structure 141 * 142 * Read the PHY management control register and check whether a PHY reset 143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 144 * return E1000_BLK_PHY_RESET (12). 145 **/ 146 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 147 { 148 u32 manc; 149 150 DEBUGFUNC("e1000_check_reset_block"); 151 152 manc = E1000_READ_REG(hw, E1000_MANC); 153 154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 155 E1000_BLK_PHY_RESET : E1000_SUCCESS; 156 } 157 158 /** 159 * e1000_get_phy_id - Retrieve the PHY ID and revision 160 * @hw: pointer to the HW structure 161 * 162 * Reads the PHY registers and stores the PHY ID and possibly the PHY 163 * revision in the hardware structure. 164 **/ 165 s32 e1000_get_phy_id(struct e1000_hw *hw) 166 { 167 struct e1000_phy_info *phy = &hw->phy; 168 s32 ret_val = E1000_SUCCESS; 169 u16 phy_id; 170 u16 retry_count = 0; 171 172 DEBUGFUNC("e1000_get_phy_id"); 173 174 if (!(phy->ops.read_reg)) 175 goto out; 176 177 while (retry_count < 2) { 178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 179 if (ret_val) 180 goto out; 181 182 phy->id = (u32)(phy_id << 16); 183 usec_delay(20); 184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 185 if (ret_val) 186 goto out; 187 188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 190 191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 192 goto out; 193 194 /* 195 * If the PHY ID is still unknown, we may have an 82577 196 * without link. We will try again after setting Slow MDIC 197 * mode. No harm in trying again in this case since the PHY 198 * ID is unknown at this point anyway. 199 */ 200 ret_val = phy->ops.acquire(hw); 201 if (ret_val) 202 goto out; 203 ret_val = e1000_set_mdio_slow_mode_hv(hw, TRUE); 204 if (ret_val) 205 goto out; 206 phy->ops.release(hw); 207 208 retry_count++; 209 } 210 out: 211 /* Revert to MDIO fast mode, if applicable */ 212 if (retry_count) { 213 ret_val = phy->ops.acquire(hw); 214 if (ret_val) 215 return ret_val; 216 ret_val = e1000_set_mdio_slow_mode_hv(hw, FALSE); 217 phy->ops.release(hw); 218 } 219 220 return ret_val; 221 } 222 223 /** 224 * e1000_phy_reset_dsp_generic - Reset PHY DSP 225 * @hw: pointer to the HW structure 226 * 227 * Reset the digital signal processor. 228 **/ 229 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 230 { 231 s32 ret_val = E1000_SUCCESS; 232 233 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 234 235 if (!(hw->phy.ops.write_reg)) 236 goto out; 237 238 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 239 if (ret_val) 240 goto out; 241 242 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 243 244 out: 245 return ret_val; 246 } 247 248 /** 249 * e1000_read_phy_reg_mdic - Read MDI control register 250 * @hw: pointer to the HW structure 251 * @offset: register offset to be read 252 * @data: pointer to the read data 253 * 254 * Reads the MDI control register in the PHY at offset and stores the 255 * information read to data. 256 **/ 257 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 258 { 259 struct e1000_phy_info *phy = &hw->phy; 260 u32 i, mdic = 0; 261 s32 ret_val = E1000_SUCCESS; 262 263 DEBUGFUNC("e1000_read_phy_reg_mdic"); 264 265 /* 266 * Set up Op-code, Phy Address, and register offset in the MDI 267 * Control register. The MAC will take care of interfacing with the 268 * PHY to retrieve the desired data. 269 */ 270 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 271 (phy->addr << E1000_MDIC_PHY_SHIFT) | 272 (E1000_MDIC_OP_READ)); 273 274 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 275 276 /* Workaround for Si errata */ 277 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 278 msec_delay(10); 279 280 /* 281 * Poll the ready bit to see if the MDI read completed 282 * Increasing the time out as testing showed failures with 283 * the lower time out 284 */ 285 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 286 usec_delay(50); 287 mdic = E1000_READ_REG(hw, E1000_MDIC); 288 if (mdic & E1000_MDIC_READY) 289 break; 290 } 291 if (!(mdic & E1000_MDIC_READY)) { 292 DEBUGOUT("MDI Read did not complete\n"); 293 ret_val = -E1000_ERR_PHY; 294 goto out; 295 } 296 if (mdic & E1000_MDIC_ERROR) { 297 DEBUGOUT("MDI Error\n"); 298 ret_val = -E1000_ERR_PHY; 299 goto out; 300 } 301 *data = (u16) mdic; 302 303 out: 304 return ret_val; 305 } 306 307 /** 308 * e1000_write_phy_reg_mdic - Write MDI control register 309 * @hw: pointer to the HW structure 310 * @offset: register offset to write to 311 * @data: data to write to register at offset 312 * 313 * Writes data to MDI control register in the PHY at offset. 314 **/ 315 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 316 { 317 struct e1000_phy_info *phy = &hw->phy; 318 u32 i, mdic = 0; 319 s32 ret_val = E1000_SUCCESS; 320 321 DEBUGFUNC("e1000_write_phy_reg_mdic"); 322 323 /* 324 * Set up Op-code, Phy Address, and register offset in the MDI 325 * Control register. The MAC will take care of interfacing with the 326 * PHY to retrieve the desired data. 327 */ 328 mdic = (((u32)data) | 329 (offset << E1000_MDIC_REG_SHIFT) | 330 (phy->addr << E1000_MDIC_PHY_SHIFT) | 331 (E1000_MDIC_OP_WRITE)); 332 333 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 334 335 /* Workaround for Si errata */ 336 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 337 msec_delay(10); 338 339 /* 340 * Poll the ready bit to see if the MDI read completed 341 * Increasing the time out as testing showed failures with 342 * the lower time out 343 */ 344 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 345 usec_delay(50); 346 mdic = E1000_READ_REG(hw, E1000_MDIC); 347 if (mdic & E1000_MDIC_READY) 348 break; 349 } 350 if (!(mdic & E1000_MDIC_READY)) { 351 DEBUGOUT("MDI Write did not complete\n"); 352 ret_val = -E1000_ERR_PHY; 353 goto out; 354 } 355 if (mdic & E1000_MDIC_ERROR) { 356 DEBUGOUT("MDI Error\n"); 357 ret_val = -E1000_ERR_PHY; 358 goto out; 359 } 360 361 out: 362 return ret_val; 363 } 364 365 /** 366 * e1000_read_phy_reg_i2c - Read PHY register using i2c 367 * @hw: pointer to the HW structure 368 * @offset: register offset to be read 369 * @data: pointer to the read data 370 * 371 * Reads the PHY register at offset using the i2c interface and stores the 372 * retrieved information in data. 373 **/ 374 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 375 { 376 struct e1000_phy_info *phy = &hw->phy; 377 u32 i, i2ccmd = 0; 378 379 DEBUGFUNC("e1000_read_phy_reg_i2c"); 380 381 /* 382 * Set up Op-code, Phy Address, and register address in the I2CCMD 383 * register. The MAC will take care of interfacing with the 384 * PHY to retrieve the desired data. 385 */ 386 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 387 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 388 (E1000_I2CCMD_OPCODE_READ)); 389 390 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 391 392 /* Poll the ready bit to see if the I2C read completed */ 393 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 394 usec_delay(50); 395 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 396 if (i2ccmd & E1000_I2CCMD_READY) 397 break; 398 } 399 if (!(i2ccmd & E1000_I2CCMD_READY)) { 400 DEBUGOUT("I2CCMD Read did not complete\n"); 401 return -E1000_ERR_PHY; 402 } 403 if (i2ccmd & E1000_I2CCMD_ERROR) { 404 DEBUGOUT("I2CCMD Error bit set\n"); 405 return -E1000_ERR_PHY; 406 } 407 408 /* Need to byte-swap the 16-bit value. */ 409 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 410 411 return E1000_SUCCESS; 412 } 413 414 /** 415 * e1000_write_phy_reg_i2c - Write PHY register using i2c 416 * @hw: pointer to the HW structure 417 * @offset: register offset to write to 418 * @data: data to write at register offset 419 * 420 * Writes the data to PHY register at the offset using the i2c interface. 421 **/ 422 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 423 { 424 struct e1000_phy_info *phy = &hw->phy; 425 u32 i, i2ccmd = 0; 426 u16 phy_data_swapped; 427 428 DEBUGFUNC("e1000_write_phy_reg_i2c"); 429 430 /* Swap the data bytes for the I2C interface */ 431 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 432 433 /* 434 * Set up Op-code, Phy Address, and register address in the I2CCMD 435 * register. The MAC will take care of interfacing with the 436 * PHY to retrieve the desired data. 437 */ 438 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 439 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 440 E1000_I2CCMD_OPCODE_WRITE | 441 phy_data_swapped); 442 443 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 444 445 /* Poll the ready bit to see if the I2C read completed */ 446 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 447 usec_delay(50); 448 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 449 if (i2ccmd & E1000_I2CCMD_READY) 450 break; 451 } 452 if (!(i2ccmd & E1000_I2CCMD_READY)) { 453 DEBUGOUT("I2CCMD Write did not complete\n"); 454 return -E1000_ERR_PHY; 455 } 456 if (i2ccmd & E1000_I2CCMD_ERROR) { 457 DEBUGOUT("I2CCMD Error bit set\n"); 458 return -E1000_ERR_PHY; 459 } 460 461 return E1000_SUCCESS; 462 } 463 464 /** 465 * e1000_read_phy_reg_m88 - Read m88 PHY register 466 * @hw: pointer to the HW structure 467 * @offset: register offset to be read 468 * @data: pointer to the read data 469 * 470 * Acquires semaphore, if necessary, then reads the PHY register at offset 471 * and storing the retrieved information in data. Release any acquired 472 * semaphores before exiting. 473 **/ 474 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 475 { 476 s32 ret_val = E1000_SUCCESS; 477 478 DEBUGFUNC("e1000_read_phy_reg_m88"); 479 480 if (!(hw->phy.ops.acquire)) 481 goto out; 482 483 ret_val = hw->phy.ops.acquire(hw); 484 if (ret_val) 485 goto out; 486 487 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 488 data); 489 490 hw->phy.ops.release(hw); 491 492 out: 493 return ret_val; 494 } 495 496 /** 497 * e1000_write_phy_reg_m88 - Write m88 PHY register 498 * @hw: pointer to the HW structure 499 * @offset: register offset to write to 500 * @data: data to write at register offset 501 * 502 * Acquires semaphore, if necessary, then writes the data to PHY register 503 * at the offset. Release any acquired semaphores before exiting. 504 **/ 505 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 506 { 507 s32 ret_val = E1000_SUCCESS; 508 509 DEBUGFUNC("e1000_write_phy_reg_m88"); 510 511 if (!(hw->phy.ops.acquire)) 512 goto out; 513 514 ret_val = hw->phy.ops.acquire(hw); 515 if (ret_val) 516 goto out; 517 518 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 519 data); 520 521 hw->phy.ops.release(hw); 522 523 out: 524 return ret_val; 525 } 526 527 /** 528 * __e1000_read_phy_reg_igp - Read igp PHY register 529 * @hw: pointer to the HW structure 530 * @offset: register offset to be read 531 * @data: pointer to the read data 532 * @locked: semaphore has already been acquired or not 533 * 534 * Acquires semaphore, if necessary, then reads the PHY register at offset 535 * and stores the retrieved information in data. Release any acquired 536 * semaphores before exiting. 537 **/ 538 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 539 bool locked) 540 { 541 s32 ret_val = E1000_SUCCESS; 542 543 DEBUGFUNC("__e1000_read_phy_reg_igp"); 544 545 if (!locked) { 546 if (!(hw->phy.ops.acquire)) 547 goto out; 548 549 ret_val = hw->phy.ops.acquire(hw); 550 if (ret_val) 551 goto out; 552 } 553 554 if (offset > MAX_PHY_MULTI_PAGE_REG) { 555 ret_val = e1000_write_phy_reg_mdic(hw, 556 IGP01E1000_PHY_PAGE_SELECT, 557 (u16)offset); 558 if (ret_val) 559 goto release; 560 } 561 562 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 563 data); 564 565 release: 566 if (!locked) 567 hw->phy.ops.release(hw); 568 out: 569 return ret_val; 570 } 571 572 /** 573 * e1000_read_phy_reg_igp - Read igp PHY register 574 * @hw: pointer to the HW structure 575 * @offset: register offset to be read 576 * @data: pointer to the read data 577 * 578 * Acquires semaphore then reads the PHY register at offset and stores the 579 * retrieved information in data. 580 * Release the acquired semaphore before exiting. 581 **/ 582 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 583 { 584 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 585 } 586 587 /** 588 * e1000_read_phy_reg_igp_locked - Read igp PHY register 589 * @hw: pointer to the HW structure 590 * @offset: register offset to be read 591 * @data: pointer to the read data 592 * 593 * Reads the PHY register at offset and stores the retrieved information 594 * in data. Assumes semaphore already acquired. 595 **/ 596 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 597 { 598 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 599 } 600 601 /** 602 * e1000_write_phy_reg_igp - Write igp PHY register 603 * @hw: pointer to the HW structure 604 * @offset: register offset to write to 605 * @data: data to write at register offset 606 * @locked: semaphore has already been acquired or not 607 * 608 * Acquires semaphore, if necessary, then writes the data to PHY register 609 * at the offset. Release any acquired semaphores before exiting. 610 **/ 611 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 612 bool locked) 613 { 614 s32 ret_val = E1000_SUCCESS; 615 616 DEBUGFUNC("e1000_write_phy_reg_igp"); 617 618 if (!locked) { 619 if (!(hw->phy.ops.acquire)) 620 goto out; 621 622 ret_val = hw->phy.ops.acquire(hw); 623 if (ret_val) 624 goto out; 625 } 626 627 if (offset > MAX_PHY_MULTI_PAGE_REG) { 628 ret_val = e1000_write_phy_reg_mdic(hw, 629 IGP01E1000_PHY_PAGE_SELECT, 630 (u16)offset); 631 if (ret_val) 632 goto release; 633 } 634 635 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 636 data); 637 638 release: 639 if (!locked) 640 hw->phy.ops.release(hw); 641 642 out: 643 return ret_val; 644 } 645 646 /** 647 * e1000_write_phy_reg_igp - Write igp PHY register 648 * @hw: pointer to the HW structure 649 * @offset: register offset to write to 650 * @data: data to write at register offset 651 * 652 * Acquires semaphore then writes the data to PHY register 653 * at the offset. Release any acquired semaphores before exiting. 654 **/ 655 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 656 { 657 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 658 } 659 660 /** 661 * e1000_write_phy_reg_igp_locked - Write igp PHY register 662 * @hw: pointer to the HW structure 663 * @offset: register offset to write to 664 * @data: data to write at register offset 665 * 666 * Writes the data to PHY register at the offset. 667 * Assumes semaphore already acquired. 668 **/ 669 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 670 { 671 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 672 } 673 674 /** 675 * __e1000_read_kmrn_reg - Read kumeran register 676 * @hw: pointer to the HW structure 677 * @offset: register offset to be read 678 * @data: pointer to the read data 679 * @locked: semaphore has already been acquired or not 680 * 681 * Acquires semaphore, if necessary. Then reads the PHY register at offset 682 * using the kumeran interface. The information retrieved is stored in data. 683 * Release any acquired semaphores before exiting. 684 **/ 685 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 686 bool locked) 687 { 688 u32 kmrnctrlsta; 689 s32 ret_val = E1000_SUCCESS; 690 691 DEBUGFUNC("__e1000_read_kmrn_reg"); 692 693 if (!locked) { 694 if (!(hw->phy.ops.acquire)) 695 goto out; 696 697 ret_val = hw->phy.ops.acquire(hw); 698 if (ret_val) 699 goto out; 700 } 701 702 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 703 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 704 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 705 706 usec_delay(2); 707 708 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 709 *data = (u16)kmrnctrlsta; 710 711 if (!locked) 712 hw->phy.ops.release(hw); 713 714 out: 715 return ret_val; 716 } 717 718 /** 719 * e1000_read_kmrn_reg_generic - Read kumeran register 720 * @hw: pointer to the HW structure 721 * @offset: register offset to be read 722 * @data: pointer to the read data 723 * 724 * Acquires semaphore then reads the PHY register at offset using the 725 * kumeran interface. The information retrieved is stored in data. 726 * Release the acquired semaphore before exiting. 727 **/ 728 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 729 { 730 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 731 } 732 733 /** 734 * e1000_read_kmrn_reg_locked - Read kumeran register 735 * @hw: pointer to the HW structure 736 * @offset: register offset to be read 737 * @data: pointer to the read data 738 * 739 * Reads the PHY register at offset using the kumeran interface. The 740 * information retrieved is stored in data. 741 * Assumes semaphore already acquired. 742 **/ 743 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 744 { 745 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 746 } 747 748 /** 749 * __e1000_write_kmrn_reg - Write kumeran register 750 * @hw: pointer to the HW structure 751 * @offset: register offset to write to 752 * @data: data to write at register offset 753 * @locked: semaphore has already been acquired or not 754 * 755 * Acquires semaphore, if necessary. Then write the data to PHY register 756 * at the offset using the kumeran interface. Release any acquired semaphores 757 * before exiting. 758 **/ 759 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 760 bool locked) 761 { 762 u32 kmrnctrlsta; 763 s32 ret_val = E1000_SUCCESS; 764 765 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 766 767 if (!locked) { 768 if (!(hw->phy.ops.acquire)) 769 goto out; 770 771 ret_val = hw->phy.ops.acquire(hw); 772 if (ret_val) 773 goto out; 774 } 775 776 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 777 E1000_KMRNCTRLSTA_OFFSET) | data; 778 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 779 780 usec_delay(2); 781 782 if (!locked) 783 hw->phy.ops.release(hw); 784 785 out: 786 return ret_val; 787 } 788 789 /** 790 * e1000_write_kmrn_reg_generic - Write kumeran register 791 * @hw: pointer to the HW structure 792 * @offset: register offset to write to 793 * @data: data to write at register offset 794 * 795 * Acquires semaphore then writes the data to the PHY register at the offset 796 * using the kumeran interface. Release the acquired semaphore before exiting. 797 **/ 798 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 799 { 800 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 801 } 802 803 /** 804 * e1000_write_kmrn_reg_locked - Write kumeran register 805 * @hw: pointer to the HW structure 806 * @offset: register offset to write to 807 * @data: data to write at register offset 808 * 809 * Write the data to PHY register at the offset using the kumeran interface. 810 * Assumes semaphore already acquired. 811 **/ 812 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 813 { 814 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 815 } 816 817 /** 818 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 819 * @hw: pointer to the HW structure 820 * 821 * Sets up Carrier-sense on Transmit and downshift values. 822 **/ 823 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 824 { 825 struct e1000_phy_info *phy = &hw->phy; 826 s32 ret_val; 827 u16 phy_data; 828 829 DEBUGFUNC("e1000_copper_link_setup_82577"); 830 831 if (phy->reset_disable) { 832 ret_val = E1000_SUCCESS; 833 goto out; 834 } 835 836 if (phy->type == e1000_phy_82580) { 837 ret_val = hw->phy.ops.reset(hw); 838 if (ret_val) { 839 DEBUGOUT("Error resetting the PHY.\n"); 840 goto out; 841 } 842 } 843 844 /* Enable CRS on TX. This must be set for half-duplex operation. */ 845 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); 846 if (ret_val) 847 goto out; 848 849 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 850 851 /* Enable downshift */ 852 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 853 854 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); 855 856 out: 857 return ret_val; 858 } 859 860 /** 861 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 862 * @hw: pointer to the HW structure 863 * 864 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 865 * and downshift values are set also. 866 **/ 867 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 868 { 869 struct e1000_phy_info *phy = &hw->phy; 870 s32 ret_val; 871 u16 phy_data; 872 873 DEBUGFUNC("e1000_copper_link_setup_m88"); 874 875 if (phy->reset_disable) { 876 ret_val = E1000_SUCCESS; 877 goto out; 878 } 879 880 /* Enable CRS on TX. This must be set for half-duplex operation. */ 881 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 882 if (ret_val) 883 goto out; 884 885 /* For BM PHY this bit is downshift enable */ 886 if (phy->type != e1000_phy_bm) 887 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 888 889 /* 890 * Options: 891 * MDI/MDI-X = 0 (default) 892 * 0 - Auto for all speeds 893 * 1 - MDI mode 894 * 2 - MDI-X mode 895 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 896 */ 897 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 898 899 switch (phy->mdix) { 900 case 1: 901 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 902 break; 903 case 2: 904 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 905 break; 906 case 3: 907 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 908 break; 909 case 0: 910 default: 911 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 912 break; 913 } 914 915 /* 916 * Options: 917 * disable_polarity_correction = 0 (default) 918 * Automatic Correction for Reversed Cable Polarity 919 * 0 - Disabled 920 * 1 - Enabled 921 */ 922 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 923 if (phy->disable_polarity_correction == 1) 924 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 925 926 /* Enable downshift on BM (disabled by default) */ 927 if (phy->type == e1000_phy_bm) 928 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 929 930 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 931 if (ret_val) 932 goto out; 933 934 if ((phy->type == e1000_phy_m88) && 935 (phy->revision < E1000_REVISION_4) && 936 (phy->id != BME1000_E_PHY_ID_R2)) { 937 /* 938 * Force TX_CLK in the Extended PHY Specific Control Register 939 * to 25MHz clock. 940 */ 941 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 942 &phy_data); 943 if (ret_val) 944 goto out; 945 946 phy_data |= M88E1000_EPSCR_TX_CLK_25; 947 948 if ((phy->revision == E1000_REVISION_2) && 949 (phy->id == M88E1111_I_PHY_ID)) { 950 /* 82573L PHY - set the downshift counter to 5x. */ 951 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 952 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 953 } else { 954 /* Configure Master and Slave downshift values */ 955 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 956 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 957 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 958 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 959 } 960 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 961 phy_data); 962 if (ret_val) 963 goto out; 964 } 965 966 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 967 /* Set PHY page 0, register 29 to 0x0003 */ 968 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 969 if (ret_val) 970 goto out; 971 972 /* Set PHY page 0, register 30 to 0x0000 */ 973 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 974 if (ret_val) 975 goto out; 976 } 977 978 /* Commit the changes. */ 979 ret_val = phy->ops.commit(hw); 980 if (ret_val) { 981 DEBUGOUT("Error committing the PHY changes\n"); 982 goto out; 983 } 984 985 if (phy->type == e1000_phy_82578) { 986 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 987 &phy_data); 988 if (ret_val) 989 goto out; 990 991 /* 82578 PHY - set the downshift count to 1x. */ 992 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 993 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 994 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 995 phy_data); 996 if (ret_val) 997 goto out; 998 } 999 1000 out: 1001 return ret_val; 1002 } 1003 1004 /** 1005 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1006 * @hw: pointer to the HW structure 1007 * 1008 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1009 * igp PHY's. 1010 **/ 1011 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1012 { 1013 struct e1000_phy_info *phy = &hw->phy; 1014 s32 ret_val; 1015 u16 data; 1016 1017 DEBUGFUNC("e1000_copper_link_setup_igp"); 1018 1019 if (phy->reset_disable) { 1020 ret_val = E1000_SUCCESS; 1021 goto out; 1022 } 1023 1024 ret_val = hw->phy.ops.reset(hw); 1025 if (ret_val) { 1026 DEBUGOUT("Error resetting the PHY.\n"); 1027 goto out; 1028 } 1029 1030 /* 1031 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1032 * timeout issues when LFS is enabled. 1033 */ 1034 msec_delay(100); 1035 1036 /* 1037 * The NVM settings will configure LPLU in D3 for 1038 * non-IGP1 PHYs. 1039 */ 1040 if (phy->type == e1000_phy_igp) { 1041 /* disable lplu d3 during driver init */ 1042 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1043 if (ret_val) { 1044 DEBUGOUT("Error Disabling LPLU D3\n"); 1045 goto out; 1046 } 1047 } 1048 1049 /* disable lplu d0 during driver init */ 1050 if (hw->phy.ops.set_d0_lplu_state) { 1051 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1052 if (ret_val) { 1053 DEBUGOUT("Error Disabling LPLU D0\n"); 1054 goto out; 1055 } 1056 } 1057 /* Configure mdi-mdix settings */ 1058 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1059 if (ret_val) 1060 goto out; 1061 1062 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1063 1064 switch (phy->mdix) { 1065 case 1: 1066 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1067 break; 1068 case 2: 1069 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1070 break; 1071 case 0: 1072 default: 1073 data |= IGP01E1000_PSCR_AUTO_MDIX; 1074 break; 1075 } 1076 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1077 if (ret_val) 1078 goto out; 1079 1080 /* set auto-master slave resolution settings */ 1081 if (hw->mac.autoneg) { 1082 /* 1083 * when autonegotiation advertisement is only 1000Mbps then we 1084 * should disable SmartSpeed and enable Auto MasterSlave 1085 * resolution as hardware default. 1086 */ 1087 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1088 /* Disable SmartSpeed */ 1089 ret_val = phy->ops.read_reg(hw, 1090 IGP01E1000_PHY_PORT_CONFIG, 1091 &data); 1092 if (ret_val) 1093 goto out; 1094 1095 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1096 ret_val = phy->ops.write_reg(hw, 1097 IGP01E1000_PHY_PORT_CONFIG, 1098 data); 1099 if (ret_val) 1100 goto out; 1101 1102 /* Set auto Master/Slave resolution process */ 1103 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1104 if (ret_val) 1105 goto out; 1106 1107 data &= ~CR_1000T_MS_ENABLE; 1108 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1109 if (ret_val) 1110 goto out; 1111 } 1112 1113 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1114 if (ret_val) 1115 goto out; 1116 1117 /* load defaults for future use */ 1118 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 1119 ((data & CR_1000T_MS_VALUE) ? 1120 e1000_ms_force_master : 1121 e1000_ms_force_slave) : 1122 e1000_ms_auto; 1123 1124 switch (phy->ms_type) { 1125 case e1000_ms_force_master: 1126 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1127 break; 1128 case e1000_ms_force_slave: 1129 data |= CR_1000T_MS_ENABLE; 1130 data &= ~(CR_1000T_MS_VALUE); 1131 break; 1132 case e1000_ms_auto: 1133 data &= ~CR_1000T_MS_ENABLE; 1134 default: 1135 break; 1136 } 1137 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1138 if (ret_val) 1139 goto out; 1140 } 1141 1142 out: 1143 return ret_val; 1144 } 1145 1146 /** 1147 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1148 * @hw: pointer to the HW structure 1149 * 1150 * Performs initial bounds checking on autoneg advertisement parameter, then 1151 * configure to advertise the full capability. Setup the PHY to autoneg 1152 * and restart the negotiation process between the link partner. If 1153 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1154 **/ 1155 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1156 { 1157 struct e1000_phy_info *phy = &hw->phy; 1158 s32 ret_val; 1159 u16 phy_ctrl; 1160 1161 DEBUGFUNC("e1000_copper_link_autoneg"); 1162 1163 /* 1164 * Perform some bounds checking on the autoneg advertisement 1165 * parameter. 1166 */ 1167 phy->autoneg_advertised &= phy->autoneg_mask; 1168 1169 /* 1170 * If autoneg_advertised is zero, we assume it was not defaulted 1171 * by the calling code so we set to advertise full capability. 1172 */ 1173 if (phy->autoneg_advertised == 0) 1174 phy->autoneg_advertised = phy->autoneg_mask; 1175 1176 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1177 ret_val = e1000_phy_setup_autoneg(hw); 1178 if (ret_val) { 1179 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1180 goto out; 1181 } 1182 DEBUGOUT("Restarting Auto-Neg\n"); 1183 1184 /* 1185 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1186 * the Auto Neg Restart bit in the PHY control register. 1187 */ 1188 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1189 if (ret_val) 1190 goto out; 1191 1192 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1193 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1194 if (ret_val) 1195 goto out; 1196 1197 /* 1198 * Does the user want to wait for Auto-Neg to complete here, or 1199 * check at a later time (for example, callback routine). 1200 */ 1201 if (phy->autoneg_wait_to_complete) { 1202 ret_val = hw->mac.ops.wait_autoneg(hw); 1203 if (ret_val) { 1204 DEBUGOUT("Error while waiting for " 1205 "autoneg to complete\n"); 1206 goto out; 1207 } 1208 } 1209 1210 hw->mac.get_link_status = TRUE; 1211 1212 out: 1213 return ret_val; 1214 } 1215 1216 /** 1217 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1218 * @hw: pointer to the HW structure 1219 * 1220 * Reads the MII auto-neg advertisement register and/or the 1000T control 1221 * register and if the PHY is already setup for auto-negotiation, then 1222 * return successful. Otherwise, setup advertisement and flow control to 1223 * the appropriate values for the wanted auto-negotiation. 1224 **/ 1225 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1226 { 1227 struct e1000_phy_info *phy = &hw->phy; 1228 s32 ret_val; 1229 u16 mii_autoneg_adv_reg; 1230 u16 mii_1000t_ctrl_reg = 0; 1231 1232 DEBUGFUNC("e1000_phy_setup_autoneg"); 1233 1234 phy->autoneg_advertised &= phy->autoneg_mask; 1235 1236 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1237 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1238 if (ret_val) 1239 goto out; 1240 1241 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1242 /* Read the MII 1000Base-T Control Register (Address 9). */ 1243 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1244 &mii_1000t_ctrl_reg); 1245 if (ret_val) 1246 goto out; 1247 } 1248 1249 /* 1250 * Need to parse both autoneg_advertised and fc and set up 1251 * the appropriate PHY registers. First we will parse for 1252 * autoneg_advertised software override. Since we can advertise 1253 * a plethora of combinations, we need to check each bit 1254 * individually. 1255 */ 1256 1257 /* 1258 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1259 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1260 * the 1000Base-T Control Register (Address 9). 1261 */ 1262 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1263 NWAY_AR_100TX_HD_CAPS | 1264 NWAY_AR_10T_FD_CAPS | 1265 NWAY_AR_10T_HD_CAPS); 1266 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1267 1268 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1269 1270 /* Do we want to advertise 10 Mb Half Duplex? */ 1271 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1272 DEBUGOUT("Advertise 10mb Half duplex\n"); 1273 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1274 } 1275 1276 /* Do we want to advertise 10 Mb Full Duplex? */ 1277 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1278 DEBUGOUT("Advertise 10mb Full duplex\n"); 1279 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1280 } 1281 1282 /* Do we want to advertise 100 Mb Half Duplex? */ 1283 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1284 DEBUGOUT("Advertise 100mb Half duplex\n"); 1285 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1286 } 1287 1288 /* Do we want to advertise 100 Mb Full Duplex? */ 1289 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1290 DEBUGOUT("Advertise 100mb Full duplex\n"); 1291 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1292 } 1293 1294 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1295 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1296 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1297 1298 /* Do we want to advertise 1000 Mb Full Duplex? */ 1299 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1300 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1301 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1302 } 1303 1304 /* 1305 * Check for a software override of the flow control settings, and 1306 * setup the PHY advertisement registers accordingly. If 1307 * auto-negotiation is enabled, then software will have to set the 1308 * "PAUSE" bits to the correct value in the Auto-Negotiation 1309 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1310 * negotiation. 1311 * 1312 * The possible values of the "fc" parameter are: 1313 * 0: Flow control is completely disabled 1314 * 1: Rx flow control is enabled (we can receive pause frames 1315 * but not send pause frames). 1316 * 2: Tx flow control is enabled (we can send pause frames 1317 * but we do not support receiving pause frames). 1318 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1319 * other: No software override. The flow control configuration 1320 * in the EEPROM is used. 1321 */ 1322 switch (hw->fc.current_mode) { 1323 case e1000_fc_none: 1324 /* 1325 * Flow control (Rx & Tx) is completely disabled by a 1326 * software over-ride. 1327 */ 1328 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1329 break; 1330 case e1000_fc_rx_pause: 1331 /* 1332 * Rx Flow control is enabled, and Tx Flow control is 1333 * disabled, by a software over-ride. 1334 * 1335 * Since there really isn't a way to advertise that we are 1336 * capable of Rx Pause ONLY, we will advertise that we 1337 * support both symmetric and asymmetric Rx PAUSE. Later 1338 * (in e1000_config_fc_after_link_up) we will disable the 1339 * hw's ability to send PAUSE frames. 1340 */ 1341 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1342 break; 1343 case e1000_fc_tx_pause: 1344 /* 1345 * Tx Flow control is enabled, and Rx Flow control is 1346 * disabled, by a software over-ride. 1347 */ 1348 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1349 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1350 break; 1351 case e1000_fc_full: 1352 /* 1353 * Flow control (both Rx and Tx) is enabled by a software 1354 * over-ride. 1355 */ 1356 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1357 break; 1358 default: 1359 DEBUGOUT("Flow control param set incorrectly\n"); 1360 ret_val = -E1000_ERR_CONFIG; 1361 goto out; 1362 } 1363 1364 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1365 if (ret_val) 1366 goto out; 1367 1368 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1369 1370 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1371 ret_val = phy->ops.write_reg(hw, 1372 PHY_1000T_CTRL, 1373 mii_1000t_ctrl_reg); 1374 if (ret_val) 1375 goto out; 1376 } 1377 1378 out: 1379 return ret_val; 1380 } 1381 1382 /** 1383 * e1000_setup_copper_link_generic - Configure copper link settings 1384 * @hw: pointer to the HW structure 1385 * 1386 * Calls the appropriate function to configure the link for auto-neg or forced 1387 * speed and duplex. Then we check for link, once link is established calls 1388 * to configure collision distance and flow control are called. If link is 1389 * not established, we return -E1000_ERR_PHY (-2). 1390 **/ 1391 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1392 { 1393 s32 ret_val; 1394 bool link; 1395 1396 DEBUGFUNC("e1000_setup_copper_link_generic"); 1397 1398 if (hw->mac.autoneg) { 1399 /* 1400 * Setup autoneg and flow control advertisement and perform 1401 * autonegotiation. 1402 */ 1403 ret_val = e1000_copper_link_autoneg(hw); 1404 if (ret_val) 1405 goto out; 1406 } else { 1407 /* 1408 * PHY will be set to 10H, 10F, 100H or 100F 1409 * depending on user settings. 1410 */ 1411 DEBUGOUT("Forcing Speed and Duplex\n"); 1412 ret_val = hw->phy.ops.force_speed_duplex(hw); 1413 if (ret_val) { 1414 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1415 goto out; 1416 } 1417 } 1418 1419 /* 1420 * Check link status. Wait up to 100 microseconds for link to become 1421 * valid. 1422 */ 1423 ret_val = e1000_phy_has_link_generic(hw, 1424 COPPER_LINK_UP_LIMIT, 1425 10, 1426 &link); 1427 if (ret_val) 1428 goto out; 1429 1430 if (link) { 1431 DEBUGOUT("Valid link established!!!\n"); 1432 e1000_config_collision_dist_generic(hw); 1433 ret_val = e1000_config_fc_after_link_up_generic(hw); 1434 } else { 1435 DEBUGOUT("Unable to establish link!!!\n"); 1436 } 1437 1438 out: 1439 return ret_val; 1440 } 1441 1442 /** 1443 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1444 * @hw: pointer to the HW structure 1445 * 1446 * Calls the PHY setup function to force speed and duplex. Clears the 1447 * auto-crossover to force MDI manually. Waits for link and returns 1448 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1449 **/ 1450 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1451 { 1452 struct e1000_phy_info *phy = &hw->phy; 1453 s32 ret_val; 1454 u16 phy_data; 1455 bool link; 1456 1457 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1458 1459 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1460 if (ret_val) 1461 goto out; 1462 1463 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1464 1465 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1466 if (ret_val) 1467 goto out; 1468 1469 /* 1470 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1471 * forced whenever speed and duplex are forced. 1472 */ 1473 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1474 if (ret_val) 1475 goto out; 1476 1477 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1478 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1479 1480 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1481 if (ret_val) 1482 goto out; 1483 1484 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1485 1486 usec_delay(1); 1487 1488 if (phy->autoneg_wait_to_complete) { 1489 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1490 1491 ret_val = e1000_phy_has_link_generic(hw, 1492 PHY_FORCE_LIMIT, 1493 100000, 1494 &link); 1495 if (ret_val) 1496 goto out; 1497 1498 if (!link) 1499 DEBUGOUT("Link taking longer than expected.\n"); 1500 1501 /* Try once more */ 1502 ret_val = e1000_phy_has_link_generic(hw, 1503 PHY_FORCE_LIMIT, 1504 100000, 1505 &link); 1506 if (ret_val) 1507 goto out; 1508 } 1509 1510 out: 1511 return ret_val; 1512 } 1513 1514 /** 1515 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1516 * @hw: pointer to the HW structure 1517 * 1518 * Calls the PHY setup function to force speed and duplex. Clears the 1519 * auto-crossover to force MDI manually. Resets the PHY to commit the 1520 * changes. If time expires while waiting for link up, we reset the DSP. 1521 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1522 * successful completion, else return corresponding error code. 1523 **/ 1524 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1525 { 1526 struct e1000_phy_info *phy = &hw->phy; 1527 s32 ret_val; 1528 u16 phy_data; 1529 bool link; 1530 1531 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1532 1533 /* 1534 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1535 * forced whenever speed and duplex are forced. 1536 */ 1537 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1538 if (ret_val) 1539 goto out; 1540 1541 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1542 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1543 if (ret_val) 1544 goto out; 1545 1546 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1547 1548 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1549 if (ret_val) 1550 goto out; 1551 1552 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1553 1554 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1555 if (ret_val) 1556 goto out; 1557 1558 /* Reset the phy to commit changes. */ 1559 ret_val = hw->phy.ops.commit(hw); 1560 if (ret_val) 1561 goto out; 1562 1563 if (phy->autoneg_wait_to_complete) { 1564 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1565 1566 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1567 100000, &link); 1568 if (ret_val) 1569 goto out; 1570 1571 if (!link) { 1572 if (hw->phy.type != e1000_phy_m88) { 1573 DEBUGOUT("Link taking longer than expected.\n"); 1574 } else { 1575 /* 1576 * We didn't get link. 1577 * Reset the DSP and cross our fingers. 1578 */ 1579 ret_val = phy->ops.write_reg(hw, 1580 M88E1000_PHY_PAGE_SELECT, 1581 0x001d); 1582 if (ret_val) 1583 goto out; 1584 ret_val = e1000_phy_reset_dsp_generic(hw); 1585 if (ret_val) 1586 goto out; 1587 } 1588 } 1589 1590 /* Try once more */ 1591 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1592 100000, &link); 1593 if (ret_val) 1594 goto out; 1595 } 1596 1597 if (hw->phy.type != e1000_phy_m88) 1598 goto out; 1599 1600 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1601 if (ret_val) 1602 goto out; 1603 1604 /* 1605 * Resetting the phy means we need to re-force TX_CLK in the 1606 * Extended PHY Specific Control Register to 25MHz clock from 1607 * the reset value of 2.5MHz. 1608 */ 1609 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1610 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1611 if (ret_val) 1612 goto out; 1613 1614 /* 1615 * In addition, we must re-enable CRS on Tx for both half and full 1616 * duplex. 1617 */ 1618 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1619 if (ret_val) 1620 goto out; 1621 1622 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1623 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1624 1625 out: 1626 return ret_val; 1627 } 1628 1629 /** 1630 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1631 * @hw: pointer to the HW structure 1632 * 1633 * Forces the speed and duplex settings of the PHY. 1634 * This is a function pointer entry point only called by 1635 * PHY setup routines. 1636 **/ 1637 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1638 { 1639 struct e1000_phy_info *phy = &hw->phy; 1640 s32 ret_val; 1641 u16 data; 1642 bool link; 1643 1644 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1645 1646 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1647 if (ret_val) 1648 goto out; 1649 1650 e1000_phy_force_speed_duplex_setup(hw, &data); 1651 1652 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1653 if (ret_val) 1654 goto out; 1655 1656 /* Disable MDI-X support for 10/100 */ 1657 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1658 if (ret_val) 1659 goto out; 1660 1661 data &= ~IFE_PMC_AUTO_MDIX; 1662 data &= ~IFE_PMC_FORCE_MDIX; 1663 1664 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1665 if (ret_val) 1666 goto out; 1667 1668 DEBUGOUT1("IFE PMC: %X\n", data); 1669 1670 usec_delay(1); 1671 1672 if (phy->autoneg_wait_to_complete) { 1673 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1674 1675 ret_val = e1000_phy_has_link_generic(hw, 1676 PHY_FORCE_LIMIT, 1677 100000, 1678 &link); 1679 if (ret_val) 1680 goto out; 1681 1682 if (!link) 1683 DEBUGOUT("Link taking longer than expected.\n"); 1684 1685 /* Try once more */ 1686 ret_val = e1000_phy_has_link_generic(hw, 1687 PHY_FORCE_LIMIT, 1688 100000, 1689 &link); 1690 if (ret_val) 1691 goto out; 1692 } 1693 1694 out: 1695 return ret_val; 1696 } 1697 1698 /** 1699 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1700 * @hw: pointer to the HW structure 1701 * @phy_ctrl: pointer to current value of PHY_CONTROL 1702 * 1703 * Forces speed and duplex on the PHY by doing the following: disable flow 1704 * control, force speed/duplex on the MAC, disable auto speed detection, 1705 * disable auto-negotiation, configure duplex, configure speed, configure 1706 * the collision distance, write configuration to CTRL register. The 1707 * caller must write to the PHY_CONTROL register for these settings to 1708 * take affect. 1709 **/ 1710 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1711 { 1712 struct e1000_mac_info *mac = &hw->mac; 1713 u32 ctrl; 1714 1715 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1716 1717 /* Turn off flow control when forcing speed/duplex */ 1718 hw->fc.current_mode = e1000_fc_none; 1719 1720 /* Force speed/duplex on the mac */ 1721 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1722 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1723 ctrl &= ~E1000_CTRL_SPD_SEL; 1724 1725 /* Disable Auto Speed Detection */ 1726 ctrl &= ~E1000_CTRL_ASDE; 1727 1728 /* Disable autoneg on the phy */ 1729 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1730 1731 /* Forcing Full or Half Duplex? */ 1732 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1733 ctrl &= ~E1000_CTRL_FD; 1734 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1735 DEBUGOUT("Half Duplex\n"); 1736 } else { 1737 ctrl |= E1000_CTRL_FD; 1738 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1739 DEBUGOUT("Full Duplex\n"); 1740 } 1741 1742 /* Forcing 10mb or 100mb? */ 1743 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1744 ctrl |= E1000_CTRL_SPD_100; 1745 *phy_ctrl |= MII_CR_SPEED_100; 1746 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1747 DEBUGOUT("Forcing 100mb\n"); 1748 } else { 1749 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1750 *phy_ctrl |= MII_CR_SPEED_10; 1751 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1752 DEBUGOUT("Forcing 10mb\n"); 1753 } 1754 1755 e1000_config_collision_dist_generic(hw); 1756 1757 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1758 } 1759 1760 /** 1761 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1762 * @hw: pointer to the HW structure 1763 * @active: boolean used to enable/disable lplu 1764 * 1765 * Success returns 0, Failure returns 1 1766 * 1767 * The low power link up (lplu) state is set to the power management level D3 1768 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1769 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1770 * is used during Dx states where the power conservation is most important. 1771 * During driver activity, SmartSpeed should be enabled so performance is 1772 * maintained. 1773 **/ 1774 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1775 { 1776 struct e1000_phy_info *phy = &hw->phy; 1777 s32 ret_val = E1000_SUCCESS; 1778 u16 data; 1779 1780 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1781 1782 if (!(hw->phy.ops.read_reg)) 1783 goto out; 1784 1785 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1786 if (ret_val) 1787 goto out; 1788 1789 if (!active) { 1790 data &= ~IGP02E1000_PM_D3_LPLU; 1791 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1792 data); 1793 if (ret_val) 1794 goto out; 1795 /* 1796 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1797 * during Dx states where the power conservation is most 1798 * important. During driver activity we should enable 1799 * SmartSpeed, so performance is maintained. 1800 */ 1801 if (phy->smart_speed == e1000_smart_speed_on) { 1802 ret_val = phy->ops.read_reg(hw, 1803 IGP01E1000_PHY_PORT_CONFIG, 1804 &data); 1805 if (ret_val) 1806 goto out; 1807 1808 data |= IGP01E1000_PSCFR_SMART_SPEED; 1809 ret_val = phy->ops.write_reg(hw, 1810 IGP01E1000_PHY_PORT_CONFIG, 1811 data); 1812 if (ret_val) 1813 goto out; 1814 } else if (phy->smart_speed == e1000_smart_speed_off) { 1815 ret_val = phy->ops.read_reg(hw, 1816 IGP01E1000_PHY_PORT_CONFIG, 1817 &data); 1818 if (ret_val) 1819 goto out; 1820 1821 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1822 ret_val = phy->ops.write_reg(hw, 1823 IGP01E1000_PHY_PORT_CONFIG, 1824 data); 1825 if (ret_val) 1826 goto out; 1827 } 1828 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1829 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1830 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1831 data |= IGP02E1000_PM_D3_LPLU; 1832 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1833 data); 1834 if (ret_val) 1835 goto out; 1836 1837 /* When LPLU is enabled, we should disable SmartSpeed */ 1838 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1839 &data); 1840 if (ret_val) 1841 goto out; 1842 1843 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1844 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1845 data); 1846 } 1847 1848 out: 1849 return ret_val; 1850 } 1851 1852 /** 1853 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1854 * @hw: pointer to the HW structure 1855 * 1856 * Success returns 0, Failure returns 1 1857 * 1858 * A downshift is detected by querying the PHY link health. 1859 **/ 1860 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1861 { 1862 struct e1000_phy_info *phy = &hw->phy; 1863 s32 ret_val; 1864 u16 phy_data, offset, mask; 1865 1866 DEBUGFUNC("e1000_check_downshift_generic"); 1867 1868 switch (phy->type) { 1869 case e1000_phy_m88: 1870 case e1000_phy_gg82563: 1871 case e1000_phy_bm: 1872 case e1000_phy_82578: 1873 offset = M88E1000_PHY_SPEC_STATUS; 1874 mask = M88E1000_PSSR_DOWNSHIFT; 1875 break; 1876 case e1000_phy_igp: 1877 case e1000_phy_igp_2: 1878 case e1000_phy_igp_3: 1879 offset = IGP01E1000_PHY_LINK_HEALTH; 1880 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1881 break; 1882 default: 1883 /* speed downshift not supported */ 1884 phy->speed_downgraded = FALSE; 1885 ret_val = E1000_SUCCESS; 1886 goto out; 1887 } 1888 1889 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1890 1891 if (!ret_val) 1892 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1893 1894 out: 1895 return ret_val; 1896 } 1897 1898 /** 1899 * e1000_check_polarity_m88 - Checks the polarity. 1900 * @hw: pointer to the HW structure 1901 * 1902 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1903 * 1904 * Polarity is determined based on the PHY specific status register. 1905 **/ 1906 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1907 { 1908 struct e1000_phy_info *phy = &hw->phy; 1909 s32 ret_val; 1910 u16 data; 1911 1912 DEBUGFUNC("e1000_check_polarity_m88"); 1913 1914 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1915 1916 if (!ret_val) 1917 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1918 ? e1000_rev_polarity_reversed 1919 : e1000_rev_polarity_normal; 1920 1921 return ret_val; 1922 } 1923 1924 /** 1925 * e1000_check_polarity_igp - Checks the polarity. 1926 * @hw: pointer to the HW structure 1927 * 1928 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1929 * 1930 * Polarity is determined based on the PHY port status register, and the 1931 * current speed (since there is no polarity at 100Mbps). 1932 **/ 1933 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1934 { 1935 struct e1000_phy_info *phy = &hw->phy; 1936 s32 ret_val; 1937 u16 data, offset, mask; 1938 1939 DEBUGFUNC("e1000_check_polarity_igp"); 1940 1941 /* 1942 * Polarity is determined based on the speed of 1943 * our connection. 1944 */ 1945 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1946 if (ret_val) 1947 goto out; 1948 1949 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1950 IGP01E1000_PSSR_SPEED_1000MBPS) { 1951 offset = IGP01E1000_PHY_PCS_INIT_REG; 1952 mask = IGP01E1000_PHY_POLARITY_MASK; 1953 } else { 1954 /* 1955 * This really only applies to 10Mbps since 1956 * there is no polarity for 100Mbps (always 0). 1957 */ 1958 offset = IGP01E1000_PHY_PORT_STATUS; 1959 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1960 } 1961 1962 ret_val = phy->ops.read_reg(hw, offset, &data); 1963 1964 if (!ret_val) 1965 phy->cable_polarity = (data & mask) 1966 ? e1000_rev_polarity_reversed 1967 : e1000_rev_polarity_normal; 1968 1969 out: 1970 return ret_val; 1971 } 1972 1973 /** 1974 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1975 * @hw: pointer to the HW structure 1976 * 1977 * Polarity is determined on the polarity reversal feature being enabled. 1978 **/ 1979 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1980 { 1981 struct e1000_phy_info *phy = &hw->phy; 1982 s32 ret_val; 1983 u16 phy_data, offset, mask; 1984 1985 DEBUGFUNC("e1000_check_polarity_ife"); 1986 1987 /* 1988 * Polarity is determined based on the reversal feature being enabled. 1989 */ 1990 if (phy->polarity_correction) { 1991 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1992 mask = IFE_PESC_POLARITY_REVERSED; 1993 } else { 1994 offset = IFE_PHY_SPECIAL_CONTROL; 1995 mask = IFE_PSC_FORCE_POLARITY; 1996 } 1997 1998 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1999 2000 if (!ret_val) 2001 phy->cable_polarity = (phy_data & mask) 2002 ? e1000_rev_polarity_reversed 2003 : e1000_rev_polarity_normal; 2004 2005 return ret_val; 2006 } 2007 2008 /** 2009 * e1000_wait_autoneg_generic - Wait for auto-neg completion 2010 * @hw: pointer to the HW structure 2011 * 2012 * Waits for auto-negotiation to complete or for the auto-negotiation time 2013 * limit to expire, which ever happens first. 2014 **/ 2015 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 2016 { 2017 s32 ret_val = E1000_SUCCESS; 2018 u16 i, phy_status; 2019 2020 DEBUGFUNC("e1000_wait_autoneg_generic"); 2021 2022 if (!(hw->phy.ops.read_reg)) 2023 return E1000_SUCCESS; 2024 2025 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2026 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2027 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2028 if (ret_val) 2029 break; 2030 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2031 if (ret_val) 2032 break; 2033 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2034 break; 2035 msec_delay(100); 2036 } 2037 2038 /* 2039 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2040 * has completed. 2041 */ 2042 return ret_val; 2043 } 2044 2045 /** 2046 * e1000_phy_has_link_generic - Polls PHY for link 2047 * @hw: pointer to the HW structure 2048 * @iterations: number of times to poll for link 2049 * @usec_interval: delay between polling attempts 2050 * @success: pointer to whether polling was successful or not 2051 * 2052 * Polls the PHY status register for link, 'iterations' number of times. 2053 **/ 2054 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2055 u32 usec_interval, bool *success) 2056 { 2057 s32 ret_val = E1000_SUCCESS; 2058 u16 i, phy_status; 2059 2060 DEBUGFUNC("e1000_phy_has_link_generic"); 2061 2062 if (!(hw->phy.ops.read_reg)) 2063 return E1000_SUCCESS; 2064 2065 for (i = 0; i < iterations; i++) { 2066 /* 2067 * Some PHYs require the PHY_STATUS register to be read 2068 * twice due to the link bit being sticky. No harm doing 2069 * it across the board. 2070 */ 2071 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2072 if (ret_val) 2073 /* 2074 * If the first read fails, another entity may have 2075 * ownership of the resources, wait and try again to 2076 * see if they have relinquished the resources yet. 2077 */ 2078 usec_delay(usec_interval); 2079 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2080 if (ret_val) 2081 break; 2082 if (phy_status & MII_SR_LINK_STATUS) 2083 break; 2084 if (usec_interval >= 1000) 2085 msec_delay_irq(usec_interval/1000); 2086 else 2087 usec_delay(usec_interval); 2088 } 2089 2090 *success = (i < iterations) ? TRUE : FALSE; 2091 2092 return ret_val; 2093 } 2094 2095 /** 2096 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2097 * @hw: pointer to the HW structure 2098 * 2099 * Reads the PHY specific status register to retrieve the cable length 2100 * information. The cable length is determined by averaging the minimum and 2101 * maximum values to get the "average" cable length. The m88 PHY has four 2102 * possible cable length values, which are: 2103 * Register Value Cable Length 2104 * 0 < 50 meters 2105 * 1 50 - 80 meters 2106 * 2 80 - 110 meters 2107 * 3 110 - 140 meters 2108 * 4 > 140 meters 2109 **/ 2110 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2111 { 2112 struct e1000_phy_info *phy = &hw->phy; 2113 s32 ret_val; 2114 u16 phy_data, index; 2115 2116 DEBUGFUNC("e1000_get_cable_length_m88"); 2117 2118 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2119 if (ret_val) 2120 goto out; 2121 2122 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2123 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2124 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2125 ret_val = -E1000_ERR_PHY; 2126 goto out; 2127 } 2128 2129 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2130 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2131 2132 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2133 2134 out: 2135 return ret_val; 2136 } 2137 2138 /** 2139 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2140 * @hw: pointer to the HW structure 2141 * 2142 * The automatic gain control (agc) normalizes the amplitude of the 2143 * received signal, adjusting for the attenuation produced by the 2144 * cable. By reading the AGC registers, which represent the 2145 * combination of coarse and fine gain value, the value can be put 2146 * into a lookup table to obtain the approximate cable length 2147 * for each channel. 2148 **/ 2149 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2150 { 2151 struct e1000_phy_info *phy = &hw->phy; 2152 s32 ret_val = E1000_SUCCESS; 2153 u16 phy_data, i, agc_value = 0; 2154 u16 cur_agc_index, max_agc_index = 0; 2155 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2156 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 2157 {IGP02E1000_PHY_AGC_A, 2158 IGP02E1000_PHY_AGC_B, 2159 IGP02E1000_PHY_AGC_C, 2160 IGP02E1000_PHY_AGC_D}; 2161 2162 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2163 2164 /* Read the AGC registers for all channels */ 2165 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2166 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2167 if (ret_val) 2168 goto out; 2169 2170 /* 2171 * Getting bits 15:9, which represent the combination of 2172 * coarse and fine gain values. The result is a number 2173 * that can be put into the lookup table to obtain the 2174 * approximate cable length. 2175 */ 2176 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2177 IGP02E1000_AGC_LENGTH_MASK; 2178 2179 /* Array index bound check. */ 2180 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2181 (cur_agc_index == 0)) { 2182 ret_val = -E1000_ERR_PHY; 2183 goto out; 2184 } 2185 2186 /* Remove min & max AGC values from calculation. */ 2187 if (e1000_igp_2_cable_length_table[min_agc_index] > 2188 e1000_igp_2_cable_length_table[cur_agc_index]) 2189 min_agc_index = cur_agc_index; 2190 if (e1000_igp_2_cable_length_table[max_agc_index] < 2191 e1000_igp_2_cable_length_table[cur_agc_index]) 2192 max_agc_index = cur_agc_index; 2193 2194 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2195 } 2196 2197 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2198 e1000_igp_2_cable_length_table[max_agc_index]); 2199 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2200 2201 /* Calculate cable length with the error range of +/- 10 meters. */ 2202 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2203 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2204 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2205 2206 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2207 2208 out: 2209 return ret_val; 2210 } 2211 2212 /** 2213 * e1000_get_phy_info_m88 - Retrieve PHY information 2214 * @hw: pointer to the HW structure 2215 * 2216 * Valid for only copper links. Read the PHY status register (sticky read) 2217 * to verify that link is up. Read the PHY special control register to 2218 * determine the polarity and 10base-T extended distance. Read the PHY 2219 * special status register to determine MDI/MDIx and current speed. If 2220 * speed is 1000, then determine cable length, local and remote receiver. 2221 **/ 2222 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2223 { 2224 struct e1000_phy_info *phy = &hw->phy; 2225 s32 ret_val; 2226 u16 phy_data; 2227 bool link; 2228 2229 DEBUGFUNC("e1000_get_phy_info_m88"); 2230 2231 if (phy->media_type != e1000_media_type_copper) { 2232 DEBUGOUT("Phy info is only valid for copper media\n"); 2233 ret_val = -E1000_ERR_CONFIG; 2234 goto out; 2235 } 2236 2237 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2238 if (ret_val) 2239 goto out; 2240 2241 if (!link) { 2242 DEBUGOUT("Phy info is only valid if link is up\n"); 2243 ret_val = -E1000_ERR_CONFIG; 2244 goto out; 2245 } 2246 2247 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2248 if (ret_val) 2249 goto out; 2250 2251 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2252 ? TRUE : FALSE; 2253 2254 ret_val = e1000_check_polarity_m88(hw); 2255 if (ret_val) 2256 goto out; 2257 2258 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2259 if (ret_val) 2260 goto out; 2261 2262 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 2263 2264 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2265 ret_val = hw->phy.ops.get_cable_length(hw); 2266 if (ret_val) 2267 goto out; 2268 2269 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2270 if (ret_val) 2271 goto out; 2272 2273 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2274 ? e1000_1000t_rx_status_ok 2275 : e1000_1000t_rx_status_not_ok; 2276 2277 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2278 ? e1000_1000t_rx_status_ok 2279 : e1000_1000t_rx_status_not_ok; 2280 } else { 2281 /* Set values to "undefined" */ 2282 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2283 phy->local_rx = e1000_1000t_rx_status_undefined; 2284 phy->remote_rx = e1000_1000t_rx_status_undefined; 2285 } 2286 2287 out: 2288 return ret_val; 2289 } 2290 2291 /** 2292 * e1000_get_phy_info_igp - Retrieve igp PHY information 2293 * @hw: pointer to the HW structure 2294 * 2295 * Read PHY status to determine if link is up. If link is up, then 2296 * set/determine 10base-T extended distance and polarity correction. Read 2297 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2298 * determine on the cable length, local and remote receiver. 2299 **/ 2300 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2301 { 2302 struct e1000_phy_info *phy = &hw->phy; 2303 s32 ret_val; 2304 u16 data; 2305 bool link; 2306 2307 DEBUGFUNC("e1000_get_phy_info_igp"); 2308 2309 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2310 if (ret_val) 2311 goto out; 2312 2313 if (!link) { 2314 DEBUGOUT("Phy info is only valid if link is up\n"); 2315 ret_val = -E1000_ERR_CONFIG; 2316 goto out; 2317 } 2318 2319 phy->polarity_correction = TRUE; 2320 2321 ret_val = e1000_check_polarity_igp(hw); 2322 if (ret_val) 2323 goto out; 2324 2325 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2326 if (ret_val) 2327 goto out; 2328 2329 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 2330 2331 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2332 IGP01E1000_PSSR_SPEED_1000MBPS) { 2333 ret_val = phy->ops.get_cable_length(hw); 2334 if (ret_val) 2335 goto out; 2336 2337 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2338 if (ret_val) 2339 goto out; 2340 2341 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2342 ? e1000_1000t_rx_status_ok 2343 : e1000_1000t_rx_status_not_ok; 2344 2345 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2346 ? e1000_1000t_rx_status_ok 2347 : e1000_1000t_rx_status_not_ok; 2348 } else { 2349 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2350 phy->local_rx = e1000_1000t_rx_status_undefined; 2351 phy->remote_rx = e1000_1000t_rx_status_undefined; 2352 } 2353 2354 out: 2355 return ret_val; 2356 } 2357 2358 /** 2359 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2360 * @hw: pointer to the HW structure 2361 * 2362 * Populates "phy" structure with various feature states. 2363 **/ 2364 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2365 { 2366 struct e1000_phy_info *phy = &hw->phy; 2367 s32 ret_val; 2368 u16 data; 2369 bool link; 2370 2371 DEBUGFUNC("e1000_get_phy_info_ife"); 2372 2373 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2374 if (ret_val) 2375 goto out; 2376 2377 if (!link) { 2378 DEBUGOUT("Phy info is only valid if link is up\n"); 2379 ret_val = -E1000_ERR_CONFIG; 2380 goto out; 2381 } 2382 2383 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2384 if (ret_val) 2385 goto out; 2386 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2387 ? FALSE : TRUE; 2388 2389 if (phy->polarity_correction) { 2390 ret_val = e1000_check_polarity_ife(hw); 2391 if (ret_val) 2392 goto out; 2393 } else { 2394 /* Polarity is forced */ 2395 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2396 ? e1000_rev_polarity_reversed 2397 : e1000_rev_polarity_normal; 2398 } 2399 2400 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2401 if (ret_val) 2402 goto out; 2403 2404 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 2405 2406 /* The following parameters are undefined for 10/100 operation. */ 2407 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2408 phy->local_rx = e1000_1000t_rx_status_undefined; 2409 phy->remote_rx = e1000_1000t_rx_status_undefined; 2410 2411 out: 2412 return ret_val; 2413 } 2414 2415 /** 2416 * e1000_phy_sw_reset_generic - PHY software reset 2417 * @hw: pointer to the HW structure 2418 * 2419 * Does a software reset of the PHY by reading the PHY control register and 2420 * setting/write the control register reset bit to the PHY. 2421 **/ 2422 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2423 { 2424 s32 ret_val = E1000_SUCCESS; 2425 u16 phy_ctrl; 2426 2427 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2428 2429 if (!(hw->phy.ops.read_reg)) 2430 goto out; 2431 2432 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2433 if (ret_val) 2434 goto out; 2435 2436 phy_ctrl |= MII_CR_RESET; 2437 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2438 if (ret_val) 2439 goto out; 2440 2441 usec_delay(1); 2442 2443 out: 2444 return ret_val; 2445 } 2446 2447 /** 2448 * e1000_phy_hw_reset_generic - PHY hardware reset 2449 * @hw: pointer to the HW structure 2450 * 2451 * Verify the reset block is not blocking us from resetting. Acquire 2452 * semaphore (if necessary) and read/set/write the device control reset 2453 * bit in the PHY. Wait the appropriate delay time for the device to 2454 * reset and release the semaphore (if necessary). 2455 **/ 2456 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2457 { 2458 struct e1000_phy_info *phy = &hw->phy; 2459 s32 ret_val = E1000_SUCCESS; 2460 u32 ctrl; 2461 2462 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2463 2464 ret_val = phy->ops.check_reset_block(hw); 2465 if (ret_val) { 2466 ret_val = E1000_SUCCESS; 2467 goto out; 2468 } 2469 2470 ret_val = phy->ops.acquire(hw); 2471 if (ret_val) 2472 goto out; 2473 2474 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2475 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2476 E1000_WRITE_FLUSH(hw); 2477 2478 usec_delay(phy->reset_delay_us); 2479 2480 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2481 E1000_WRITE_FLUSH(hw); 2482 2483 usec_delay(150); 2484 2485 phy->ops.release(hw); 2486 2487 ret_val = phy->ops.get_cfg_done(hw); 2488 2489 out: 2490 return ret_val; 2491 } 2492 2493 /** 2494 * e1000_get_cfg_done_generic - Generic configuration done 2495 * @hw: pointer to the HW structure 2496 * 2497 * Generic function to wait 10 milli-seconds for configuration to complete 2498 * and return success. 2499 **/ 2500 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2501 { 2502 DEBUGFUNC("e1000_get_cfg_done_generic"); 2503 2504 msec_delay_irq(10); 2505 2506 return E1000_SUCCESS; 2507 } 2508 2509 /** 2510 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2511 * @hw: pointer to the HW structure 2512 * 2513 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2514 **/ 2515 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2516 { 2517 DEBUGOUT("Running IGP 3 PHY init script\n"); 2518 2519 /* PHY init IGP 3 */ 2520 /* Enable rise/fall, 10-mode work in class-A */ 2521 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2522 /* Remove all caps from Replica path filter */ 2523 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2524 /* Bias trimming for ADC, AFE and Driver (Default) */ 2525 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2526 /* Increase Hybrid poly bias */ 2527 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2528 /* Add 4% to Tx amplitude in Gig mode */ 2529 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2530 /* Disable trimming (TTT) */ 2531 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2532 /* Poly DC correction to 94.6% + 2% for all channels */ 2533 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2534 /* ABS DC correction to 95.9% */ 2535 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2536 /* BG temp curve trim */ 2537 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2538 /* Increasing ADC OPAMP stage 1 currents to max */ 2539 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2540 /* Force 1000 ( required for enabling PHY regs configuration) */ 2541 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2542 /* Set upd_freq to 6 */ 2543 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2544 /* Disable NPDFE */ 2545 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2546 /* Disable adaptive fixed FFE (Default) */ 2547 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2548 /* Enable FFE hysteresis */ 2549 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2550 /* Fixed FFE for short cable lengths */ 2551 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2552 /* Fixed FFE for medium cable lengths */ 2553 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2554 /* Fixed FFE for long cable lengths */ 2555 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2556 /* Enable Adaptive Clip Threshold */ 2557 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2558 /* AHT reset limit to 1 */ 2559 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2560 /* Set AHT master delay to 127 msec */ 2561 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2562 /* Set scan bits for AHT */ 2563 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2564 /* Set AHT Preset bits */ 2565 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2566 /* Change integ_factor of channel A to 3 */ 2567 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2568 /* Change prop_factor of channels BCD to 8 */ 2569 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2570 /* Change cg_icount + enable integbp for channels BCD */ 2571 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2572 /* 2573 * Change cg_icount + enable integbp + change prop_factor_master 2574 * to 8 for channel A 2575 */ 2576 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2577 /* Disable AHT in Slave mode on channel A */ 2578 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2579 /* 2580 * Enable LPLU and disable AN to 1000 in non-D0a states, 2581 * Enable SPD+B2B 2582 */ 2583 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2584 /* Enable restart AN on an1000_dis change */ 2585 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2586 /* Enable wh_fifo read clock in 10/100 modes */ 2587 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2588 /* Restart AN, Speed selection is 1000 */ 2589 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2590 2591 return E1000_SUCCESS; 2592 } 2593 2594 /** 2595 * e1000_get_phy_type_from_id - Get PHY type from id 2596 * @phy_id: phy_id read from the phy 2597 * 2598 * Returns the phy type from the id. 2599 **/ 2600 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2601 { 2602 enum e1000_phy_type phy_type = e1000_phy_unknown; 2603 2604 switch (phy_id) { 2605 case M88E1000_I_PHY_ID: 2606 case M88E1000_E_PHY_ID: 2607 case M88E1111_I_PHY_ID: 2608 case M88E1011_I_PHY_ID: 2609 phy_type = e1000_phy_m88; 2610 break; 2611 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2612 phy_type = e1000_phy_igp_2; 2613 break; 2614 case GG82563_E_PHY_ID: 2615 phy_type = e1000_phy_gg82563; 2616 break; 2617 case IGP03E1000_E_PHY_ID: 2618 phy_type = e1000_phy_igp_3; 2619 break; 2620 case IFE_E_PHY_ID: 2621 case IFE_PLUS_E_PHY_ID: 2622 case IFE_C_E_PHY_ID: 2623 phy_type = e1000_phy_ife; 2624 break; 2625 case BME1000_E_PHY_ID: 2626 case BME1000_E_PHY_ID_R2: 2627 phy_type = e1000_phy_bm; 2628 break; 2629 case I82578_E_PHY_ID: 2630 phy_type = e1000_phy_82578; 2631 break; 2632 case I82577_E_PHY_ID: 2633 phy_type = e1000_phy_82577; 2634 break; 2635 case I82580_I_PHY_ID: 2636 phy_type = e1000_phy_82580; 2637 break; 2638 default: 2639 phy_type = e1000_phy_unknown; 2640 break; 2641 } 2642 return phy_type; 2643 } 2644 2645 /** 2646 * e1000_determine_phy_address - Determines PHY address. 2647 * @hw: pointer to the HW structure 2648 * 2649 * This uses a trial and error method to loop through possible PHY 2650 * addresses. It tests each by reading the PHY ID registers and 2651 * checking for a match. 2652 **/ 2653 s32 e1000_determine_phy_address(struct e1000_hw *hw) 2654 { 2655 s32 ret_val = -E1000_ERR_PHY_TYPE; 2656 u32 phy_addr = 0; 2657 u32 i; 2658 enum e1000_phy_type phy_type = e1000_phy_unknown; 2659 2660 hw->phy.id = phy_type; 2661 2662 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2663 hw->phy.addr = phy_addr; 2664 i = 0; 2665 2666 do { 2667 e1000_get_phy_id(hw); 2668 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2669 2670 /* 2671 * If phy_type is valid, break - we found our 2672 * PHY address 2673 */ 2674 if (phy_type != e1000_phy_unknown) { 2675 ret_val = E1000_SUCCESS; 2676 goto out; 2677 } 2678 msec_delay(1); 2679 i++; 2680 } while (i < 10); 2681 } 2682 2683 out: 2684 return ret_val; 2685 } 2686 2687 /** 2688 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2689 * @page: page to access 2690 * 2691 * Returns the phy address for the page requested. 2692 **/ 2693 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2694 { 2695 u32 phy_addr = 2; 2696 2697 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2698 phy_addr = 1; 2699 2700 return phy_addr; 2701 } 2702 2703 /** 2704 * e1000_write_phy_reg_bm - Write BM PHY register 2705 * @hw: pointer to the HW structure 2706 * @offset: register offset to write to 2707 * @data: data to write at register offset 2708 * 2709 * Acquires semaphore, if necessary, then writes the data to PHY register 2710 * at the offset. Release any acquired semaphores before exiting. 2711 **/ 2712 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2713 { 2714 s32 ret_val; 2715 u32 page_select = 0; 2716 u32 page = offset >> IGP_PAGE_SHIFT; 2717 u32 page_shift = 0; 2718 2719 DEBUGFUNC("e1000_write_phy_reg_bm"); 2720 2721 ret_val = hw->phy.ops.acquire(hw); 2722 if (ret_val) 2723 return ret_val; 2724 2725 /* Page 800 works differently than the rest so it has its own func */ 2726 if (page == BM_WUC_PAGE) { 2727 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2728 FALSE); 2729 goto out; 2730 } 2731 2732 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2733 2734 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2735 /* 2736 * Page select is register 31 for phy address 1 and 22 for 2737 * phy address 2 and 3. Page select is shifted only for 2738 * phy address 1. 2739 */ 2740 if (hw->phy.addr == 1) { 2741 page_shift = IGP_PAGE_SHIFT; 2742 page_select = IGP01E1000_PHY_PAGE_SELECT; 2743 } else { 2744 page_shift = 0; 2745 page_select = BM_PHY_PAGE_SELECT; 2746 } 2747 2748 /* Page is shifted left, PHY expects (page x 32) */ 2749 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2750 (page << page_shift)); 2751 if (ret_val) 2752 goto out; 2753 } 2754 2755 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2756 data); 2757 2758 out: 2759 hw->phy.ops.release(hw); 2760 return ret_val; 2761 } 2762 2763 /** 2764 * e1000_read_phy_reg_bm - Read BM PHY register 2765 * @hw: pointer to the HW structure 2766 * @offset: register offset to be read 2767 * @data: pointer to the read data 2768 * 2769 * Acquires semaphore, if necessary, then reads the PHY register at offset 2770 * and storing the retrieved information in data. Release any acquired 2771 * semaphores before exiting. 2772 **/ 2773 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2774 { 2775 s32 ret_val; 2776 u32 page_select = 0; 2777 u32 page = offset >> IGP_PAGE_SHIFT; 2778 u32 page_shift = 0; 2779 2780 DEBUGFUNC("e1000_read_phy_reg_bm"); 2781 2782 ret_val = hw->phy.ops.acquire(hw); 2783 if (ret_val) 2784 return ret_val; 2785 2786 /* Page 800 works differently than the rest so it has its own func */ 2787 if (page == BM_WUC_PAGE) { 2788 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2789 TRUE); 2790 goto out; 2791 } 2792 2793 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2794 2795 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2796 /* 2797 * Page select is register 31 for phy address 1 and 22 for 2798 * phy address 2 and 3. Page select is shifted only for 2799 * phy address 1. 2800 */ 2801 if (hw->phy.addr == 1) { 2802 page_shift = IGP_PAGE_SHIFT; 2803 page_select = IGP01E1000_PHY_PAGE_SELECT; 2804 } else { 2805 page_shift = 0; 2806 page_select = BM_PHY_PAGE_SELECT; 2807 } 2808 2809 /* Page is shifted left, PHY expects (page x 32) */ 2810 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2811 (page << page_shift)); 2812 if (ret_val) 2813 goto out; 2814 } 2815 2816 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2817 data); 2818 out: 2819 hw->phy.ops.release(hw); 2820 return ret_val; 2821 } 2822 2823 /** 2824 * e1000_read_phy_reg_bm2 - Read BM PHY register 2825 * @hw: pointer to the HW structure 2826 * @offset: register offset to be read 2827 * @data: pointer to the read data 2828 * 2829 * Acquires semaphore, if necessary, then reads the PHY register at offset 2830 * and storing the retrieved information in data. Release any acquired 2831 * semaphores before exiting. 2832 **/ 2833 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2834 { 2835 s32 ret_val; 2836 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2837 2838 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2839 2840 ret_val = hw->phy.ops.acquire(hw); 2841 if (ret_val) 2842 return ret_val; 2843 2844 /* Page 800 works differently than the rest so it has its own func */ 2845 if (page == BM_WUC_PAGE) { 2846 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2847 TRUE); 2848 goto out; 2849 } 2850 2851 hw->phy.addr = 1; 2852 2853 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2854 2855 /* Page is shifted left, PHY expects (page x 32) */ 2856 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2857 page); 2858 2859 if (ret_val) 2860 goto out; 2861 } 2862 2863 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2864 data); 2865 out: 2866 hw->phy.ops.release(hw); 2867 return ret_val; 2868 } 2869 2870 /** 2871 * e1000_write_phy_reg_bm2 - Write BM PHY register 2872 * @hw: pointer to the HW structure 2873 * @offset: register offset to write to 2874 * @data: data to write at register offset 2875 * 2876 * Acquires semaphore, if necessary, then writes the data to PHY register 2877 * at the offset. Release any acquired semaphores before exiting. 2878 **/ 2879 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2880 { 2881 s32 ret_val; 2882 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2883 2884 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2885 2886 ret_val = hw->phy.ops.acquire(hw); 2887 if (ret_val) 2888 return ret_val; 2889 2890 /* Page 800 works differently than the rest so it has its own func */ 2891 if (page == BM_WUC_PAGE) { 2892 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2893 FALSE); 2894 goto out; 2895 } 2896 2897 hw->phy.addr = 1; 2898 2899 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2900 /* Page is shifted left, PHY expects (page x 32) */ 2901 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2902 page); 2903 2904 if (ret_val) 2905 goto out; 2906 } 2907 2908 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2909 data); 2910 2911 out: 2912 hw->phy.ops.release(hw); 2913 return ret_val; 2914 } 2915 2916 /** 2917 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2918 * @hw: pointer to the HW structure 2919 * @offset: register offset to be read or written 2920 * @data: pointer to the data to read or write 2921 * @read: determines if operation is read or write 2922 * 2923 * Acquires semaphore, if necessary, then reads the PHY register at offset 2924 * and storing the retrieved information in data. Release any acquired 2925 * semaphores before exiting. Note that procedure to read the wakeup 2926 * registers are different. It works as such: 2927 * 1) Set page 769, register 17, bit 2 = 1 2928 * 2) Set page to 800 for host (801 if we were manageability) 2929 * 3) Write the address using the address opcode (0x11) 2930 * 4) Read or write the data using the data opcode (0x12) 2931 * 5) Restore 769_17.2 to its original value 2932 * 2933 * Assumes semaphore already acquired. 2934 **/ 2935 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2936 u16 *data, bool read) 2937 { 2938 s32 ret_val; 2939 u16 reg = BM_PHY_REG_NUM(offset); 2940 u16 phy_reg = 0; 2941 2942 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 2943 2944 /* Gig must be disabled for MDIO accesses to page 800 */ 2945 if ((hw->mac.type == e1000_pchlan) && 2946 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2947 DEBUGOUT("Attempting to access page 800 while gig enabled.\n"); 2948 2949 /* All operations in this function are phy address 1 */ 2950 hw->phy.addr = 1; 2951 2952 /* Set page 769 */ 2953 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2954 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2955 2956 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2957 if (ret_val) { 2958 DEBUGOUT("Could not read PHY page 769\n"); 2959 goto out; 2960 } 2961 2962 /* First clear bit 4 to avoid a power state change */ 2963 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2964 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2965 if (ret_val) { 2966 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 2967 goto out; 2968 } 2969 2970 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2971 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2972 phy_reg | BM_WUC_ENABLE_BIT); 2973 if (ret_val) { 2974 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 2975 goto out; 2976 } 2977 2978 /* Select page 800 */ 2979 ret_val = e1000_write_phy_reg_mdic(hw, 2980 IGP01E1000_PHY_PAGE_SELECT, 2981 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2982 2983 /* Write the page 800 offset value using opcode 0x11 */ 2984 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2985 if (ret_val) { 2986 DEBUGOUT("Could not write address opcode to page 800\n"); 2987 goto out; 2988 } 2989 2990 if (read) { 2991 /* Read the page 800 value using opcode 0x12 */ 2992 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2993 data); 2994 } else { 2995 /* Write the page 800 value using opcode 0x12 */ 2996 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2997 *data); 2998 } 2999 3000 if (ret_val) { 3001 DEBUGOUT("Could not access data value from page 800\n"); 3002 goto out; 3003 } 3004 3005 /* 3006 * Restore 769_17.2 to its original value 3007 * Set page 769 3008 */ 3009 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3010 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3011 3012 /* Clear 769_17.2 */ 3013 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3014 if (ret_val) { 3015 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 3016 goto out; 3017 } 3018 3019 out: 3020 return ret_val; 3021 } 3022 3023 /** 3024 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3025 * @hw: pointer to the HW structure 3026 * 3027 * In the case of a PHY power down to save power, or to turn off link during a 3028 * driver unload, or wake on lan is not enabled, restore the link to previous 3029 * settings. 3030 **/ 3031 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3032 { 3033 u16 mii_reg = 0; 3034 3035 /* The PHY will retain its settings across a power down/up cycle */ 3036 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3037 mii_reg &= ~MII_CR_POWER_DOWN; 3038 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3039 } 3040 3041 /** 3042 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3043 * @hw: pointer to the HW structure 3044 * 3045 * In the case of a PHY power down to save power, or to turn off link during a 3046 * driver unload, or wake on lan is not enabled, restore the link to previous 3047 * settings. 3048 **/ 3049 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3050 { 3051 u16 mii_reg = 0; 3052 3053 /* The PHY will retain its settings across a power down/up cycle */ 3054 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3055 mii_reg |= MII_CR_POWER_DOWN; 3056 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3057 msec_delay(1); 3058 } 3059 3060 /** 3061 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 3062 * @hw: pointer to the HW structure 3063 * @slow: TRUE for slow mode, FALSE for normal mode 3064 * 3065 * Assumes semaphore already acquired. 3066 **/ 3067 s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) 3068 { 3069 s32 ret_val = E1000_SUCCESS; 3070 u16 data = 0; 3071 3072 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ 3073 hw->phy.addr = 1; 3074 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3075 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3076 if (ret_val) 3077 goto out; 3078 3079 ret_val = e1000_write_phy_reg_mdic(hw, BM_CS_CTRL1, 3080 (0x2180 | (slow << 10))); 3081 if (ret_val) 3082 goto out; 3083 3084 /* dummy read when reverting to fast mode - throw away result */ 3085 if (!slow) 3086 ret_val = e1000_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); 3087 3088 out: 3089 return ret_val; 3090 } 3091 3092 /** 3093 * __e1000_read_phy_reg_hv - Read HV PHY register 3094 * @hw: pointer to the HW structure 3095 * @offset: register offset to be read 3096 * @data: pointer to the read data 3097 * @locked: semaphore has already been acquired or not 3098 * 3099 * Acquires semaphore, if necessary, then reads the PHY register at offset 3100 * and stores the retrieved information in data. Release any acquired 3101 * semaphore before exiting. 3102 **/ 3103 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3104 bool locked) 3105 { 3106 s32 ret_val; 3107 u16 page = BM_PHY_REG_PAGE(offset); 3108 u16 reg = BM_PHY_REG_NUM(offset); 3109 bool in_slow_mode = FALSE; 3110 3111 DEBUGFUNC("e1000_read_phy_reg_hv"); 3112 3113 if (!locked) { 3114 ret_val = hw->phy.ops.acquire(hw); 3115 if (ret_val) 3116 return ret_val; 3117 } 3118 3119 /* Workaround failure in MDIO access while cable is disconnected */ 3120 if ((hw->phy.type == e1000_phy_82577) && 3121 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 3122 ret_val = e1000_set_mdio_slow_mode_hv(hw, TRUE); 3123 if (ret_val) 3124 goto out; 3125 3126 in_slow_mode = TRUE; 3127 } 3128 3129 /* Page 800 works differently than the rest so it has its own func */ 3130 if (page == BM_WUC_PAGE) { 3131 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3132 data, TRUE); 3133 goto out; 3134 } 3135 3136 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3137 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3138 data, TRUE); 3139 goto out; 3140 } 3141 3142 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3143 3144 if (page == HV_INTC_FC_PAGE_START) 3145 page = 0; 3146 3147 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3148 u32 phy_addr = hw->phy.addr; 3149 3150 hw->phy.addr = 1; 3151 3152 /* Page is shifted left, PHY expects (page x 32) */ 3153 ret_val = e1000_write_phy_reg_mdic(hw, 3154 IGP01E1000_PHY_PAGE_SELECT, 3155 (page << IGP_PAGE_SHIFT)); 3156 hw->phy.addr = phy_addr; 3157 3158 if (ret_val) 3159 goto out; 3160 } 3161 3162 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3163 data); 3164 out: 3165 /* Revert to MDIO fast mode, if applicable */ 3166 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 3167 ret_val |= e1000_set_mdio_slow_mode_hv(hw, FALSE); 3168 3169 if (!locked) 3170 hw->phy.ops.release(hw); 3171 3172 return ret_val; 3173 } 3174 3175 /** 3176 * e1000_read_phy_reg_hv - Read HV PHY register 3177 * @hw: pointer to the HW structure 3178 * @offset: register offset to be read 3179 * @data: pointer to the read data 3180 * 3181 * Acquires semaphore then reads the PHY register at offset and stores 3182 * the retrieved information in data. Release the acquired semaphore 3183 * before exiting. 3184 **/ 3185 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3186 { 3187 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE); 3188 } 3189 3190 /** 3191 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3192 * @hw: pointer to the HW structure 3193 * @offset: register offset to be read 3194 * @data: pointer to the read data 3195 * 3196 * Reads the PHY register at offset and stores the retrieved information 3197 * in data. Assumes semaphore already acquired. 3198 **/ 3199 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3200 { 3201 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE); 3202 } 3203 3204 /** 3205 * __e1000_write_phy_reg_hv - Write HV PHY register 3206 * @hw: pointer to the HW structure 3207 * @offset: register offset to write to 3208 * @data: data to write at register offset 3209 * @locked: semaphore has already been acquired or not 3210 * 3211 * Acquires semaphore, if necessary, then writes the data to PHY register 3212 * at the offset. Release any acquired semaphores before exiting. 3213 **/ 3214 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3215 bool locked) 3216 { 3217 s32 ret_val; 3218 u16 page = BM_PHY_REG_PAGE(offset); 3219 u16 reg = BM_PHY_REG_NUM(offset); 3220 bool in_slow_mode = FALSE; 3221 3222 DEBUGFUNC("e1000_write_phy_reg_hv"); 3223 3224 if (!locked) { 3225 ret_val = hw->phy.ops.acquire(hw); 3226 if (ret_val) 3227 return ret_val; 3228 } 3229 3230 /* Workaround failure in MDIO access while cable is disconnected */ 3231 if ((hw->phy.type == e1000_phy_82577) && 3232 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 3233 ret_val = e1000_set_mdio_slow_mode_hv(hw, TRUE); 3234 if (ret_val) 3235 goto out; 3236 3237 in_slow_mode = TRUE; 3238 } 3239 3240 /* Page 800 works differently than the rest so it has its own func */ 3241 if (page == BM_WUC_PAGE) { 3242 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3243 &data, FALSE); 3244 goto out; 3245 } 3246 3247 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3248 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3249 &data, FALSE); 3250 goto out; 3251 } 3252 3253 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3254 3255 if (page == HV_INTC_FC_PAGE_START) 3256 page = 0; 3257 3258 /* 3259 * Workaround MDIO accesses being disabled after entering IEEE Power 3260 * Down (whenever bit 11 of the PHY Control register is set) 3261 */ 3262 if ((hw->phy.type == e1000_phy_82578) && 3263 (hw->phy.revision >= 1) && 3264 (hw->phy.addr == 2) && 3265 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 3266 (data & (1 << 11))) { 3267 u16 data2 = 0x7EFF; 3268 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 3269 &data2, FALSE); 3270 if (ret_val) 3271 goto out; 3272 } 3273 3274 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3275 u32 phy_addr = hw->phy.addr; 3276 3277 hw->phy.addr = 1; 3278 3279 /* Page is shifted left, PHY expects (page x 32) */ 3280 ret_val = e1000_write_phy_reg_mdic(hw, 3281 IGP01E1000_PHY_PAGE_SELECT, 3282 (page << IGP_PAGE_SHIFT)); 3283 hw->phy.addr = phy_addr; 3284 3285 if (ret_val) 3286 goto out; 3287 } 3288 3289 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3290 data); 3291 3292 out: 3293 /* Revert to MDIO fast mode, if applicable */ 3294 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 3295 ret_val |= e1000_set_mdio_slow_mode_hv(hw, FALSE); 3296 3297 if (!locked) 3298 hw->phy.ops.release(hw); 3299 3300 return ret_val; 3301 } 3302 3303 /** 3304 * e1000_write_phy_reg_hv - Write HV PHY register 3305 * @hw: pointer to the HW structure 3306 * @offset: register offset to write to 3307 * @data: data to write at register offset 3308 * 3309 * Acquires semaphore then writes the data to PHY register at the offset. 3310 * Release the acquired semaphores before exiting. 3311 **/ 3312 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3313 { 3314 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE); 3315 } 3316 3317 /** 3318 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3319 * @hw: pointer to the HW structure 3320 * @offset: register offset to write to 3321 * @data: data to write at register offset 3322 * 3323 * Writes the data to PHY register at the offset. Assumes semaphore 3324 * already acquired. 3325 **/ 3326 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3327 { 3328 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE); 3329 } 3330 3331 /** 3332 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3333 * @page: page to be accessed 3334 **/ 3335 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3336 { 3337 u32 phy_addr = 2; 3338 3339 if (page >= HV_INTC_FC_PAGE_START) 3340 phy_addr = 1; 3341 3342 return phy_addr; 3343 } 3344 3345 /** 3346 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3347 * @hw: pointer to the HW structure 3348 * @offset: register offset to be read or written 3349 * @data: pointer to the data to be read or written 3350 * @read: determines if operation is read or written 3351 * 3352 * Reads the PHY register at offset and stores the retreived information 3353 * in data. Assumes semaphore already acquired. Note that the procedure 3354 * to read these regs uses the address port and data port to read/write. 3355 **/ 3356 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3357 u16 *data, bool read) 3358 { 3359 s32 ret_val; 3360 u32 addr_reg = 0; 3361 u32 data_reg = 0; 3362 3363 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3364 3365 /* This takes care of the difference with desktop vs mobile phy */ 3366 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3367 I82578_ADDR_REG : I82577_ADDR_REG; 3368 data_reg = addr_reg + 1; 3369 3370 /* All operations in this function are phy address 2 */ 3371 hw->phy.addr = 2; 3372 3373 /* masking with 0x3F to remove the page from offset */ 3374 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3375 if (ret_val) { 3376 DEBUGOUT("Could not write PHY the HV address register\n"); 3377 goto out; 3378 } 3379 3380 /* Read or write the data value next */ 3381 if (read) 3382 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3383 else 3384 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3385 3386 if (ret_val) { 3387 DEBUGOUT("Could not read data value from HV data register\n"); 3388 goto out; 3389 } 3390 3391 out: 3392 return ret_val; 3393 } 3394 3395 /** 3396 * e1000_link_stall_workaround_hv - Si workaround 3397 * @hw: pointer to the HW structure 3398 * 3399 * This function works around a Si bug where the link partner can get 3400 * a link up indication before the PHY does. If small packets are sent 3401 * by the link partner they can be placed in the packet buffer without 3402 * being properly accounted for by the PHY and will stall preventing 3403 * further packets from being received. The workaround is to clear the 3404 * packet buffer after the PHY detects link up. 3405 **/ 3406 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3407 { 3408 s32 ret_val = E1000_SUCCESS; 3409 u16 data; 3410 3411 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3412 3413 if (hw->phy.type != e1000_phy_82578) 3414 goto out; 3415 3416 /* Do not apply workaround if in PHY loopback bit 14 set */ 3417 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3418 if (data & PHY_CONTROL_LB) 3419 goto out; 3420 3421 /* check if link is up and at 1Gbps */ 3422 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3423 if (ret_val) 3424 goto out; 3425 3426 data &= BM_CS_STATUS_LINK_UP | 3427 BM_CS_STATUS_RESOLVED | 3428 BM_CS_STATUS_SPEED_MASK; 3429 3430 if (data != (BM_CS_STATUS_LINK_UP | 3431 BM_CS_STATUS_RESOLVED | 3432 BM_CS_STATUS_SPEED_1000)) 3433 goto out; 3434 3435 msec_delay(200); 3436 3437 /* flush the packets in the fifo buffer */ 3438 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3439 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3440 HV_MUX_DATA_CTRL_FORCE_SPEED); 3441 if (ret_val) 3442 goto out; 3443 3444 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3445 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3446 3447 out: 3448 return ret_val; 3449 } 3450 3451 /** 3452 * e1000_check_polarity_82577 - Checks the polarity. 3453 * @hw: pointer to the HW structure 3454 * 3455 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3456 * 3457 * Polarity is determined based on the PHY specific status register. 3458 **/ 3459 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3460 { 3461 struct e1000_phy_info *phy = &hw->phy; 3462 s32 ret_val; 3463 u16 data; 3464 3465 DEBUGFUNC("e1000_check_polarity_82577"); 3466 3467 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3468 3469 if (!ret_val) 3470 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3471 ? e1000_rev_polarity_reversed 3472 : e1000_rev_polarity_normal; 3473 3474 return ret_val; 3475 } 3476 3477 /** 3478 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3479 * @hw: pointer to the HW structure 3480 * 3481 * Calls the PHY setup function to force speed and duplex. Clears the 3482 * auto-crossover to force MDI manually. Waits for link and returns 3483 * successful if link up is successful, else -E1000_ERR_PHY (-2). 3484 **/ 3485 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3486 { 3487 struct e1000_phy_info *phy = &hw->phy; 3488 s32 ret_val; 3489 u16 phy_data; 3490 bool link; 3491 3492 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3493 3494 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3495 if (ret_val) 3496 goto out; 3497 3498 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3499 3500 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3501 if (ret_val) 3502 goto out; 3503 3504 /* 3505 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI 3506 * forced whenever speed and duplex are forced. 3507 */ 3508 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 3509 if (ret_val) 3510 goto out; 3511 3512 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; 3513 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; 3514 3515 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 3516 if (ret_val) 3517 goto out; 3518 3519 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data); 3520 3521 usec_delay(1); 3522 3523 if (phy->autoneg_wait_to_complete) { 3524 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3525 3526 ret_val = e1000_phy_has_link_generic(hw, 3527 PHY_FORCE_LIMIT, 3528 100000, 3529 &link); 3530 if (ret_val) 3531 goto out; 3532 3533 if (!link) 3534 DEBUGOUT("Link taking longer than expected.\n"); 3535 3536 /* Try once more */ 3537 ret_val = e1000_phy_has_link_generic(hw, 3538 PHY_FORCE_LIMIT, 3539 100000, 3540 &link); 3541 if (ret_val) 3542 goto out; 3543 } 3544 3545 out: 3546 return ret_val; 3547 } 3548 3549 /** 3550 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3551 * @hw: pointer to the HW structure 3552 * 3553 * Read PHY status to determine if link is up. If link is up, then 3554 * set/determine 10base-T extended distance and polarity correction. Read 3555 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3556 * determine on the cable length, local and remote receiver. 3557 **/ 3558 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3559 { 3560 struct e1000_phy_info *phy = &hw->phy; 3561 s32 ret_val; 3562 u16 data; 3563 bool link; 3564 3565 DEBUGFUNC("e1000_get_phy_info_82577"); 3566 3567 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3568 if (ret_val) 3569 goto out; 3570 3571 if (!link) { 3572 DEBUGOUT("Phy info is only valid if link is up\n"); 3573 ret_val = -E1000_ERR_CONFIG; 3574 goto out; 3575 } 3576 3577 phy->polarity_correction = TRUE; 3578 3579 ret_val = e1000_check_polarity_82577(hw); 3580 if (ret_val) 3581 goto out; 3582 3583 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3584 if (ret_val) 3585 goto out; 3586 3587 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE; 3588 3589 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3590 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3591 ret_val = hw->phy.ops.get_cable_length(hw); 3592 if (ret_val) 3593 goto out; 3594 3595 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3596 if (ret_val) 3597 goto out; 3598 3599 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3600 ? e1000_1000t_rx_status_ok 3601 : e1000_1000t_rx_status_not_ok; 3602 3603 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3604 ? e1000_1000t_rx_status_ok 3605 : e1000_1000t_rx_status_not_ok; 3606 } else { 3607 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3608 phy->local_rx = e1000_1000t_rx_status_undefined; 3609 phy->remote_rx = e1000_1000t_rx_status_undefined; 3610 } 3611 3612 out: 3613 return ret_val; 3614 } 3615 3616 /** 3617 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3618 * @hw: pointer to the HW structure 3619 * 3620 * Reads the diagnostic status register and verifies result is valid before 3621 * placing it in the phy_cable_length field. 3622 **/ 3623 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3624 { 3625 struct e1000_phy_info *phy = &hw->phy; 3626 s32 ret_val; 3627 u16 phy_data, length; 3628 3629 DEBUGFUNC("e1000_get_cable_length_82577"); 3630 3631 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3632 if (ret_val) 3633 goto out; 3634 3635 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3636 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3637 3638 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3639 ret_val = -E1000_ERR_PHY; 3640 3641 phy->cable_length = length; 3642 3643 out: 3644 return ret_val; 3645 } 3646