1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = 46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = 52 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 53 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 54 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 55 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 56 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 57 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 58 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 59 104, 109, 114, 118, 121, 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.read_reg = e1000_null_read_reg; 86 phy->ops.read_reg_locked = e1000_null_read_reg; 87 phy->ops.release = e1000_null_phy_generic; 88 phy->ops.reset = e1000_null_ops_generic; 89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 91 phy->ops.write_reg = e1000_null_write_reg; 92 phy->ops.write_reg_locked = e1000_null_write_reg; 93 phy->ops.power_up = e1000_null_phy_generic; 94 phy->ops.power_down = e1000_null_phy_generic; 95 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 96 } 97 98 /** 99 * e1000_null_read_reg - No-op function, return 0 100 * @hw: pointer to the HW structure 101 **/ 102 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 103 { 104 DEBUGFUNC("e1000_null_read_reg"); 105 return E1000_SUCCESS; 106 } 107 108 /** 109 * e1000_null_phy_generic - No-op function, return void 110 * @hw: pointer to the HW structure 111 **/ 112 void e1000_null_phy_generic(struct e1000_hw *hw) 113 { 114 DEBUGFUNC("e1000_null_phy_generic"); 115 return; 116 } 117 118 /** 119 * e1000_null_lplu_state - No-op function, return 0 120 * @hw: pointer to the HW structure 121 **/ 122 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 123 { 124 DEBUGFUNC("e1000_null_lplu_state"); 125 return E1000_SUCCESS; 126 } 127 128 /** 129 * e1000_null_write_reg - No-op function, return 0 130 * @hw: pointer to the HW structure 131 **/ 132 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 133 { 134 DEBUGFUNC("e1000_null_write_reg"); 135 return E1000_SUCCESS; 136 } 137 138 /** 139 * e1000_check_reset_block_generic - Check if PHY reset is blocked 140 * @hw: pointer to the HW structure 141 * 142 * Read the PHY management control register and check whether a PHY reset 143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 144 * return E1000_BLK_PHY_RESET (12). 145 **/ 146 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 147 { 148 u32 manc; 149 150 DEBUGFUNC("e1000_check_reset_block"); 151 152 manc = E1000_READ_REG(hw, E1000_MANC); 153 154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 155 E1000_BLK_PHY_RESET : E1000_SUCCESS; 156 } 157 158 /** 159 * e1000_get_phy_id - Retrieve the PHY ID and revision 160 * @hw: pointer to the HW structure 161 * 162 * Reads the PHY registers and stores the PHY ID and possibly the PHY 163 * revision in the hardware structure. 164 **/ 165 s32 e1000_get_phy_id(struct e1000_hw *hw) 166 { 167 struct e1000_phy_info *phy = &hw->phy; 168 s32 ret_val = E1000_SUCCESS; 169 u16 phy_id; 170 u16 retry_count = 0; 171 172 DEBUGFUNC("e1000_get_phy_id"); 173 174 if (!(phy->ops.read_reg)) 175 goto out; 176 177 while (retry_count < 2) { 178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 179 if (ret_val) 180 goto out; 181 182 phy->id = (u32)(phy_id << 16); 183 usec_delay(20); 184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 185 if (ret_val) 186 goto out; 187 188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 190 191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 192 goto out; 193 194 retry_count++; 195 } 196 out: 197 return ret_val; 198 } 199 200 /** 201 * e1000_phy_reset_dsp_generic - Reset PHY DSP 202 * @hw: pointer to the HW structure 203 * 204 * Reset the digital signal processor. 205 **/ 206 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 207 { 208 s32 ret_val = E1000_SUCCESS; 209 210 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 211 212 if (!(hw->phy.ops.write_reg)) 213 goto out; 214 215 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 216 if (ret_val) 217 goto out; 218 219 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 220 221 out: 222 return ret_val; 223 } 224 225 /** 226 * e1000_read_phy_reg_mdic - Read MDI control register 227 * @hw: pointer to the HW structure 228 * @offset: register offset to be read 229 * @data: pointer to the read data 230 * 231 * Reads the MDI control register in the PHY at offset and stores the 232 * information read to data. 233 **/ 234 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 235 { 236 struct e1000_phy_info *phy = &hw->phy; 237 u32 i, mdic = 0; 238 s32 ret_val = E1000_SUCCESS; 239 240 DEBUGFUNC("e1000_read_phy_reg_mdic"); 241 242 if (offset > MAX_PHY_REG_ADDRESS) { 243 DEBUGOUT1("PHY Address %d is out of range\n", offset); 244 return -E1000_ERR_PARAM; 245 } 246 247 /* 248 * Set up Op-code, Phy Address, and register offset in the MDI 249 * Control register. The MAC will take care of interfacing with the 250 * PHY to retrieve the desired data. 251 */ 252 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 253 (phy->addr << E1000_MDIC_PHY_SHIFT) | 254 (E1000_MDIC_OP_READ)); 255 256 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 257 258 /* Workaround for Si errata */ 259 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 260 msec_delay(10); 261 262 /* 263 * Poll the ready bit to see if the MDI read completed 264 * Increasing the time out as testing showed failures with 265 * the lower time out 266 */ 267 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 268 usec_delay(50); 269 mdic = E1000_READ_REG(hw, E1000_MDIC); 270 if (mdic & E1000_MDIC_READY) 271 break; 272 } 273 if (!(mdic & E1000_MDIC_READY)) { 274 DEBUGOUT("MDI Read did not complete\n"); 275 ret_val = -E1000_ERR_PHY; 276 goto out; 277 } 278 if (mdic & E1000_MDIC_ERROR) { 279 DEBUGOUT("MDI Error\n"); 280 ret_val = -E1000_ERR_PHY; 281 goto out; 282 } 283 *data = (u16) mdic; 284 285 /* 286 * Allow some time after each MDIC transaction to avoid 287 * reading duplicate data in the next MDIC transaction. 288 */ 289 if (hw->mac.type == e1000_pch2lan) 290 usec_delay(100); 291 292 out: 293 return ret_val; 294 } 295 296 /** 297 * e1000_write_phy_reg_mdic - Write MDI control register 298 * @hw: pointer to the HW structure 299 * @offset: register offset to write to 300 * @data: data to write to register at offset 301 * 302 * Writes data to MDI control register in the PHY at offset. 303 **/ 304 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 305 { 306 struct e1000_phy_info *phy = &hw->phy; 307 u32 i, mdic = 0; 308 s32 ret_val = E1000_SUCCESS; 309 310 DEBUGFUNC("e1000_write_phy_reg_mdic"); 311 312 if (offset > MAX_PHY_REG_ADDRESS) { 313 DEBUGOUT1("PHY Address %d is out of range\n", offset); 314 return -E1000_ERR_PARAM; 315 } 316 317 /* 318 * Set up Op-code, Phy Address, and register offset in the MDI 319 * Control register. The MAC will take care of interfacing with the 320 * PHY to retrieve the desired data. 321 */ 322 mdic = (((u32)data) | 323 (offset << E1000_MDIC_REG_SHIFT) | 324 (phy->addr << E1000_MDIC_PHY_SHIFT) | 325 (E1000_MDIC_OP_WRITE)); 326 327 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 328 329 /* Workaround for Si errata */ 330 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 331 msec_delay(10); 332 333 /* 334 * Poll the ready bit to see if the MDI read completed 335 * Increasing the time out as testing showed failures with 336 * the lower time out 337 */ 338 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 339 usec_delay(50); 340 mdic = E1000_READ_REG(hw, E1000_MDIC); 341 if (mdic & E1000_MDIC_READY) 342 break; 343 } 344 if (!(mdic & E1000_MDIC_READY)) { 345 DEBUGOUT("MDI Write did not complete\n"); 346 ret_val = -E1000_ERR_PHY; 347 goto out; 348 } 349 if (mdic & E1000_MDIC_ERROR) { 350 DEBUGOUT("MDI Error\n"); 351 ret_val = -E1000_ERR_PHY; 352 goto out; 353 } 354 355 /* 356 * Allow some time after each MDIC transaction to avoid 357 * reading duplicate data in the next MDIC transaction. 358 */ 359 if (hw->mac.type == e1000_pch2lan) 360 usec_delay(100); 361 362 out: 363 return ret_val; 364 } 365 366 /** 367 * e1000_read_phy_reg_i2c - Read PHY register using i2c 368 * @hw: pointer to the HW structure 369 * @offset: register offset to be read 370 * @data: pointer to the read data 371 * 372 * Reads the PHY register at offset using the i2c interface and stores the 373 * retrieved information in data. 374 **/ 375 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 376 { 377 struct e1000_phy_info *phy = &hw->phy; 378 u32 i, i2ccmd = 0; 379 380 DEBUGFUNC("e1000_read_phy_reg_i2c"); 381 382 /* 383 * Set up Op-code, Phy Address, and register address in the I2CCMD 384 * register. The MAC will take care of interfacing with the 385 * PHY to retrieve the desired data. 386 */ 387 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 388 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 389 (E1000_I2CCMD_OPCODE_READ)); 390 391 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 392 393 /* Poll the ready bit to see if the I2C read completed */ 394 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 395 usec_delay(50); 396 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 397 if (i2ccmd & E1000_I2CCMD_READY) 398 break; 399 } 400 if (!(i2ccmd & E1000_I2CCMD_READY)) { 401 DEBUGOUT("I2CCMD Read did not complete\n"); 402 return -E1000_ERR_PHY; 403 } 404 if (i2ccmd & E1000_I2CCMD_ERROR) { 405 DEBUGOUT("I2CCMD Error bit set\n"); 406 return -E1000_ERR_PHY; 407 } 408 409 /* Need to byte-swap the 16-bit value. */ 410 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 411 412 return E1000_SUCCESS; 413 } 414 415 /** 416 * e1000_write_phy_reg_i2c - Write PHY register using i2c 417 * @hw: pointer to the HW structure 418 * @offset: register offset to write to 419 * @data: data to write at register offset 420 * 421 * Writes the data to PHY register at the offset using the i2c interface. 422 **/ 423 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 424 { 425 struct e1000_phy_info *phy = &hw->phy; 426 u32 i, i2ccmd = 0; 427 u16 phy_data_swapped; 428 429 DEBUGFUNC("e1000_write_phy_reg_i2c"); 430 431 /* Swap the data bytes for the I2C interface */ 432 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 433 434 /* 435 * Set up Op-code, Phy Address, and register address in the I2CCMD 436 * register. The MAC will take care of interfacing with the 437 * PHY to retrieve the desired data. 438 */ 439 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 440 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 441 E1000_I2CCMD_OPCODE_WRITE | 442 phy_data_swapped); 443 444 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 445 446 /* Poll the ready bit to see if the I2C read completed */ 447 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 448 usec_delay(50); 449 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 450 if (i2ccmd & E1000_I2CCMD_READY) 451 break; 452 } 453 if (!(i2ccmd & E1000_I2CCMD_READY)) { 454 DEBUGOUT("I2CCMD Write did not complete\n"); 455 return -E1000_ERR_PHY; 456 } 457 if (i2ccmd & E1000_I2CCMD_ERROR) { 458 DEBUGOUT("I2CCMD Error bit set\n"); 459 return -E1000_ERR_PHY; 460 } 461 462 return E1000_SUCCESS; 463 } 464 465 /** 466 * e1000_read_phy_reg_m88 - Read m88 PHY register 467 * @hw: pointer to the HW structure 468 * @offset: register offset to be read 469 * @data: pointer to the read data 470 * 471 * Acquires semaphore, if necessary, then reads the PHY register at offset 472 * and storing the retrieved information in data. Release any acquired 473 * semaphores before exiting. 474 **/ 475 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 476 { 477 s32 ret_val = E1000_SUCCESS; 478 479 DEBUGFUNC("e1000_read_phy_reg_m88"); 480 481 if (!(hw->phy.ops.acquire)) 482 goto out; 483 484 ret_val = hw->phy.ops.acquire(hw); 485 if (ret_val) 486 goto out; 487 488 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 489 data); 490 491 hw->phy.ops.release(hw); 492 493 out: 494 return ret_val; 495 } 496 497 /** 498 * e1000_write_phy_reg_m88 - Write m88 PHY register 499 * @hw: pointer to the HW structure 500 * @offset: register offset to write to 501 * @data: data to write at register offset 502 * 503 * Acquires semaphore, if necessary, then writes the data to PHY register 504 * at the offset. Release any acquired semaphores before exiting. 505 **/ 506 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 507 { 508 s32 ret_val = E1000_SUCCESS; 509 510 DEBUGFUNC("e1000_write_phy_reg_m88"); 511 512 if (!(hw->phy.ops.acquire)) 513 goto out; 514 515 ret_val = hw->phy.ops.acquire(hw); 516 if (ret_val) 517 goto out; 518 519 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 520 data); 521 522 hw->phy.ops.release(hw); 523 524 out: 525 return ret_val; 526 } 527 528 /** 529 * __e1000_read_phy_reg_igp - Read igp PHY register 530 * @hw: pointer to the HW structure 531 * @offset: register offset to be read 532 * @data: pointer to the read data 533 * @locked: semaphore has already been acquired or not 534 * 535 * Acquires semaphore, if necessary, then reads the PHY register at offset 536 * and stores the retrieved information in data. Release any acquired 537 * semaphores before exiting. 538 **/ 539 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 540 bool locked) 541 { 542 s32 ret_val = E1000_SUCCESS; 543 544 DEBUGFUNC("__e1000_read_phy_reg_igp"); 545 546 if (!locked) { 547 if (!(hw->phy.ops.acquire)) 548 goto out; 549 550 ret_val = hw->phy.ops.acquire(hw); 551 if (ret_val) 552 goto out; 553 } 554 555 if (offset > MAX_PHY_MULTI_PAGE_REG) { 556 ret_val = e1000_write_phy_reg_mdic(hw, 557 IGP01E1000_PHY_PAGE_SELECT, 558 (u16)offset); 559 if (ret_val) 560 goto release; 561 } 562 563 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 564 data); 565 566 release: 567 if (!locked) 568 hw->phy.ops.release(hw); 569 out: 570 return ret_val; 571 } 572 573 /** 574 * e1000_read_phy_reg_igp - Read igp PHY register 575 * @hw: pointer to the HW structure 576 * @offset: register offset to be read 577 * @data: pointer to the read data 578 * 579 * Acquires semaphore then reads the PHY register at offset and stores the 580 * retrieved information in data. 581 * Release the acquired semaphore before exiting. 582 **/ 583 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 584 { 585 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 586 } 587 588 /** 589 * e1000_read_phy_reg_igp_locked - Read igp PHY register 590 * @hw: pointer to the HW structure 591 * @offset: register offset to be read 592 * @data: pointer to the read data 593 * 594 * Reads the PHY register at offset and stores the retrieved information 595 * in data. Assumes semaphore already acquired. 596 **/ 597 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 598 { 599 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 600 } 601 602 /** 603 * e1000_write_phy_reg_igp - Write igp PHY register 604 * @hw: pointer to the HW structure 605 * @offset: register offset to write to 606 * @data: data to write at register offset 607 * @locked: semaphore has already been acquired or not 608 * 609 * Acquires semaphore, if necessary, then writes the data to PHY register 610 * at the offset. Release any acquired semaphores before exiting. 611 **/ 612 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 613 bool locked) 614 { 615 s32 ret_val = E1000_SUCCESS; 616 617 DEBUGFUNC("e1000_write_phy_reg_igp"); 618 619 if (!locked) { 620 if (!(hw->phy.ops.acquire)) 621 goto out; 622 623 ret_val = hw->phy.ops.acquire(hw); 624 if (ret_val) 625 goto out; 626 } 627 628 if (offset > MAX_PHY_MULTI_PAGE_REG) { 629 ret_val = e1000_write_phy_reg_mdic(hw, 630 IGP01E1000_PHY_PAGE_SELECT, 631 (u16)offset); 632 if (ret_val) 633 goto release; 634 } 635 636 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 637 data); 638 639 release: 640 if (!locked) 641 hw->phy.ops.release(hw); 642 643 out: 644 return ret_val; 645 } 646 647 /** 648 * e1000_write_phy_reg_igp - Write igp PHY register 649 * @hw: pointer to the HW structure 650 * @offset: register offset to write to 651 * @data: data to write at register offset 652 * 653 * Acquires semaphore then writes the data to PHY register 654 * at the offset. Release any acquired semaphores before exiting. 655 **/ 656 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 657 { 658 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 659 } 660 661 /** 662 * e1000_write_phy_reg_igp_locked - Write igp PHY register 663 * @hw: pointer to the HW structure 664 * @offset: register offset to write to 665 * @data: data to write at register offset 666 * 667 * Writes the data to PHY register at the offset. 668 * Assumes semaphore already acquired. 669 **/ 670 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 671 { 672 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 673 } 674 675 /** 676 * __e1000_read_kmrn_reg - Read kumeran register 677 * @hw: pointer to the HW structure 678 * @offset: register offset to be read 679 * @data: pointer to the read data 680 * @locked: semaphore has already been acquired or not 681 * 682 * Acquires semaphore, if necessary. Then reads the PHY register at offset 683 * using the kumeran interface. The information retrieved is stored in data. 684 * Release any acquired semaphores before exiting. 685 **/ 686 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 687 bool locked) 688 { 689 u32 kmrnctrlsta; 690 s32 ret_val = E1000_SUCCESS; 691 692 DEBUGFUNC("__e1000_read_kmrn_reg"); 693 694 if (!locked) { 695 if (!(hw->phy.ops.acquire)) 696 goto out; 697 698 ret_val = hw->phy.ops.acquire(hw); 699 if (ret_val) 700 goto out; 701 } 702 703 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 704 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 705 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 706 707 usec_delay(2); 708 709 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 710 *data = (u16)kmrnctrlsta; 711 712 if (!locked) 713 hw->phy.ops.release(hw); 714 715 out: 716 return ret_val; 717 } 718 719 /** 720 * e1000_read_kmrn_reg_generic - Read kumeran register 721 * @hw: pointer to the HW structure 722 * @offset: register offset to be read 723 * @data: pointer to the read data 724 * 725 * Acquires semaphore then reads the PHY register at offset using the 726 * kumeran interface. The information retrieved is stored in data. 727 * Release the acquired semaphore before exiting. 728 **/ 729 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 730 { 731 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 732 } 733 734 /** 735 * e1000_read_kmrn_reg_locked - Read kumeran register 736 * @hw: pointer to the HW structure 737 * @offset: register offset to be read 738 * @data: pointer to the read data 739 * 740 * Reads the PHY register at offset using the kumeran interface. The 741 * information retrieved is stored in data. 742 * Assumes semaphore already acquired. 743 **/ 744 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 745 { 746 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 747 } 748 749 /** 750 * __e1000_write_kmrn_reg - Write kumeran register 751 * @hw: pointer to the HW structure 752 * @offset: register offset to write to 753 * @data: data to write at register offset 754 * @locked: semaphore has already been acquired or not 755 * 756 * Acquires semaphore, if necessary. Then write the data to PHY register 757 * at the offset using the kumeran interface. Release any acquired semaphores 758 * before exiting. 759 **/ 760 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 761 bool locked) 762 { 763 u32 kmrnctrlsta; 764 s32 ret_val = E1000_SUCCESS; 765 766 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 767 768 if (!locked) { 769 if (!(hw->phy.ops.acquire)) 770 goto out; 771 772 ret_val = hw->phy.ops.acquire(hw); 773 if (ret_val) 774 goto out; 775 } 776 777 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 778 E1000_KMRNCTRLSTA_OFFSET) | data; 779 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 780 781 usec_delay(2); 782 783 if (!locked) 784 hw->phy.ops.release(hw); 785 786 out: 787 return ret_val; 788 } 789 790 /** 791 * e1000_write_kmrn_reg_generic - Write kumeran register 792 * @hw: pointer to the HW structure 793 * @offset: register offset to write to 794 * @data: data to write at register offset 795 * 796 * Acquires semaphore then writes the data to the PHY register at the offset 797 * using the kumeran interface. Release the acquired semaphore before exiting. 798 **/ 799 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 800 { 801 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 802 } 803 804 /** 805 * e1000_write_kmrn_reg_locked - Write kumeran register 806 * @hw: pointer to the HW structure 807 * @offset: register offset to write to 808 * @data: data to write at register offset 809 * 810 * Write the data to PHY register at the offset using the kumeran interface. 811 * Assumes semaphore already acquired. 812 **/ 813 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 814 { 815 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 816 } 817 818 /** 819 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 820 * @hw: pointer to the HW structure 821 * 822 * Sets up Carrier-sense on Transmit and downshift values. 823 **/ 824 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 825 { 826 s32 ret_val; 827 u16 phy_data; 828 829 DEBUGFUNC("e1000_copper_link_setup_82577"); 830 831 if (hw->phy.reset_disable) { 832 ret_val = E1000_SUCCESS; 833 goto out; 834 } 835 836 if (hw->phy.type == e1000_phy_82580) { 837 ret_val = hw->phy.ops.reset(hw); 838 if (ret_val) { 839 DEBUGOUT("Error resetting the PHY.\n"); 840 goto out; 841 } 842 } 843 844 /* Enable CRS on TX. This must be set for half-duplex operation. */ 845 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 846 if (ret_val) 847 goto out; 848 849 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 850 851 /* Enable downshift */ 852 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 853 854 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 855 856 out: 857 return ret_val; 858 } 859 860 /** 861 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 862 * @hw: pointer to the HW structure 863 * 864 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 865 * and downshift values are set also. 866 **/ 867 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 868 { 869 struct e1000_phy_info *phy = &hw->phy; 870 s32 ret_val; 871 u16 phy_data; 872 873 DEBUGFUNC("e1000_copper_link_setup_m88"); 874 875 if (phy->reset_disable) { 876 ret_val = E1000_SUCCESS; 877 goto out; 878 } 879 880 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 881 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 882 if (ret_val) 883 goto out; 884 885 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 886 /* For BM PHY this bit is downshift enable */ 887 if (phy->type == e1000_phy_bm) 888 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 889 890 /* 891 * Options: 892 * MDI/MDI-X = 0 (default) 893 * 0 - Auto for all speeds 894 * 1 - MDI mode 895 * 2 - MDI-X mode 896 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 897 */ 898 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 899 900 switch (phy->mdix) { 901 case 1: 902 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 903 break; 904 case 2: 905 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 906 break; 907 case 3: 908 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 909 break; 910 case 0: 911 default: 912 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 913 break; 914 } 915 916 /* 917 * Options: 918 * disable_polarity_correction = 0 (default) 919 * Automatic Correction for Reversed Cable Polarity 920 * 0 - Disabled 921 * 1 - Enabled 922 */ 923 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 924 if (phy->disable_polarity_correction == 1) 925 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 926 927 /* Enable downshift on BM (disabled by default) */ 928 if (phy->type == e1000_phy_bm) 929 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 930 931 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 932 if (ret_val) 933 goto out; 934 935 if ((phy->type == e1000_phy_m88) && 936 (phy->revision < E1000_REVISION_4) && 937 (phy->id != BME1000_E_PHY_ID_R2)) { 938 /* 939 * Force TX_CLK in the Extended PHY Specific Control Register 940 * to 25MHz clock. 941 */ 942 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 943 &phy_data); 944 if (ret_val) 945 goto out; 946 947 phy_data |= M88E1000_EPSCR_TX_CLK_25; 948 949 if ((phy->revision == E1000_REVISION_2) && 950 (phy->id == M88E1111_I_PHY_ID)) { 951 /* 82573L PHY - set the downshift counter to 5x. */ 952 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 953 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 954 } else { 955 /* Configure Master and Slave downshift values */ 956 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 957 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 958 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 959 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 960 } 961 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 962 phy_data); 963 if (ret_val) 964 goto out; 965 } 966 967 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 968 /* Set PHY page 0, register 29 to 0x0003 */ 969 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 970 if (ret_val) 971 goto out; 972 973 /* Set PHY page 0, register 30 to 0x0000 */ 974 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 975 if (ret_val) 976 goto out; 977 } 978 979 /* Commit the changes. */ 980 ret_val = phy->ops.commit(hw); 981 if (ret_val) { 982 DEBUGOUT("Error committing the PHY changes\n"); 983 goto out; 984 } 985 986 if (phy->type == e1000_phy_82578) { 987 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 988 &phy_data); 989 if (ret_val) 990 goto out; 991 992 /* 82578 PHY - set the downshift count to 1x. */ 993 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 994 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 995 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 996 phy_data); 997 if (ret_val) 998 goto out; 999 } 1000 1001 out: 1002 return ret_val; 1003 } 1004 1005 /** 1006 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1007 * @hw: pointer to the HW structure 1008 * 1009 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1010 * igp PHY's. 1011 **/ 1012 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1013 { 1014 struct e1000_phy_info *phy = &hw->phy; 1015 s32 ret_val; 1016 u16 data; 1017 1018 DEBUGFUNC("e1000_copper_link_setup_igp"); 1019 1020 if (phy->reset_disable) { 1021 ret_val = E1000_SUCCESS; 1022 goto out; 1023 } 1024 1025 ret_val = hw->phy.ops.reset(hw); 1026 if (ret_val) { 1027 DEBUGOUT("Error resetting the PHY.\n"); 1028 goto out; 1029 } 1030 1031 /* 1032 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1033 * timeout issues when LFS is enabled. 1034 */ 1035 msec_delay(100); 1036 1037 /* 1038 * The NVM settings will configure LPLU in D3 for 1039 * non-IGP1 PHYs. 1040 */ 1041 if (phy->type == e1000_phy_igp) { 1042 /* disable lplu d3 during driver init */ 1043 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1044 if (ret_val) { 1045 DEBUGOUT("Error Disabling LPLU D3\n"); 1046 goto out; 1047 } 1048 } 1049 1050 /* disable lplu d0 during driver init */ 1051 if (hw->phy.ops.set_d0_lplu_state) { 1052 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1053 if (ret_val) { 1054 DEBUGOUT("Error Disabling LPLU D0\n"); 1055 goto out; 1056 } 1057 } 1058 /* Configure mdi-mdix settings */ 1059 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1060 if (ret_val) 1061 goto out; 1062 1063 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1064 1065 switch (phy->mdix) { 1066 case 1: 1067 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1068 break; 1069 case 2: 1070 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1071 break; 1072 case 0: 1073 default: 1074 data |= IGP01E1000_PSCR_AUTO_MDIX; 1075 break; 1076 } 1077 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1078 if (ret_val) 1079 goto out; 1080 1081 /* set auto-master slave resolution settings */ 1082 if (hw->mac.autoneg) { 1083 /* 1084 * when autonegotiation advertisement is only 1000Mbps then we 1085 * should disable SmartSpeed and enable Auto MasterSlave 1086 * resolution as hardware default. 1087 */ 1088 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1089 /* Disable SmartSpeed */ 1090 ret_val = phy->ops.read_reg(hw, 1091 IGP01E1000_PHY_PORT_CONFIG, 1092 &data); 1093 if (ret_val) 1094 goto out; 1095 1096 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1097 ret_val = phy->ops.write_reg(hw, 1098 IGP01E1000_PHY_PORT_CONFIG, 1099 data); 1100 if (ret_val) 1101 goto out; 1102 1103 /* Set auto Master/Slave resolution process */ 1104 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1105 if (ret_val) 1106 goto out; 1107 1108 data &= ~CR_1000T_MS_ENABLE; 1109 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1110 if (ret_val) 1111 goto out; 1112 } 1113 1114 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1115 if (ret_val) 1116 goto out; 1117 1118 /* load defaults for future use */ 1119 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 1120 ((data & CR_1000T_MS_VALUE) ? 1121 e1000_ms_force_master : 1122 e1000_ms_force_slave) : 1123 e1000_ms_auto; 1124 1125 switch (phy->ms_type) { 1126 case e1000_ms_force_master: 1127 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1128 break; 1129 case e1000_ms_force_slave: 1130 data |= CR_1000T_MS_ENABLE; 1131 data &= ~(CR_1000T_MS_VALUE); 1132 break; 1133 case e1000_ms_auto: 1134 data &= ~CR_1000T_MS_ENABLE; 1135 default: 1136 break; 1137 } 1138 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1139 if (ret_val) 1140 goto out; 1141 } 1142 1143 out: 1144 return ret_val; 1145 } 1146 1147 /** 1148 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1149 * @hw: pointer to the HW structure 1150 * 1151 * Performs initial bounds checking on autoneg advertisement parameter, then 1152 * configure to advertise the full capability. Setup the PHY to autoneg 1153 * and restart the negotiation process between the link partner. If 1154 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1155 **/ 1156 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1157 { 1158 struct e1000_phy_info *phy = &hw->phy; 1159 s32 ret_val; 1160 u16 phy_ctrl; 1161 1162 DEBUGFUNC("e1000_copper_link_autoneg"); 1163 1164 /* 1165 * Perform some bounds checking on the autoneg advertisement 1166 * parameter. 1167 */ 1168 phy->autoneg_advertised &= phy->autoneg_mask; 1169 1170 /* 1171 * If autoneg_advertised is zero, we assume it was not defaulted 1172 * by the calling code so we set to advertise full capability. 1173 */ 1174 if (phy->autoneg_advertised == 0) 1175 phy->autoneg_advertised = phy->autoneg_mask; 1176 1177 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1178 ret_val = e1000_phy_setup_autoneg(hw); 1179 if (ret_val) { 1180 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1181 goto out; 1182 } 1183 DEBUGOUT("Restarting Auto-Neg\n"); 1184 1185 /* 1186 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1187 * the Auto Neg Restart bit in the PHY control register. 1188 */ 1189 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1190 if (ret_val) 1191 goto out; 1192 1193 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1194 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1195 if (ret_val) 1196 goto out; 1197 1198 /* 1199 * Does the user want to wait for Auto-Neg to complete here, or 1200 * check at a later time (for example, callback routine). 1201 */ 1202 if (phy->autoneg_wait_to_complete) { 1203 ret_val = hw->mac.ops.wait_autoneg(hw); 1204 if (ret_val) { 1205 DEBUGOUT("Error while waiting for " 1206 "autoneg to complete\n"); 1207 goto out; 1208 } 1209 } 1210 1211 hw->mac.get_link_status = TRUE; 1212 1213 out: 1214 return ret_val; 1215 } 1216 1217 /** 1218 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1219 * @hw: pointer to the HW structure 1220 * 1221 * Reads the MII auto-neg advertisement register and/or the 1000T control 1222 * register and if the PHY is already setup for auto-negotiation, then 1223 * return successful. Otherwise, setup advertisement and flow control to 1224 * the appropriate values for the wanted auto-negotiation. 1225 **/ 1226 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1227 { 1228 struct e1000_phy_info *phy = &hw->phy; 1229 s32 ret_val; 1230 u16 mii_autoneg_adv_reg; 1231 u16 mii_1000t_ctrl_reg = 0; 1232 1233 DEBUGFUNC("e1000_phy_setup_autoneg"); 1234 1235 phy->autoneg_advertised &= phy->autoneg_mask; 1236 1237 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1238 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1239 if (ret_val) 1240 goto out; 1241 1242 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1243 /* Read the MII 1000Base-T Control Register (Address 9). */ 1244 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1245 &mii_1000t_ctrl_reg); 1246 if (ret_val) 1247 goto out; 1248 } 1249 1250 /* 1251 * Need to parse both autoneg_advertised and fc and set up 1252 * the appropriate PHY registers. First we will parse for 1253 * autoneg_advertised software override. Since we can advertise 1254 * a plethora of combinations, we need to check each bit 1255 * individually. 1256 */ 1257 1258 /* 1259 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1260 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1261 * the 1000Base-T Control Register (Address 9). 1262 */ 1263 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1264 NWAY_AR_100TX_HD_CAPS | 1265 NWAY_AR_10T_FD_CAPS | 1266 NWAY_AR_10T_HD_CAPS); 1267 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1268 1269 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1270 1271 /* Do we want to advertise 10 Mb Half Duplex? */ 1272 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1273 DEBUGOUT("Advertise 10mb Half duplex\n"); 1274 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1275 } 1276 1277 /* Do we want to advertise 10 Mb Full Duplex? */ 1278 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1279 DEBUGOUT("Advertise 10mb Full duplex\n"); 1280 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1281 } 1282 1283 /* Do we want to advertise 100 Mb Half Duplex? */ 1284 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1285 DEBUGOUT("Advertise 100mb Half duplex\n"); 1286 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1287 } 1288 1289 /* Do we want to advertise 100 Mb Full Duplex? */ 1290 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1291 DEBUGOUT("Advertise 100mb Full duplex\n"); 1292 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1293 } 1294 1295 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1296 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1297 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1298 1299 /* Do we want to advertise 1000 Mb Full Duplex? */ 1300 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1301 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1302 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1303 } 1304 1305 /* 1306 * Check for a software override of the flow control settings, and 1307 * setup the PHY advertisement registers accordingly. If 1308 * auto-negotiation is enabled, then software will have to set the 1309 * "PAUSE" bits to the correct value in the Auto-Negotiation 1310 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1311 * negotiation. 1312 * 1313 * The possible values of the "fc" parameter are: 1314 * 0: Flow control is completely disabled 1315 * 1: Rx flow control is enabled (we can receive pause frames 1316 * but not send pause frames). 1317 * 2: Tx flow control is enabled (we can send pause frames 1318 * but we do not support receiving pause frames). 1319 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1320 * other: No software override. The flow control configuration 1321 * in the EEPROM is used. 1322 */ 1323 switch (hw->fc.current_mode) { 1324 case e1000_fc_none: 1325 /* 1326 * Flow control (Rx & Tx) is completely disabled by a 1327 * software over-ride. 1328 */ 1329 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1330 break; 1331 case e1000_fc_rx_pause: 1332 /* 1333 * Rx Flow control is enabled, and Tx Flow control is 1334 * disabled, by a software over-ride. 1335 * 1336 * Since there really isn't a way to advertise that we are 1337 * capable of Rx Pause ONLY, we will advertise that we 1338 * support both symmetric and asymmetric Rx PAUSE. Later 1339 * (in e1000_config_fc_after_link_up) we will disable the 1340 * hw's ability to send PAUSE frames. 1341 */ 1342 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1343 break; 1344 case e1000_fc_tx_pause: 1345 /* 1346 * Tx Flow control is enabled, and Rx Flow control is 1347 * disabled, by a software over-ride. 1348 */ 1349 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1350 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1351 break; 1352 case e1000_fc_full: 1353 /* 1354 * Flow control (both Rx and Tx) is enabled by a software 1355 * over-ride. 1356 */ 1357 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1358 break; 1359 default: 1360 DEBUGOUT("Flow control param set incorrectly\n"); 1361 ret_val = -E1000_ERR_CONFIG; 1362 goto out; 1363 } 1364 1365 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1366 if (ret_val) 1367 goto out; 1368 1369 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1370 1371 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1372 ret_val = phy->ops.write_reg(hw, 1373 PHY_1000T_CTRL, 1374 mii_1000t_ctrl_reg); 1375 if (ret_val) 1376 goto out; 1377 } 1378 1379 out: 1380 return ret_val; 1381 } 1382 1383 /** 1384 * e1000_setup_copper_link_generic - Configure copper link settings 1385 * @hw: pointer to the HW structure 1386 * 1387 * Calls the appropriate function to configure the link for auto-neg or forced 1388 * speed and duplex. Then we check for link, once link is established calls 1389 * to configure collision distance and flow control are called. If link is 1390 * not established, we return -E1000_ERR_PHY (-2). 1391 **/ 1392 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1393 { 1394 s32 ret_val; 1395 bool link; 1396 1397 DEBUGFUNC("e1000_setup_copper_link_generic"); 1398 1399 if (hw->mac.autoneg) { 1400 /* 1401 * Setup autoneg and flow control advertisement and perform 1402 * autonegotiation. 1403 */ 1404 ret_val = e1000_copper_link_autoneg(hw); 1405 if (ret_val) 1406 goto out; 1407 } else { 1408 /* 1409 * PHY will be set to 10H, 10F, 100H or 100F 1410 * depending on user settings. 1411 */ 1412 DEBUGOUT("Forcing Speed and Duplex\n"); 1413 ret_val = hw->phy.ops.force_speed_duplex(hw); 1414 if (ret_val) { 1415 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1416 goto out; 1417 } 1418 } 1419 1420 /* 1421 * Check link status. Wait up to 100 microseconds for link to become 1422 * valid. 1423 */ 1424 ret_val = e1000_phy_has_link_generic(hw, 1425 COPPER_LINK_UP_LIMIT, 1426 10, 1427 &link); 1428 if (ret_val) 1429 goto out; 1430 1431 if (link) { 1432 DEBUGOUT("Valid link established!!!\n"); 1433 e1000_config_collision_dist_generic(hw); 1434 ret_val = e1000_config_fc_after_link_up_generic(hw); 1435 } else { 1436 DEBUGOUT("Unable to establish link!!!\n"); 1437 } 1438 1439 out: 1440 return ret_val; 1441 } 1442 1443 /** 1444 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1445 * @hw: pointer to the HW structure 1446 * 1447 * Calls the PHY setup function to force speed and duplex. Clears the 1448 * auto-crossover to force MDI manually. Waits for link and returns 1449 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1450 **/ 1451 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1452 { 1453 struct e1000_phy_info *phy = &hw->phy; 1454 s32 ret_val; 1455 u16 phy_data; 1456 bool link; 1457 1458 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1459 1460 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1461 if (ret_val) 1462 goto out; 1463 1464 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1465 1466 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1467 if (ret_val) 1468 goto out; 1469 1470 /* 1471 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1472 * forced whenever speed and duplex are forced. 1473 */ 1474 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1475 if (ret_val) 1476 goto out; 1477 1478 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1479 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1480 1481 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1482 if (ret_val) 1483 goto out; 1484 1485 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1486 1487 usec_delay(1); 1488 1489 if (phy->autoneg_wait_to_complete) { 1490 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1491 1492 ret_val = e1000_phy_has_link_generic(hw, 1493 PHY_FORCE_LIMIT, 1494 100000, 1495 &link); 1496 if (ret_val) 1497 goto out; 1498 1499 if (!link) 1500 DEBUGOUT("Link taking longer than expected.\n"); 1501 1502 /* Try once more */ 1503 ret_val = e1000_phy_has_link_generic(hw, 1504 PHY_FORCE_LIMIT, 1505 100000, 1506 &link); 1507 if (ret_val) 1508 goto out; 1509 } 1510 1511 out: 1512 return ret_val; 1513 } 1514 1515 /** 1516 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1517 * @hw: pointer to the HW structure 1518 * 1519 * Calls the PHY setup function to force speed and duplex. Clears the 1520 * auto-crossover to force MDI manually. Resets the PHY to commit the 1521 * changes. If time expires while waiting for link up, we reset the DSP. 1522 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1523 * successful completion, else return corresponding error code. 1524 **/ 1525 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1526 { 1527 struct e1000_phy_info *phy = &hw->phy; 1528 s32 ret_val; 1529 u16 phy_data; 1530 bool link; 1531 1532 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1533 1534 /* 1535 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1536 * forced whenever speed and duplex are forced. 1537 */ 1538 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1539 if (ret_val) 1540 goto out; 1541 1542 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1543 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1544 if (ret_val) 1545 goto out; 1546 1547 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1548 1549 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1550 if (ret_val) 1551 goto out; 1552 1553 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1554 1555 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1556 if (ret_val) 1557 goto out; 1558 1559 /* Reset the phy to commit changes. */ 1560 ret_val = hw->phy.ops.commit(hw); 1561 if (ret_val) 1562 goto out; 1563 1564 if (phy->autoneg_wait_to_complete) { 1565 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1566 1567 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1568 100000, &link); 1569 if (ret_val) 1570 goto out; 1571 1572 if (!link) { 1573 if (hw->phy.type != e1000_phy_m88) { 1574 DEBUGOUT("Link taking longer than expected.\n"); 1575 } else { 1576 /* 1577 * We didn't get link. 1578 * Reset the DSP and cross our fingers. 1579 */ 1580 ret_val = phy->ops.write_reg(hw, 1581 M88E1000_PHY_PAGE_SELECT, 1582 0x001d); 1583 if (ret_val) 1584 goto out; 1585 ret_val = e1000_phy_reset_dsp_generic(hw); 1586 if (ret_val) 1587 goto out; 1588 } 1589 } 1590 1591 /* Try once more */ 1592 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1593 100000, &link); 1594 if (ret_val) 1595 goto out; 1596 } 1597 1598 if (hw->phy.type != e1000_phy_m88) 1599 goto out; 1600 1601 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1602 if (ret_val) 1603 goto out; 1604 1605 /* 1606 * Resetting the phy means we need to re-force TX_CLK in the 1607 * Extended PHY Specific Control Register to 25MHz clock from 1608 * the reset value of 2.5MHz. 1609 */ 1610 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1611 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1612 if (ret_val) 1613 goto out; 1614 1615 /* 1616 * In addition, we must re-enable CRS on Tx for both half and full 1617 * duplex. 1618 */ 1619 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1620 if (ret_val) 1621 goto out; 1622 1623 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1624 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1625 1626 out: 1627 return ret_val; 1628 } 1629 1630 /** 1631 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1632 * @hw: pointer to the HW structure 1633 * 1634 * Forces the speed and duplex settings of the PHY. 1635 * This is a function pointer entry point only called by 1636 * PHY setup routines. 1637 **/ 1638 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1639 { 1640 struct e1000_phy_info *phy = &hw->phy; 1641 s32 ret_val; 1642 u16 data; 1643 bool link; 1644 1645 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1646 1647 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1648 if (ret_val) 1649 goto out; 1650 1651 e1000_phy_force_speed_duplex_setup(hw, &data); 1652 1653 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1654 if (ret_val) 1655 goto out; 1656 1657 /* Disable MDI-X support for 10/100 */ 1658 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1659 if (ret_val) 1660 goto out; 1661 1662 data &= ~IFE_PMC_AUTO_MDIX; 1663 data &= ~IFE_PMC_FORCE_MDIX; 1664 1665 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1666 if (ret_val) 1667 goto out; 1668 1669 DEBUGOUT1("IFE PMC: %X\n", data); 1670 1671 usec_delay(1); 1672 1673 if (phy->autoneg_wait_to_complete) { 1674 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1675 1676 ret_val = e1000_phy_has_link_generic(hw, 1677 PHY_FORCE_LIMIT, 1678 100000, 1679 &link); 1680 if (ret_val) 1681 goto out; 1682 1683 if (!link) 1684 DEBUGOUT("Link taking longer than expected.\n"); 1685 1686 /* Try once more */ 1687 ret_val = e1000_phy_has_link_generic(hw, 1688 PHY_FORCE_LIMIT, 1689 100000, 1690 &link); 1691 if (ret_val) 1692 goto out; 1693 } 1694 1695 out: 1696 return ret_val; 1697 } 1698 1699 /** 1700 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1701 * @hw: pointer to the HW structure 1702 * @phy_ctrl: pointer to current value of PHY_CONTROL 1703 * 1704 * Forces speed and duplex on the PHY by doing the following: disable flow 1705 * control, force speed/duplex on the MAC, disable auto speed detection, 1706 * disable auto-negotiation, configure duplex, configure speed, configure 1707 * the collision distance, write configuration to CTRL register. The 1708 * caller must write to the PHY_CONTROL register for these settings to 1709 * take affect. 1710 **/ 1711 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1712 { 1713 struct e1000_mac_info *mac = &hw->mac; 1714 u32 ctrl; 1715 1716 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1717 1718 /* Turn off flow control when forcing speed/duplex */ 1719 hw->fc.current_mode = e1000_fc_none; 1720 1721 /* Force speed/duplex on the mac */ 1722 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1723 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1724 ctrl &= ~E1000_CTRL_SPD_SEL; 1725 1726 /* Disable Auto Speed Detection */ 1727 ctrl &= ~E1000_CTRL_ASDE; 1728 1729 /* Disable autoneg on the phy */ 1730 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1731 1732 /* Forcing Full or Half Duplex? */ 1733 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1734 ctrl &= ~E1000_CTRL_FD; 1735 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1736 DEBUGOUT("Half Duplex\n"); 1737 } else { 1738 ctrl |= E1000_CTRL_FD; 1739 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1740 DEBUGOUT("Full Duplex\n"); 1741 } 1742 1743 /* Forcing 10mb or 100mb? */ 1744 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1745 ctrl |= E1000_CTRL_SPD_100; 1746 *phy_ctrl |= MII_CR_SPEED_100; 1747 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1748 DEBUGOUT("Forcing 100mb\n"); 1749 } else { 1750 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1751 *phy_ctrl |= MII_CR_SPEED_10; 1752 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1753 DEBUGOUT("Forcing 10mb\n"); 1754 } 1755 1756 e1000_config_collision_dist_generic(hw); 1757 1758 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1759 } 1760 1761 /** 1762 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1763 * @hw: pointer to the HW structure 1764 * @active: boolean used to enable/disable lplu 1765 * 1766 * Success returns 0, Failure returns 1 1767 * 1768 * The low power link up (lplu) state is set to the power management level D3 1769 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1770 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1771 * is used during Dx states where the power conservation is most important. 1772 * During driver activity, SmartSpeed should be enabled so performance is 1773 * maintained. 1774 **/ 1775 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1776 { 1777 struct e1000_phy_info *phy = &hw->phy; 1778 s32 ret_val = E1000_SUCCESS; 1779 u16 data; 1780 1781 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1782 1783 if (!(hw->phy.ops.read_reg)) 1784 goto out; 1785 1786 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1787 if (ret_val) 1788 goto out; 1789 1790 if (!active) { 1791 data &= ~IGP02E1000_PM_D3_LPLU; 1792 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1793 data); 1794 if (ret_val) 1795 goto out; 1796 /* 1797 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1798 * during Dx states where the power conservation is most 1799 * important. During driver activity we should enable 1800 * SmartSpeed, so performance is maintained. 1801 */ 1802 if (phy->smart_speed == e1000_smart_speed_on) { 1803 ret_val = phy->ops.read_reg(hw, 1804 IGP01E1000_PHY_PORT_CONFIG, 1805 &data); 1806 if (ret_val) 1807 goto out; 1808 1809 data |= IGP01E1000_PSCFR_SMART_SPEED; 1810 ret_val = phy->ops.write_reg(hw, 1811 IGP01E1000_PHY_PORT_CONFIG, 1812 data); 1813 if (ret_val) 1814 goto out; 1815 } else if (phy->smart_speed == e1000_smart_speed_off) { 1816 ret_val = phy->ops.read_reg(hw, 1817 IGP01E1000_PHY_PORT_CONFIG, 1818 &data); 1819 if (ret_val) 1820 goto out; 1821 1822 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1823 ret_val = phy->ops.write_reg(hw, 1824 IGP01E1000_PHY_PORT_CONFIG, 1825 data); 1826 if (ret_val) 1827 goto out; 1828 } 1829 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1830 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1831 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1832 data |= IGP02E1000_PM_D3_LPLU; 1833 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1834 data); 1835 if (ret_val) 1836 goto out; 1837 1838 /* When LPLU is enabled, we should disable SmartSpeed */ 1839 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1840 &data); 1841 if (ret_val) 1842 goto out; 1843 1844 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1845 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1846 data); 1847 } 1848 1849 out: 1850 return ret_val; 1851 } 1852 1853 /** 1854 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1855 * @hw: pointer to the HW structure 1856 * 1857 * Success returns 0, Failure returns 1 1858 * 1859 * A downshift is detected by querying the PHY link health. 1860 **/ 1861 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1862 { 1863 struct e1000_phy_info *phy = &hw->phy; 1864 s32 ret_val; 1865 u16 phy_data, offset, mask; 1866 1867 DEBUGFUNC("e1000_check_downshift_generic"); 1868 1869 switch (phy->type) { 1870 case e1000_phy_m88: 1871 case e1000_phy_gg82563: 1872 case e1000_phy_bm: 1873 case e1000_phy_82578: 1874 offset = M88E1000_PHY_SPEC_STATUS; 1875 mask = M88E1000_PSSR_DOWNSHIFT; 1876 break; 1877 case e1000_phy_igp: 1878 case e1000_phy_igp_2: 1879 case e1000_phy_igp_3: 1880 offset = IGP01E1000_PHY_LINK_HEALTH; 1881 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1882 break; 1883 default: 1884 /* speed downshift not supported */ 1885 phy->speed_downgraded = FALSE; 1886 ret_val = E1000_SUCCESS; 1887 goto out; 1888 } 1889 1890 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1891 1892 if (!ret_val) 1893 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1894 1895 out: 1896 return ret_val; 1897 } 1898 1899 /** 1900 * e1000_check_polarity_m88 - Checks the polarity. 1901 * @hw: pointer to the HW structure 1902 * 1903 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1904 * 1905 * Polarity is determined based on the PHY specific status register. 1906 **/ 1907 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1908 { 1909 struct e1000_phy_info *phy = &hw->phy; 1910 s32 ret_val; 1911 u16 data; 1912 1913 DEBUGFUNC("e1000_check_polarity_m88"); 1914 1915 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1916 1917 if (!ret_val) 1918 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1919 ? e1000_rev_polarity_reversed 1920 : e1000_rev_polarity_normal; 1921 1922 return ret_val; 1923 } 1924 1925 /** 1926 * e1000_check_polarity_igp - Checks the polarity. 1927 * @hw: pointer to the HW structure 1928 * 1929 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1930 * 1931 * Polarity is determined based on the PHY port status register, and the 1932 * current speed (since there is no polarity at 100Mbps). 1933 **/ 1934 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1935 { 1936 struct e1000_phy_info *phy = &hw->phy; 1937 s32 ret_val; 1938 u16 data, offset, mask; 1939 1940 DEBUGFUNC("e1000_check_polarity_igp"); 1941 1942 /* 1943 * Polarity is determined based on the speed of 1944 * our connection. 1945 */ 1946 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1947 if (ret_val) 1948 goto out; 1949 1950 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1951 IGP01E1000_PSSR_SPEED_1000MBPS) { 1952 offset = IGP01E1000_PHY_PCS_INIT_REG; 1953 mask = IGP01E1000_PHY_POLARITY_MASK; 1954 } else { 1955 /* 1956 * This really only applies to 10Mbps since 1957 * there is no polarity for 100Mbps (always 0). 1958 */ 1959 offset = IGP01E1000_PHY_PORT_STATUS; 1960 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1961 } 1962 1963 ret_val = phy->ops.read_reg(hw, offset, &data); 1964 1965 if (!ret_val) 1966 phy->cable_polarity = (data & mask) 1967 ? e1000_rev_polarity_reversed 1968 : e1000_rev_polarity_normal; 1969 1970 out: 1971 return ret_val; 1972 } 1973 1974 /** 1975 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1976 * @hw: pointer to the HW structure 1977 * 1978 * Polarity is determined on the polarity reversal feature being enabled. 1979 **/ 1980 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1981 { 1982 struct e1000_phy_info *phy = &hw->phy; 1983 s32 ret_val; 1984 u16 phy_data, offset, mask; 1985 1986 DEBUGFUNC("e1000_check_polarity_ife"); 1987 1988 /* 1989 * Polarity is determined based on the reversal feature being enabled. 1990 */ 1991 if (phy->polarity_correction) { 1992 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1993 mask = IFE_PESC_POLARITY_REVERSED; 1994 } else { 1995 offset = IFE_PHY_SPECIAL_CONTROL; 1996 mask = IFE_PSC_FORCE_POLARITY; 1997 } 1998 1999 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2000 2001 if (!ret_val) 2002 phy->cable_polarity = (phy_data & mask) 2003 ? e1000_rev_polarity_reversed 2004 : e1000_rev_polarity_normal; 2005 2006 return ret_val; 2007 } 2008 2009 /** 2010 * e1000_wait_autoneg_generic - Wait for auto-neg completion 2011 * @hw: pointer to the HW structure 2012 * 2013 * Waits for auto-negotiation to complete or for the auto-negotiation time 2014 * limit to expire, which ever happens first. 2015 **/ 2016 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 2017 { 2018 s32 ret_val = E1000_SUCCESS; 2019 u16 i, phy_status; 2020 2021 DEBUGFUNC("e1000_wait_autoneg_generic"); 2022 2023 if (!(hw->phy.ops.read_reg)) 2024 return E1000_SUCCESS; 2025 2026 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2027 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2028 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2029 if (ret_val) 2030 break; 2031 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2032 if (ret_val) 2033 break; 2034 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2035 break; 2036 msec_delay(100); 2037 } 2038 2039 /* 2040 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2041 * has completed. 2042 */ 2043 return ret_val; 2044 } 2045 2046 /** 2047 * e1000_phy_has_link_generic - Polls PHY for link 2048 * @hw: pointer to the HW structure 2049 * @iterations: number of times to poll for link 2050 * @usec_interval: delay between polling attempts 2051 * @success: pointer to whether polling was successful or not 2052 * 2053 * Polls the PHY status register for link, 'iterations' number of times. 2054 **/ 2055 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2056 u32 usec_interval, bool *success) 2057 { 2058 s32 ret_val = E1000_SUCCESS; 2059 u16 i, phy_status; 2060 2061 DEBUGFUNC("e1000_phy_has_link_generic"); 2062 2063 if (!(hw->phy.ops.read_reg)) 2064 return E1000_SUCCESS; 2065 2066 for (i = 0; i < iterations; i++) { 2067 /* 2068 * Some PHYs require the PHY_STATUS register to be read 2069 * twice due to the link bit being sticky. No harm doing 2070 * it across the board. 2071 */ 2072 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2073 if (ret_val) 2074 /* 2075 * If the first read fails, another entity may have 2076 * ownership of the resources, wait and try again to 2077 * see if they have relinquished the resources yet. 2078 */ 2079 usec_delay(usec_interval); 2080 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2081 if (ret_val) 2082 break; 2083 if (phy_status & MII_SR_LINK_STATUS) 2084 break; 2085 if (usec_interval >= 1000) 2086 msec_delay_irq(usec_interval/1000); 2087 else 2088 usec_delay(usec_interval); 2089 } 2090 2091 *success = (i < iterations) ? TRUE : FALSE; 2092 2093 return ret_val; 2094 } 2095 2096 /** 2097 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2098 * @hw: pointer to the HW structure 2099 * 2100 * Reads the PHY specific status register to retrieve the cable length 2101 * information. The cable length is determined by averaging the minimum and 2102 * maximum values to get the "average" cable length. The m88 PHY has four 2103 * possible cable length values, which are: 2104 * Register Value Cable Length 2105 * 0 < 50 meters 2106 * 1 50 - 80 meters 2107 * 2 80 - 110 meters 2108 * 3 110 - 140 meters 2109 * 4 > 140 meters 2110 **/ 2111 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2112 { 2113 struct e1000_phy_info *phy = &hw->phy; 2114 s32 ret_val; 2115 u16 phy_data, index; 2116 2117 DEBUGFUNC("e1000_get_cable_length_m88"); 2118 2119 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2120 if (ret_val) 2121 goto out; 2122 2123 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2124 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2125 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2126 ret_val = -E1000_ERR_PHY; 2127 goto out; 2128 } 2129 2130 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2131 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2132 2133 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2134 2135 out: 2136 return ret_val; 2137 } 2138 2139 /** 2140 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2141 * @hw: pointer to the HW structure 2142 * 2143 * The automatic gain control (agc) normalizes the amplitude of the 2144 * received signal, adjusting for the attenuation produced by the 2145 * cable. By reading the AGC registers, which represent the 2146 * combination of coarse and fine gain value, the value can be put 2147 * into a lookup table to obtain the approximate cable length 2148 * for each channel. 2149 **/ 2150 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2151 { 2152 struct e1000_phy_info *phy = &hw->phy; 2153 s32 ret_val = E1000_SUCCESS; 2154 u16 phy_data, i, agc_value = 0; 2155 u16 cur_agc_index, max_agc_index = 0; 2156 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2157 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 2158 {IGP02E1000_PHY_AGC_A, 2159 IGP02E1000_PHY_AGC_B, 2160 IGP02E1000_PHY_AGC_C, 2161 IGP02E1000_PHY_AGC_D}; 2162 2163 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2164 2165 /* Read the AGC registers for all channels */ 2166 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2167 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2168 if (ret_val) 2169 goto out; 2170 2171 /* 2172 * Getting bits 15:9, which represent the combination of 2173 * coarse and fine gain values. The result is a number 2174 * that can be put into the lookup table to obtain the 2175 * approximate cable length. 2176 */ 2177 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2178 IGP02E1000_AGC_LENGTH_MASK; 2179 2180 /* Array index bound check. */ 2181 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2182 (cur_agc_index == 0)) { 2183 ret_val = -E1000_ERR_PHY; 2184 goto out; 2185 } 2186 2187 /* Remove min & max AGC values from calculation. */ 2188 if (e1000_igp_2_cable_length_table[min_agc_index] > 2189 e1000_igp_2_cable_length_table[cur_agc_index]) 2190 min_agc_index = cur_agc_index; 2191 if (e1000_igp_2_cable_length_table[max_agc_index] < 2192 e1000_igp_2_cable_length_table[cur_agc_index]) 2193 max_agc_index = cur_agc_index; 2194 2195 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2196 } 2197 2198 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2199 e1000_igp_2_cable_length_table[max_agc_index]); 2200 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2201 2202 /* Calculate cable length with the error range of +/- 10 meters. */ 2203 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2204 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2205 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2206 2207 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2208 2209 out: 2210 return ret_val; 2211 } 2212 2213 /** 2214 * e1000_get_phy_info_m88 - Retrieve PHY information 2215 * @hw: pointer to the HW structure 2216 * 2217 * Valid for only copper links. Read the PHY status register (sticky read) 2218 * to verify that link is up. Read the PHY special control register to 2219 * determine the polarity and 10base-T extended distance. Read the PHY 2220 * special status register to determine MDI/MDIx and current speed. If 2221 * speed is 1000, then determine cable length, local and remote receiver. 2222 **/ 2223 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2224 { 2225 struct e1000_phy_info *phy = &hw->phy; 2226 s32 ret_val; 2227 u16 phy_data; 2228 bool link; 2229 2230 DEBUGFUNC("e1000_get_phy_info_m88"); 2231 2232 if (phy->media_type != e1000_media_type_copper) { 2233 DEBUGOUT("Phy info is only valid for copper media\n"); 2234 ret_val = -E1000_ERR_CONFIG; 2235 goto out; 2236 } 2237 2238 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2239 if (ret_val) 2240 goto out; 2241 2242 if (!link) { 2243 DEBUGOUT("Phy info is only valid if link is up\n"); 2244 ret_val = -E1000_ERR_CONFIG; 2245 goto out; 2246 } 2247 2248 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2249 if (ret_val) 2250 goto out; 2251 2252 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2253 ? TRUE : FALSE; 2254 2255 ret_val = e1000_check_polarity_m88(hw); 2256 if (ret_val) 2257 goto out; 2258 2259 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2260 if (ret_val) 2261 goto out; 2262 2263 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 2264 2265 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2266 ret_val = hw->phy.ops.get_cable_length(hw); 2267 if (ret_val) 2268 goto out; 2269 2270 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2271 if (ret_val) 2272 goto out; 2273 2274 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2275 ? e1000_1000t_rx_status_ok 2276 : e1000_1000t_rx_status_not_ok; 2277 2278 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2279 ? e1000_1000t_rx_status_ok 2280 : e1000_1000t_rx_status_not_ok; 2281 } else { 2282 /* Set values to "undefined" */ 2283 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2284 phy->local_rx = e1000_1000t_rx_status_undefined; 2285 phy->remote_rx = e1000_1000t_rx_status_undefined; 2286 } 2287 2288 out: 2289 return ret_val; 2290 } 2291 2292 /** 2293 * e1000_get_phy_info_igp - Retrieve igp PHY information 2294 * @hw: pointer to the HW structure 2295 * 2296 * Read PHY status to determine if link is up. If link is up, then 2297 * set/determine 10base-T extended distance and polarity correction. Read 2298 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2299 * determine on the cable length, local and remote receiver. 2300 **/ 2301 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2302 { 2303 struct e1000_phy_info *phy = &hw->phy; 2304 s32 ret_val; 2305 u16 data; 2306 bool link; 2307 2308 DEBUGFUNC("e1000_get_phy_info_igp"); 2309 2310 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2311 if (ret_val) 2312 goto out; 2313 2314 if (!link) { 2315 DEBUGOUT("Phy info is only valid if link is up\n"); 2316 ret_val = -E1000_ERR_CONFIG; 2317 goto out; 2318 } 2319 2320 phy->polarity_correction = TRUE; 2321 2322 ret_val = e1000_check_polarity_igp(hw); 2323 if (ret_val) 2324 goto out; 2325 2326 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2327 if (ret_val) 2328 goto out; 2329 2330 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 2331 2332 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2333 IGP01E1000_PSSR_SPEED_1000MBPS) { 2334 ret_val = phy->ops.get_cable_length(hw); 2335 if (ret_val) 2336 goto out; 2337 2338 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2339 if (ret_val) 2340 goto out; 2341 2342 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2343 ? e1000_1000t_rx_status_ok 2344 : e1000_1000t_rx_status_not_ok; 2345 2346 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2347 ? e1000_1000t_rx_status_ok 2348 : e1000_1000t_rx_status_not_ok; 2349 } else { 2350 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2351 phy->local_rx = e1000_1000t_rx_status_undefined; 2352 phy->remote_rx = e1000_1000t_rx_status_undefined; 2353 } 2354 2355 out: 2356 return ret_val; 2357 } 2358 2359 /** 2360 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2361 * @hw: pointer to the HW structure 2362 * 2363 * Populates "phy" structure with various feature states. 2364 **/ 2365 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2366 { 2367 struct e1000_phy_info *phy = &hw->phy; 2368 s32 ret_val; 2369 u16 data; 2370 bool link; 2371 2372 DEBUGFUNC("e1000_get_phy_info_ife"); 2373 2374 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2375 if (ret_val) 2376 goto out; 2377 2378 if (!link) { 2379 DEBUGOUT("Phy info is only valid if link is up\n"); 2380 ret_val = -E1000_ERR_CONFIG; 2381 goto out; 2382 } 2383 2384 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2385 if (ret_val) 2386 goto out; 2387 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2388 ? FALSE : TRUE; 2389 2390 if (phy->polarity_correction) { 2391 ret_val = e1000_check_polarity_ife(hw); 2392 if (ret_val) 2393 goto out; 2394 } else { 2395 /* Polarity is forced */ 2396 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2397 ? e1000_rev_polarity_reversed 2398 : e1000_rev_polarity_normal; 2399 } 2400 2401 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2402 if (ret_val) 2403 goto out; 2404 2405 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 2406 2407 /* The following parameters are undefined for 10/100 operation. */ 2408 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2409 phy->local_rx = e1000_1000t_rx_status_undefined; 2410 phy->remote_rx = e1000_1000t_rx_status_undefined; 2411 2412 out: 2413 return ret_val; 2414 } 2415 2416 /** 2417 * e1000_phy_sw_reset_generic - PHY software reset 2418 * @hw: pointer to the HW structure 2419 * 2420 * Does a software reset of the PHY by reading the PHY control register and 2421 * setting/write the control register reset bit to the PHY. 2422 **/ 2423 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2424 { 2425 s32 ret_val = E1000_SUCCESS; 2426 u16 phy_ctrl; 2427 2428 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2429 2430 if (!(hw->phy.ops.read_reg)) 2431 goto out; 2432 2433 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2434 if (ret_val) 2435 goto out; 2436 2437 phy_ctrl |= MII_CR_RESET; 2438 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2439 if (ret_val) 2440 goto out; 2441 2442 usec_delay(1); 2443 2444 out: 2445 return ret_val; 2446 } 2447 2448 /** 2449 * e1000_phy_hw_reset_generic - PHY hardware reset 2450 * @hw: pointer to the HW structure 2451 * 2452 * Verify the reset block is not blocking us from resetting. Acquire 2453 * semaphore (if necessary) and read/set/write the device control reset 2454 * bit in the PHY. Wait the appropriate delay time for the device to 2455 * reset and release the semaphore (if necessary). 2456 **/ 2457 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2458 { 2459 struct e1000_phy_info *phy = &hw->phy; 2460 s32 ret_val = E1000_SUCCESS; 2461 u32 ctrl; 2462 2463 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2464 2465 ret_val = phy->ops.check_reset_block(hw); 2466 if (ret_val) { 2467 ret_val = E1000_SUCCESS; 2468 goto out; 2469 } 2470 2471 ret_val = phy->ops.acquire(hw); 2472 if (ret_val) 2473 goto out; 2474 2475 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2476 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2477 E1000_WRITE_FLUSH(hw); 2478 2479 usec_delay(phy->reset_delay_us); 2480 2481 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2482 E1000_WRITE_FLUSH(hw); 2483 2484 usec_delay(150); 2485 2486 phy->ops.release(hw); 2487 2488 ret_val = phy->ops.get_cfg_done(hw); 2489 2490 out: 2491 return ret_val; 2492 } 2493 2494 /** 2495 * e1000_get_cfg_done_generic - Generic configuration done 2496 * @hw: pointer to the HW structure 2497 * 2498 * Generic function to wait 10 milli-seconds for configuration to complete 2499 * and return success. 2500 **/ 2501 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2502 { 2503 DEBUGFUNC("e1000_get_cfg_done_generic"); 2504 2505 msec_delay_irq(10); 2506 2507 return E1000_SUCCESS; 2508 } 2509 2510 /** 2511 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2512 * @hw: pointer to the HW structure 2513 * 2514 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2515 **/ 2516 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2517 { 2518 DEBUGOUT("Running IGP 3 PHY init script\n"); 2519 2520 /* PHY init IGP 3 */ 2521 /* Enable rise/fall, 10-mode work in class-A */ 2522 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2523 /* Remove all caps from Replica path filter */ 2524 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2525 /* Bias trimming for ADC, AFE and Driver (Default) */ 2526 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2527 /* Increase Hybrid poly bias */ 2528 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2529 /* Add 4% to Tx amplitude in Gig mode */ 2530 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2531 /* Disable trimming (TTT) */ 2532 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2533 /* Poly DC correction to 94.6% + 2% for all channels */ 2534 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2535 /* ABS DC correction to 95.9% */ 2536 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2537 /* BG temp curve trim */ 2538 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2539 /* Increasing ADC OPAMP stage 1 currents to max */ 2540 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2541 /* Force 1000 ( required for enabling PHY regs configuration) */ 2542 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2543 /* Set upd_freq to 6 */ 2544 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2545 /* Disable NPDFE */ 2546 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2547 /* Disable adaptive fixed FFE (Default) */ 2548 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2549 /* Enable FFE hysteresis */ 2550 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2551 /* Fixed FFE for short cable lengths */ 2552 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2553 /* Fixed FFE for medium cable lengths */ 2554 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2555 /* Fixed FFE for long cable lengths */ 2556 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2557 /* Enable Adaptive Clip Threshold */ 2558 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2559 /* AHT reset limit to 1 */ 2560 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2561 /* Set AHT master delay to 127 msec */ 2562 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2563 /* Set scan bits for AHT */ 2564 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2565 /* Set AHT Preset bits */ 2566 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2567 /* Change integ_factor of channel A to 3 */ 2568 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2569 /* Change prop_factor of channels BCD to 8 */ 2570 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2571 /* Change cg_icount + enable integbp for channels BCD */ 2572 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2573 /* 2574 * Change cg_icount + enable integbp + change prop_factor_master 2575 * to 8 for channel A 2576 */ 2577 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2578 /* Disable AHT in Slave mode on channel A */ 2579 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2580 /* 2581 * Enable LPLU and disable AN to 1000 in non-D0a states, 2582 * Enable SPD+B2B 2583 */ 2584 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2585 /* Enable restart AN on an1000_dis change */ 2586 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2587 /* Enable wh_fifo read clock in 10/100 modes */ 2588 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2589 /* Restart AN, Speed selection is 1000 */ 2590 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2591 2592 return E1000_SUCCESS; 2593 } 2594 2595 /** 2596 * e1000_get_phy_type_from_id - Get PHY type from id 2597 * @phy_id: phy_id read from the phy 2598 * 2599 * Returns the phy type from the id. 2600 **/ 2601 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2602 { 2603 enum e1000_phy_type phy_type = e1000_phy_unknown; 2604 2605 switch (phy_id) { 2606 case M88E1000_I_PHY_ID: 2607 case M88E1000_E_PHY_ID: 2608 case M88E1111_I_PHY_ID: 2609 case M88E1011_I_PHY_ID: 2610 phy_type = e1000_phy_m88; 2611 break; 2612 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2613 phy_type = e1000_phy_igp_2; 2614 break; 2615 case GG82563_E_PHY_ID: 2616 phy_type = e1000_phy_gg82563; 2617 break; 2618 case IGP03E1000_E_PHY_ID: 2619 phy_type = e1000_phy_igp_3; 2620 break; 2621 case IFE_E_PHY_ID: 2622 case IFE_PLUS_E_PHY_ID: 2623 case IFE_C_E_PHY_ID: 2624 phy_type = e1000_phy_ife; 2625 break; 2626 case BME1000_E_PHY_ID: 2627 case BME1000_E_PHY_ID_R2: 2628 phy_type = e1000_phy_bm; 2629 break; 2630 case I82578_E_PHY_ID: 2631 phy_type = e1000_phy_82578; 2632 break; 2633 case I82577_E_PHY_ID: 2634 phy_type = e1000_phy_82577; 2635 break; 2636 case I82579_E_PHY_ID: 2637 phy_type = e1000_phy_82579; 2638 break; 2639 case I82580_I_PHY_ID: 2640 phy_type = e1000_phy_82580; 2641 break; 2642 default: 2643 phy_type = e1000_phy_unknown; 2644 break; 2645 } 2646 return phy_type; 2647 } 2648 2649 /** 2650 * e1000_determine_phy_address - Determines PHY address. 2651 * @hw: pointer to the HW structure 2652 * 2653 * This uses a trial and error method to loop through possible PHY 2654 * addresses. It tests each by reading the PHY ID registers and 2655 * checking for a match. 2656 **/ 2657 s32 e1000_determine_phy_address(struct e1000_hw *hw) 2658 { 2659 s32 ret_val = -E1000_ERR_PHY_TYPE; 2660 u32 phy_addr = 0; 2661 u32 i; 2662 enum e1000_phy_type phy_type = e1000_phy_unknown; 2663 2664 hw->phy.id = phy_type; 2665 2666 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2667 hw->phy.addr = phy_addr; 2668 i = 0; 2669 2670 do { 2671 e1000_get_phy_id(hw); 2672 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2673 2674 /* 2675 * If phy_type is valid, break - we found our 2676 * PHY address 2677 */ 2678 if (phy_type != e1000_phy_unknown) { 2679 ret_val = E1000_SUCCESS; 2680 goto out; 2681 } 2682 msec_delay(1); 2683 i++; 2684 } while (i < 10); 2685 } 2686 2687 out: 2688 return ret_val; 2689 } 2690 2691 /** 2692 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2693 * @page: page to access 2694 * 2695 * Returns the phy address for the page requested. 2696 **/ 2697 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2698 { 2699 u32 phy_addr = 2; 2700 2701 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2702 phy_addr = 1; 2703 2704 return phy_addr; 2705 } 2706 2707 /** 2708 * e1000_write_phy_reg_bm - Write BM PHY register 2709 * @hw: pointer to the HW structure 2710 * @offset: register offset to write to 2711 * @data: data to write at register offset 2712 * 2713 * Acquires semaphore, if necessary, then writes the data to PHY register 2714 * at the offset. Release any acquired semaphores before exiting. 2715 **/ 2716 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2717 { 2718 s32 ret_val; 2719 u32 page_select = 0; 2720 u32 page = offset >> IGP_PAGE_SHIFT; 2721 u32 page_shift = 0; 2722 2723 DEBUGFUNC("e1000_write_phy_reg_bm"); 2724 2725 ret_val = hw->phy.ops.acquire(hw); 2726 if (ret_val) 2727 return ret_val; 2728 2729 /* Page 800 works differently than the rest so it has its own func */ 2730 if (page == BM_WUC_PAGE) { 2731 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2732 FALSE); 2733 goto out; 2734 } 2735 2736 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2737 2738 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2739 /* 2740 * Page select is register 31 for phy address 1 and 22 for 2741 * phy address 2 and 3. Page select is shifted only for 2742 * phy address 1. 2743 */ 2744 if (hw->phy.addr == 1) { 2745 page_shift = IGP_PAGE_SHIFT; 2746 page_select = IGP01E1000_PHY_PAGE_SELECT; 2747 } else { 2748 page_shift = 0; 2749 page_select = BM_PHY_PAGE_SELECT; 2750 } 2751 2752 /* Page is shifted left, PHY expects (page x 32) */ 2753 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2754 (page << page_shift)); 2755 if (ret_val) 2756 goto out; 2757 } 2758 2759 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2760 data); 2761 2762 out: 2763 hw->phy.ops.release(hw); 2764 return ret_val; 2765 } 2766 2767 /** 2768 * e1000_read_phy_reg_bm - Read BM PHY register 2769 * @hw: pointer to the HW structure 2770 * @offset: register offset to be read 2771 * @data: pointer to the read data 2772 * 2773 * Acquires semaphore, if necessary, then reads the PHY register at offset 2774 * and storing the retrieved information in data. Release any acquired 2775 * semaphores before exiting. 2776 **/ 2777 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2778 { 2779 s32 ret_val; 2780 u32 page_select = 0; 2781 u32 page = offset >> IGP_PAGE_SHIFT; 2782 u32 page_shift = 0; 2783 2784 DEBUGFUNC("e1000_read_phy_reg_bm"); 2785 2786 ret_val = hw->phy.ops.acquire(hw); 2787 if (ret_val) 2788 return ret_val; 2789 2790 /* Page 800 works differently than the rest so it has its own func */ 2791 if (page == BM_WUC_PAGE) { 2792 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2793 TRUE); 2794 goto out; 2795 } 2796 2797 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2798 2799 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2800 /* 2801 * Page select is register 31 for phy address 1 and 22 for 2802 * phy address 2 and 3. Page select is shifted only for 2803 * phy address 1. 2804 */ 2805 if (hw->phy.addr == 1) { 2806 page_shift = IGP_PAGE_SHIFT; 2807 page_select = IGP01E1000_PHY_PAGE_SELECT; 2808 } else { 2809 page_shift = 0; 2810 page_select = BM_PHY_PAGE_SELECT; 2811 } 2812 2813 /* Page is shifted left, PHY expects (page x 32) */ 2814 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2815 (page << page_shift)); 2816 if (ret_val) 2817 goto out; 2818 } 2819 2820 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2821 data); 2822 out: 2823 hw->phy.ops.release(hw); 2824 return ret_val; 2825 } 2826 2827 /** 2828 * e1000_read_phy_reg_bm2 - Read BM PHY register 2829 * @hw: pointer to the HW structure 2830 * @offset: register offset to be read 2831 * @data: pointer to the read data 2832 * 2833 * Acquires semaphore, if necessary, then reads the PHY register at offset 2834 * and storing the retrieved information in data. Release any acquired 2835 * semaphores before exiting. 2836 **/ 2837 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2838 { 2839 s32 ret_val; 2840 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2841 2842 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2843 2844 ret_val = hw->phy.ops.acquire(hw); 2845 if (ret_val) 2846 return ret_val; 2847 2848 /* Page 800 works differently than the rest so it has its own func */ 2849 if (page == BM_WUC_PAGE) { 2850 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2851 TRUE); 2852 goto out; 2853 } 2854 2855 hw->phy.addr = 1; 2856 2857 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2858 2859 /* Page is shifted left, PHY expects (page x 32) */ 2860 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2861 page); 2862 2863 if (ret_val) 2864 goto out; 2865 } 2866 2867 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2868 data); 2869 out: 2870 hw->phy.ops.release(hw); 2871 return ret_val; 2872 } 2873 2874 /** 2875 * e1000_write_phy_reg_bm2 - Write BM PHY register 2876 * @hw: pointer to the HW structure 2877 * @offset: register offset to write to 2878 * @data: data to write at register offset 2879 * 2880 * Acquires semaphore, if necessary, then writes the data to PHY register 2881 * at the offset. Release any acquired semaphores before exiting. 2882 **/ 2883 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2884 { 2885 s32 ret_val; 2886 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2887 2888 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2889 2890 ret_val = hw->phy.ops.acquire(hw); 2891 if (ret_val) 2892 return ret_val; 2893 2894 /* Page 800 works differently than the rest so it has its own func */ 2895 if (page == BM_WUC_PAGE) { 2896 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2897 FALSE); 2898 goto out; 2899 } 2900 2901 hw->phy.addr = 1; 2902 2903 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2904 /* Page is shifted left, PHY expects (page x 32) */ 2905 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2906 page); 2907 2908 if (ret_val) 2909 goto out; 2910 } 2911 2912 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2913 data); 2914 2915 out: 2916 hw->phy.ops.release(hw); 2917 return ret_val; 2918 } 2919 2920 /** 2921 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2922 * @hw: pointer to the HW structure 2923 * @offset: register offset to be read or written 2924 * @data: pointer to the data to read or write 2925 * @read: determines if operation is read or write 2926 * 2927 * Acquires semaphore, if necessary, then reads the PHY register at offset 2928 * and storing the retrieved information in data. Release any acquired 2929 * semaphores before exiting. Note that procedure to read the wakeup 2930 * registers are different. It works as such: 2931 * 1) Set page 769, register 17, bit 2 = 1 2932 * 2) Set page to 800 for host (801 if we were manageability) 2933 * 3) Write the address using the address opcode (0x11) 2934 * 4) Read or write the data using the data opcode (0x12) 2935 * 5) Restore 769_17.2 to its original value 2936 * 2937 * Assumes semaphore already acquired. 2938 **/ 2939 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2940 u16 *data, bool read) 2941 { 2942 s32 ret_val; 2943 u16 reg = BM_PHY_REG_NUM(offset); 2944 u16 phy_reg = 0; 2945 2946 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 2947 2948 /* Gig must be disabled for MDIO accesses to page 800 */ 2949 if ((hw->mac.type == e1000_pchlan) && 2950 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2951 DEBUGOUT("Attempting to access page 800 while gig enabled.\n"); 2952 2953 /* All operations in this function are phy address 1 */ 2954 hw->phy.addr = 1; 2955 2956 /* Set page 769 */ 2957 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2958 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2959 2960 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2961 if (ret_val) { 2962 DEBUGOUT("Could not read PHY page 769\n"); 2963 goto out; 2964 } 2965 2966 /* First clear bit 4 to avoid a power state change */ 2967 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2968 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2969 if (ret_val) { 2970 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 2971 goto out; 2972 } 2973 2974 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2975 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2976 phy_reg | BM_WUC_ENABLE_BIT); 2977 if (ret_val) { 2978 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 2979 goto out; 2980 } 2981 2982 /* Select page 800 */ 2983 ret_val = e1000_write_phy_reg_mdic(hw, 2984 IGP01E1000_PHY_PAGE_SELECT, 2985 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2986 2987 /* Write the page 800 offset value using opcode 0x11 */ 2988 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2989 if (ret_val) { 2990 DEBUGOUT("Could not write address opcode to page 800\n"); 2991 goto out; 2992 } 2993 2994 if (read) { 2995 /* Read the page 800 value using opcode 0x12 */ 2996 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2997 data); 2998 } else { 2999 /* Write the page 800 value using opcode 0x12 */ 3000 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3001 *data); 3002 } 3003 3004 if (ret_val) { 3005 DEBUGOUT("Could not access data value from page 800\n"); 3006 goto out; 3007 } 3008 3009 /* 3010 * Restore 769_17.2 to its original value 3011 * Set page 769 3012 */ 3013 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3014 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3015 3016 /* Clear 769_17.2 */ 3017 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3018 if (ret_val) { 3019 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 3020 goto out; 3021 } 3022 3023 out: 3024 return ret_val; 3025 } 3026 3027 /** 3028 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3029 * @hw: pointer to the HW structure 3030 * 3031 * In the case of a PHY power down to save power, or to turn off link during a 3032 * driver unload, or wake on lan is not enabled, restore the link to previous 3033 * settings. 3034 **/ 3035 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3036 { 3037 u16 mii_reg = 0; 3038 3039 /* The PHY will retain its settings across a power down/up cycle */ 3040 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3041 mii_reg &= ~MII_CR_POWER_DOWN; 3042 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3043 } 3044 3045 /** 3046 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3047 * @hw: pointer to the HW structure 3048 * 3049 * In the case of a PHY power down to save power, or to turn off link during a 3050 * driver unload, or wake on lan is not enabled, restore the link to previous 3051 * settings. 3052 **/ 3053 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3054 { 3055 u16 mii_reg = 0; 3056 3057 /* The PHY will retain its settings across a power down/up cycle */ 3058 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3059 mii_reg |= MII_CR_POWER_DOWN; 3060 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3061 msec_delay(1); 3062 } 3063 3064 /** 3065 * __e1000_read_phy_reg_hv - Read HV PHY register 3066 * @hw: pointer to the HW structure 3067 * @offset: register offset to be read 3068 * @data: pointer to the read data 3069 * @locked: semaphore has already been acquired or not 3070 * 3071 * Acquires semaphore, if necessary, then reads the PHY register at offset 3072 * and stores the retrieved information in data. Release any acquired 3073 * semaphore before exiting. 3074 **/ 3075 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3076 bool locked) 3077 { 3078 s32 ret_val; 3079 u16 page = BM_PHY_REG_PAGE(offset); 3080 u16 reg = BM_PHY_REG_NUM(offset); 3081 3082 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3083 3084 if (!locked) { 3085 ret_val = hw->phy.ops.acquire(hw); 3086 if (ret_val) 3087 return ret_val; 3088 } 3089 3090 /* Page 800 works differently than the rest so it has its own func */ 3091 if (page == BM_WUC_PAGE) { 3092 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3093 data, TRUE); 3094 goto out; 3095 } 3096 3097 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3098 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3099 data, TRUE); 3100 goto out; 3101 } 3102 3103 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3104 3105 if (page == HV_INTC_FC_PAGE_START) 3106 page = 0; 3107 3108 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3109 u32 phy_addr = hw->phy.addr; 3110 3111 hw->phy.addr = 1; 3112 3113 /* Page is shifted left, PHY expects (page x 32) */ 3114 ret_val = e1000_write_phy_reg_mdic(hw, 3115 IGP01E1000_PHY_PAGE_SELECT, 3116 (page << IGP_PAGE_SHIFT)); 3117 hw->phy.addr = phy_addr; 3118 3119 if (ret_val) 3120 goto out; 3121 } 3122 3123 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3124 data); 3125 out: 3126 if (!locked) 3127 hw->phy.ops.release(hw); 3128 3129 return ret_val; 3130 } 3131 3132 /** 3133 * e1000_read_phy_reg_hv - Read HV PHY register 3134 * @hw: pointer to the HW structure 3135 * @offset: register offset to be read 3136 * @data: pointer to the read data 3137 * 3138 * Acquires semaphore then reads the PHY register at offset and stores 3139 * the retrieved information in data. Release the acquired semaphore 3140 * before exiting. 3141 **/ 3142 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3143 { 3144 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE); 3145 } 3146 3147 /** 3148 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3149 * @hw: pointer to the HW structure 3150 * @offset: register offset to be read 3151 * @data: pointer to the read data 3152 * 3153 * Reads the PHY register at offset and stores the retrieved information 3154 * in data. Assumes semaphore already acquired. 3155 **/ 3156 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3157 { 3158 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE); 3159 } 3160 3161 /** 3162 * __e1000_write_phy_reg_hv - Write HV PHY register 3163 * @hw: pointer to the HW structure 3164 * @offset: register offset to write to 3165 * @data: data to write at register offset 3166 * @locked: semaphore has already been acquired or not 3167 * 3168 * Acquires semaphore, if necessary, then writes the data to PHY register 3169 * at the offset. Release any acquired semaphores before exiting. 3170 **/ 3171 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3172 bool locked) 3173 { 3174 s32 ret_val; 3175 u16 page = BM_PHY_REG_PAGE(offset); 3176 u16 reg = BM_PHY_REG_NUM(offset); 3177 3178 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3179 3180 if (!locked) { 3181 ret_val = hw->phy.ops.acquire(hw); 3182 if (ret_val) 3183 return ret_val; 3184 } 3185 3186 /* Page 800 works differently than the rest so it has its own func */ 3187 if (page == BM_WUC_PAGE) { 3188 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3189 &data, FALSE); 3190 goto out; 3191 } 3192 3193 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3194 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3195 &data, FALSE); 3196 goto out; 3197 } 3198 3199 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3200 3201 if (page == HV_INTC_FC_PAGE_START) 3202 page = 0; 3203 3204 /* 3205 * Workaround MDIO accesses being disabled after entering IEEE Power 3206 * Down (whenever bit 11 of the PHY Control register is set) 3207 */ 3208 if ((hw->phy.type == e1000_phy_82578) && 3209 (hw->phy.revision >= 1) && 3210 (hw->phy.addr == 2) && 3211 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 3212 (data & (1 << 11))) { 3213 u16 data2 = 0x7EFF; 3214 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 3215 &data2, FALSE); 3216 if (ret_val) 3217 goto out; 3218 } 3219 3220 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3221 u32 phy_addr = hw->phy.addr; 3222 3223 hw->phy.addr = 1; 3224 3225 /* Page is shifted left, PHY expects (page x 32) */ 3226 ret_val = e1000_write_phy_reg_mdic(hw, 3227 IGP01E1000_PHY_PAGE_SELECT, 3228 (page << IGP_PAGE_SHIFT)); 3229 hw->phy.addr = phy_addr; 3230 3231 if (ret_val) 3232 goto out; 3233 } 3234 3235 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3236 data); 3237 3238 out: 3239 if (!locked) 3240 hw->phy.ops.release(hw); 3241 3242 return ret_val; 3243 } 3244 3245 /** 3246 * e1000_write_phy_reg_hv - Write HV PHY register 3247 * @hw: pointer to the HW structure 3248 * @offset: register offset to write to 3249 * @data: data to write at register offset 3250 * 3251 * Acquires semaphore then writes the data to PHY register at the offset. 3252 * Release the acquired semaphores before exiting. 3253 **/ 3254 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3255 { 3256 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE); 3257 } 3258 3259 /** 3260 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3261 * @hw: pointer to the HW structure 3262 * @offset: register offset to write to 3263 * @data: data to write at register offset 3264 * 3265 * Writes the data to PHY register at the offset. Assumes semaphore 3266 * already acquired. 3267 **/ 3268 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3269 { 3270 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE); 3271 } 3272 3273 /** 3274 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3275 * @page: page to be accessed 3276 **/ 3277 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3278 { 3279 u32 phy_addr = 2; 3280 3281 if (page >= HV_INTC_FC_PAGE_START) 3282 phy_addr = 1; 3283 3284 return phy_addr; 3285 } 3286 3287 /** 3288 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3289 * @hw: pointer to the HW structure 3290 * @offset: register offset to be read or written 3291 * @data: pointer to the data to be read or written 3292 * @read: determines if operation is read or written 3293 * 3294 * Reads the PHY register at offset and stores the retreived information 3295 * in data. Assumes semaphore already acquired. Note that the procedure 3296 * to read these regs uses the address port and data port to read/write. 3297 **/ 3298 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3299 u16 *data, bool read) 3300 { 3301 s32 ret_val; 3302 u32 addr_reg = 0; 3303 u32 data_reg = 0; 3304 3305 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3306 3307 /* This takes care of the difference with desktop vs mobile phy */ 3308 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3309 I82578_ADDR_REG : I82577_ADDR_REG; 3310 data_reg = addr_reg + 1; 3311 3312 /* All operations in this function are phy address 2 */ 3313 hw->phy.addr = 2; 3314 3315 /* masking with 0x3F to remove the page from offset */ 3316 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3317 if (ret_val) { 3318 DEBUGOUT("Could not write PHY the HV address register\n"); 3319 goto out; 3320 } 3321 3322 /* Read or write the data value next */ 3323 if (read) 3324 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3325 else 3326 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3327 3328 if (ret_val) { 3329 DEBUGOUT("Could not read data value from HV data register\n"); 3330 goto out; 3331 } 3332 3333 out: 3334 return ret_val; 3335 } 3336 3337 /** 3338 * e1000_link_stall_workaround_hv - Si workaround 3339 * @hw: pointer to the HW structure 3340 * 3341 * This function works around a Si bug where the link partner can get 3342 * a link up indication before the PHY does. If small packets are sent 3343 * by the link partner they can be placed in the packet buffer without 3344 * being properly accounted for by the PHY and will stall preventing 3345 * further packets from being received. The workaround is to clear the 3346 * packet buffer after the PHY detects link up. 3347 **/ 3348 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3349 { 3350 s32 ret_val = E1000_SUCCESS; 3351 u16 data; 3352 3353 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3354 3355 if (hw->phy.type != e1000_phy_82578) 3356 goto out; 3357 3358 /* Do not apply workaround if in PHY loopback bit 14 set */ 3359 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3360 if (data & PHY_CONTROL_LB) 3361 goto out; 3362 3363 /* check if link is up and at 1Gbps */ 3364 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3365 if (ret_val) 3366 goto out; 3367 3368 data &= BM_CS_STATUS_LINK_UP | 3369 BM_CS_STATUS_RESOLVED | 3370 BM_CS_STATUS_SPEED_MASK; 3371 3372 if (data != (BM_CS_STATUS_LINK_UP | 3373 BM_CS_STATUS_RESOLVED | 3374 BM_CS_STATUS_SPEED_1000)) 3375 goto out; 3376 3377 msec_delay(200); 3378 3379 /* flush the packets in the fifo buffer */ 3380 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3381 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3382 HV_MUX_DATA_CTRL_FORCE_SPEED); 3383 if (ret_val) 3384 goto out; 3385 3386 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3387 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3388 3389 out: 3390 return ret_val; 3391 } 3392 3393 /** 3394 * e1000_check_polarity_82577 - Checks the polarity. 3395 * @hw: pointer to the HW structure 3396 * 3397 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3398 * 3399 * Polarity is determined based on the PHY specific status register. 3400 **/ 3401 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3402 { 3403 struct e1000_phy_info *phy = &hw->phy; 3404 s32 ret_val; 3405 u16 data; 3406 3407 DEBUGFUNC("e1000_check_polarity_82577"); 3408 3409 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3410 3411 if (!ret_val) 3412 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3413 ? e1000_rev_polarity_reversed 3414 : e1000_rev_polarity_normal; 3415 3416 return ret_val; 3417 } 3418 3419 /** 3420 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3421 * @hw: pointer to the HW structure 3422 * 3423 * Calls the PHY setup function to force speed and duplex. 3424 **/ 3425 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3426 { 3427 struct e1000_phy_info *phy = &hw->phy; 3428 s32 ret_val; 3429 u16 phy_data; 3430 bool link; 3431 3432 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3433 3434 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3435 if (ret_val) 3436 goto out; 3437 3438 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3439 3440 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3441 if (ret_val) 3442 goto out; 3443 3444 usec_delay(1); 3445 3446 if (phy->autoneg_wait_to_complete) { 3447 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3448 3449 ret_val = e1000_phy_has_link_generic(hw, 3450 PHY_FORCE_LIMIT, 3451 100000, 3452 &link); 3453 if (ret_val) 3454 goto out; 3455 3456 if (!link) 3457 DEBUGOUT("Link taking longer than expected.\n"); 3458 3459 /* Try once more */ 3460 ret_val = e1000_phy_has_link_generic(hw, 3461 PHY_FORCE_LIMIT, 3462 100000, 3463 &link); 3464 if (ret_val) 3465 goto out; 3466 } 3467 3468 out: 3469 return ret_val; 3470 } 3471 3472 /** 3473 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3474 * @hw: pointer to the HW structure 3475 * 3476 * Read PHY status to determine if link is up. If link is up, then 3477 * set/determine 10base-T extended distance and polarity correction. Read 3478 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3479 * determine on the cable length, local and remote receiver. 3480 **/ 3481 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3482 { 3483 struct e1000_phy_info *phy = &hw->phy; 3484 s32 ret_val; 3485 u16 data; 3486 bool link; 3487 3488 DEBUGFUNC("e1000_get_phy_info_82577"); 3489 3490 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3491 if (ret_val) 3492 goto out; 3493 3494 if (!link) { 3495 DEBUGOUT("Phy info is only valid if link is up\n"); 3496 ret_val = -E1000_ERR_CONFIG; 3497 goto out; 3498 } 3499 3500 phy->polarity_correction = TRUE; 3501 3502 ret_val = e1000_check_polarity_82577(hw); 3503 if (ret_val) 3504 goto out; 3505 3506 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3507 if (ret_val) 3508 goto out; 3509 3510 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE; 3511 3512 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3513 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3514 ret_val = hw->phy.ops.get_cable_length(hw); 3515 if (ret_val) 3516 goto out; 3517 3518 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3519 if (ret_val) 3520 goto out; 3521 3522 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3523 ? e1000_1000t_rx_status_ok 3524 : e1000_1000t_rx_status_not_ok; 3525 3526 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3527 ? e1000_1000t_rx_status_ok 3528 : e1000_1000t_rx_status_not_ok; 3529 } else { 3530 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3531 phy->local_rx = e1000_1000t_rx_status_undefined; 3532 phy->remote_rx = e1000_1000t_rx_status_undefined; 3533 } 3534 3535 out: 3536 return ret_val; 3537 } 3538 3539 /** 3540 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3541 * @hw: pointer to the HW structure 3542 * 3543 * Reads the diagnostic status register and verifies result is valid before 3544 * placing it in the phy_cable_length field. 3545 **/ 3546 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3547 { 3548 struct e1000_phy_info *phy = &hw->phy; 3549 s32 ret_val; 3550 u16 phy_data, length; 3551 3552 DEBUGFUNC("e1000_get_cable_length_82577"); 3553 3554 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3555 if (ret_val) 3556 goto out; 3557 3558 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3559 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3560 3561 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3562 ret_val = -E1000_ERR_PHY; 3563 3564 phy->cable_length = length; 3565 3566 out: 3567 return ret_val; 3568 } 3569