1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = 46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = 52 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 53 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 54 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 55 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 56 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 57 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 58 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 59 104, 109, 114, 118, 121, 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.read_reg = e1000_null_read_reg; 86 phy->ops.release = e1000_null_phy_generic; 87 phy->ops.reset = e1000_null_ops_generic; 88 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 89 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 90 phy->ops.write_reg = e1000_null_write_reg; 91 phy->ops.power_up = e1000_null_phy_generic; 92 phy->ops.power_down = e1000_null_phy_generic; 93 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 94 } 95 96 /** 97 * e1000_null_read_reg - No-op function, return 0 98 * @hw: pointer to the HW structure 99 **/ 100 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 101 { 102 DEBUGFUNC("e1000_null_read_reg"); 103 return E1000_SUCCESS; 104 } 105 106 /** 107 * e1000_null_phy_generic - No-op function, return void 108 * @hw: pointer to the HW structure 109 **/ 110 void e1000_null_phy_generic(struct e1000_hw *hw) 111 { 112 DEBUGFUNC("e1000_null_phy_generic"); 113 return; 114 } 115 116 /** 117 * e1000_null_lplu_state - No-op function, return 0 118 * @hw: pointer to the HW structure 119 **/ 120 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 121 { 122 DEBUGFUNC("e1000_null_lplu_state"); 123 return E1000_SUCCESS; 124 } 125 126 /** 127 * e1000_null_write_reg - No-op function, return 0 128 * @hw: pointer to the HW structure 129 **/ 130 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 131 { 132 DEBUGFUNC("e1000_null_write_reg"); 133 return E1000_SUCCESS; 134 } 135 136 /** 137 * e1000_check_reset_block_generic - Check if PHY reset is blocked 138 * @hw: pointer to the HW structure 139 * 140 * Read the PHY management control register and check whether a PHY reset 141 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 142 * return E1000_BLK_PHY_RESET (12). 143 **/ 144 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 145 { 146 u32 manc; 147 148 DEBUGFUNC("e1000_check_reset_block"); 149 150 manc = E1000_READ_REG(hw, E1000_MANC); 151 152 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 153 E1000_BLK_PHY_RESET : E1000_SUCCESS; 154 } 155 156 /** 157 * e1000_get_phy_id - Retrieve the PHY ID and revision 158 * @hw: pointer to the HW structure 159 * 160 * Reads the PHY registers and stores the PHY ID and possibly the PHY 161 * revision in the hardware structure. 162 **/ 163 s32 e1000_get_phy_id(struct e1000_hw *hw) 164 { 165 struct e1000_phy_info *phy = &hw->phy; 166 s32 ret_val = E1000_SUCCESS; 167 u16 phy_id; 168 u16 retry_count = 0; 169 170 DEBUGFUNC("e1000_get_phy_id"); 171 172 if (!(phy->ops.read_reg)) 173 goto out; 174 175 while (retry_count < 2) { 176 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 177 if (ret_val) 178 goto out; 179 180 phy->id = (u32)(phy_id << 16); 181 usec_delay(20); 182 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 183 if (ret_val) 184 goto out; 185 186 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 187 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 188 189 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 190 goto out; 191 192 /* 193 * If the PHY ID is still unknown, we may have an 82577 without link. 194 * We will try again after setting Slow MDIC mode. No harm in trying 195 * again in this case since the PHY ID is unknown at this point anyway 196 */ 197 ret_val = e1000_set_mdio_slow_mode_hv(hw, TRUE); 198 if (ret_val) 199 goto out; 200 201 retry_count++; 202 } 203 out: 204 /* Revert to MDIO fast mode, if applicable */ 205 if (retry_count) 206 ret_val = e1000_set_mdio_slow_mode_hv(hw, FALSE); 207 208 return ret_val; 209 } 210 211 /** 212 * e1000_phy_reset_dsp_generic - Reset PHY DSP 213 * @hw: pointer to the HW structure 214 * 215 * Reset the digital signal processor. 216 **/ 217 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 218 { 219 s32 ret_val = E1000_SUCCESS; 220 221 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 222 223 if (!(hw->phy.ops.write_reg)) 224 goto out; 225 226 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 227 if (ret_val) 228 goto out; 229 230 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 231 232 out: 233 return ret_val; 234 } 235 236 /** 237 * e1000_read_phy_reg_mdic - Read MDI control register 238 * @hw: pointer to the HW structure 239 * @offset: register offset to be read 240 * @data: pointer to the read data 241 * 242 * Reads the MDI control register in the PHY at offset and stores the 243 * information read to data. 244 **/ 245 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 246 { 247 struct e1000_phy_info *phy = &hw->phy; 248 u32 i, mdic = 0; 249 s32 ret_val = E1000_SUCCESS; 250 251 DEBUGFUNC("e1000_read_phy_reg_mdic"); 252 253 /* 254 * Set up Op-code, Phy Address, and register offset in the MDI 255 * Control register. The MAC will take care of interfacing with the 256 * PHY to retrieve the desired data. 257 */ 258 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 259 (phy->addr << E1000_MDIC_PHY_SHIFT) | 260 (E1000_MDIC_OP_READ)); 261 262 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 263 264 /* Workaround for Si errata */ 265 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 266 msec_delay(10); 267 268 /* 269 * Poll the ready bit to see if the MDI read completed 270 * Increasing the time out as testing showed failures with 271 * the lower time out 272 */ 273 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 274 usec_delay(50); 275 mdic = E1000_READ_REG(hw, E1000_MDIC); 276 if (mdic & E1000_MDIC_READY) 277 break; 278 } 279 if (!(mdic & E1000_MDIC_READY)) { 280 DEBUGOUT("MDI Read did not complete\n"); 281 ret_val = -E1000_ERR_PHY; 282 goto out; 283 } 284 if (mdic & E1000_MDIC_ERROR) { 285 DEBUGOUT("MDI Error\n"); 286 ret_val = -E1000_ERR_PHY; 287 goto out; 288 } 289 *data = (u16) mdic; 290 291 out: 292 return ret_val; 293 } 294 295 /** 296 * e1000_write_phy_reg_mdic - Write MDI control register 297 * @hw: pointer to the HW structure 298 * @offset: register offset to write to 299 * @data: data to write to register at offset 300 * 301 * Writes data to MDI control register in the PHY at offset. 302 **/ 303 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 304 { 305 struct e1000_phy_info *phy = &hw->phy; 306 u32 i, mdic = 0; 307 s32 ret_val = E1000_SUCCESS; 308 309 DEBUGFUNC("e1000_write_phy_reg_mdic"); 310 311 /* 312 * Set up Op-code, Phy Address, and register offset in the MDI 313 * Control register. The MAC will take care of interfacing with the 314 * PHY to retrieve the desired data. 315 */ 316 mdic = (((u32)data) | 317 (offset << E1000_MDIC_REG_SHIFT) | 318 (phy->addr << E1000_MDIC_PHY_SHIFT) | 319 (E1000_MDIC_OP_WRITE)); 320 321 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 322 323 /* Workaround for Si errata */ 324 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 325 msec_delay(10); 326 327 /* 328 * Poll the ready bit to see if the MDI read completed 329 * Increasing the time out as testing showed failures with 330 * the lower time out 331 */ 332 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 333 usec_delay(50); 334 mdic = E1000_READ_REG(hw, E1000_MDIC); 335 if (mdic & E1000_MDIC_READY) 336 break; 337 } 338 if (!(mdic & E1000_MDIC_READY)) { 339 DEBUGOUT("MDI Write did not complete\n"); 340 ret_val = -E1000_ERR_PHY; 341 goto out; 342 } 343 if (mdic & E1000_MDIC_ERROR) { 344 DEBUGOUT("MDI Error\n"); 345 ret_val = -E1000_ERR_PHY; 346 goto out; 347 } 348 349 out: 350 return ret_val; 351 } 352 353 /** 354 * e1000_read_phy_reg_m88 - Read m88 PHY register 355 * @hw: pointer to the HW structure 356 * @offset: register offset to be read 357 * @data: pointer to the read data 358 * 359 * Acquires semaphore, if necessary, then reads the PHY register at offset 360 * and storing the retrieved information in data. Release any acquired 361 * semaphores before exiting. 362 **/ 363 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 364 { 365 s32 ret_val = E1000_SUCCESS; 366 367 DEBUGFUNC("e1000_read_phy_reg_m88"); 368 369 if (!(hw->phy.ops.acquire)) 370 goto out; 371 372 ret_val = hw->phy.ops.acquire(hw); 373 if (ret_val) 374 goto out; 375 376 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 377 data); 378 379 hw->phy.ops.release(hw); 380 381 out: 382 return ret_val; 383 } 384 385 /** 386 * e1000_write_phy_reg_m88 - Write m88 PHY register 387 * @hw: pointer to the HW structure 388 * @offset: register offset to write to 389 * @data: data to write at register offset 390 * 391 * Acquires semaphore, if necessary, then writes the data to PHY register 392 * at the offset. Release any acquired semaphores before exiting. 393 **/ 394 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 395 { 396 s32 ret_val = E1000_SUCCESS; 397 398 DEBUGFUNC("e1000_write_phy_reg_m88"); 399 400 if (!(hw->phy.ops.acquire)) 401 goto out; 402 403 ret_val = hw->phy.ops.acquire(hw); 404 if (ret_val) 405 goto out; 406 407 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 408 data); 409 410 hw->phy.ops.release(hw); 411 412 out: 413 return ret_val; 414 } 415 416 /** 417 * e1000_read_phy_reg_igp - Read igp PHY register 418 * @hw: pointer to the HW structure 419 * @offset: register offset to be read 420 * @data: pointer to the read data 421 * 422 * Acquires semaphore, if necessary, then reads the PHY register at offset 423 * and storing the retrieved information in data. Release any acquired 424 * semaphores before exiting. 425 **/ 426 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 427 { 428 s32 ret_val = E1000_SUCCESS; 429 430 DEBUGFUNC("e1000_read_phy_reg_igp"); 431 432 if (!(hw->phy.ops.acquire)) 433 goto out; 434 435 ret_val = hw->phy.ops.acquire(hw); 436 if (ret_val) 437 goto out; 438 439 if (offset > MAX_PHY_MULTI_PAGE_REG) { 440 ret_val = e1000_write_phy_reg_mdic(hw, 441 IGP01E1000_PHY_PAGE_SELECT, 442 (u16)offset); 443 if (ret_val) { 444 hw->phy.ops.release(hw); 445 goto out; 446 } 447 } 448 449 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 450 data); 451 452 hw->phy.ops.release(hw); 453 454 out: 455 return ret_val; 456 } 457 458 /** 459 * e1000_write_phy_reg_igp - Write igp PHY register 460 * @hw: pointer to the HW structure 461 * @offset: register offset to write to 462 * @data: data to write at register offset 463 * 464 * Acquires semaphore, if necessary, then writes the data to PHY register 465 * at the offset. Release any acquired semaphores before exiting. 466 **/ 467 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 468 { 469 s32 ret_val = E1000_SUCCESS; 470 471 DEBUGFUNC("e1000_write_phy_reg_igp"); 472 473 if (!(hw->phy.ops.acquire)) 474 goto out; 475 476 ret_val = hw->phy.ops.acquire(hw); 477 if (ret_val) 478 goto out; 479 480 if (offset > MAX_PHY_MULTI_PAGE_REG) { 481 ret_val = e1000_write_phy_reg_mdic(hw, 482 IGP01E1000_PHY_PAGE_SELECT, 483 (u16)offset); 484 if (ret_val) { 485 hw->phy.ops.release(hw); 486 goto out; 487 } 488 } 489 490 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 491 data); 492 493 hw->phy.ops.release(hw); 494 495 out: 496 return ret_val; 497 } 498 499 /** 500 * e1000_read_kmrn_reg_generic - Read kumeran register 501 * @hw: pointer to the HW structure 502 * @offset: register offset to be read 503 * @data: pointer to the read data 504 * 505 * Acquires semaphore, if necessary. Then reads the PHY register at offset 506 * using the kumeran interface. The information retrieved is stored in data. 507 * Release any acquired semaphores before exiting. 508 **/ 509 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 510 { 511 u32 kmrnctrlsta; 512 s32 ret_val = E1000_SUCCESS; 513 514 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 515 516 if (!(hw->phy.ops.acquire)) 517 goto out; 518 519 ret_val = hw->phy.ops.acquire(hw); 520 if (ret_val) 521 goto out; 522 523 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 524 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 525 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 526 527 usec_delay(2); 528 529 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 530 *data = (u16)kmrnctrlsta; 531 532 hw->phy.ops.release(hw); 533 534 out: 535 return ret_val; 536 } 537 538 /** 539 * e1000_write_kmrn_reg_generic - Write kumeran register 540 * @hw: pointer to the HW structure 541 * @offset: register offset to write to 542 * @data: data to write at register offset 543 * 544 * Acquires semaphore, if necessary. Then write the data to PHY register 545 * at the offset using the kumeran interface. Release any acquired semaphores 546 * before exiting. 547 **/ 548 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 549 { 550 u32 kmrnctrlsta; 551 s32 ret_val = E1000_SUCCESS; 552 553 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 554 555 if (!(hw->phy.ops.acquire)) 556 goto out; 557 558 ret_val = hw->phy.ops.acquire(hw); 559 if (ret_val) 560 goto out; 561 562 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 563 E1000_KMRNCTRLSTA_OFFSET) | data; 564 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 565 566 usec_delay(2); 567 hw->phy.ops.release(hw); 568 569 out: 570 return ret_val; 571 } 572 573 /** 574 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 575 * @hw: pointer to the HW structure 576 * 577 * Sets up Carrier-sense on Transmit and downshift values. 578 **/ 579 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 580 { 581 struct e1000_phy_info *phy = &hw->phy; 582 s32 ret_val; 583 u16 phy_data; 584 585 DEBUGFUNC("e1000_copper_link_setup_82577"); 586 587 if (phy->reset_disable) { 588 ret_val = E1000_SUCCESS; 589 goto out; 590 } 591 592 /* Enable CRS on TX. This must be set for half-duplex operation. */ 593 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); 594 if (ret_val) 595 goto out; 596 597 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 598 599 /* Enable downshift */ 600 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 601 602 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); 603 if (ret_val) 604 goto out; 605 606 /* Set number of link attempts before downshift */ 607 ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data); 608 if (ret_val) 609 goto out; 610 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; 611 ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data); 612 613 out: 614 return ret_val; 615 } 616 617 /** 618 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 619 * @hw: pointer to the HW structure 620 * 621 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 622 * and downshift values are set also. 623 **/ 624 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 625 { 626 struct e1000_phy_info *phy = &hw->phy; 627 s32 ret_val; 628 u16 phy_data; 629 630 DEBUGFUNC("e1000_copper_link_setup_m88"); 631 632 if (phy->reset_disable) { 633 ret_val = E1000_SUCCESS; 634 goto out; 635 } 636 637 /* Enable CRS on TX. This must be set for half-duplex operation. */ 638 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 639 if (ret_val) 640 goto out; 641 642 /* For BM PHY this bit is downshift enable */ 643 if (phy->type != e1000_phy_bm) 644 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 645 646 /* 647 * Options: 648 * MDI/MDI-X = 0 (default) 649 * 0 - Auto for all speeds 650 * 1 - MDI mode 651 * 2 - MDI-X mode 652 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 653 */ 654 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 655 656 switch (phy->mdix) { 657 case 1: 658 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 659 break; 660 case 2: 661 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 662 break; 663 case 3: 664 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 665 break; 666 case 0: 667 default: 668 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 669 break; 670 } 671 672 /* 673 * Options: 674 * disable_polarity_correction = 0 (default) 675 * Automatic Correction for Reversed Cable Polarity 676 * 0 - Disabled 677 * 1 - Enabled 678 */ 679 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 680 if (phy->disable_polarity_correction == 1) 681 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 682 683 /* Enable downshift on BM (disabled by default) */ 684 if (phy->type == e1000_phy_bm) 685 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 686 687 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 688 if (ret_val) 689 goto out; 690 691 if ((phy->type == e1000_phy_m88) && 692 (phy->revision < E1000_REVISION_4) && 693 (phy->id != BME1000_E_PHY_ID_R2)) { 694 /* 695 * Force TX_CLK in the Extended PHY Specific Control Register 696 * to 25MHz clock. 697 */ 698 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 699 &phy_data); 700 if (ret_val) 701 goto out; 702 703 phy_data |= M88E1000_EPSCR_TX_CLK_25; 704 705 if ((phy->revision == E1000_REVISION_2) && 706 (phy->id == M88E1111_I_PHY_ID)) { 707 /* 82573L PHY - set the downshift counter to 5x. */ 708 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 709 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 710 } else { 711 /* Configure Master and Slave downshift values */ 712 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 713 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 714 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 715 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 716 } 717 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 718 phy_data); 719 if (ret_val) 720 goto out; 721 } 722 723 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 724 /* Set PHY page 0, register 29 to 0x0003 */ 725 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 726 if (ret_val) 727 goto out; 728 729 /* Set PHY page 0, register 30 to 0x0000 */ 730 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 731 if (ret_val) 732 goto out; 733 } 734 735 /* Commit the changes. */ 736 ret_val = phy->ops.commit(hw); 737 if (ret_val) { 738 DEBUGOUT("Error committing the PHY changes\n"); 739 goto out; 740 } 741 742 if (phy->type == e1000_phy_82578) { 743 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 744 &phy_data); 745 if (ret_val) 746 goto out; 747 748 /* 82578 PHY - set the downshift count to 1x. */ 749 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 750 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 751 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 752 phy_data); 753 if (ret_val) 754 goto out; 755 } 756 757 out: 758 return ret_val; 759 } 760 761 /** 762 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 763 * @hw: pointer to the HW structure 764 * 765 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 766 * igp PHY's. 767 **/ 768 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 769 { 770 struct e1000_phy_info *phy = &hw->phy; 771 s32 ret_val; 772 u16 data; 773 774 DEBUGFUNC("e1000_copper_link_setup_igp"); 775 776 if (phy->reset_disable) { 777 ret_val = E1000_SUCCESS; 778 goto out; 779 } 780 781 ret_val = hw->phy.ops.reset(hw); 782 if (ret_val) { 783 DEBUGOUT("Error resetting the PHY.\n"); 784 goto out; 785 } 786 787 /* 788 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 789 * timeout issues when LFS is enabled. 790 */ 791 msec_delay(100); 792 793 /* 794 * The NVM settings will configure LPLU in D3 for 795 * non-IGP1 PHYs. 796 */ 797 if (phy->type == e1000_phy_igp) { 798 /* disable lplu d3 during driver init */ 799 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 800 if (ret_val) { 801 DEBUGOUT("Error Disabling LPLU D3\n"); 802 goto out; 803 } 804 } 805 806 /* disable lplu d0 during driver init */ 807 if (hw->phy.ops.set_d0_lplu_state) { 808 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 809 if (ret_val) { 810 DEBUGOUT("Error Disabling LPLU D0\n"); 811 goto out; 812 } 813 } 814 /* Configure mdi-mdix settings */ 815 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 816 if (ret_val) 817 goto out; 818 819 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 820 821 switch (phy->mdix) { 822 case 1: 823 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 824 break; 825 case 2: 826 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 827 break; 828 case 0: 829 default: 830 data |= IGP01E1000_PSCR_AUTO_MDIX; 831 break; 832 } 833 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 834 if (ret_val) 835 goto out; 836 837 /* set auto-master slave resolution settings */ 838 if (hw->mac.autoneg) { 839 /* 840 * when autonegotiation advertisement is only 1000Mbps then we 841 * should disable SmartSpeed and enable Auto MasterSlave 842 * resolution as hardware default. 843 */ 844 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 845 /* Disable SmartSpeed */ 846 ret_val = phy->ops.read_reg(hw, 847 IGP01E1000_PHY_PORT_CONFIG, 848 &data); 849 if (ret_val) 850 goto out; 851 852 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 853 ret_val = phy->ops.write_reg(hw, 854 IGP01E1000_PHY_PORT_CONFIG, 855 data); 856 if (ret_val) 857 goto out; 858 859 /* Set auto Master/Slave resolution process */ 860 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 861 if (ret_val) 862 goto out; 863 864 data &= ~CR_1000T_MS_ENABLE; 865 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 866 if (ret_val) 867 goto out; 868 } 869 870 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 871 if (ret_val) 872 goto out; 873 874 /* load defaults for future use */ 875 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 876 ((data & CR_1000T_MS_VALUE) ? 877 e1000_ms_force_master : 878 e1000_ms_force_slave) : 879 e1000_ms_auto; 880 881 switch (phy->ms_type) { 882 case e1000_ms_force_master: 883 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 884 break; 885 case e1000_ms_force_slave: 886 data |= CR_1000T_MS_ENABLE; 887 data &= ~(CR_1000T_MS_VALUE); 888 break; 889 case e1000_ms_auto: 890 data &= ~CR_1000T_MS_ENABLE; 891 default: 892 break; 893 } 894 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 895 if (ret_val) 896 goto out; 897 } 898 899 out: 900 return ret_val; 901 } 902 903 /** 904 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 905 * @hw: pointer to the HW structure 906 * 907 * Performs initial bounds checking on autoneg advertisement parameter, then 908 * configure to advertise the full capability. Setup the PHY to autoneg 909 * and restart the negotiation process between the link partner. If 910 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 911 **/ 912 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 913 { 914 struct e1000_phy_info *phy = &hw->phy; 915 s32 ret_val; 916 u16 phy_ctrl; 917 918 DEBUGFUNC("e1000_copper_link_autoneg"); 919 920 /* 921 * Perform some bounds checking on the autoneg advertisement 922 * parameter. 923 */ 924 phy->autoneg_advertised &= phy->autoneg_mask; 925 926 /* 927 * If autoneg_advertised is zero, we assume it was not defaulted 928 * by the calling code so we set to advertise full capability. 929 */ 930 if (phy->autoneg_advertised == 0) 931 phy->autoneg_advertised = phy->autoneg_mask; 932 933 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 934 ret_val = e1000_phy_setup_autoneg(hw); 935 if (ret_val) { 936 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 937 goto out; 938 } 939 DEBUGOUT("Restarting Auto-Neg\n"); 940 941 /* 942 * Restart auto-negotiation by setting the Auto Neg Enable bit and 943 * the Auto Neg Restart bit in the PHY control register. 944 */ 945 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 946 if (ret_val) 947 goto out; 948 949 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 950 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 951 if (ret_val) 952 goto out; 953 954 /* 955 * Does the user want to wait for Auto-Neg to complete here, or 956 * check at a later time (for example, callback routine). 957 */ 958 if (phy->autoneg_wait_to_complete) { 959 ret_val = hw->mac.ops.wait_autoneg(hw); 960 if (ret_val) { 961 DEBUGOUT("Error while waiting for " 962 "autoneg to complete\n"); 963 goto out; 964 } 965 } 966 967 hw->mac.get_link_status = TRUE; 968 969 out: 970 return ret_val; 971 } 972 973 /** 974 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 975 * @hw: pointer to the HW structure 976 * 977 * Reads the MII auto-neg advertisement register and/or the 1000T control 978 * register and if the PHY is already setup for auto-negotiation, then 979 * return successful. Otherwise, setup advertisement and flow control to 980 * the appropriate values for the wanted auto-negotiation. 981 **/ 982 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 983 { 984 struct e1000_phy_info *phy = &hw->phy; 985 s32 ret_val; 986 u16 mii_autoneg_adv_reg; 987 u16 mii_1000t_ctrl_reg = 0; 988 989 DEBUGFUNC("e1000_phy_setup_autoneg"); 990 991 phy->autoneg_advertised &= phy->autoneg_mask; 992 993 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 994 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 995 if (ret_val) 996 goto out; 997 998 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 999 /* Read the MII 1000Base-T Control Register (Address 9). */ 1000 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1001 &mii_1000t_ctrl_reg); 1002 if (ret_val) 1003 goto out; 1004 } 1005 1006 /* 1007 * Need to parse both autoneg_advertised and fc and set up 1008 * the appropriate PHY registers. First we will parse for 1009 * autoneg_advertised software override. Since we can advertise 1010 * a plethora of combinations, we need to check each bit 1011 * individually. 1012 */ 1013 1014 /* 1015 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1016 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1017 * the 1000Base-T Control Register (Address 9). 1018 */ 1019 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1020 NWAY_AR_100TX_HD_CAPS | 1021 NWAY_AR_10T_FD_CAPS | 1022 NWAY_AR_10T_HD_CAPS); 1023 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1024 1025 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1026 1027 /* Do we want to advertise 10 Mb Half Duplex? */ 1028 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1029 DEBUGOUT("Advertise 10mb Half duplex\n"); 1030 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1031 } 1032 1033 /* Do we want to advertise 10 Mb Full Duplex? */ 1034 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1035 DEBUGOUT("Advertise 10mb Full duplex\n"); 1036 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1037 } 1038 1039 /* Do we want to advertise 100 Mb Half Duplex? */ 1040 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1041 DEBUGOUT("Advertise 100mb Half duplex\n"); 1042 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1043 } 1044 1045 /* Do we want to advertise 100 Mb Full Duplex? */ 1046 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1047 DEBUGOUT("Advertise 100mb Full duplex\n"); 1048 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1049 } 1050 1051 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1052 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1053 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1054 1055 /* Do we want to advertise 1000 Mb Full Duplex? */ 1056 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1057 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1058 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1059 } 1060 1061 /* 1062 * Check for a software override of the flow control settings, and 1063 * setup the PHY advertisement registers accordingly. If 1064 * auto-negotiation is enabled, then software will have to set the 1065 * "PAUSE" bits to the correct value in the Auto-Negotiation 1066 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1067 * negotiation. 1068 * 1069 * The possible values of the "fc" parameter are: 1070 * 0: Flow control is completely disabled 1071 * 1: Rx flow control is enabled (we can receive pause frames 1072 * but not send pause frames). 1073 * 2: Tx flow control is enabled (we can send pause frames 1074 * but we do not support receiving pause frames). 1075 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1076 * other: No software override. The flow control configuration 1077 * in the EEPROM is used. 1078 */ 1079 switch (hw->fc.current_mode) { 1080 case e1000_fc_none: 1081 /* 1082 * Flow control (Rx & Tx) is completely disabled by a 1083 * software over-ride. 1084 */ 1085 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1086 break; 1087 case e1000_fc_rx_pause: 1088 /* 1089 * Rx Flow control is enabled, and Tx Flow control is 1090 * disabled, by a software over-ride. 1091 * 1092 * Since there really isn't a way to advertise that we are 1093 * capable of Rx Pause ONLY, we will advertise that we 1094 * support both symmetric and asymmetric Rx PAUSE. Later 1095 * (in e1000_config_fc_after_link_up) we will disable the 1096 * hw's ability to send PAUSE frames. 1097 */ 1098 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1099 break; 1100 case e1000_fc_tx_pause: 1101 /* 1102 * Tx Flow control is enabled, and Rx Flow control is 1103 * disabled, by a software over-ride. 1104 */ 1105 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1106 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1107 break; 1108 case e1000_fc_full: 1109 /* 1110 * Flow control (both Rx and Tx) is enabled by a software 1111 * over-ride. 1112 */ 1113 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1114 break; 1115 default: 1116 DEBUGOUT("Flow control param set incorrectly\n"); 1117 ret_val = -E1000_ERR_CONFIG; 1118 goto out; 1119 } 1120 1121 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1122 if (ret_val) 1123 goto out; 1124 1125 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1126 1127 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1128 ret_val = phy->ops.write_reg(hw, 1129 PHY_1000T_CTRL, 1130 mii_1000t_ctrl_reg); 1131 if (ret_val) 1132 goto out; 1133 } 1134 1135 out: 1136 return ret_val; 1137 } 1138 1139 /** 1140 * e1000_setup_copper_link_generic - Configure copper link settings 1141 * @hw: pointer to the HW structure 1142 * 1143 * Calls the appropriate function to configure the link for auto-neg or forced 1144 * speed and duplex. Then we check for link, once link is established calls 1145 * to configure collision distance and flow control are called. If link is 1146 * not established, we return -E1000_ERR_PHY (-2). 1147 **/ 1148 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1149 { 1150 s32 ret_val; 1151 bool link; 1152 1153 DEBUGFUNC("e1000_setup_copper_link_generic"); 1154 1155 if (hw->mac.autoneg) { 1156 /* 1157 * Setup autoneg and flow control advertisement and perform 1158 * autonegotiation. 1159 */ 1160 ret_val = e1000_copper_link_autoneg(hw); 1161 if (ret_val) 1162 goto out; 1163 } else { 1164 /* 1165 * PHY will be set to 10H, 10F, 100H or 100F 1166 * depending on user settings. 1167 */ 1168 DEBUGOUT("Forcing Speed and Duplex\n"); 1169 ret_val = hw->phy.ops.force_speed_duplex(hw); 1170 if (ret_val) { 1171 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1172 goto out; 1173 } 1174 } 1175 1176 /* 1177 * Check link status. Wait up to 100 microseconds for link to become 1178 * valid. 1179 */ 1180 ret_val = e1000_phy_has_link_generic(hw, 1181 COPPER_LINK_UP_LIMIT, 1182 10, 1183 &link); 1184 if (ret_val) 1185 goto out; 1186 1187 if (link) { 1188 DEBUGOUT("Valid link established!!!\n"); 1189 e1000_config_collision_dist_generic(hw); 1190 ret_val = e1000_config_fc_after_link_up_generic(hw); 1191 } else { 1192 DEBUGOUT("Unable to establish link!!!\n"); 1193 } 1194 1195 out: 1196 return ret_val; 1197 } 1198 1199 /** 1200 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1201 * @hw: pointer to the HW structure 1202 * 1203 * Calls the PHY setup function to force speed and duplex. Clears the 1204 * auto-crossover to force MDI manually. Waits for link and returns 1205 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1206 **/ 1207 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1208 { 1209 struct e1000_phy_info *phy = &hw->phy; 1210 s32 ret_val; 1211 u16 phy_data; 1212 bool link; 1213 1214 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1215 1216 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1217 if (ret_val) 1218 goto out; 1219 1220 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1221 1222 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1223 if (ret_val) 1224 goto out; 1225 1226 /* 1227 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1228 * forced whenever speed and duplex are forced. 1229 */ 1230 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1231 if (ret_val) 1232 goto out; 1233 1234 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1235 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1236 1237 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1238 if (ret_val) 1239 goto out; 1240 1241 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1242 1243 usec_delay(1); 1244 1245 if (phy->autoneg_wait_to_complete) { 1246 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1247 1248 ret_val = e1000_phy_has_link_generic(hw, 1249 PHY_FORCE_LIMIT, 1250 100000, 1251 &link); 1252 if (ret_val) 1253 goto out; 1254 1255 if (!link) 1256 DEBUGOUT("Link taking longer than expected.\n"); 1257 1258 /* Try once more */ 1259 ret_val = e1000_phy_has_link_generic(hw, 1260 PHY_FORCE_LIMIT, 1261 100000, 1262 &link); 1263 if (ret_val) 1264 goto out; 1265 } 1266 1267 out: 1268 return ret_val; 1269 } 1270 1271 /** 1272 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1273 * @hw: pointer to the HW structure 1274 * 1275 * Calls the PHY setup function to force speed and duplex. Clears the 1276 * auto-crossover to force MDI manually. Resets the PHY to commit the 1277 * changes. If time expires while waiting for link up, we reset the DSP. 1278 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1279 * successful completion, else return corresponding error code. 1280 **/ 1281 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1282 { 1283 struct e1000_phy_info *phy = &hw->phy; 1284 s32 ret_val; 1285 u16 phy_data; 1286 bool link; 1287 1288 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1289 1290 /* 1291 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1292 * forced whenever speed and duplex are forced. 1293 */ 1294 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1295 if (ret_val) 1296 goto out; 1297 1298 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1299 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1300 if (ret_val) 1301 goto out; 1302 1303 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1304 1305 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1306 if (ret_val) 1307 goto out; 1308 1309 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1310 1311 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1312 if (ret_val) 1313 goto out; 1314 1315 /* Reset the phy to commit changes. */ 1316 ret_val = hw->phy.ops.commit(hw); 1317 if (ret_val) 1318 goto out; 1319 1320 if (phy->autoneg_wait_to_complete) { 1321 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1322 1323 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1324 100000, &link); 1325 if (ret_val) 1326 goto out; 1327 1328 if (!link) { 1329 /* 1330 * We didn't get link. 1331 * Reset the DSP and cross our fingers. 1332 */ 1333 ret_val = phy->ops.write_reg(hw, 1334 M88E1000_PHY_PAGE_SELECT, 1335 0x001d); 1336 if (ret_val) 1337 goto out; 1338 ret_val = e1000_phy_reset_dsp_generic(hw); 1339 if (ret_val) 1340 goto out; 1341 } 1342 1343 /* Try once more */ 1344 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1345 100000, &link); 1346 if (ret_val) 1347 goto out; 1348 } 1349 1350 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1351 if (ret_val) 1352 goto out; 1353 1354 /* 1355 * Resetting the phy means we need to re-force TX_CLK in the 1356 * Extended PHY Specific Control Register to 25MHz clock from 1357 * the reset value of 2.5MHz. 1358 */ 1359 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1360 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1361 if (ret_val) 1362 goto out; 1363 1364 /* 1365 * In addition, we must re-enable CRS on Tx for both half and full 1366 * duplex. 1367 */ 1368 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1369 if (ret_val) 1370 goto out; 1371 1372 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1373 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1374 1375 out: 1376 return ret_val; 1377 } 1378 1379 /** 1380 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1381 * @hw: pointer to the HW structure 1382 * 1383 * Forces the speed and duplex settings of the PHY. 1384 * This is a function pointer entry point only called by 1385 * PHY setup routines. 1386 **/ 1387 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1388 { 1389 struct e1000_phy_info *phy = &hw->phy; 1390 s32 ret_val; 1391 u16 data; 1392 bool link; 1393 1394 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1395 1396 if (phy->type != e1000_phy_ife) { 1397 ret_val = e1000_phy_force_speed_duplex_igp(hw); 1398 goto out; 1399 } 1400 1401 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1402 if (ret_val) 1403 goto out; 1404 1405 e1000_phy_force_speed_duplex_setup(hw, &data); 1406 1407 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1408 if (ret_val) 1409 goto out; 1410 1411 /* Disable MDI-X support for 10/100 */ 1412 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1413 if (ret_val) 1414 goto out; 1415 1416 data &= ~IFE_PMC_AUTO_MDIX; 1417 data &= ~IFE_PMC_FORCE_MDIX; 1418 1419 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1420 if (ret_val) 1421 goto out; 1422 1423 DEBUGOUT1("IFE PMC: %X\n", data); 1424 1425 usec_delay(1); 1426 1427 if (phy->autoneg_wait_to_complete) { 1428 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1429 1430 ret_val = e1000_phy_has_link_generic(hw, 1431 PHY_FORCE_LIMIT, 1432 100000, 1433 &link); 1434 if (ret_val) 1435 goto out; 1436 1437 if (!link) 1438 DEBUGOUT("Link taking longer than expected.\n"); 1439 1440 /* Try once more */ 1441 ret_val = e1000_phy_has_link_generic(hw, 1442 PHY_FORCE_LIMIT, 1443 100000, 1444 &link); 1445 if (ret_val) 1446 goto out; 1447 } 1448 1449 out: 1450 return ret_val; 1451 } 1452 1453 /** 1454 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1455 * @hw: pointer to the HW structure 1456 * @phy_ctrl: pointer to current value of PHY_CONTROL 1457 * 1458 * Forces speed and duplex on the PHY by doing the following: disable flow 1459 * control, force speed/duplex on the MAC, disable auto speed detection, 1460 * disable auto-negotiation, configure duplex, configure speed, configure 1461 * the collision distance, write configuration to CTRL register. The 1462 * caller must write to the PHY_CONTROL register for these settings to 1463 * take affect. 1464 **/ 1465 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1466 { 1467 struct e1000_mac_info *mac = &hw->mac; 1468 u32 ctrl; 1469 1470 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1471 1472 /* Turn off flow control when forcing speed/duplex */ 1473 hw->fc.current_mode = e1000_fc_none; 1474 1475 /* Force speed/duplex on the mac */ 1476 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1477 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1478 ctrl &= ~E1000_CTRL_SPD_SEL; 1479 1480 /* Disable Auto Speed Detection */ 1481 ctrl &= ~E1000_CTRL_ASDE; 1482 1483 /* Disable autoneg on the phy */ 1484 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1485 1486 /* Forcing Full or Half Duplex? */ 1487 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1488 ctrl &= ~E1000_CTRL_FD; 1489 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1490 DEBUGOUT("Half Duplex\n"); 1491 } else { 1492 ctrl |= E1000_CTRL_FD; 1493 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1494 DEBUGOUT("Full Duplex\n"); 1495 } 1496 1497 /* Forcing 10mb or 100mb? */ 1498 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1499 ctrl |= E1000_CTRL_SPD_100; 1500 *phy_ctrl |= MII_CR_SPEED_100; 1501 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1502 DEBUGOUT("Forcing 100mb\n"); 1503 } else { 1504 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1505 *phy_ctrl |= MII_CR_SPEED_10; 1506 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1507 DEBUGOUT("Forcing 10mb\n"); 1508 } 1509 1510 e1000_config_collision_dist_generic(hw); 1511 1512 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1513 } 1514 1515 /** 1516 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1517 * @hw: pointer to the HW structure 1518 * @active: boolean used to enable/disable lplu 1519 * 1520 * Success returns 0, Failure returns 1 1521 * 1522 * The low power link up (lplu) state is set to the power management level D3 1523 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1524 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1525 * is used during Dx states where the power conservation is most important. 1526 * During driver activity, SmartSpeed should be enabled so performance is 1527 * maintained. 1528 **/ 1529 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1530 { 1531 struct e1000_phy_info *phy = &hw->phy; 1532 s32 ret_val = E1000_SUCCESS; 1533 u16 data; 1534 1535 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1536 1537 if (!(hw->phy.ops.read_reg)) 1538 goto out; 1539 1540 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1541 if (ret_val) 1542 goto out; 1543 1544 if (!active) { 1545 data &= ~IGP02E1000_PM_D3_LPLU; 1546 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1547 data); 1548 if (ret_val) 1549 goto out; 1550 /* 1551 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1552 * during Dx states where the power conservation is most 1553 * important. During driver activity we should enable 1554 * SmartSpeed, so performance is maintained. 1555 */ 1556 if (phy->smart_speed == e1000_smart_speed_on) { 1557 ret_val = phy->ops.read_reg(hw, 1558 IGP01E1000_PHY_PORT_CONFIG, 1559 &data); 1560 if (ret_val) 1561 goto out; 1562 1563 data |= IGP01E1000_PSCFR_SMART_SPEED; 1564 ret_val = phy->ops.write_reg(hw, 1565 IGP01E1000_PHY_PORT_CONFIG, 1566 data); 1567 if (ret_val) 1568 goto out; 1569 } else if (phy->smart_speed == e1000_smart_speed_off) { 1570 ret_val = phy->ops.read_reg(hw, 1571 IGP01E1000_PHY_PORT_CONFIG, 1572 &data); 1573 if (ret_val) 1574 goto out; 1575 1576 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1577 ret_val = phy->ops.write_reg(hw, 1578 IGP01E1000_PHY_PORT_CONFIG, 1579 data); 1580 if (ret_val) 1581 goto out; 1582 } 1583 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1584 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1585 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1586 data |= IGP02E1000_PM_D3_LPLU; 1587 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1588 data); 1589 if (ret_val) 1590 goto out; 1591 1592 /* When LPLU is enabled, we should disable SmartSpeed */ 1593 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1594 &data); 1595 if (ret_val) 1596 goto out; 1597 1598 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1599 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1600 data); 1601 } 1602 1603 out: 1604 return ret_val; 1605 } 1606 1607 /** 1608 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1609 * @hw: pointer to the HW structure 1610 * 1611 * Success returns 0, Failure returns 1 1612 * 1613 * A downshift is detected by querying the PHY link health. 1614 **/ 1615 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1616 { 1617 struct e1000_phy_info *phy = &hw->phy; 1618 s32 ret_val; 1619 u16 phy_data, offset, mask; 1620 1621 DEBUGFUNC("e1000_check_downshift_generic"); 1622 1623 switch (phy->type) { 1624 case e1000_phy_m88: 1625 case e1000_phy_gg82563: 1626 case e1000_phy_bm: 1627 case e1000_phy_82578: 1628 case e1000_phy_82577: 1629 offset = M88E1000_PHY_SPEC_STATUS; 1630 mask = M88E1000_PSSR_DOWNSHIFT; 1631 break; 1632 case e1000_phy_igp_2: 1633 case e1000_phy_igp: 1634 case e1000_phy_igp_3: 1635 offset = IGP01E1000_PHY_LINK_HEALTH; 1636 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1637 break; 1638 default: 1639 /* speed downshift not supported */ 1640 phy->speed_downgraded = FALSE; 1641 ret_val = E1000_SUCCESS; 1642 goto out; 1643 } 1644 1645 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1646 1647 if (!ret_val) 1648 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1649 1650 out: 1651 return ret_val; 1652 } 1653 1654 /** 1655 * e1000_check_polarity_m88 - Checks the polarity. 1656 * @hw: pointer to the HW structure 1657 * 1658 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1659 * 1660 * Polarity is determined based on the PHY specific status register. 1661 **/ 1662 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1663 { 1664 struct e1000_phy_info *phy = &hw->phy; 1665 s32 ret_val; 1666 u16 data; 1667 1668 DEBUGFUNC("e1000_check_polarity_m88"); 1669 1670 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1671 1672 if (!ret_val) 1673 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1674 ? e1000_rev_polarity_reversed 1675 : e1000_rev_polarity_normal; 1676 1677 return ret_val; 1678 } 1679 1680 /** 1681 * e1000_check_polarity_igp - Checks the polarity. 1682 * @hw: pointer to the HW structure 1683 * 1684 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1685 * 1686 * Polarity is determined based on the PHY port status register, and the 1687 * current speed (since there is no polarity at 100Mbps). 1688 **/ 1689 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1690 { 1691 struct e1000_phy_info *phy = &hw->phy; 1692 s32 ret_val; 1693 u16 data, offset, mask; 1694 1695 DEBUGFUNC("e1000_check_polarity_igp"); 1696 1697 /* 1698 * Polarity is determined based on the speed of 1699 * our connection. 1700 */ 1701 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1702 if (ret_val) 1703 goto out; 1704 1705 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1706 IGP01E1000_PSSR_SPEED_1000MBPS) { 1707 offset = IGP01E1000_PHY_PCS_INIT_REG; 1708 mask = IGP01E1000_PHY_POLARITY_MASK; 1709 } else { 1710 /* 1711 * This really only applies to 10Mbps since 1712 * there is no polarity for 100Mbps (always 0). 1713 */ 1714 offset = IGP01E1000_PHY_PORT_STATUS; 1715 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1716 } 1717 1718 ret_val = phy->ops.read_reg(hw, offset, &data); 1719 1720 if (!ret_val) 1721 phy->cable_polarity = (data & mask) 1722 ? e1000_rev_polarity_reversed 1723 : e1000_rev_polarity_normal; 1724 1725 out: 1726 return ret_val; 1727 } 1728 1729 /** 1730 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1731 * @hw: pointer to the HW structure 1732 * 1733 * Polarity is determined on the polarity reversal feature being enabled. 1734 **/ 1735 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1736 { 1737 struct e1000_phy_info *phy = &hw->phy; 1738 s32 ret_val; 1739 u16 phy_data, offset, mask; 1740 1741 DEBUGFUNC("e1000_check_polarity_ife"); 1742 1743 /* 1744 * Polarity is determined based on the reversal feature being enabled. 1745 */ 1746 if (phy->polarity_correction) { 1747 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1748 mask = IFE_PESC_POLARITY_REVERSED; 1749 } else { 1750 offset = IFE_PHY_SPECIAL_CONTROL; 1751 mask = IFE_PSC_FORCE_POLARITY; 1752 } 1753 1754 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1755 1756 if (!ret_val) 1757 phy->cable_polarity = (phy_data & mask) 1758 ? e1000_rev_polarity_reversed 1759 : e1000_rev_polarity_normal; 1760 1761 return ret_val; 1762 } 1763 1764 /** 1765 * e1000_wait_autoneg_generic - Wait for auto-neg completion 1766 * @hw: pointer to the HW structure 1767 * 1768 * Waits for auto-negotiation to complete or for the auto-negotiation time 1769 * limit to expire, which ever happens first. 1770 **/ 1771 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1772 { 1773 s32 ret_val = E1000_SUCCESS; 1774 u16 i, phy_status; 1775 1776 DEBUGFUNC("e1000_wait_autoneg_generic"); 1777 1778 if (!(hw->phy.ops.read_reg)) 1779 return E1000_SUCCESS; 1780 1781 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1782 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1783 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1784 if (ret_val) 1785 break; 1786 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1787 if (ret_val) 1788 break; 1789 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1790 break; 1791 msec_delay(100); 1792 } 1793 1794 /* 1795 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1796 * has completed. 1797 */ 1798 return ret_val; 1799 } 1800 1801 /** 1802 * e1000_phy_has_link_generic - Polls PHY for link 1803 * @hw: pointer to the HW structure 1804 * @iterations: number of times to poll for link 1805 * @usec_interval: delay between polling attempts 1806 * @success: pointer to whether polling was successful or not 1807 * 1808 * Polls the PHY status register for link, 'iterations' number of times. 1809 **/ 1810 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1811 u32 usec_interval, bool *success) 1812 { 1813 s32 ret_val = E1000_SUCCESS; 1814 u16 i, phy_status; 1815 1816 DEBUGFUNC("e1000_phy_has_link_generic"); 1817 1818 if (!(hw->phy.ops.read_reg)) 1819 return E1000_SUCCESS; 1820 1821 for (i = 0; i < iterations; i++) { 1822 /* 1823 * Some PHYs require the PHY_STATUS register to be read 1824 * twice due to the link bit being sticky. No harm doing 1825 * it across the board. 1826 */ 1827 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1828 if (ret_val) { 1829 /* 1830 * If the first read fails, another entity may have 1831 * ownership of the resources, wait and try again to 1832 * see if they have relinquished the resources yet. 1833 */ 1834 usec_delay(usec_interval); 1835 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 1836 &phy_status); 1837 } 1838 if (ret_val) 1839 break; 1840 if (phy_status & MII_SR_LINK_STATUS) 1841 break; 1842 if (usec_interval >= 1000) 1843 msec_delay_irq(usec_interval/1000); 1844 else 1845 usec_delay(usec_interval); 1846 } 1847 1848 *success = (i < iterations) ? TRUE : FALSE; 1849 1850 return ret_val; 1851 } 1852 1853 /** 1854 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1855 * @hw: pointer to the HW structure 1856 * 1857 * Reads the PHY specific status register to retrieve the cable length 1858 * information. The cable length is determined by averaging the minimum and 1859 * maximum values to get the "average" cable length. The m88 PHY has four 1860 * possible cable length values, which are: 1861 * Register Value Cable Length 1862 * 0 < 50 meters 1863 * 1 50 - 80 meters 1864 * 2 80 - 110 meters 1865 * 3 110 - 140 meters 1866 * 4 > 140 meters 1867 **/ 1868 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 1869 { 1870 struct e1000_phy_info *phy = &hw->phy; 1871 s32 ret_val; 1872 u16 phy_data, index; 1873 1874 DEBUGFUNC("e1000_get_cable_length_m88"); 1875 1876 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1877 if (ret_val) 1878 goto out; 1879 1880 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1881 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1882 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) { 1883 ret_val = E1000_ERR_PHY; 1884 goto out; 1885 } 1886 1887 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1888 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1889 1890 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1891 1892 out: 1893 return ret_val; 1894 } 1895 1896 /** 1897 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1898 * @hw: pointer to the HW structure 1899 * 1900 * The automatic gain control (agc) normalizes the amplitude of the 1901 * received signal, adjusting for the attenuation produced by the 1902 * cable. By reading the AGC registers, which represent the 1903 * combination of coarse and fine gain value, the value can be put 1904 * into a lookup table to obtain the approximate cable length 1905 * for each channel. 1906 **/ 1907 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1908 { 1909 struct e1000_phy_info *phy = &hw->phy; 1910 s32 ret_val = E1000_SUCCESS; 1911 u16 phy_data, i, agc_value = 0; 1912 u16 cur_agc_index, max_agc_index = 0; 1913 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1914 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1915 {IGP02E1000_PHY_AGC_A, 1916 IGP02E1000_PHY_AGC_B, 1917 IGP02E1000_PHY_AGC_C, 1918 IGP02E1000_PHY_AGC_D}; 1919 1920 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1921 1922 /* Read the AGC registers for all channels */ 1923 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1924 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1925 if (ret_val) 1926 goto out; 1927 1928 /* 1929 * Getting bits 15:9, which represent the combination of 1930 * coarse and fine gain values. The result is a number 1931 * that can be put into the lookup table to obtain the 1932 * approximate cable length. 1933 */ 1934 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1935 IGP02E1000_AGC_LENGTH_MASK; 1936 1937 /* Array index bound check. */ 1938 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1939 (cur_agc_index == 0)) { 1940 ret_val = -E1000_ERR_PHY; 1941 goto out; 1942 } 1943 1944 /* Remove min & max AGC values from calculation. */ 1945 if (e1000_igp_2_cable_length_table[min_agc_index] > 1946 e1000_igp_2_cable_length_table[cur_agc_index]) 1947 min_agc_index = cur_agc_index; 1948 if (e1000_igp_2_cable_length_table[max_agc_index] < 1949 e1000_igp_2_cable_length_table[cur_agc_index]) 1950 max_agc_index = cur_agc_index; 1951 1952 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1953 } 1954 1955 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1956 e1000_igp_2_cable_length_table[max_agc_index]); 1957 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1958 1959 /* Calculate cable length with the error range of +/- 10 meters. */ 1960 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1961 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1962 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1963 1964 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1965 1966 out: 1967 return ret_val; 1968 } 1969 1970 /** 1971 * e1000_get_phy_info_m88 - Retrieve PHY information 1972 * @hw: pointer to the HW structure 1973 * 1974 * Valid for only copper links. Read the PHY status register (sticky read) 1975 * to verify that link is up. Read the PHY special control register to 1976 * determine the polarity and 10base-T extended distance. Read the PHY 1977 * special status register to determine MDI/MDIx and current speed. If 1978 * speed is 1000, then determine cable length, local and remote receiver. 1979 **/ 1980 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 1981 { 1982 struct e1000_phy_info *phy = &hw->phy; 1983 s32 ret_val; 1984 u16 phy_data; 1985 bool link; 1986 1987 DEBUGFUNC("e1000_get_phy_info_m88"); 1988 1989 if (hw->phy.media_type != e1000_media_type_copper) { 1990 DEBUGOUT("Phy info is only valid for copper media\n"); 1991 ret_val = -E1000_ERR_CONFIG; 1992 goto out; 1993 } 1994 1995 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1996 if (ret_val) 1997 goto out; 1998 1999 if (!link) { 2000 DEBUGOUT("Phy info is only valid if link is up\n"); 2001 ret_val = -E1000_ERR_CONFIG; 2002 goto out; 2003 } 2004 2005 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2006 if (ret_val) 2007 goto out; 2008 2009 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2010 ? TRUE : FALSE; 2011 2012 ret_val = e1000_check_polarity_m88(hw); 2013 if (ret_val) 2014 goto out; 2015 2016 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2017 if (ret_val) 2018 goto out; 2019 2020 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 2021 2022 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2023 ret_val = hw->phy.ops.get_cable_length(hw); 2024 if (ret_val) 2025 goto out; 2026 2027 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2028 if (ret_val) 2029 goto out; 2030 2031 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2032 ? e1000_1000t_rx_status_ok 2033 : e1000_1000t_rx_status_not_ok; 2034 2035 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2036 ? e1000_1000t_rx_status_ok 2037 : e1000_1000t_rx_status_not_ok; 2038 } else { 2039 /* Set values to "undefined" */ 2040 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2041 phy->local_rx = e1000_1000t_rx_status_undefined; 2042 phy->remote_rx = e1000_1000t_rx_status_undefined; 2043 } 2044 2045 out: 2046 return ret_val; 2047 } 2048 2049 /** 2050 * e1000_get_phy_info_igp - Retrieve igp PHY information 2051 * @hw: pointer to the HW structure 2052 * 2053 * Read PHY status to determine if link is up. If link is up, then 2054 * set/determine 10base-T extended distance and polarity correction. Read 2055 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2056 * determine on the cable length, local and remote receiver. 2057 **/ 2058 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2059 { 2060 struct e1000_phy_info *phy = &hw->phy; 2061 s32 ret_val; 2062 u16 data; 2063 bool link; 2064 2065 DEBUGFUNC("e1000_get_phy_info_igp"); 2066 2067 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2068 if (ret_val) 2069 goto out; 2070 2071 if (!link) { 2072 DEBUGOUT("Phy info is only valid if link is up\n"); 2073 ret_val = -E1000_ERR_CONFIG; 2074 goto out; 2075 } 2076 2077 phy->polarity_correction = TRUE; 2078 2079 ret_val = e1000_check_polarity_igp(hw); 2080 if (ret_val) 2081 goto out; 2082 2083 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2084 if (ret_val) 2085 goto out; 2086 2087 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 2088 2089 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2090 IGP01E1000_PSSR_SPEED_1000MBPS) { 2091 ret_val = hw->phy.ops.get_cable_length(hw); 2092 if (ret_val) 2093 goto out; 2094 2095 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2096 if (ret_val) 2097 goto out; 2098 2099 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2100 ? e1000_1000t_rx_status_ok 2101 : e1000_1000t_rx_status_not_ok; 2102 2103 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2104 ? e1000_1000t_rx_status_ok 2105 : e1000_1000t_rx_status_not_ok; 2106 } else { 2107 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2108 phy->local_rx = e1000_1000t_rx_status_undefined; 2109 phy->remote_rx = e1000_1000t_rx_status_undefined; 2110 } 2111 2112 out: 2113 return ret_val; 2114 } 2115 2116 /** 2117 * e1000_phy_sw_reset_generic - PHY software reset 2118 * @hw: pointer to the HW structure 2119 * 2120 * Does a software reset of the PHY by reading the PHY control register and 2121 * setting/write the control register reset bit to the PHY. 2122 **/ 2123 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2124 { 2125 s32 ret_val = E1000_SUCCESS; 2126 u16 phy_ctrl; 2127 2128 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2129 2130 if (!(hw->phy.ops.read_reg)) 2131 goto out; 2132 2133 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2134 if (ret_val) 2135 goto out; 2136 2137 phy_ctrl |= MII_CR_RESET; 2138 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2139 if (ret_val) 2140 goto out; 2141 2142 usec_delay(1); 2143 2144 out: 2145 return ret_val; 2146 } 2147 2148 /** 2149 * e1000_phy_hw_reset_generic - PHY hardware reset 2150 * @hw: pointer to the HW structure 2151 * 2152 * Verify the reset block is not blocking us from resetting. Acquire 2153 * semaphore (if necessary) and read/set/write the device control reset 2154 * bit in the PHY. Wait the appropriate delay time for the device to 2155 * reset and release the semaphore (if necessary). 2156 **/ 2157 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2158 { 2159 struct e1000_phy_info *phy = &hw->phy; 2160 s32 ret_val = E1000_SUCCESS; 2161 u32 ctrl; 2162 2163 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2164 2165 ret_val = phy->ops.check_reset_block(hw); 2166 if (ret_val) { 2167 ret_val = E1000_SUCCESS; 2168 goto out; 2169 } 2170 2171 ret_val = phy->ops.acquire(hw); 2172 if (ret_val) 2173 goto out; 2174 2175 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2176 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2177 E1000_WRITE_FLUSH(hw); 2178 2179 usec_delay(phy->reset_delay_us); 2180 2181 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2182 E1000_WRITE_FLUSH(hw); 2183 2184 usec_delay(150); 2185 2186 phy->ops.release(hw); 2187 2188 ret_val = phy->ops.get_cfg_done(hw); 2189 2190 out: 2191 return ret_val; 2192 } 2193 2194 /** 2195 * e1000_get_cfg_done_generic - Generic configuration done 2196 * @hw: pointer to the HW structure 2197 * 2198 * Generic function to wait 10 milli-seconds for configuration to complete 2199 * and return success. 2200 **/ 2201 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2202 { 2203 DEBUGFUNC("e1000_get_cfg_done_generic"); 2204 2205 msec_delay_irq(10); 2206 2207 return E1000_SUCCESS; 2208 } 2209 2210 /** 2211 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2212 * @hw: pointer to the HW structure 2213 * 2214 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2215 **/ 2216 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2217 { 2218 DEBUGOUT("Running IGP 3 PHY init script\n"); 2219 2220 /* PHY init IGP 3 */ 2221 /* Enable rise/fall, 10-mode work in class-A */ 2222 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2223 /* Remove all caps from Replica path filter */ 2224 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2225 /* Bias trimming for ADC, AFE and Driver (Default) */ 2226 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2227 /* Increase Hybrid poly bias */ 2228 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2229 /* Add 4% to Tx amplitude in Gig mode */ 2230 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2231 /* Disable trimming (TTT) */ 2232 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2233 /* Poly DC correction to 94.6% + 2% for all channels */ 2234 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2235 /* ABS DC correction to 95.9% */ 2236 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2237 /* BG temp curve trim */ 2238 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2239 /* Increasing ADC OPAMP stage 1 currents to max */ 2240 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2241 /* Force 1000 ( required for enabling PHY regs configuration) */ 2242 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2243 /* Set upd_freq to 6 */ 2244 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2245 /* Disable NPDFE */ 2246 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2247 /* Disable adaptive fixed FFE (Default) */ 2248 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2249 /* Enable FFE hysteresis */ 2250 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2251 /* Fixed FFE for short cable lengths */ 2252 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2253 /* Fixed FFE for medium cable lengths */ 2254 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2255 /* Fixed FFE for long cable lengths */ 2256 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2257 /* Enable Adaptive Clip Threshold */ 2258 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2259 /* AHT reset limit to 1 */ 2260 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2261 /* Set AHT master delay to 127 msec */ 2262 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2263 /* Set scan bits for AHT */ 2264 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2265 /* Set AHT Preset bits */ 2266 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2267 /* Change integ_factor of channel A to 3 */ 2268 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2269 /* Change prop_factor of channels BCD to 8 */ 2270 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2271 /* Change cg_icount + enable integbp for channels BCD */ 2272 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2273 /* 2274 * Change cg_icount + enable integbp + change prop_factor_master 2275 * to 8 for channel A 2276 */ 2277 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2278 /* Disable AHT in Slave mode on channel A */ 2279 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2280 /* 2281 * Enable LPLU and disable AN to 1000 in non-D0a states, 2282 * Enable SPD+B2B 2283 */ 2284 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2285 /* Enable restart AN on an1000_dis change */ 2286 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2287 /* Enable wh_fifo read clock in 10/100 modes */ 2288 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2289 /* Restart AN, Speed selection is 1000 */ 2290 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2291 2292 return E1000_SUCCESS; 2293 } 2294 2295 /** 2296 * e1000_get_phy_type_from_id - Get PHY type from id 2297 * @phy_id: phy_id read from the phy 2298 * 2299 * Returns the phy type from the id. 2300 **/ 2301 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2302 { 2303 enum e1000_phy_type phy_type = e1000_phy_unknown; 2304 2305 switch (phy_id) { 2306 case M88E1000_I_PHY_ID: 2307 case M88E1000_E_PHY_ID: 2308 case M88E1111_I_PHY_ID: 2309 case M88E1011_I_PHY_ID: 2310 phy_type = e1000_phy_m88; 2311 break; 2312 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2313 phy_type = e1000_phy_igp_2; 2314 break; 2315 case GG82563_E_PHY_ID: 2316 phy_type = e1000_phy_gg82563; 2317 break; 2318 case IGP03E1000_E_PHY_ID: 2319 phy_type = e1000_phy_igp_3; 2320 break; 2321 case IFE_E_PHY_ID: 2322 case IFE_PLUS_E_PHY_ID: 2323 case IFE_C_E_PHY_ID: 2324 phy_type = e1000_phy_ife; 2325 break; 2326 case BME1000_E_PHY_ID: 2327 case BME1000_E_PHY_ID_R2: 2328 phy_type = e1000_phy_bm; 2329 break; 2330 case I82578_E_PHY_ID: 2331 phy_type = e1000_phy_82578; 2332 break; 2333 case I82577_E_PHY_ID: 2334 phy_type = e1000_phy_82577; 2335 break; 2336 default: 2337 phy_type = e1000_phy_unknown; 2338 break; 2339 } 2340 return phy_type; 2341 } 2342 2343 /** 2344 * e1000_determine_phy_address - Determines PHY address. 2345 * @hw: pointer to the HW structure 2346 * 2347 * This uses a trial and error method to loop through possible PHY 2348 * addresses. It tests each by reading the PHY ID registers and 2349 * checking for a match. 2350 **/ 2351 s32 e1000_determine_phy_address(struct e1000_hw *hw) 2352 { 2353 s32 ret_val = -E1000_ERR_PHY_TYPE; 2354 u32 phy_addr = 0; 2355 u32 i; 2356 enum e1000_phy_type phy_type = e1000_phy_unknown; 2357 2358 hw->phy.id = phy_type; 2359 2360 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2361 hw->phy.addr = phy_addr; 2362 i = 0; 2363 2364 do { 2365 e1000_get_phy_id(hw); 2366 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2367 2368 /* 2369 * If phy_type is valid, break - we found our 2370 * PHY address 2371 */ 2372 if (phy_type != e1000_phy_unknown) { 2373 ret_val = E1000_SUCCESS; 2374 goto out; 2375 } 2376 msec_delay(1); 2377 i++; 2378 } while (i < 10); 2379 } 2380 2381 out: 2382 return ret_val; 2383 } 2384 2385 /** 2386 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2387 * @page: page to access 2388 * 2389 * Returns the phy address for the page requested. 2390 **/ 2391 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2392 { 2393 u32 phy_addr = 2; 2394 2395 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2396 phy_addr = 1; 2397 2398 return phy_addr; 2399 } 2400 2401 /** 2402 * e1000_write_phy_reg_bm - Write BM PHY register 2403 * @hw: pointer to the HW structure 2404 * @offset: register offset to write to 2405 * @data: data to write at register offset 2406 * 2407 * Acquires semaphore, if necessary, then writes the data to PHY register 2408 * at the offset. Release any acquired semaphores before exiting. 2409 **/ 2410 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2411 { 2412 s32 ret_val; 2413 u32 page_select = 0; 2414 u32 page = offset >> IGP_PAGE_SHIFT; 2415 u32 page_shift = 0; 2416 2417 DEBUGFUNC("e1000_write_phy_reg_bm"); 2418 2419 /* Page 800 works differently than the rest so it has its own func */ 2420 if (page == BM_WUC_PAGE) { 2421 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2422 FALSE); 2423 goto out; 2424 } 2425 2426 ret_val = hw->phy.ops.acquire(hw); 2427 if (ret_val) 2428 goto out; 2429 2430 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2431 2432 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2433 /* 2434 * Page select is register 31 for phy address 1 and 22 for 2435 * phy address 2 and 3. Page select is shifted only for 2436 * phy address 1. 2437 */ 2438 if (hw->phy.addr == 1) { 2439 page_shift = IGP_PAGE_SHIFT; 2440 page_select = IGP01E1000_PHY_PAGE_SELECT; 2441 } else { 2442 page_shift = 0; 2443 page_select = BM_PHY_PAGE_SELECT; 2444 } 2445 2446 /* Page is shifted left, PHY expects (page x 32) */ 2447 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2448 (page << page_shift)); 2449 if (ret_val) { 2450 hw->phy.ops.release(hw); 2451 goto out; 2452 } 2453 } 2454 2455 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2456 data); 2457 2458 hw->phy.ops.release(hw); 2459 2460 out: 2461 return ret_val; 2462 } 2463 2464 /** 2465 * e1000_read_phy_reg_bm - Read BM PHY register 2466 * @hw: pointer to the HW structure 2467 * @offset: register offset to be read 2468 * @data: pointer to the read data 2469 * 2470 * Acquires semaphore, if necessary, then reads the PHY register at offset 2471 * and storing the retrieved information in data. Release any acquired 2472 * semaphores before exiting. 2473 **/ 2474 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2475 { 2476 s32 ret_val; 2477 u32 page_select = 0; 2478 u32 page = offset >> IGP_PAGE_SHIFT; 2479 u32 page_shift = 0; 2480 2481 DEBUGFUNC("e1000_read_phy_reg_bm"); 2482 2483 /* Page 800 works differently than the rest so it has its own func */ 2484 if (page == BM_WUC_PAGE) { 2485 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2486 TRUE); 2487 goto out; 2488 } 2489 2490 ret_val = hw->phy.ops.acquire(hw); 2491 if (ret_val) 2492 goto out; 2493 2494 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2495 2496 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2497 /* 2498 * Page select is register 31 for phy address 1 and 22 for 2499 * phy address 2 and 3. Page select is shifted only for 2500 * phy address 1. 2501 */ 2502 if (hw->phy.addr == 1) { 2503 page_shift = IGP_PAGE_SHIFT; 2504 page_select = IGP01E1000_PHY_PAGE_SELECT; 2505 } else { 2506 page_shift = 0; 2507 page_select = BM_PHY_PAGE_SELECT; 2508 } 2509 2510 /* Page is shifted left, PHY expects (page x 32) */ 2511 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2512 (page << page_shift)); 2513 if (ret_val) { 2514 hw->phy.ops.release(hw); 2515 goto out; 2516 } 2517 } 2518 2519 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2520 data); 2521 hw->phy.ops.release(hw); 2522 2523 out: 2524 return ret_val; 2525 } 2526 2527 /** 2528 * e1000_read_phy_reg_bm2 - Read BM PHY register 2529 * @hw: pointer to the HW structure 2530 * @offset: register offset to be read 2531 * @data: pointer to the read data 2532 * 2533 * Acquires semaphore, if necessary, then reads the PHY register at offset 2534 * and storing the retrieved information in data. Release any acquired 2535 * semaphores before exiting. 2536 **/ 2537 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2538 { 2539 s32 ret_val; 2540 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2541 2542 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2543 2544 /* Page 800 works differently than the rest so it has its own func */ 2545 if (page == BM_WUC_PAGE) { 2546 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2547 TRUE); 2548 goto out; 2549 } 2550 2551 ret_val = hw->phy.ops.acquire(hw); 2552 if (ret_val) 2553 goto out; 2554 2555 hw->phy.addr = 1; 2556 2557 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2558 2559 /* Page is shifted left, PHY expects (page x 32) */ 2560 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2561 page); 2562 2563 if (ret_val) { 2564 hw->phy.ops.release(hw); 2565 goto out; 2566 } 2567 } 2568 2569 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2570 data); 2571 hw->phy.ops.release(hw); 2572 2573 out: 2574 return ret_val; 2575 } 2576 2577 /** 2578 * e1000_write_phy_reg_bm2 - Write BM PHY register 2579 * @hw: pointer to the HW structure 2580 * @offset: register offset to write to 2581 * @data: data to write at register offset 2582 * 2583 * Acquires semaphore, if necessary, then writes the data to PHY register 2584 * at the offset. Release any acquired semaphores before exiting. 2585 **/ 2586 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2587 { 2588 s32 ret_val; 2589 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2590 2591 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2592 2593 /* Page 800 works differently than the rest so it has its own func */ 2594 if (page == BM_WUC_PAGE) { 2595 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2596 FALSE); 2597 goto out; 2598 } 2599 2600 ret_val = hw->phy.ops.acquire(hw); 2601 if (ret_val) 2602 goto out; 2603 2604 hw->phy.addr = 1; 2605 2606 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2607 /* Page is shifted left, PHY expects (page x 32) */ 2608 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2609 page); 2610 2611 if (ret_val) { 2612 hw->phy.ops.release(hw); 2613 goto out; 2614 } 2615 } 2616 2617 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2618 data); 2619 2620 hw->phy.ops.release(hw); 2621 2622 out: 2623 return ret_val; 2624 } 2625 2626 /** 2627 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2628 * @hw: pointer to the HW structure 2629 * @offset: register offset to be read or written 2630 * @data: pointer to the data to read or write 2631 * @read: determines if operation is read or write 2632 * 2633 * Acquires semaphore, if necessary, then reads the PHY register at offset 2634 * and storing the retrieved information in data. Release any acquired 2635 * semaphores before exiting. Note that procedure to read the wakeup 2636 * registers are different. It works as such: 2637 * 1) Set page 769, register 17, bit 2 = 1 2638 * 2) Set page to 800 for host (801 if we were manageability) 2639 * 3) Write the address using the address opcode (0x11) 2640 * 4) Read or write the data using the data opcode (0x12) 2641 * 5) Restore 769_17.2 to its original value 2642 **/ 2643 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2644 u16 *data, bool read) 2645 { 2646 s32 ret_val; 2647 u16 reg = BM_PHY_REG_NUM(offset); 2648 u16 phy_reg = 0; 2649 u8 phy_acquired = 1; 2650 2651 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 2652 2653 /* Gig must be disabled for MDIO accesses to page 800 */ 2654 if ((hw->mac.type == e1000_pchlan) && 2655 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2656 DEBUGOUT("Attempting to access page 800 while gig enabled.\n"); 2657 2658 ret_val = hw->phy.ops.acquire(hw); 2659 if (ret_val) { 2660 DEBUGOUT("Could not acquire PHY\n"); 2661 phy_acquired = 0; 2662 goto out; 2663 } 2664 2665 /* All operations in this function are phy address 1 */ 2666 hw->phy.addr = 1; 2667 2668 /* Set page 769 */ 2669 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2670 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2671 2672 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2673 if (ret_val) { 2674 DEBUGOUT("Could not read PHY page 769\n"); 2675 goto out; 2676 } 2677 2678 /* First clear bit 4 to avoid a power state change */ 2679 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2680 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2681 if (ret_val) { 2682 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 2683 goto out; 2684 } 2685 2686 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2687 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2688 phy_reg | BM_WUC_ENABLE_BIT); 2689 if (ret_val) { 2690 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 2691 goto out; 2692 } 2693 2694 /* Select page 800 */ 2695 ret_val = e1000_write_phy_reg_mdic(hw, 2696 IGP01E1000_PHY_PAGE_SELECT, 2697 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2698 2699 /* Write the page 800 offset value using opcode 0x11 */ 2700 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2701 if (ret_val) { 2702 DEBUGOUT("Could not write address opcode to page 800\n"); 2703 goto out; 2704 } 2705 2706 if (read) { 2707 /* Read the page 800 value using opcode 0x12 */ 2708 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2709 data); 2710 } else { 2711 /* Write the page 800 value using opcode 0x12 */ 2712 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2713 *data); 2714 } 2715 2716 if (ret_val) { 2717 DEBUGOUT("Could not access data value from page 800\n"); 2718 goto out; 2719 } 2720 2721 /* 2722 * Restore 769_17.2 to its original value 2723 * Set page 769 2724 */ 2725 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2726 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2727 2728 /* Clear 769_17.2 */ 2729 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2730 if (ret_val) { 2731 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 2732 goto out; 2733 } 2734 2735 out: 2736 if (phy_acquired == 1) 2737 hw->phy.ops.release(hw); 2738 return ret_val; 2739 } 2740 2741 /** 2742 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2743 * @hw: pointer to the HW structure 2744 * 2745 * In the case of a PHY power down to save power, or to turn off link during a 2746 * driver unload, or wake on lan is not enabled, restore the link to previous 2747 * settings. 2748 **/ 2749 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2750 { 2751 u16 mii_reg = 0; 2752 2753 /* The PHY will retain its settings across a power down/up cycle */ 2754 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2755 mii_reg &= ~MII_CR_POWER_DOWN; 2756 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2757 } 2758 2759 /** 2760 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2761 * @hw: pointer to the HW structure 2762 * 2763 * In the case of a PHY power down to save power, or to turn off link during a 2764 * driver unload, or wake on lan is not enabled, restore the link to previous 2765 * settings. 2766 **/ 2767 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2768 { 2769 u16 mii_reg = 0; 2770 2771 /* The PHY will retain its settings across a power down/up cycle */ 2772 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2773 mii_reg |= MII_CR_POWER_DOWN; 2774 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2775 msec_delay(1); 2776 } 2777 2778 s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) 2779 { 2780 s32 ret_val = E1000_SUCCESS; 2781 u16 data = 0; 2782 2783 ret_val = hw->phy.ops.acquire(hw); 2784 if (ret_val) 2785 return ret_val; 2786 2787 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ 2788 hw->phy.addr = 1; 2789 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2790 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2791 if (ret_val) { 2792 hw->phy.ops.release(hw); 2793 return ret_val; 2794 } 2795 ret_val = e1000_write_phy_reg_mdic(hw, BM_CS_CTRL1, 2796 (0x2180 | (slow << 10))); 2797 2798 /* dummy read when reverting to fast mode - throw away result */ 2799 if (!slow) 2800 e1000_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); 2801 2802 hw->phy.ops.release(hw); 2803 2804 return ret_val; 2805 } 2806 2807 /** 2808 * e1000_read_phy_reg_hv - Read HV PHY register 2809 * @hw: pointer to the HW structure 2810 * @offset: register offset to be read 2811 * @data: pointer to the read data 2812 * 2813 * Acquires semaphore, if necessary, then reads the PHY register at offset 2814 * and storing the retrieved information in data. Release any acquired 2815 * semaphore before exiting. 2816 **/ 2817 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2818 { 2819 s32 ret_val; 2820 u16 page = BM_PHY_REG_PAGE(offset); 2821 u16 reg = BM_PHY_REG_NUM(offset); 2822 bool in_slow_mode = FALSE; 2823 2824 DEBUGFUNC("e1000_read_phy_reg_hv"); 2825 2826 /* Workaround failure in MDIO access while cable is disconnected */ 2827 if ((hw->phy.type == e1000_phy_82577) && 2828 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 2829 ret_val = e1000_set_mdio_slow_mode_hv(hw, TRUE); 2830 if (ret_val) 2831 goto out; 2832 2833 in_slow_mode = TRUE; 2834 } 2835 2836 /* Page 800 works differently than the rest so it has its own func */ 2837 if (page == BM_WUC_PAGE) { 2838 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 2839 data, TRUE); 2840 goto out; 2841 } 2842 2843 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2844 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2845 data, TRUE); 2846 goto out; 2847 } 2848 2849 ret_val = hw->phy.ops.acquire(hw); 2850 if (ret_val) 2851 goto out; 2852 2853 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2854 2855 if (page == HV_INTC_FC_PAGE_START) 2856 page = 0; 2857 2858 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2859 if ((hw->phy.type != e1000_phy_82578) || 2860 ((reg != I82578_ADDR_REG) && 2861 (reg != I82578_ADDR_REG + 1))) { 2862 u32 phy_addr = hw->phy.addr; 2863 2864 hw->phy.addr = 1; 2865 2866 /* Page is shifted left, PHY expects (page x 32) */ 2867 ret_val = e1000_write_phy_reg_mdic(hw, 2868 IGP01E1000_PHY_PAGE_SELECT, 2869 (page << IGP_PAGE_SHIFT)); 2870 if (ret_val) { 2871 hw->phy.ops.release(hw); 2872 goto out; 2873 } 2874 hw->phy.addr = phy_addr; 2875 } 2876 } 2877 2878 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2879 data); 2880 hw->phy.ops.release(hw); 2881 2882 out: 2883 /* Revert to MDIO fast mode, if applicable */ 2884 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 2885 ret_val = e1000_set_mdio_slow_mode_hv(hw, FALSE); 2886 2887 return ret_val; 2888 } 2889 2890 /** 2891 * e1000_write_phy_reg_hv - Write HV PHY register 2892 * @hw: pointer to the HW structure 2893 * @offset: register offset to write to 2894 * @data: data to write at register offset 2895 * 2896 * Acquires semaphore, if necessary, then writes the data to PHY register 2897 * at the offset. Release any acquired semaphores before exiting. 2898 **/ 2899 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 2900 { 2901 s32 ret_val; 2902 u16 page = BM_PHY_REG_PAGE(offset); 2903 u16 reg = BM_PHY_REG_NUM(offset); 2904 bool in_slow_mode = FALSE; 2905 2906 DEBUGFUNC("e1000_write_phy_reg_hv"); 2907 2908 /* Workaround failure in MDIO access while cable is disconnected */ 2909 if ((hw->phy.type == e1000_phy_82577) && 2910 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 2911 ret_val = e1000_set_mdio_slow_mode_hv(hw, TRUE); 2912 if (ret_val) 2913 goto out; 2914 2915 in_slow_mode = TRUE; 2916 } 2917 2918 /* Page 800 works differently than the rest so it has its own func */ 2919 if (page == BM_WUC_PAGE) { 2920 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 2921 &data, FALSE); 2922 goto out; 2923 } 2924 2925 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2926 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2927 &data, FALSE); 2928 goto out; 2929 } 2930 2931 ret_val = hw->phy.ops.acquire(hw); 2932 if (ret_val) 2933 goto out; 2934 2935 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2936 2937 if (page == HV_INTC_FC_PAGE_START) 2938 page = 0; 2939 2940 /* 2941 * Workaround MDIO accesses being disabled after entering IEEE Power 2942 * Down (whenever bit 11 of the PHY Control register is set) 2943 */ 2944 if ((hw->phy.type == e1000_phy_82578) && 2945 (hw->phy.revision >= 1) && 2946 (hw->phy.addr == 2) && 2947 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 2948 (data & (1 << 11))) { 2949 u16 data2 = 0x7EFF; 2950 hw->phy.ops.release(hw); 2951 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 2952 &data2, FALSE); 2953 if (ret_val) 2954 goto out; 2955 2956 ret_val = hw->phy.ops.acquire(hw); 2957 if (ret_val) 2958 goto out; 2959 } 2960 2961 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2962 if ((hw->phy.type != e1000_phy_82578) || 2963 ((reg != I82578_ADDR_REG) && 2964 (reg != I82578_ADDR_REG + 1))) { 2965 u32 phy_addr = hw->phy.addr; 2966 2967 hw->phy.addr = 1; 2968 2969 /* Page is shifted left, PHY expects (page x 32) */ 2970 ret_val = e1000_write_phy_reg_mdic(hw, 2971 IGP01E1000_PHY_PAGE_SELECT, 2972 (page << IGP_PAGE_SHIFT)); 2973 if (ret_val) { 2974 hw->phy.ops.release(hw); 2975 goto out; 2976 } 2977 hw->phy.addr = phy_addr; 2978 } 2979 } 2980 2981 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2982 data); 2983 hw->phy.ops.release(hw); 2984 2985 out: 2986 /* Revert to MDIO fast mode, if applicable */ 2987 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 2988 ret_val = e1000_set_mdio_slow_mode_hv(hw, FALSE); 2989 2990 return ret_val; 2991 } 2992 2993 /** 2994 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 2995 * @page: page to be accessed 2996 **/ 2997 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 2998 { 2999 u32 phy_addr = 2; 3000 3001 if (page >= HV_INTC_FC_PAGE_START) 3002 phy_addr = 1; 3003 3004 return phy_addr; 3005 } 3006 3007 /** 3008 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3009 * @hw: pointer to the HW structure 3010 * @offset: register offset to be read or written 3011 * @data: pointer to the data to be read or written 3012 * @read: determines if operation is read or written 3013 * 3014 * Acquires semaphore, if necessary, then reads the PHY register at offset 3015 * and storing the retreived information in data. Release any acquired 3016 * semaphores before exiting. Note that the procedure to read these regs 3017 * uses the address port and data port to read/write. 3018 **/ 3019 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3020 u16 *data, bool read) 3021 { 3022 s32 ret_val; 3023 u32 addr_reg = 0; 3024 u32 data_reg = 0; 3025 u8 phy_acquired = 1; 3026 3027 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3028 3029 /* This takes care of the difference with desktop vs mobile phy */ 3030 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3031 I82578_ADDR_REG : I82577_ADDR_REG; 3032 data_reg = addr_reg + 1; 3033 3034 ret_val = hw->phy.ops.acquire(hw); 3035 if (ret_val) { 3036 DEBUGOUT("Could not acquire PHY\n"); 3037 phy_acquired = 0; 3038 goto out; 3039 } 3040 3041 /* All operations in this function are phy address 2 */ 3042 hw->phy.addr = 2; 3043 3044 /* masking with 0x3F to remove the page from offset */ 3045 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3046 if (ret_val) { 3047 DEBUGOUT("Could not write PHY the HV address register\n"); 3048 goto out; 3049 } 3050 3051 /* Read or write the data value next */ 3052 if (read) 3053 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3054 else 3055 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3056 3057 if (ret_val) { 3058 DEBUGOUT("Could not read data value from HV data register\n"); 3059 goto out; 3060 } 3061 3062 out: 3063 if (phy_acquired == 1) 3064 hw->phy.ops.release(hw); 3065 return ret_val; 3066 } 3067 3068 /** 3069 * e1000_link_stall_workaround_hv - Si workaround 3070 * @hw: pointer to the HW structure 3071 * 3072 * This function works around a Si bug where the link partner can get 3073 * a link up indication before the PHY does. If small packets are sent 3074 * by the link partner they can be placed in the packet buffer without 3075 * being properly accounted for by the PHY and will stall preventing 3076 * further packets from being received. The workaround is to clear the 3077 * packet buffer after the PHY detects link up. 3078 **/ 3079 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3080 { 3081 s32 ret_val = E1000_SUCCESS; 3082 u16 data; 3083 3084 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3085 3086 if (hw->phy.type != e1000_phy_82578) 3087 goto out; 3088 3089 /* Do not apply workaround if in PHY loopback bit 14 set */ 3090 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3091 if (data & PHY_CONTROL_LB) 3092 goto out; 3093 3094 /* check if link is up and at 1Gbps */ 3095 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3096 if (ret_val) 3097 goto out; 3098 3099 data &= BM_CS_STATUS_LINK_UP | 3100 BM_CS_STATUS_RESOLVED | 3101 BM_CS_STATUS_SPEED_MASK; 3102 3103 if (data != (BM_CS_STATUS_LINK_UP | 3104 BM_CS_STATUS_RESOLVED | 3105 BM_CS_STATUS_SPEED_1000)) 3106 goto out; 3107 3108 msec_delay(200); 3109 3110 /* flush the packets in the fifo buffer */ 3111 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3112 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3113 HV_MUX_DATA_CTRL_FORCE_SPEED); 3114 if (ret_val) 3115 goto out; 3116 3117 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3118 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3119 3120 out: 3121 return ret_val; 3122 } 3123 3124 /** 3125 * e1000_check_polarity_82577 - Checks the polarity. 3126 * @hw: pointer to the HW structure 3127 * 3128 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3129 * 3130 * Polarity is determined based on the PHY specific status register. 3131 **/ 3132 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3133 { 3134 struct e1000_phy_info *phy = &hw->phy; 3135 s32 ret_val; 3136 u16 data; 3137 3138 DEBUGFUNC("e1000_check_polarity_82577"); 3139 3140 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3141 3142 if (!ret_val) 3143 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3144 ? e1000_rev_polarity_reversed 3145 : e1000_rev_polarity_normal; 3146 3147 return ret_val; 3148 } 3149 3150 /** 3151 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3152 * @hw: pointer to the HW structure 3153 * 3154 * Calls the PHY setup function to force speed and duplex. Clears the 3155 * auto-crossover to force MDI manually. Waits for link and returns 3156 * successful if link up is successful, else -E1000_ERR_PHY (-2). 3157 **/ 3158 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3159 { 3160 struct e1000_phy_info *phy = &hw->phy; 3161 s32 ret_val; 3162 u16 phy_data; 3163 bool link; 3164 3165 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3166 3167 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3168 if (ret_val) 3169 goto out; 3170 3171 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3172 3173 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3174 if (ret_val) 3175 goto out; 3176 3177 /* 3178 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI 3179 * forced whenever speed and duplex are forced. 3180 */ 3181 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 3182 if (ret_val) 3183 goto out; 3184 3185 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; 3186 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; 3187 3188 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 3189 if (ret_val) 3190 goto out; 3191 3192 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data); 3193 3194 usec_delay(1); 3195 3196 if (phy->autoneg_wait_to_complete) { 3197 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3198 3199 ret_val = e1000_phy_has_link_generic(hw, 3200 PHY_FORCE_LIMIT, 3201 100000, 3202 &link); 3203 if (ret_val) 3204 goto out; 3205 3206 if (!link) 3207 DEBUGOUT("Link taking longer than expected.\n"); 3208 3209 /* Try once more */ 3210 ret_val = e1000_phy_has_link_generic(hw, 3211 PHY_FORCE_LIMIT, 3212 100000, 3213 &link); 3214 if (ret_val) 3215 goto out; 3216 } 3217 3218 out: 3219 return ret_val; 3220 } 3221 3222 /** 3223 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3224 * @hw: pointer to the HW structure 3225 * 3226 * Read PHY status to determine if link is up. If link is up, then 3227 * set/determine 10base-T extended distance and polarity correction. Read 3228 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3229 * determine on the cable length, local and remote receiver. 3230 **/ 3231 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3232 { 3233 struct e1000_phy_info *phy = &hw->phy; 3234 s32 ret_val; 3235 u16 data; 3236 bool link; 3237 3238 DEBUGFUNC("e1000_get_phy_info_82577"); 3239 3240 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3241 if (ret_val) 3242 goto out; 3243 3244 if (!link) { 3245 DEBUGOUT("Phy info is only valid if link is up\n"); 3246 ret_val = -E1000_ERR_CONFIG; 3247 goto out; 3248 } 3249 3250 phy->polarity_correction = TRUE; 3251 3252 ret_val = e1000_check_polarity_82577(hw); 3253 if (ret_val) 3254 goto out; 3255 3256 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3257 if (ret_val) 3258 goto out; 3259 3260 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE; 3261 3262 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3263 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3264 ret_val = hw->phy.ops.get_cable_length(hw); 3265 if (ret_val) 3266 goto out; 3267 3268 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3269 if (ret_val) 3270 goto out; 3271 3272 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3273 ? e1000_1000t_rx_status_ok 3274 : e1000_1000t_rx_status_not_ok; 3275 3276 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3277 ? e1000_1000t_rx_status_ok 3278 : e1000_1000t_rx_status_not_ok; 3279 } else { 3280 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3281 phy->local_rx = e1000_1000t_rx_status_undefined; 3282 phy->remote_rx = e1000_1000t_rx_status_undefined; 3283 } 3284 3285 out: 3286 return ret_val; 3287 } 3288 3289 /** 3290 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3291 * @hw: pointer to the HW structure 3292 * 3293 * Reads the diagnostic status register and verifies result is valid before 3294 * placing it in the phy_cable_length field. 3295 **/ 3296 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3297 { 3298 struct e1000_phy_info *phy = &hw->phy; 3299 s32 ret_val; 3300 u16 phy_data, length; 3301 3302 DEBUGFUNC("e1000_get_cable_length_82577"); 3303 3304 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3305 if (ret_val) 3306 goto out; 3307 3308 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3309 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3310 3311 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3312 ret_val = E1000_ERR_PHY; 3313 3314 phy->cable_length = length; 3315 3316 out: 3317 return ret_val; 3318 } 3319