xref: /freebsd/sys/dev/e1000/e1000_phy.c (revision 3332f1b444d4a73238e9f59cca27bfc95fe936bd)
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2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2020, Intel Corporation
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6 
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33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #include "e1000_api.h"
37 
38 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
39 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
40 					  u16 *data, bool read, bool page_set);
41 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
42 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
43 					  u16 *data, bool read);
44 
45 /* Cable length tables */
46 static const u16 e1000_m88_cable_length_table[] = {
47 	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
48 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
49 		(sizeof(e1000_m88_cable_length_table) / \
50 		 sizeof(e1000_m88_cable_length_table[0]))
51 
52 static const u16 e1000_igp_2_cable_length_table[] = {
53 	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
54 	6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
55 	26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
56 	44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
57 	66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
58 	87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
59 	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
60 	124};
61 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
62 		(sizeof(e1000_igp_2_cable_length_table) / \
63 		 sizeof(e1000_igp_2_cable_length_table[0]))
64 
65 /**
66  *  e1000_init_phy_ops_generic - Initialize PHY function pointers
67  *  @hw: pointer to the HW structure
68  *
69  *  Setups up the function pointers to no-op functions
70  **/
71 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 {
73 	struct e1000_phy_info *phy = &hw->phy;
74 	DEBUGFUNC("e1000_init_phy_ops_generic");
75 
76 	/* Initialize function pointers */
77 	phy->ops.init_params = e1000_null_ops_generic;
78 	phy->ops.acquire = e1000_null_ops_generic;
79 	phy->ops.check_polarity = e1000_null_ops_generic;
80 	phy->ops.check_reset_block = e1000_null_ops_generic;
81 	phy->ops.commit = e1000_null_ops_generic;
82 	phy->ops.force_speed_duplex = e1000_null_ops_generic;
83 	phy->ops.get_cfg_done = e1000_null_ops_generic;
84 	phy->ops.get_cable_length = e1000_null_ops_generic;
85 	phy->ops.get_info = e1000_null_ops_generic;
86 	phy->ops.set_page = e1000_null_set_page;
87 	phy->ops.read_reg = e1000_null_read_reg;
88 	phy->ops.read_reg_locked = e1000_null_read_reg;
89 	phy->ops.read_reg_page = e1000_null_read_reg;
90 	phy->ops.release = e1000_null_phy_generic;
91 	phy->ops.reset = e1000_null_ops_generic;
92 	phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
93 	phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
94 	phy->ops.write_reg = e1000_null_write_reg;
95 	phy->ops.write_reg_locked = e1000_null_write_reg;
96 	phy->ops.write_reg_page = e1000_null_write_reg;
97 	phy->ops.power_up = e1000_null_phy_generic;
98 	phy->ops.power_down = e1000_null_phy_generic;
99 	phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
100 	phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
101 	phy->ops.cfg_on_link_up = e1000_null_ops_generic;
102 }
103 
104 /**
105  *  e1000_null_set_page - No-op function, return 0
106  *  @hw: pointer to the HW structure
107  *  @data: dummy variable
108  **/
109 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
110 			u16 E1000_UNUSEDARG data)
111 {
112 	DEBUGFUNC("e1000_null_set_page");
113 	return E1000_SUCCESS;
114 }
115 
116 /**
117  *  e1000_null_read_reg - No-op function, return 0
118  *  @hw: pointer to the HW structure
119  *  @offset: dummy variable
120  *  @data: dummy variable
121  **/
122 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
123 			u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
124 {
125 	DEBUGFUNC("e1000_null_read_reg");
126 	return E1000_SUCCESS;
127 }
128 
129 /**
130  *  e1000_null_phy_generic - No-op function, return void
131  *  @hw: pointer to the HW structure
132  **/
133 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
134 {
135 	DEBUGFUNC("e1000_null_phy_generic");
136 	return;
137 }
138 
139 /**
140  *  e1000_null_lplu_state - No-op function, return 0
141  *  @hw: pointer to the HW structure
142  *  @active: dummy variable
143  **/
144 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
145 			  bool E1000_UNUSEDARG active)
146 {
147 	DEBUGFUNC("e1000_null_lplu_state");
148 	return E1000_SUCCESS;
149 }
150 
151 /**
152  *  e1000_null_write_reg - No-op function, return 0
153  *  @hw: pointer to the HW structure
154  *  @offset: dummy variable
155  *  @data: dummy variable
156  **/
157 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
158 			 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
159 {
160 	DEBUGFUNC("e1000_null_write_reg");
161 	return E1000_SUCCESS;
162 }
163 
164 /**
165  *  e1000_read_i2c_byte_null - No-op function, return 0
166  *  @hw: pointer to hardware structure
167  *  @byte_offset: byte offset to write
168  *  @dev_addr: device address
169  *  @data: data value read
170  *
171  **/
172 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
173 			     u8 E1000_UNUSEDARG byte_offset,
174 			     u8 E1000_UNUSEDARG dev_addr,
175 			     u8 E1000_UNUSEDARG *data)
176 {
177 	DEBUGFUNC("e1000_read_i2c_byte_null");
178 	return E1000_SUCCESS;
179 }
180 
181 /**
182  *  e1000_write_i2c_byte_null - No-op function, return 0
183  *  @hw: pointer to hardware structure
184  *  @byte_offset: byte offset to write
185  *  @dev_addr: device address
186  *  @data: data value to write
187  *
188  **/
189 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
190 			      u8 E1000_UNUSEDARG byte_offset,
191 			      u8 E1000_UNUSEDARG dev_addr,
192 			      u8 E1000_UNUSEDARG data)
193 {
194 	DEBUGFUNC("e1000_write_i2c_byte_null");
195 	return E1000_SUCCESS;
196 }
197 
198 /**
199  *  e1000_check_reset_block_generic - Check if PHY reset is blocked
200  *  @hw: pointer to the HW structure
201  *
202  *  Read the PHY management control register and check whether a PHY reset
203  *  is blocked.  If a reset is not blocked return E1000_SUCCESS, otherwise
204  *  return E1000_BLK_PHY_RESET (12).
205  **/
206 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
207 {
208 	u32 manc;
209 
210 	DEBUGFUNC("e1000_check_reset_block");
211 
212 	manc = E1000_READ_REG(hw, E1000_MANC);
213 
214 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
215 	       E1000_BLK_PHY_RESET : E1000_SUCCESS;
216 }
217 
218 /**
219  *  e1000_get_phy_id - Retrieve the PHY ID and revision
220  *  @hw: pointer to the HW structure
221  *
222  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
223  *  revision in the hardware structure.
224  **/
225 s32 e1000_get_phy_id(struct e1000_hw *hw)
226 {
227 	struct e1000_phy_info *phy = &hw->phy;
228 	s32 ret_val = E1000_SUCCESS;
229 	u16 phy_id;
230 	u16 retry_count = 0;
231 
232 	DEBUGFUNC("e1000_get_phy_id");
233 
234 	if (!phy->ops.read_reg)
235 		return E1000_SUCCESS;
236 
237 	while (retry_count < 2) {
238 		ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
239 		if (ret_val)
240 			return ret_val;
241 
242 		phy->id = (u32)(phy_id << 16);
243 		usec_delay(20);
244 		ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
245 		if (ret_val)
246 			return ret_val;
247 
248 		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
249 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
250 
251 		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
252 			return E1000_SUCCESS;
253 
254 		retry_count++;
255 	}
256 
257 	return E1000_SUCCESS;
258 }
259 
260 /**
261  *  e1000_phy_reset_dsp_generic - Reset PHY DSP
262  *  @hw: pointer to the HW structure
263  *
264  *  Reset the digital signal processor.
265  **/
266 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
267 {
268 	s32 ret_val;
269 
270 	DEBUGFUNC("e1000_phy_reset_dsp_generic");
271 
272 	if (!hw->phy.ops.write_reg)
273 		return E1000_SUCCESS;
274 
275 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
276 	if (ret_val)
277 		return ret_val;
278 
279 	return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
280 }
281 
282 /**
283  *  e1000_read_phy_reg_mdic - Read MDI control register
284  *  @hw: pointer to the HW structure
285  *  @offset: register offset to be read
286  *  @data: pointer to the read data
287  *
288  *  Reads the MDI control register in the PHY at offset and stores the
289  *  information read to data.
290  **/
291 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
292 {
293 	struct e1000_phy_info *phy = &hw->phy;
294 	u32 i, mdic = 0;
295 
296 	DEBUGFUNC("e1000_read_phy_reg_mdic");
297 
298 	if (offset > MAX_PHY_REG_ADDRESS) {
299 		DEBUGOUT1("PHY Address %d is out of range\n", offset);
300 		return -E1000_ERR_PARAM;
301 	}
302 
303 	/* Set up Op-code, Phy Address, and register offset in the MDI
304 	 * Control register.  The MAC will take care of interfacing with the
305 	 * PHY to retrieve the desired data.
306 	 */
307 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
308 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
309 		(E1000_MDIC_OP_READ));
310 
311 	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
312 
313 	/* Poll the ready bit to see if the MDI read completed
314 	 * Increasing the time out as testing showed failures with
315 	 * the lower time out
316 	 */
317 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
318 		usec_delay_irq(50);
319 		mdic = E1000_READ_REG(hw, E1000_MDIC);
320 		if (mdic & E1000_MDIC_READY)
321 			break;
322 	}
323 	if (!(mdic & E1000_MDIC_READY)) {
324 		DEBUGOUT("MDI Read did not complete\n");
325 		return -E1000_ERR_PHY;
326 	}
327 	if (mdic & E1000_MDIC_ERROR) {
328 		DEBUGOUT("MDI Error\n");
329 		return -E1000_ERR_PHY;
330 	}
331 	if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
332 		DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
333 			  offset,
334 			  (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
335 		return -E1000_ERR_PHY;
336 	}
337 	*data = (u16) mdic;
338 
339 	/* Allow some time after each MDIC transaction to avoid
340 	 * reading duplicate data in the next MDIC transaction.
341 	 */
342 	if (hw->mac.type == e1000_pch2lan)
343 		usec_delay_irq(100);
344 
345 	return E1000_SUCCESS;
346 }
347 
348 /**
349  *  e1000_write_phy_reg_mdic - Write MDI control register
350  *  @hw: pointer to the HW structure
351  *  @offset: register offset to write to
352  *  @data: data to write to register at offset
353  *
354  *  Writes data to MDI control register in the PHY at offset.
355  **/
356 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
357 {
358 	struct e1000_phy_info *phy = &hw->phy;
359 	u32 i, mdic = 0;
360 
361 	DEBUGFUNC("e1000_write_phy_reg_mdic");
362 
363 	if (offset > MAX_PHY_REG_ADDRESS) {
364 		DEBUGOUT1("PHY Address %d is out of range\n", offset);
365 		return -E1000_ERR_PARAM;
366 	}
367 
368 	/* Set up Op-code, Phy Address, and register offset in the MDI
369 	 * Control register.  The MAC will take care of interfacing with the
370 	 * PHY to retrieve the desired data.
371 	 */
372 	mdic = (((u32)data) |
373 		(offset << E1000_MDIC_REG_SHIFT) |
374 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
375 		(E1000_MDIC_OP_WRITE));
376 
377 	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
378 
379 	/* Poll the ready bit to see if the MDI read completed
380 	 * Increasing the time out as testing showed failures with
381 	 * the lower time out
382 	 */
383 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
384 		usec_delay_irq(50);
385 		mdic = E1000_READ_REG(hw, E1000_MDIC);
386 		if (mdic & E1000_MDIC_READY)
387 			break;
388 	}
389 	if (!(mdic & E1000_MDIC_READY)) {
390 		DEBUGOUT("MDI Write did not complete\n");
391 		return -E1000_ERR_PHY;
392 	}
393 	if (mdic & E1000_MDIC_ERROR) {
394 		DEBUGOUT("MDI Error\n");
395 		return -E1000_ERR_PHY;
396 	}
397 	if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
398 		DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
399 			  offset,
400 			  (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
401 		return -E1000_ERR_PHY;
402 	}
403 
404 	/* Allow some time after each MDIC transaction to avoid
405 	 * reading duplicate data in the next MDIC transaction.
406 	 */
407 	if (hw->mac.type == e1000_pch2lan)
408 		usec_delay_irq(100);
409 
410 	return E1000_SUCCESS;
411 }
412 
413 /**
414  *  e1000_read_phy_reg_i2c - Read PHY register using i2c
415  *  @hw: pointer to the HW structure
416  *  @offset: register offset to be read
417  *  @data: pointer to the read data
418  *
419  *  Reads the PHY register at offset using the i2c interface and stores the
420  *  retrieved information in data.
421  **/
422 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
423 {
424 	struct e1000_phy_info *phy = &hw->phy;
425 	u32 i, i2ccmd = 0;
426 
427 	DEBUGFUNC("e1000_read_phy_reg_i2c");
428 
429 	/* Set up Op-code, Phy Address, and register address in the I2CCMD
430 	 * register.  The MAC will take care of interfacing with the
431 	 * PHY to retrieve the desired data.
432 	 */
433 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
434 		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
435 		  (E1000_I2CCMD_OPCODE_READ));
436 
437 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
438 
439 	/* Poll the ready bit to see if the I2C read completed */
440 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
441 		usec_delay(50);
442 		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
443 		if (i2ccmd & E1000_I2CCMD_READY)
444 			break;
445 	}
446 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
447 		DEBUGOUT("I2CCMD Read did not complete\n");
448 		return -E1000_ERR_PHY;
449 	}
450 	if (i2ccmd & E1000_I2CCMD_ERROR) {
451 		DEBUGOUT("I2CCMD Error bit set\n");
452 		return -E1000_ERR_PHY;
453 	}
454 
455 	/* Need to byte-swap the 16-bit value. */
456 	*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
457 
458 	return E1000_SUCCESS;
459 }
460 
461 /**
462  *  e1000_write_phy_reg_i2c - Write PHY register using i2c
463  *  @hw: pointer to the HW structure
464  *  @offset: register offset to write to
465  *  @data: data to write at register offset
466  *
467  *  Writes the data to PHY register at the offset using the i2c interface.
468  **/
469 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
470 {
471 	struct e1000_phy_info *phy = &hw->phy;
472 	u32 i, i2ccmd = 0;
473 	u16 phy_data_swapped;
474 
475 	DEBUGFUNC("e1000_write_phy_reg_i2c");
476 
477 	/* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
478 	if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
479 		DEBUGOUT1("PHY I2C Address %d is out of range.\n",
480 			  hw->phy.addr);
481 		return -E1000_ERR_CONFIG;
482 	}
483 
484 	/* Swap the data bytes for the I2C interface */
485 	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
486 
487 	/* Set up Op-code, Phy Address, and register address in the I2CCMD
488 	 * register.  The MAC will take care of interfacing with the
489 	 * PHY to retrieve the desired data.
490 	 */
491 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
492 		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
493 		  E1000_I2CCMD_OPCODE_WRITE |
494 		  phy_data_swapped);
495 
496 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
497 
498 	/* Poll the ready bit to see if the I2C read completed */
499 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
500 		usec_delay(50);
501 		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
502 		if (i2ccmd & E1000_I2CCMD_READY)
503 			break;
504 	}
505 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
506 		DEBUGOUT("I2CCMD Write did not complete\n");
507 		return -E1000_ERR_PHY;
508 	}
509 	if (i2ccmd & E1000_I2CCMD_ERROR) {
510 		DEBUGOUT("I2CCMD Error bit set\n");
511 		return -E1000_ERR_PHY;
512 	}
513 
514 	return E1000_SUCCESS;
515 }
516 
517 /**
518  *  e1000_read_sfp_data_byte - Reads SFP module data.
519  *  @hw: pointer to the HW structure
520  *  @offset: byte location offset to be read
521  *  @data: read data buffer pointer
522  *
523  *  Reads one byte from SFP module data stored
524  *  in SFP resided EEPROM memory or SFP diagnostic area.
525  *  Function should be called with
526  *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
527  *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
528  *  access
529  **/
530 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
531 {
532 	u32 i = 0;
533 	u32 i2ccmd = 0;
534 	u32 data_local = 0;
535 
536 	DEBUGFUNC("e1000_read_sfp_data_byte");
537 
538 	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
539 		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
540 		return -E1000_ERR_PHY;
541 	}
542 
543 	/* Set up Op-code, EEPROM Address,in the I2CCMD
544 	 * register. The MAC will take care of interfacing with the
545 	 * EEPROM to retrieve the desired data.
546 	 */
547 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
548 		  E1000_I2CCMD_OPCODE_READ);
549 
550 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
551 
552 	/* Poll the ready bit to see if the I2C read completed */
553 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
554 		usec_delay(50);
555 		data_local = E1000_READ_REG(hw, E1000_I2CCMD);
556 		if (data_local & E1000_I2CCMD_READY)
557 			break;
558 	}
559 	if (!(data_local & E1000_I2CCMD_READY)) {
560 		DEBUGOUT("I2CCMD Read did not complete\n");
561 		return -E1000_ERR_PHY;
562 	}
563 	if (data_local & E1000_I2CCMD_ERROR) {
564 		DEBUGOUT("I2CCMD Error bit set\n");
565 		return -E1000_ERR_PHY;
566 	}
567 	*data = (u8) data_local & 0xFF;
568 
569 	return E1000_SUCCESS;
570 }
571 
572 /**
573  *  e1000_write_sfp_data_byte - Writes SFP module data.
574  *  @hw: pointer to the HW structure
575  *  @offset: byte location offset to write to
576  *  @data: data to write
577  *
578  *  Writes one byte to SFP module data stored
579  *  in SFP resided EEPROM memory or SFP diagnostic area.
580  *  Function should be called with
581  *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
582  *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
583  *  access
584  **/
585 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
586 {
587 	u32 i = 0;
588 	u32 i2ccmd = 0;
589 	u32 data_local = 0;
590 
591 	DEBUGFUNC("e1000_write_sfp_data_byte");
592 
593 	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
594 		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
595 		return -E1000_ERR_PHY;
596 	}
597 	/* The programming interface is 16 bits wide
598 	 * so we need to read the whole word first
599 	 * then update appropriate byte lane and write
600 	 * the updated word back.
601 	 */
602 	/* Set up Op-code, EEPROM Address,in the I2CCMD
603 	 * register. The MAC will take care of interfacing
604 	 * with an EEPROM to write the data given.
605 	 */
606 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
607 		  E1000_I2CCMD_OPCODE_READ);
608 	/* Set a command to read single word */
609 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
610 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
611 		usec_delay(50);
612 		/* Poll the ready bit to see if lastly
613 		 * launched I2C operation completed
614 		 */
615 		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
616 		if (i2ccmd & E1000_I2CCMD_READY) {
617 			/* Check if this is READ or WRITE phase */
618 			if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
619 			    E1000_I2CCMD_OPCODE_READ) {
620 				/* Write the selected byte
621 				 * lane and update whole word
622 				 */
623 				data_local = i2ccmd & 0xFF00;
624 				data_local |= (u32)data;
625 				i2ccmd = ((offset <<
626 					E1000_I2CCMD_REG_ADDR_SHIFT) |
627 					E1000_I2CCMD_OPCODE_WRITE | data_local);
628 				E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
629 			} else {
630 				break;
631 			}
632 		}
633 	}
634 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
635 		DEBUGOUT("I2CCMD Write did not complete\n");
636 		return -E1000_ERR_PHY;
637 	}
638 	if (i2ccmd & E1000_I2CCMD_ERROR) {
639 		DEBUGOUT("I2CCMD Error bit set\n");
640 		return -E1000_ERR_PHY;
641 	}
642 	return E1000_SUCCESS;
643 }
644 
645 /**
646  *  e1000_read_phy_reg_m88 - Read m88 PHY register
647  *  @hw: pointer to the HW structure
648  *  @offset: register offset to be read
649  *  @data: pointer to the read data
650  *
651  *  Acquires semaphore, if necessary, then reads the PHY register at offset
652  *  and storing the retrieved information in data.  Release any acquired
653  *  semaphores before exiting.
654  **/
655 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
656 {
657 	s32 ret_val;
658 
659 	DEBUGFUNC("e1000_read_phy_reg_m88");
660 
661 	if (!hw->phy.ops.acquire)
662 		return E1000_SUCCESS;
663 
664 	ret_val = hw->phy.ops.acquire(hw);
665 	if (ret_val)
666 		return ret_val;
667 
668 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
669 					  data);
670 
671 	hw->phy.ops.release(hw);
672 
673 	return ret_val;
674 }
675 
676 /**
677  *  e1000_write_phy_reg_m88 - Write m88 PHY register
678  *  @hw: pointer to the HW structure
679  *  @offset: register offset to write to
680  *  @data: data to write at register offset
681  *
682  *  Acquires semaphore, if necessary, then writes the data to PHY register
683  *  at the offset.  Release any acquired semaphores before exiting.
684  **/
685 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
686 {
687 	s32 ret_val;
688 
689 	DEBUGFUNC("e1000_write_phy_reg_m88");
690 
691 	if (!hw->phy.ops.acquire)
692 		return E1000_SUCCESS;
693 
694 	ret_val = hw->phy.ops.acquire(hw);
695 	if (ret_val)
696 		return ret_val;
697 
698 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
699 					   data);
700 
701 	hw->phy.ops.release(hw);
702 
703 	return ret_val;
704 }
705 
706 /**
707  *  e1000_set_page_igp - Set page as on IGP-like PHY(s)
708  *  @hw: pointer to the HW structure
709  *  @page: page to set (shifted left when necessary)
710  *
711  *  Sets PHY page required for PHY register access.  Assumes semaphore is
712  *  already acquired.  Note, this function sets phy.addr to 1 so the caller
713  *  must set it appropriately (if necessary) after this function returns.
714  **/
715 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
716 {
717 	DEBUGFUNC("e1000_set_page_igp");
718 
719 	DEBUGOUT1("Setting page 0x%x\n", page);
720 
721 	hw->phy.addr = 1;
722 
723 	return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
724 }
725 
726 /**
727  *  __e1000_read_phy_reg_igp - Read igp PHY register
728  *  @hw: pointer to the HW structure
729  *  @offset: register offset to be read
730  *  @data: pointer to the read data
731  *  @locked: semaphore has already been acquired or not
732  *
733  *  Acquires semaphore, if necessary, then reads the PHY register at offset
734  *  and stores the retrieved information in data.  Release any acquired
735  *  semaphores before exiting.
736  **/
737 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
738 				    bool locked)
739 {
740 	s32 ret_val = E1000_SUCCESS;
741 
742 	DEBUGFUNC("__e1000_read_phy_reg_igp");
743 
744 	if (!locked) {
745 		if (!hw->phy.ops.acquire)
746 			return E1000_SUCCESS;
747 
748 		ret_val = hw->phy.ops.acquire(hw);
749 		if (ret_val)
750 			return ret_val;
751 	}
752 
753 	if (offset > MAX_PHY_MULTI_PAGE_REG)
754 		ret_val = e1000_write_phy_reg_mdic(hw,
755 						   IGP01E1000_PHY_PAGE_SELECT,
756 						   (u16)offset);
757 	if (!ret_val)
758 		ret_val = e1000_read_phy_reg_mdic(hw,
759 						  MAX_PHY_REG_ADDRESS & offset,
760 						  data);
761 	if (!locked)
762 		hw->phy.ops.release(hw);
763 
764 	return ret_val;
765 }
766 
767 /**
768  *  e1000_read_phy_reg_igp - Read igp PHY register
769  *  @hw: pointer to the HW structure
770  *  @offset: register offset to be read
771  *  @data: pointer to the read data
772  *
773  *  Acquires semaphore then reads the PHY register at offset and stores the
774  *  retrieved information in data.
775  *  Release the acquired semaphore before exiting.
776  **/
777 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
778 {
779 	return __e1000_read_phy_reg_igp(hw, offset, data, false);
780 }
781 
782 /**
783  *  e1000_read_phy_reg_igp_locked - Read igp PHY register
784  *  @hw: pointer to the HW structure
785  *  @offset: register offset to be read
786  *  @data: pointer to the read data
787  *
788  *  Reads the PHY register at offset and stores the retrieved information
789  *  in data.  Assumes semaphore already acquired.
790  **/
791 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
792 {
793 	return __e1000_read_phy_reg_igp(hw, offset, data, true);
794 }
795 
796 /**
797  *  e1000_write_phy_reg_igp - Write igp PHY register
798  *  @hw: pointer to the HW structure
799  *  @offset: register offset to write to
800  *  @data: data to write at register offset
801  *  @locked: semaphore has already been acquired or not
802  *
803  *  Acquires semaphore, if necessary, then writes the data to PHY register
804  *  at the offset.  Release any acquired semaphores before exiting.
805  **/
806 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
807 				     bool locked)
808 {
809 	s32 ret_val = E1000_SUCCESS;
810 
811 	DEBUGFUNC("e1000_write_phy_reg_igp");
812 
813 	if (!locked) {
814 		if (!hw->phy.ops.acquire)
815 			return E1000_SUCCESS;
816 
817 		ret_val = hw->phy.ops.acquire(hw);
818 		if (ret_val)
819 			return ret_val;
820 	}
821 
822 	if (offset > MAX_PHY_MULTI_PAGE_REG)
823 		ret_val = e1000_write_phy_reg_mdic(hw,
824 						   IGP01E1000_PHY_PAGE_SELECT,
825 						   (u16)offset);
826 	if (!ret_val)
827 		ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
828 						       offset,
829 						   data);
830 	if (!locked)
831 		hw->phy.ops.release(hw);
832 
833 	return ret_val;
834 }
835 
836 /**
837  *  e1000_write_phy_reg_igp - Write igp PHY register
838  *  @hw: pointer to the HW structure
839  *  @offset: register offset to write to
840  *  @data: data to write at register offset
841  *
842  *  Acquires semaphore then writes the data to PHY register
843  *  at the offset.  Release any acquired semaphores before exiting.
844  **/
845 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
846 {
847 	return __e1000_write_phy_reg_igp(hw, offset, data, false);
848 }
849 
850 /**
851  *  e1000_write_phy_reg_igp_locked - Write igp PHY register
852  *  @hw: pointer to the HW structure
853  *  @offset: register offset to write to
854  *  @data: data to write at register offset
855  *
856  *  Writes the data to PHY register at the offset.
857  *  Assumes semaphore already acquired.
858  **/
859 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
860 {
861 	return __e1000_write_phy_reg_igp(hw, offset, data, true);
862 }
863 
864 /**
865  *  __e1000_read_kmrn_reg - Read kumeran register
866  *  @hw: pointer to the HW structure
867  *  @offset: register offset to be read
868  *  @data: pointer to the read data
869  *  @locked: semaphore has already been acquired or not
870  *
871  *  Acquires semaphore, if necessary.  Then reads the PHY register at offset
872  *  using the kumeran interface.  The information retrieved is stored in data.
873  *  Release any acquired semaphores before exiting.
874  **/
875 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
876 				 bool locked)
877 {
878 	u32 kmrnctrlsta;
879 
880 	DEBUGFUNC("__e1000_read_kmrn_reg");
881 
882 	if (!locked) {
883 		s32 ret_val = E1000_SUCCESS;
884 
885 		if (!hw->phy.ops.acquire)
886 			return E1000_SUCCESS;
887 
888 		ret_val = hw->phy.ops.acquire(hw);
889 		if (ret_val)
890 			return ret_val;
891 	}
892 
893 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
894 		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
895 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
896 	E1000_WRITE_FLUSH(hw);
897 
898 	usec_delay(2);
899 
900 	kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
901 	*data = (u16)kmrnctrlsta;
902 
903 	if (!locked)
904 		hw->phy.ops.release(hw);
905 
906 	return E1000_SUCCESS;
907 }
908 
909 /**
910  *  e1000_read_kmrn_reg_generic -  Read kumeran register
911  *  @hw: pointer to the HW structure
912  *  @offset: register offset to be read
913  *  @data: pointer to the read data
914  *
915  *  Acquires semaphore then reads the PHY register at offset using the
916  *  kumeran interface.  The information retrieved is stored in data.
917  *  Release the acquired semaphore before exiting.
918  **/
919 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
920 {
921 	return __e1000_read_kmrn_reg(hw, offset, data, false);
922 }
923 
924 /**
925  *  e1000_read_kmrn_reg_locked -  Read kumeran register
926  *  @hw: pointer to the HW structure
927  *  @offset: register offset to be read
928  *  @data: pointer to the read data
929  *
930  *  Reads the PHY register at offset using the kumeran interface.  The
931  *  information retrieved is stored in data.
932  *  Assumes semaphore already acquired.
933  **/
934 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
935 {
936 	return __e1000_read_kmrn_reg(hw, offset, data, true);
937 }
938 
939 /**
940  *  __e1000_write_kmrn_reg - Write kumeran register
941  *  @hw: pointer to the HW structure
942  *  @offset: register offset to write to
943  *  @data: data to write at register offset
944  *  @locked: semaphore has already been acquired or not
945  *
946  *  Acquires semaphore, if necessary.  Then write the data to PHY register
947  *  at the offset using the kumeran interface.  Release any acquired semaphores
948  *  before exiting.
949  **/
950 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
951 				  bool locked)
952 {
953 	u32 kmrnctrlsta;
954 
955 	DEBUGFUNC("e1000_write_kmrn_reg_generic");
956 
957 	if (!locked) {
958 		s32 ret_val = E1000_SUCCESS;
959 
960 		if (!hw->phy.ops.acquire)
961 			return E1000_SUCCESS;
962 
963 		ret_val = hw->phy.ops.acquire(hw);
964 		if (ret_val)
965 			return ret_val;
966 	}
967 
968 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
969 		       E1000_KMRNCTRLSTA_OFFSET) | data;
970 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
971 	E1000_WRITE_FLUSH(hw);
972 
973 	usec_delay(2);
974 
975 	if (!locked)
976 		hw->phy.ops.release(hw);
977 
978 	return E1000_SUCCESS;
979 }
980 
981 /**
982  *  e1000_write_kmrn_reg_generic -  Write kumeran register
983  *  @hw: pointer to the HW structure
984  *  @offset: register offset to write to
985  *  @data: data to write at register offset
986  *
987  *  Acquires semaphore then writes the data to the PHY register at the offset
988  *  using the kumeran interface.  Release the acquired semaphore before exiting.
989  **/
990 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
991 {
992 	return __e1000_write_kmrn_reg(hw, offset, data, false);
993 }
994 
995 /**
996  *  e1000_write_kmrn_reg_locked -  Write kumeran register
997  *  @hw: pointer to the HW structure
998  *  @offset: register offset to write to
999  *  @data: data to write at register offset
1000  *
1001  *  Write the data to PHY register at the offset using the kumeran interface.
1002  *  Assumes semaphore already acquired.
1003  **/
1004 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1005 {
1006 	return __e1000_write_kmrn_reg(hw, offset, data, true);
1007 }
1008 
1009 /**
1010  *  e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1011  *  @hw: pointer to the HW structure
1012  *
1013  *  Sets up Master/slave mode
1014  **/
1015 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1016 {
1017 	s32 ret_val;
1018 	u16 phy_data;
1019 
1020 	/* Resolve Master/Slave mode */
1021 	ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1022 	if (ret_val)
1023 		return ret_val;
1024 
1025 	/* load defaults for future use */
1026 	hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1027 				   ((phy_data & CR_1000T_MS_VALUE) ?
1028 				    e1000_ms_force_master :
1029 				    e1000_ms_force_slave) : e1000_ms_auto;
1030 
1031 	switch (hw->phy.ms_type) {
1032 	case e1000_ms_force_master:
1033 		phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1034 		break;
1035 	case e1000_ms_force_slave:
1036 		phy_data |= CR_1000T_MS_ENABLE;
1037 		phy_data &= ~(CR_1000T_MS_VALUE);
1038 		break;
1039 	case e1000_ms_auto:
1040 		phy_data &= ~CR_1000T_MS_ENABLE;
1041 		/* FALLTHROUGH */
1042 	default:
1043 		break;
1044 	}
1045 
1046 	return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1047 }
1048 
1049 /**
1050  *  e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1051  *  @hw: pointer to the HW structure
1052  *
1053  *  Sets up Carrier-sense on Transmit and downshift values.
1054  **/
1055 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1056 {
1057 	s32 ret_val;
1058 	u16 phy_data;
1059 
1060 	DEBUGFUNC("e1000_copper_link_setup_82577");
1061 
1062 	if (hw->phy.type == e1000_phy_82580) {
1063 		ret_val = hw->phy.ops.reset(hw);
1064 		if (ret_val) {
1065 			DEBUGOUT("Error resetting the PHY.\n");
1066 			return ret_val;
1067 		}
1068 	}
1069 
1070 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
1071 	ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1072 	if (ret_val)
1073 		return ret_val;
1074 
1075 	phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1076 
1077 	/* Enable downshift */
1078 	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1079 
1080 	ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1081 	if (ret_val)
1082 		return ret_val;
1083 
1084 	/* Set MDI/MDIX mode */
1085 	ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1086 	if (ret_val)
1087 		return ret_val;
1088 	phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1089 	/* Options:
1090 	 *   0 - Auto (default)
1091 	 *   1 - MDI mode
1092 	 *   2 - MDI-X mode
1093 	 */
1094 	switch (hw->phy.mdix) {
1095 	case 1:
1096 		break;
1097 	case 2:
1098 		phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1099 		break;
1100 	case 0:
1101 		/* FALLTHROUGH */
1102 	default:
1103 		phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1104 		break;
1105 	}
1106 	ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1107 	if (ret_val)
1108 		return ret_val;
1109 
1110 	return e1000_set_master_slave_mode(hw);
1111 }
1112 
1113 /**
1114  *  e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1115  *  @hw: pointer to the HW structure
1116  *
1117  *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
1118  *  and downshift values are set also.
1119  **/
1120 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1121 {
1122 	struct e1000_phy_info *phy = &hw->phy;
1123 	s32 ret_val;
1124 	u16 phy_data;
1125 
1126 	DEBUGFUNC("e1000_copper_link_setup_m88");
1127 
1128 
1129 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
1130 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1131 	if (ret_val)
1132 		return ret_val;
1133 
1134 	/* For BM PHY this bit is downshift enable */
1135 	if (phy->type != e1000_phy_bm)
1136 		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1137 
1138 	/* Options:
1139 	 *   MDI/MDI-X = 0 (default)
1140 	 *   0 - Auto for all speeds
1141 	 *   1 - MDI mode
1142 	 *   2 - MDI-X mode
1143 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1144 	 */
1145 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1146 
1147 	switch (phy->mdix) {
1148 	case 1:
1149 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1150 		break;
1151 	case 2:
1152 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1153 		break;
1154 	case 3:
1155 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1156 		break;
1157 	case 0:
1158 		/* FALLTHROUGH */
1159 	default:
1160 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1161 		break;
1162 	}
1163 
1164 	/* Options:
1165 	 *   disable_polarity_correction = 0 (default)
1166 	 *       Automatic Correction for Reversed Cable Polarity
1167 	 *   0 - Disabled
1168 	 *   1 - Enabled
1169 	 */
1170 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1171 	if (phy->disable_polarity_correction)
1172 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1173 
1174 	/* Enable downshift on BM (disabled by default) */
1175 	if (phy->type == e1000_phy_bm) {
1176 		/* For 82574/82583, first disable then enable downshift */
1177 		if (phy->id == BME1000_E_PHY_ID_R2) {
1178 			phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1179 			ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1180 						     phy_data);
1181 			if (ret_val)
1182 				return ret_val;
1183 			/* Commit the changes. */
1184 			ret_val = phy->ops.commit(hw);
1185 			if (ret_val) {
1186 				DEBUGOUT("Error committing the PHY changes\n");
1187 				return ret_val;
1188 			}
1189 		}
1190 
1191 		phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1192 	}
1193 
1194 	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1195 	if (ret_val)
1196 		return ret_val;
1197 
1198 	if ((phy->type == e1000_phy_m88) &&
1199 	    (phy->revision < E1000_REVISION_4) &&
1200 	    (phy->id != BME1000_E_PHY_ID_R2)) {
1201 		/* Force TX_CLK in the Extended PHY Specific Control Register
1202 		 * to 25MHz clock.
1203 		 */
1204 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1205 					    &phy_data);
1206 		if (ret_val)
1207 			return ret_val;
1208 
1209 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
1210 
1211 		if ((phy->revision == E1000_REVISION_2) &&
1212 		    (phy->id == M88E1111_I_PHY_ID)) {
1213 			/* 82573L PHY - set the downshift counter to 5x. */
1214 			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1215 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1216 		} else {
1217 			/* Configure Master and Slave downshift values */
1218 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1219 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1220 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1221 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1222 		}
1223 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1224 					     phy_data);
1225 		if (ret_val)
1226 			return ret_val;
1227 	}
1228 
1229 	if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1230 		/* Set PHY page 0, register 29 to 0x0003 */
1231 		ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1232 		if (ret_val)
1233 			return ret_val;
1234 
1235 		/* Set PHY page 0, register 30 to 0x0000 */
1236 		ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1237 		if (ret_val)
1238 			return ret_val;
1239 	}
1240 
1241 	/* Commit the changes. */
1242 	ret_val = phy->ops.commit(hw);
1243 	if (ret_val) {
1244 		DEBUGOUT("Error committing the PHY changes\n");
1245 		return ret_val;
1246 	}
1247 
1248 	if (phy->type == e1000_phy_82578) {
1249 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1250 					    &phy_data);
1251 		if (ret_val)
1252 			return ret_val;
1253 
1254 		/* 82578 PHY - set the downshift count to 1x. */
1255 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1256 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1257 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1258 					     phy_data);
1259 		if (ret_val)
1260 			return ret_val;
1261 	}
1262 
1263 	return E1000_SUCCESS;
1264 }
1265 
1266 /**
1267  *  e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1268  *  @hw: pointer to the HW structure
1269  *
1270  *  Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1271  *  Also enables and sets the downshift parameters.
1272  **/
1273 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1274 {
1275 	struct e1000_phy_info *phy = &hw->phy;
1276 	s32 ret_val;
1277 	u16 phy_data;
1278 
1279 	DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1280 
1281 
1282 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
1283 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1284 	if (ret_val)
1285 		return ret_val;
1286 
1287 	/* Options:
1288 	 *   MDI/MDI-X = 0 (default)
1289 	 *   0 - Auto for all speeds
1290 	 *   1 - MDI mode
1291 	 *   2 - MDI-X mode
1292 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1293 	 */
1294 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1295 
1296 	switch (phy->mdix) {
1297 	case 1:
1298 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1299 		break;
1300 	case 2:
1301 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1302 		break;
1303 	case 3:
1304 		/* M88E1112 does not support this mode) */
1305 		if (phy->id != M88E1112_E_PHY_ID) {
1306 			phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1307 			break;
1308 		}
1309 		/* FALLTHROUGH */
1310 	case 0:
1311 		/* FALLTHROUGH */
1312 	default:
1313 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1314 		break;
1315 	}
1316 
1317 	/* Options:
1318 	 *   disable_polarity_correction = 0 (default)
1319 	 *       Automatic Correction for Reversed Cable Polarity
1320 	 *   0 - Disabled
1321 	 *   1 - Enabled
1322 	 */
1323 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1324 	if (phy->disable_polarity_correction)
1325 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1326 
1327 	/* Enable downshift and setting it to X6 */
1328 	if (phy->id == M88E1543_E_PHY_ID) {
1329 		phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1330 		ret_val =
1331 		    phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1332 		if (ret_val)
1333 			return ret_val;
1334 
1335 		ret_val = phy->ops.commit(hw);
1336 		if (ret_val) {
1337 			DEBUGOUT("Error committing the PHY changes\n");
1338 			return ret_val;
1339 		}
1340 	}
1341 
1342 	phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1343 	phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1344 	phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1345 
1346 	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1347 	if (ret_val)
1348 		return ret_val;
1349 
1350 	/* Commit the changes. */
1351 	ret_val = phy->ops.commit(hw);
1352 	if (ret_val) {
1353 		DEBUGOUT("Error committing the PHY changes\n");
1354 		return ret_val;
1355 	}
1356 
1357 	ret_val = e1000_set_master_slave_mode(hw);
1358 	if (ret_val)
1359 		return ret_val;
1360 
1361 	return E1000_SUCCESS;
1362 }
1363 
1364 /**
1365  *  e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1366  *  @hw: pointer to the HW structure
1367  *
1368  *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1369  *  igp PHY's.
1370  **/
1371 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1372 {
1373 	struct e1000_phy_info *phy = &hw->phy;
1374 	s32 ret_val;
1375 	u16 data;
1376 
1377 	DEBUGFUNC("e1000_copper_link_setup_igp");
1378 
1379 
1380 	ret_val = hw->phy.ops.reset(hw);
1381 	if (ret_val) {
1382 		DEBUGOUT("Error resetting the PHY.\n");
1383 		return ret_val;
1384 	}
1385 
1386 	/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1387 	 * timeout issues when LFS is enabled.
1388 	 */
1389 	msec_delay(100);
1390 
1391 	/* The NVM settings will configure LPLU in D3 for
1392 	 * non-IGP1 PHYs.
1393 	 */
1394 	if (phy->type == e1000_phy_igp) {
1395 		/* disable lplu d3 during driver init */
1396 		ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1397 		if (ret_val) {
1398 			DEBUGOUT("Error Disabling LPLU D3\n");
1399 			return ret_val;
1400 		}
1401 	}
1402 
1403 	/* disable lplu d0 during driver init */
1404 	if (hw->phy.ops.set_d0_lplu_state) {
1405 		ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1406 		if (ret_val) {
1407 			DEBUGOUT("Error Disabling LPLU D0\n");
1408 			return ret_val;
1409 		}
1410 	}
1411 	/* Configure mdi-mdix settings */
1412 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1413 	if (ret_val)
1414 		return ret_val;
1415 
1416 	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1417 
1418 	switch (phy->mdix) {
1419 	case 1:
1420 		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1421 		break;
1422 	case 2:
1423 		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1424 		break;
1425 	case 0:
1426 		/* FALLTHROUGH */
1427 	default:
1428 		data |= IGP01E1000_PSCR_AUTO_MDIX;
1429 		break;
1430 	}
1431 	ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1432 	if (ret_val)
1433 		return ret_val;
1434 
1435 	/* set auto-master slave resolution settings */
1436 	if (hw->mac.autoneg) {
1437 		/* when autonegotiation advertisement is only 1000Mbps then we
1438 		 * should disable SmartSpeed and enable Auto MasterSlave
1439 		 * resolution as hardware default.
1440 		 */
1441 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1442 			/* Disable SmartSpeed */
1443 			ret_val = phy->ops.read_reg(hw,
1444 						    IGP01E1000_PHY_PORT_CONFIG,
1445 						    &data);
1446 			if (ret_val)
1447 				return ret_val;
1448 
1449 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1450 			ret_val = phy->ops.write_reg(hw,
1451 						     IGP01E1000_PHY_PORT_CONFIG,
1452 						     data);
1453 			if (ret_val)
1454 				return ret_val;
1455 
1456 			/* Set auto Master/Slave resolution process */
1457 			ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1458 			if (ret_val)
1459 				return ret_val;
1460 
1461 			data &= ~CR_1000T_MS_ENABLE;
1462 			ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1463 			if (ret_val)
1464 				return ret_val;
1465 		}
1466 
1467 		ret_val = e1000_set_master_slave_mode(hw);
1468 	}
1469 
1470 	return ret_val;
1471 }
1472 
1473 /**
1474  *  e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1475  *  @hw: pointer to the HW structure
1476  *
1477  *  Reads the MII auto-neg advertisement register and/or the 1000T control
1478  *  register and if the PHY is already setup for auto-negotiation, then
1479  *  return successful.  Otherwise, setup advertisement and flow control to
1480  *  the appropriate values for the wanted auto-negotiation.
1481  **/
1482 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1483 {
1484 	struct e1000_phy_info *phy = &hw->phy;
1485 	s32 ret_val;
1486 	u16 mii_autoneg_adv_reg;
1487 	u16 mii_1000t_ctrl_reg = 0;
1488 
1489 	DEBUGFUNC("e1000_phy_setup_autoneg");
1490 
1491 	phy->autoneg_advertised &= phy->autoneg_mask;
1492 
1493 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
1494 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1495 	if (ret_val)
1496 		return ret_val;
1497 
1498 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1499 		/* Read the MII 1000Base-T Control Register (Address 9). */
1500 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1501 					    &mii_1000t_ctrl_reg);
1502 		if (ret_val)
1503 			return ret_val;
1504 	}
1505 
1506 	/* Need to parse both autoneg_advertised and fc and set up
1507 	 * the appropriate PHY registers.  First we will parse for
1508 	 * autoneg_advertised software override.  Since we can advertise
1509 	 * a plethora of combinations, we need to check each bit
1510 	 * individually.
1511 	 */
1512 
1513 	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
1514 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1515 	 * the  1000Base-T Control Register (Address 9).
1516 	 */
1517 	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1518 				 NWAY_AR_100TX_HD_CAPS |
1519 				 NWAY_AR_10T_FD_CAPS   |
1520 				 NWAY_AR_10T_HD_CAPS);
1521 	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1522 
1523 	DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1524 
1525 	/* Do we want to advertise 10 Mb Half Duplex? */
1526 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1527 		DEBUGOUT("Advertise 10mb Half duplex\n");
1528 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1529 	}
1530 
1531 	/* Do we want to advertise 10 Mb Full Duplex? */
1532 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1533 		DEBUGOUT("Advertise 10mb Full duplex\n");
1534 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1535 	}
1536 
1537 	/* Do we want to advertise 100 Mb Half Duplex? */
1538 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1539 		DEBUGOUT("Advertise 100mb Half duplex\n");
1540 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1541 	}
1542 
1543 	/* Do we want to advertise 100 Mb Full Duplex? */
1544 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1545 		DEBUGOUT("Advertise 100mb Full duplex\n");
1546 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1547 	}
1548 
1549 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1550 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1551 		DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1552 
1553 	/* Do we want to advertise 1000 Mb Full Duplex? */
1554 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1555 		DEBUGOUT("Advertise 1000mb Full duplex\n");
1556 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1557 	}
1558 
1559 	/* Check for a software override of the flow control settings, and
1560 	 * setup the PHY advertisement registers accordingly.  If
1561 	 * auto-negotiation is enabled, then software will have to set the
1562 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
1563 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1564 	 * negotiation.
1565 	 *
1566 	 * The possible values of the "fc" parameter are:
1567 	 *      0:  Flow control is completely disabled
1568 	 *      1:  Rx flow control is enabled (we can receive pause frames
1569 	 *          but not send pause frames).
1570 	 *      2:  Tx flow control is enabled (we can send pause frames
1571 	 *          but we do not support receiving pause frames).
1572 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
1573 	 *  other:  No software override.  The flow control configuration
1574 	 *          in the EEPROM is used.
1575 	 */
1576 	switch (hw->fc.current_mode) {
1577 	case e1000_fc_none:
1578 		/* Flow control (Rx & Tx) is completely disabled by a
1579 		 * software over-ride.
1580 		 */
1581 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1582 		break;
1583 	case e1000_fc_rx_pause:
1584 		/* Rx Flow control is enabled, and Tx Flow control is
1585 		 * disabled, by a software over-ride.
1586 		 *
1587 		 * Since there really isn't a way to advertise that we are
1588 		 * capable of Rx Pause ONLY, we will advertise that we
1589 		 * support both symmetric and asymmetric Rx PAUSE.  Later
1590 		 * (in e1000_config_fc_after_link_up) we will disable the
1591 		 * hw's ability to send PAUSE frames.
1592 		 */
1593 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1594 		break;
1595 	case e1000_fc_tx_pause:
1596 		/* Tx Flow control is enabled, and Rx Flow control is
1597 		 * disabled, by a software over-ride.
1598 		 */
1599 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1600 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1601 		break;
1602 	case e1000_fc_full:
1603 		/* Flow control (both Rx and Tx) is enabled by a software
1604 		 * over-ride.
1605 		 */
1606 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1607 		break;
1608 	default:
1609 		DEBUGOUT("Flow control param set incorrectly\n");
1610 		return -E1000_ERR_CONFIG;
1611 	}
1612 
1613 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1614 	if (ret_val)
1615 		return ret_val;
1616 
1617 	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1618 
1619 	if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1620 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1621 					     mii_1000t_ctrl_reg);
1622 
1623 	return ret_val;
1624 }
1625 
1626 /**
1627  *  e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1628  *  @hw: pointer to the HW structure
1629  *
1630  *  Performs initial bounds checking on autoneg advertisement parameter, then
1631  *  configure to advertise the full capability.  Setup the PHY to autoneg
1632  *  and restart the negotiation process between the link partner.  If
1633  *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1634  **/
1635 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1636 {
1637 	struct e1000_phy_info *phy = &hw->phy;
1638 	s32 ret_val;
1639 	u16 phy_ctrl;
1640 
1641 	DEBUGFUNC("e1000_copper_link_autoneg");
1642 
1643 	/* Perform some bounds checking on the autoneg advertisement
1644 	 * parameter.
1645 	 */
1646 	phy->autoneg_advertised &= phy->autoneg_mask;
1647 
1648 	/* If autoneg_advertised is zero, we assume it was not defaulted
1649 	 * by the calling code so we set to advertise full capability.
1650 	 */
1651 	if (!phy->autoneg_advertised)
1652 		phy->autoneg_advertised = phy->autoneg_mask;
1653 
1654 	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1655 	ret_val = e1000_phy_setup_autoneg(hw);
1656 	if (ret_val) {
1657 		DEBUGOUT("Error Setting up Auto-Negotiation\n");
1658 		return ret_val;
1659 	}
1660 	DEBUGOUT("Restarting Auto-Neg\n");
1661 
1662 	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
1663 	 * the Auto Neg Restart bit in the PHY control register.
1664 	 */
1665 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1666 	if (ret_val)
1667 		return ret_val;
1668 
1669 	phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1670 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1671 	if (ret_val)
1672 		return ret_val;
1673 
1674 	/* Does the user want to wait for Auto-Neg to complete here, or
1675 	 * check at a later time (for example, callback routine).
1676 	 */
1677 	if (phy->autoneg_wait_to_complete) {
1678 		ret_val = e1000_wait_autoneg(hw);
1679 		if (ret_val) {
1680 			DEBUGOUT("Error while waiting for autoneg to complete\n");
1681 			return ret_val;
1682 		}
1683 	}
1684 
1685 	hw->mac.get_link_status = true;
1686 
1687 	return ret_val;
1688 }
1689 
1690 /**
1691  *  e1000_setup_copper_link_generic - Configure copper link settings
1692  *  @hw: pointer to the HW structure
1693  *
1694  *  Calls the appropriate function to configure the link for auto-neg or forced
1695  *  speed and duplex.  Then we check for link, once link is established calls
1696  *  to configure collision distance and flow control are called.  If link is
1697  *  not established, we return -E1000_ERR_PHY (-2).
1698  **/
1699 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1700 {
1701 	s32 ret_val;
1702 	bool link = true;
1703 
1704 	DEBUGFUNC("e1000_setup_copper_link_generic");
1705 
1706 	if (hw->mac.autoneg) {
1707 		/* Setup autoneg and flow control advertisement and perform
1708 		 * autonegotiation.
1709 		 */
1710 		ret_val = e1000_copper_link_autoneg(hw);
1711 		if (ret_val)
1712 			return ret_val;
1713 	} else {
1714 		/* PHY will be set to 10H, 10F, 100H or 100F
1715 		 * depending on user settings.
1716 		 */
1717 		DEBUGOUT("Forcing Speed and Duplex\n");
1718 		ret_val = hw->phy.ops.force_speed_duplex(hw);
1719 		if (ret_val) {
1720 			DEBUGOUT("Error Forcing Speed and Duplex\n");
1721 			return ret_val;
1722 		}
1723 	}
1724 
1725 	/* Check link status. Wait up to 100 microseconds for link to become
1726 	 * valid.
1727 	 */
1728 	ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1729 					     &link);
1730 	if (ret_val)
1731 		return ret_val;
1732 
1733 	if (link) {
1734 		DEBUGOUT("Valid link established!!!\n");
1735 		hw->mac.ops.config_collision_dist(hw);
1736 		ret_val = e1000_config_fc_after_link_up_generic(hw);
1737 	} else {
1738 		DEBUGOUT("Unable to establish link!!!\n");
1739 	}
1740 
1741 	return ret_val;
1742 }
1743 
1744 /**
1745  *  e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1746  *  @hw: pointer to the HW structure
1747  *
1748  *  Calls the PHY setup function to force speed and duplex.  Clears the
1749  *  auto-crossover to force MDI manually.  Waits for link and returns
1750  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
1751  **/
1752 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1753 {
1754 	struct e1000_phy_info *phy = &hw->phy;
1755 	s32 ret_val;
1756 	u16 phy_data;
1757 	bool link;
1758 
1759 	DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1760 
1761 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1762 	if (ret_val)
1763 		return ret_val;
1764 
1765 	e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1766 
1767 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1768 	if (ret_val)
1769 		return ret_val;
1770 
1771 	/* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
1772 	 * forced whenever speed and duplex are forced.
1773 	 */
1774 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1775 	if (ret_val)
1776 		return ret_val;
1777 
1778 	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1779 	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1780 
1781 	ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1782 	if (ret_val)
1783 		return ret_val;
1784 
1785 	DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1786 
1787 	usec_delay(1);
1788 
1789 	if (phy->autoneg_wait_to_complete) {
1790 		DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1791 
1792 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1793 						     100000, &link);
1794 		if (ret_val)
1795 			return ret_val;
1796 
1797 		if (!link)
1798 			DEBUGOUT("Link taking longer than expected.\n");
1799 
1800 		/* Try once more */
1801 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1802 						     100000, &link);
1803 	}
1804 
1805 	return ret_val;
1806 }
1807 
1808 /**
1809  *  e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1810  *  @hw: pointer to the HW structure
1811  *
1812  *  Calls the PHY setup function to force speed and duplex.  Clears the
1813  *  auto-crossover to force MDI manually.  Resets the PHY to commit the
1814  *  changes.  If time expires while waiting for link up, we reset the DSP.
1815  *  After reset, TX_CLK and CRS on Tx must be set.  Return successful upon
1816  *  successful completion, else return corresponding error code.
1817  **/
1818 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1819 {
1820 	struct e1000_phy_info *phy = &hw->phy;
1821 	s32 ret_val;
1822 	u16 phy_data;
1823 	bool link;
1824 
1825 	DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1826 
1827 	/* I210 and I211 devices support Auto-Crossover in forced operation. */
1828 	if (phy->type != e1000_phy_i210) {
1829 		/* Clear Auto-Crossover to force MDI manually.  M88E1000
1830 		 * requires MDI forced whenever speed and duplex are forced.
1831 		 */
1832 		ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1833 					    &phy_data);
1834 		if (ret_val)
1835 			return ret_val;
1836 
1837 		phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1838 		ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1839 					     phy_data);
1840 		if (ret_val)
1841 			return ret_val;
1842 
1843 		DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1844 	}
1845 
1846 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1847 	if (ret_val)
1848 		return ret_val;
1849 
1850 	e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1851 
1852 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1853 	if (ret_val)
1854 		return ret_val;
1855 
1856 	/* Reset the phy to commit changes. */
1857 	ret_val = hw->phy.ops.commit(hw);
1858 	if (ret_val)
1859 		return ret_val;
1860 
1861 	if (phy->autoneg_wait_to_complete) {
1862 		DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1863 
1864 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1865 						     100000, &link);
1866 		if (ret_val)
1867 			return ret_val;
1868 
1869 		if (!link) {
1870 			bool reset_dsp = true;
1871 
1872 			switch (hw->phy.id) {
1873 			case I347AT4_E_PHY_ID:
1874 			case M88E1340M_E_PHY_ID:
1875 			case M88E1112_E_PHY_ID:
1876 			case M88E1543_E_PHY_ID:
1877 			case M88E1512_E_PHY_ID:
1878 			case I210_I_PHY_ID:
1879 				reset_dsp = false;
1880 				break;
1881 			default:
1882 				if (hw->phy.type != e1000_phy_m88)
1883 					reset_dsp = false;
1884 				break;
1885 			}
1886 
1887 			if (!reset_dsp) {
1888 				DEBUGOUT("Link taking longer than expected.\n");
1889 			} else {
1890 				/* We didn't get link.
1891 				 * Reset the DSP and cross our fingers.
1892 				 */
1893 				ret_val = phy->ops.write_reg(hw,
1894 						M88E1000_PHY_PAGE_SELECT,
1895 						0x001d);
1896 				if (ret_val)
1897 					return ret_val;
1898 				ret_val = e1000_phy_reset_dsp_generic(hw);
1899 				if (ret_val)
1900 					return ret_val;
1901 			}
1902 		}
1903 
1904 		/* Try once more */
1905 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1906 						     100000, &link);
1907 		if (ret_val)
1908 			return ret_val;
1909 	}
1910 
1911 	if (hw->phy.type != e1000_phy_m88)
1912 		return E1000_SUCCESS;
1913 
1914 	if (hw->phy.id == I347AT4_E_PHY_ID ||
1915 		hw->phy.id == M88E1340M_E_PHY_ID ||
1916 		hw->phy.id == M88E1112_E_PHY_ID)
1917 		return E1000_SUCCESS;
1918 	if (hw->phy.id == I210_I_PHY_ID)
1919 		return E1000_SUCCESS;
1920 	if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1921 	    (hw->phy.id == M88E1512_E_PHY_ID))
1922 		return E1000_SUCCESS;
1923 	ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1924 	if (ret_val)
1925 		return ret_val;
1926 
1927 	/* Resetting the phy means we need to re-force TX_CLK in the
1928 	 * Extended PHY Specific Control Register to 25MHz clock from
1929 	 * the reset value of 2.5MHz.
1930 	 */
1931 	phy_data |= M88E1000_EPSCR_TX_CLK_25;
1932 	ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1933 	if (ret_val)
1934 		return ret_val;
1935 
1936 	/* In addition, we must re-enable CRS on Tx for both half and full
1937 	 * duplex.
1938 	 */
1939 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1940 	if (ret_val)
1941 		return ret_val;
1942 
1943 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1944 	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1945 
1946 	return ret_val;
1947 }
1948 
1949 /**
1950  *  e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1951  *  @hw: pointer to the HW structure
1952  *
1953  *  Forces the speed and duplex settings of the PHY.
1954  *  This is a function pointer entry point only called by
1955  *  PHY setup routines.
1956  **/
1957 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1958 {
1959 	struct e1000_phy_info *phy = &hw->phy;
1960 	s32 ret_val;
1961 	u16 data;
1962 	bool link;
1963 
1964 	DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1965 
1966 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1967 	if (ret_val)
1968 		return ret_val;
1969 
1970 	e1000_phy_force_speed_duplex_setup(hw, &data);
1971 
1972 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1973 	if (ret_val)
1974 		return ret_val;
1975 
1976 	/* Disable MDI-X support for 10/100 */
1977 	ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1978 	if (ret_val)
1979 		return ret_val;
1980 
1981 	data &= ~IFE_PMC_AUTO_MDIX;
1982 	data &= ~IFE_PMC_FORCE_MDIX;
1983 
1984 	ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1985 	if (ret_val)
1986 		return ret_val;
1987 
1988 	DEBUGOUT1("IFE PMC: %X\n", data);
1989 
1990 	usec_delay(1);
1991 
1992 	if (phy->autoneg_wait_to_complete) {
1993 		DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1994 
1995 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1996 						     100000, &link);
1997 		if (ret_val)
1998 			return ret_val;
1999 
2000 		if (!link)
2001 			DEBUGOUT("Link taking longer than expected.\n");
2002 
2003 		/* Try once more */
2004 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2005 						     100000, &link);
2006 		if (ret_val)
2007 			return ret_val;
2008 	}
2009 
2010 	return E1000_SUCCESS;
2011 }
2012 
2013 /**
2014  *  e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2015  *  @hw: pointer to the HW structure
2016  *  @phy_ctrl: pointer to current value of PHY_CONTROL
2017  *
2018  *  Forces speed and duplex on the PHY by doing the following: disable flow
2019  *  control, force speed/duplex on the MAC, disable auto speed detection,
2020  *  disable auto-negotiation, configure duplex, configure speed, configure
2021  *  the collision distance, write configuration to CTRL register.  The
2022  *  caller must write to the PHY_CONTROL register for these settings to
2023  *  take affect.
2024  **/
2025 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2026 {
2027 	struct e1000_mac_info *mac = &hw->mac;
2028 	u32 ctrl;
2029 
2030 	DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2031 
2032 	/* Turn off flow control when forcing speed/duplex */
2033 	hw->fc.current_mode = e1000_fc_none;
2034 
2035 	/* Force speed/duplex on the mac */
2036 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
2037 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2038 	ctrl &= ~E1000_CTRL_SPD_SEL;
2039 
2040 	/* Disable Auto Speed Detection */
2041 	ctrl &= ~E1000_CTRL_ASDE;
2042 
2043 	/* Disable autoneg on the phy */
2044 	*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2045 
2046 	/* Forcing Full or Half Duplex? */
2047 	if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2048 		ctrl &= ~E1000_CTRL_FD;
2049 		*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2050 		DEBUGOUT("Half Duplex\n");
2051 	} else {
2052 		ctrl |= E1000_CTRL_FD;
2053 		*phy_ctrl |= MII_CR_FULL_DUPLEX;
2054 		DEBUGOUT("Full Duplex\n");
2055 	}
2056 
2057 	/* Forcing 10mb or 100mb? */
2058 	if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2059 		ctrl |= E1000_CTRL_SPD_100;
2060 		*phy_ctrl |= MII_CR_SPEED_100;
2061 		*phy_ctrl &= ~MII_CR_SPEED_1000;
2062 		DEBUGOUT("Forcing 100mb\n");
2063 	} else {
2064 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2065 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2066 		DEBUGOUT("Forcing 10mb\n");
2067 	}
2068 
2069 	hw->mac.ops.config_collision_dist(hw);
2070 
2071 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2072 }
2073 
2074 /**
2075  *  e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2076  *  @hw: pointer to the HW structure
2077  *  @active: boolean used to enable/disable lplu
2078  *
2079  *  Success returns 0, Failure returns 1
2080  *
2081  *  The low power link up (lplu) state is set to the power management level D3
2082  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
2083  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
2084  *  is used during Dx states where the power conservation is most important.
2085  *  During driver activity, SmartSpeed should be enabled so performance is
2086  *  maintained.
2087  **/
2088 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2089 {
2090 	struct e1000_phy_info *phy = &hw->phy;
2091 	s32 ret_val;
2092 	u16 data;
2093 
2094 	DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2095 
2096 	if (!hw->phy.ops.read_reg)
2097 		return E1000_SUCCESS;
2098 
2099 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2100 	if (ret_val)
2101 		return ret_val;
2102 
2103 	if (!active) {
2104 		data &= ~IGP02E1000_PM_D3_LPLU;
2105 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2106 					     data);
2107 		if (ret_val)
2108 			return ret_val;
2109 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2110 		 * during Dx states where the power conservation is most
2111 		 * important.  During driver activity we should enable
2112 		 * SmartSpeed, so performance is maintained.
2113 		 */
2114 		if (phy->smart_speed == e1000_smart_speed_on) {
2115 			ret_val = phy->ops.read_reg(hw,
2116 						    IGP01E1000_PHY_PORT_CONFIG,
2117 						    &data);
2118 			if (ret_val)
2119 				return ret_val;
2120 
2121 			data |= IGP01E1000_PSCFR_SMART_SPEED;
2122 			ret_val = phy->ops.write_reg(hw,
2123 						     IGP01E1000_PHY_PORT_CONFIG,
2124 						     data);
2125 			if (ret_val)
2126 				return ret_val;
2127 		} else if (phy->smart_speed == e1000_smart_speed_off) {
2128 			ret_val = phy->ops.read_reg(hw,
2129 						    IGP01E1000_PHY_PORT_CONFIG,
2130 						    &data);
2131 			if (ret_val)
2132 				return ret_val;
2133 
2134 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2135 			ret_val = phy->ops.write_reg(hw,
2136 						     IGP01E1000_PHY_PORT_CONFIG,
2137 						     data);
2138 			if (ret_val)
2139 				return ret_val;
2140 		}
2141 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2142 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2143 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2144 		data |= IGP02E1000_PM_D3_LPLU;
2145 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2146 					     data);
2147 		if (ret_val)
2148 			return ret_val;
2149 
2150 		/* When LPLU is enabled, we should disable SmartSpeed */
2151 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2152 					    &data);
2153 		if (ret_val)
2154 			return ret_val;
2155 
2156 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2157 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2158 					     data);
2159 	}
2160 
2161 	return ret_val;
2162 }
2163 
2164 /**
2165  *  e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2166  *  @hw: pointer to the HW structure
2167  *
2168  *  Success returns 0, Failure returns 1
2169  *
2170  *  A downshift is detected by querying the PHY link health.
2171  **/
2172 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2173 {
2174 	struct e1000_phy_info *phy = &hw->phy;
2175 	s32 ret_val;
2176 	u16 phy_data, offset, mask;
2177 
2178 	DEBUGFUNC("e1000_check_downshift_generic");
2179 
2180 	switch (phy->type) {
2181 	case e1000_phy_i210:
2182 	case e1000_phy_m88:
2183 	case e1000_phy_gg82563:
2184 	case e1000_phy_bm:
2185 	case e1000_phy_82578:
2186 		offset = M88E1000_PHY_SPEC_STATUS;
2187 		mask = M88E1000_PSSR_DOWNSHIFT;
2188 		break;
2189 	case e1000_phy_igp:
2190 	case e1000_phy_igp_2:
2191 	case e1000_phy_igp_3:
2192 		offset = IGP01E1000_PHY_LINK_HEALTH;
2193 		mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2194 		break;
2195 	default:
2196 		/* speed downshift not supported */
2197 		phy->speed_downgraded = false;
2198 		return E1000_SUCCESS;
2199 	}
2200 
2201 	ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2202 
2203 	if (!ret_val)
2204 		phy->speed_downgraded = !!(phy_data & mask);
2205 
2206 	return ret_val;
2207 }
2208 
2209 /**
2210  *  e1000_check_polarity_m88 - Checks the polarity.
2211  *  @hw: pointer to the HW structure
2212  *
2213  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2214  *
2215  *  Polarity is determined based on the PHY specific status register.
2216  **/
2217 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2218 {
2219 	struct e1000_phy_info *phy = &hw->phy;
2220 	s32 ret_val;
2221 	u16 data;
2222 
2223 	DEBUGFUNC("e1000_check_polarity_m88");
2224 
2225 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2226 
2227 	if (!ret_val)
2228 		phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2229 				       ? e1000_rev_polarity_reversed
2230 				       : e1000_rev_polarity_normal);
2231 
2232 	return ret_val;
2233 }
2234 
2235 /**
2236  *  e1000_check_polarity_igp - Checks the polarity.
2237  *  @hw: pointer to the HW structure
2238  *
2239  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2240  *
2241  *  Polarity is determined based on the PHY port status register, and the
2242  *  current speed (since there is no polarity at 100Mbps).
2243  **/
2244 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2245 {
2246 	struct e1000_phy_info *phy = &hw->phy;
2247 	s32 ret_val;
2248 	u16 data, offset, mask;
2249 
2250 	DEBUGFUNC("e1000_check_polarity_igp");
2251 
2252 	/* Polarity is determined based on the speed of
2253 	 * our connection.
2254 	 */
2255 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2256 	if (ret_val)
2257 		return ret_val;
2258 
2259 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2260 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
2261 		offset = IGP01E1000_PHY_PCS_INIT_REG;
2262 		mask = IGP01E1000_PHY_POLARITY_MASK;
2263 	} else {
2264 		/* This really only applies to 10Mbps since
2265 		 * there is no polarity for 100Mbps (always 0).
2266 		 */
2267 		offset = IGP01E1000_PHY_PORT_STATUS;
2268 		mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2269 	}
2270 
2271 	ret_val = phy->ops.read_reg(hw, offset, &data);
2272 
2273 	if (!ret_val)
2274 		phy->cable_polarity = ((data & mask)
2275 				       ? e1000_rev_polarity_reversed
2276 				       : e1000_rev_polarity_normal);
2277 
2278 	return ret_val;
2279 }
2280 
2281 /**
2282  *  e1000_check_polarity_ife - Check cable polarity for IFE PHY
2283  *  @hw: pointer to the HW structure
2284  *
2285  *  Polarity is determined on the polarity reversal feature being enabled.
2286  **/
2287 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2288 {
2289 	struct e1000_phy_info *phy = &hw->phy;
2290 	s32 ret_val;
2291 	u16 phy_data, offset, mask;
2292 
2293 	DEBUGFUNC("e1000_check_polarity_ife");
2294 
2295 	/* Polarity is determined based on the reversal feature being enabled.
2296 	 */
2297 	if (phy->polarity_correction) {
2298 		offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2299 		mask = IFE_PESC_POLARITY_REVERSED;
2300 	} else {
2301 		offset = IFE_PHY_SPECIAL_CONTROL;
2302 		mask = IFE_PSC_FORCE_POLARITY;
2303 	}
2304 
2305 	ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2306 
2307 	if (!ret_val)
2308 		phy->cable_polarity = ((phy_data & mask)
2309 				       ? e1000_rev_polarity_reversed
2310 				       : e1000_rev_polarity_normal);
2311 
2312 	return ret_val;
2313 }
2314 
2315 /**
2316  *  e1000_wait_autoneg - Wait for auto-neg completion
2317  *  @hw: pointer to the HW structure
2318  *
2319  *  Waits for auto-negotiation to complete or for the auto-negotiation time
2320  *  limit to expire, which ever happens first.
2321  **/
2322 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2323 {
2324 	s32 ret_val = E1000_SUCCESS;
2325 	u16 i, phy_status;
2326 
2327 	DEBUGFUNC("e1000_wait_autoneg");
2328 
2329 	if (!hw->phy.ops.read_reg)
2330 		return E1000_SUCCESS;
2331 
2332 	/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2333 	for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2334 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2335 		if (ret_val)
2336 			break;
2337 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2338 		if (ret_val)
2339 			break;
2340 		if (phy_status & MII_SR_AUTONEG_COMPLETE)
2341 			break;
2342 		msec_delay(100);
2343 	}
2344 
2345 	/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2346 	 * has completed.
2347 	 */
2348 	return ret_val;
2349 }
2350 
2351 /**
2352  *  e1000_phy_has_link_generic - Polls PHY for link
2353  *  @hw: pointer to the HW structure
2354  *  @iterations: number of times to poll for link
2355  *  @usec_interval: delay between polling attempts
2356  *  @success: pointer to whether polling was successful or not
2357  *
2358  *  Polls the PHY status register for link, 'iterations' number of times.
2359  **/
2360 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2361 			       u32 usec_interval, bool *success)
2362 {
2363 	s32 ret_val = E1000_SUCCESS;
2364 	u16 i, phy_status;
2365 
2366 	DEBUGFUNC("e1000_phy_has_link_generic");
2367 
2368 	if (!hw->phy.ops.read_reg)
2369 		return E1000_SUCCESS;
2370 
2371 	for (i = 0; i < iterations; i++) {
2372 		/* Some PHYs require the PHY_STATUS register to be read
2373 		 * twice due to the link bit being sticky.  No harm doing
2374 		 * it across the board.
2375 		 */
2376 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2377 		if (ret_val) {
2378 			/* If the first read fails, another entity may have
2379 			 * ownership of the resources, wait and try again to
2380 			 * see if they have relinquished the resources yet.
2381 			 */
2382 			if (usec_interval >= 1000)
2383 				msec_delay(usec_interval/1000);
2384 			else
2385 				usec_delay(usec_interval);
2386 		}
2387 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2388 		if (ret_val)
2389 			break;
2390 		if (phy_status & MII_SR_LINK_STATUS)
2391 			break;
2392 		if (usec_interval >= 1000)
2393 			msec_delay(usec_interval/1000);
2394 		else
2395 			usec_delay(usec_interval);
2396 	}
2397 
2398 	*success = (i < iterations);
2399 
2400 	return ret_val;
2401 }
2402 
2403 /**
2404  *  e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2405  *  @hw: pointer to the HW structure
2406  *
2407  *  Reads the PHY specific status register to retrieve the cable length
2408  *  information.  The cable length is determined by averaging the minimum and
2409  *  maximum values to get the "average" cable length.  The m88 PHY has four
2410  *  possible cable length values, which are:
2411  *	Register Value		Cable Length
2412  *	0			< 50 meters
2413  *	1			50 - 80 meters
2414  *	2			80 - 110 meters
2415  *	3			110 - 140 meters
2416  *	4			> 140 meters
2417  **/
2418 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2419 {
2420 	struct e1000_phy_info *phy = &hw->phy;
2421 	s32 ret_val;
2422 	u16 phy_data, index;
2423 
2424 	DEBUGFUNC("e1000_get_cable_length_m88");
2425 
2426 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2427 	if (ret_val)
2428 		return ret_val;
2429 
2430 	index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2431 		 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2432 
2433 	if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2434 		return -E1000_ERR_PHY;
2435 
2436 	phy->min_cable_length = e1000_m88_cable_length_table[index];
2437 	phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2438 
2439 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2440 
2441 	return E1000_SUCCESS;
2442 }
2443 
2444 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2445 {
2446 	struct e1000_phy_info *phy = &hw->phy;
2447 	s32 ret_val;
2448 	u16 phy_data, phy_data2, is_cm;
2449 	u16 index, default_page;
2450 
2451 	DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2452 
2453 	switch (hw->phy.id) {
2454 	case I210_I_PHY_ID:
2455 		/* Get cable length from PHY Cable Diagnostics Control Reg */
2456 		ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2457 					    (I347AT4_PCDL + phy->addr),
2458 					    &phy_data);
2459 		if (ret_val)
2460 			return ret_val;
2461 
2462 		/* Check if the unit of cable length is meters or cm */
2463 		ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2464 					    I347AT4_PCDC, &phy_data2);
2465 		if (ret_val)
2466 			return ret_val;
2467 
2468 		is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2469 
2470 		/* Populate the phy structure with cable length in meters */
2471 		phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2472 		phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2473 		phy->cable_length = phy_data / (is_cm ? 100 : 1);
2474 		break;
2475 	case M88E1543_E_PHY_ID:
2476 	case M88E1512_E_PHY_ID:
2477 	case M88E1340M_E_PHY_ID:
2478 	case I347AT4_E_PHY_ID:
2479 		/* Remember the original page select and set it to 7 */
2480 		ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2481 					    &default_page);
2482 		if (ret_val)
2483 			return ret_val;
2484 
2485 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2486 		if (ret_val)
2487 			return ret_val;
2488 
2489 		/* Get cable length from PHY Cable Diagnostics Control Reg */
2490 		ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2491 					    &phy_data);
2492 		if (ret_val)
2493 			return ret_val;
2494 
2495 		/* Check if the unit of cable length is meters or cm */
2496 		ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2497 		if (ret_val)
2498 			return ret_val;
2499 
2500 		is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2501 
2502 		/* Populate the phy structure with cable length in meters */
2503 		phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2504 		phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2505 		phy->cable_length = phy_data / (is_cm ? 100 : 1);
2506 
2507 		/* Reset the page select to its original value */
2508 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2509 					     default_page);
2510 		if (ret_val)
2511 			return ret_val;
2512 		break;
2513 
2514 	case M88E1112_E_PHY_ID:
2515 		/* Remember the original page select and set it to 5 */
2516 		ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2517 					    &default_page);
2518 		if (ret_val)
2519 			return ret_val;
2520 
2521 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2522 		if (ret_val)
2523 			return ret_val;
2524 
2525 		ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2526 					    &phy_data);
2527 		if (ret_val)
2528 			return ret_val;
2529 
2530 		index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2531 			M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2532 
2533 		if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2534 			return -E1000_ERR_PHY;
2535 
2536 		phy->min_cable_length = e1000_m88_cable_length_table[index];
2537 		phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2538 
2539 		phy->cable_length = (phy->min_cable_length +
2540 				     phy->max_cable_length) / 2;
2541 
2542 		/* Reset the page select to its original value */
2543 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2544 					     default_page);
2545 		if (ret_val)
2546 			return ret_val;
2547 
2548 		break;
2549 	default:
2550 		return -E1000_ERR_PHY;
2551 	}
2552 
2553 	return ret_val;
2554 }
2555 
2556 /**
2557  *  e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2558  *  @hw: pointer to the HW structure
2559  *
2560  *  The automatic gain control (agc) normalizes the amplitude of the
2561  *  received signal, adjusting for the attenuation produced by the
2562  *  cable.  By reading the AGC registers, which represent the
2563  *  combination of coarse and fine gain value, the value can be put
2564  *  into a lookup table to obtain the approximate cable length
2565  *  for each channel.
2566  **/
2567 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2568 {
2569 	struct e1000_phy_info *phy = &hw->phy;
2570 	s32 ret_val;
2571 	u16 phy_data, i, agc_value = 0;
2572 	u16 cur_agc_index, max_agc_index = 0;
2573 	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2574 	static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2575 		IGP02E1000_PHY_AGC_A,
2576 		IGP02E1000_PHY_AGC_B,
2577 		IGP02E1000_PHY_AGC_C,
2578 		IGP02E1000_PHY_AGC_D
2579 	};
2580 
2581 	DEBUGFUNC("e1000_get_cable_length_igp_2");
2582 
2583 	/* Read the AGC registers for all channels */
2584 	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2585 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2586 		if (ret_val)
2587 			return ret_val;
2588 
2589 		/* Getting bits 15:9, which represent the combination of
2590 		 * coarse and fine gain values.  The result is a number
2591 		 * that can be put into the lookup table to obtain the
2592 		 * approximate cable length.
2593 		 */
2594 		cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2595 				 IGP02E1000_AGC_LENGTH_MASK);
2596 
2597 		/* Array index bound check. */
2598 		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2599 		    (cur_agc_index == 0))
2600 			return -E1000_ERR_PHY;
2601 
2602 		/* Remove min & max AGC values from calculation. */
2603 		if (e1000_igp_2_cable_length_table[min_agc_index] >
2604 		    e1000_igp_2_cable_length_table[cur_agc_index])
2605 			min_agc_index = cur_agc_index;
2606 		if (e1000_igp_2_cable_length_table[max_agc_index] <
2607 		    e1000_igp_2_cable_length_table[cur_agc_index])
2608 			max_agc_index = cur_agc_index;
2609 
2610 		agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2611 	}
2612 
2613 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2614 		      e1000_igp_2_cable_length_table[max_agc_index]);
2615 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2616 
2617 	/* Calculate cable length with the error range of +/- 10 meters. */
2618 	phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2619 				 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2620 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2621 
2622 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2623 
2624 	return E1000_SUCCESS;
2625 }
2626 
2627 /**
2628  *  e1000_get_phy_info_m88 - Retrieve PHY information
2629  *  @hw: pointer to the HW structure
2630  *
2631  *  Valid for only copper links.  Read the PHY status register (sticky read)
2632  *  to verify that link is up.  Read the PHY special control register to
2633  *  determine the polarity and 10base-T extended distance.  Read the PHY
2634  *  special status register to determine MDI/MDIx and current speed.  If
2635  *  speed is 1000, then determine cable length, local and remote receiver.
2636  **/
2637 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2638 {
2639 	struct e1000_phy_info *phy = &hw->phy;
2640 	s32  ret_val;
2641 	u16 phy_data;
2642 	bool link;
2643 
2644 	DEBUGFUNC("e1000_get_phy_info_m88");
2645 
2646 	if (phy->media_type != e1000_media_type_copper) {
2647 		DEBUGOUT("Phy info is only valid for copper media\n");
2648 		return -E1000_ERR_CONFIG;
2649 	}
2650 
2651 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2652 	if (ret_val)
2653 		return ret_val;
2654 
2655 	if (!link) {
2656 		DEBUGOUT("Phy info is only valid if link is up\n");
2657 		return -E1000_ERR_CONFIG;
2658 	}
2659 
2660 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2661 	if (ret_val)
2662 		return ret_val;
2663 
2664 	phy->polarity_correction = !!(phy_data &
2665 				      M88E1000_PSCR_POLARITY_REVERSAL);
2666 
2667 	ret_val = e1000_check_polarity_m88(hw);
2668 	if (ret_val)
2669 		return ret_val;
2670 
2671 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2672 	if (ret_val)
2673 		return ret_val;
2674 
2675 	phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2676 
2677 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2678 		ret_val = hw->phy.ops.get_cable_length(hw);
2679 		if (ret_val)
2680 			return ret_val;
2681 
2682 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2683 		if (ret_val)
2684 			return ret_val;
2685 
2686 		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2687 				? e1000_1000t_rx_status_ok
2688 				: e1000_1000t_rx_status_not_ok;
2689 
2690 		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2691 				 ? e1000_1000t_rx_status_ok
2692 				 : e1000_1000t_rx_status_not_ok;
2693 	} else {
2694 		/* Set values to "undefined" */
2695 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2696 		phy->local_rx = e1000_1000t_rx_status_undefined;
2697 		phy->remote_rx = e1000_1000t_rx_status_undefined;
2698 	}
2699 
2700 	return ret_val;
2701 }
2702 
2703 /**
2704  *  e1000_get_phy_info_igp - Retrieve igp PHY information
2705  *  @hw: pointer to the HW structure
2706  *
2707  *  Read PHY status to determine if link is up.  If link is up, then
2708  *  set/determine 10base-T extended distance and polarity correction.  Read
2709  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
2710  *  determine on the cable length, local and remote receiver.
2711  **/
2712 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2713 {
2714 	struct e1000_phy_info *phy = &hw->phy;
2715 	s32 ret_val;
2716 	u16 data;
2717 	bool link;
2718 
2719 	DEBUGFUNC("e1000_get_phy_info_igp");
2720 
2721 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2722 	if (ret_val)
2723 		return ret_val;
2724 
2725 	if (!link) {
2726 		DEBUGOUT("Phy info is only valid if link is up\n");
2727 		return -E1000_ERR_CONFIG;
2728 	}
2729 
2730 	phy->polarity_correction = true;
2731 
2732 	ret_val = e1000_check_polarity_igp(hw);
2733 	if (ret_val)
2734 		return ret_val;
2735 
2736 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2737 	if (ret_val)
2738 		return ret_val;
2739 
2740 	phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2741 
2742 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2743 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
2744 		ret_val = phy->ops.get_cable_length(hw);
2745 		if (ret_val)
2746 			return ret_val;
2747 
2748 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2749 		if (ret_val)
2750 			return ret_val;
2751 
2752 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2753 				? e1000_1000t_rx_status_ok
2754 				: e1000_1000t_rx_status_not_ok;
2755 
2756 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2757 				 ? e1000_1000t_rx_status_ok
2758 				 : e1000_1000t_rx_status_not_ok;
2759 	} else {
2760 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 		phy->local_rx = e1000_1000t_rx_status_undefined;
2762 		phy->remote_rx = e1000_1000t_rx_status_undefined;
2763 	}
2764 
2765 	return ret_val;
2766 }
2767 
2768 /**
2769  *  e1000_get_phy_info_ife - Retrieves various IFE PHY states
2770  *  @hw: pointer to the HW structure
2771  *
2772  *  Populates "phy" structure with various feature states.
2773  **/
2774 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2775 {
2776 	struct e1000_phy_info *phy = &hw->phy;
2777 	s32 ret_val;
2778 	u16 data;
2779 	bool link;
2780 
2781 	DEBUGFUNC("e1000_get_phy_info_ife");
2782 
2783 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2784 	if (ret_val)
2785 		return ret_val;
2786 
2787 	if (!link) {
2788 		DEBUGOUT("Phy info is only valid if link is up\n");
2789 		return -E1000_ERR_CONFIG;
2790 	}
2791 
2792 	ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2793 	if (ret_val)
2794 		return ret_val;
2795 	phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2796 
2797 	if (phy->polarity_correction) {
2798 		ret_val = e1000_check_polarity_ife(hw);
2799 		if (ret_val)
2800 			return ret_val;
2801 	} else {
2802 		/* Polarity is forced */
2803 		phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2804 				       ? e1000_rev_polarity_reversed
2805 				       : e1000_rev_polarity_normal);
2806 	}
2807 
2808 	ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2809 	if (ret_val)
2810 		return ret_val;
2811 
2812 	phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2813 
2814 	/* The following parameters are undefined for 10/100 operation. */
2815 	phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2816 	phy->local_rx = e1000_1000t_rx_status_undefined;
2817 	phy->remote_rx = e1000_1000t_rx_status_undefined;
2818 
2819 	return E1000_SUCCESS;
2820 }
2821 
2822 /**
2823  *  e1000_phy_sw_reset_generic - PHY software reset
2824  *  @hw: pointer to the HW structure
2825  *
2826  *  Does a software reset of the PHY by reading the PHY control register and
2827  *  setting/write the control register reset bit to the PHY.
2828  **/
2829 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2830 {
2831 	s32 ret_val;
2832 	u16 phy_ctrl;
2833 
2834 	DEBUGFUNC("e1000_phy_sw_reset_generic");
2835 
2836 	if (!hw->phy.ops.read_reg)
2837 		return E1000_SUCCESS;
2838 
2839 	ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2840 	if (ret_val)
2841 		return ret_val;
2842 
2843 	phy_ctrl |= MII_CR_RESET;
2844 	ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2845 	if (ret_val)
2846 		return ret_val;
2847 
2848 	usec_delay(1);
2849 
2850 	return ret_val;
2851 }
2852 
2853 /**
2854  *  e1000_phy_hw_reset_generic - PHY hardware reset
2855  *  @hw: pointer to the HW structure
2856  *
2857  *  Verify the reset block is not blocking us from resetting.  Acquire
2858  *  semaphore (if necessary) and read/set/write the device control reset
2859  *  bit in the PHY.  Wait the appropriate delay time for the device to
2860  *  reset and release the semaphore (if necessary).
2861  **/
2862 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2863 {
2864 	struct e1000_phy_info *phy = &hw->phy;
2865 	s32 ret_val;
2866 	u32 ctrl;
2867 
2868 	DEBUGFUNC("e1000_phy_hw_reset_generic");
2869 
2870 	if (phy->ops.check_reset_block) {
2871 		ret_val = phy->ops.check_reset_block(hw);
2872 		if (ret_val)
2873 			return E1000_SUCCESS;
2874 	}
2875 
2876 	ret_val = phy->ops.acquire(hw);
2877 	if (ret_val)
2878 		return ret_val;
2879 
2880 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
2881 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2882 	E1000_WRITE_FLUSH(hw);
2883 
2884 	usec_delay(phy->reset_delay_us);
2885 
2886 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2887 	E1000_WRITE_FLUSH(hw);
2888 
2889 	usec_delay(150);
2890 
2891 	phy->ops.release(hw);
2892 
2893 	return phy->ops.get_cfg_done(hw);
2894 }
2895 
2896 /**
2897  *  e1000_get_cfg_done_generic - Generic configuration done
2898  *  @hw: pointer to the HW structure
2899  *
2900  *  Generic function to wait 10 milli-seconds for configuration to complete
2901  *  and return success.
2902  **/
2903 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2904 {
2905 	DEBUGFUNC("e1000_get_cfg_done_generic");
2906 
2907 	msec_delay_irq(10);
2908 
2909 	return E1000_SUCCESS;
2910 }
2911 
2912 /**
2913  *  e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2914  *  @hw: pointer to the HW structure
2915  *
2916  *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2917  **/
2918 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2919 {
2920 	DEBUGOUT("Running IGP 3 PHY init script\n");
2921 
2922 	/* PHY init IGP 3 */
2923 	/* Enable rise/fall, 10-mode work in class-A */
2924 	hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2925 	/* Remove all caps from Replica path filter */
2926 	hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2927 	/* Bias trimming for ADC, AFE and Driver (Default) */
2928 	hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2929 	/* Increase Hybrid poly bias */
2930 	hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2931 	/* Add 4% to Tx amplitude in Gig mode */
2932 	hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2933 	/* Disable trimming (TTT) */
2934 	hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2935 	/* Poly DC correction to 94.6% + 2% for all channels */
2936 	hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2937 	/* ABS DC correction to 95.9% */
2938 	hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2939 	/* BG temp curve trim */
2940 	hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2941 	/* Increasing ADC OPAMP stage 1 currents to max */
2942 	hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2943 	/* Force 1000 ( required for enabling PHY regs configuration) */
2944 	hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2945 	/* Set upd_freq to 6 */
2946 	hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2947 	/* Disable NPDFE */
2948 	hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2949 	/* Disable adaptive fixed FFE (Default) */
2950 	hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2951 	/* Enable FFE hysteresis */
2952 	hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2953 	/* Fixed FFE for short cable lengths */
2954 	hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2955 	/* Fixed FFE for medium cable lengths */
2956 	hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2957 	/* Fixed FFE for long cable lengths */
2958 	hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2959 	/* Enable Adaptive Clip Threshold */
2960 	hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2961 	/* AHT reset limit to 1 */
2962 	hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2963 	/* Set AHT master delay to 127 msec */
2964 	hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2965 	/* Set scan bits for AHT */
2966 	hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2967 	/* Set AHT Preset bits */
2968 	hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2969 	/* Change integ_factor of channel A to 3 */
2970 	hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2971 	/* Change prop_factor of channels BCD to 8 */
2972 	hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2973 	/* Change cg_icount + enable integbp for channels BCD */
2974 	hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2975 	/* Change cg_icount + enable integbp + change prop_factor_master
2976 	 * to 8 for channel A
2977 	 */
2978 	hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2979 	/* Disable AHT in Slave mode on channel A */
2980 	hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2981 	/* Enable LPLU and disable AN to 1000 in non-D0a states,
2982 	 * Enable SPD+B2B
2983 	 */
2984 	hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2985 	/* Enable restart AN on an1000_dis change */
2986 	hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2987 	/* Enable wh_fifo read clock in 10/100 modes */
2988 	hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2989 	/* Restart AN, Speed selection is 1000 */
2990 	hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2991 
2992 	return E1000_SUCCESS;
2993 }
2994 
2995 /**
2996  *  e1000_get_phy_type_from_id - Get PHY type from id
2997  *  @phy_id: phy_id read from the phy
2998  *
2999  *  Returns the phy type from the id.
3000  **/
3001 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
3002 {
3003 	enum e1000_phy_type phy_type = e1000_phy_unknown;
3004 
3005 	switch (phy_id) {
3006 	case M88E1000_I_PHY_ID:
3007 	case M88E1000_E_PHY_ID:
3008 	case M88E1111_I_PHY_ID:
3009 	case M88E1011_I_PHY_ID:
3010 	case M88E1543_E_PHY_ID:
3011 	case M88E1512_E_PHY_ID:
3012 	case I347AT4_E_PHY_ID:
3013 	case M88E1112_E_PHY_ID:
3014 	case M88E1340M_E_PHY_ID:
3015 		phy_type = e1000_phy_m88;
3016 		break;
3017 	case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3018 		phy_type = e1000_phy_igp_2;
3019 		break;
3020 	case GG82563_E_PHY_ID:
3021 		phy_type = e1000_phy_gg82563;
3022 		break;
3023 	case IGP03E1000_E_PHY_ID:
3024 		phy_type = e1000_phy_igp_3;
3025 		break;
3026 	case IFE_E_PHY_ID:
3027 	case IFE_PLUS_E_PHY_ID:
3028 	case IFE_C_E_PHY_ID:
3029 		phy_type = e1000_phy_ife;
3030 		break;
3031 	case BME1000_E_PHY_ID:
3032 	case BME1000_E_PHY_ID_R2:
3033 		phy_type = e1000_phy_bm;
3034 		break;
3035 	case I82578_E_PHY_ID:
3036 		phy_type = e1000_phy_82578;
3037 		break;
3038 	case I82577_E_PHY_ID:
3039 		phy_type = e1000_phy_82577;
3040 		break;
3041 	case I82579_E_PHY_ID:
3042 		phy_type = e1000_phy_82579;
3043 		break;
3044 	case I217_E_PHY_ID:
3045 		phy_type = e1000_phy_i217;
3046 		break;
3047 	case I82580_I_PHY_ID:
3048 		phy_type = e1000_phy_82580;
3049 		break;
3050 	case I210_I_PHY_ID:
3051 		phy_type = e1000_phy_i210;
3052 		break;
3053 	default:
3054 		phy_type = e1000_phy_unknown;
3055 		break;
3056 	}
3057 	return phy_type;
3058 }
3059 
3060 /**
3061  *  e1000_determine_phy_address - Determines PHY address.
3062  *  @hw: pointer to the HW structure
3063  *
3064  *  This uses a trial and error method to loop through possible PHY
3065  *  addresses. It tests each by reading the PHY ID registers and
3066  *  checking for a match.
3067  **/
3068 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3069 {
3070 	u32 phy_addr = 0;
3071 	u32 i;
3072 	enum e1000_phy_type phy_type = e1000_phy_unknown;
3073 
3074 	hw->phy.id = phy_type;
3075 
3076 	for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3077 		hw->phy.addr = phy_addr;
3078 		i = 0;
3079 
3080 		do {
3081 			e1000_get_phy_id(hw);
3082 			phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3083 
3084 			/* If phy_type is valid, break - we found our
3085 			 * PHY address
3086 			 */
3087 			if (phy_type != e1000_phy_unknown)
3088 				return E1000_SUCCESS;
3089 
3090 			msec_delay(1);
3091 			i++;
3092 		} while (i < 10);
3093 	}
3094 
3095 	return -E1000_ERR_PHY_TYPE;
3096 }
3097 
3098 /**
3099  *  e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3100  *  @page: page to access
3101  *  @reg: register to access
3102  *
3103  *  Returns the phy address for the page requested.
3104  **/
3105 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3106 {
3107 	u32 phy_addr = 2;
3108 
3109 	if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3110 		phy_addr = 1;
3111 
3112 	return phy_addr;
3113 }
3114 
3115 /**
3116  *  e1000_write_phy_reg_bm - Write BM PHY register
3117  *  @hw: pointer to the HW structure
3118  *  @offset: register offset to write to
3119  *  @data: data to write at register offset
3120  *
3121  *  Acquires semaphore, if necessary, then writes the data to PHY register
3122  *  at the offset.  Release any acquired semaphores before exiting.
3123  **/
3124 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3125 {
3126 	s32 ret_val;
3127 	u32 page = offset >> IGP_PAGE_SHIFT;
3128 
3129 	DEBUGFUNC("e1000_write_phy_reg_bm");
3130 
3131 	ret_val = hw->phy.ops.acquire(hw);
3132 	if (ret_val)
3133 		return ret_val;
3134 
3135 	/* Page 800 works differently than the rest so it has its own func */
3136 	if (page == BM_WUC_PAGE) {
3137 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3138 							 false, false);
3139 		goto release;
3140 	}
3141 
3142 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3143 
3144 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
3145 		u32 page_shift, page_select;
3146 
3147 		/* Page select is register 31 for phy address 1 and 22 for
3148 		 * phy address 2 and 3. Page select is shifted only for
3149 		 * phy address 1.
3150 		 */
3151 		if (hw->phy.addr == 1) {
3152 			page_shift = IGP_PAGE_SHIFT;
3153 			page_select = IGP01E1000_PHY_PAGE_SELECT;
3154 		} else {
3155 			page_shift = 0;
3156 			page_select = BM_PHY_PAGE_SELECT;
3157 		}
3158 
3159 		/* Page is shifted left, PHY expects (page x 32) */
3160 		ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3161 						   (page << page_shift));
3162 		if (ret_val)
3163 			goto release;
3164 	}
3165 
3166 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3167 					   data);
3168 
3169 release:
3170 	hw->phy.ops.release(hw);
3171 	return ret_val;
3172 }
3173 
3174 /**
3175  *  e1000_read_phy_reg_bm - Read BM PHY register
3176  *  @hw: pointer to the HW structure
3177  *  @offset: register offset to be read
3178  *  @data: pointer to the read data
3179  *
3180  *  Acquires semaphore, if necessary, then reads the PHY register at offset
3181  *  and storing the retrieved information in data.  Release any acquired
3182  *  semaphores before exiting.
3183  **/
3184 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3185 {
3186 	s32 ret_val;
3187 	u32 page = offset >> IGP_PAGE_SHIFT;
3188 
3189 	DEBUGFUNC("e1000_read_phy_reg_bm");
3190 
3191 	ret_val = hw->phy.ops.acquire(hw);
3192 	if (ret_val)
3193 		return ret_val;
3194 
3195 	/* Page 800 works differently than the rest so it has its own func */
3196 	if (page == BM_WUC_PAGE) {
3197 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3198 							 true, false);
3199 		goto release;
3200 	}
3201 
3202 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3203 
3204 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
3205 		u32 page_shift, page_select;
3206 
3207 		/* Page select is register 31 for phy address 1 and 22 for
3208 		 * phy address 2 and 3. Page select is shifted only for
3209 		 * phy address 1.
3210 		 */
3211 		if (hw->phy.addr == 1) {
3212 			page_shift = IGP_PAGE_SHIFT;
3213 			page_select = IGP01E1000_PHY_PAGE_SELECT;
3214 		} else {
3215 			page_shift = 0;
3216 			page_select = BM_PHY_PAGE_SELECT;
3217 		}
3218 
3219 		/* Page is shifted left, PHY expects (page x 32) */
3220 		ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3221 						   (page << page_shift));
3222 		if (ret_val)
3223 			goto release;
3224 	}
3225 
3226 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3227 					  data);
3228 release:
3229 	hw->phy.ops.release(hw);
3230 	return ret_val;
3231 }
3232 
3233 /**
3234  *  e1000_read_phy_reg_bm2 - Read BM PHY register
3235  *  @hw: pointer to the HW structure
3236  *  @offset: register offset to be read
3237  *  @data: pointer to the read data
3238  *
3239  *  Acquires semaphore, if necessary, then reads the PHY register at offset
3240  *  and storing the retrieved information in data.  Release any acquired
3241  *  semaphores before exiting.
3242  **/
3243 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3244 {
3245 	s32 ret_val;
3246 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3247 
3248 	DEBUGFUNC("e1000_read_phy_reg_bm2");
3249 
3250 	ret_val = hw->phy.ops.acquire(hw);
3251 	if (ret_val)
3252 		return ret_val;
3253 
3254 	/* Page 800 works differently than the rest so it has its own func */
3255 	if (page == BM_WUC_PAGE) {
3256 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3257 							 true, false);
3258 		goto release;
3259 	}
3260 
3261 	hw->phy.addr = 1;
3262 
3263 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
3264 		/* Page is shifted left, PHY expects (page x 32) */
3265 		ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3266 						   page);
3267 
3268 		if (ret_val)
3269 			goto release;
3270 	}
3271 
3272 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3273 					  data);
3274 release:
3275 	hw->phy.ops.release(hw);
3276 	return ret_val;
3277 }
3278 
3279 /**
3280  *  e1000_write_phy_reg_bm2 - Write BM PHY register
3281  *  @hw: pointer to the HW structure
3282  *  @offset: register offset to write to
3283  *  @data: data to write at register offset
3284  *
3285  *  Acquires semaphore, if necessary, then writes the data to PHY register
3286  *  at the offset.  Release any acquired semaphores before exiting.
3287  **/
3288 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3289 {
3290 	s32 ret_val;
3291 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3292 
3293 	DEBUGFUNC("e1000_write_phy_reg_bm2");
3294 
3295 	ret_val = hw->phy.ops.acquire(hw);
3296 	if (ret_val)
3297 		return ret_val;
3298 
3299 	/* Page 800 works differently than the rest so it has its own func */
3300 	if (page == BM_WUC_PAGE) {
3301 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3302 							 false, false);
3303 		goto release;
3304 	}
3305 
3306 	hw->phy.addr = 1;
3307 
3308 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
3309 		/* Page is shifted left, PHY expects (page x 32) */
3310 		ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3311 						   page);
3312 
3313 		if (ret_val)
3314 			goto release;
3315 	}
3316 
3317 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3318 					   data);
3319 
3320 release:
3321 	hw->phy.ops.release(hw);
3322 	return ret_val;
3323 }
3324 
3325 /**
3326  *  e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3327  *  @hw: pointer to the HW structure
3328  *  @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3329  *
3330  *  Assumes semaphore already acquired and phy_reg points to a valid memory
3331  *  address to store contents of the BM_WUC_ENABLE_REG register.
3332  **/
3333 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3334 {
3335 	s32 ret_val;
3336 	u16 temp;
3337 
3338 	DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3339 
3340 	if (!phy_reg)
3341 		return -E1000_ERR_PARAM;
3342 
3343 	/* All page select, port ctrl and wakeup registers use phy address 1 */
3344 	hw->phy.addr = 1;
3345 
3346 	/* Select Port Control Registers page */
3347 	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3348 	if (ret_val) {
3349 		DEBUGOUT("Could not set Port Control page\n");
3350 		return ret_val;
3351 	}
3352 
3353 	ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3354 	if (ret_val) {
3355 		DEBUGOUT2("Could not read PHY register %d.%d\n",
3356 			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3357 		return ret_val;
3358 	}
3359 
3360 	/* Enable both PHY wakeup mode and Wakeup register page writes.
3361 	 * Prevent a power state change by disabling ME and Host PHY wakeup.
3362 	 */
3363 	temp = *phy_reg;
3364 	temp |= BM_WUC_ENABLE_BIT;
3365 	temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3366 
3367 	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3368 	if (ret_val) {
3369 		DEBUGOUT2("Could not write PHY register %d.%d\n",
3370 			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3371 		return ret_val;
3372 	}
3373 
3374 	/* Select Host Wakeup Registers page - caller now able to write
3375 	 * registers on the Wakeup registers page
3376 	 */
3377 	return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3378 }
3379 
3380 /**
3381  *  e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3382  *  @hw: pointer to the HW structure
3383  *  @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3384  *
3385  *  Restore BM_WUC_ENABLE_REG to its original value.
3386  *
3387  *  Assumes semaphore already acquired and *phy_reg is the contents of the
3388  *  BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3389  *  caller.
3390  **/
3391 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3392 {
3393 	s32 ret_val;
3394 
3395 	DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3396 
3397 	if (!phy_reg)
3398 		return -E1000_ERR_PARAM;
3399 
3400 	/* Select Port Control Registers page */
3401 	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3402 	if (ret_val) {
3403 		DEBUGOUT("Could not set Port Control page\n");
3404 		return ret_val;
3405 	}
3406 
3407 	/* Restore 769.17 to its original value */
3408 	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3409 	if (ret_val)
3410 		DEBUGOUT2("Could not restore PHY register %d.%d\n",
3411 			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3412 
3413 	return ret_val;
3414 }
3415 
3416 /**
3417  *  e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3418  *  @hw: pointer to the HW structure
3419  *  @offset: register offset to be read or written
3420  *  @data: pointer to the data to read or write
3421  *  @read: determines if operation is read or write
3422  *  @page_set: BM_WUC_PAGE already set and access enabled
3423  *
3424  *  Read the PHY register at offset and store the retrieved information in
3425  *  data, or write data to PHY register at offset.  Note the procedure to
3426  *  access the PHY wakeup registers is different than reading the other PHY
3427  *  registers. It works as such:
3428  *  1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3429  *  2) Set page to 800 for host (801 if we were manageability)
3430  *  3) Write the address using the address opcode (0x11)
3431  *  4) Read or write the data using the data opcode (0x12)
3432  *  5) Restore 769.17.2 to its original value
3433  *
3434  *  Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3435  *  step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3436  *
3437  *  Assumes semaphore is already acquired.  When page_set==true, assumes
3438  *  the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3439  *  is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3440  **/
3441 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3442 					  u16 *data, bool read, bool page_set)
3443 {
3444 	s32 ret_val;
3445 	u16 reg = BM_PHY_REG_NUM(offset);
3446 	u16 page = BM_PHY_REG_PAGE(offset);
3447 	u16 phy_reg = 0;
3448 
3449 	DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3450 
3451 	/* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3452 	if ((hw->mac.type == e1000_pchlan) &&
3453 	   (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3454 		DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3455 			  page);
3456 
3457 	if (!page_set) {
3458 		/* Enable access to PHY wakeup registers */
3459 		ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3460 		if (ret_val) {
3461 			DEBUGOUT("Could not enable PHY wakeup reg access\n");
3462 			return ret_val;
3463 		}
3464 	}
3465 
3466 	DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3467 
3468 	/* Write the Wakeup register page offset value using opcode 0x11 */
3469 	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3470 	if (ret_val) {
3471 		DEBUGOUT1("Could not write address opcode to page %d\n", page);
3472 		return ret_val;
3473 	}
3474 
3475 	if (read) {
3476 		/* Read the Wakeup register page value using opcode 0x12 */
3477 		ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3478 						  data);
3479 	} else {
3480 		/* Write the Wakeup register page value using opcode 0x12 */
3481 		ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3482 						   *data);
3483 	}
3484 
3485 	if (ret_val) {
3486 		DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3487 		return ret_val;
3488 	}
3489 
3490 	if (!page_set)
3491 		ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3492 
3493 	return ret_val;
3494 }
3495 
3496 /**
3497  * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3498  * @hw: pointer to the HW structure
3499  *
3500  * In the case of a PHY power down to save power, or to turn off link during a
3501  * driver unload, or wake on lan is not enabled, restore the link to previous
3502  * settings.
3503  **/
3504 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3505 {
3506 	u16 mii_reg = 0;
3507 
3508 	/* The PHY will retain its settings across a power down/up cycle */
3509 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3510 	mii_reg &= ~MII_CR_POWER_DOWN;
3511 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3512 }
3513 
3514 /**
3515  * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3516  * @hw: pointer to the HW structure
3517  *
3518  * In the case of a PHY power down to save power, or to turn off link during a
3519  * driver unload, or wake on lan is not enabled, restore the link to previous
3520  * settings.
3521  **/
3522 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3523 {
3524 	u16 mii_reg = 0;
3525 
3526 	/* The PHY will retain its settings across a power down/up cycle */
3527 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3528 	mii_reg |= MII_CR_POWER_DOWN;
3529 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3530 	msec_delay(1);
3531 }
3532 
3533 /**
3534  *  __e1000_read_phy_reg_hv -  Read HV PHY register
3535  *  @hw: pointer to the HW structure
3536  *  @offset: register offset to be read
3537  *  @data: pointer to the read data
3538  *  @locked: semaphore has already been acquired or not
3539  *  @page_set: BM_WUC_PAGE already set and access enabled
3540  *
3541  *  Acquires semaphore, if necessary, then reads the PHY register at offset
3542  *  and stores the retrieved information in data.  Release any acquired
3543  *  semaphore before exiting.
3544  **/
3545 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3546 				   bool locked, bool page_set)
3547 {
3548 	s32 ret_val;
3549 	u16 page = BM_PHY_REG_PAGE(offset);
3550 	u16 reg = BM_PHY_REG_NUM(offset);
3551 	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3552 
3553 	DEBUGFUNC("__e1000_read_phy_reg_hv");
3554 
3555 	if (!locked) {
3556 		ret_val = hw->phy.ops.acquire(hw);
3557 		if (ret_val)
3558 			return ret_val;
3559 	}
3560 	/* Page 800 works differently than the rest so it has its own func */
3561 	if (page == BM_WUC_PAGE) {
3562 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3563 							 true, page_set);
3564 		goto out;
3565 	}
3566 
3567 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3568 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3569 							 data, true);
3570 		goto out;
3571 	}
3572 
3573 	if (!page_set) {
3574 		if (page == HV_INTC_FC_PAGE_START)
3575 			page = 0;
3576 
3577 		if (reg > MAX_PHY_MULTI_PAGE_REG) {
3578 			/* Page is shifted left, PHY expects (page x 32) */
3579 			ret_val = e1000_set_page_igp(hw,
3580 						     (page << IGP_PAGE_SHIFT));
3581 
3582 			hw->phy.addr = phy_addr;
3583 
3584 			if (ret_val)
3585 				goto out;
3586 		}
3587 	}
3588 
3589 	DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3590 		  page << IGP_PAGE_SHIFT, reg);
3591 
3592 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3593 					  data);
3594 out:
3595 	if (!locked)
3596 		hw->phy.ops.release(hw);
3597 
3598 	return ret_val;
3599 }
3600 
3601 /**
3602  *  e1000_read_phy_reg_hv -  Read HV PHY register
3603  *  @hw: pointer to the HW structure
3604  *  @offset: register offset to be read
3605  *  @data: pointer to the read data
3606  *
3607  *  Acquires semaphore then reads the PHY register at offset and stores
3608  *  the retrieved information in data.  Release the acquired semaphore
3609  *  before exiting.
3610  **/
3611 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3612 {
3613 	return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3614 }
3615 
3616 /**
3617  *  e1000_read_phy_reg_hv_locked -  Read HV PHY register
3618  *  @hw: pointer to the HW structure
3619  *  @offset: register offset to be read
3620  *  @data: pointer to the read data
3621  *
3622  *  Reads the PHY register at offset and stores the retrieved information
3623  *  in data.  Assumes semaphore already acquired.
3624  **/
3625 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3626 {
3627 	return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3628 }
3629 
3630 /**
3631  *  e1000_read_phy_reg_page_hv - Read HV PHY register
3632  *  @hw: pointer to the HW structure
3633  *  @offset: register offset to write to
3634  *  @data: data to write at register offset
3635  *
3636  *  Reads the PHY register at offset and stores the retrieved information
3637  *  in data.  Assumes semaphore already acquired and page already set.
3638  **/
3639 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3640 {
3641 	return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3642 }
3643 
3644 /**
3645  *  __e1000_write_phy_reg_hv - Write HV PHY register
3646  *  @hw: pointer to the HW structure
3647  *  @offset: register offset to write to
3648  *  @data: data to write at register offset
3649  *  @locked: semaphore has already been acquired or not
3650  *  @page_set: BM_WUC_PAGE already set and access enabled
3651  *
3652  *  Acquires semaphore, if necessary, then writes the data to PHY register
3653  *  at the offset.  Release any acquired semaphores before exiting.
3654  **/
3655 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3656 				    bool locked, bool page_set)
3657 {
3658 	s32 ret_val;
3659 	u16 page = BM_PHY_REG_PAGE(offset);
3660 	u16 reg = BM_PHY_REG_NUM(offset);
3661 	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3662 
3663 	DEBUGFUNC("__e1000_write_phy_reg_hv");
3664 
3665 	if (!locked) {
3666 		ret_val = hw->phy.ops.acquire(hw);
3667 		if (ret_val)
3668 			return ret_val;
3669 	}
3670 	/* Page 800 works differently than the rest so it has its own func */
3671 	if (page == BM_WUC_PAGE) {
3672 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3673 							 false, page_set);
3674 		goto out;
3675 	}
3676 
3677 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3678 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3679 							 &data, false);
3680 		goto out;
3681 	}
3682 
3683 	if (!page_set) {
3684 		if (page == HV_INTC_FC_PAGE_START)
3685 			page = 0;
3686 
3687 		/* Workaround MDIO accesses being disabled after entering IEEE
3688 		 * Power Down (when bit 11 of the PHY Control register is set)
3689 		 */
3690 		if ((hw->phy.type == e1000_phy_82578) &&
3691 		    (hw->phy.revision >= 1) &&
3692 		    (hw->phy.addr == 2) &&
3693 		    !(MAX_PHY_REG_ADDRESS & reg) &&
3694 		    (data & (1 << 11))) {
3695 			u16 data2 = 0x7EFF;
3696 			ret_val = e1000_access_phy_debug_regs_hv(hw,
3697 								 (1 << 6) | 0x3,
3698 								 &data2, false);
3699 			if (ret_val)
3700 				goto out;
3701 		}
3702 
3703 		if (reg > MAX_PHY_MULTI_PAGE_REG) {
3704 			/* Page is shifted left, PHY expects (page x 32) */
3705 			ret_val = e1000_set_page_igp(hw,
3706 						     (page << IGP_PAGE_SHIFT));
3707 
3708 			hw->phy.addr = phy_addr;
3709 
3710 			if (ret_val)
3711 				goto out;
3712 		}
3713 	}
3714 
3715 	DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3716 		  page << IGP_PAGE_SHIFT, reg);
3717 
3718 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3719 					   data);
3720 
3721 out:
3722 	if (!locked)
3723 		hw->phy.ops.release(hw);
3724 
3725 	return ret_val;
3726 }
3727 
3728 /**
3729  *  e1000_write_phy_reg_hv - Write HV PHY register
3730  *  @hw: pointer to the HW structure
3731  *  @offset: register offset to write to
3732  *  @data: data to write at register offset
3733  *
3734  *  Acquires semaphore then writes the data to PHY register at the offset.
3735  *  Release the acquired semaphores before exiting.
3736  **/
3737 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3738 {
3739 	return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3740 }
3741 
3742 /**
3743  *  e1000_write_phy_reg_hv_locked - Write HV PHY register
3744  *  @hw: pointer to the HW structure
3745  *  @offset: register offset to write to
3746  *  @data: data to write at register offset
3747  *
3748  *  Writes the data to PHY register at the offset.  Assumes semaphore
3749  *  already acquired.
3750  **/
3751 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3752 {
3753 	return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3754 }
3755 
3756 /**
3757  *  e1000_write_phy_reg_page_hv - Write HV PHY register
3758  *  @hw: pointer to the HW structure
3759  *  @offset: register offset to write to
3760  *  @data: data to write at register offset
3761  *
3762  *  Writes the data to PHY register at the offset.  Assumes semaphore
3763  *  already acquired and page already set.
3764  **/
3765 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3766 {
3767 	return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3768 }
3769 
3770 /**
3771  *  e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3772  *  @page: page to be accessed
3773  **/
3774 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3775 {
3776 	u32 phy_addr = 2;
3777 
3778 	if (page >= HV_INTC_FC_PAGE_START)
3779 		phy_addr = 1;
3780 
3781 	return phy_addr;
3782 }
3783 
3784 /**
3785  *  e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3786  *  @hw: pointer to the HW structure
3787  *  @offset: register offset to be read or written
3788  *  @data: pointer to the data to be read or written
3789  *  @read: determines if operation is read or write
3790  *
3791  *  Reads the PHY register at offset and stores the retreived information
3792  *  in data.  Assumes semaphore already acquired.  Note that the procedure
3793  *  to access these regs uses the address port and data port to read/write.
3794  *  These accesses done with PHY address 2 and without using pages.
3795  **/
3796 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3797 					  u16 *data, bool read)
3798 {
3799 	s32 ret_val;
3800 	u32 addr_reg;
3801 	u32 data_reg;
3802 
3803 	DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3804 
3805 	/* This takes care of the difference with desktop vs mobile phy */
3806 	addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3807 		    I82578_ADDR_REG : I82577_ADDR_REG);
3808 	data_reg = addr_reg + 1;
3809 
3810 	/* All operations in this function are phy address 2 */
3811 	hw->phy.addr = 2;
3812 
3813 	/* masking with 0x3F to remove the page from offset */
3814 	ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3815 	if (ret_val) {
3816 		DEBUGOUT("Could not write the Address Offset port register\n");
3817 		return ret_val;
3818 	}
3819 
3820 	/* Read or write the data value next */
3821 	if (read)
3822 		ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3823 	else
3824 		ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3825 
3826 	if (ret_val)
3827 		DEBUGOUT("Could not access the Data port register\n");
3828 
3829 	return ret_val;
3830 }
3831 
3832 /**
3833  *  e1000_link_stall_workaround_hv - Si workaround
3834  *  @hw: pointer to the HW structure
3835  *
3836  *  This function works around a Si bug where the link partner can get
3837  *  a link up indication before the PHY does.  If small packets are sent
3838  *  by the link partner they can be placed in the packet buffer without
3839  *  being properly accounted for by the PHY and will stall preventing
3840  *  further packets from being received.  The workaround is to clear the
3841  *  packet buffer after the PHY detects link up.
3842  **/
3843 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3844 {
3845 	s32 ret_val = E1000_SUCCESS;
3846 	u16 data;
3847 
3848 	DEBUGFUNC("e1000_link_stall_workaround_hv");
3849 
3850 	if (hw->phy.type != e1000_phy_82578)
3851 		return E1000_SUCCESS;
3852 
3853 	/* Do not apply workaround if in PHY loopback bit 14 set */
3854 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3855 	if (data & PHY_CONTROL_LB)
3856 		return E1000_SUCCESS;
3857 
3858 	/* check if link is up and at 1Gbps */
3859 	ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3860 	if (ret_val)
3861 		return ret_val;
3862 
3863 	data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3864 		 BM_CS_STATUS_SPEED_MASK);
3865 
3866 	if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3867 		     BM_CS_STATUS_SPEED_1000))
3868 		return E1000_SUCCESS;
3869 
3870 	msec_delay(200);
3871 
3872 	/* flush the packets in the fifo buffer */
3873 	ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3874 					(HV_MUX_DATA_CTRL_GEN_TO_MAC |
3875 					 HV_MUX_DATA_CTRL_FORCE_SPEED));
3876 	if (ret_val)
3877 		return ret_val;
3878 
3879 	return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3880 				     HV_MUX_DATA_CTRL_GEN_TO_MAC);
3881 }
3882 
3883 /**
3884  *  e1000_check_polarity_82577 - Checks the polarity.
3885  *  @hw: pointer to the HW structure
3886  *
3887  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3888  *
3889  *  Polarity is determined based on the PHY specific status register.
3890  **/
3891 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3892 {
3893 	struct e1000_phy_info *phy = &hw->phy;
3894 	s32 ret_val;
3895 	u16 data;
3896 
3897 	DEBUGFUNC("e1000_check_polarity_82577");
3898 
3899 	ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3900 
3901 	if (!ret_val)
3902 		phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3903 				       ? e1000_rev_polarity_reversed
3904 				       : e1000_rev_polarity_normal);
3905 
3906 	return ret_val;
3907 }
3908 
3909 /**
3910  *  e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3911  *  @hw: pointer to the HW structure
3912  *
3913  *  Calls the PHY setup function to force speed and duplex.
3914  **/
3915 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3916 {
3917 	struct e1000_phy_info *phy = &hw->phy;
3918 	s32 ret_val;
3919 	u16 phy_data;
3920 	bool link;
3921 
3922 	DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3923 
3924 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3925 	if (ret_val)
3926 		return ret_val;
3927 
3928 	e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3929 
3930 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3931 	if (ret_val)
3932 		return ret_val;
3933 
3934 	usec_delay(1);
3935 
3936 	if (phy->autoneg_wait_to_complete) {
3937 		DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3938 
3939 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3940 						     100000, &link);
3941 		if (ret_val)
3942 			return ret_val;
3943 
3944 		if (!link)
3945 			DEBUGOUT("Link taking longer than expected.\n");
3946 
3947 		/* Try once more */
3948 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3949 						     100000, &link);
3950 	}
3951 
3952 	return ret_val;
3953 }
3954 
3955 /**
3956  *  e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3957  *  @hw: pointer to the HW structure
3958  *
3959  *  Read PHY status to determine if link is up.  If link is up, then
3960  *  set/determine 10base-T extended distance and polarity correction.  Read
3961  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
3962  *  determine on the cable length, local and remote receiver.
3963  **/
3964 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3965 {
3966 	struct e1000_phy_info *phy = &hw->phy;
3967 	s32 ret_val;
3968 	u16 data;
3969 	bool link;
3970 
3971 	DEBUGFUNC("e1000_get_phy_info_82577");
3972 
3973 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3974 	if (ret_val)
3975 		return ret_val;
3976 
3977 	if (!link) {
3978 		DEBUGOUT("Phy info is only valid if link is up\n");
3979 		return -E1000_ERR_CONFIG;
3980 	}
3981 
3982 	phy->polarity_correction = true;
3983 
3984 	ret_val = e1000_check_polarity_82577(hw);
3985 	if (ret_val)
3986 		return ret_val;
3987 
3988 	ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3989 	if (ret_val)
3990 		return ret_val;
3991 
3992 	phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3993 
3994 	if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3995 	    I82577_PHY_STATUS2_SPEED_1000MBPS) {
3996 		ret_val = hw->phy.ops.get_cable_length(hw);
3997 		if (ret_val)
3998 			return ret_val;
3999 
4000 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4001 		if (ret_val)
4002 			return ret_val;
4003 
4004 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4005 				? e1000_1000t_rx_status_ok
4006 				: e1000_1000t_rx_status_not_ok;
4007 
4008 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4009 				 ? e1000_1000t_rx_status_ok
4010 				 : e1000_1000t_rx_status_not_ok;
4011 	} else {
4012 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4013 		phy->local_rx = e1000_1000t_rx_status_undefined;
4014 		phy->remote_rx = e1000_1000t_rx_status_undefined;
4015 	}
4016 
4017 	return E1000_SUCCESS;
4018 }
4019 
4020 /**
4021  *  e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4022  *  @hw: pointer to the HW structure
4023  *
4024  * Reads the diagnostic status register and verifies result is valid before
4025  * placing it in the phy_cable_length field.
4026  **/
4027 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4028 {
4029 	struct e1000_phy_info *phy = &hw->phy;
4030 	s32 ret_val;
4031 	u16 phy_data, length;
4032 
4033 	DEBUGFUNC("e1000_get_cable_length_82577");
4034 
4035 	ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4036 	if (ret_val)
4037 		return ret_val;
4038 
4039 	length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4040 		  I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4041 
4042 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
4043 		return -E1000_ERR_PHY;
4044 
4045 	phy->cable_length = length;
4046 
4047 	return E1000_SUCCESS;
4048 }
4049 
4050 /**
4051  *  e1000_write_phy_reg_gs40g - Write GS40G  PHY register
4052  *  @hw: pointer to the HW structure
4053  *  @offset: register offset to write to
4054  *  @data: data to write at register offset
4055  *
4056  *  Acquires semaphore, if necessary, then writes the data to PHY register
4057  *  at the offset.  Release any acquired semaphores before exiting.
4058  **/
4059 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4060 {
4061 	s32 ret_val;
4062 	u16 page = offset >> GS40G_PAGE_SHIFT;
4063 
4064 	DEBUGFUNC("e1000_write_phy_reg_gs40g");
4065 
4066 	offset = offset & GS40G_OFFSET_MASK;
4067 	ret_val = hw->phy.ops.acquire(hw);
4068 	if (ret_val)
4069 		return ret_val;
4070 
4071 	ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4072 	if (ret_val)
4073 		goto release;
4074 	ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4075 
4076 release:
4077 	hw->phy.ops.release(hw);
4078 	return ret_val;
4079 }
4080 
4081 /**
4082  *  e1000_read_phy_reg_gs40g - Read GS40G  PHY register
4083  *  @hw: pointer to the HW structure
4084  *  @offset: lower half is register offset to read to
4085  *     upper half is page to use.
4086  *  @data: data to read at register offset
4087  *
4088  *  Acquires semaphore, if necessary, then reads the data in the PHY register
4089  *  at the offset.  Release any acquired semaphores before exiting.
4090  **/
4091 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4092 {
4093 	s32 ret_val;
4094 	u16 page = offset >> GS40G_PAGE_SHIFT;
4095 
4096 	DEBUGFUNC("e1000_read_phy_reg_gs40g");
4097 
4098 	offset = offset & GS40G_OFFSET_MASK;
4099 	ret_val = hw->phy.ops.acquire(hw);
4100 	if (ret_val)
4101 		return ret_val;
4102 
4103 	ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4104 	if (ret_val)
4105 		goto release;
4106 	ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4107 
4108 release:
4109 	hw->phy.ops.release(hw);
4110 	return ret_val;
4111 }
4112 
4113 /**
4114  *  e1000_read_phy_reg_mphy - Read mPHY control register
4115  *  @hw: pointer to the HW structure
4116  *  @address: address to be read
4117  *  @data: pointer to the read data
4118  *
4119  *  Reads the mPHY control register in the PHY at offset and stores the
4120  *  information read to data.
4121  **/
4122 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4123 {
4124 	u32 mphy_ctrl = 0;
4125 	bool locked = false;
4126 	bool ready;
4127 
4128 	DEBUGFUNC("e1000_read_phy_reg_mphy");
4129 
4130 	/* Check if mPHY is ready to read/write operations */
4131 	ready = e1000_is_mphy_ready(hw);
4132 	if (!ready)
4133 		return -E1000_ERR_PHY;
4134 
4135 	/* Check if mPHY access is disabled and enable it if so */
4136 	mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4137 	if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4138 		locked = true;
4139 		ready = e1000_is_mphy_ready(hw);
4140 		if (!ready)
4141 			return -E1000_ERR_PHY;
4142 		mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4143 		E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4144 	}
4145 
4146 	/* Set the address that we want to read */
4147 	ready = e1000_is_mphy_ready(hw);
4148 	if (!ready)
4149 		return -E1000_ERR_PHY;
4150 
4151 	/* We mask address, because we want to use only current lane */
4152 	mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4153 		~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4154 		(address & E1000_MPHY_ADDRESS_MASK);
4155 	E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4156 
4157 	/* Read data from the address */
4158 	ready = e1000_is_mphy_ready(hw);
4159 	if (!ready)
4160 		return -E1000_ERR_PHY;
4161 	*data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4162 
4163 	/* Disable access to mPHY if it was originally disabled */
4164 	if (locked)
4165 		ready = e1000_is_mphy_ready(hw);
4166 	if (!ready)
4167 		return -E1000_ERR_PHY;
4168 	E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4169 			E1000_MPHY_DIS_ACCESS);
4170 
4171 	return E1000_SUCCESS;
4172 }
4173 
4174 /**
4175  *  e1000_write_phy_reg_mphy - Write mPHY control register
4176  *  @hw: pointer to the HW structure
4177  *  @address: address to write to
4178  *  @data: data to write to register at offset
4179  *  @line_override: used when we want to use different line than default one
4180  *
4181  *  Writes data to mPHY control register.
4182  **/
4183 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4184 			     bool line_override)
4185 {
4186 	u32 mphy_ctrl = 0;
4187 	bool locked = false;
4188 	bool ready;
4189 
4190 	DEBUGFUNC("e1000_write_phy_reg_mphy");
4191 
4192 	/* Check if mPHY is ready to read/write operations */
4193 	ready = e1000_is_mphy_ready(hw);
4194 	if (!ready)
4195 		return -E1000_ERR_PHY;
4196 
4197 	/* Check if mPHY access is disabled and enable it if so */
4198 	mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4199 	if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4200 		locked = true;
4201 		ready = e1000_is_mphy_ready(hw);
4202 		if (!ready)
4203 			return -E1000_ERR_PHY;
4204 		mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4205 		E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4206 	}
4207 
4208 	/* Set the address that we want to read */
4209 	ready = e1000_is_mphy_ready(hw);
4210 	if (!ready)
4211 		return -E1000_ERR_PHY;
4212 
4213 	/* We mask address, because we want to use only current lane */
4214 	if (line_override)
4215 		mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4216 	else
4217 		mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4218 	mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4219 		(address & E1000_MPHY_ADDRESS_MASK);
4220 	E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4221 
4222 	/* Read data from the address */
4223 	ready = e1000_is_mphy_ready(hw);
4224 	if (!ready)
4225 		return -E1000_ERR_PHY;
4226 	E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4227 
4228 	/* Disable access to mPHY if it was originally disabled */
4229 	if (locked)
4230 		ready = e1000_is_mphy_ready(hw);
4231 	if (!ready)
4232 		return -E1000_ERR_PHY;
4233 	E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4234 			E1000_MPHY_DIS_ACCESS);
4235 
4236 	return E1000_SUCCESS;
4237 }
4238 
4239 /**
4240  *  e1000_is_mphy_ready - Check if mPHY control register is not busy
4241  *  @hw: pointer to the HW structure
4242  *
4243  *  Returns mPHY control register status.
4244  **/
4245 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4246 {
4247 	u16 retry_count = 0;
4248 	u32 mphy_ctrl = 0;
4249 	bool ready = false;
4250 
4251 	while (retry_count < 2) {
4252 		mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4253 		if (mphy_ctrl & E1000_MPHY_BUSY) {
4254 			usec_delay(20);
4255 			retry_count++;
4256 			continue;
4257 		}
4258 		ready = true;
4259 		break;
4260 	}
4261 
4262 	if (!ready)
4263 		DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4264 
4265 	return ready;
4266 }
4267 
4268 /**
4269  *  __e1000_access_xmdio_reg - Read/write XMDIO register
4270  *  @hw: pointer to the HW structure
4271  *  @address: XMDIO address to program
4272  *  @dev_addr: device address to program
4273  *  @data: pointer to value to read/write from/to the XMDIO address
4274  *  @read: boolean flag to indicate read or write
4275  **/
4276 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4277 				    u8 dev_addr, u16 *data, bool read)
4278 {
4279 	s32 ret_val;
4280 
4281 	DEBUGFUNC("__e1000_access_xmdio_reg");
4282 
4283 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4284 	if (ret_val)
4285 		return ret_val;
4286 
4287 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4288 	if (ret_val)
4289 		return ret_val;
4290 
4291 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4292 					dev_addr);
4293 	if (ret_val)
4294 		return ret_val;
4295 
4296 	if (read)
4297 		ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4298 	else
4299 		ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4300 	if (ret_val)
4301 		return ret_val;
4302 
4303 	/* Recalibrate the device back to 0 */
4304 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4305 	if (ret_val)
4306 		return ret_val;
4307 
4308 	return ret_val;
4309 }
4310 
4311 /**
4312  *  e1000_read_xmdio_reg - Read XMDIO register
4313  *  @hw: pointer to the HW structure
4314  *  @addr: XMDIO address to program
4315  *  @dev_addr: device address to program
4316  *  @data: value to be read from the EMI address
4317  **/
4318 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4319 {
4320 	DEBUGFUNC("e1000_read_xmdio_reg");
4321 
4322 		return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4323 }
4324 
4325 /**
4326  *  e1000_write_xmdio_reg - Write XMDIO register
4327  *  @hw: pointer to the HW structure
4328  *  @addr: XMDIO address to program
4329  *  @dev_addr: device address to program
4330  *  @data: value to be written to the XMDIO address
4331  **/
4332 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4333 {
4334 	DEBUGFUNC("e1000_write_xmdio_reg");
4335 
4336 		return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,
4337 						false);
4338 }
4339