1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 /* Cable length tables */ 39 static const u16 e1000_m88_cable_length_table[] = 40 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 41 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 42 (sizeof(e1000_m88_cable_length_table) / \ 43 sizeof(e1000_m88_cable_length_table[0])) 44 45 static const u16 e1000_igp_2_cable_length_table[] = 46 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 47 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 48 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 49 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 50 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 51 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 52 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 53 104, 109, 114, 118, 121, 124}; 54 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 55 (sizeof(e1000_igp_2_cable_length_table) / \ 56 sizeof(e1000_igp_2_cable_length_table[0])) 57 58 /** 59 * e1000_init_phy_ops_generic - Initialize PHY function pointers 60 * @hw: pointer to the HW structure 61 * 62 * Setups up the function pointers to no-op functions 63 **/ 64 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 65 { 66 struct e1000_phy_info *phy = &hw->phy; 67 DEBUGFUNC("e1000_init_phy_ops_generic"); 68 69 /* Initialize function pointers */ 70 phy->ops.init_params = e1000_null_ops_generic; 71 phy->ops.acquire = e1000_null_ops_generic; 72 phy->ops.check_polarity = e1000_null_ops_generic; 73 phy->ops.check_reset_block = e1000_null_ops_generic; 74 phy->ops.commit = e1000_null_ops_generic; 75 phy->ops.force_speed_duplex = e1000_null_ops_generic; 76 phy->ops.get_cfg_done = e1000_null_ops_generic; 77 phy->ops.get_cable_length = e1000_null_ops_generic; 78 phy->ops.get_info = e1000_null_ops_generic; 79 phy->ops.read_reg = e1000_null_read_reg; 80 phy->ops.release = e1000_null_phy_generic; 81 phy->ops.reset = e1000_null_ops_generic; 82 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 83 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 84 phy->ops.write_reg = e1000_null_write_reg; 85 phy->ops.power_up = e1000_null_phy_generic; 86 phy->ops.power_down = e1000_null_phy_generic; 87 } 88 89 /** 90 * e1000_null_read_reg - No-op function, return 0 91 * @hw: pointer to the HW structure 92 **/ 93 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 94 { 95 DEBUGFUNC("e1000_null_read_reg"); 96 return E1000_SUCCESS; 97 } 98 99 /** 100 * e1000_null_phy_generic - No-op function, return void 101 * @hw: pointer to the HW structure 102 **/ 103 void e1000_null_phy_generic(struct e1000_hw *hw) 104 { 105 DEBUGFUNC("e1000_null_phy_generic"); 106 return; 107 } 108 109 /** 110 * e1000_null_lplu_state - No-op function, return 0 111 * @hw: pointer to the HW structure 112 **/ 113 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 114 { 115 DEBUGFUNC("e1000_null_lplu_state"); 116 return E1000_SUCCESS; 117 } 118 119 /** 120 * e1000_null_write_reg - No-op function, return 0 121 * @hw: pointer to the HW structure 122 **/ 123 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 124 { 125 DEBUGFUNC("e1000_null_write_reg"); 126 return E1000_SUCCESS; 127 } 128 129 /** 130 * e1000_check_reset_block_generic - Check if PHY reset is blocked 131 * @hw: pointer to the HW structure 132 * 133 * Read the PHY management control register and check whether a PHY reset 134 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 135 * return E1000_BLK_PHY_RESET (12). 136 **/ 137 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 138 { 139 u32 manc; 140 141 DEBUGFUNC("e1000_check_reset_block"); 142 143 manc = E1000_READ_REG(hw, E1000_MANC); 144 145 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 146 E1000_BLK_PHY_RESET : E1000_SUCCESS; 147 } 148 149 /** 150 * e1000_get_phy_id - Retrieve the PHY ID and revision 151 * @hw: pointer to the HW structure 152 * 153 * Reads the PHY registers and stores the PHY ID and possibly the PHY 154 * revision in the hardware structure. 155 **/ 156 s32 e1000_get_phy_id(struct e1000_hw *hw) 157 { 158 struct e1000_phy_info *phy = &hw->phy; 159 s32 ret_val = E1000_SUCCESS; 160 u16 phy_id; 161 162 DEBUGFUNC("e1000_get_phy_id"); 163 164 if (!(phy->ops.read_reg)) 165 goto out; 166 167 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 168 if (ret_val) 169 goto out; 170 171 phy->id = (u32)(phy_id << 16); 172 usec_delay(20); 173 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 174 if (ret_val) 175 goto out; 176 177 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 178 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 179 180 out: 181 return ret_val; 182 } 183 184 /** 185 * e1000_phy_reset_dsp_generic - Reset PHY DSP 186 * @hw: pointer to the HW structure 187 * 188 * Reset the digital signal processor. 189 **/ 190 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 191 { 192 s32 ret_val = E1000_SUCCESS; 193 194 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 195 196 if (!(hw->phy.ops.write_reg)) 197 goto out; 198 199 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 200 if (ret_val) 201 goto out; 202 203 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 204 205 out: 206 return ret_val; 207 } 208 209 /** 210 * e1000_read_phy_reg_mdic - Read MDI control register 211 * @hw: pointer to the HW structure 212 * @offset: register offset to be read 213 * @data: pointer to the read data 214 * 215 * Reads the MDI control register in the PHY at offset and stores the 216 * information read to data. 217 **/ 218 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 219 { 220 struct e1000_phy_info *phy = &hw->phy; 221 u32 i, mdic = 0; 222 s32 ret_val = E1000_SUCCESS; 223 224 DEBUGFUNC("e1000_read_phy_reg_mdic"); 225 226 /* 227 * Set up Op-code, Phy Address, and register offset in the MDI 228 * Control register. The MAC will take care of interfacing with the 229 * PHY to retrieve the desired data. 230 */ 231 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 232 (phy->addr << E1000_MDIC_PHY_SHIFT) | 233 (E1000_MDIC_OP_READ)); 234 235 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 236 237 /* 238 * Poll the ready bit to see if the MDI read completed 239 * Increasing the time out as testing showed failures with 240 * the lower time out 241 */ 242 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 243 usec_delay(50); 244 mdic = E1000_READ_REG(hw, E1000_MDIC); 245 if (mdic & E1000_MDIC_READY) 246 break; 247 } 248 if (!(mdic & E1000_MDIC_READY)) { 249 DEBUGOUT("MDI Read did not complete\n"); 250 ret_val = -E1000_ERR_PHY; 251 goto out; 252 } 253 if (mdic & E1000_MDIC_ERROR) { 254 DEBUGOUT("MDI Error\n"); 255 ret_val = -E1000_ERR_PHY; 256 goto out; 257 } 258 *data = (u16) mdic; 259 260 out: 261 return ret_val; 262 } 263 264 /** 265 * e1000_write_phy_reg_mdic - Write MDI control register 266 * @hw: pointer to the HW structure 267 * @offset: register offset to write to 268 * @data: data to write to register at offset 269 * 270 * Writes data to MDI control register in the PHY at offset. 271 **/ 272 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 273 { 274 struct e1000_phy_info *phy = &hw->phy; 275 u32 i, mdic = 0; 276 s32 ret_val = E1000_SUCCESS; 277 278 DEBUGFUNC("e1000_write_phy_reg_mdic"); 279 280 /* 281 * Set up Op-code, Phy Address, and register offset in the MDI 282 * Control register. The MAC will take care of interfacing with the 283 * PHY to retrieve the desired data. 284 */ 285 mdic = (((u32)data) | 286 (offset << E1000_MDIC_REG_SHIFT) | 287 (phy->addr << E1000_MDIC_PHY_SHIFT) | 288 (E1000_MDIC_OP_WRITE)); 289 290 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 291 292 /* 293 * Poll the ready bit to see if the MDI read completed 294 * Increasing the time out as testing showed failures with 295 * the lower time out 296 */ 297 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 298 usec_delay(50); 299 mdic = E1000_READ_REG(hw, E1000_MDIC); 300 if (mdic & E1000_MDIC_READY) 301 break; 302 } 303 if (!(mdic & E1000_MDIC_READY)) { 304 DEBUGOUT("MDI Write did not complete\n"); 305 ret_val = -E1000_ERR_PHY; 306 goto out; 307 } 308 if (mdic & E1000_MDIC_ERROR) { 309 DEBUGOUT("MDI Error\n"); 310 ret_val = -E1000_ERR_PHY; 311 goto out; 312 } 313 314 out: 315 return ret_val; 316 } 317 318 /** 319 * e1000_read_phy_reg_m88 - Read m88 PHY register 320 * @hw: pointer to the HW structure 321 * @offset: register offset to be read 322 * @data: pointer to the read data 323 * 324 * Acquires semaphore, if necessary, then reads the PHY register at offset 325 * and storing the retrieved information in data. Release any acquired 326 * semaphores before exiting. 327 **/ 328 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 329 { 330 s32 ret_val = E1000_SUCCESS; 331 332 DEBUGFUNC("e1000_read_phy_reg_m88"); 333 334 if (!(hw->phy.ops.acquire)) 335 goto out; 336 337 ret_val = hw->phy.ops.acquire(hw); 338 if (ret_val) 339 goto out; 340 341 ret_val = e1000_read_phy_reg_mdic(hw, 342 MAX_PHY_REG_ADDRESS & offset, 343 data); 344 345 hw->phy.ops.release(hw); 346 347 out: 348 return ret_val; 349 } 350 351 /** 352 * e1000_write_phy_reg_m88 - Write m88 PHY register 353 * @hw: pointer to the HW structure 354 * @offset: register offset to write to 355 * @data: data to write at register offset 356 * 357 * Acquires semaphore, if necessary, then writes the data to PHY register 358 * at the offset. Release any acquired semaphores before exiting. 359 **/ 360 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 361 { 362 s32 ret_val = E1000_SUCCESS; 363 364 DEBUGFUNC("e1000_write_phy_reg_m88"); 365 366 if (!(hw->phy.ops.acquire)) 367 goto out; 368 369 ret_val = hw->phy.ops.acquire(hw); 370 if (ret_val) 371 goto out; 372 373 ret_val = e1000_write_phy_reg_mdic(hw, 374 MAX_PHY_REG_ADDRESS & offset, 375 data); 376 377 hw->phy.ops.release(hw); 378 379 out: 380 return ret_val; 381 } 382 383 /** 384 * e1000_read_phy_reg_igp - Read igp PHY register 385 * @hw: pointer to the HW structure 386 * @offset: register offset to be read 387 * @data: pointer to the read data 388 * 389 * Acquires semaphore, if necessary, then reads the PHY register at offset 390 * and storing the retrieved information in data. Release any acquired 391 * semaphores before exiting. 392 **/ 393 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 394 { 395 s32 ret_val = E1000_SUCCESS; 396 397 DEBUGFUNC("e1000_read_phy_reg_igp"); 398 399 if (!(hw->phy.ops.acquire)) 400 goto out; 401 402 ret_val = hw->phy.ops.acquire(hw); 403 if (ret_val) 404 goto out; 405 406 if (offset > MAX_PHY_MULTI_PAGE_REG) { 407 ret_val = e1000_write_phy_reg_mdic(hw, 408 IGP01E1000_PHY_PAGE_SELECT, 409 (u16)offset); 410 if (ret_val) { 411 hw->phy.ops.release(hw); 412 goto out; 413 } 414 } 415 416 ret_val = e1000_read_phy_reg_mdic(hw, 417 MAX_PHY_REG_ADDRESS & offset, 418 data); 419 420 hw->phy.ops.release(hw); 421 422 out: 423 return ret_val; 424 } 425 426 /** 427 * e1000_write_phy_reg_igp - Write igp PHY register 428 * @hw: pointer to the HW structure 429 * @offset: register offset to write to 430 * @data: data to write at register offset 431 * 432 * Acquires semaphore, if necessary, then writes the data to PHY register 433 * at the offset. Release any acquired semaphores before exiting. 434 **/ 435 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 436 { 437 s32 ret_val = E1000_SUCCESS; 438 439 DEBUGFUNC("e1000_write_phy_reg_igp"); 440 441 if (!(hw->phy.ops.acquire)) 442 goto out; 443 444 ret_val = hw->phy.ops.acquire(hw); 445 if (ret_val) 446 goto out; 447 448 if (offset > MAX_PHY_MULTI_PAGE_REG) { 449 ret_val = e1000_write_phy_reg_mdic(hw, 450 IGP01E1000_PHY_PAGE_SELECT, 451 (u16)offset); 452 if (ret_val) { 453 hw->phy.ops.release(hw); 454 goto out; 455 } 456 } 457 458 ret_val = e1000_write_phy_reg_mdic(hw, 459 MAX_PHY_REG_ADDRESS & offset, 460 data); 461 462 hw->phy.ops.release(hw); 463 464 out: 465 return ret_val; 466 } 467 468 /** 469 * e1000_read_kmrn_reg_generic - Read kumeran register 470 * @hw: pointer to the HW structure 471 * @offset: register offset to be read 472 * @data: pointer to the read data 473 * 474 * Acquires semaphore, if necessary. Then reads the PHY register at offset 475 * using the kumeran interface. The information retrieved is stored in data. 476 * Release any acquired semaphores before exiting. 477 **/ 478 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 479 { 480 u32 kmrnctrlsta; 481 s32 ret_val = E1000_SUCCESS; 482 483 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 484 485 if (!(hw->phy.ops.acquire)) 486 goto out; 487 488 ret_val = hw->phy.ops.acquire(hw); 489 if (ret_val) 490 goto out; 491 492 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 493 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 494 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 495 496 usec_delay(2); 497 498 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 499 *data = (u16)kmrnctrlsta; 500 501 hw->phy.ops.release(hw); 502 503 out: 504 return ret_val; 505 } 506 507 /** 508 * e1000_write_kmrn_reg_generic - Write kumeran register 509 * @hw: pointer to the HW structure 510 * @offset: register offset to write to 511 * @data: data to write at register offset 512 * 513 * Acquires semaphore, if necessary. Then write the data to PHY register 514 * at the offset using the kumeran interface. Release any acquired semaphores 515 * before exiting. 516 **/ 517 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 518 { 519 u32 kmrnctrlsta; 520 s32 ret_val = E1000_SUCCESS; 521 522 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 523 524 if (!(hw->phy.ops.acquire)) 525 goto out; 526 527 ret_val = hw->phy.ops.acquire(hw); 528 if (ret_val) 529 goto out; 530 531 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 532 E1000_KMRNCTRLSTA_OFFSET) | data; 533 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 534 535 usec_delay(2); 536 hw->phy.ops.release(hw); 537 538 out: 539 return ret_val; 540 } 541 542 /** 543 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 544 * @hw: pointer to the HW structure 545 * 546 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 547 * and downshift values are set also. 548 **/ 549 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 550 { 551 struct e1000_phy_info *phy = &hw->phy; 552 s32 ret_val; 553 u16 phy_data; 554 555 DEBUGFUNC("e1000_copper_link_setup_m88"); 556 557 if (phy->reset_disable) { 558 ret_val = E1000_SUCCESS; 559 goto out; 560 } 561 562 /* Enable CRS on TX. This must be set for half-duplex operation. */ 563 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 564 if (ret_val) 565 goto out; 566 567 /* For newer PHYs this bit is downshift enable */ 568 if (phy->type == e1000_phy_m88) 569 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 570 571 /* 572 * Options: 573 * MDI/MDI-X = 0 (default) 574 * 0 - Auto for all speeds 575 * 1 - MDI mode 576 * 2 - MDI-X mode 577 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 578 */ 579 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 580 581 switch (phy->mdix) { 582 case 1: 583 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 584 break; 585 case 2: 586 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 587 break; 588 case 3: 589 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 590 break; 591 case 0: 592 default: 593 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 594 break; 595 } 596 597 /* 598 * Options: 599 * disable_polarity_correction = 0 (default) 600 * Automatic Correction for Reversed Cable Polarity 601 * 0 - Disabled 602 * 1 - Enabled 603 */ 604 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 605 if (phy->disable_polarity_correction == 1) 606 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 607 608 /* Enable downshift on BM (disabled by default) */ 609 if (phy->type == e1000_phy_bm) 610 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 611 612 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 613 if (ret_val) 614 goto out; 615 616 if ((phy->type == e1000_phy_m88) && 617 (phy->revision < E1000_REVISION_4) && 618 (phy->id != BME1000_E_PHY_ID_R2)) { 619 /* 620 * Force TX_CLK in the Extended PHY Specific Control Register 621 * to 25MHz clock. 622 */ 623 ret_val = phy->ops.read_reg(hw, 624 M88E1000_EXT_PHY_SPEC_CTRL, 625 &phy_data); 626 if (ret_val) 627 goto out; 628 629 phy_data |= M88E1000_EPSCR_TX_CLK_25; 630 631 if ((phy->revision == E1000_REVISION_2) && 632 (phy->id == M88E1111_I_PHY_ID)) { 633 /* 82573L PHY - set the downshift counter to 5x. */ 634 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 635 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 636 } else { 637 /* Configure Master and Slave downshift values */ 638 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 639 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 640 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 641 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 642 } 643 ret_val = phy->ops.write_reg(hw, 644 M88E1000_EXT_PHY_SPEC_CTRL, 645 phy_data); 646 if (ret_val) 647 goto out; 648 } 649 650 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 651 /* Set PHY page 0, register 29 to 0x0003 */ 652 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 653 if (ret_val) 654 goto out; 655 656 /* Set PHY page 0, register 30 to 0x0000 */ 657 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 658 if (ret_val) 659 goto out; 660 } 661 662 /* Commit the changes. */ 663 ret_val = phy->ops.commit(hw); 664 if (ret_val) { 665 DEBUGOUT("Error committing the PHY changes\n"); 666 goto out; 667 } 668 669 out: 670 return ret_val; 671 } 672 673 /** 674 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 675 * @hw: pointer to the HW structure 676 * 677 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 678 * igp PHY's. 679 **/ 680 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 681 { 682 struct e1000_phy_info *phy = &hw->phy; 683 s32 ret_val; 684 u16 data; 685 686 DEBUGFUNC("e1000_copper_link_setup_igp"); 687 688 if (phy->reset_disable) { 689 ret_val = E1000_SUCCESS; 690 goto out; 691 } 692 693 ret_val = hw->phy.ops.reset(hw); 694 if (ret_val) { 695 DEBUGOUT("Error resetting the PHY.\n"); 696 goto out; 697 } 698 699 /* 700 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 701 * timeout issues when LFS is enabled. 702 */ 703 msec_delay(100); 704 705 /* 706 * The NVM settings will configure LPLU in D3 for 707 * non-IGP1 PHYs. 708 */ 709 if (phy->type == e1000_phy_igp) { 710 /* disable lplu d3 during driver init */ 711 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 712 if (ret_val) { 713 DEBUGOUT("Error Disabling LPLU D3\n"); 714 goto out; 715 } 716 } 717 718 /* disable lplu d0 during driver init */ 719 if (hw->phy.ops.set_d0_lplu_state) { 720 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 721 if (ret_val) { 722 DEBUGOUT("Error Disabling LPLU D0\n"); 723 goto out; 724 } 725 } 726 /* Configure mdi-mdix settings */ 727 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 728 if (ret_val) 729 goto out; 730 731 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 732 733 switch (phy->mdix) { 734 case 1: 735 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 736 break; 737 case 2: 738 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 739 break; 740 case 0: 741 default: 742 data |= IGP01E1000_PSCR_AUTO_MDIX; 743 break; 744 } 745 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 746 if (ret_val) 747 goto out; 748 749 /* set auto-master slave resolution settings */ 750 if (hw->mac.autoneg) { 751 /* 752 * when autonegotiation advertisement is only 1000Mbps then we 753 * should disable SmartSpeed and enable Auto MasterSlave 754 * resolution as hardware default. 755 */ 756 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 757 /* Disable SmartSpeed */ 758 ret_val = phy->ops.read_reg(hw, 759 IGP01E1000_PHY_PORT_CONFIG, 760 &data); 761 if (ret_val) 762 goto out; 763 764 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 765 ret_val = phy->ops.write_reg(hw, 766 IGP01E1000_PHY_PORT_CONFIG, 767 data); 768 if (ret_val) 769 goto out; 770 771 /* Set auto Master/Slave resolution process */ 772 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 773 if (ret_val) 774 goto out; 775 776 data &= ~CR_1000T_MS_ENABLE; 777 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 778 if (ret_val) 779 goto out; 780 } 781 782 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 783 if (ret_val) 784 goto out; 785 786 /* load defaults for future use */ 787 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 788 ((data & CR_1000T_MS_VALUE) ? 789 e1000_ms_force_master : 790 e1000_ms_force_slave) : 791 e1000_ms_auto; 792 793 switch (phy->ms_type) { 794 case e1000_ms_force_master: 795 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 796 break; 797 case e1000_ms_force_slave: 798 data |= CR_1000T_MS_ENABLE; 799 data &= ~(CR_1000T_MS_VALUE); 800 break; 801 case e1000_ms_auto: 802 data &= ~CR_1000T_MS_ENABLE; 803 default: 804 break; 805 } 806 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 807 if (ret_val) 808 goto out; 809 } 810 811 out: 812 return ret_val; 813 } 814 815 /** 816 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 817 * @hw: pointer to the HW structure 818 * 819 * Performs initial bounds checking on autoneg advertisement parameter, then 820 * configure to advertise the full capability. Setup the PHY to autoneg 821 * and restart the negotiation process between the link partner. If 822 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 823 **/ 824 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 825 { 826 struct e1000_phy_info *phy = &hw->phy; 827 s32 ret_val; 828 u16 phy_ctrl; 829 830 DEBUGFUNC("e1000_copper_link_autoneg"); 831 832 /* 833 * Perform some bounds checking on the autoneg advertisement 834 * parameter. 835 */ 836 phy->autoneg_advertised &= phy->autoneg_mask; 837 838 /* 839 * If autoneg_advertised is zero, we assume it was not defaulted 840 * by the calling code so we set to advertise full capability. 841 */ 842 if (phy->autoneg_advertised == 0) 843 phy->autoneg_advertised = phy->autoneg_mask; 844 845 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 846 ret_val = e1000_phy_setup_autoneg(hw); 847 if (ret_val) { 848 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 849 goto out; 850 } 851 DEBUGOUT("Restarting Auto-Neg\n"); 852 853 /* 854 * Restart auto-negotiation by setting the Auto Neg Enable bit and 855 * the Auto Neg Restart bit in the PHY control register. 856 */ 857 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 858 if (ret_val) 859 goto out; 860 861 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 862 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 863 if (ret_val) 864 goto out; 865 866 /* 867 * Does the user want to wait for Auto-Neg to complete here, or 868 * check at a later time (for example, callback routine). 869 */ 870 if (phy->autoneg_wait_to_complete) { 871 ret_val = hw->mac.ops.wait_autoneg(hw); 872 if (ret_val) { 873 DEBUGOUT("Error while waiting for " 874 "autoneg to complete\n"); 875 goto out; 876 } 877 } 878 879 hw->mac.get_link_status = TRUE; 880 881 out: 882 return ret_val; 883 } 884 885 /** 886 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 887 * @hw: pointer to the HW structure 888 * 889 * Reads the MII auto-neg advertisement register and/or the 1000T control 890 * register and if the PHY is already setup for auto-negotiation, then 891 * return successful. Otherwise, setup advertisement and flow control to 892 * the appropriate values for the wanted auto-negotiation. 893 **/ 894 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 895 { 896 struct e1000_phy_info *phy = &hw->phy; 897 s32 ret_val; 898 u16 mii_autoneg_adv_reg; 899 u16 mii_1000t_ctrl_reg = 0; 900 901 DEBUGFUNC("e1000_phy_setup_autoneg"); 902 903 phy->autoneg_advertised &= phy->autoneg_mask; 904 905 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 906 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 907 if (ret_val) 908 goto out; 909 910 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 911 /* Read the MII 1000Base-T Control Register (Address 9). */ 912 ret_val = phy->ops.read_reg(hw, 913 PHY_1000T_CTRL, 914 &mii_1000t_ctrl_reg); 915 if (ret_val) 916 goto out; 917 } 918 919 /* 920 * Need to parse both autoneg_advertised and fc and set up 921 * the appropriate PHY registers. First we will parse for 922 * autoneg_advertised software override. Since we can advertise 923 * a plethora of combinations, we need to check each bit 924 * individually. 925 */ 926 927 /* 928 * First we clear all the 10/100 mb speed bits in the Auto-Neg 929 * Advertisement Register (Address 4) and the 1000 mb speed bits in 930 * the 1000Base-T Control Register (Address 9). 931 */ 932 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 933 NWAY_AR_100TX_HD_CAPS | 934 NWAY_AR_10T_FD_CAPS | 935 NWAY_AR_10T_HD_CAPS); 936 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 937 938 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 939 940 /* Do we want to advertise 10 Mb Half Duplex? */ 941 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 942 DEBUGOUT("Advertise 10mb Half duplex\n"); 943 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 944 } 945 946 /* Do we want to advertise 10 Mb Full Duplex? */ 947 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 948 DEBUGOUT("Advertise 10mb Full duplex\n"); 949 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 950 } 951 952 /* Do we want to advertise 100 Mb Half Duplex? */ 953 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 954 DEBUGOUT("Advertise 100mb Half duplex\n"); 955 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 956 } 957 958 /* Do we want to advertise 100 Mb Full Duplex? */ 959 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 960 DEBUGOUT("Advertise 100mb Full duplex\n"); 961 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 962 } 963 964 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 965 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) { 966 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 967 } 968 969 /* Do we want to advertise 1000 Mb Full Duplex? */ 970 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 971 DEBUGOUT("Advertise 1000mb Full duplex\n"); 972 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 973 } 974 975 /* 976 * Check for a software override of the flow control settings, and 977 * setup the PHY advertisement registers accordingly. If 978 * auto-negotiation is enabled, then software will have to set the 979 * "PAUSE" bits to the correct value in the Auto-Negotiation 980 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 981 * negotiation. 982 * 983 * The possible values of the "fc" parameter are: 984 * 0: Flow control is completely disabled 985 * 1: Rx flow control is enabled (we can receive pause frames 986 * but not send pause frames). 987 * 2: Tx flow control is enabled (we can send pause frames 988 * but we do not support receiving pause frames). 989 * 3: Both Rx and Tx flow control (symmetric) are enabled. 990 * other: No software override. The flow control configuration 991 * in the EEPROM is used. 992 */ 993 switch (hw->fc.type) { 994 case e1000_fc_none: 995 /* 996 * Flow control (Rx & Tx) is completely disabled by a 997 * software over-ride. 998 */ 999 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1000 break; 1001 case e1000_fc_rx_pause: 1002 /* 1003 * Rx Flow control is enabled, and Tx Flow control is 1004 * disabled, by a software over-ride. 1005 * 1006 * Since there really isn't a way to advertise that we are 1007 * capable of Rx Pause ONLY, we will advertise that we 1008 * support both symmetric and asymmetric Rx PAUSE. Later 1009 * (in e1000_config_fc_after_link_up) we will disable the 1010 * hw's ability to send PAUSE frames. 1011 */ 1012 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1013 break; 1014 case e1000_fc_tx_pause: 1015 /* 1016 * Tx Flow control is enabled, and Rx Flow control is 1017 * disabled, by a software over-ride. 1018 */ 1019 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1020 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1021 break; 1022 case e1000_fc_full: 1023 /* 1024 * Flow control (both Rx and Tx) is enabled by a software 1025 * over-ride. 1026 */ 1027 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1028 break; 1029 default: 1030 DEBUGOUT("Flow control param set incorrectly\n"); 1031 ret_val = -E1000_ERR_CONFIG; 1032 goto out; 1033 } 1034 1035 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1036 if (ret_val) 1037 goto out; 1038 1039 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1040 1041 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1042 ret_val = phy->ops.write_reg(hw, 1043 PHY_1000T_CTRL, 1044 mii_1000t_ctrl_reg); 1045 if (ret_val) 1046 goto out; 1047 } 1048 1049 out: 1050 return ret_val; 1051 } 1052 1053 /** 1054 * e1000_setup_copper_link_generic - Configure copper link settings 1055 * @hw: pointer to the HW structure 1056 * 1057 * Calls the appropriate function to configure the link for auto-neg or forced 1058 * speed and duplex. Then we check for link, once link is established calls 1059 * to configure collision distance and flow control are called. If link is 1060 * not established, we return -E1000_ERR_PHY (-2). 1061 **/ 1062 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1063 { 1064 s32 ret_val; 1065 bool link; 1066 1067 DEBUGFUNC("e1000_setup_copper_link_generic"); 1068 1069 if (hw->mac.autoneg) { 1070 /* 1071 * Setup autoneg and flow control advertisement and perform 1072 * autonegotiation. 1073 */ 1074 ret_val = e1000_copper_link_autoneg(hw); 1075 if (ret_val) 1076 goto out; 1077 } else { 1078 /* 1079 * PHY will be set to 10H, 10F, 100H or 100F 1080 * depending on user settings. 1081 */ 1082 DEBUGOUT("Forcing Speed and Duplex\n"); 1083 ret_val = hw->phy.ops.force_speed_duplex(hw); 1084 if (ret_val) { 1085 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1086 goto out; 1087 } 1088 } 1089 1090 /* 1091 * Check link status. Wait up to 100 microseconds for link to become 1092 * valid. 1093 */ 1094 ret_val = e1000_phy_has_link_generic(hw, 1095 COPPER_LINK_UP_LIMIT, 1096 10, 1097 &link); 1098 if (ret_val) 1099 goto out; 1100 1101 if (link) { 1102 DEBUGOUT("Valid link established!!!\n"); 1103 e1000_config_collision_dist_generic(hw); 1104 ret_val = e1000_config_fc_after_link_up_generic(hw); 1105 } else { 1106 DEBUGOUT("Unable to establish link!!!\n"); 1107 } 1108 1109 out: 1110 return ret_val; 1111 } 1112 1113 /** 1114 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1115 * @hw: pointer to the HW structure 1116 * 1117 * Calls the PHY setup function to force speed and duplex. Clears the 1118 * auto-crossover to force MDI manually. Waits for link and returns 1119 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1120 **/ 1121 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1122 { 1123 struct e1000_phy_info *phy = &hw->phy; 1124 s32 ret_val; 1125 u16 phy_data; 1126 bool link; 1127 1128 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1129 1130 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1131 if (ret_val) 1132 goto out; 1133 1134 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1135 1136 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1137 if (ret_val) 1138 goto out; 1139 1140 /* 1141 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1142 * forced whenever speed and duplex are forced. 1143 */ 1144 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1145 if (ret_val) 1146 goto out; 1147 1148 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1149 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1150 1151 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1152 if (ret_val) 1153 goto out; 1154 1155 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1156 1157 usec_delay(1); 1158 1159 if (phy->autoneg_wait_to_complete) { 1160 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1161 1162 ret_val = e1000_phy_has_link_generic(hw, 1163 PHY_FORCE_LIMIT, 1164 100000, 1165 &link); 1166 if (ret_val) 1167 goto out; 1168 1169 if (!link) { 1170 DEBUGOUT("Link taking longer than expected.\n"); 1171 } 1172 1173 /* Try once more */ 1174 ret_val = e1000_phy_has_link_generic(hw, 1175 PHY_FORCE_LIMIT, 1176 100000, 1177 &link); 1178 if (ret_val) 1179 goto out; 1180 } 1181 1182 out: 1183 return ret_val; 1184 } 1185 1186 /** 1187 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1188 * @hw: pointer to the HW structure 1189 * 1190 * Calls the PHY setup function to force speed and duplex. Clears the 1191 * auto-crossover to force MDI manually. Resets the PHY to commit the 1192 * changes. If time expires while waiting for link up, we reset the DSP. 1193 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1194 * successful completion, else return corresponding error code. 1195 **/ 1196 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1197 { 1198 struct e1000_phy_info *phy = &hw->phy; 1199 s32 ret_val; 1200 u16 phy_data; 1201 bool link; 1202 1203 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1204 1205 /* 1206 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1207 * forced whenever speed and duplex are forced. 1208 */ 1209 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1210 if (ret_val) 1211 goto out; 1212 1213 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1214 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1215 if (ret_val) 1216 goto out; 1217 1218 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1219 1220 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1221 if (ret_val) 1222 goto out; 1223 1224 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1225 1226 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1227 if (ret_val) 1228 goto out; 1229 1230 /* Reset the phy to commit changes. */ 1231 ret_val = hw->phy.ops.commit(hw); 1232 if (ret_val) 1233 goto out; 1234 1235 if (phy->autoneg_wait_to_complete) { 1236 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1237 1238 ret_val = e1000_phy_has_link_generic(hw, 1239 PHY_FORCE_LIMIT, 1240 100000, 1241 &link); 1242 if (ret_val) 1243 goto out; 1244 1245 if (!link) { 1246 /* 1247 * We didn't get link. 1248 * Reset the DSP and cross our fingers. 1249 */ 1250 ret_val = phy->ops.write_reg(hw, 1251 M88E1000_PHY_PAGE_SELECT, 1252 0x001d); 1253 if (ret_val) 1254 goto out; 1255 ret_val = e1000_phy_reset_dsp_generic(hw); 1256 if (ret_val) 1257 goto out; 1258 } 1259 1260 /* Try once more */ 1261 ret_val = e1000_phy_has_link_generic(hw, 1262 PHY_FORCE_LIMIT, 1263 100000, 1264 &link); 1265 if (ret_val) 1266 goto out; 1267 } 1268 1269 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1270 if (ret_val) 1271 goto out; 1272 1273 /* 1274 * Resetting the phy means we need to re-force TX_CLK in the 1275 * Extended PHY Specific Control Register to 25MHz clock from 1276 * the reset value of 2.5MHz. 1277 */ 1278 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1279 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1280 if (ret_val) 1281 goto out; 1282 1283 /* 1284 * In addition, we must re-enable CRS on Tx for both half and full 1285 * duplex. 1286 */ 1287 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1288 if (ret_val) 1289 goto out; 1290 1291 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1292 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1293 1294 out: 1295 return ret_val; 1296 } 1297 1298 /** 1299 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1300 * @hw: pointer to the HW structure 1301 * @phy_ctrl: pointer to current value of PHY_CONTROL 1302 * 1303 * Forces speed and duplex on the PHY by doing the following: disable flow 1304 * control, force speed/duplex on the MAC, disable auto speed detection, 1305 * disable auto-negotiation, configure duplex, configure speed, configure 1306 * the collision distance, write configuration to CTRL register. The 1307 * caller must write to the PHY_CONTROL register for these settings to 1308 * take affect. 1309 **/ 1310 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1311 { 1312 struct e1000_mac_info *mac = &hw->mac; 1313 u32 ctrl; 1314 1315 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1316 1317 /* Turn off flow control when forcing speed/duplex */ 1318 hw->fc.type = e1000_fc_none; 1319 1320 /* Force speed/duplex on the mac */ 1321 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1322 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1323 ctrl &= ~E1000_CTRL_SPD_SEL; 1324 1325 /* Disable Auto Speed Detection */ 1326 ctrl &= ~E1000_CTRL_ASDE; 1327 1328 /* Disable autoneg on the phy */ 1329 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1330 1331 /* Forcing Full or Half Duplex? */ 1332 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1333 ctrl &= ~E1000_CTRL_FD; 1334 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1335 DEBUGOUT("Half Duplex\n"); 1336 } else { 1337 ctrl |= E1000_CTRL_FD; 1338 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1339 DEBUGOUT("Full Duplex\n"); 1340 } 1341 1342 /* Forcing 10mb or 100mb? */ 1343 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1344 ctrl |= E1000_CTRL_SPD_100; 1345 *phy_ctrl |= MII_CR_SPEED_100; 1346 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1347 DEBUGOUT("Forcing 100mb\n"); 1348 } else { 1349 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1350 *phy_ctrl |= MII_CR_SPEED_10; 1351 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1352 DEBUGOUT("Forcing 10mb\n"); 1353 } 1354 1355 e1000_config_collision_dist_generic(hw); 1356 1357 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1358 } 1359 1360 /** 1361 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1362 * @hw: pointer to the HW structure 1363 * @active: boolean used to enable/disable lplu 1364 * 1365 * Success returns 0, Failure returns 1 1366 * 1367 * The low power link up (lplu) state is set to the power management level D3 1368 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1369 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1370 * is used during Dx states where the power conservation is most important. 1371 * During driver activity, SmartSpeed should be enabled so performance is 1372 * maintained. 1373 **/ 1374 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1375 { 1376 struct e1000_phy_info *phy = &hw->phy; 1377 s32 ret_val = E1000_SUCCESS; 1378 u16 data; 1379 1380 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1381 1382 if (!(hw->phy.ops.read_reg)) 1383 goto out; 1384 1385 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1386 if (ret_val) 1387 goto out; 1388 1389 if (!active) { 1390 data &= ~IGP02E1000_PM_D3_LPLU; 1391 ret_val = phy->ops.write_reg(hw, 1392 IGP02E1000_PHY_POWER_MGMT, 1393 data); 1394 if (ret_val) 1395 goto out; 1396 /* 1397 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1398 * during Dx states where the power conservation is most 1399 * important. During driver activity we should enable 1400 * SmartSpeed, so performance is maintained. 1401 */ 1402 if (phy->smart_speed == e1000_smart_speed_on) { 1403 ret_val = phy->ops.read_reg(hw, 1404 IGP01E1000_PHY_PORT_CONFIG, 1405 &data); 1406 if (ret_val) 1407 goto out; 1408 1409 data |= IGP01E1000_PSCFR_SMART_SPEED; 1410 ret_val = phy->ops.write_reg(hw, 1411 IGP01E1000_PHY_PORT_CONFIG, 1412 data); 1413 if (ret_val) 1414 goto out; 1415 } else if (phy->smart_speed == e1000_smart_speed_off) { 1416 ret_val = phy->ops.read_reg(hw, 1417 IGP01E1000_PHY_PORT_CONFIG, 1418 &data); 1419 if (ret_val) 1420 goto out; 1421 1422 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1423 ret_val = phy->ops.write_reg(hw, 1424 IGP01E1000_PHY_PORT_CONFIG, 1425 data); 1426 if (ret_val) 1427 goto out; 1428 } 1429 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1430 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1431 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1432 data |= IGP02E1000_PM_D3_LPLU; 1433 ret_val = phy->ops.write_reg(hw, 1434 IGP02E1000_PHY_POWER_MGMT, 1435 data); 1436 if (ret_val) 1437 goto out; 1438 1439 /* When LPLU is enabled, we should disable SmartSpeed */ 1440 ret_val = phy->ops.read_reg(hw, 1441 IGP01E1000_PHY_PORT_CONFIG, 1442 &data); 1443 if (ret_val) 1444 goto out; 1445 1446 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1447 ret_val = phy->ops.write_reg(hw, 1448 IGP01E1000_PHY_PORT_CONFIG, 1449 data); 1450 } 1451 1452 out: 1453 return ret_val; 1454 } 1455 1456 /** 1457 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1458 * @hw: pointer to the HW structure 1459 * 1460 * Success returns 0, Failure returns 1 1461 * 1462 * A downshift is detected by querying the PHY link health. 1463 **/ 1464 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1465 { 1466 struct e1000_phy_info *phy = &hw->phy; 1467 s32 ret_val; 1468 u16 phy_data, offset, mask; 1469 1470 DEBUGFUNC("e1000_check_downshift_generic"); 1471 1472 switch (phy->type) { 1473 case e1000_phy_m88: 1474 case e1000_phy_gg82563: 1475 case e1000_phy_bm: 1476 offset = M88E1000_PHY_SPEC_STATUS; 1477 mask = M88E1000_PSSR_DOWNSHIFT; 1478 break; 1479 case e1000_phy_igp_2: 1480 case e1000_phy_igp: 1481 case e1000_phy_igp_3: 1482 offset = IGP01E1000_PHY_LINK_HEALTH; 1483 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1484 break; 1485 default: 1486 /* speed downshift not supported */ 1487 phy->speed_downgraded = FALSE; 1488 ret_val = E1000_SUCCESS; 1489 goto out; 1490 } 1491 1492 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1493 1494 if (!ret_val) 1495 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1496 1497 out: 1498 return ret_val; 1499 } 1500 1501 /** 1502 * e1000_check_polarity_m88 - Checks the polarity. 1503 * @hw: pointer to the HW structure 1504 * 1505 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1506 * 1507 * Polarity is determined based on the PHY specific status register. 1508 **/ 1509 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1510 { 1511 struct e1000_phy_info *phy = &hw->phy; 1512 s32 ret_val; 1513 u16 data; 1514 1515 DEBUGFUNC("e1000_check_polarity_m88"); 1516 1517 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1518 1519 if (!ret_val) 1520 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1521 ? e1000_rev_polarity_reversed 1522 : e1000_rev_polarity_normal; 1523 1524 return ret_val; 1525 } 1526 1527 /** 1528 * e1000_check_polarity_igp - Checks the polarity. 1529 * @hw: pointer to the HW structure 1530 * 1531 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1532 * 1533 * Polarity is determined based on the PHY port status register, and the 1534 * current speed (since there is no polarity at 100Mbps). 1535 **/ 1536 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1537 { 1538 struct e1000_phy_info *phy = &hw->phy; 1539 s32 ret_val; 1540 u16 data, offset, mask; 1541 1542 DEBUGFUNC("e1000_check_polarity_igp"); 1543 1544 /* 1545 * Polarity is determined based on the speed of 1546 * our connection. 1547 */ 1548 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1549 if (ret_val) 1550 goto out; 1551 1552 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1553 IGP01E1000_PSSR_SPEED_1000MBPS) { 1554 offset = IGP01E1000_PHY_PCS_INIT_REG; 1555 mask = IGP01E1000_PHY_POLARITY_MASK; 1556 } else { 1557 /* 1558 * This really only applies to 10Mbps since 1559 * there is no polarity for 100Mbps (always 0). 1560 */ 1561 offset = IGP01E1000_PHY_PORT_STATUS; 1562 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1563 } 1564 1565 ret_val = phy->ops.read_reg(hw, offset, &data); 1566 1567 if (!ret_val) 1568 phy->cable_polarity = (data & mask) 1569 ? e1000_rev_polarity_reversed 1570 : e1000_rev_polarity_normal; 1571 1572 out: 1573 return ret_val; 1574 } 1575 1576 /** 1577 * e1000_wait_autoneg_generic - Wait for auto-neg completion 1578 * @hw: pointer to the HW structure 1579 * 1580 * Waits for auto-negotiation to complete or for the auto-negotiation time 1581 * limit to expire, which ever happens first. 1582 **/ 1583 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1584 { 1585 s32 ret_val = E1000_SUCCESS; 1586 u16 i, phy_status; 1587 1588 DEBUGFUNC("e1000_wait_autoneg_generic"); 1589 1590 if (!(hw->phy.ops.read_reg)) 1591 return E1000_SUCCESS; 1592 1593 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1594 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1595 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1596 if (ret_val) 1597 break; 1598 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1599 if (ret_val) 1600 break; 1601 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1602 break; 1603 msec_delay(100); 1604 } 1605 1606 /* 1607 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1608 * has completed. 1609 */ 1610 return ret_val; 1611 } 1612 1613 /** 1614 * e1000_phy_has_link_generic - Polls PHY for link 1615 * @hw: pointer to the HW structure 1616 * @iterations: number of times to poll for link 1617 * @usec_interval: delay between polling attempts 1618 * @success: pointer to whether polling was successful or not 1619 * 1620 * Polls the PHY status register for link, 'iterations' number of times. 1621 **/ 1622 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1623 u32 usec_interval, bool *success) 1624 { 1625 s32 ret_val = E1000_SUCCESS; 1626 u16 i, phy_status; 1627 1628 DEBUGFUNC("e1000_phy_has_link_generic"); 1629 1630 if (!(hw->phy.ops.read_reg)) 1631 return E1000_SUCCESS; 1632 1633 for (i = 0; i < iterations; i++) { 1634 /* 1635 * Some PHYs require the PHY_STATUS register to be read 1636 * twice due to the link bit being sticky. No harm doing 1637 * it across the board. 1638 */ 1639 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1640 if (ret_val) 1641 break; 1642 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1643 if (ret_val) 1644 break; 1645 if (phy_status & MII_SR_LINK_STATUS) 1646 break; 1647 if (usec_interval >= 1000) 1648 msec_delay_irq(usec_interval/1000); 1649 else 1650 usec_delay(usec_interval); 1651 } 1652 1653 *success = (i < iterations) ? TRUE : FALSE; 1654 1655 return ret_val; 1656 } 1657 1658 /** 1659 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1660 * @hw: pointer to the HW structure 1661 * 1662 * Reads the PHY specific status register to retrieve the cable length 1663 * information. The cable length is determined by averaging the minimum and 1664 * maximum values to get the "average" cable length. The m88 PHY has four 1665 * possible cable length values, which are: 1666 * Register Value Cable Length 1667 * 0 < 50 meters 1668 * 1 50 - 80 meters 1669 * 2 80 - 110 meters 1670 * 3 110 - 140 meters 1671 * 4 > 140 meters 1672 **/ 1673 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 1674 { 1675 struct e1000_phy_info *phy = &hw->phy; 1676 s32 ret_val; 1677 u16 phy_data, index; 1678 1679 DEBUGFUNC("e1000_get_cable_length_m88"); 1680 1681 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1682 if (ret_val) 1683 goto out; 1684 1685 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1686 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1687 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1688 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1689 1690 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1691 1692 out: 1693 return ret_val; 1694 } 1695 1696 /** 1697 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1698 * @hw: pointer to the HW structure 1699 * 1700 * The automatic gain control (agc) normalizes the amplitude of the 1701 * received signal, adjusting for the attenuation produced by the 1702 * cable. By reading the AGC registers, which represent the 1703 * combination of coarse and fine gain value, the value can be put 1704 * into a lookup table to obtain the approximate cable length 1705 * for each channel. 1706 **/ 1707 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1708 { 1709 struct e1000_phy_info *phy = &hw->phy; 1710 s32 ret_val = E1000_SUCCESS; 1711 u16 phy_data, i, agc_value = 0; 1712 u16 cur_agc_index, max_agc_index = 0; 1713 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1714 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1715 {IGP02E1000_PHY_AGC_A, 1716 IGP02E1000_PHY_AGC_B, 1717 IGP02E1000_PHY_AGC_C, 1718 IGP02E1000_PHY_AGC_D}; 1719 1720 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1721 1722 /* Read the AGC registers for all channels */ 1723 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1724 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1725 if (ret_val) 1726 goto out; 1727 1728 /* 1729 * Getting bits 15:9, which represent the combination of 1730 * coarse and fine gain values. The result is a number 1731 * that can be put into the lookup table to obtain the 1732 * approximate cable length. 1733 */ 1734 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1735 IGP02E1000_AGC_LENGTH_MASK; 1736 1737 /* Array index bound check. */ 1738 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1739 (cur_agc_index == 0)) { 1740 ret_val = -E1000_ERR_PHY; 1741 goto out; 1742 } 1743 1744 /* Remove min & max AGC values from calculation. */ 1745 if (e1000_igp_2_cable_length_table[min_agc_index] > 1746 e1000_igp_2_cable_length_table[cur_agc_index]) 1747 min_agc_index = cur_agc_index; 1748 if (e1000_igp_2_cable_length_table[max_agc_index] < 1749 e1000_igp_2_cable_length_table[cur_agc_index]) 1750 max_agc_index = cur_agc_index; 1751 1752 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1753 } 1754 1755 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1756 e1000_igp_2_cable_length_table[max_agc_index]); 1757 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1758 1759 /* Calculate cable length with the error range of +/- 10 meters. */ 1760 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1761 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1762 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1763 1764 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1765 1766 out: 1767 return ret_val; 1768 } 1769 1770 /** 1771 * e1000_get_phy_info_m88 - Retrieve PHY information 1772 * @hw: pointer to the HW structure 1773 * 1774 * Valid for only copper links. Read the PHY status register (sticky read) 1775 * to verify that link is up. Read the PHY special control register to 1776 * determine the polarity and 10base-T extended distance. Read the PHY 1777 * special status register to determine MDI/MDIx and current speed. If 1778 * speed is 1000, then determine cable length, local and remote receiver. 1779 **/ 1780 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 1781 { 1782 struct e1000_phy_info *phy = &hw->phy; 1783 s32 ret_val; 1784 u16 phy_data; 1785 bool link; 1786 1787 DEBUGFUNC("e1000_get_phy_info_m88"); 1788 1789 if (hw->phy.media_type != e1000_media_type_copper) { 1790 DEBUGOUT("Phy info is only valid for copper media\n"); 1791 ret_val = -E1000_ERR_CONFIG; 1792 goto out; 1793 } 1794 1795 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1796 if (ret_val) 1797 goto out; 1798 1799 if (!link) { 1800 DEBUGOUT("Phy info is only valid if link is up\n"); 1801 ret_val = -E1000_ERR_CONFIG; 1802 goto out; 1803 } 1804 1805 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1806 if (ret_val) 1807 goto out; 1808 1809 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1810 ? TRUE 1811 : FALSE; 1812 1813 ret_val = e1000_check_polarity_m88(hw); 1814 if (ret_val) 1815 goto out; 1816 1817 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1818 if (ret_val) 1819 goto out; 1820 1821 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 1822 1823 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1824 ret_val = hw->phy.ops.get_cable_length(hw); 1825 if (ret_val) 1826 goto out; 1827 1828 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1829 if (ret_val) 1830 goto out; 1831 1832 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1833 ? e1000_1000t_rx_status_ok 1834 : e1000_1000t_rx_status_not_ok; 1835 1836 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1837 ? e1000_1000t_rx_status_ok 1838 : e1000_1000t_rx_status_not_ok; 1839 } else { 1840 /* Set values to "undefined" */ 1841 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1842 phy->local_rx = e1000_1000t_rx_status_undefined; 1843 phy->remote_rx = e1000_1000t_rx_status_undefined; 1844 } 1845 1846 out: 1847 return ret_val; 1848 } 1849 1850 /** 1851 * e1000_get_phy_info_igp - Retrieve igp PHY information 1852 * @hw: pointer to the HW structure 1853 * 1854 * Read PHY status to determine if link is up. If link is up, then 1855 * set/determine 10base-T extended distance and polarity correction. Read 1856 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1857 * determine on the cable length, local and remote receiver. 1858 **/ 1859 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 1860 { 1861 struct e1000_phy_info *phy = &hw->phy; 1862 s32 ret_val; 1863 u16 data; 1864 bool link; 1865 1866 DEBUGFUNC("e1000_get_phy_info_igp"); 1867 1868 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1869 if (ret_val) 1870 goto out; 1871 1872 if (!link) { 1873 DEBUGOUT("Phy info is only valid if link is up\n"); 1874 ret_val = -E1000_ERR_CONFIG; 1875 goto out; 1876 } 1877 1878 phy->polarity_correction = TRUE; 1879 1880 ret_val = e1000_check_polarity_igp(hw); 1881 if (ret_val) 1882 goto out; 1883 1884 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1885 if (ret_val) 1886 goto out; 1887 1888 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 1889 1890 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1891 IGP01E1000_PSSR_SPEED_1000MBPS) { 1892 ret_val = hw->phy.ops.get_cable_length(hw); 1893 if (ret_val) 1894 goto out; 1895 1896 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 1897 if (ret_val) 1898 goto out; 1899 1900 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1901 ? e1000_1000t_rx_status_ok 1902 : e1000_1000t_rx_status_not_ok; 1903 1904 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1905 ? e1000_1000t_rx_status_ok 1906 : e1000_1000t_rx_status_not_ok; 1907 } else { 1908 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1909 phy->local_rx = e1000_1000t_rx_status_undefined; 1910 phy->remote_rx = e1000_1000t_rx_status_undefined; 1911 } 1912 1913 out: 1914 return ret_val; 1915 } 1916 1917 /** 1918 * e1000_phy_sw_reset_generic - PHY software reset 1919 * @hw: pointer to the HW structure 1920 * 1921 * Does a software reset of the PHY by reading the PHY control register and 1922 * setting/write the control register reset bit to the PHY. 1923 **/ 1924 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 1925 { 1926 s32 ret_val = E1000_SUCCESS; 1927 u16 phy_ctrl; 1928 1929 DEBUGFUNC("e1000_phy_sw_reset_generic"); 1930 1931 if (!(hw->phy.ops.read_reg)) 1932 goto out; 1933 1934 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1935 if (ret_val) 1936 goto out; 1937 1938 phy_ctrl |= MII_CR_RESET; 1939 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1940 if (ret_val) 1941 goto out; 1942 1943 usec_delay(1); 1944 1945 out: 1946 return ret_val; 1947 } 1948 1949 /** 1950 * e1000_phy_hw_reset_generic - PHY hardware reset 1951 * @hw: pointer to the HW structure 1952 * 1953 * Verify the reset block is not blocking us from resetting. Acquire 1954 * semaphore (if necessary) and read/set/write the device control reset 1955 * bit in the PHY. Wait the appropriate delay time for the device to 1956 * reset and release the semaphore (if necessary). 1957 **/ 1958 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 1959 { 1960 struct e1000_phy_info *phy = &hw->phy; 1961 s32 ret_val = E1000_SUCCESS; 1962 u32 ctrl; 1963 1964 DEBUGFUNC("e1000_phy_hw_reset_generic"); 1965 1966 ret_val = phy->ops.check_reset_block(hw); 1967 if (ret_val) { 1968 ret_val = E1000_SUCCESS; 1969 goto out; 1970 } 1971 1972 ret_val = phy->ops.acquire(hw); 1973 if (ret_val) 1974 goto out; 1975 1976 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1977 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 1978 E1000_WRITE_FLUSH(hw); 1979 1980 usec_delay(phy->reset_delay_us); 1981 1982 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1983 E1000_WRITE_FLUSH(hw); 1984 1985 usec_delay(150); 1986 1987 phy->ops.release(hw); 1988 1989 ret_val = phy->ops.get_cfg_done(hw); 1990 1991 out: 1992 return ret_val; 1993 } 1994 1995 /** 1996 * e1000_get_cfg_done_generic - Generic configuration done 1997 * @hw: pointer to the HW structure 1998 * 1999 * Generic function to wait 10 milli-seconds for configuration to complete 2000 * and return success. 2001 **/ 2002 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2003 { 2004 DEBUGFUNC("e1000_get_cfg_done_generic"); 2005 2006 msec_delay_irq(10); 2007 2008 return E1000_SUCCESS; 2009 } 2010 2011 /** 2012 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2013 * @hw: pointer to the HW structure 2014 * 2015 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2016 **/ 2017 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2018 { 2019 DEBUGOUT("Running IGP 3 PHY init script\n"); 2020 2021 /* PHY init IGP 3 */ 2022 /* Enable rise/fall, 10-mode work in class-A */ 2023 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2024 /* Remove all caps from Replica path filter */ 2025 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2026 /* Bias trimming for ADC, AFE and Driver (Default) */ 2027 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2028 /* Increase Hybrid poly bias */ 2029 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2030 /* Add 4% to Tx amplitude in Gig mode */ 2031 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2032 /* Disable trimming (TTT) */ 2033 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2034 /* Poly DC correction to 94.6% + 2% for all channels */ 2035 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2036 /* ABS DC correction to 95.9% */ 2037 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2038 /* BG temp curve trim */ 2039 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2040 /* Increasing ADC OPAMP stage 1 currents to max */ 2041 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2042 /* Force 1000 ( required for enabling PHY regs configuration) */ 2043 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2044 /* Set upd_freq to 6 */ 2045 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2046 /* Disable NPDFE */ 2047 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2048 /* Disable adaptive fixed FFE (Default) */ 2049 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2050 /* Enable FFE hysteresis */ 2051 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2052 /* Fixed FFE for short cable lengths */ 2053 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2054 /* Fixed FFE for medium cable lengths */ 2055 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2056 /* Fixed FFE for long cable lengths */ 2057 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2058 /* Enable Adaptive Clip Threshold */ 2059 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2060 /* AHT reset limit to 1 */ 2061 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2062 /* Set AHT master delay to 127 msec */ 2063 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2064 /* Set scan bits for AHT */ 2065 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2066 /* Set AHT Preset bits */ 2067 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2068 /* Change integ_factor of channel A to 3 */ 2069 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2070 /* Change prop_factor of channels BCD to 8 */ 2071 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2072 /* Change cg_icount + enable integbp for channels BCD */ 2073 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2074 /* 2075 * Change cg_icount + enable integbp + change prop_factor_master 2076 * to 8 for channel A 2077 */ 2078 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2079 /* Disable AHT in Slave mode on channel A */ 2080 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2081 /* 2082 * Enable LPLU and disable AN to 1000 in non-D0a states, 2083 * Enable SPD+B2B 2084 */ 2085 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2086 /* Enable restart AN on an1000_dis change */ 2087 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2088 /* Enable wh_fifo read clock in 10/100 modes */ 2089 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2090 /* Restart AN, Speed selection is 1000 */ 2091 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2092 2093 return E1000_SUCCESS; 2094 } 2095 2096 /** 2097 * e1000_get_phy_type_from_id - Get PHY type from id 2098 * @phy_id: phy_id read from the phy 2099 * 2100 * Returns the phy type from the id. 2101 **/ 2102 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2103 { 2104 enum e1000_phy_type phy_type = e1000_phy_unknown; 2105 2106 switch (phy_id) { 2107 case M88E1000_I_PHY_ID: 2108 case M88E1000_E_PHY_ID: 2109 case M88E1111_I_PHY_ID: 2110 case M88E1011_I_PHY_ID: 2111 phy_type = e1000_phy_m88; 2112 break; 2113 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2114 phy_type = e1000_phy_igp_2; 2115 break; 2116 case GG82563_E_PHY_ID: 2117 phy_type = e1000_phy_gg82563; 2118 break; 2119 case IGP03E1000_E_PHY_ID: 2120 phy_type = e1000_phy_igp_3; 2121 break; 2122 case IFE_E_PHY_ID: 2123 case IFE_PLUS_E_PHY_ID: 2124 case IFE_C_E_PHY_ID: 2125 phy_type = e1000_phy_ife; 2126 break; 2127 case BME1000_E_PHY_ID: 2128 case BME1000_E_PHY_ID_R2: 2129 phy_type = e1000_phy_bm; 2130 break; 2131 default: 2132 phy_type = e1000_phy_unknown; 2133 break; 2134 } 2135 return phy_type; 2136 } 2137 2138 /** 2139 * e1000_determine_phy_address - Determines PHY address. 2140 * @hw: pointer to the HW structure 2141 * 2142 * This uses a trial and error method to loop through possible PHY 2143 * addresses. It tests each by reading the PHY ID registers and 2144 * checking for a match. 2145 **/ 2146 s32 e1000_determine_phy_address(struct e1000_hw* hw) 2147 { 2148 s32 ret_val = -E1000_ERR_PHY_TYPE; 2149 u32 phy_addr= 0; 2150 u32 i; 2151 enum e1000_phy_type phy_type = e1000_phy_unknown; 2152 2153 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2154 hw->phy.addr = phy_addr; 2155 i = 0; 2156 2157 do { 2158 e1000_get_phy_id(hw); 2159 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2160 2161 /* 2162 * If phy_type is valid, break - we found our 2163 * PHY address 2164 */ 2165 if (phy_type != e1000_phy_unknown) { 2166 ret_val = E1000_SUCCESS; 2167 goto out; 2168 } 2169 msec_delay(1); 2170 i++; 2171 } while (i < 10); 2172 } 2173 2174 out: 2175 return ret_val; 2176 } 2177 2178 /** 2179 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2180 * @page: page to access 2181 * 2182 * Returns the phy address for the page requested. 2183 **/ 2184 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2185 { 2186 u32 phy_addr = 2; 2187 2188 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2189 phy_addr = 1; 2190 2191 return phy_addr; 2192 } 2193 2194 /** 2195 * e1000_write_phy_reg_bm - Write BM PHY register 2196 * @hw: pointer to the HW structure 2197 * @offset: register offset to write to 2198 * @data: data to write at register offset 2199 * 2200 * Acquires semaphore, if necessary, then writes the data to PHY register 2201 * at the offset. Release any acquired semaphores before exiting. 2202 **/ 2203 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2204 { 2205 s32 ret_val; 2206 u32 page_select = 0; 2207 u32 page = offset >> IGP_PAGE_SHIFT; 2208 u32 page_shift = 0; 2209 2210 DEBUGFUNC("e1000_write_phy_reg_bm"); 2211 2212 /* Page 800 works differently than the rest so it has its own func */ 2213 if (page == BM_WUC_PAGE) { 2214 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2215 offset, &data, FALSE); 2216 goto out; 2217 } 2218 2219 ret_val = hw->phy.ops.acquire(hw); 2220 if (ret_val) 2221 goto out; 2222 2223 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2224 2225 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2226 /* 2227 * Page select is register 31 for phy address 1 and 22 for 2228 * phy address 2 and 3. Page select is shifted only for 2229 * phy address 1. 2230 */ 2231 if (hw->phy.addr == 1) { 2232 page_shift = IGP_PAGE_SHIFT; 2233 page_select = IGP01E1000_PHY_PAGE_SELECT; 2234 } else { 2235 page_shift = 0; 2236 page_select = BM_PHY_PAGE_SELECT; 2237 } 2238 2239 /* Page is shifted left, PHY expects (page x 32) */ 2240 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2241 (page << page_shift)); 2242 if (ret_val) { 2243 hw->phy.ops.release(hw); 2244 goto out; 2245 } 2246 } 2247 2248 ret_val = e1000_write_phy_reg_mdic(hw, 2249 MAX_PHY_REG_ADDRESS & offset, 2250 data); 2251 2252 hw->phy.ops.release(hw); 2253 2254 out: 2255 return ret_val; 2256 } 2257 2258 /** 2259 * e1000_read_phy_reg_bm - Read BM PHY register 2260 * @hw: pointer to the HW structure 2261 * @offset: register offset to be read 2262 * @data: pointer to the read data 2263 * 2264 * Acquires semaphore, if necessary, then reads the PHY register at offset 2265 * and storing the retrieved information in data. Release any acquired 2266 * semaphores before exiting. 2267 **/ 2268 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2269 { 2270 s32 ret_val; 2271 u32 page_select = 0; 2272 u32 page = offset >> IGP_PAGE_SHIFT; 2273 u32 page_shift = 0; 2274 2275 DEBUGFUNC("e1000_read_phy_reg_bm"); 2276 2277 /* Page 800 works differently than the rest so it has its own func */ 2278 if (page == BM_WUC_PAGE) { 2279 ret_val = e1000_access_phy_wakeup_reg_bm(hw, 2280 offset, data, TRUE); 2281 goto out; 2282 } 2283 2284 ret_val = hw->phy.ops.acquire(hw); 2285 if (ret_val) 2286 goto out; 2287 2288 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2289 2290 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2291 /* 2292 * Page select is register 31 for phy address 1 and 22 for 2293 * phy address 2 and 3. Page select is shifted only for 2294 * phy address 1. 2295 */ 2296 if (hw->phy.addr == 1) { 2297 page_shift = IGP_PAGE_SHIFT; 2298 page_select = IGP01E1000_PHY_PAGE_SELECT; 2299 } else { 2300 page_shift = 0; 2301 page_select = BM_PHY_PAGE_SELECT; 2302 } 2303 2304 /* Page is shifted left, PHY expects (page x 32) */ 2305 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2306 (page << page_shift)); 2307 if (ret_val) { 2308 hw->phy.ops.release(hw); 2309 goto out; 2310 } 2311 } 2312 2313 ret_val = e1000_read_phy_reg_mdic(hw, 2314 MAX_PHY_REG_ADDRESS & offset, 2315 data); 2316 hw->phy.ops.release(hw); 2317 2318 out: 2319 return ret_val; 2320 } 2321 2322 /** 2323 * e1000_read_phy_reg_bm2 - Read BM PHY register 2324 * @hw: pointer to the HW structure 2325 * @offset: register offset to be read 2326 * @data: pointer to the read data 2327 * 2328 * Acquires semaphore, if necessary, then reads the PHY register at offset 2329 * and storing the retrieved information in data. Release any acquired 2330 * semaphores before exiting. 2331 **/ 2332 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2333 { 2334 s32 ret_val; 2335 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2336 2337 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2338 2339 /* Page 800 works differently than the rest so it has its own func */ 2340 if (page == BM_WUC_PAGE) { 2341 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2342 TRUE); 2343 goto out; 2344 } 2345 2346 ret_val = hw->phy.ops.acquire(hw); 2347 if (ret_val) 2348 goto out; 2349 2350 hw->phy.addr = 1; 2351 2352 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2353 2354 /* Page is shifted left, PHY expects (page x 32) */ 2355 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2356 page); 2357 2358 if (ret_val) { 2359 hw->phy.ops.release(hw); 2360 goto out; 2361 } 2362 } 2363 2364 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2365 data); 2366 hw->phy.ops.release(hw); 2367 2368 out: 2369 return ret_val; 2370 } 2371 2372 /** 2373 * e1000_write_phy_reg_bm2 - Write BM PHY register 2374 * @hw: pointer to the HW structure 2375 * @offset: register offset to write to 2376 * @data: data to write at register offset 2377 * 2378 * Acquires semaphore, if necessary, then writes the data to PHY register 2379 * at the offset. Release any acquired semaphores before exiting. 2380 **/ 2381 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2382 { 2383 s32 ret_val; 2384 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2385 2386 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2387 2388 /* Page 800 works differently than the rest so it has its own func */ 2389 if (page == BM_WUC_PAGE) { 2390 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2391 FALSE); 2392 goto out; 2393 } 2394 2395 ret_val = hw->phy.ops.acquire(hw); 2396 if (ret_val) 2397 goto out; 2398 2399 hw->phy.addr = 1; 2400 2401 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2402 /* Page is shifted left, PHY expects (page x 32) */ 2403 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2404 page); 2405 2406 if (ret_val) { 2407 hw->phy.ops.release(hw); 2408 goto out; 2409 } 2410 } 2411 2412 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2413 data); 2414 2415 hw->phy.ops.release(hw); 2416 2417 out: 2418 return ret_val; 2419 } 2420 2421 /** 2422 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2423 * @hw: pointer to the HW structure 2424 * @offset: register offset to be read or written 2425 * @data: pointer to the data to read or write 2426 * @read: determines if operation is read or write 2427 * 2428 * Acquires semaphore, if necessary, then reads the PHY register at offset 2429 * and storing the retrieved information in data. Release any acquired 2430 * semaphores before exiting. Note that procedure to read the wakeup 2431 * registers are different. It works as such: 2432 * 1) Set page 769, register 17, bit 2 = 1 2433 * 2) Set page to 800 for host (801 if we were manageability) 2434 * 3) Write the address using the address opcode (0x11) 2435 * 4) Read or write the data using the data opcode (0x12) 2436 * 5) Restore 769_17.2 to its original value 2437 **/ 2438 s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, 2439 u32 offset, u16 *data, bool read) 2440 { 2441 s32 ret_val; 2442 u16 reg = ((u16)offset); 2443 u16 phy_reg = 0; 2444 u8 phy_acquired = 1; 2445 2446 DEBUGFUNC("e1000_read_phy_wakeup_reg_bm"); 2447 2448 ret_val = hw->phy.ops.acquire(hw); 2449 if (ret_val) { 2450 DEBUGOUT("Could not acquire PHY\n"); 2451 phy_acquired = 0; 2452 goto out; 2453 } 2454 2455 /* All operations in this function are phy address 1 */ 2456 hw->phy.addr = 1; 2457 2458 /* Set page 769 */ 2459 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2460 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2461 2462 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2463 if (ret_val) { 2464 DEBUGOUT("Could not read PHY page 769\n"); 2465 goto out; 2466 } 2467 2468 /* First clear bit 4 to avoid a power state change */ 2469 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2470 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2471 if (ret_val) { 2472 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 2473 goto out; 2474 } 2475 2476 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2477 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2478 phy_reg | BM_WUC_ENABLE_BIT); 2479 if (ret_val) { 2480 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 2481 goto out; 2482 } 2483 2484 /* Select page 800 */ 2485 ret_val = e1000_write_phy_reg_mdic(hw, 2486 IGP01E1000_PHY_PAGE_SELECT, 2487 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2488 2489 /* Write the page 800 offset value using opcode 0x11 */ 2490 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2491 if (ret_val) { 2492 DEBUGOUT("Could not write address opcode to page 800\n"); 2493 goto out; 2494 } 2495 2496 if (read) { 2497 /* Read the page 800 value using opcode 0x12 */ 2498 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2499 data); 2500 } else { 2501 /* Read the page 800 value using opcode 0x12 */ 2502 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2503 *data); 2504 } 2505 2506 if (ret_val) { 2507 DEBUGOUT("Could not read data value from page 800\n"); 2508 goto out; 2509 } 2510 2511 /* 2512 * Restore 769_17.2 to its original value 2513 * Set page 769 2514 */ 2515 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2516 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2517 2518 /* Clear 769_17.2 */ 2519 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2520 if (ret_val) { 2521 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 2522 goto out; 2523 } 2524 2525 out: 2526 if (phy_acquired == 1) 2527 hw->phy.ops.release(hw); 2528 return ret_val; 2529 } 2530 2531 /** 2532 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2533 * @hw: pointer to the HW structure 2534 * 2535 * In the case of a PHY power down to save power, or to turn off link during a 2536 * driver unload, or wake on lan is not enabled, restore the link to previous 2537 * settings. 2538 **/ 2539 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2540 { 2541 u16 mii_reg = 0; 2542 2543 /* The PHY will retain its settings across a power down/up cycle */ 2544 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2545 mii_reg &= ~MII_CR_POWER_DOWN; 2546 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2547 } 2548 2549 /** 2550 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2551 * @hw: pointer to the HW structure 2552 * 2553 * In the case of a PHY power down to save power, or to turn off link during a 2554 * driver unload, or wake on lan is not enabled, restore the link to previous 2555 * settings. 2556 **/ 2557 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2558 { 2559 u16 mii_reg = 0; 2560 2561 /* The PHY will retain its settings across a power down/up cycle */ 2562 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2563 mii_reg |= MII_CR_POWER_DOWN; 2564 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2565 msec_delay(1); 2566 } 2567