1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "e1000_api.h" 36 37 /* 38 * NOTE: the following routines using the e1000 39 * naming style are provided to the shared 40 * code but are OS specific 41 */ 42 43 void 44 e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 45 { 46 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2); 47 } 48 49 void 50 e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 51 { 52 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2); 53 } 54 55 void 56 e1000_pci_set_mwi(struct e1000_hw *hw) 57 { 58 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 59 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 60 } 61 62 void 63 e1000_pci_clear_mwi(struct e1000_hw *hw) 64 { 65 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 66 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 67 } 68 69 /* 70 * Read the PCI Express capabilities 71 */ 72 int32_t 73 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 74 { 75 device_t dev = ((struct e1000_osdep *)hw->back)->dev; 76 u32 offset; 77 78 pci_find_cap(dev, PCIY_EXPRESS, &offset); 79 *value = pci_read_config(dev, offset + reg, 2); 80 return (E1000_SUCCESS); 81 } 82 83 /* 84 * Write the PCI Express capabilities 85 */ 86 int32_t 87 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 88 { 89 device_t dev = ((struct e1000_osdep *)hw->back)->dev; 90 u32 offset; 91 92 pci_find_cap(dev, PCIY_EXPRESS, &offset); 93 pci_write_config(dev, offset + reg, *value, 2); 94 return (E1000_SUCCESS); 95 } 96