xref: /freebsd/sys/dev/e1000/e1000_nvm.c (revision de0ae5d1cb896dbc04c5334ef0b864b3c841c3ce)
1 /******************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2020, Intel Corporation
5   All rights reserved.
6 
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32 
33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #include "e1000_api.h"
37 
38 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
39 
40 /**
41  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
42  *  @hw: pointer to the HW structure
43  *
44  *  Setups up the function pointers to no-op functions
45  **/
46 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 {
48 	struct e1000_nvm_info *nvm = &hw->nvm;
49 	DEBUGFUNC("e1000_init_nvm_ops_generic");
50 
51 	/* Initialize function pointers */
52 	nvm->ops.init_params = e1000_null_ops_generic;
53 	nvm->ops.acquire = e1000_null_ops_generic;
54 	nvm->ops.read = e1000_null_read_nvm;
55 	nvm->ops.release = e1000_null_nvm_generic;
56 	nvm->ops.reload = e1000_reload_nvm_generic;
57 	nvm->ops.update = e1000_null_ops_generic;
58 	nvm->ops.valid_led_default = e1000_null_led_default;
59 	nvm->ops.validate = e1000_null_ops_generic;
60 	nvm->ops.write = e1000_null_write_nvm;
61 }
62 
63 /**
64  *  e1000_null_nvm_read - No-op function, return 0
65  *  @hw: pointer to the HW structure
66  **/
67 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
68 			u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
69 			u16 E1000_UNUSEDARG *c)
70 {
71 	DEBUGFUNC("e1000_null_read_nvm");
72 	return E1000_SUCCESS;
73 }
74 
75 /**
76  *  e1000_null_nvm_generic - No-op function, return void
77  *  @hw: pointer to the HW structure
78  **/
79 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
80 {
81 	DEBUGFUNC("e1000_null_nvm_generic");
82 	return;
83 }
84 
85 /**
86  *  e1000_null_led_default - No-op function, return 0
87  *  @hw: pointer to the HW structure
88  **/
89 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
90 			   u16 E1000_UNUSEDARG *data)
91 {
92 	DEBUGFUNC("e1000_null_led_default");
93 	return E1000_SUCCESS;
94 }
95 
96 /**
97  *  e1000_null_write_nvm - No-op function, return 0
98  *  @hw: pointer to the HW structure
99  **/
100 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
101 			 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
102 			 u16 E1000_UNUSEDARG *c)
103 {
104 	DEBUGFUNC("e1000_null_write_nvm");
105 	return E1000_SUCCESS;
106 }
107 
108 /**
109  *  e1000_raise_eec_clk - Raise EEPROM clock
110  *  @hw: pointer to the HW structure
111  *  @eecd: pointer to the EEPROM
112  *
113  *  Enable/Raise the EEPROM clock bit.
114  **/
115 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
116 {
117 	*eecd = *eecd | E1000_EECD_SK;
118 	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
119 	E1000_WRITE_FLUSH(hw);
120 	usec_delay(hw->nvm.delay_usec);
121 }
122 
123 /**
124  *  e1000_lower_eec_clk - Lower EEPROM clock
125  *  @hw: pointer to the HW structure
126  *  @eecd: pointer to the EEPROM
127  *
128  *  Clear/Lower the EEPROM clock bit.
129  **/
130 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
131 {
132 	*eecd = *eecd & ~E1000_EECD_SK;
133 	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
134 	E1000_WRITE_FLUSH(hw);
135 	usec_delay(hw->nvm.delay_usec);
136 }
137 
138 /**
139  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
140  *  @hw: pointer to the HW structure
141  *  @data: data to send to the EEPROM
142  *  @count: number of bits to shift out
143  *
144  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
145  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
146  *  In order to do this, "data" must be broken down into bits.
147  **/
148 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
149 {
150 	struct e1000_nvm_info *nvm = &hw->nvm;
151 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
152 	u32 mask;
153 
154 	DEBUGFUNC("e1000_shift_out_eec_bits");
155 
156 	mask = 0x01 << (count - 1);
157 	if (nvm->type == e1000_nvm_eeprom_microwire)
158 		eecd &= ~E1000_EECD_DO;
159 	else
160 	if (nvm->type == e1000_nvm_eeprom_spi)
161 		eecd |= E1000_EECD_DO;
162 
163 	do {
164 		eecd &= ~E1000_EECD_DI;
165 
166 		if (data & mask)
167 			eecd |= E1000_EECD_DI;
168 
169 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
170 		E1000_WRITE_FLUSH(hw);
171 
172 		usec_delay(nvm->delay_usec);
173 
174 		e1000_raise_eec_clk(hw, &eecd);
175 		e1000_lower_eec_clk(hw, &eecd);
176 
177 		mask >>= 1;
178 	} while (mask);
179 
180 	eecd &= ~E1000_EECD_DI;
181 	E1000_WRITE_REG(hw, E1000_EECD, eecd);
182 }
183 
184 /**
185  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
186  *  @hw: pointer to the HW structure
187  *  @count: number of bits to shift in
188  *
189  *  In order to read a register from the EEPROM, we need to shift 'count' bits
190  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
191  *  the EEPROM (setting the SK bit), and then reading the value of the data out
192  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
193  *  always be clear.
194  **/
195 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
196 {
197 	u32 eecd;
198 	u32 i;
199 	u16 data;
200 
201 	DEBUGFUNC("e1000_shift_in_eec_bits");
202 
203 	eecd = E1000_READ_REG(hw, E1000_EECD);
204 
205 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
206 	data = 0;
207 
208 	for (i = 0; i < count; i++) {
209 		data <<= 1;
210 		e1000_raise_eec_clk(hw, &eecd);
211 
212 		eecd = E1000_READ_REG(hw, E1000_EECD);
213 
214 		eecd &= ~E1000_EECD_DI;
215 		if (eecd & E1000_EECD_DO)
216 			data |= 1;
217 
218 		e1000_lower_eec_clk(hw, &eecd);
219 	}
220 
221 	return data;
222 }
223 
224 /**
225  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
226  *  @hw: pointer to the HW structure
227  *  @ee_reg: EEPROM flag for polling
228  *
229  *  Polls the EEPROM status bit for either read or write completion based
230  *  upon the value of 'ee_reg'.
231  **/
232 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
233 {
234 	u32 attempts = 100000;
235 	u32 i, reg = 0;
236 
237 	DEBUGFUNC("e1000_poll_eerd_eewr_done");
238 
239 	for (i = 0; i < attempts; i++) {
240 		if (ee_reg == E1000_NVM_POLL_READ)
241 			reg = E1000_READ_REG(hw, E1000_EERD);
242 		else
243 			reg = E1000_READ_REG(hw, E1000_EEWR);
244 
245 		if (reg & E1000_NVM_RW_REG_DONE)
246 			return E1000_SUCCESS;
247 
248 		usec_delay(5);
249 	}
250 
251 	return -E1000_ERR_NVM;
252 }
253 
254 /**
255  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
256  *  @hw: pointer to the HW structure
257  *
258  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
259  *  Return successful if access grant bit set, else clear the request for
260  *  EEPROM access and return -E1000_ERR_NVM (-1).
261  **/
262 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
263 {
264 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
265 	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
266 
267 	DEBUGFUNC("e1000_acquire_nvm_generic");
268 
269 	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
270 	eecd = E1000_READ_REG(hw, E1000_EECD);
271 
272 	while (timeout) {
273 		if (eecd & E1000_EECD_GNT)
274 			break;
275 		usec_delay(5);
276 		eecd = E1000_READ_REG(hw, E1000_EECD);
277 		timeout--;
278 	}
279 
280 	if (!timeout) {
281 		eecd &= ~E1000_EECD_REQ;
282 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
283 		DEBUGOUT("Could not acquire NVM grant\n");
284 		return -E1000_ERR_NVM;
285 	}
286 
287 	return E1000_SUCCESS;
288 }
289 
290 /**
291  *  e1000_standby_nvm - Return EEPROM to standby state
292  *  @hw: pointer to the HW structure
293  *
294  *  Return the EEPROM to a standby state.
295  **/
296 static void e1000_standby_nvm(struct e1000_hw *hw)
297 {
298 	struct e1000_nvm_info *nvm = &hw->nvm;
299 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
300 
301 	DEBUGFUNC("e1000_standby_nvm");
302 
303 	if (nvm->type == e1000_nvm_eeprom_microwire) {
304 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
305 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
306 		E1000_WRITE_FLUSH(hw);
307 		usec_delay(nvm->delay_usec);
308 
309 		e1000_raise_eec_clk(hw, &eecd);
310 
311 		/* Select EEPROM */
312 		eecd |= E1000_EECD_CS;
313 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
314 		E1000_WRITE_FLUSH(hw);
315 		usec_delay(nvm->delay_usec);
316 
317 		e1000_lower_eec_clk(hw, &eecd);
318 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
319 		/* Toggle CS to flush commands */
320 		eecd |= E1000_EECD_CS;
321 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
322 		E1000_WRITE_FLUSH(hw);
323 		usec_delay(nvm->delay_usec);
324 		eecd &= ~E1000_EECD_CS;
325 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
326 		E1000_WRITE_FLUSH(hw);
327 		usec_delay(nvm->delay_usec);
328 	}
329 }
330 
331 /**
332  *  e1000_stop_nvm - Terminate EEPROM command
333  *  @hw: pointer to the HW structure
334  *
335  *  Terminates the current command by inverting the EEPROM's chip select pin.
336  **/
337 void e1000_stop_nvm(struct e1000_hw *hw)
338 {
339 	u32 eecd;
340 
341 	DEBUGFUNC("e1000_stop_nvm");
342 
343 	eecd = E1000_READ_REG(hw, E1000_EECD);
344 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
345 		/* Pull CS high */
346 		eecd |= E1000_EECD_CS;
347 		e1000_lower_eec_clk(hw, &eecd);
348 	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
349 		/* CS on Microwire is active-high */
350 		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
351 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
352 		e1000_raise_eec_clk(hw, &eecd);
353 		e1000_lower_eec_clk(hw, &eecd);
354 	}
355 }
356 
357 /**
358  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
359  *  @hw: pointer to the HW structure
360  *
361  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
362  **/
363 void e1000_release_nvm_generic(struct e1000_hw *hw)
364 {
365 	u32 eecd;
366 
367 	DEBUGFUNC("e1000_release_nvm_generic");
368 
369 	e1000_stop_nvm(hw);
370 
371 	eecd = E1000_READ_REG(hw, E1000_EECD);
372 	eecd &= ~E1000_EECD_REQ;
373 	E1000_WRITE_REG(hw, E1000_EECD, eecd);
374 }
375 
376 /**
377  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
378  *  @hw: pointer to the HW structure
379  *
380  *  Setups the EEPROM for reading and writing.
381  **/
382 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
383 {
384 	struct e1000_nvm_info *nvm = &hw->nvm;
385 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
386 	u8 spi_stat_reg;
387 
388 	DEBUGFUNC("e1000_ready_nvm_eeprom");
389 
390 	if (nvm->type == e1000_nvm_eeprom_microwire) {
391 		/* Clear SK and DI */
392 		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
393 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
394 		/* Set CS */
395 		eecd |= E1000_EECD_CS;
396 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
397 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
398 		u16 timeout = NVM_MAX_RETRY_SPI;
399 
400 		/* Clear SK and CS */
401 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
402 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
403 		E1000_WRITE_FLUSH(hw);
404 		usec_delay(1);
405 
406 		/* Read "Status Register" repeatedly until the LSB is cleared.
407 		 * The EEPROM will signal that the command has been completed
408 		 * by clearing bit 0 of the internal status register.  If it's
409 		 * not cleared within 'timeout', then error out.
410 		 */
411 		while (timeout) {
412 			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
413 						 hw->nvm.opcode_bits);
414 			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
415 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
416 				break;
417 
418 			usec_delay(5);
419 			e1000_standby_nvm(hw);
420 			timeout--;
421 		}
422 
423 		if (!timeout) {
424 			DEBUGOUT("SPI NVM Status error\n");
425 			return -E1000_ERR_NVM;
426 		}
427 	}
428 
429 	return E1000_SUCCESS;
430 }
431 
432 /**
433  *  e1000_read_nvm_spi - Read EEPROM's using SPI
434  *  @hw: pointer to the HW structure
435  *  @offset: offset of word in the EEPROM to read
436  *  @words: number of words to read
437  *  @data: word read from the EEPROM
438  *
439  *  Reads a 16 bit word from the EEPROM.
440  **/
441 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
442 {
443 	struct e1000_nvm_info *nvm = &hw->nvm;
444 	u32 i = 0;
445 	s32 ret_val;
446 	u16 word_in;
447 	u8 read_opcode = NVM_READ_OPCODE_SPI;
448 
449 	DEBUGFUNC("e1000_read_nvm_spi");
450 
451 	/* A check for invalid values:  offset too large, too many words,
452 	 * and not enough words.
453 	 */
454 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
455 	    (words == 0)) {
456 		DEBUGOUT("nvm parameter(s) out of bounds\n");
457 		return -E1000_ERR_NVM;
458 	}
459 
460 	ret_val = nvm->ops.acquire(hw);
461 	if (ret_val)
462 		return ret_val;
463 
464 	ret_val = e1000_ready_nvm_eeprom(hw);
465 	if (ret_val)
466 		goto release;
467 
468 	e1000_standby_nvm(hw);
469 
470 	if ((nvm->address_bits == 8) && (offset >= 128))
471 		read_opcode |= NVM_A8_OPCODE_SPI;
472 
473 	/* Send the READ command (opcode + addr) */
474 	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
475 	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
476 
477 	/* Read the data.  SPI NVMs increment the address with each byte
478 	 * read and will roll over if reading beyond the end.  This allows
479 	 * us to read the whole NVM from any offset
480 	 */
481 	for (i = 0; i < words; i++) {
482 		word_in = e1000_shift_in_eec_bits(hw, 16);
483 		data[i] = (word_in >> 8) | (word_in << 8);
484 	}
485 
486 release:
487 	nvm->ops.release(hw);
488 
489 	return ret_val;
490 }
491 
492 /**
493  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
494  *  @hw: pointer to the HW structure
495  *  @offset: offset of word in the EEPROM to read
496  *  @words: number of words to read
497  *  @data: word read from the EEPROM
498  *
499  *  Reads a 16 bit word from the EEPROM.
500  **/
501 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
502 			     u16 *data)
503 {
504 	struct e1000_nvm_info *nvm = &hw->nvm;
505 	u32 i = 0;
506 	s32 ret_val;
507 	u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
508 
509 	DEBUGFUNC("e1000_read_nvm_microwire");
510 
511 	/* A check for invalid values:  offset too large, too many words,
512 	 * and not enough words.
513 	 */
514 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
515 	    (words == 0)) {
516 		DEBUGOUT("nvm parameter(s) out of bounds\n");
517 		return -E1000_ERR_NVM;
518 	}
519 
520 	ret_val = nvm->ops.acquire(hw);
521 	if (ret_val)
522 		return ret_val;
523 
524 	ret_val = e1000_ready_nvm_eeprom(hw);
525 	if (ret_val)
526 		goto release;
527 
528 	for (i = 0; i < words; i++) {
529 		/* Send the READ command (opcode + addr) */
530 		e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
531 		e1000_shift_out_eec_bits(hw, (u16)(offset + i),
532 					nvm->address_bits);
533 
534 		/* Read the data.  For microwire, each word requires the
535 		 * overhead of setup and tear-down.
536 		 */
537 		data[i] = e1000_shift_in_eec_bits(hw, 16);
538 		e1000_standby_nvm(hw);
539 	}
540 
541 release:
542 	nvm->ops.release(hw);
543 
544 	return ret_val;
545 }
546 
547 /**
548  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
549  *  @hw: pointer to the HW structure
550  *  @offset: offset of word in the EEPROM to read
551  *  @words: number of words to read
552  *  @data: word read from the EEPROM
553  *
554  *  Reads a 16 bit word from the EEPROM using the EERD register.
555  **/
556 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
557 {
558 	struct e1000_nvm_info *nvm = &hw->nvm;
559 	u32 i, eerd = 0;
560 	s32 ret_val = E1000_SUCCESS;
561 
562 	DEBUGFUNC("e1000_read_nvm_eerd");
563 
564 	/* A check for invalid values:  offset too large, too many words,
565 	 * too many words for the offset, and not enough words.
566 	 */
567 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
568 	    (words == 0)) {
569 		DEBUGOUT("nvm parameter(s) out of bounds\n");
570 		return -E1000_ERR_NVM;
571 	}
572 
573 	for (i = 0; i < words; i++) {
574 		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
575 		       E1000_NVM_RW_REG_START;
576 
577 		E1000_WRITE_REG(hw, E1000_EERD, eerd);
578 		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
579 		if (ret_val)
580 			break;
581 
582 		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
583 			   E1000_NVM_RW_REG_DATA);
584 	}
585 
586 	if (ret_val)
587 		DEBUGOUT1("NVM read error: %d\n", ret_val);
588 
589 	return ret_val;
590 }
591 
592 /**
593  *  e1000_write_nvm_spi - Write to EEPROM using SPI
594  *  @hw: pointer to the HW structure
595  *  @offset: offset within the EEPROM to be written to
596  *  @words: number of words to write
597  *  @data: 16 bit word(s) to be written to the EEPROM
598  *
599  *  Writes data to EEPROM at offset using SPI interface.
600  *
601  *  If e1000_update_nvm_checksum is not called after this function , the
602  *  EEPROM will most likely contain an invalid checksum.
603  **/
604 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
605 {
606 	struct e1000_nvm_info *nvm = &hw->nvm;
607 	s32 ret_val = -E1000_ERR_NVM;
608 	u16 widx = 0;
609 
610 	DEBUGFUNC("e1000_write_nvm_spi");
611 
612 	/* A check for invalid values:  offset too large, too many words,
613 	 * and not enough words.
614 	 */
615 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
616 	    (words == 0)) {
617 		DEBUGOUT("nvm parameter(s) out of bounds\n");
618 		return -E1000_ERR_NVM;
619 	}
620 
621 	while (widx < words) {
622 		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
623 
624 		ret_val = nvm->ops.acquire(hw);
625 		if (ret_val)
626 			return ret_val;
627 
628 		ret_val = e1000_ready_nvm_eeprom(hw);
629 		if (ret_val) {
630 			nvm->ops.release(hw);
631 			return ret_val;
632 		}
633 
634 		e1000_standby_nvm(hw);
635 
636 		/* Send the WRITE ENABLE command (8 bit opcode) */
637 		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
638 					 nvm->opcode_bits);
639 
640 		e1000_standby_nvm(hw);
641 
642 		/* Some SPI eeproms use the 8th address bit embedded in the
643 		 * opcode
644 		 */
645 		if ((nvm->address_bits == 8) && (offset >= 128))
646 			write_opcode |= NVM_A8_OPCODE_SPI;
647 
648 		/* Send the Write command (8-bit opcode + addr) */
649 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
650 		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
651 					 nvm->address_bits);
652 
653 		/* Loop to allow for up to whole page write of eeprom */
654 		while (widx < words) {
655 			u16 word_out = data[widx];
656 			word_out = (word_out >> 8) | (word_out << 8);
657 			e1000_shift_out_eec_bits(hw, word_out, 16);
658 			widx++;
659 
660 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
661 				e1000_standby_nvm(hw);
662 				break;
663 			}
664 		}
665 		msec_delay(10);
666 		nvm->ops.release(hw);
667 	}
668 
669 	return ret_val;
670 }
671 
672 /**
673  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
674  *  @hw: pointer to the HW structure
675  *  @offset: offset within the EEPROM to be written to
676  *  @words: number of words to write
677  *  @data: 16 bit word(s) to be written to the EEPROM
678  *
679  *  Writes data to EEPROM at offset using microwire interface.
680  *
681  *  If e1000_update_nvm_checksum is not called after this function , the
682  *  EEPROM will most likely contain an invalid checksum.
683  **/
684 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
685 			      u16 *data)
686 {
687 	struct e1000_nvm_info *nvm = &hw->nvm;
688 	s32  ret_val;
689 	u32 eecd;
690 	u16 words_written = 0;
691 	u16 widx = 0;
692 
693 	DEBUGFUNC("e1000_write_nvm_microwire");
694 
695 	/* A check for invalid values:  offset too large, too many words,
696 	 * and not enough words.
697 	 */
698 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
699 	    (words == 0)) {
700 		DEBUGOUT("nvm parameter(s) out of bounds\n");
701 		return -E1000_ERR_NVM;
702 	}
703 
704 	ret_val = nvm->ops.acquire(hw);
705 	if (ret_val)
706 		return ret_val;
707 
708 	ret_val = e1000_ready_nvm_eeprom(hw);
709 	if (ret_val)
710 		goto release;
711 
712 	e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
713 				 (u16)(nvm->opcode_bits + 2));
714 
715 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
716 
717 	e1000_standby_nvm(hw);
718 
719 	while (words_written < words) {
720 		e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
721 					 nvm->opcode_bits);
722 
723 		e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
724 					 nvm->address_bits);
725 
726 		e1000_shift_out_eec_bits(hw, data[words_written], 16);
727 
728 		e1000_standby_nvm(hw);
729 
730 		for (widx = 0; widx < 200; widx++) {
731 			eecd = E1000_READ_REG(hw, E1000_EECD);
732 			if (eecd & E1000_EECD_DO)
733 				break;
734 			usec_delay(50);
735 		}
736 
737 		if (widx == 200) {
738 			DEBUGOUT("NVM Write did not complete\n");
739 			ret_val = -E1000_ERR_NVM;
740 			goto release;
741 		}
742 
743 		e1000_standby_nvm(hw);
744 
745 		words_written++;
746 	}
747 
748 	e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
749 				 (u16)(nvm->opcode_bits + 2));
750 
751 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
752 
753 release:
754 	nvm->ops.release(hw);
755 
756 	return ret_val;
757 }
758 
759 /**
760  *  e1000_read_pba_string_generic - Read device part number
761  *  @hw: pointer to the HW structure
762  *  @pba_num: pointer to device part number
763  *  @pba_num_size: size of part number buffer
764  *
765  *  Reads the product board assembly (PBA) number from the EEPROM and stores
766  *  the value in pba_num.
767  **/
768 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
769 				  u32 pba_num_size)
770 {
771 	s32 ret_val;
772 	u16 nvm_data;
773 	u16 pba_ptr;
774 	u16 offset;
775 	u16 length;
776 
777 	DEBUGFUNC("e1000_read_pba_string_generic");
778 
779 	if ((hw->mac.type == e1000_i210 ||
780 	     hw->mac.type == e1000_i211) &&
781 	     !e1000_get_flash_presence_i210(hw)) {
782 		DEBUGOUT("Flashless no PBA string\n");
783 		return -E1000_ERR_NVM_PBA_SECTION;
784 	}
785 
786 	if (pba_num == NULL) {
787 		DEBUGOUT("PBA string buffer was null\n");
788 		return -E1000_ERR_INVALID_ARGUMENT;
789 	}
790 
791 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
792 	if (ret_val) {
793 		DEBUGOUT("NVM Read Error\n");
794 		return ret_val;
795 	}
796 
797 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
798 	if (ret_val) {
799 		DEBUGOUT("NVM Read Error\n");
800 		return ret_val;
801 	}
802 
803 	/* if nvm_data is not ptr guard the PBA must be in legacy format which
804 	 * means pba_ptr is actually our second data word for the PBA number
805 	 * and we can decode it into an ascii string
806 	 */
807 	if (nvm_data != NVM_PBA_PTR_GUARD) {
808 		DEBUGOUT("NVM PBA number is not stored as string\n");
809 
810 		/* make sure callers buffer is big enough to store the PBA */
811 		if (pba_num_size < E1000_PBANUM_LENGTH) {
812 			DEBUGOUT("PBA string buffer too small\n");
813 			return E1000_ERR_NO_SPACE;
814 		}
815 
816 		/* extract hex string from data and pba_ptr */
817 		pba_num[0] = (nvm_data >> 12) & 0xF;
818 		pba_num[1] = (nvm_data >> 8) & 0xF;
819 		pba_num[2] = (nvm_data >> 4) & 0xF;
820 		pba_num[3] = nvm_data & 0xF;
821 		pba_num[4] = (pba_ptr >> 12) & 0xF;
822 		pba_num[5] = (pba_ptr >> 8) & 0xF;
823 		pba_num[6] = '-';
824 		pba_num[7] = 0;
825 		pba_num[8] = (pba_ptr >> 4) & 0xF;
826 		pba_num[9] = pba_ptr & 0xF;
827 
828 		/* put a null character on the end of our string */
829 		pba_num[10] = '\0';
830 
831 		/* switch all the data but the '-' to hex char */
832 		for (offset = 0; offset < 10; offset++) {
833 			if (pba_num[offset] < 0xA)
834 				pba_num[offset] += '0';
835 			else if (pba_num[offset] < 0x10)
836 				pba_num[offset] += 'A' - 0xA;
837 		}
838 
839 		return E1000_SUCCESS;
840 	}
841 
842 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
843 	if (ret_val) {
844 		DEBUGOUT("NVM Read Error\n");
845 		return ret_val;
846 	}
847 
848 	if (length == 0xFFFF || length == 0) {
849 		DEBUGOUT("NVM PBA number section invalid length\n");
850 		return -E1000_ERR_NVM_PBA_SECTION;
851 	}
852 	/* check if pba_num buffer is big enough */
853 	if (pba_num_size < (((u32)length * 2) - 1)) {
854 		DEBUGOUT("PBA string buffer too small\n");
855 		return -E1000_ERR_NO_SPACE;
856 	}
857 
858 	/* trim pba length from start of string */
859 	pba_ptr++;
860 	length--;
861 
862 	for (offset = 0; offset < length; offset++) {
863 		ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
864 		if (ret_val) {
865 			DEBUGOUT("NVM Read Error\n");
866 			return ret_val;
867 		}
868 		pba_num[offset * 2] = (u8)(nvm_data >> 8);
869 		pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
870 	}
871 	pba_num[offset * 2] = '\0';
872 
873 	return E1000_SUCCESS;
874 }
875 
876 /**
877  *  e1000_read_pba_length_generic - Read device part number length
878  *  @hw: pointer to the HW structure
879  *  @pba_num_size: size of part number buffer
880  *
881  *  Reads the product board assembly (PBA) number length from the EEPROM and
882  *  stores the value in pba_num_size.
883  **/
884 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
885 {
886 	s32 ret_val;
887 	u16 nvm_data;
888 	u16 pba_ptr;
889 	u16 length;
890 
891 	DEBUGFUNC("e1000_read_pba_length_generic");
892 
893 	if (pba_num_size == NULL) {
894 		DEBUGOUT("PBA buffer size was null\n");
895 		return -E1000_ERR_INVALID_ARGUMENT;
896 	}
897 
898 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
899 	if (ret_val) {
900 		DEBUGOUT("NVM Read Error\n");
901 		return ret_val;
902 	}
903 
904 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
905 	if (ret_val) {
906 		DEBUGOUT("NVM Read Error\n");
907 		return ret_val;
908 	}
909 
910 	 /* if data is not ptr guard the PBA must be in legacy format */
911 	if (nvm_data != NVM_PBA_PTR_GUARD) {
912 		*pba_num_size = E1000_PBANUM_LENGTH;
913 		return E1000_SUCCESS;
914 	}
915 
916 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
917 	if (ret_val) {
918 		DEBUGOUT("NVM Read Error\n");
919 		return ret_val;
920 	}
921 
922 	if (length == 0xFFFF || length == 0) {
923 		DEBUGOUT("NVM PBA number section invalid length\n");
924 		return -E1000_ERR_NVM_PBA_SECTION;
925 	}
926 
927 	/* Convert from length in u16 values to u8 chars, add 1 for NULL,
928 	 * and subtract 2 because length field is included in length.
929 	 */
930 	*pba_num_size = ((u32)length * 2) - 1;
931 
932 	return E1000_SUCCESS;
933 }
934 
935 
936 /**
937  *  e1000_read_pba_raw
938  *  @hw: pointer to the HW structure
939  *  @eeprom_buf: optional pointer to EEPROM image
940  *  @eeprom_buf_size: size of EEPROM image in words
941  *  @max_pba_block_size: PBA block size limit
942  *  @pba: pointer to output PBA structure
943  *
944  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
945  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
946  *
947  **/
948 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
949 		       u32 eeprom_buf_size, u16 max_pba_block_size,
950 		       struct e1000_pba *pba)
951 {
952 	s32 ret_val;
953 	u16 pba_block_size;
954 
955 	if (pba == NULL)
956 		return -E1000_ERR_PARAM;
957 
958 	if (eeprom_buf == NULL) {
959 		ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
960 					 &pba->word[0]);
961 		if (ret_val)
962 			return ret_val;
963 	} else {
964 		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
965 			pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
966 			pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
967 		} else {
968 			return -E1000_ERR_PARAM;
969 		}
970 	}
971 
972 	if (pba->word[0] == NVM_PBA_PTR_GUARD) {
973 		if (pba->pba_block == NULL)
974 			return -E1000_ERR_PARAM;
975 
976 		ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
977 						   eeprom_buf_size,
978 						   &pba_block_size);
979 		if (ret_val)
980 			return ret_val;
981 
982 		if (pba_block_size > max_pba_block_size)
983 			return -E1000_ERR_PARAM;
984 
985 		if (eeprom_buf == NULL) {
986 			ret_val = e1000_read_nvm(hw, pba->word[1],
987 						 pba_block_size,
988 						 pba->pba_block);
989 			if (ret_val)
990 				return ret_val;
991 		} else {
992 			if (eeprom_buf_size > (u32)(pba->word[1] +
993 					      pba_block_size)) {
994 				memcpy(pba->pba_block,
995 				       &eeprom_buf[pba->word[1]],
996 				       pba_block_size * sizeof(u16));
997 			} else {
998 				return -E1000_ERR_PARAM;
999 			}
1000 		}
1001 	}
1002 
1003 	return E1000_SUCCESS;
1004 }
1005 
1006 /**
1007  *  e1000_write_pba_raw
1008  *  @hw: pointer to the HW structure
1009  *  @eeprom_buf: optional pointer to EEPROM image
1010  *  @eeprom_buf_size: size of EEPROM image in words
1011  *  @pba: pointer to PBA structure
1012  *
1013  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1014  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1015  *
1016  **/
1017 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1018 			u32 eeprom_buf_size, struct e1000_pba *pba)
1019 {
1020 	s32 ret_val;
1021 
1022 	if (pba == NULL)
1023 		return -E1000_ERR_PARAM;
1024 
1025 	if (eeprom_buf == NULL) {
1026 		ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1027 					  &pba->word[0]);
1028 		if (ret_val)
1029 			return ret_val;
1030 	} else {
1031 		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1032 			eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1033 			eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1034 		} else {
1035 			return -E1000_ERR_PARAM;
1036 		}
1037 	}
1038 
1039 	if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1040 		if (pba->pba_block == NULL)
1041 			return -E1000_ERR_PARAM;
1042 
1043 		if (eeprom_buf == NULL) {
1044 			ret_val = e1000_write_nvm(hw, pba->word[1],
1045 						  pba->pba_block[0],
1046 						  pba->pba_block);
1047 			if (ret_val)
1048 				return ret_val;
1049 		} else {
1050 			if (eeprom_buf_size > (u32)(pba->word[1] +
1051 					      pba->pba_block[0])) {
1052 				memcpy(&eeprom_buf[pba->word[1]],
1053 				       pba->pba_block,
1054 				       pba->pba_block[0] * sizeof(u16));
1055 			} else {
1056 				return -E1000_ERR_PARAM;
1057 			}
1058 		}
1059 	}
1060 
1061 	return E1000_SUCCESS;
1062 }
1063 
1064 /**
1065  *  e1000_get_pba_block_size
1066  *  @hw: pointer to the HW structure
1067  *  @eeprom_buf: optional pointer to EEPROM image
1068  *  @eeprom_buf_size: size of EEPROM image in words
1069  *  @pba_data_size: pointer to output variable
1070  *
1071  *  Returns the size of the PBA block in words. Function operates on EEPROM
1072  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1073  *  EEPROM device.
1074  *
1075  **/
1076 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1077 			     u32 eeprom_buf_size, u16 *pba_block_size)
1078 {
1079 	s32 ret_val;
1080 	u16 pba_word[2];
1081 	u16 length;
1082 
1083 	DEBUGFUNC("e1000_get_pba_block_size");
1084 
1085 	if (eeprom_buf == NULL) {
1086 		ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1087 		if (ret_val)
1088 			return ret_val;
1089 	} else {
1090 		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1091 			pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1092 			pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1093 		} else {
1094 			return -E1000_ERR_PARAM;
1095 		}
1096 	}
1097 
1098 	if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1099 		if (eeprom_buf == NULL) {
1100 			ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1101 						 &length);
1102 			if (ret_val)
1103 				return ret_val;
1104 		} else {
1105 			if (eeprom_buf_size > pba_word[1])
1106 				length = eeprom_buf[pba_word[1] + 0];
1107 			else
1108 				return -E1000_ERR_PARAM;
1109 		}
1110 
1111 		if (length == 0xFFFF || length == 0)
1112 			return -E1000_ERR_NVM_PBA_SECTION;
1113 	} else {
1114 		/* PBA number in legacy format, there is no PBA Block. */
1115 		length = 0;
1116 	}
1117 
1118 	if (pba_block_size != NULL)
1119 		*pba_block_size = length;
1120 
1121 	return E1000_SUCCESS;
1122 }
1123 
1124 /**
1125  *  e1000_read_mac_addr_generic - Read device MAC address
1126  *  @hw: pointer to the HW structure
1127  *
1128  *  Reads the device MAC address from the EEPROM and stores the value.
1129  *  Since devices with two ports use the same EEPROM, we increment the
1130  *  last bit in the MAC address for the second port.
1131  **/
1132 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1133 {
1134 	u32 rar_high;
1135 	u32 rar_low;
1136 	u16 i;
1137 
1138 	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1139 	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1140 
1141 	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1142 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1143 
1144 	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1145 		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1146 
1147 	for (i = 0; i < ETHER_ADDR_LEN; i++)
1148 		hw->mac.addr[i] = hw->mac.perm_addr[i];
1149 
1150 	return E1000_SUCCESS;
1151 }
1152 
1153 /**
1154  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1155  *  @hw: pointer to the HW structure
1156  *
1157  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1158  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1159  **/
1160 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1161 {
1162 	s32 ret_val;
1163 	u16 checksum = 0;
1164 	u16 i, nvm_data;
1165 
1166 	DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1167 
1168 	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1169 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1170 		if (ret_val) {
1171 			DEBUGOUT("NVM Read Error\n");
1172 			return ret_val;
1173 		}
1174 		checksum += nvm_data;
1175 	}
1176 
1177 	if (checksum != (u16) NVM_SUM) {
1178 		DEBUGOUT("NVM Checksum Invalid\n");
1179 		return -E1000_ERR_NVM;
1180 	}
1181 
1182 	return E1000_SUCCESS;
1183 }
1184 
1185 /**
1186  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1187  *  @hw: pointer to the HW structure
1188  *
1189  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1190  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1191  *  value to the EEPROM.
1192  **/
1193 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1194 {
1195 	s32 ret_val;
1196 	u16 checksum = 0;
1197 	u16 i, nvm_data;
1198 
1199 	DEBUGFUNC("e1000_update_nvm_checksum");
1200 
1201 	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1202 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1203 		if (ret_val) {
1204 			DEBUGOUT("NVM Read Error while updating checksum.\n");
1205 			return ret_val;
1206 		}
1207 		checksum += nvm_data;
1208 	}
1209 	checksum = (u16) NVM_SUM - checksum;
1210 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1211 	if (ret_val)
1212 		DEBUGOUT("NVM Write Error while updating checksum.\n");
1213 
1214 	return ret_val;
1215 }
1216 
1217 /**
1218  *  e1000_reload_nvm_generic - Reloads EEPROM
1219  *  @hw: pointer to the HW structure
1220  *
1221  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1222  *  extended control register.
1223  **/
1224 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1225 {
1226 	u32 ctrl_ext;
1227 
1228 	DEBUGFUNC("e1000_reload_nvm_generic");
1229 
1230 	usec_delay(10);
1231 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1232 	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1233 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1234 	E1000_WRITE_FLUSH(hw);
1235 }
1236 
1237 
1238