1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 /** 38 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 39 * @hw: pointer to the HW structure 40 * 41 * Setups up the function pointers to no-op functions 42 **/ 43 void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 44 { 45 struct e1000_nvm_info *nvm = &hw->nvm; 46 DEBUGFUNC("e1000_init_nvm_ops_generic"); 47 48 /* Initialize function pointers */ 49 nvm->ops.init_params = e1000_null_ops_generic; 50 nvm->ops.acquire = e1000_null_ops_generic; 51 nvm->ops.read = e1000_null_read_nvm; 52 nvm->ops.release = e1000_null_nvm_generic; 53 nvm->ops.reload = e1000_reload_nvm_generic; 54 nvm->ops.update = e1000_null_ops_generic; 55 nvm->ops.valid_led_default = e1000_null_led_default; 56 nvm->ops.validate = e1000_null_ops_generic; 57 nvm->ops.write = e1000_null_write_nvm; 58 } 59 60 /** 61 * e1000_null_nvm_read - No-op function, return 0 62 * @hw: pointer to the HW structure 63 **/ 64 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 65 { 66 DEBUGFUNC("e1000_null_read_nvm"); 67 return E1000_SUCCESS; 68 } 69 70 /** 71 * e1000_null_nvm_generic - No-op function, return void 72 * @hw: pointer to the HW structure 73 **/ 74 void e1000_null_nvm_generic(struct e1000_hw *hw) 75 { 76 DEBUGFUNC("e1000_null_nvm_generic"); 77 return; 78 } 79 80 /** 81 * e1000_null_led_default - No-op function, return 0 82 * @hw: pointer to the HW structure 83 **/ 84 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data) 85 { 86 DEBUGFUNC("e1000_null_led_default"); 87 return E1000_SUCCESS; 88 } 89 90 /** 91 * e1000_null_write_nvm - No-op function, return 0 92 * @hw: pointer to the HW structure 93 **/ 94 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 95 { 96 DEBUGFUNC("e1000_null_write_nvm"); 97 return E1000_SUCCESS; 98 } 99 100 /** 101 * e1000_raise_eec_clk - Raise EEPROM clock 102 * @hw: pointer to the HW structure 103 * @eecd: pointer to the EEPROM 104 * 105 * Enable/Raise the EEPROM clock bit. 106 **/ 107 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 108 { 109 *eecd = *eecd | E1000_EECD_SK; 110 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 111 E1000_WRITE_FLUSH(hw); 112 usec_delay(hw->nvm.delay_usec); 113 } 114 115 /** 116 * e1000_lower_eec_clk - Lower EEPROM clock 117 * @hw: pointer to the HW structure 118 * @eecd: pointer to the EEPROM 119 * 120 * Clear/Lower the EEPROM clock bit. 121 **/ 122 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 123 { 124 *eecd = *eecd & ~E1000_EECD_SK; 125 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 126 E1000_WRITE_FLUSH(hw); 127 usec_delay(hw->nvm.delay_usec); 128 } 129 130 /** 131 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 132 * @hw: pointer to the HW structure 133 * @data: data to send to the EEPROM 134 * @count: number of bits to shift out 135 * 136 * We need to shift 'count' bits out to the EEPROM. So, the value in the 137 * "data" parameter will be shifted out to the EEPROM one bit at a time. 138 * In order to do this, "data" must be broken down into bits. 139 **/ 140 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 141 { 142 struct e1000_nvm_info *nvm = &hw->nvm; 143 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 144 u32 mask; 145 146 DEBUGFUNC("e1000_shift_out_eec_bits"); 147 148 mask = 0x01 << (count - 1); 149 if (nvm->type == e1000_nvm_eeprom_microwire) 150 eecd &= ~E1000_EECD_DO; 151 else if (nvm->type == e1000_nvm_eeprom_spi) 152 eecd |= E1000_EECD_DO; 153 154 do { 155 eecd &= ~E1000_EECD_DI; 156 157 if (data & mask) 158 eecd |= E1000_EECD_DI; 159 160 E1000_WRITE_REG(hw, E1000_EECD, eecd); 161 E1000_WRITE_FLUSH(hw); 162 163 usec_delay(nvm->delay_usec); 164 165 e1000_raise_eec_clk(hw, &eecd); 166 e1000_lower_eec_clk(hw, &eecd); 167 168 mask >>= 1; 169 } while (mask); 170 171 eecd &= ~E1000_EECD_DI; 172 E1000_WRITE_REG(hw, E1000_EECD, eecd); 173 } 174 175 /** 176 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 177 * @hw: pointer to the HW structure 178 * @count: number of bits to shift in 179 * 180 * In order to read a register from the EEPROM, we need to shift 'count' bits 181 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 182 * the EEPROM (setting the SK bit), and then reading the value of the data out 183 * "DO" bit. During this "shifting in" process the data in "DI" bit should 184 * always be clear. 185 **/ 186 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 187 { 188 u32 eecd; 189 u32 i; 190 u16 data; 191 192 DEBUGFUNC("e1000_shift_in_eec_bits"); 193 194 eecd = E1000_READ_REG(hw, E1000_EECD); 195 196 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 197 data = 0; 198 199 for (i = 0; i < count; i++) { 200 data <<= 1; 201 e1000_raise_eec_clk(hw, &eecd); 202 203 eecd = E1000_READ_REG(hw, E1000_EECD); 204 205 eecd &= ~E1000_EECD_DI; 206 if (eecd & E1000_EECD_DO) 207 data |= 1; 208 209 e1000_lower_eec_clk(hw, &eecd); 210 } 211 212 return data; 213 } 214 215 /** 216 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 217 * @hw: pointer to the HW structure 218 * @ee_reg: EEPROM flag for polling 219 * 220 * Polls the EEPROM status bit for either read or write completion based 221 * upon the value of 'ee_reg'. 222 **/ 223 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 224 { 225 u32 attempts = 100000; 226 u32 i, reg = 0; 227 s32 ret_val = -E1000_ERR_NVM; 228 229 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 230 231 for (i = 0; i < attempts; i++) { 232 if (ee_reg == E1000_NVM_POLL_READ) 233 reg = E1000_READ_REG(hw, E1000_EERD); 234 else 235 reg = E1000_READ_REG(hw, E1000_EEWR); 236 237 if (reg & E1000_NVM_RW_REG_DONE) { 238 ret_val = E1000_SUCCESS; 239 break; 240 } 241 242 usec_delay(5); 243 } 244 245 return ret_val; 246 } 247 248 /** 249 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 250 * @hw: pointer to the HW structure 251 * 252 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 253 * Return successful if access grant bit set, else clear the request for 254 * EEPROM access and return -E1000_ERR_NVM (-1). 255 **/ 256 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 257 { 258 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 259 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 260 s32 ret_val = E1000_SUCCESS; 261 262 DEBUGFUNC("e1000_acquire_nvm_generic"); 263 264 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 265 eecd = E1000_READ_REG(hw, E1000_EECD); 266 267 while (timeout) { 268 if (eecd & E1000_EECD_GNT) 269 break; 270 usec_delay(5); 271 eecd = E1000_READ_REG(hw, E1000_EECD); 272 timeout--; 273 } 274 275 if (!timeout) { 276 eecd &= ~E1000_EECD_REQ; 277 E1000_WRITE_REG(hw, E1000_EECD, eecd); 278 DEBUGOUT("Could not acquire NVM grant\n"); 279 ret_val = -E1000_ERR_NVM; 280 } 281 282 return ret_val; 283 } 284 285 /** 286 * e1000_standby_nvm - Return EEPROM to standby state 287 * @hw: pointer to the HW structure 288 * 289 * Return the EEPROM to a standby state. 290 **/ 291 static void e1000_standby_nvm(struct e1000_hw *hw) 292 { 293 struct e1000_nvm_info *nvm = &hw->nvm; 294 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 295 296 DEBUGFUNC("e1000_standby_nvm"); 297 298 if (nvm->type == e1000_nvm_eeprom_microwire) { 299 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 300 E1000_WRITE_REG(hw, E1000_EECD, eecd); 301 E1000_WRITE_FLUSH(hw); 302 usec_delay(nvm->delay_usec); 303 304 e1000_raise_eec_clk(hw, &eecd); 305 306 /* Select EEPROM */ 307 eecd |= E1000_EECD_CS; 308 E1000_WRITE_REG(hw, E1000_EECD, eecd); 309 E1000_WRITE_FLUSH(hw); 310 usec_delay(nvm->delay_usec); 311 312 e1000_lower_eec_clk(hw, &eecd); 313 } else if (nvm->type == e1000_nvm_eeprom_spi) { 314 /* Toggle CS to flush commands */ 315 eecd |= E1000_EECD_CS; 316 E1000_WRITE_REG(hw, E1000_EECD, eecd); 317 E1000_WRITE_FLUSH(hw); 318 usec_delay(nvm->delay_usec); 319 eecd &= ~E1000_EECD_CS; 320 E1000_WRITE_REG(hw, E1000_EECD, eecd); 321 E1000_WRITE_FLUSH(hw); 322 usec_delay(nvm->delay_usec); 323 } 324 } 325 326 /** 327 * e1000_stop_nvm - Terminate EEPROM command 328 * @hw: pointer to the HW structure 329 * 330 * Terminates the current command by inverting the EEPROM's chip select pin. 331 **/ 332 void e1000_stop_nvm(struct e1000_hw *hw) 333 { 334 u32 eecd; 335 336 DEBUGFUNC("e1000_stop_nvm"); 337 338 eecd = E1000_READ_REG(hw, E1000_EECD); 339 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 340 /* Pull CS high */ 341 eecd |= E1000_EECD_CS; 342 e1000_lower_eec_clk(hw, &eecd); 343 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 344 /* CS on Microwire is active-high */ 345 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 346 E1000_WRITE_REG(hw, E1000_EECD, eecd); 347 e1000_raise_eec_clk(hw, &eecd); 348 e1000_lower_eec_clk(hw, &eecd); 349 } 350 } 351 352 /** 353 * e1000_release_nvm_generic - Release exclusive access to EEPROM 354 * @hw: pointer to the HW structure 355 * 356 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 357 **/ 358 void e1000_release_nvm_generic(struct e1000_hw *hw) 359 { 360 u32 eecd; 361 362 DEBUGFUNC("e1000_release_nvm_generic"); 363 364 e1000_stop_nvm(hw); 365 366 eecd = E1000_READ_REG(hw, E1000_EECD); 367 eecd &= ~E1000_EECD_REQ; 368 E1000_WRITE_REG(hw, E1000_EECD, eecd); 369 } 370 371 /** 372 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 373 * @hw: pointer to the HW structure 374 * 375 * Setups the EEPROM for reading and writing. 376 **/ 377 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 378 { 379 struct e1000_nvm_info *nvm = &hw->nvm; 380 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 381 s32 ret_val = E1000_SUCCESS; 382 u16 timeout = 0; 383 u8 spi_stat_reg; 384 385 DEBUGFUNC("e1000_ready_nvm_eeprom"); 386 387 if (nvm->type == e1000_nvm_eeprom_microwire) { 388 /* Clear SK and DI */ 389 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 390 E1000_WRITE_REG(hw, E1000_EECD, eecd); 391 /* Set CS */ 392 eecd |= E1000_EECD_CS; 393 E1000_WRITE_REG(hw, E1000_EECD, eecd); 394 } else if (nvm->type == e1000_nvm_eeprom_spi) { 395 /* Clear SK and CS */ 396 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 397 E1000_WRITE_REG(hw, E1000_EECD, eecd); 398 usec_delay(1); 399 timeout = NVM_MAX_RETRY_SPI; 400 401 /* 402 * Read "Status Register" repeatedly until the LSB is cleared. 403 * The EEPROM will signal that the command has been completed 404 * by clearing bit 0 of the internal status register. If it's 405 * not cleared within 'timeout', then error out. 406 */ 407 while (timeout) { 408 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 409 hw->nvm.opcode_bits); 410 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 411 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 412 break; 413 414 usec_delay(5); 415 e1000_standby_nvm(hw); 416 timeout--; 417 } 418 419 if (!timeout) { 420 DEBUGOUT("SPI NVM Status error\n"); 421 ret_val = -E1000_ERR_NVM; 422 goto out; 423 } 424 } 425 426 out: 427 return ret_val; 428 } 429 430 /** 431 * e1000_read_nvm_spi - Read EEPROM's using SPI 432 * @hw: pointer to the HW structure 433 * @offset: offset of word in the EEPROM to read 434 * @words: number of words to read 435 * @data: word read from the EEPROM 436 * 437 * Reads a 16 bit word from the EEPROM. 438 **/ 439 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 440 { 441 struct e1000_nvm_info *nvm = &hw->nvm; 442 u32 i = 0; 443 s32 ret_val; 444 u16 word_in; 445 u8 read_opcode = NVM_READ_OPCODE_SPI; 446 447 DEBUGFUNC("e1000_read_nvm_spi"); 448 449 /* 450 * A check for invalid values: offset too large, too many words, 451 * and not enough words. 452 */ 453 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 454 (words == 0)) { 455 DEBUGOUT("nvm parameter(s) out of bounds\n"); 456 ret_val = -E1000_ERR_NVM; 457 goto out; 458 } 459 460 ret_val = nvm->ops.acquire(hw); 461 if (ret_val) 462 goto out; 463 464 ret_val = e1000_ready_nvm_eeprom(hw); 465 if (ret_val) 466 goto release; 467 468 e1000_standby_nvm(hw); 469 470 if ((nvm->address_bits == 8) && (offset >= 128)) 471 read_opcode |= NVM_A8_OPCODE_SPI; 472 473 /* Send the READ command (opcode + addr) */ 474 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 475 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 476 477 /* 478 * Read the data. SPI NVMs increment the address with each byte 479 * read and will roll over if reading beyond the end. This allows 480 * us to read the whole NVM from any offset 481 */ 482 for (i = 0; i < words; i++) { 483 word_in = e1000_shift_in_eec_bits(hw, 16); 484 data[i] = (word_in >> 8) | (word_in << 8); 485 } 486 487 release: 488 nvm->ops.release(hw); 489 490 out: 491 return ret_val; 492 } 493 494 /** 495 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 496 * @hw: pointer to the HW structure 497 * @offset: offset of word in the EEPROM to read 498 * @words: number of words to read 499 * @data: word read from the EEPROM 500 * 501 * Reads a 16 bit word from the EEPROM. 502 **/ 503 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 504 u16 *data) 505 { 506 struct e1000_nvm_info *nvm = &hw->nvm; 507 u32 i = 0; 508 s32 ret_val; 509 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 510 511 DEBUGFUNC("e1000_read_nvm_microwire"); 512 513 /* 514 * A check for invalid values: offset too large, too many words, 515 * and not enough words. 516 */ 517 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 518 (words == 0)) { 519 DEBUGOUT("nvm parameter(s) out of bounds\n"); 520 ret_val = -E1000_ERR_NVM; 521 goto out; 522 } 523 524 ret_val = nvm->ops.acquire(hw); 525 if (ret_val) 526 goto out; 527 528 ret_val = e1000_ready_nvm_eeprom(hw); 529 if (ret_val) 530 goto release; 531 532 for (i = 0; i < words; i++) { 533 /* Send the READ command (opcode + addr) */ 534 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 535 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 536 nvm->address_bits); 537 538 /* 539 * Read the data. For microwire, each word requires the 540 * overhead of setup and tear-down. 541 */ 542 data[i] = e1000_shift_in_eec_bits(hw, 16); 543 e1000_standby_nvm(hw); 544 } 545 546 release: 547 nvm->ops.release(hw); 548 549 out: 550 return ret_val; 551 } 552 553 /** 554 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 555 * @hw: pointer to the HW structure 556 * @offset: offset of word in the EEPROM to read 557 * @words: number of words to read 558 * @data: word read from the EEPROM 559 * 560 * Reads a 16 bit word from the EEPROM using the EERD register. 561 **/ 562 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 563 { 564 struct e1000_nvm_info *nvm = &hw->nvm; 565 u32 i, eerd = 0; 566 s32 ret_val = E1000_SUCCESS; 567 568 DEBUGFUNC("e1000_read_nvm_eerd"); 569 570 /* 571 * A check for invalid values: offset too large, too many words, 572 * too many words for the offset, and not enough words. 573 */ 574 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 575 (words == 0)) { 576 DEBUGOUT("nvm parameter(s) out of bounds\n"); 577 ret_val = -E1000_ERR_NVM; 578 goto out; 579 } 580 581 for (i = 0; i < words; i++) { 582 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 583 E1000_NVM_RW_REG_START; 584 585 E1000_WRITE_REG(hw, E1000_EERD, eerd); 586 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 587 if (ret_val) 588 break; 589 590 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 591 E1000_NVM_RW_REG_DATA); 592 } 593 594 out: 595 return ret_val; 596 } 597 598 /** 599 * e1000_write_nvm_spi - Write to EEPROM using SPI 600 * @hw: pointer to the HW structure 601 * @offset: offset within the EEPROM to be written to 602 * @words: number of words to write 603 * @data: 16 bit word(s) to be written to the EEPROM 604 * 605 * Writes data to EEPROM at offset using SPI interface. 606 * 607 * If e1000_update_nvm_checksum is not called after this function , the 608 * EEPROM will most likely contain an invalid checksum. 609 **/ 610 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 611 { 612 struct e1000_nvm_info *nvm = &hw->nvm; 613 s32 ret_val; 614 u16 widx = 0; 615 616 DEBUGFUNC("e1000_write_nvm_spi"); 617 618 /* 619 * A check for invalid values: offset too large, too many words, 620 * and not enough words. 621 */ 622 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 623 (words == 0)) { 624 DEBUGOUT("nvm parameter(s) out of bounds\n"); 625 ret_val = -E1000_ERR_NVM; 626 goto out; 627 } 628 629 ret_val = nvm->ops.acquire(hw); 630 if (ret_val) 631 goto out; 632 633 while (widx < words) { 634 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 635 636 ret_val = e1000_ready_nvm_eeprom(hw); 637 if (ret_val) 638 goto release; 639 640 e1000_standby_nvm(hw); 641 642 /* Send the WRITE ENABLE command (8 bit opcode) */ 643 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 644 nvm->opcode_bits); 645 646 e1000_standby_nvm(hw); 647 648 /* 649 * Some SPI eeproms use the 8th address bit embedded in the 650 * opcode 651 */ 652 if ((nvm->address_bits == 8) && (offset >= 128)) 653 write_opcode |= NVM_A8_OPCODE_SPI; 654 655 /* Send the Write command (8-bit opcode + addr) */ 656 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 657 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 658 nvm->address_bits); 659 660 /* Loop to allow for up to whole page write of eeprom */ 661 while (widx < words) { 662 u16 word_out = data[widx]; 663 word_out = (word_out >> 8) | (word_out << 8); 664 e1000_shift_out_eec_bits(hw, word_out, 16); 665 widx++; 666 667 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 668 e1000_standby_nvm(hw); 669 break; 670 } 671 } 672 } 673 674 msec_delay(nvm->semaphore_delay); 675 release: 676 nvm->ops.release(hw); 677 678 out: 679 return ret_val; 680 } 681 682 /** 683 * e1000_write_nvm_microwire - Writes EEPROM using microwire 684 * @hw: pointer to the HW structure 685 * @offset: offset within the EEPROM to be written to 686 * @words: number of words to write 687 * @data: 16 bit word(s) to be written to the EEPROM 688 * 689 * Writes data to EEPROM at offset using microwire interface. 690 * 691 * If e1000_update_nvm_checksum is not called after this function , the 692 * EEPROM will most likely contain an invalid checksum. 693 **/ 694 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 695 u16 *data) 696 { 697 struct e1000_nvm_info *nvm = &hw->nvm; 698 s32 ret_val; 699 u32 eecd; 700 u16 words_written = 0; 701 u16 widx = 0; 702 703 DEBUGFUNC("e1000_write_nvm_microwire"); 704 705 /* 706 * A check for invalid values: offset too large, too many words, 707 * and not enough words. 708 */ 709 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 710 (words == 0)) { 711 DEBUGOUT("nvm parameter(s) out of bounds\n"); 712 ret_val = -E1000_ERR_NVM; 713 goto out; 714 } 715 716 ret_val = nvm->ops.acquire(hw); 717 if (ret_val) 718 goto out; 719 720 ret_val = e1000_ready_nvm_eeprom(hw); 721 if (ret_val) 722 goto release; 723 724 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 725 (u16)(nvm->opcode_bits + 2)); 726 727 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 728 729 e1000_standby_nvm(hw); 730 731 while (words_written < words) { 732 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 733 nvm->opcode_bits); 734 735 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 736 nvm->address_bits); 737 738 e1000_shift_out_eec_bits(hw, data[words_written], 16); 739 740 e1000_standby_nvm(hw); 741 742 for (widx = 0; widx < 200; widx++) { 743 eecd = E1000_READ_REG(hw, E1000_EECD); 744 if (eecd & E1000_EECD_DO) 745 break; 746 usec_delay(50); 747 } 748 749 if (widx == 200) { 750 DEBUGOUT("NVM Write did not complete\n"); 751 ret_val = -E1000_ERR_NVM; 752 goto release; 753 } 754 755 e1000_standby_nvm(hw); 756 757 words_written++; 758 } 759 760 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 761 (u16)(nvm->opcode_bits + 2)); 762 763 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 764 765 release: 766 nvm->ops.release(hw); 767 768 out: 769 return ret_val; 770 } 771 772 /** 773 * e1000_read_pba_num_generic - Read device part number 774 * @hw: pointer to the HW structure 775 * @pba_num: pointer to device part number 776 * 777 * Reads the product board assembly (PBA) number from the EEPROM and stores 778 * the value in pba_num. 779 **/ 780 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) 781 { 782 s32 ret_val; 783 u16 nvm_data; 784 785 DEBUGFUNC("e1000_read_pba_num_generic"); 786 787 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 788 if (ret_val) { 789 DEBUGOUT("NVM Read Error\n"); 790 goto out; 791 } 792 *pba_num = (u32)(nvm_data << 16); 793 794 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 795 if (ret_val) { 796 DEBUGOUT("NVM Read Error\n"); 797 goto out; 798 } 799 *pba_num |= nvm_data; 800 801 out: 802 return ret_val; 803 } 804 805 /** 806 * e1000_read_mac_addr_generic - Read device MAC address 807 * @hw: pointer to the HW structure 808 * 809 * Reads the device MAC address from the EEPROM and stores the value. 810 * Since devices with two ports use the same EEPROM, we increment the 811 * last bit in the MAC address for the second port. 812 **/ 813 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 814 { 815 s32 ret_val = E1000_SUCCESS; 816 u16 offset, nvm_data, i; 817 818 DEBUGFUNC("e1000_read_mac_addr"); 819 820 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 821 offset = i >> 1; 822 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 823 if (ret_val) { 824 DEBUGOUT("NVM Read Error\n"); 825 goto out; 826 } 827 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 828 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 829 } 830 831 /* Flip last bit of mac address if we're on second port */ 832 if (hw->bus.func == E1000_FUNC_1) 833 hw->mac.perm_addr[5] ^= 1; 834 835 for (i = 0; i < ETH_ADDR_LEN; i++) 836 hw->mac.addr[i] = hw->mac.perm_addr[i]; 837 838 out: 839 return ret_val; 840 } 841 842 /** 843 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 844 * @hw: pointer to the HW structure 845 * 846 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 847 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 848 **/ 849 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 850 { 851 s32 ret_val = E1000_SUCCESS; 852 u16 checksum = 0; 853 u16 i, nvm_data; 854 855 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 856 857 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 858 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 859 if (ret_val) { 860 DEBUGOUT("NVM Read Error\n"); 861 goto out; 862 } 863 checksum += nvm_data; 864 } 865 866 if (checksum != (u16) NVM_SUM) { 867 DEBUGOUT("NVM Checksum Invalid\n"); 868 ret_val = -E1000_ERR_NVM; 869 goto out; 870 } 871 872 out: 873 return ret_val; 874 } 875 876 /** 877 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 878 * @hw: pointer to the HW structure 879 * 880 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 881 * up to the checksum. Then calculates the EEPROM checksum and writes the 882 * value to the EEPROM. 883 **/ 884 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 885 { 886 s32 ret_val; 887 u16 checksum = 0; 888 u16 i, nvm_data; 889 890 DEBUGFUNC("e1000_update_nvm_checksum"); 891 892 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 893 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 894 if (ret_val) { 895 DEBUGOUT("NVM Read Error while updating checksum.\n"); 896 goto out; 897 } 898 checksum += nvm_data; 899 } 900 checksum = (u16) NVM_SUM - checksum; 901 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 902 if (ret_val) { 903 DEBUGOUT("NVM Write Error while updating checksum.\n"); 904 } 905 906 out: 907 return ret_val; 908 } 909 910 /** 911 * e1000_reload_nvm_generic - Reloads EEPROM 912 * @hw: pointer to the HW structure 913 * 914 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 915 * extended control register. 916 **/ 917 void e1000_reload_nvm_generic(struct e1000_hw *hw) 918 { 919 u32 ctrl_ext; 920 921 DEBUGFUNC("e1000_reload_nvm_generic"); 922 923 usec_delay(10); 924 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 925 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 926 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 927 E1000_WRITE_FLUSH(hw); 928 } 929 930