xref: /freebsd/sys/dev/e1000/e1000_nvm.c (revision 5b426b3e8cbd5abdb3a57ff49cd27c36cac03427)
1 /******************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2020, Intel Corporation
5   All rights reserved.
6 
7   Redistribution and use in source and binary forms, with or without
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11       this list of conditions and the following disclaimer.
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32 
33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #include "e1000_api.h"
37 
38 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
39 
40 /**
41  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
42  *  @hw: pointer to the HW structure
43  *
44  *  Setups up the function pointers to no-op functions
45  **/
46 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 {
48 	struct e1000_nvm_info *nvm = &hw->nvm;
49 	DEBUGFUNC("e1000_init_nvm_ops_generic");
50 
51 	/* Initialize function pointers */
52 	nvm->ops.init_params = e1000_null_ops_generic;
53 	nvm->ops.acquire = e1000_null_ops_generic;
54 	nvm->ops.read = e1000_null_read_nvm;
55 	nvm->ops.release = e1000_null_nvm_generic;
56 	nvm->ops.reload = e1000_reload_nvm_generic;
57 	nvm->ops.update = e1000_null_ops_generic;
58 	nvm->ops.valid_led_default = e1000_null_led_default;
59 	nvm->ops.validate = e1000_null_ops_generic;
60 	nvm->ops.write = e1000_null_write_nvm;
61 }
62 
63 /**
64  *  e1000_null_nvm_read - No-op function, return 0
65  *  @hw: pointer to the HW structure
66  *  @a: dummy variable
67  *  @b: dummy variable
68  *  @c: dummy variable
69  **/
70 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
71 			u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
72 			u16 E1000_UNUSEDARG *c)
73 {
74 	DEBUGFUNC("e1000_null_read_nvm");
75 	return E1000_SUCCESS;
76 }
77 
78 /**
79  *  e1000_null_nvm_generic - No-op function, return void
80  *  @hw: pointer to the HW structure
81  **/
82 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
83 {
84 	DEBUGFUNC("e1000_null_nvm_generic");
85 	return;
86 }
87 
88 /**
89  *  e1000_null_led_default - No-op function, return 0
90  *  @hw: pointer to the HW structure
91  *  @data: dummy variable
92  **/
93 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
94 			   u16 E1000_UNUSEDARG *data)
95 {
96 	DEBUGFUNC("e1000_null_led_default");
97 	return E1000_SUCCESS;
98 }
99 
100 /**
101  *  e1000_null_write_nvm - No-op function, return 0
102  *  @hw: pointer to the HW structure
103  *  @a: dummy variable
104  *  @b: dummy variable
105  *  @c: dummy variable
106  **/
107 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
108 			 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
109 			 u16 E1000_UNUSEDARG *c)
110 {
111 	DEBUGFUNC("e1000_null_write_nvm");
112 	return E1000_SUCCESS;
113 }
114 
115 /**
116  *  e1000_raise_eec_clk - Raise EEPROM clock
117  *  @hw: pointer to the HW structure
118  *  @eecd: pointer to the EEPROM
119  *
120  *  Enable/Raise the EEPROM clock bit.
121  **/
122 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
123 {
124 	*eecd = *eecd | E1000_EECD_SK;
125 	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
126 	E1000_WRITE_FLUSH(hw);
127 	usec_delay(hw->nvm.delay_usec);
128 }
129 
130 /**
131  *  e1000_lower_eec_clk - Lower EEPROM clock
132  *  @hw: pointer to the HW structure
133  *  @eecd: pointer to the EEPROM
134  *
135  *  Clear/Lower the EEPROM clock bit.
136  **/
137 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
138 {
139 	*eecd = *eecd & ~E1000_EECD_SK;
140 	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
141 	E1000_WRITE_FLUSH(hw);
142 	usec_delay(hw->nvm.delay_usec);
143 }
144 
145 /**
146  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
147  *  @hw: pointer to the HW structure
148  *  @data: data to send to the EEPROM
149  *  @count: number of bits to shift out
150  *
151  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
152  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
153  *  In order to do this, "data" must be broken down into bits.
154  **/
155 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
156 {
157 	struct e1000_nvm_info *nvm = &hw->nvm;
158 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
159 	u32 mask;
160 
161 	DEBUGFUNC("e1000_shift_out_eec_bits");
162 
163 	mask = 0x01 << (count - 1);
164 	if (nvm->type == e1000_nvm_eeprom_microwire)
165 		eecd &= ~E1000_EECD_DO;
166 	else
167 	if (nvm->type == e1000_nvm_eeprom_spi)
168 		eecd |= E1000_EECD_DO;
169 
170 	do {
171 		eecd &= ~E1000_EECD_DI;
172 
173 		if (data & mask)
174 			eecd |= E1000_EECD_DI;
175 
176 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
177 		E1000_WRITE_FLUSH(hw);
178 
179 		usec_delay(nvm->delay_usec);
180 
181 		e1000_raise_eec_clk(hw, &eecd);
182 		e1000_lower_eec_clk(hw, &eecd);
183 
184 		mask >>= 1;
185 	} while (mask);
186 
187 	eecd &= ~E1000_EECD_DI;
188 	E1000_WRITE_REG(hw, E1000_EECD, eecd);
189 }
190 
191 /**
192  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
193  *  @hw: pointer to the HW structure
194  *  @count: number of bits to shift in
195  *
196  *  In order to read a register from the EEPROM, we need to shift 'count' bits
197  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
198  *  the EEPROM (setting the SK bit), and then reading the value of the data out
199  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
200  *  always be clear.
201  **/
202 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
203 {
204 	u32 eecd;
205 	u32 i;
206 	u16 data;
207 
208 	DEBUGFUNC("e1000_shift_in_eec_bits");
209 
210 	eecd = E1000_READ_REG(hw, E1000_EECD);
211 
212 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
213 	data = 0;
214 
215 	for (i = 0; i < count; i++) {
216 		data <<= 1;
217 		e1000_raise_eec_clk(hw, &eecd);
218 
219 		eecd = E1000_READ_REG(hw, E1000_EECD);
220 
221 		eecd &= ~E1000_EECD_DI;
222 		if (eecd & E1000_EECD_DO)
223 			data |= 1;
224 
225 		e1000_lower_eec_clk(hw, &eecd);
226 	}
227 
228 	return data;
229 }
230 
231 /**
232  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
233  *  @hw: pointer to the HW structure
234  *  @ee_reg: EEPROM flag for polling
235  *
236  *  Polls the EEPROM status bit for either read or write completion based
237  *  upon the value of 'ee_reg'.
238  **/
239 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
240 {
241 	u32 attempts = 100000;
242 	u32 i, reg = 0;
243 
244 	DEBUGFUNC("e1000_poll_eerd_eewr_done");
245 
246 	for (i = 0; i < attempts; i++) {
247 		if (ee_reg == E1000_NVM_POLL_READ)
248 			reg = E1000_READ_REG(hw, E1000_EERD);
249 		else
250 			reg = E1000_READ_REG(hw, E1000_EEWR);
251 
252 		if (reg & E1000_NVM_RW_REG_DONE)
253 			return E1000_SUCCESS;
254 
255 		usec_delay(5);
256 	}
257 
258 	return -E1000_ERR_NVM;
259 }
260 
261 /**
262  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
263  *  @hw: pointer to the HW structure
264  *
265  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
266  *  Return successful if access grant bit set, else clear the request for
267  *  EEPROM access and return -E1000_ERR_NVM (-1).
268  **/
269 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
270 {
271 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
272 	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
273 
274 	DEBUGFUNC("e1000_acquire_nvm_generic");
275 
276 	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
277 	eecd = E1000_READ_REG(hw, E1000_EECD);
278 
279 	while (timeout) {
280 		if (eecd & E1000_EECD_GNT)
281 			break;
282 		usec_delay(5);
283 		eecd = E1000_READ_REG(hw, E1000_EECD);
284 		timeout--;
285 	}
286 
287 	if (!timeout) {
288 		eecd &= ~E1000_EECD_REQ;
289 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
290 		DEBUGOUT("Could not acquire NVM grant\n");
291 		return -E1000_ERR_NVM;
292 	}
293 
294 	return E1000_SUCCESS;
295 }
296 
297 /**
298  *  e1000_standby_nvm - Return EEPROM to standby state
299  *  @hw: pointer to the HW structure
300  *
301  *  Return the EEPROM to a standby state.
302  **/
303 static void e1000_standby_nvm(struct e1000_hw *hw)
304 {
305 	struct e1000_nvm_info *nvm = &hw->nvm;
306 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
307 
308 	DEBUGFUNC("e1000_standby_nvm");
309 
310 	if (nvm->type == e1000_nvm_eeprom_microwire) {
311 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
312 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
313 		E1000_WRITE_FLUSH(hw);
314 		usec_delay(nvm->delay_usec);
315 
316 		e1000_raise_eec_clk(hw, &eecd);
317 
318 		/* Select EEPROM */
319 		eecd |= E1000_EECD_CS;
320 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
321 		E1000_WRITE_FLUSH(hw);
322 		usec_delay(nvm->delay_usec);
323 
324 		e1000_lower_eec_clk(hw, &eecd);
325 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
326 		/* Toggle CS to flush commands */
327 		eecd |= E1000_EECD_CS;
328 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
329 		E1000_WRITE_FLUSH(hw);
330 		usec_delay(nvm->delay_usec);
331 		eecd &= ~E1000_EECD_CS;
332 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
333 		E1000_WRITE_FLUSH(hw);
334 		usec_delay(nvm->delay_usec);
335 	}
336 }
337 
338 /**
339  *  e1000_stop_nvm - Terminate EEPROM command
340  *  @hw: pointer to the HW structure
341  *
342  *  Terminates the current command by inverting the EEPROM's chip select pin.
343  **/
344 void e1000_stop_nvm(struct e1000_hw *hw)
345 {
346 	u32 eecd;
347 
348 	DEBUGFUNC("e1000_stop_nvm");
349 
350 	eecd = E1000_READ_REG(hw, E1000_EECD);
351 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
352 		/* Pull CS high */
353 		eecd |= E1000_EECD_CS;
354 		e1000_lower_eec_clk(hw, &eecd);
355 	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
356 		/* CS on Microwire is active-high */
357 		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
358 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
359 		e1000_raise_eec_clk(hw, &eecd);
360 		e1000_lower_eec_clk(hw, &eecd);
361 	}
362 }
363 
364 /**
365  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
366  *  @hw: pointer to the HW structure
367  *
368  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
369  **/
370 void e1000_release_nvm_generic(struct e1000_hw *hw)
371 {
372 	u32 eecd;
373 
374 	DEBUGFUNC("e1000_release_nvm_generic");
375 
376 	e1000_stop_nvm(hw);
377 
378 	eecd = E1000_READ_REG(hw, E1000_EECD);
379 	eecd &= ~E1000_EECD_REQ;
380 	E1000_WRITE_REG(hw, E1000_EECD, eecd);
381 }
382 
383 /**
384  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
385  *  @hw: pointer to the HW structure
386  *
387  *  Setups the EEPROM for reading and writing.
388  **/
389 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
390 {
391 	struct e1000_nvm_info *nvm = &hw->nvm;
392 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
393 	u8 spi_stat_reg;
394 
395 	DEBUGFUNC("e1000_ready_nvm_eeprom");
396 
397 	if (nvm->type == e1000_nvm_eeprom_microwire) {
398 		/* Clear SK and DI */
399 		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
400 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
401 		/* Set CS */
402 		eecd |= E1000_EECD_CS;
403 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
404 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
405 		u16 timeout = NVM_MAX_RETRY_SPI;
406 
407 		/* Clear SK and CS */
408 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
409 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
410 		E1000_WRITE_FLUSH(hw);
411 		usec_delay(1);
412 
413 		/* Read "Status Register" repeatedly until the LSB is cleared.
414 		 * The EEPROM will signal that the command has been completed
415 		 * by clearing bit 0 of the internal status register.  If it's
416 		 * not cleared within 'timeout', then error out.
417 		 */
418 		while (timeout) {
419 			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
420 						 hw->nvm.opcode_bits);
421 			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
422 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
423 				break;
424 
425 			usec_delay(5);
426 			e1000_standby_nvm(hw);
427 			timeout--;
428 		}
429 
430 		if (!timeout) {
431 			DEBUGOUT("SPI NVM Status error\n");
432 			return -E1000_ERR_NVM;
433 		}
434 	}
435 
436 	return E1000_SUCCESS;
437 }
438 
439 /**
440  *  e1000_read_nvm_spi - Read EEPROM's using SPI
441  *  @hw: pointer to the HW structure
442  *  @offset: offset of word in the EEPROM to read
443  *  @words: number of words to read
444  *  @data: word read from the EEPROM
445  *
446  *  Reads a 16 bit word from the EEPROM.
447  **/
448 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
449 {
450 	struct e1000_nvm_info *nvm = &hw->nvm;
451 	u32 i = 0;
452 	s32 ret_val;
453 	u16 word_in;
454 	u8 read_opcode = NVM_READ_OPCODE_SPI;
455 
456 	DEBUGFUNC("e1000_read_nvm_spi");
457 
458 	/* A check for invalid values:  offset too large, too many words,
459 	 * and not enough words.
460 	 */
461 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
462 	    (words == 0)) {
463 		DEBUGOUT("nvm parameter(s) out of bounds\n");
464 		return -E1000_ERR_NVM;
465 	}
466 
467 	ret_val = nvm->ops.acquire(hw);
468 	if (ret_val)
469 		return ret_val;
470 
471 	ret_val = e1000_ready_nvm_eeprom(hw);
472 	if (ret_val)
473 		goto release;
474 
475 	e1000_standby_nvm(hw);
476 
477 	if ((nvm->address_bits == 8) && (offset >= 128))
478 		read_opcode |= NVM_A8_OPCODE_SPI;
479 
480 	/* Send the READ command (opcode + addr) */
481 	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
482 	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
483 
484 	/* Read the data.  SPI NVMs increment the address with each byte
485 	 * read and will roll over if reading beyond the end.  This allows
486 	 * us to read the whole NVM from any offset
487 	 */
488 	for (i = 0; i < words; i++) {
489 		word_in = e1000_shift_in_eec_bits(hw, 16);
490 		data[i] = (word_in >> 8) | (word_in << 8);
491 	}
492 
493 release:
494 	nvm->ops.release(hw);
495 
496 	return ret_val;
497 }
498 
499 /**
500  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
501  *  @hw: pointer to the HW structure
502  *  @offset: offset of word in the EEPROM to read
503  *  @words: number of words to read
504  *  @data: word read from the EEPROM
505  *
506  *  Reads a 16 bit word from the EEPROM.
507  **/
508 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
509 			     u16 *data)
510 {
511 	struct e1000_nvm_info *nvm = &hw->nvm;
512 	u32 i = 0;
513 	s32 ret_val;
514 	u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
515 
516 	DEBUGFUNC("e1000_read_nvm_microwire");
517 
518 	/* A check for invalid values:  offset too large, too many words,
519 	 * and not enough words.
520 	 */
521 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
522 	    (words == 0)) {
523 		DEBUGOUT("nvm parameter(s) out of bounds\n");
524 		return -E1000_ERR_NVM;
525 	}
526 
527 	ret_val = nvm->ops.acquire(hw);
528 	if (ret_val)
529 		return ret_val;
530 
531 	ret_val = e1000_ready_nvm_eeprom(hw);
532 	if (ret_val)
533 		goto release;
534 
535 	for (i = 0; i < words; i++) {
536 		/* Send the READ command (opcode + addr) */
537 		e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
538 		e1000_shift_out_eec_bits(hw, (u16)(offset + i),
539 					nvm->address_bits);
540 
541 		/* Read the data.  For microwire, each word requires the
542 		 * overhead of setup and tear-down.
543 		 */
544 		data[i] = e1000_shift_in_eec_bits(hw, 16);
545 		e1000_standby_nvm(hw);
546 	}
547 
548 release:
549 	nvm->ops.release(hw);
550 
551 	return ret_val;
552 }
553 
554 /**
555  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
556  *  @hw: pointer to the HW structure
557  *  @offset: offset of word in the EEPROM to read
558  *  @words: number of words to read
559  *  @data: word read from the EEPROM
560  *
561  *  Reads a 16 bit word from the EEPROM using the EERD register.
562  **/
563 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
564 {
565 	struct e1000_nvm_info *nvm = &hw->nvm;
566 	u32 i, eerd = 0;
567 	s32 ret_val = E1000_SUCCESS;
568 
569 	DEBUGFUNC("e1000_read_nvm_eerd");
570 
571 	/* A check for invalid values:  offset too large, too many words,
572 	 * too many words for the offset, and not enough words.
573 	 */
574 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
575 	    (words == 0)) {
576 		DEBUGOUT("nvm parameter(s) out of bounds\n");
577 		return -E1000_ERR_NVM;
578 	}
579 
580 	for (i = 0; i < words; i++) {
581 		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
582 		       E1000_NVM_RW_REG_START;
583 
584 		E1000_WRITE_REG(hw, E1000_EERD, eerd);
585 		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
586 		if (ret_val)
587 			break;
588 
589 		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
590 			   E1000_NVM_RW_REG_DATA);
591 	}
592 
593 	if (ret_val)
594 		DEBUGOUT1("NVM read error: %d\n", ret_val);
595 
596 	return ret_val;
597 }
598 
599 /**
600  *  e1000_write_nvm_spi - Write to EEPROM using SPI
601  *  @hw: pointer to the HW structure
602  *  @offset: offset within the EEPROM to be written to
603  *  @words: number of words to write
604  *  @data: 16 bit word(s) to be written to the EEPROM
605  *
606  *  Writes data to EEPROM at offset using SPI interface.
607  *
608  *  If e1000_update_nvm_checksum is not called after this function , the
609  *  EEPROM will most likely contain an invalid checksum.
610  **/
611 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
612 {
613 	struct e1000_nvm_info *nvm = &hw->nvm;
614 	s32 ret_val = -E1000_ERR_NVM;
615 	u16 widx = 0;
616 
617 	DEBUGFUNC("e1000_write_nvm_spi");
618 
619 	/* A check for invalid values:  offset too large, too many words,
620 	 * and not enough words.
621 	 */
622 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
623 	    (words == 0)) {
624 		DEBUGOUT("nvm parameter(s) out of bounds\n");
625 		return -E1000_ERR_NVM;
626 	}
627 
628 	while (widx < words) {
629 		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
630 
631 		ret_val = nvm->ops.acquire(hw);
632 		if (ret_val)
633 			return ret_val;
634 
635 		ret_val = e1000_ready_nvm_eeprom(hw);
636 		if (ret_val) {
637 			nvm->ops.release(hw);
638 			return ret_val;
639 		}
640 
641 		e1000_standby_nvm(hw);
642 
643 		/* Send the WRITE ENABLE command (8 bit opcode) */
644 		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
645 					 nvm->opcode_bits);
646 
647 		e1000_standby_nvm(hw);
648 
649 		/* Some SPI eeproms use the 8th address bit embedded in the
650 		 * opcode
651 		 */
652 		if ((nvm->address_bits == 8) && (offset >= 128))
653 			write_opcode |= NVM_A8_OPCODE_SPI;
654 
655 		/* Send the Write command (8-bit opcode + addr) */
656 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
657 		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
658 					 nvm->address_bits);
659 
660 		/* Loop to allow for up to whole page write of eeprom */
661 		while (widx < words) {
662 			u16 word_out = data[widx];
663 			word_out = (word_out >> 8) | (word_out << 8);
664 			e1000_shift_out_eec_bits(hw, word_out, 16);
665 			widx++;
666 
667 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
668 				e1000_standby_nvm(hw);
669 				break;
670 			}
671 		}
672 		msec_delay(10);
673 		nvm->ops.release(hw);
674 	}
675 
676 	return ret_val;
677 }
678 
679 /**
680  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
681  *  @hw: pointer to the HW structure
682  *  @offset: offset within the EEPROM to be written to
683  *  @words: number of words to write
684  *  @data: 16 bit word(s) to be written to the EEPROM
685  *
686  *  Writes data to EEPROM at offset using microwire interface.
687  *
688  *  If e1000_update_nvm_checksum is not called after this function , the
689  *  EEPROM will most likely contain an invalid checksum.
690  **/
691 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
692 			      u16 *data)
693 {
694 	struct e1000_nvm_info *nvm = &hw->nvm;
695 	s32  ret_val;
696 	u32 eecd;
697 	u16 words_written = 0;
698 	u16 widx = 0;
699 
700 	DEBUGFUNC("e1000_write_nvm_microwire");
701 
702 	/* A check for invalid values:  offset too large, too many words,
703 	 * and not enough words.
704 	 */
705 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
706 	    (words == 0)) {
707 		DEBUGOUT("nvm parameter(s) out of bounds\n");
708 		return -E1000_ERR_NVM;
709 	}
710 
711 	ret_val = nvm->ops.acquire(hw);
712 	if (ret_val)
713 		return ret_val;
714 
715 	ret_val = e1000_ready_nvm_eeprom(hw);
716 	if (ret_val)
717 		goto release;
718 
719 	e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
720 				 (u16)(nvm->opcode_bits + 2));
721 
722 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
723 
724 	e1000_standby_nvm(hw);
725 
726 	while (words_written < words) {
727 		e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
728 					 nvm->opcode_bits);
729 
730 		e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
731 					 nvm->address_bits);
732 
733 		e1000_shift_out_eec_bits(hw, data[words_written], 16);
734 
735 		e1000_standby_nvm(hw);
736 
737 		for (widx = 0; widx < 200; widx++) {
738 			eecd = E1000_READ_REG(hw, E1000_EECD);
739 			if (eecd & E1000_EECD_DO)
740 				break;
741 			usec_delay(50);
742 		}
743 
744 		if (widx == 200) {
745 			DEBUGOUT("NVM Write did not complete\n");
746 			ret_val = -E1000_ERR_NVM;
747 			goto release;
748 		}
749 
750 		e1000_standby_nvm(hw);
751 
752 		words_written++;
753 	}
754 
755 	e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
756 				 (u16)(nvm->opcode_bits + 2));
757 
758 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
759 
760 release:
761 	nvm->ops.release(hw);
762 
763 	return ret_val;
764 }
765 
766 /**
767  *  e1000_read_pba_string_generic - Read device part number
768  *  @hw: pointer to the HW structure
769  *  @pba_num: pointer to device part number
770  *  @pba_num_size: size of part number buffer
771  *
772  *  Reads the product board assembly (PBA) number from the EEPROM and stores
773  *  the value in pba_num.
774  **/
775 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
776 				  u32 pba_num_size)
777 {
778 	s32 ret_val;
779 	u16 nvm_data;
780 	u16 pba_ptr;
781 	u16 offset;
782 	u16 length;
783 
784 	DEBUGFUNC("e1000_read_pba_string_generic");
785 
786 	if ((hw->mac.type == e1000_i210 ||
787 	     hw->mac.type == e1000_i211) &&
788 	     !e1000_get_flash_presence_i210(hw)) {
789 		DEBUGOUT("Flashless no PBA string\n");
790 		return -E1000_ERR_NVM_PBA_SECTION;
791 	}
792 
793 	if (pba_num == NULL) {
794 		DEBUGOUT("PBA string buffer was null\n");
795 		return -E1000_ERR_INVALID_ARGUMENT;
796 	}
797 
798 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
799 	if (ret_val) {
800 		DEBUGOUT("NVM Read Error\n");
801 		return ret_val;
802 	}
803 
804 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
805 	if (ret_val) {
806 		DEBUGOUT("NVM Read Error\n");
807 		return ret_val;
808 	}
809 
810 	/* if nvm_data is not ptr guard the PBA must be in legacy format which
811 	 * means pba_ptr is actually our second data word for the PBA number
812 	 * and we can decode it into an ascii string
813 	 */
814 	if (nvm_data != NVM_PBA_PTR_GUARD) {
815 		DEBUGOUT("NVM PBA number is not stored as string\n");
816 
817 		/* make sure callers buffer is big enough to store the PBA */
818 		if (pba_num_size < E1000_PBANUM_LENGTH) {
819 			DEBUGOUT("PBA string buffer too small\n");
820 			return E1000_ERR_NO_SPACE;
821 		}
822 
823 		/* extract hex string from data and pba_ptr */
824 		pba_num[0] = (nvm_data >> 12) & 0xF;
825 		pba_num[1] = (nvm_data >> 8) & 0xF;
826 		pba_num[2] = (nvm_data >> 4) & 0xF;
827 		pba_num[3] = nvm_data & 0xF;
828 		pba_num[4] = (pba_ptr >> 12) & 0xF;
829 		pba_num[5] = (pba_ptr >> 8) & 0xF;
830 		pba_num[6] = '-';
831 		pba_num[7] = 0;
832 		pba_num[8] = (pba_ptr >> 4) & 0xF;
833 		pba_num[9] = pba_ptr & 0xF;
834 
835 		/* put a null character on the end of our string */
836 		pba_num[10] = '\0';
837 
838 		/* switch all the data but the '-' to hex char */
839 		for (offset = 0; offset < 10; offset++) {
840 			if (pba_num[offset] < 0xA)
841 				pba_num[offset] += '0';
842 			else if (pba_num[offset] < 0x10)
843 				pba_num[offset] += 'A' - 0xA;
844 		}
845 
846 		return E1000_SUCCESS;
847 	}
848 
849 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
850 	if (ret_val) {
851 		DEBUGOUT("NVM Read Error\n");
852 		return ret_val;
853 	}
854 
855 	if (length == 0xFFFF || length == 0) {
856 		DEBUGOUT("NVM PBA number section invalid length\n");
857 		return -E1000_ERR_NVM_PBA_SECTION;
858 	}
859 	/* check if pba_num buffer is big enough */
860 	if (pba_num_size < (((u32)length * 2) - 1)) {
861 		DEBUGOUT("PBA string buffer too small\n");
862 		return -E1000_ERR_NO_SPACE;
863 	}
864 
865 	/* trim pba length from start of string */
866 	pba_ptr++;
867 	length--;
868 
869 	for (offset = 0; offset < length; offset++) {
870 		ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
871 		if (ret_val) {
872 			DEBUGOUT("NVM Read Error\n");
873 			return ret_val;
874 		}
875 		pba_num[offset * 2] = (u8)(nvm_data >> 8);
876 		pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
877 	}
878 	pba_num[offset * 2] = '\0';
879 
880 	return E1000_SUCCESS;
881 }
882 
883 /**
884  *  e1000_read_pba_length_generic - Read device part number length
885  *  @hw: pointer to the HW structure
886  *  @pba_num_size: size of part number buffer
887  *
888  *  Reads the product board assembly (PBA) number length from the EEPROM and
889  *  stores the value in pba_num_size.
890  **/
891 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
892 {
893 	s32 ret_val;
894 	u16 nvm_data;
895 	u16 pba_ptr;
896 	u16 length;
897 
898 	DEBUGFUNC("e1000_read_pba_length_generic");
899 
900 	if (pba_num_size == NULL) {
901 		DEBUGOUT("PBA buffer size was null\n");
902 		return -E1000_ERR_INVALID_ARGUMENT;
903 	}
904 
905 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
906 	if (ret_val) {
907 		DEBUGOUT("NVM Read Error\n");
908 		return ret_val;
909 	}
910 
911 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
912 	if (ret_val) {
913 		DEBUGOUT("NVM Read Error\n");
914 		return ret_val;
915 	}
916 
917 	 /* if data is not ptr guard the PBA must be in legacy format */
918 	if (nvm_data != NVM_PBA_PTR_GUARD) {
919 		*pba_num_size = E1000_PBANUM_LENGTH;
920 		return E1000_SUCCESS;
921 	}
922 
923 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
924 	if (ret_val) {
925 		DEBUGOUT("NVM Read Error\n");
926 		return ret_val;
927 	}
928 
929 	if (length == 0xFFFF || length == 0) {
930 		DEBUGOUT("NVM PBA number section invalid length\n");
931 		return -E1000_ERR_NVM_PBA_SECTION;
932 	}
933 
934 	/* Convert from length in u16 values to u8 chars, add 1 for NULL,
935 	 * and subtract 2 because length field is included in length.
936 	 */
937 	*pba_num_size = ((u32)length * 2) - 1;
938 
939 	return E1000_SUCCESS;
940 }
941 
942 
943 /**
944  *  e1000_read_pba_raw
945  *  @hw: pointer to the HW structure
946  *  @eeprom_buf: optional pointer to EEPROM image
947  *  @eeprom_buf_size: size of EEPROM image in words
948  *  @max_pba_block_size: PBA block size limit
949  *  @pba: pointer to output PBA structure
950  *
951  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
952  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
953  *
954  **/
955 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
956 		       u32 eeprom_buf_size, u16 max_pba_block_size,
957 		       struct e1000_pba *pba)
958 {
959 	s32 ret_val;
960 	u16 pba_block_size;
961 
962 	if (pba == NULL)
963 		return -E1000_ERR_PARAM;
964 
965 	if (eeprom_buf == NULL) {
966 		ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
967 					 &pba->word[0]);
968 		if (ret_val)
969 			return ret_val;
970 	} else {
971 		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
972 			pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
973 			pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
974 		} else {
975 			return -E1000_ERR_PARAM;
976 		}
977 	}
978 
979 	if (pba->word[0] == NVM_PBA_PTR_GUARD) {
980 		if (pba->pba_block == NULL)
981 			return -E1000_ERR_PARAM;
982 
983 		ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
984 						   eeprom_buf_size,
985 						   &pba_block_size);
986 		if (ret_val)
987 			return ret_val;
988 
989 		if (pba_block_size > max_pba_block_size)
990 			return -E1000_ERR_PARAM;
991 
992 		if (eeprom_buf == NULL) {
993 			ret_val = e1000_read_nvm(hw, pba->word[1],
994 						 pba_block_size,
995 						 pba->pba_block);
996 			if (ret_val)
997 				return ret_val;
998 		} else {
999 			if (eeprom_buf_size > (u32)(pba->word[1] +
1000 					      pba_block_size)) {
1001 				memcpy(pba->pba_block,
1002 				       &eeprom_buf[pba->word[1]],
1003 				       pba_block_size * sizeof(u16));
1004 			} else {
1005 				return -E1000_ERR_PARAM;
1006 			}
1007 		}
1008 	}
1009 
1010 	return E1000_SUCCESS;
1011 }
1012 
1013 /**
1014  *  e1000_write_pba_raw
1015  *  @hw: pointer to the HW structure
1016  *  @eeprom_buf: optional pointer to EEPROM image
1017  *  @eeprom_buf_size: size of EEPROM image in words
1018  *  @pba: pointer to PBA structure
1019  *
1020  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1021  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1022  *
1023  **/
1024 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1025 			u32 eeprom_buf_size, struct e1000_pba *pba)
1026 {
1027 	s32 ret_val;
1028 
1029 	if (pba == NULL)
1030 		return -E1000_ERR_PARAM;
1031 
1032 	if (eeprom_buf == NULL) {
1033 		ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1034 					  &pba->word[0]);
1035 		if (ret_val)
1036 			return ret_val;
1037 	} else {
1038 		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1039 			eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1040 			eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1041 		} else {
1042 			return -E1000_ERR_PARAM;
1043 		}
1044 	}
1045 
1046 	if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1047 		if (pba->pba_block == NULL)
1048 			return -E1000_ERR_PARAM;
1049 
1050 		if (eeprom_buf == NULL) {
1051 			ret_val = e1000_write_nvm(hw, pba->word[1],
1052 						  pba->pba_block[0],
1053 						  pba->pba_block);
1054 			if (ret_val)
1055 				return ret_val;
1056 		} else {
1057 			if (eeprom_buf_size > (u32)(pba->word[1] +
1058 					      pba->pba_block[0])) {
1059 				memcpy(&eeprom_buf[pba->word[1]],
1060 				       pba->pba_block,
1061 				       pba->pba_block[0] * sizeof(u16));
1062 			} else {
1063 				return -E1000_ERR_PARAM;
1064 			}
1065 		}
1066 	}
1067 
1068 	return E1000_SUCCESS;
1069 }
1070 
1071 /**
1072  *  e1000_get_pba_block_size
1073  *  @hw: pointer to the HW structure
1074  *  @eeprom_buf: optional pointer to EEPROM image
1075  *  @eeprom_buf_size: size of EEPROM image in words
1076  *  @pba_data_size: pointer to output variable
1077  *
1078  *  Returns the size of the PBA block in words. Function operates on EEPROM
1079  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1080  *  EEPROM device.
1081  *
1082  **/
1083 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1084 			     u32 eeprom_buf_size, u16 *pba_block_size)
1085 {
1086 	s32 ret_val;
1087 	u16 pba_word[2];
1088 	u16 length;
1089 
1090 	DEBUGFUNC("e1000_get_pba_block_size");
1091 
1092 	if (eeprom_buf == NULL) {
1093 		ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1094 		if (ret_val)
1095 			return ret_val;
1096 	} else {
1097 		if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1098 			pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1099 			pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1100 		} else {
1101 			return -E1000_ERR_PARAM;
1102 		}
1103 	}
1104 
1105 	if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1106 		if (eeprom_buf == NULL) {
1107 			ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1108 						 &length);
1109 			if (ret_val)
1110 				return ret_val;
1111 		} else {
1112 			if (eeprom_buf_size > pba_word[1])
1113 				length = eeprom_buf[pba_word[1] + 0];
1114 			else
1115 				return -E1000_ERR_PARAM;
1116 		}
1117 
1118 		if (length == 0xFFFF || length == 0)
1119 			return -E1000_ERR_NVM_PBA_SECTION;
1120 	} else {
1121 		/* PBA number in legacy format, there is no PBA Block. */
1122 		length = 0;
1123 	}
1124 
1125 	if (pba_block_size != NULL)
1126 		*pba_block_size = length;
1127 
1128 	return E1000_SUCCESS;
1129 }
1130 
1131 /**
1132  *  e1000_read_mac_addr_generic - Read device MAC address
1133  *  @hw: pointer to the HW structure
1134  *
1135  *  Reads the device MAC address from the EEPROM and stores the value.
1136  *  Since devices with two ports use the same EEPROM, we increment the
1137  *  last bit in the MAC address for the second port.
1138  **/
1139 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1140 {
1141 	u32 rar_high;
1142 	u32 rar_low;
1143 	u16 i;
1144 
1145 	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1146 	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1147 
1148 	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1149 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1150 
1151 	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1152 		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1153 
1154 	for (i = 0; i < ETHER_ADDR_LEN; i++)
1155 		hw->mac.addr[i] = hw->mac.perm_addr[i];
1156 
1157 	return E1000_SUCCESS;
1158 }
1159 
1160 /**
1161  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1165  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1166  **/
1167 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1168 {
1169 	s32 ret_val;
1170 	u16 checksum = 0;
1171 	u16 i, nvm_data;
1172 
1173 	DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1174 
1175 	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1176 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1177 		if (ret_val) {
1178 			DEBUGOUT("NVM Read Error\n");
1179 			return ret_val;
1180 		}
1181 		checksum += nvm_data;
1182 	}
1183 
1184 	if (checksum != (u16) NVM_SUM) {
1185 		DEBUGOUT("NVM Checksum Invalid\n");
1186 		return -E1000_ERR_NVM;
1187 	}
1188 
1189 	return E1000_SUCCESS;
1190 }
1191 
1192 /**
1193  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1194  *  @hw: pointer to the HW structure
1195  *
1196  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1197  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1198  *  value to the EEPROM.
1199  **/
1200 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1201 {
1202 	s32 ret_val;
1203 	u16 checksum = 0;
1204 	u16 i, nvm_data;
1205 
1206 	DEBUGFUNC("e1000_update_nvm_checksum");
1207 
1208 	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1209 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1210 		if (ret_val) {
1211 			DEBUGOUT("NVM Read Error while updating checksum.\n");
1212 			return ret_val;
1213 		}
1214 		checksum += nvm_data;
1215 	}
1216 	checksum = (u16) NVM_SUM - checksum;
1217 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1218 	if (ret_val)
1219 		DEBUGOUT("NVM Write Error while updating checksum.\n");
1220 
1221 	return ret_val;
1222 }
1223 
1224 /**
1225  *  e1000_reload_nvm_generic - Reloads EEPROM
1226  *  @hw: pointer to the HW structure
1227  *
1228  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1229  *  extended control register.
1230  **/
1231 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1232 {
1233 	u32 ctrl_ext;
1234 
1235 	DEBUGFUNC("e1000_reload_nvm_generic");
1236 
1237 	usec_delay(10);
1238 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1239 	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1240 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1241 	E1000_WRITE_FLUSH(hw);
1242 }
1243 
1244 
1245