1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static void e1000_reload_nvm_generic(struct e1000_hw *hw); 38 39 /** 40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 **/ 45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 46 { 47 struct e1000_nvm_info *nvm = &hw->nvm; 48 DEBUGFUNC("e1000_init_nvm_ops_generic"); 49 50 /* Initialize function pointers */ 51 nvm->ops.init_params = e1000_null_ops_generic; 52 nvm->ops.acquire = e1000_null_ops_generic; 53 nvm->ops.read = e1000_null_read_nvm; 54 nvm->ops.release = e1000_null_nvm_generic; 55 nvm->ops.reload = e1000_reload_nvm_generic; 56 nvm->ops.update = e1000_null_ops_generic; 57 nvm->ops.valid_led_default = e1000_null_led_default; 58 nvm->ops.validate = e1000_null_ops_generic; 59 nvm->ops.write = e1000_null_write_nvm; 60 } 61 62 /** 63 * e1000_null_nvm_read - No-op function, return 0 64 * @hw: pointer to the HW structure 65 **/ 66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 67 { 68 DEBUGFUNC("e1000_null_read_nvm"); 69 return E1000_SUCCESS; 70 } 71 72 /** 73 * e1000_null_nvm_generic - No-op function, return void 74 * @hw: pointer to the HW structure 75 **/ 76 void e1000_null_nvm_generic(struct e1000_hw *hw) 77 { 78 DEBUGFUNC("e1000_null_nvm_generic"); 79 return; 80 } 81 82 /** 83 * e1000_null_led_default - No-op function, return 0 84 * @hw: pointer to the HW structure 85 **/ 86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data) 87 { 88 DEBUGFUNC("e1000_null_led_default"); 89 return E1000_SUCCESS; 90 } 91 92 /** 93 * e1000_null_write_nvm - No-op function, return 0 94 * @hw: pointer to the HW structure 95 **/ 96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 97 { 98 DEBUGFUNC("e1000_null_write_nvm"); 99 return E1000_SUCCESS; 100 } 101 102 /** 103 * e1000_raise_eec_clk - Raise EEPROM clock 104 * @hw: pointer to the HW structure 105 * @eecd: pointer to the EEPROM 106 * 107 * Enable/Raise the EEPROM clock bit. 108 **/ 109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 110 { 111 *eecd = *eecd | E1000_EECD_SK; 112 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 113 E1000_WRITE_FLUSH(hw); 114 usec_delay(hw->nvm.delay_usec); 115 } 116 117 /** 118 * e1000_lower_eec_clk - Lower EEPROM clock 119 * @hw: pointer to the HW structure 120 * @eecd: pointer to the EEPROM 121 * 122 * Clear/Lower the EEPROM clock bit. 123 **/ 124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 125 { 126 *eecd = *eecd & ~E1000_EECD_SK; 127 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 128 E1000_WRITE_FLUSH(hw); 129 usec_delay(hw->nvm.delay_usec); 130 } 131 132 /** 133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 134 * @hw: pointer to the HW structure 135 * @data: data to send to the EEPROM 136 * @count: number of bits to shift out 137 * 138 * We need to shift 'count' bits out to the EEPROM. So, the value in the 139 * "data" parameter will be shifted out to the EEPROM one bit at a time. 140 * In order to do this, "data" must be broken down into bits. 141 **/ 142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 143 { 144 struct e1000_nvm_info *nvm = &hw->nvm; 145 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 146 u32 mask; 147 148 DEBUGFUNC("e1000_shift_out_eec_bits"); 149 150 mask = 0x01 << (count - 1); 151 if (nvm->type == e1000_nvm_eeprom_microwire) 152 eecd &= ~E1000_EECD_DO; 153 else 154 if (nvm->type == e1000_nvm_eeprom_spi) 155 eecd |= E1000_EECD_DO; 156 157 do { 158 eecd &= ~E1000_EECD_DI; 159 160 if (data & mask) 161 eecd |= E1000_EECD_DI; 162 163 E1000_WRITE_REG(hw, E1000_EECD, eecd); 164 E1000_WRITE_FLUSH(hw); 165 166 usec_delay(nvm->delay_usec); 167 168 e1000_raise_eec_clk(hw, &eecd); 169 e1000_lower_eec_clk(hw, &eecd); 170 171 mask >>= 1; 172 } while (mask); 173 174 eecd &= ~E1000_EECD_DI; 175 E1000_WRITE_REG(hw, E1000_EECD, eecd); 176 } 177 178 /** 179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 180 * @hw: pointer to the HW structure 181 * @count: number of bits to shift in 182 * 183 * In order to read a register from the EEPROM, we need to shift 'count' bits 184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 185 * the EEPROM (setting the SK bit), and then reading the value of the data out 186 * "DO" bit. During this "shifting in" process the data in "DI" bit should 187 * always be clear. 188 **/ 189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 190 { 191 u32 eecd; 192 u32 i; 193 u16 data; 194 195 DEBUGFUNC("e1000_shift_in_eec_bits"); 196 197 eecd = E1000_READ_REG(hw, E1000_EECD); 198 199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 200 data = 0; 201 202 for (i = 0; i < count; i++) { 203 data <<= 1; 204 e1000_raise_eec_clk(hw, &eecd); 205 206 eecd = E1000_READ_REG(hw, E1000_EECD); 207 208 eecd &= ~E1000_EECD_DI; 209 if (eecd & E1000_EECD_DO) 210 data |= 1; 211 212 e1000_lower_eec_clk(hw, &eecd); 213 } 214 215 return data; 216 } 217 218 /** 219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 220 * @hw: pointer to the HW structure 221 * @ee_reg: EEPROM flag for polling 222 * 223 * Polls the EEPROM status bit for either read or write completion based 224 * upon the value of 'ee_reg'. 225 **/ 226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 227 { 228 u32 attempts = 100000; 229 u32 i, reg = 0; 230 231 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 232 233 for (i = 0; i < attempts; i++) { 234 if (ee_reg == E1000_NVM_POLL_READ) 235 reg = E1000_READ_REG(hw, E1000_EERD); 236 else 237 reg = E1000_READ_REG(hw, E1000_EEWR); 238 239 if (reg & E1000_NVM_RW_REG_DONE) 240 return E1000_SUCCESS; 241 242 usec_delay(5); 243 } 244 245 return -E1000_ERR_NVM; 246 } 247 248 /** 249 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 250 * @hw: pointer to the HW structure 251 * 252 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 253 * Return successful if access grant bit set, else clear the request for 254 * EEPROM access and return -E1000_ERR_NVM (-1). 255 **/ 256 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 257 { 258 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 259 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 260 261 DEBUGFUNC("e1000_acquire_nvm_generic"); 262 263 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 264 eecd = E1000_READ_REG(hw, E1000_EECD); 265 266 while (timeout) { 267 if (eecd & E1000_EECD_GNT) 268 break; 269 usec_delay(5); 270 eecd = E1000_READ_REG(hw, E1000_EECD); 271 timeout--; 272 } 273 274 if (!timeout) { 275 eecd &= ~E1000_EECD_REQ; 276 E1000_WRITE_REG(hw, E1000_EECD, eecd); 277 DEBUGOUT("Could not acquire NVM grant\n"); 278 return -E1000_ERR_NVM; 279 } 280 281 return E1000_SUCCESS; 282 } 283 284 /** 285 * e1000_standby_nvm - Return EEPROM to standby state 286 * @hw: pointer to the HW structure 287 * 288 * Return the EEPROM to a standby state. 289 **/ 290 static void e1000_standby_nvm(struct e1000_hw *hw) 291 { 292 struct e1000_nvm_info *nvm = &hw->nvm; 293 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 294 295 DEBUGFUNC("e1000_standby_nvm"); 296 297 if (nvm->type == e1000_nvm_eeprom_microwire) { 298 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 299 E1000_WRITE_REG(hw, E1000_EECD, eecd); 300 E1000_WRITE_FLUSH(hw); 301 usec_delay(nvm->delay_usec); 302 303 e1000_raise_eec_clk(hw, &eecd); 304 305 /* Select EEPROM */ 306 eecd |= E1000_EECD_CS; 307 E1000_WRITE_REG(hw, E1000_EECD, eecd); 308 E1000_WRITE_FLUSH(hw); 309 usec_delay(nvm->delay_usec); 310 311 e1000_lower_eec_clk(hw, &eecd); 312 } else if (nvm->type == e1000_nvm_eeprom_spi) { 313 /* Toggle CS to flush commands */ 314 eecd |= E1000_EECD_CS; 315 E1000_WRITE_REG(hw, E1000_EECD, eecd); 316 E1000_WRITE_FLUSH(hw); 317 usec_delay(nvm->delay_usec); 318 eecd &= ~E1000_EECD_CS; 319 E1000_WRITE_REG(hw, E1000_EECD, eecd); 320 E1000_WRITE_FLUSH(hw); 321 usec_delay(nvm->delay_usec); 322 } 323 } 324 325 /** 326 * e1000_stop_nvm - Terminate EEPROM command 327 * @hw: pointer to the HW structure 328 * 329 * Terminates the current command by inverting the EEPROM's chip select pin. 330 **/ 331 void e1000_stop_nvm(struct e1000_hw *hw) 332 { 333 u32 eecd; 334 335 DEBUGFUNC("e1000_stop_nvm"); 336 337 eecd = E1000_READ_REG(hw, E1000_EECD); 338 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 339 /* Pull CS high */ 340 eecd |= E1000_EECD_CS; 341 e1000_lower_eec_clk(hw, &eecd); 342 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 343 /* CS on Microwire is active-high */ 344 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 345 E1000_WRITE_REG(hw, E1000_EECD, eecd); 346 e1000_raise_eec_clk(hw, &eecd); 347 e1000_lower_eec_clk(hw, &eecd); 348 } 349 } 350 351 /** 352 * e1000_release_nvm_generic - Release exclusive access to EEPROM 353 * @hw: pointer to the HW structure 354 * 355 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 356 **/ 357 void e1000_release_nvm_generic(struct e1000_hw *hw) 358 { 359 u32 eecd; 360 361 DEBUGFUNC("e1000_release_nvm_generic"); 362 363 e1000_stop_nvm(hw); 364 365 eecd = E1000_READ_REG(hw, E1000_EECD); 366 eecd &= ~E1000_EECD_REQ; 367 E1000_WRITE_REG(hw, E1000_EECD, eecd); 368 } 369 370 /** 371 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 372 * @hw: pointer to the HW structure 373 * 374 * Setups the EEPROM for reading and writing. 375 **/ 376 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 377 { 378 struct e1000_nvm_info *nvm = &hw->nvm; 379 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 380 u8 spi_stat_reg; 381 382 DEBUGFUNC("e1000_ready_nvm_eeprom"); 383 384 if (nvm->type == e1000_nvm_eeprom_microwire) { 385 /* Clear SK and DI */ 386 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 387 E1000_WRITE_REG(hw, E1000_EECD, eecd); 388 /* Set CS */ 389 eecd |= E1000_EECD_CS; 390 E1000_WRITE_REG(hw, E1000_EECD, eecd); 391 } else if (nvm->type == e1000_nvm_eeprom_spi) { 392 u16 timeout = NVM_MAX_RETRY_SPI; 393 394 /* Clear SK and CS */ 395 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 396 E1000_WRITE_REG(hw, E1000_EECD, eecd); 397 E1000_WRITE_FLUSH(hw); 398 usec_delay(1); 399 400 /* Read "Status Register" repeatedly until the LSB is cleared. 401 * The EEPROM will signal that the command has been completed 402 * by clearing bit 0 of the internal status register. If it's 403 * not cleared within 'timeout', then error out. 404 */ 405 while (timeout) { 406 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 407 hw->nvm.opcode_bits); 408 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 409 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 410 break; 411 412 usec_delay(5); 413 e1000_standby_nvm(hw); 414 timeout--; 415 } 416 417 if (!timeout) { 418 DEBUGOUT("SPI NVM Status error\n"); 419 return -E1000_ERR_NVM; 420 } 421 } 422 423 return E1000_SUCCESS; 424 } 425 426 /** 427 * e1000_read_nvm_spi - Read EEPROM's using SPI 428 * @hw: pointer to the HW structure 429 * @offset: offset of word in the EEPROM to read 430 * @words: number of words to read 431 * @data: word read from the EEPROM 432 * 433 * Reads a 16 bit word from the EEPROM. 434 **/ 435 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 436 { 437 struct e1000_nvm_info *nvm = &hw->nvm; 438 u32 i = 0; 439 s32 ret_val; 440 u16 word_in; 441 u8 read_opcode = NVM_READ_OPCODE_SPI; 442 443 DEBUGFUNC("e1000_read_nvm_spi"); 444 445 /* A check for invalid values: offset too large, too many words, 446 * and not enough words. 447 */ 448 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 449 (words == 0)) { 450 DEBUGOUT("nvm parameter(s) out of bounds\n"); 451 return -E1000_ERR_NVM; 452 } 453 454 ret_val = nvm->ops.acquire(hw); 455 if (ret_val) 456 return ret_val; 457 458 ret_val = e1000_ready_nvm_eeprom(hw); 459 if (ret_val) 460 goto release; 461 462 e1000_standby_nvm(hw); 463 464 if ((nvm->address_bits == 8) && (offset >= 128)) 465 read_opcode |= NVM_A8_OPCODE_SPI; 466 467 /* Send the READ command (opcode + addr) */ 468 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 469 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 470 471 /* Read the data. SPI NVMs increment the address with each byte 472 * read and will roll over if reading beyond the end. This allows 473 * us to read the whole NVM from any offset 474 */ 475 for (i = 0; i < words; i++) { 476 word_in = e1000_shift_in_eec_bits(hw, 16); 477 data[i] = (word_in >> 8) | (word_in << 8); 478 } 479 480 release: 481 nvm->ops.release(hw); 482 483 return ret_val; 484 } 485 486 /** 487 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 488 * @hw: pointer to the HW structure 489 * @offset: offset of word in the EEPROM to read 490 * @words: number of words to read 491 * @data: word read from the EEPROM 492 * 493 * Reads a 16 bit word from the EEPROM. 494 **/ 495 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 496 u16 *data) 497 { 498 struct e1000_nvm_info *nvm = &hw->nvm; 499 u32 i = 0; 500 s32 ret_val; 501 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 502 503 DEBUGFUNC("e1000_read_nvm_microwire"); 504 505 /* A check for invalid values: offset too large, too many words, 506 * and not enough words. 507 */ 508 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 509 (words == 0)) { 510 DEBUGOUT("nvm parameter(s) out of bounds\n"); 511 return -E1000_ERR_NVM; 512 } 513 514 ret_val = nvm->ops.acquire(hw); 515 if (ret_val) 516 return ret_val; 517 518 ret_val = e1000_ready_nvm_eeprom(hw); 519 if (ret_val) 520 goto release; 521 522 for (i = 0; i < words; i++) { 523 /* Send the READ command (opcode + addr) */ 524 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 525 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 526 nvm->address_bits); 527 528 /* Read the data. For microwire, each word requires the 529 * overhead of setup and tear-down. 530 */ 531 data[i] = e1000_shift_in_eec_bits(hw, 16); 532 e1000_standby_nvm(hw); 533 } 534 535 release: 536 nvm->ops.release(hw); 537 538 return ret_val; 539 } 540 541 /** 542 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 543 * @hw: pointer to the HW structure 544 * @offset: offset of word in the EEPROM to read 545 * @words: number of words to read 546 * @data: word read from the EEPROM 547 * 548 * Reads a 16 bit word from the EEPROM using the EERD register. 549 **/ 550 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 551 { 552 struct e1000_nvm_info *nvm = &hw->nvm; 553 u32 i, eerd = 0; 554 s32 ret_val = E1000_SUCCESS; 555 556 DEBUGFUNC("e1000_read_nvm_eerd"); 557 558 /* A check for invalid values: offset too large, too many words, 559 * too many words for the offset, and not enough words. 560 */ 561 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 562 (words == 0)) { 563 DEBUGOUT("nvm parameter(s) out of bounds\n"); 564 return -E1000_ERR_NVM; 565 } 566 567 for (i = 0; i < words; i++) { 568 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 569 E1000_NVM_RW_REG_START; 570 571 E1000_WRITE_REG(hw, E1000_EERD, eerd); 572 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 573 if (ret_val) 574 break; 575 576 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 577 E1000_NVM_RW_REG_DATA); 578 } 579 580 return ret_val; 581 } 582 583 /** 584 * e1000_write_nvm_spi - Write to EEPROM using SPI 585 * @hw: pointer to the HW structure 586 * @offset: offset within the EEPROM to be written to 587 * @words: number of words to write 588 * @data: 16 bit word(s) to be written to the EEPROM 589 * 590 * Writes data to EEPROM at offset using SPI interface. 591 * 592 * If e1000_update_nvm_checksum is not called after this function , the 593 * EEPROM will most likely contain an invalid checksum. 594 **/ 595 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 596 { 597 struct e1000_nvm_info *nvm = &hw->nvm; 598 s32 ret_val = -E1000_ERR_NVM; 599 u16 widx = 0; 600 601 DEBUGFUNC("e1000_write_nvm_spi"); 602 603 /* A check for invalid values: offset too large, too many words, 604 * and not enough words. 605 */ 606 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 607 (words == 0)) { 608 DEBUGOUT("nvm parameter(s) out of bounds\n"); 609 return -E1000_ERR_NVM; 610 } 611 612 while (widx < words) { 613 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 614 615 ret_val = nvm->ops.acquire(hw); 616 if (ret_val) 617 return ret_val; 618 619 ret_val = e1000_ready_nvm_eeprom(hw); 620 if (ret_val) { 621 nvm->ops.release(hw); 622 return ret_val; 623 } 624 625 e1000_standby_nvm(hw); 626 627 /* Send the WRITE ENABLE command (8 bit opcode) */ 628 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 629 nvm->opcode_bits); 630 631 e1000_standby_nvm(hw); 632 633 /* Some SPI eeproms use the 8th address bit embedded in the 634 * opcode 635 */ 636 if ((nvm->address_bits == 8) && (offset >= 128)) 637 write_opcode |= NVM_A8_OPCODE_SPI; 638 639 /* Send the Write command (8-bit opcode + addr) */ 640 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 641 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 642 nvm->address_bits); 643 644 /* Loop to allow for up to whole page write of eeprom */ 645 while (widx < words) { 646 u16 word_out = data[widx]; 647 word_out = (word_out >> 8) | (word_out << 8); 648 e1000_shift_out_eec_bits(hw, word_out, 16); 649 widx++; 650 651 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 652 e1000_standby_nvm(hw); 653 break; 654 } 655 } 656 msec_delay(10); 657 nvm->ops.release(hw); 658 } 659 660 return ret_val; 661 } 662 663 /** 664 * e1000_write_nvm_microwire - Writes EEPROM using microwire 665 * @hw: pointer to the HW structure 666 * @offset: offset within the EEPROM to be written to 667 * @words: number of words to write 668 * @data: 16 bit word(s) to be written to the EEPROM 669 * 670 * Writes data to EEPROM at offset using microwire interface. 671 * 672 * If e1000_update_nvm_checksum is not called after this function , the 673 * EEPROM will most likely contain an invalid checksum. 674 **/ 675 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 676 u16 *data) 677 { 678 struct e1000_nvm_info *nvm = &hw->nvm; 679 s32 ret_val; 680 u32 eecd; 681 u16 words_written = 0; 682 u16 widx = 0; 683 684 DEBUGFUNC("e1000_write_nvm_microwire"); 685 686 /* A check for invalid values: offset too large, too many words, 687 * and not enough words. 688 */ 689 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 690 (words == 0)) { 691 DEBUGOUT("nvm parameter(s) out of bounds\n"); 692 return -E1000_ERR_NVM; 693 } 694 695 ret_val = nvm->ops.acquire(hw); 696 if (ret_val) 697 return ret_val; 698 699 ret_val = e1000_ready_nvm_eeprom(hw); 700 if (ret_val) 701 goto release; 702 703 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 704 (u16)(nvm->opcode_bits + 2)); 705 706 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 707 708 e1000_standby_nvm(hw); 709 710 while (words_written < words) { 711 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 712 nvm->opcode_bits); 713 714 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 715 nvm->address_bits); 716 717 e1000_shift_out_eec_bits(hw, data[words_written], 16); 718 719 e1000_standby_nvm(hw); 720 721 for (widx = 0; widx < 200; widx++) { 722 eecd = E1000_READ_REG(hw, E1000_EECD); 723 if (eecd & E1000_EECD_DO) 724 break; 725 usec_delay(50); 726 } 727 728 if (widx == 200) { 729 DEBUGOUT("NVM Write did not complete\n"); 730 ret_val = -E1000_ERR_NVM; 731 goto release; 732 } 733 734 e1000_standby_nvm(hw); 735 736 words_written++; 737 } 738 739 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 740 (u16)(nvm->opcode_bits + 2)); 741 742 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 743 744 release: 745 nvm->ops.release(hw); 746 747 return ret_val; 748 } 749 750 /** 751 * e1000_read_pba_string_generic - Read device part number 752 * @hw: pointer to the HW structure 753 * @pba_num: pointer to device part number 754 * @pba_num_size: size of part number buffer 755 * 756 * Reads the product board assembly (PBA) number from the EEPROM and stores 757 * the value in pba_num. 758 **/ 759 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 760 u32 pba_num_size) 761 { 762 s32 ret_val; 763 u16 nvm_data; 764 u16 pba_ptr; 765 u16 offset; 766 u16 length; 767 768 DEBUGFUNC("e1000_read_pba_string_generic"); 769 770 if (pba_num == NULL) { 771 DEBUGOUT("PBA string buffer was null\n"); 772 return -E1000_ERR_INVALID_ARGUMENT; 773 } 774 775 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 776 if (ret_val) { 777 DEBUGOUT("NVM Read Error\n"); 778 return ret_val; 779 } 780 781 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 782 if (ret_val) { 783 DEBUGOUT("NVM Read Error\n"); 784 return ret_val; 785 } 786 787 /* if nvm_data is not ptr guard the PBA must be in legacy format which 788 * means pba_ptr is actually our second data word for the PBA number 789 * and we can decode it into an ascii string 790 */ 791 if (nvm_data != NVM_PBA_PTR_GUARD) { 792 DEBUGOUT("NVM PBA number is not stored as string\n"); 793 794 /* make sure callers buffer is big enough to store the PBA */ 795 if (pba_num_size < E1000_PBANUM_LENGTH) { 796 DEBUGOUT("PBA string buffer too small\n"); 797 return E1000_ERR_NO_SPACE; 798 } 799 800 /* extract hex string from data and pba_ptr */ 801 pba_num[0] = (nvm_data >> 12) & 0xF; 802 pba_num[1] = (nvm_data >> 8) & 0xF; 803 pba_num[2] = (nvm_data >> 4) & 0xF; 804 pba_num[3] = nvm_data & 0xF; 805 pba_num[4] = (pba_ptr >> 12) & 0xF; 806 pba_num[5] = (pba_ptr >> 8) & 0xF; 807 pba_num[6] = '-'; 808 pba_num[7] = 0; 809 pba_num[8] = (pba_ptr >> 4) & 0xF; 810 pba_num[9] = pba_ptr & 0xF; 811 812 /* put a null character on the end of our string */ 813 pba_num[10] = '\0'; 814 815 /* switch all the data but the '-' to hex char */ 816 for (offset = 0; offset < 10; offset++) { 817 if (pba_num[offset] < 0xA) 818 pba_num[offset] += '0'; 819 else if (pba_num[offset] < 0x10) 820 pba_num[offset] += 'A' - 0xA; 821 } 822 823 return E1000_SUCCESS; 824 } 825 826 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 827 if (ret_val) { 828 DEBUGOUT("NVM Read Error\n"); 829 return ret_val; 830 } 831 832 if (length == 0xFFFF || length == 0) { 833 DEBUGOUT("NVM PBA number section invalid length\n"); 834 return -E1000_ERR_NVM_PBA_SECTION; 835 } 836 /* check if pba_num buffer is big enough */ 837 if (pba_num_size < (((u32)length * 2) - 1)) { 838 DEBUGOUT("PBA string buffer too small\n"); 839 return -E1000_ERR_NO_SPACE; 840 } 841 842 /* trim pba length from start of string */ 843 pba_ptr++; 844 length--; 845 846 for (offset = 0; offset < length; offset++) { 847 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 848 if (ret_val) { 849 DEBUGOUT("NVM Read Error\n"); 850 return ret_val; 851 } 852 pba_num[offset * 2] = (u8)(nvm_data >> 8); 853 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 854 } 855 pba_num[offset * 2] = '\0'; 856 857 return E1000_SUCCESS; 858 } 859 860 /** 861 * e1000_read_pba_length_generic - Read device part number length 862 * @hw: pointer to the HW structure 863 * @pba_num_size: size of part number buffer 864 * 865 * Reads the product board assembly (PBA) number length from the EEPROM and 866 * stores the value in pba_num_size. 867 **/ 868 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) 869 { 870 s32 ret_val; 871 u16 nvm_data; 872 u16 pba_ptr; 873 u16 length; 874 875 DEBUGFUNC("e1000_read_pba_length_generic"); 876 877 if (pba_num_size == NULL) { 878 DEBUGOUT("PBA buffer size was null\n"); 879 return -E1000_ERR_INVALID_ARGUMENT; 880 } 881 882 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 883 if (ret_val) { 884 DEBUGOUT("NVM Read Error\n"); 885 return ret_val; 886 } 887 888 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 889 if (ret_val) { 890 DEBUGOUT("NVM Read Error\n"); 891 return ret_val; 892 } 893 894 /* if data is not ptr guard the PBA must be in legacy format */ 895 if (nvm_data != NVM_PBA_PTR_GUARD) { 896 *pba_num_size = E1000_PBANUM_LENGTH; 897 return E1000_SUCCESS; 898 } 899 900 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 901 if (ret_val) { 902 DEBUGOUT("NVM Read Error\n"); 903 return ret_val; 904 } 905 906 if (length == 0xFFFF || length == 0) { 907 DEBUGOUT("NVM PBA number section invalid length\n"); 908 return -E1000_ERR_NVM_PBA_SECTION; 909 } 910 911 /* Convert from length in u16 values to u8 chars, add 1 for NULL, 912 * and subtract 2 because length field is included in length. 913 */ 914 *pba_num_size = ((u32)length * 2) - 1; 915 916 return E1000_SUCCESS; 917 } 918 919 920 /** 921 * e1000_read_pba_raw 922 * @hw: pointer to the HW structure 923 * @eeprom_buf: optional pointer to EEPROM image 924 * @eeprom_buf_size: size of EEPROM image in words 925 * @max_pba_block_size: PBA block size limit 926 * @pba: pointer to output PBA structure 927 * 928 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 929 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 930 * 931 **/ 932 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 933 u32 eeprom_buf_size, u16 max_pba_block_size, 934 struct e1000_pba *pba) 935 { 936 s32 ret_val; 937 u16 pba_block_size; 938 939 if (pba == NULL) 940 return -E1000_ERR_PARAM; 941 942 if (eeprom_buf == NULL) { 943 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, 944 &pba->word[0]); 945 if (ret_val) 946 return ret_val; 947 } else { 948 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 949 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 950 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 951 } else { 952 return -E1000_ERR_PARAM; 953 } 954 } 955 956 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 957 if (pba->pba_block == NULL) 958 return -E1000_ERR_PARAM; 959 960 ret_val = e1000_get_pba_block_size(hw, eeprom_buf, 961 eeprom_buf_size, 962 &pba_block_size); 963 if (ret_val) 964 return ret_val; 965 966 if (pba_block_size > max_pba_block_size) 967 return -E1000_ERR_PARAM; 968 969 if (eeprom_buf == NULL) { 970 ret_val = e1000_read_nvm(hw, pba->word[1], 971 pba_block_size, 972 pba->pba_block); 973 if (ret_val) 974 return ret_val; 975 } else { 976 if (eeprom_buf_size > (u32)(pba->word[1] + 977 pba->pba_block[0])) { 978 memcpy(pba->pba_block, 979 &eeprom_buf[pba->word[1]], 980 pba_block_size * sizeof(u16)); 981 } else { 982 return -E1000_ERR_PARAM; 983 } 984 } 985 } 986 987 return E1000_SUCCESS; 988 } 989 990 /** 991 * e1000_write_pba_raw 992 * @hw: pointer to the HW structure 993 * @eeprom_buf: optional pointer to EEPROM image 994 * @eeprom_buf_size: size of EEPROM image in words 995 * @pba: pointer to PBA structure 996 * 997 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 998 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 999 * 1000 **/ 1001 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 1002 u32 eeprom_buf_size, struct e1000_pba *pba) 1003 { 1004 s32 ret_val; 1005 1006 if (pba == NULL) 1007 return -E1000_ERR_PARAM; 1008 1009 if (eeprom_buf == NULL) { 1010 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2, 1011 &pba->word[0]); 1012 if (ret_val) 1013 return ret_val; 1014 } else { 1015 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1016 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0]; 1017 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1]; 1018 } else { 1019 return -E1000_ERR_PARAM; 1020 } 1021 } 1022 1023 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 1024 if (pba->pba_block == NULL) 1025 return -E1000_ERR_PARAM; 1026 1027 if (eeprom_buf == NULL) { 1028 ret_val = e1000_write_nvm(hw, pba->word[1], 1029 pba->pba_block[0], 1030 pba->pba_block); 1031 if (ret_val) 1032 return ret_val; 1033 } else { 1034 if (eeprom_buf_size > (u32)(pba->word[1] + 1035 pba->pba_block[0])) { 1036 memcpy(&eeprom_buf[pba->word[1]], 1037 pba->pba_block, 1038 pba->pba_block[0] * sizeof(u16)); 1039 } else { 1040 return -E1000_ERR_PARAM; 1041 } 1042 } 1043 } 1044 1045 return E1000_SUCCESS; 1046 } 1047 1048 /** 1049 * e1000_get_pba_block_size 1050 * @hw: pointer to the HW structure 1051 * @eeprom_buf: optional pointer to EEPROM image 1052 * @eeprom_buf_size: size of EEPROM image in words 1053 * @pba_data_size: pointer to output variable 1054 * 1055 * Returns the size of the PBA block in words. Function operates on EEPROM 1056 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 1057 * EEPROM device. 1058 * 1059 **/ 1060 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, 1061 u32 eeprom_buf_size, u16 *pba_block_size) 1062 { 1063 s32 ret_val; 1064 u16 pba_word[2]; 1065 u16 length; 1066 1067 DEBUGFUNC("e1000_get_pba_block_size"); 1068 1069 if (eeprom_buf == NULL) { 1070 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]); 1071 if (ret_val) 1072 return ret_val; 1073 } else { 1074 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1075 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 1076 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 1077 } else { 1078 return -E1000_ERR_PARAM; 1079 } 1080 } 1081 1082 if (pba_word[0] == NVM_PBA_PTR_GUARD) { 1083 if (eeprom_buf == NULL) { 1084 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1, 1085 &length); 1086 if (ret_val) 1087 return ret_val; 1088 } else { 1089 if (eeprom_buf_size > pba_word[1]) 1090 length = eeprom_buf[pba_word[1] + 0]; 1091 else 1092 return -E1000_ERR_PARAM; 1093 } 1094 1095 if (length == 0xFFFF || length == 0) 1096 return -E1000_ERR_NVM_PBA_SECTION; 1097 } else { 1098 /* PBA number in legacy format, there is no PBA Block. */ 1099 length = 0; 1100 } 1101 1102 if (pba_block_size != NULL) 1103 *pba_block_size = length; 1104 1105 return E1000_SUCCESS; 1106 } 1107 1108 /** 1109 * e1000_read_mac_addr_generic - Read device MAC address 1110 * @hw: pointer to the HW structure 1111 * 1112 * Reads the device MAC address from the EEPROM and stores the value. 1113 * Since devices with two ports use the same EEPROM, we increment the 1114 * last bit in the MAC address for the second port. 1115 **/ 1116 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 1117 { 1118 u32 rar_high; 1119 u32 rar_low; 1120 u16 i; 1121 1122 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 1123 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 1124 1125 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 1126 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 1127 1128 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 1129 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 1130 1131 for (i = 0; i < ETH_ADDR_LEN; i++) 1132 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1133 1134 return E1000_SUCCESS; 1135 } 1136 1137 /** 1138 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 1139 * @hw: pointer to the HW structure 1140 * 1141 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 1142 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 1143 **/ 1144 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 1145 { 1146 s32 ret_val; 1147 u16 checksum = 0; 1148 u16 i, nvm_data; 1149 1150 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 1151 1152 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 1153 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1154 if (ret_val) { 1155 DEBUGOUT("NVM Read Error\n"); 1156 return ret_val; 1157 } 1158 checksum += nvm_data; 1159 } 1160 1161 if (checksum != (u16) NVM_SUM) { 1162 DEBUGOUT("NVM Checksum Invalid\n"); 1163 return -E1000_ERR_NVM; 1164 } 1165 1166 return E1000_SUCCESS; 1167 } 1168 1169 /** 1170 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 1171 * @hw: pointer to the HW structure 1172 * 1173 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1174 * up to the checksum. Then calculates the EEPROM checksum and writes the 1175 * value to the EEPROM. 1176 **/ 1177 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 1178 { 1179 s32 ret_val; 1180 u16 checksum = 0; 1181 u16 i, nvm_data; 1182 1183 DEBUGFUNC("e1000_update_nvm_checksum"); 1184 1185 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 1186 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1187 if (ret_val) { 1188 DEBUGOUT("NVM Read Error while updating checksum.\n"); 1189 return ret_val; 1190 } 1191 checksum += nvm_data; 1192 } 1193 checksum = (u16) NVM_SUM - checksum; 1194 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 1195 if (ret_val) 1196 DEBUGOUT("NVM Write Error while updating checksum.\n"); 1197 1198 return ret_val; 1199 } 1200 1201 /** 1202 * e1000_reload_nvm_generic - Reloads EEPROM 1203 * @hw: pointer to the HW structure 1204 * 1205 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 1206 * extended control register. 1207 **/ 1208 static void e1000_reload_nvm_generic(struct e1000_hw *hw) 1209 { 1210 u32 ctrl_ext; 1211 1212 DEBUGFUNC("e1000_reload_nvm_generic"); 1213 1214 usec_delay(10); 1215 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1216 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1217 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1218 E1000_WRITE_FLUSH(hw); 1219 } 1220 1221 1222