1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #ifndef _E1000_MANAGE_H_ 36 #define _E1000_MANAGE_H_ 37 38 bool e1000_check_mng_mode_generic(struct e1000_hw *hw); 39 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw); 40 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw); 41 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, 42 u16 length, u16 offset, u8 *sum); 43 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw, 44 struct e1000_host_mng_command_header *hdr); 45 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, 46 u8 *buffer, u16 length); 47 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw); 48 u8 e1000_calculate_checksum(u8 *buffer, u32 length); 49 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length); 50 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length); 51 52 enum e1000_mng_mode { 53 e1000_mng_mode_none = 0, 54 e1000_mng_mode_asf, 55 e1000_mng_mode_pt, 56 e1000_mng_mode_ipmi, 57 e1000_mng_mode_host_if_only 58 }; 59 60 #define E1000_FACTPS_MNGCG 0x20000000 61 62 #define E1000_FWSM_MODE_MASK 0xE 63 #define E1000_FWSM_MODE_SHIFT 1 64 #define E1000_FWSM_FW_VALID 0x00008000 65 #define E1000_FWSM_HI_EN_ONLY_MODE 0x4 66 67 #define E1000_MNG_IAMT_MODE 0x3 68 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 69 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 70 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 71 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 72 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 73 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 74 75 #define E1000_VFTA_ENTRY_SHIFT 5 76 #define E1000_VFTA_ENTRY_MASK 0x7F 77 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 78 79 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 80 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 81 #define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI cmd limit */ 82 #define E1000_HI_FW_BASE_ADDRESS 0x10000 83 #define E1000_HI_FW_MAX_LENGTH (64 * 1024) /* Num of bytes */ 84 #define E1000_HI_FW_BLOCK_DWORD_LENGTH 256 /* Num of DWORDs per page */ 85 #define E1000_HICR_MEMORY_BASE_EN 0x200 /* MB Enable bit - RO */ 86 #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 87 /* Driver sets this bit when done to put command in RAM */ 88 #define E1000_HICR_C 0x02 89 #define E1000_HICR_SV 0x04 /* Status Validity */ 90 #define E1000_HICR_FW_RESET_ENABLE 0x40 91 #define E1000_HICR_FW_RESET 0x80 92 93 /* Intel(R) Active Management Technology signature */ 94 #define E1000_IAMT_SIGNATURE 0x544D4149 95 96 #endif 97