1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 /** 38 * e1000_init_mac_ops_generic - Initialize MAC function pointers 39 * @hw: pointer to the HW structure 40 * 41 * Setups up the function pointers to no-op functions 42 **/ 43 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 44 { 45 struct e1000_mac_info *mac = &hw->mac; 46 DEBUGFUNC("e1000_init_mac_ops_generic"); 47 48 /* General Setup */ 49 mac->ops.init_params = e1000_null_ops_generic; 50 mac->ops.init_hw = e1000_null_ops_generic; 51 mac->ops.reset_hw = e1000_null_ops_generic; 52 mac->ops.setup_physical_interface = e1000_null_ops_generic; 53 mac->ops.get_bus_info = e1000_null_ops_generic; 54 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 55 mac->ops.remove_device = e1000_remove_device_generic; 56 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 57 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 58 /* LED */ 59 mac->ops.cleanup_led = e1000_null_ops_generic; 60 mac->ops.setup_led = e1000_null_ops_generic; 61 mac->ops.blink_led = e1000_null_ops_generic; 62 mac->ops.led_on = e1000_null_ops_generic; 63 mac->ops.led_off = e1000_null_ops_generic; 64 /* LINK */ 65 mac->ops.setup_link = e1000_null_ops_generic; 66 mac->ops.get_link_up_info = e1000_null_link_info; 67 mac->ops.check_for_link = e1000_null_ops_generic; 68 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 69 /* Management */ 70 mac->ops.check_mng_mode = e1000_null_mng_mode; 71 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 72 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 73 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 74 /* VLAN, MC, etc. */ 75 mac->ops.update_mc_addr_list = e1000_null_update_mc; 76 mac->ops.clear_vfta = e1000_null_mac_generic; 77 mac->ops.write_vfta = e1000_null_write_vfta; 78 mac->ops.mta_set = e1000_null_mta_set; 79 mac->ops.rar_set = e1000_rar_set_generic; 80 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 81 } 82 83 /** 84 * e1000_null_ops_generic - No-op function, returns 0 85 * @hw: pointer to the HW structure 86 **/ 87 s32 e1000_null_ops_generic(struct e1000_hw *hw) 88 { 89 DEBUGFUNC("e1000_null_ops_generic"); 90 return E1000_SUCCESS; 91 } 92 93 /** 94 * e1000_null_mac_generic - No-op function, return void 95 * @hw: pointer to the HW structure 96 **/ 97 void e1000_null_mac_generic(struct e1000_hw *hw) 98 { 99 DEBUGFUNC("e1000_null_mac_generic"); 100 return; 101 } 102 103 /** 104 * e1000_null_link_info - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 108 { 109 DEBUGFUNC("e1000_null_link_info"); 110 return E1000_SUCCESS; 111 } 112 113 /** 114 * e1000_null_mng_mode - No-op function, return FALSE 115 * @hw: pointer to the HW structure 116 **/ 117 bool e1000_null_mng_mode(struct e1000_hw *hw) 118 { 119 DEBUGFUNC("e1000_null_mng_mode"); 120 return FALSE; 121 } 122 123 /** 124 * e1000_null_update_mc - No-op function, return void 125 * @hw: pointer to the HW structure 126 **/ 127 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a, u32 b, u32 c) 128 { 129 DEBUGFUNC("e1000_null_update_mc"); 130 return; 131 } 132 133 /** 134 * e1000_null_write_vfta - No-op function, return void 135 * @hw: pointer to the HW structure 136 **/ 137 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 138 { 139 DEBUGFUNC("e1000_null_write_vfta"); 140 return; 141 } 142 143 /** 144 * e1000_null_set_mta - No-op function, return void 145 * @hw: pointer to the HW structure 146 **/ 147 void e1000_null_mta_set(struct e1000_hw *hw, u32 a) 148 { 149 DEBUGFUNC("e1000_null_mta_set"); 150 return; 151 } 152 153 /** 154 * e1000_null_rar_set - No-op function, return void 155 * @hw: pointer to the HW structure 156 **/ 157 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 158 { 159 DEBUGFUNC("e1000_null_rar_set"); 160 return; 161 } 162 163 /** 164 * e1000_remove_device_generic - Free device specific structure 165 * @hw: pointer to the HW structure 166 * 167 * If a device specific structure was allocated, this function will 168 * free it. 169 **/ 170 void e1000_remove_device_generic(struct e1000_hw *hw) 171 { 172 DEBUGFUNC("e1000_remove_device_generic"); 173 174 /* Freeing the dev_spec member of e1000_hw structure */ 175 e1000_free_dev_spec_struct(hw); 176 } 177 178 /** 179 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 180 * @hw: pointer to the HW structure 181 * 182 * Determines and stores the system bus information for a particular 183 * network interface. The following bus information is determined and stored: 184 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 185 **/ 186 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 187 { 188 struct e1000_bus_info *bus = &hw->bus; 189 u32 status = E1000_READ_REG(hw, E1000_STATUS); 190 s32 ret_val = E1000_SUCCESS; 191 u16 pci_header_type; 192 193 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 194 195 /* PCI or PCI-X? */ 196 bus->type = (status & E1000_STATUS_PCIX_MODE) 197 ? e1000_bus_type_pcix 198 : e1000_bus_type_pci; 199 200 /* Bus speed */ 201 if (bus->type == e1000_bus_type_pci) { 202 bus->speed = (status & E1000_STATUS_PCI66) 203 ? e1000_bus_speed_66 204 : e1000_bus_speed_33; 205 } else { 206 switch (status & E1000_STATUS_PCIX_SPEED) { 207 case E1000_STATUS_PCIX_SPEED_66: 208 bus->speed = e1000_bus_speed_66; 209 break; 210 case E1000_STATUS_PCIX_SPEED_100: 211 bus->speed = e1000_bus_speed_100; 212 break; 213 case E1000_STATUS_PCIX_SPEED_133: 214 bus->speed = e1000_bus_speed_133; 215 break; 216 default: 217 bus->speed = e1000_bus_speed_reserved; 218 break; 219 } 220 } 221 222 /* Bus width */ 223 bus->width = (status & E1000_STATUS_BUS64) 224 ? e1000_bus_width_64 225 : e1000_bus_width_32; 226 227 /* Which PCI(-X) function? */ 228 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 229 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 230 bus->func = (status & E1000_STATUS_FUNC_MASK) 231 >> E1000_STATUS_FUNC_SHIFT; 232 else 233 bus->func = 0; 234 235 return ret_val; 236 } 237 238 /** 239 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 240 * @hw: pointer to the HW structure 241 * 242 * Determines and stores the system bus information for a particular 243 * network interface. The following bus information is determined and stored: 244 * bus speed, bus width, type (PCIe), and PCIe function. 245 **/ 246 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 247 { 248 struct e1000_bus_info *bus = &hw->bus; 249 s32 ret_val; 250 u32 status; 251 u16 pcie_link_status, pci_header_type; 252 253 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 254 255 bus->type = e1000_bus_type_pci_express; 256 bus->speed = e1000_bus_speed_2500; 257 258 ret_val = e1000_read_pcie_cap_reg(hw, 259 PCIE_LINK_STATUS, 260 &pcie_link_status); 261 if (ret_val) 262 bus->width = e1000_bus_width_unknown; 263 else 264 bus->width = (enum e1000_bus_width)((pcie_link_status & 265 PCIE_LINK_WIDTH_MASK) >> 266 PCIE_LINK_WIDTH_SHIFT); 267 268 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 269 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 270 status = E1000_READ_REG(hw, E1000_STATUS); 271 bus->func = (status & E1000_STATUS_FUNC_MASK) 272 >> E1000_STATUS_FUNC_SHIFT; 273 } else { 274 bus->func = 0; 275 } 276 277 return E1000_SUCCESS; 278 } 279 280 /** 281 * e1000_clear_vfta_generic - Clear VLAN filter table 282 * @hw: pointer to the HW structure 283 * 284 * Clears the register array which contains the VLAN filter table by 285 * setting all the values to 0. 286 **/ 287 void e1000_clear_vfta_generic(struct e1000_hw *hw) 288 { 289 u32 offset; 290 291 DEBUGFUNC("e1000_clear_vfta_generic"); 292 293 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 294 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 295 E1000_WRITE_FLUSH(hw); 296 } 297 } 298 299 /** 300 * e1000_write_vfta_generic - Write value to VLAN filter table 301 * @hw: pointer to the HW structure 302 * @offset: register offset in VLAN filter table 303 * @value: register value written to VLAN filter table 304 * 305 * Writes value at the given offset in the register array which stores 306 * the VLAN filter table. 307 **/ 308 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 309 { 310 DEBUGFUNC("e1000_write_vfta_generic"); 311 312 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 313 E1000_WRITE_FLUSH(hw); 314 } 315 316 /** 317 * e1000_init_rx_addrs_generic - Initialize receive address's 318 * @hw: pointer to the HW structure 319 * @rar_count: receive address registers 320 * 321 * Setups the receive address registers by setting the base receive address 322 * register to the devices MAC address and clearing all the other receive 323 * address registers to 0. 324 **/ 325 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 326 { 327 u32 i; 328 329 DEBUGFUNC("e1000_init_rx_addrs_generic"); 330 331 /* Setup the receive address */ 332 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 333 334 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 335 336 /* Zero out the other (rar_entry_count - 1) receive addresses */ 337 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 338 for (i = 1; i < rar_count; i++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 340 E1000_WRITE_FLUSH(hw); 341 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 342 E1000_WRITE_FLUSH(hw); 343 } 344 } 345 346 /** 347 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 348 * @hw: pointer to the HW structure 349 * 350 * Checks the nvm for an alternate MAC address. An alternate MAC address 351 * can be setup by pre-boot software and must be treated like a permanent 352 * address and must override the actual permanent MAC address. If an 353 * alternate MAC address is found it is saved in the hw struct and 354 * programmed into RAR0 and the function returns success, otherwise the 355 * function returns an error. 356 **/ 357 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 358 { 359 u32 i; 360 s32 ret_val = E1000_SUCCESS; 361 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 362 u8 alt_mac_addr[ETH_ADDR_LEN]; 363 364 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 365 366 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 367 &nvm_alt_mac_addr_offset); 368 if (ret_val) { 369 DEBUGOUT("NVM Read Error\n"); 370 goto out; 371 } 372 373 if (nvm_alt_mac_addr_offset == 0xFFFF) { 374 ret_val = -(E1000_NOT_IMPLEMENTED); 375 goto out; 376 } 377 378 if (hw->bus.func == E1000_FUNC_1) 379 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16); 380 381 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 382 offset = nvm_alt_mac_addr_offset + (i >> 1); 383 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 384 if (ret_val) { 385 DEBUGOUT("NVM Read Error\n"); 386 goto out; 387 } 388 389 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 390 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 391 } 392 393 /* if multicast bit is set, the alternate address will not be used */ 394 if (alt_mac_addr[0] & 0x01) { 395 ret_val = -(E1000_NOT_IMPLEMENTED); 396 goto out; 397 } 398 399 for (i = 0; i < ETH_ADDR_LEN; i++) 400 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 401 402 hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); 403 404 out: 405 return ret_val; 406 } 407 408 /** 409 * e1000_rar_set_generic - Set receive address register 410 * @hw: pointer to the HW structure 411 * @addr: pointer to the receive address 412 * @index: receive address array register 413 * 414 * Sets the receive address array register at index to the address passed 415 * in by addr. 416 **/ 417 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 418 { 419 u32 rar_low, rar_high; 420 421 DEBUGFUNC("e1000_rar_set_generic"); 422 423 /* 424 * HW expects these in little endian so we reverse the byte order 425 * from network order (big endian) to little endian 426 */ 427 rar_low = ((u32) addr[0] | 428 ((u32) addr[1] << 8) | 429 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 430 431 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 432 433 /* If MAC address zero, no need to set the AV bit */ 434 if (rar_low || rar_high) { 435 if (!hw->mac.disable_av) 436 rar_high |= E1000_RAH_AV; 437 } 438 439 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 440 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 441 } 442 443 /** 444 * e1000_mta_set_generic - Set multicast filter table address 445 * @hw: pointer to the HW structure 446 * @hash_value: determines the MTA register and bit to set 447 * 448 * The multicast table address is a register array of 32-bit registers. 449 * The hash_value is used to determine what register the bit is in, the 450 * current value is read, the new bit is OR'd in and the new value is 451 * written back into the register. 452 **/ 453 void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 454 { 455 u32 hash_bit, hash_reg, mta; 456 457 DEBUGFUNC("e1000_mta_set_generic"); 458 /* 459 * The MTA is a register array of 32-bit registers. It is 460 * treated like an array of (32*mta_reg_count) bits. We want to 461 * set bit BitArray[hash_value]. So we figure out what register 462 * the bit is in, read it, OR in the new bit, then write 463 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 464 * mask to bits 31:5 of the hash value which gives us the 465 * register we're modifying. The hash bit within that register 466 * is determined by the lower 5 bits of the hash value. 467 */ 468 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 469 hash_bit = hash_value & 0x1F; 470 471 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 472 473 mta |= (1 << hash_bit); 474 475 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 476 E1000_WRITE_FLUSH(hw); 477 } 478 479 /** 480 * e1000_update_mc_addr_list_generic - Update Multicast addresses 481 * @hw: pointer to the HW structure 482 * @mc_addr_list: array of multicast addresses to program 483 * @mc_addr_count: number of multicast addresses to program 484 * @rar_used_count: the first RAR register free to program 485 * @rar_count: total number of supported Receive Address Registers 486 * 487 * Updates the Receive Address Registers and Multicast Table Array. 488 * The caller must have a packed mc_addr_list of multicast addresses. 489 * The parameter rar_count will usually be hw->mac.rar_entry_count 490 * unless there are workarounds that change this. 491 **/ 492 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 493 u8 *mc_addr_list, u32 mc_addr_count, 494 u32 rar_used_count, u32 rar_count) 495 { 496 u32 hash_value; 497 u32 i; 498 499 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 500 501 /* 502 * Load the first set of multicast addresses into the exact 503 * filters (RAR). If there are not enough to fill the RAR 504 * array, clear the filters. 505 */ 506 for (i = rar_used_count; i < rar_count; i++) { 507 if (mc_addr_count) { 508 hw->mac.ops.rar_set(hw, mc_addr_list, i); 509 mc_addr_count--; 510 mc_addr_list += ETH_ADDR_LEN; 511 } else { 512 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 513 E1000_WRITE_FLUSH(hw); 514 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 515 E1000_WRITE_FLUSH(hw); 516 } 517 } 518 519 /* Clear the old settings from the MTA */ 520 DEBUGOUT("Clearing MTA\n"); 521 for (i = 0; i < hw->mac.mta_reg_count; i++) { 522 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 523 E1000_WRITE_FLUSH(hw); 524 } 525 526 /* Load any remaining multicast addresses into the hash table. */ 527 for (; mc_addr_count > 0; mc_addr_count--) { 528 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 529 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 530 hw->mac.ops.mta_set(hw, hash_value); 531 mc_addr_list += ETH_ADDR_LEN; 532 } 533 } 534 535 /** 536 * e1000_hash_mc_addr_generic - Generate a multicast hash value 537 * @hw: pointer to the HW structure 538 * @mc_addr: pointer to a multicast address 539 * 540 * Generates a multicast address hash value which is used to determine 541 * the multicast filter table array address and new table value. See 542 * e1000_mta_set_generic() 543 **/ 544 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 545 { 546 u32 hash_value, hash_mask; 547 u8 bit_shift = 0; 548 549 DEBUGFUNC("e1000_hash_mc_addr_generic"); 550 551 /* Register count multiplied by bits per register */ 552 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 553 554 /* 555 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 556 * where 0xFF would still fall within the hash mask. 557 */ 558 while (hash_mask >> bit_shift != 0xFF) 559 bit_shift++; 560 561 /* 562 * The portion of the address that is used for the hash table 563 * is determined by the mc_filter_type setting. 564 * The algorithm is such that there is a total of 8 bits of shifting. 565 * The bit_shift for a mc_filter_type of 0 represents the number of 566 * left-shifts where the MSB of mc_addr[5] would still fall within 567 * the hash_mask. Case 0 does this exactly. Since there are a total 568 * of 8 bits of shifting, then mc_addr[4] will shift right the 569 * remaining number of bits. Thus 8 - bit_shift. The rest of the 570 * cases are a variation of this algorithm...essentially raising the 571 * number of bits to shift mc_addr[5] left, while still keeping the 572 * 8-bit shifting total. 573 * 574 * For example, given the following Destination MAC Address and an 575 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 576 * we can see that the bit_shift for case 0 is 4. These are the hash 577 * values resulting from each mc_filter_type... 578 * [0] [1] [2] [3] [4] [5] 579 * 01 AA 00 12 34 56 580 * LSB MSB 581 * 582 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 583 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 584 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 585 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 586 */ 587 switch (hw->mac.mc_filter_type) { 588 default: 589 case 0: 590 break; 591 case 1: 592 bit_shift += 1; 593 break; 594 case 2: 595 bit_shift += 2; 596 break; 597 case 3: 598 bit_shift += 4; 599 break; 600 } 601 602 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 603 (((u16) mc_addr[5]) << bit_shift))); 604 605 return hash_value; 606 } 607 608 /** 609 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 610 * @hw: pointer to the HW structure 611 * 612 * In certain situations, a system BIOS may report that the PCIx maximum 613 * memory read byte count (MMRBC) value is higher than than the actual 614 * value. We check the PCIx command register with the current PCIx status 615 * register. 616 **/ 617 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 618 { 619 u16 cmd_mmrbc; 620 u16 pcix_cmd; 621 u16 pcix_stat_hi_word; 622 u16 stat_mmrbc; 623 624 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 625 626 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 627 if (hw->bus.type != e1000_bus_type_pcix) 628 return; 629 630 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 631 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 632 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 633 PCIX_COMMAND_MMRBC_SHIFT; 634 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 635 PCIX_STATUS_HI_MMRBC_SHIFT; 636 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 637 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 638 if (cmd_mmrbc > stat_mmrbc) { 639 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 640 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 641 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 642 } 643 } 644 645 /** 646 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 647 * @hw: pointer to the HW structure 648 * 649 * Clears the base hardware counters by reading the counter registers. 650 **/ 651 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 652 { 653 volatile u32 temp; 654 655 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 656 657 temp = E1000_READ_REG(hw, E1000_CRCERRS); 658 temp = E1000_READ_REG(hw, E1000_SYMERRS); 659 temp = E1000_READ_REG(hw, E1000_MPC); 660 temp = E1000_READ_REG(hw, E1000_SCC); 661 temp = E1000_READ_REG(hw, E1000_ECOL); 662 temp = E1000_READ_REG(hw, E1000_MCC); 663 temp = E1000_READ_REG(hw, E1000_LATECOL); 664 temp = E1000_READ_REG(hw, E1000_COLC); 665 temp = E1000_READ_REG(hw, E1000_DC); 666 temp = E1000_READ_REG(hw, E1000_SEC); 667 temp = E1000_READ_REG(hw, E1000_RLEC); 668 temp = E1000_READ_REG(hw, E1000_XONRXC); 669 temp = E1000_READ_REG(hw, E1000_XONTXC); 670 temp = E1000_READ_REG(hw, E1000_XOFFRXC); 671 temp = E1000_READ_REG(hw, E1000_XOFFTXC); 672 temp = E1000_READ_REG(hw, E1000_FCRUC); 673 temp = E1000_READ_REG(hw, E1000_GPRC); 674 temp = E1000_READ_REG(hw, E1000_BPRC); 675 temp = E1000_READ_REG(hw, E1000_MPRC); 676 temp = E1000_READ_REG(hw, E1000_GPTC); 677 temp = E1000_READ_REG(hw, E1000_GORCL); 678 temp = E1000_READ_REG(hw, E1000_GORCH); 679 temp = E1000_READ_REG(hw, E1000_GOTCL); 680 temp = E1000_READ_REG(hw, E1000_GOTCH); 681 temp = E1000_READ_REG(hw, E1000_RNBC); 682 temp = E1000_READ_REG(hw, E1000_RUC); 683 temp = E1000_READ_REG(hw, E1000_RFC); 684 temp = E1000_READ_REG(hw, E1000_ROC); 685 temp = E1000_READ_REG(hw, E1000_RJC); 686 temp = E1000_READ_REG(hw, E1000_TORL); 687 temp = E1000_READ_REG(hw, E1000_TORH); 688 temp = E1000_READ_REG(hw, E1000_TOTL); 689 temp = E1000_READ_REG(hw, E1000_TOTH); 690 temp = E1000_READ_REG(hw, E1000_TPR); 691 temp = E1000_READ_REG(hw, E1000_TPT); 692 temp = E1000_READ_REG(hw, E1000_MPTC); 693 temp = E1000_READ_REG(hw, E1000_BPTC); 694 } 695 696 /** 697 * e1000_check_for_copper_link_generic - Check for link (Copper) 698 * @hw: pointer to the HW structure 699 * 700 * Checks to see of the link status of the hardware has changed. If a 701 * change in link status has been detected, then we read the PHY registers 702 * to get the current speed/duplex if link exists. 703 **/ 704 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 705 { 706 struct e1000_mac_info *mac = &hw->mac; 707 s32 ret_val; 708 bool link; 709 710 DEBUGFUNC("e1000_check_for_copper_link"); 711 712 /* 713 * We only want to go out to the PHY registers to see if Auto-Neg 714 * has completed and/or if our link status has changed. The 715 * get_link_status flag is set upon receiving a Link Status 716 * Change or Rx Sequence Error interrupt. 717 */ 718 if (!mac->get_link_status) { 719 ret_val = E1000_SUCCESS; 720 goto out; 721 } 722 723 /* 724 * First we want to see if the MII Status Register reports 725 * link. If so, then we want to get the current speed/duplex 726 * of the PHY. 727 */ 728 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 729 if (ret_val) 730 goto out; 731 732 if (!link) 733 goto out; /* No link detected */ 734 735 mac->get_link_status = FALSE; 736 737 /* 738 * Check if there was DownShift, must be checked 739 * immediately after link-up 740 */ 741 e1000_check_downshift_generic(hw); 742 743 /* 744 * If we are forcing speed/duplex, then we simply return since 745 * we have already determined whether we have link or not. 746 */ 747 if (!mac->autoneg) { 748 ret_val = -E1000_ERR_CONFIG; 749 goto out; 750 } 751 752 /* 753 * Auto-Neg is enabled. Auto Speed Detection takes care 754 * of MAC speed/duplex configuration. So we only need to 755 * configure Collision Distance in the MAC. 756 */ 757 e1000_config_collision_dist_generic(hw); 758 759 /* 760 * Configure Flow Control now that Auto-Neg has completed. 761 * First, we need to restore the desired flow control 762 * settings because we may have had to re-autoneg with a 763 * different link partner. 764 */ 765 ret_val = e1000_config_fc_after_link_up_generic(hw); 766 if (ret_val) { 767 DEBUGOUT("Error configuring flow control\n"); 768 } 769 770 out: 771 return ret_val; 772 } 773 774 /** 775 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 776 * @hw: pointer to the HW structure 777 * 778 * Checks for link up on the hardware. If link is not up and we have 779 * a signal, then we need to force link up. 780 **/ 781 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 782 { 783 struct e1000_mac_info *mac = &hw->mac; 784 u32 rxcw; 785 u32 ctrl; 786 u32 status; 787 s32 ret_val = E1000_SUCCESS; 788 789 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 790 791 ctrl = E1000_READ_REG(hw, E1000_CTRL); 792 status = E1000_READ_REG(hw, E1000_STATUS); 793 rxcw = E1000_READ_REG(hw, E1000_RXCW); 794 795 /* 796 * If we don't have link (auto-negotiation failed or link partner 797 * cannot auto-negotiate), the cable is plugged in (we have signal), 798 * and our link partner is not trying to auto-negotiate with us (we 799 * are receiving idles or data), we need to force link up. We also 800 * need to give auto-negotiation time to complete, in case the cable 801 * was just plugged in. The autoneg_failed flag does this. 802 */ 803 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 804 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 805 (!(rxcw & E1000_RXCW_C))) { 806 if (mac->autoneg_failed == 0) { 807 mac->autoneg_failed = 1; 808 goto out; 809 } 810 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 811 812 /* Disable auto-negotiation in the TXCW register */ 813 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 814 815 /* Force link-up and also force full-duplex. */ 816 ctrl = E1000_READ_REG(hw, E1000_CTRL); 817 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 818 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 819 820 /* Configure Flow Control after forcing link up. */ 821 ret_val = e1000_config_fc_after_link_up_generic(hw); 822 if (ret_val) { 823 DEBUGOUT("Error configuring flow control\n"); 824 goto out; 825 } 826 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 827 /* 828 * If we are forcing link and we are receiving /C/ ordered 829 * sets, re-enable auto-negotiation in the TXCW register 830 * and disable forced link in the Device Control register 831 * in an attempt to auto-negotiate with our link partner. 832 */ 833 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 834 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 835 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 836 837 mac->serdes_has_link = TRUE; 838 } 839 840 out: 841 return ret_val; 842 } 843 844 /** 845 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 846 * @hw: pointer to the HW structure 847 * 848 * Checks for link up on the hardware. If link is not up and we have 849 * a signal, then we need to force link up. 850 **/ 851 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 852 { 853 struct e1000_mac_info *mac = &hw->mac; 854 u32 rxcw; 855 u32 ctrl; 856 u32 status; 857 s32 ret_val = E1000_SUCCESS; 858 859 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 860 861 ctrl = E1000_READ_REG(hw, E1000_CTRL); 862 status = E1000_READ_REG(hw, E1000_STATUS); 863 rxcw = E1000_READ_REG(hw, E1000_RXCW); 864 865 /* 866 * If we don't have link (auto-negotiation failed or link partner 867 * cannot auto-negotiate), and our link partner is not trying to 868 * auto-negotiate with us (we are receiving idles or data), 869 * we need to force link up. We also need to give auto-negotiation 870 * time to complete. 871 */ 872 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 873 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 874 if (mac->autoneg_failed == 0) { 875 mac->autoneg_failed = 1; 876 goto out; 877 } 878 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 879 880 /* Disable auto-negotiation in the TXCW register */ 881 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 882 883 /* Force link-up and also force full-duplex. */ 884 ctrl = E1000_READ_REG(hw, E1000_CTRL); 885 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 886 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 887 888 /* Configure Flow Control after forcing link up. */ 889 ret_val = e1000_config_fc_after_link_up_generic(hw); 890 if (ret_val) { 891 DEBUGOUT("Error configuring flow control\n"); 892 goto out; 893 } 894 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 895 /* 896 * If we are forcing link and we are receiving /C/ ordered 897 * sets, re-enable auto-negotiation in the TXCW register 898 * and disable forced link in the Device Control register 899 * in an attempt to auto-negotiate with our link partner. 900 */ 901 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 902 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 903 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 904 905 mac->serdes_has_link = TRUE; 906 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 907 /* 908 * If we force link for non-auto-negotiation switch, check 909 * link status based on MAC synchronization for internal 910 * serdes media type. 911 */ 912 /* SYNCH bit and IV bit are sticky. */ 913 usec_delay(10); 914 rxcw = E1000_READ_REG(hw, E1000_RXCW); 915 if (rxcw & E1000_RXCW_SYNCH) { 916 if (!(rxcw & E1000_RXCW_IV)) { 917 mac->serdes_has_link = TRUE; 918 DEBUGOUT("SERDES: Link up - forced.\n"); 919 } 920 } else { 921 mac->serdes_has_link = FALSE; 922 DEBUGOUT("SERDES: Link down - force failed.\n"); 923 } 924 } 925 926 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 927 status = E1000_READ_REG(hw, E1000_STATUS); 928 if (status & E1000_STATUS_LU) { 929 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 930 usec_delay(10); 931 rxcw = E1000_READ_REG(hw, E1000_RXCW); 932 if (rxcw & E1000_RXCW_SYNCH) { 933 if (!(rxcw & E1000_RXCW_IV)) { 934 mac->serdes_has_link = TRUE; 935 DEBUGOUT("SERDES: Link up - autoneg " 936 "completed sucessfully.\n"); 937 } else { 938 mac->serdes_has_link = FALSE; 939 DEBUGOUT("SERDES: Link down - invalid" 940 "codewords detected in autoneg.\n"); 941 } 942 } else { 943 mac->serdes_has_link = FALSE; 944 DEBUGOUT("SERDES: Link down - no sync.\n"); 945 } 946 } else { 947 mac->serdes_has_link = FALSE; 948 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 949 } 950 } 951 952 out: 953 return ret_val; 954 } 955 956 /** 957 * e1000_setup_link_generic - Setup flow control and link settings 958 * @hw: pointer to the HW structure 959 * 960 * Determines which flow control settings to use, then configures flow 961 * control. Calls the appropriate media-specific link configuration 962 * function. Assuming the adapter has a valid link partner, a valid link 963 * should be established. Assumes the hardware has previously been reset 964 * and the transmitter and receiver are not enabled. 965 **/ 966 s32 e1000_setup_link_generic(struct e1000_hw *hw) 967 { 968 s32 ret_val = E1000_SUCCESS; 969 970 DEBUGFUNC("e1000_setup_link_generic"); 971 972 /* 973 * In the case of the phy reset being blocked, we already have a link. 974 * We do not need to set it up again. 975 */ 976 if (hw->phy.ops.check_reset_block) 977 if (hw->phy.ops.check_reset_block(hw)) 978 goto out; 979 980 /* 981 * If flow control is set to default, set flow control based on 982 * the EEPROM flow control settings. 983 */ 984 if (hw->fc.type == e1000_fc_default) { 985 ret_val = e1000_set_default_fc_generic(hw); 986 if (ret_val) 987 goto out; 988 } 989 990 /* 991 * We want to save off the original Flow Control configuration just 992 * in case we get disconnected and then reconnected into a different 993 * hub or switch with different Flow Control capabilities. 994 */ 995 hw->fc.original_type = hw->fc.type; 996 997 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 998 999 /* Call the necessary media_type subroutine to configure the link. */ 1000 ret_val = hw->mac.ops.setup_physical_interface(hw); 1001 if (ret_val) 1002 goto out; 1003 1004 /* 1005 * Initialize the flow control address, type, and PAUSE timer 1006 * registers to their default values. This is done even if flow 1007 * control is disabled, because it does not hurt anything to 1008 * initialize these registers. 1009 */ 1010 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1011 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1012 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1013 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1014 1015 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1016 1017 ret_val = e1000_set_fc_watermarks_generic(hw); 1018 1019 out: 1020 return ret_val; 1021 } 1022 1023 /** 1024 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1025 * @hw: pointer to the HW structure 1026 * 1027 * Configures collision distance and flow control for fiber and serdes 1028 * links. Upon successful setup, poll for link. 1029 **/ 1030 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1031 { 1032 u32 ctrl; 1033 s32 ret_val = E1000_SUCCESS; 1034 1035 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1036 1037 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1038 1039 /* Take the link out of reset */ 1040 ctrl &= ~E1000_CTRL_LRST; 1041 1042 e1000_config_collision_dist_generic(hw); 1043 1044 ret_val = e1000_commit_fc_settings_generic(hw); 1045 if (ret_val) 1046 goto out; 1047 1048 /* 1049 * Since auto-negotiation is enabled, take the link out of reset (the 1050 * link will be in reset, because we previously reset the chip). This 1051 * will restart auto-negotiation. If auto-negotiation is successful 1052 * then the link-up status bit will be set and the flow control enable 1053 * bits (RFCE and TFCE) will be set according to their negotiated value. 1054 */ 1055 DEBUGOUT("Auto-negotiation enabled\n"); 1056 1057 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1058 E1000_WRITE_FLUSH(hw); 1059 msec_delay(1); 1060 1061 /* 1062 * For these adapters, the SW definable pin 1 is set when the optics 1063 * detect a signal. If we have a signal, then poll for a "Link-Up" 1064 * indication. 1065 */ 1066 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1067 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1068 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1069 } else { 1070 DEBUGOUT("No signal detected\n"); 1071 } 1072 1073 out: 1074 return ret_val; 1075 } 1076 1077 /** 1078 * e1000_config_collision_dist_generic - Configure collision distance 1079 * @hw: pointer to the HW structure 1080 * 1081 * Configures the collision distance to the default value and is used 1082 * during link setup. Currently no func pointer exists and all 1083 * implementations are handled in the generic version of this function. 1084 **/ 1085 void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1086 { 1087 u32 tctl; 1088 1089 DEBUGFUNC("e1000_config_collision_dist_generic"); 1090 1091 tctl = E1000_READ_REG(hw, E1000_TCTL); 1092 1093 tctl &= ~E1000_TCTL_COLD; 1094 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1095 1096 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1097 E1000_WRITE_FLUSH(hw); 1098 } 1099 1100 /** 1101 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1102 * @hw: pointer to the HW structure 1103 * 1104 * Polls for link up by reading the status register, if link fails to come 1105 * up with auto-negotiation, then the link is forced if a signal is detected. 1106 **/ 1107 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1108 { 1109 struct e1000_mac_info *mac = &hw->mac; 1110 u32 i, status; 1111 s32 ret_val = E1000_SUCCESS; 1112 1113 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1114 1115 /* 1116 * If we have a signal (the cable is plugged in, or assumed TRUE for 1117 * serdes media) then poll for a "Link-Up" indication in the Device 1118 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1119 * seconds (Auto-negotiation should complete in less than 500 1120 * milliseconds even if the other end is doing it in SW). 1121 */ 1122 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1123 msec_delay(10); 1124 status = E1000_READ_REG(hw, E1000_STATUS); 1125 if (status & E1000_STATUS_LU) 1126 break; 1127 } 1128 if (i == FIBER_LINK_UP_LIMIT) { 1129 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1130 mac->autoneg_failed = 1; 1131 /* 1132 * AutoNeg failed to achieve a link, so we'll call 1133 * mac->check_for_link. This routine will force the 1134 * link up if we detect a signal. This will allow us to 1135 * communicate with non-autonegotiating link partners. 1136 */ 1137 ret_val = hw->mac.ops.check_for_link(hw); 1138 if (ret_val) { 1139 DEBUGOUT("Error while checking for link\n"); 1140 goto out; 1141 } 1142 mac->autoneg_failed = 0; 1143 } else { 1144 mac->autoneg_failed = 0; 1145 DEBUGOUT("Valid Link Found\n"); 1146 } 1147 1148 out: 1149 return ret_val; 1150 } 1151 1152 /** 1153 * e1000_commit_fc_settings_generic - Configure flow control 1154 * @hw: pointer to the HW structure 1155 * 1156 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1157 * base on the flow control settings in e1000_mac_info. 1158 **/ 1159 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1160 { 1161 struct e1000_mac_info *mac = &hw->mac; 1162 u32 txcw; 1163 s32 ret_val = E1000_SUCCESS; 1164 1165 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1166 1167 /* 1168 * Check for a software override of the flow control settings, and 1169 * setup the device accordingly. If auto-negotiation is enabled, then 1170 * software will have to set the "PAUSE" bits to the correct value in 1171 * the Transmit Config Word Register (TXCW) and re-start auto- 1172 * negotiation. However, if auto-negotiation is disabled, then 1173 * software will have to manually configure the two flow control enable 1174 * bits in the CTRL register. 1175 * 1176 * The possible values of the "fc" parameter are: 1177 * 0: Flow control is completely disabled 1178 * 1: Rx flow control is enabled (we can receive pause frames, 1179 * but not send pause frames). 1180 * 2: Tx flow control is enabled (we can send pause frames but we 1181 * do not support receiving pause frames). 1182 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1183 */ 1184 switch (hw->fc.type) { 1185 case e1000_fc_none: 1186 /* Flow control completely disabled by a software over-ride. */ 1187 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1188 break; 1189 case e1000_fc_rx_pause: 1190 /* 1191 * Rx Flow control is enabled and Tx Flow control is disabled 1192 * by a software over-ride. Since there really isn't a way to 1193 * advertise that we are capable of Rx Pause ONLY, we will 1194 * advertise that we support both symmetric and asymmetric RX 1195 * PAUSE. Later, we will disable the adapter's ability to send 1196 * PAUSE frames. 1197 */ 1198 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1199 break; 1200 case e1000_fc_tx_pause: 1201 /* 1202 * Tx Flow control is enabled, and Rx Flow control is disabled, 1203 * by a software over-ride. 1204 */ 1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1206 break; 1207 case e1000_fc_full: 1208 /* 1209 * Flow control (both Rx and Tx) is enabled by a software 1210 * over-ride. 1211 */ 1212 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1213 break; 1214 default: 1215 DEBUGOUT("Flow control param set incorrectly\n"); 1216 ret_val = -E1000_ERR_CONFIG; 1217 goto out; 1218 break; 1219 } 1220 1221 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1222 mac->txcw = txcw; 1223 1224 out: 1225 return ret_val; 1226 } 1227 1228 /** 1229 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1230 * @hw: pointer to the HW structure 1231 * 1232 * Sets the flow control high/low threshold (watermark) registers. If 1233 * flow control XON frame transmission is enabled, then set XON frame 1234 * transmission as well. 1235 **/ 1236 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1237 { 1238 s32 ret_val = E1000_SUCCESS; 1239 u32 fcrtl = 0, fcrth = 0; 1240 1241 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1242 1243 /* 1244 * Set the flow control receive threshold registers. Normally, 1245 * these registers will be set to a default threshold that may be 1246 * adjusted later by the driver's runtime code. However, if the 1247 * ability to transmit pause frames is not enabled, then these 1248 * registers will be set to 0. 1249 */ 1250 if (hw->fc.type & e1000_fc_tx_pause) { 1251 /* 1252 * We need to set up the Receive Threshold high and low water 1253 * marks as well as (optionally) enabling the transmission of 1254 * XON frames. 1255 */ 1256 fcrtl = hw->fc.low_water; 1257 if (hw->fc.send_xon) 1258 fcrtl |= E1000_FCRTL_XONE; 1259 1260 fcrth = hw->fc.high_water; 1261 } 1262 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1263 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1264 1265 return ret_val; 1266 } 1267 1268 /** 1269 * e1000_set_default_fc_generic - Set flow control default values 1270 * @hw: pointer to the HW structure 1271 * 1272 * Read the EEPROM for the default values for flow control and store the 1273 * values. 1274 **/ 1275 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1276 { 1277 s32 ret_val = E1000_SUCCESS; 1278 u16 nvm_data; 1279 1280 DEBUGFUNC("e1000_set_default_fc_generic"); 1281 1282 /* 1283 * Read and store word 0x0F of the EEPROM. This word contains bits 1284 * that determine the hardware's default PAUSE (flow control) mode, 1285 * a bit that determines whether the HW defaults to enabling or 1286 * disabling auto-negotiation, and the direction of the 1287 * SW defined pins. If there is no SW over-ride of the flow 1288 * control setting, then the variable hw->fc will 1289 * be initialized based on a value in the EEPROM. 1290 */ 1291 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1292 1293 if (ret_val) { 1294 DEBUGOUT("NVM Read Error\n"); 1295 goto out; 1296 } 1297 1298 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1299 hw->fc.type = e1000_fc_none; 1300 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1301 NVM_WORD0F_ASM_DIR) 1302 hw->fc.type = e1000_fc_tx_pause; 1303 else 1304 hw->fc.type = e1000_fc_full; 1305 1306 out: 1307 return ret_val; 1308 } 1309 1310 /** 1311 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1312 * @hw: pointer to the HW structure 1313 * 1314 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1315 * device control register to reflect the adapter settings. TFCE and RFCE 1316 * need to be explicitly set by software when a copper PHY is used because 1317 * autonegotiation is managed by the PHY rather than the MAC. Software must 1318 * also configure these bits when link is forced on a fiber connection. 1319 **/ 1320 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1321 { 1322 u32 ctrl; 1323 s32 ret_val = E1000_SUCCESS; 1324 1325 DEBUGFUNC("e1000_force_mac_fc_generic"); 1326 1327 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1328 1329 /* 1330 * Because we didn't get link via the internal auto-negotiation 1331 * mechanism (we either forced link or we got link via PHY 1332 * auto-neg), we have to manually enable/disable transmit an 1333 * receive flow control. 1334 * 1335 * The "Case" statement below enables/disable flow control 1336 * according to the "hw->fc.type" parameter. 1337 * 1338 * The possible values of the "fc" parameter are: 1339 * 0: Flow control is completely disabled 1340 * 1: Rx flow control is enabled (we can receive pause 1341 * frames but not send pause frames). 1342 * 2: Tx flow control is enabled (we can send pause frames 1343 * frames but we do not receive pause frames). 1344 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1345 * other: No other values should be possible at this point. 1346 */ 1347 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type); 1348 1349 switch (hw->fc.type) { 1350 case e1000_fc_none: 1351 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1352 break; 1353 case e1000_fc_rx_pause: 1354 ctrl &= (~E1000_CTRL_TFCE); 1355 ctrl |= E1000_CTRL_RFCE; 1356 break; 1357 case e1000_fc_tx_pause: 1358 ctrl &= (~E1000_CTRL_RFCE); 1359 ctrl |= E1000_CTRL_TFCE; 1360 break; 1361 case e1000_fc_full: 1362 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1363 break; 1364 default: 1365 DEBUGOUT("Flow control param set incorrectly\n"); 1366 ret_val = -E1000_ERR_CONFIG; 1367 goto out; 1368 } 1369 1370 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1371 1372 out: 1373 return ret_val; 1374 } 1375 1376 /** 1377 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1378 * @hw: pointer to the HW structure 1379 * 1380 * Checks the status of auto-negotiation after link up to ensure that the 1381 * speed and duplex were not forced. If the link needed to be forced, then 1382 * flow control needs to be forced also. If auto-negotiation is enabled 1383 * and did not fail, then we configure flow control based on our link 1384 * partner. 1385 **/ 1386 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1387 { 1388 struct e1000_mac_info *mac = &hw->mac; 1389 struct e1000_phy_info *phy = &hw->phy; 1390 s32 ret_val = E1000_SUCCESS; 1391 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1392 u16 speed, duplex; 1393 1394 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1395 1396 /* 1397 * Check for the case where we have fiber media and auto-neg failed 1398 * so we had to force link. In this case, we need to force the 1399 * configuration of the MAC to match the "fc" parameter. 1400 */ 1401 if (mac->autoneg_failed) { 1402 if (hw->phy.media_type == e1000_media_type_fiber || 1403 hw->phy.media_type == e1000_media_type_internal_serdes) 1404 ret_val = e1000_force_mac_fc_generic(hw); 1405 } else { 1406 if (hw->phy.media_type == e1000_media_type_copper) 1407 ret_val = e1000_force_mac_fc_generic(hw); 1408 } 1409 1410 if (ret_val) { 1411 DEBUGOUT("Error forcing flow control settings\n"); 1412 goto out; 1413 } 1414 1415 /* 1416 * Check for the case where we have copper media and auto-neg is 1417 * enabled. In this case, we need to check and see if Auto-Neg 1418 * has completed, and if so, how the PHY and link partner has 1419 * flow control configured. 1420 */ 1421 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1422 /* 1423 * Read the MII Status Register and check to see if AutoNeg 1424 * has completed. We read this twice because this reg has 1425 * some "sticky" (latched) bits. 1426 */ 1427 ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1428 if (ret_val) 1429 goto out; 1430 ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1431 if (ret_val) 1432 goto out; 1433 1434 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1435 DEBUGOUT("Copper PHY and Auto Neg " 1436 "has not completed.\n"); 1437 goto out; 1438 } 1439 1440 /* 1441 * The AutoNeg process has completed, so we now need to 1442 * read both the Auto Negotiation Advertisement 1443 * Register (Address 4) and the Auto_Negotiation Base 1444 * Page Ability Register (Address 5) to determine how 1445 * flow control was negotiated. 1446 */ 1447 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, 1448 &mii_nway_adv_reg); 1449 if (ret_val) 1450 goto out; 1451 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, 1452 &mii_nway_lp_ability_reg); 1453 if (ret_val) 1454 goto out; 1455 1456 /* 1457 * Two bits in the Auto Negotiation Advertisement Register 1458 * (Address 4) and two bits in the Auto Negotiation Base 1459 * Page Ability Register (Address 5) determine flow control 1460 * for both the PHY and the link partner. The following 1461 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1462 * 1999, describes these PAUSE resolution bits and how flow 1463 * control is determined based upon these settings. 1464 * NOTE: DC = Don't Care 1465 * 1466 * LOCAL DEVICE | LINK PARTNER 1467 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1468 *-------|---------|-------|---------|-------------------- 1469 * 0 | 0 | DC | DC | e1000_fc_none 1470 * 0 | 1 | 0 | DC | e1000_fc_none 1471 * 0 | 1 | 1 | 0 | e1000_fc_none 1472 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1473 * 1 | 0 | 0 | DC | e1000_fc_none 1474 * 1 | DC | 1 | DC | e1000_fc_full 1475 * 1 | 1 | 0 | 0 | e1000_fc_none 1476 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1477 * 1478 * Are both PAUSE bits set to 1? If so, this implies 1479 * Symmetric Flow Control is enabled at both ends. The 1480 * ASM_DIR bits are irrelevant per the spec. 1481 * 1482 * For Symmetric Flow Control: 1483 * 1484 * LOCAL DEVICE | LINK PARTNER 1485 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1486 *-------|---------|-------|---------|-------------------- 1487 * 1 | DC | 1 | DC | E1000_fc_full 1488 * 1489 */ 1490 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1491 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1492 /* 1493 * Now we need to check if the user selected Rx ONLY 1494 * of pause frames. In this case, we had to advertise 1495 * FULL flow control because we could not advertise RX 1496 * ONLY. Hence, we must now check to see if we need to 1497 * turn OFF the TRANSMISSION of PAUSE frames. 1498 */ 1499 if (hw->fc.original_type == e1000_fc_full) { 1500 hw->fc.type = e1000_fc_full; 1501 DEBUGOUT("Flow Control = FULL.\r\n"); 1502 } else { 1503 hw->fc.type = e1000_fc_rx_pause; 1504 DEBUGOUT("Flow Control = " 1505 "RX PAUSE frames only.\r\n"); 1506 } 1507 } 1508 /* 1509 * For receiving PAUSE frames ONLY. 1510 * 1511 * LOCAL DEVICE | LINK PARTNER 1512 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1513 *-------|---------|-------|---------|-------------------- 1514 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1515 */ 1516 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1517 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1518 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1519 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1520 hw->fc.type = e1000_fc_tx_pause; 1521 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1522 } 1523 /* 1524 * For transmitting PAUSE frames ONLY. 1525 * 1526 * LOCAL DEVICE | LINK PARTNER 1527 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1528 *-------|---------|-------|---------|-------------------- 1529 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1530 */ 1531 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1532 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1533 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1534 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1535 hw->fc.type = e1000_fc_rx_pause; 1536 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1537 } else { 1538 /* 1539 * Per the IEEE spec, at this point flow control 1540 * should be disabled. 1541 */ 1542 hw->fc.type = e1000_fc_none; 1543 DEBUGOUT("Flow Control = NONE.\r\n"); 1544 } 1545 1546 /* 1547 * Now we need to do one last check... If we auto- 1548 * negotiated to HALF DUPLEX, flow control should not be 1549 * enabled per IEEE 802.3 spec. 1550 */ 1551 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1552 if (ret_val) { 1553 DEBUGOUT("Error getting link speed and duplex\n"); 1554 goto out; 1555 } 1556 1557 if (duplex == HALF_DUPLEX) 1558 hw->fc.type = e1000_fc_none; 1559 1560 /* 1561 * Now we call a subroutine to actually force the MAC 1562 * controller to use the correct flow control settings. 1563 */ 1564 ret_val = e1000_force_mac_fc_generic(hw); 1565 if (ret_val) { 1566 DEBUGOUT("Error forcing flow control settings\n"); 1567 goto out; 1568 } 1569 } 1570 1571 out: 1572 return ret_val; 1573 } 1574 1575 /** 1576 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1577 * @hw: pointer to the HW structure 1578 * @speed: stores the current speed 1579 * @duplex: stores the current duplex 1580 * 1581 * Read the status register for the current speed/duplex and store the current 1582 * speed and duplex for copper connections. 1583 **/ 1584 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1585 u16 *duplex) 1586 { 1587 u32 status; 1588 1589 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1590 1591 status = E1000_READ_REG(hw, E1000_STATUS); 1592 if (status & E1000_STATUS_SPEED_1000) { 1593 *speed = SPEED_1000; 1594 DEBUGOUT("1000 Mbs, "); 1595 } else if (status & E1000_STATUS_SPEED_100) { 1596 *speed = SPEED_100; 1597 DEBUGOUT("100 Mbs, "); 1598 } else { 1599 *speed = SPEED_10; 1600 DEBUGOUT("10 Mbs, "); 1601 } 1602 1603 if (status & E1000_STATUS_FD) { 1604 *duplex = FULL_DUPLEX; 1605 DEBUGOUT("Full Duplex\n"); 1606 } else { 1607 *duplex = HALF_DUPLEX; 1608 DEBUGOUT("Half Duplex\n"); 1609 } 1610 1611 return E1000_SUCCESS; 1612 } 1613 1614 /** 1615 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1616 * @hw: pointer to the HW structure 1617 * @speed: stores the current speed 1618 * @duplex: stores the current duplex 1619 * 1620 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1621 * for fiber/serdes links. 1622 **/ 1623 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1624 u16 *speed, u16 *duplex) 1625 { 1626 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1627 1628 *speed = SPEED_1000; 1629 *duplex = FULL_DUPLEX; 1630 1631 return E1000_SUCCESS; 1632 } 1633 1634 /** 1635 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1636 * @hw: pointer to the HW structure 1637 * 1638 * Acquire the HW semaphore to access the PHY or NVM 1639 **/ 1640 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1641 { 1642 u32 swsm; 1643 s32 ret_val = E1000_SUCCESS; 1644 s32 timeout = hw->nvm.word_size + 1; 1645 s32 i = 0; 1646 1647 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1648 1649 /* Get the SW semaphore */ 1650 while (i < timeout) { 1651 swsm = E1000_READ_REG(hw, E1000_SWSM); 1652 if (!(swsm & E1000_SWSM_SMBI)) 1653 break; 1654 1655 usec_delay(50); 1656 i++; 1657 } 1658 1659 if (i == timeout) { 1660 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1661 ret_val = -E1000_ERR_NVM; 1662 goto out; 1663 } 1664 1665 /* Get the FW semaphore. */ 1666 for (i = 0; i < timeout; i++) { 1667 swsm = E1000_READ_REG(hw, E1000_SWSM); 1668 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1669 1670 /* Semaphore acquired if bit latched */ 1671 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1672 break; 1673 1674 usec_delay(50); 1675 } 1676 1677 if (i == timeout) { 1678 /* Release semaphores */ 1679 e1000_put_hw_semaphore_generic(hw); 1680 DEBUGOUT("Driver can't access the NVM\n"); 1681 ret_val = -E1000_ERR_NVM; 1682 goto out; 1683 } 1684 1685 out: 1686 return ret_val; 1687 } 1688 1689 /** 1690 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1691 * @hw: pointer to the HW structure 1692 * 1693 * Release hardware semaphore used to access the PHY or NVM 1694 **/ 1695 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1696 { 1697 u32 swsm; 1698 1699 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1700 1701 swsm = E1000_READ_REG(hw, E1000_SWSM); 1702 1703 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1704 1705 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1706 } 1707 1708 /** 1709 * e1000_get_auto_rd_done_generic - Check for auto read completion 1710 * @hw: pointer to the HW structure 1711 * 1712 * Check EEPROM for Auto Read done bit. 1713 **/ 1714 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1715 { 1716 s32 i = 0; 1717 s32 ret_val = E1000_SUCCESS; 1718 1719 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1720 1721 while (i < AUTO_READ_DONE_TIMEOUT) { 1722 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1723 break; 1724 msec_delay(1); 1725 i++; 1726 } 1727 1728 if (i == AUTO_READ_DONE_TIMEOUT) { 1729 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1730 ret_val = -E1000_ERR_RESET; 1731 goto out; 1732 } 1733 1734 out: 1735 return ret_val; 1736 } 1737 1738 /** 1739 * e1000_valid_led_default_generic - Verify a valid default LED config 1740 * @hw: pointer to the HW structure 1741 * @data: pointer to the NVM (EEPROM) 1742 * 1743 * Read the EEPROM for the current default LED configuration. If the 1744 * LED configuration is not valid, set to a valid LED configuration. 1745 **/ 1746 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1747 { 1748 s32 ret_val; 1749 1750 DEBUGFUNC("e1000_valid_led_default_generic"); 1751 1752 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1753 if (ret_val) { 1754 DEBUGOUT("NVM Read Error\n"); 1755 goto out; 1756 } 1757 1758 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1759 *data = ID_LED_DEFAULT; 1760 1761 out: 1762 return ret_val; 1763 } 1764 1765 /** 1766 * e1000_id_led_init_generic - 1767 * @hw: pointer to the HW structure 1768 * 1769 **/ 1770 s32 e1000_id_led_init_generic(struct e1000_hw * hw) 1771 { 1772 struct e1000_mac_info *mac = &hw->mac; 1773 s32 ret_val; 1774 const u32 ledctl_mask = 0x000000FF; 1775 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1776 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1777 u16 data, i, temp; 1778 const u16 led_mask = 0x0F; 1779 1780 DEBUGFUNC("e1000_id_led_init_generic"); 1781 1782 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1783 if (ret_val) 1784 goto out; 1785 1786 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1787 mac->ledctl_mode1 = mac->ledctl_default; 1788 mac->ledctl_mode2 = mac->ledctl_default; 1789 1790 for (i = 0; i < 4; i++) { 1791 temp = (data >> (i << 2)) & led_mask; 1792 switch (temp) { 1793 case ID_LED_ON1_DEF2: 1794 case ID_LED_ON1_ON2: 1795 case ID_LED_ON1_OFF2: 1796 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1797 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1798 break; 1799 case ID_LED_OFF1_DEF2: 1800 case ID_LED_OFF1_ON2: 1801 case ID_LED_OFF1_OFF2: 1802 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1803 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1804 break; 1805 default: 1806 /* Do nothing */ 1807 break; 1808 } 1809 switch (temp) { 1810 case ID_LED_DEF1_ON2: 1811 case ID_LED_ON1_ON2: 1812 case ID_LED_OFF1_ON2: 1813 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1814 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1815 break; 1816 case ID_LED_DEF1_OFF2: 1817 case ID_LED_ON1_OFF2: 1818 case ID_LED_OFF1_OFF2: 1819 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1820 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1821 break; 1822 default: 1823 /* Do nothing */ 1824 break; 1825 } 1826 } 1827 1828 out: 1829 return ret_val; 1830 } 1831 1832 /** 1833 * e1000_setup_led_generic - Configures SW controllable LED 1834 * @hw: pointer to the HW structure 1835 * 1836 * This prepares the SW controllable LED for use and saves the current state 1837 * of the LED so it can be later restored. 1838 **/ 1839 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1840 { 1841 u32 ledctl; 1842 s32 ret_val = E1000_SUCCESS; 1843 1844 DEBUGFUNC("e1000_setup_led_generic"); 1845 1846 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1847 ret_val = -E1000_ERR_CONFIG; 1848 goto out; 1849 } 1850 1851 if (hw->phy.media_type == e1000_media_type_fiber) { 1852 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1853 hw->mac.ledctl_default = ledctl; 1854 /* Turn off LED0 */ 1855 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1856 E1000_LEDCTL_LED0_BLINK | 1857 E1000_LEDCTL_LED0_MODE_MASK); 1858 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1859 E1000_LEDCTL_LED0_MODE_SHIFT); 1860 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1861 } else if (hw->phy.media_type == e1000_media_type_copper) { 1862 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1863 } 1864 1865 out: 1866 return ret_val; 1867 } 1868 1869 /** 1870 * e1000_cleanup_led_generic - Set LED config to default operation 1871 * @hw: pointer to the HW structure 1872 * 1873 * Remove the current LED configuration and set the LED configuration 1874 * to the default value, saved from the EEPROM. 1875 **/ 1876 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1877 { 1878 s32 ret_val = E1000_SUCCESS; 1879 1880 DEBUGFUNC("e1000_cleanup_led_generic"); 1881 1882 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1883 ret_val = -E1000_ERR_CONFIG; 1884 goto out; 1885 } 1886 1887 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1888 1889 out: 1890 return ret_val; 1891 } 1892 1893 /** 1894 * e1000_blink_led_generic - Blink LED 1895 * @hw: pointer to the HW structure 1896 * 1897 * Blink the LEDs which are set to be on. 1898 **/ 1899 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1900 { 1901 u32 ledctl_blink = 0; 1902 u32 i; 1903 1904 DEBUGFUNC("e1000_blink_led_generic"); 1905 1906 if (hw->phy.media_type == e1000_media_type_fiber) { 1907 /* always blink LED0 for PCI-E fiber */ 1908 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1909 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1910 } else { 1911 /* 1912 * set the blink bit for each LED that's "on" (0x0E) 1913 * in ledctl_mode2 1914 */ 1915 ledctl_blink = hw->mac.ledctl_mode2; 1916 for (i = 0; i < 4; i++) 1917 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1918 E1000_LEDCTL_MODE_LED_ON) 1919 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1920 (i * 8)); 1921 } 1922 1923 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1924 1925 return E1000_SUCCESS; 1926 } 1927 1928 /** 1929 * e1000_led_on_generic - Turn LED on 1930 * @hw: pointer to the HW structure 1931 * 1932 * Turn LED on. 1933 **/ 1934 s32 e1000_led_on_generic(struct e1000_hw *hw) 1935 { 1936 u32 ctrl; 1937 1938 DEBUGFUNC("e1000_led_on_generic"); 1939 1940 switch (hw->phy.media_type) { 1941 case e1000_media_type_fiber: 1942 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1943 ctrl &= ~E1000_CTRL_SWDPIN0; 1944 ctrl |= E1000_CTRL_SWDPIO0; 1945 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1946 break; 1947 case e1000_media_type_copper: 1948 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1949 break; 1950 default: 1951 break; 1952 } 1953 1954 return E1000_SUCCESS; 1955 } 1956 1957 /** 1958 * e1000_led_off_generic - Turn LED off 1959 * @hw: pointer to the HW structure 1960 * 1961 * Turn LED off. 1962 **/ 1963 s32 e1000_led_off_generic(struct e1000_hw *hw) 1964 { 1965 u32 ctrl; 1966 1967 DEBUGFUNC("e1000_led_off_generic"); 1968 1969 switch (hw->phy.media_type) { 1970 case e1000_media_type_fiber: 1971 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1972 ctrl |= E1000_CTRL_SWDPIN0; 1973 ctrl |= E1000_CTRL_SWDPIO0; 1974 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1975 break; 1976 case e1000_media_type_copper: 1977 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1978 break; 1979 default: 1980 break; 1981 } 1982 1983 return E1000_SUCCESS; 1984 } 1985 1986 /** 1987 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1988 * @hw: pointer to the HW structure 1989 * @no_snoop: bitmap of snoop events 1990 * 1991 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1992 **/ 1993 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1994 { 1995 u32 gcr; 1996 1997 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1998 1999 if (hw->bus.type != e1000_bus_type_pci_express) 2000 goto out; 2001 2002 if (no_snoop) { 2003 gcr = E1000_READ_REG(hw, E1000_GCR); 2004 gcr &= ~(PCIE_NO_SNOOP_ALL); 2005 gcr |= no_snoop; 2006 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2007 } 2008 out: 2009 return; 2010 } 2011 2012 /** 2013 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2014 * @hw: pointer to the HW structure 2015 * 2016 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 2017 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2018 * the master requests to be disabled. 2019 * 2020 * Disables PCI-Express master access and verifies there are no pending 2021 * requests. 2022 **/ 2023 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2024 { 2025 u32 ctrl; 2026 s32 timeout = MASTER_DISABLE_TIMEOUT; 2027 s32 ret_val = E1000_SUCCESS; 2028 2029 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2030 2031 if (hw->bus.type != e1000_bus_type_pci_express) 2032 goto out; 2033 2034 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2035 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2036 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2037 2038 while (timeout) { 2039 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2040 E1000_STATUS_GIO_MASTER_ENABLE)) 2041 break; 2042 usec_delay(100); 2043 timeout--; 2044 } 2045 2046 if (!timeout) { 2047 DEBUGOUT("Master requests are pending.\n"); 2048 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2049 goto out; 2050 } 2051 2052 out: 2053 return ret_val; 2054 } 2055 2056 /** 2057 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2058 * @hw: pointer to the HW structure 2059 * 2060 * Reset the Adaptive Interframe Spacing throttle to default values. 2061 **/ 2062 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2063 { 2064 struct e1000_mac_info *mac = &hw->mac; 2065 2066 DEBUGFUNC("e1000_reset_adaptive_generic"); 2067 2068 if (!mac->adaptive_ifs) { 2069 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2070 goto out; 2071 } 2072 2073 if (!mac->ifs_params_forced) { 2074 mac->current_ifs_val = 0; 2075 mac->ifs_min_val = IFS_MIN; 2076 mac->ifs_max_val = IFS_MAX; 2077 mac->ifs_step_size = IFS_STEP; 2078 mac->ifs_ratio = IFS_RATIO; 2079 } 2080 2081 mac->in_ifs_mode = FALSE; 2082 E1000_WRITE_REG(hw, E1000_AIT, 0); 2083 out: 2084 return; 2085 } 2086 2087 /** 2088 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2089 * @hw: pointer to the HW structure 2090 * 2091 * Update the Adaptive Interframe Spacing Throttle value based on the 2092 * time between transmitted packets and time between collisions. 2093 **/ 2094 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2095 { 2096 struct e1000_mac_info *mac = &hw->mac; 2097 2098 DEBUGFUNC("e1000_update_adaptive_generic"); 2099 2100 if (!mac->adaptive_ifs) { 2101 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2102 goto out; 2103 } 2104 2105 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2106 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2107 mac->in_ifs_mode = TRUE; 2108 if (mac->current_ifs_val < mac->ifs_max_val) { 2109 if (!mac->current_ifs_val) 2110 mac->current_ifs_val = mac->ifs_min_val; 2111 else 2112 mac->current_ifs_val += 2113 mac->ifs_step_size; 2114 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2115 } 2116 } 2117 } else { 2118 if (mac->in_ifs_mode && 2119 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2120 mac->current_ifs_val = 0; 2121 mac->in_ifs_mode = FALSE; 2122 E1000_WRITE_REG(hw, E1000_AIT, 0); 2123 } 2124 } 2125 out: 2126 return; 2127 } 2128 2129 /** 2130 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2131 * @hw: pointer to the HW structure 2132 * 2133 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2134 * set, which is forced to MDI mode only. 2135 **/ 2136 s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2137 { 2138 s32 ret_val = E1000_SUCCESS; 2139 2140 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2141 2142 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2143 DEBUGOUT("Invalid MDI setting detected\n"); 2144 hw->phy.mdix = 1; 2145 ret_val = -E1000_ERR_CONFIG; 2146 goto out; 2147 } 2148 2149 out: 2150 return ret_val; 2151 } 2152 2153 /** 2154 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2155 * @hw: pointer to the HW structure 2156 * @reg: 32bit register offset such as E1000_SCTL 2157 * @offset: register offset to write to 2158 * @data: data to write at register offset 2159 * 2160 * Writes an address/data control type register. There are several of these 2161 * and they all have the format address << 8 | data and bit 31 is polled for 2162 * completion. 2163 **/ 2164 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2165 u32 offset, u8 data) 2166 { 2167 u32 i, regvalue = 0; 2168 s32 ret_val = E1000_SUCCESS; 2169 2170 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2171 2172 /* Set up the address and data */ 2173 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2174 E1000_WRITE_REG(hw, reg, regvalue); 2175 2176 /* Poll the ready bit to see if the MDI read completed */ 2177 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2178 usec_delay(5); 2179 regvalue = E1000_READ_REG(hw, reg); 2180 if (regvalue & E1000_GEN_CTL_READY) 2181 break; 2182 } 2183 if (!(regvalue & E1000_GEN_CTL_READY)) { 2184 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2185 ret_val = -E1000_ERR_PHY; 2186 goto out; 2187 } 2188 2189 out: 2190 return ret_val; 2191 } 2192