1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 41 /** 42 * e1000_init_mac_ops_generic - Initialize MAC function pointers 43 * @hw: pointer to the HW structure 44 * 45 * Setups up the function pointers to no-op functions 46 **/ 47 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 48 { 49 struct e1000_mac_info *mac = &hw->mac; 50 DEBUGFUNC("e1000_init_mac_ops_generic"); 51 52 /* General Setup */ 53 mac->ops.init_params = e1000_null_ops_generic; 54 mac->ops.init_hw = e1000_null_ops_generic; 55 mac->ops.reset_hw = e1000_null_ops_generic; 56 mac->ops.setup_physical_interface = e1000_null_ops_generic; 57 mac->ops.get_bus_info = e1000_null_ops_generic; 58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 62 /* LED */ 63 mac->ops.cleanup_led = e1000_null_ops_generic; 64 mac->ops.setup_led = e1000_null_ops_generic; 65 mac->ops.blink_led = e1000_null_ops_generic; 66 mac->ops.led_on = e1000_null_ops_generic; 67 mac->ops.led_off = e1000_null_ops_generic; 68 /* LINK */ 69 mac->ops.setup_link = e1000_null_ops_generic; 70 mac->ops.get_link_up_info = e1000_null_link_info; 71 mac->ops.check_for_link = e1000_null_ops_generic; 72 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 73 /* Management */ 74 mac->ops.check_mng_mode = e1000_null_mng_mode; 75 /* VLAN, MC, etc. */ 76 mac->ops.update_mc_addr_list = e1000_null_update_mc; 77 mac->ops.clear_vfta = e1000_null_mac_generic; 78 mac->ops.write_vfta = e1000_null_write_vfta; 79 mac->ops.rar_set = e1000_rar_set_generic; 80 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 81 } 82 83 /** 84 * e1000_null_ops_generic - No-op function, returns 0 85 * @hw: pointer to the HW structure 86 **/ 87 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 88 { 89 DEBUGFUNC("e1000_null_ops_generic"); 90 return E1000_SUCCESS; 91 } 92 93 /** 94 * e1000_null_mac_generic - No-op function, return void 95 * @hw: pointer to the HW structure 96 **/ 97 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 98 { 99 DEBUGFUNC("e1000_null_mac_generic"); 100 return; 101 } 102 103 /** 104 * e1000_null_link_info - No-op function, return 0 105 * @hw: pointer to the HW structure 106 * @s: dummy variable 107 * @d: dummy variable 108 **/ 109 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 110 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 111 { 112 DEBUGFUNC("e1000_null_link_info"); 113 return E1000_SUCCESS; 114 } 115 116 /** 117 * e1000_null_mng_mode - No-op function, return false 118 * @hw: pointer to the HW structure 119 **/ 120 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 121 { 122 DEBUGFUNC("e1000_null_mng_mode"); 123 return false; 124 } 125 126 /** 127 * e1000_null_update_mc - No-op function, return void 128 * @hw: pointer to the HW structure 129 * @h: dummy variable 130 * @a: dummy variable 131 **/ 132 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 133 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 134 { 135 DEBUGFUNC("e1000_null_update_mc"); 136 return; 137 } 138 139 /** 140 * e1000_null_write_vfta - No-op function, return void 141 * @hw: pointer to the HW structure 142 * @a: dummy variable 143 * @b: dummy variable 144 **/ 145 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 146 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 147 { 148 DEBUGFUNC("e1000_null_write_vfta"); 149 return; 150 } 151 152 /** 153 * e1000_null_rar_set - No-op function, return 0 154 * @hw: pointer to the HW structure 155 * @h: dummy variable 156 * @a: dummy variable 157 **/ 158 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 159 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 160 { 161 DEBUGFUNC("e1000_null_rar_set"); 162 return E1000_SUCCESS; 163 } 164 165 /** 166 * e1000_null_set_obff_timer - No-op function, return 0 167 * @hw: pointer to the HW structure 168 **/ 169 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 170 u32 E1000_UNUSEDARG a) 171 { 172 DEBUGFUNC("e1000_null_set_obff_timer"); 173 return E1000_SUCCESS; 174 } 175 176 /** 177 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 178 * @hw: pointer to the HW structure 179 * 180 * Determines and stores the system bus information for a particular 181 * network interface. The following bus information is determined and stored: 182 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 183 **/ 184 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 185 { 186 struct e1000_mac_info *mac = &hw->mac; 187 struct e1000_bus_info *bus = &hw->bus; 188 u32 status = E1000_READ_REG(hw, E1000_STATUS); 189 s32 ret_val = E1000_SUCCESS; 190 191 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 192 193 /* PCI or PCI-X? */ 194 bus->type = (status & E1000_STATUS_PCIX_MODE) 195 ? e1000_bus_type_pcix 196 : e1000_bus_type_pci; 197 198 /* Bus speed */ 199 if (bus->type == e1000_bus_type_pci) { 200 bus->speed = (status & E1000_STATUS_PCI66) 201 ? e1000_bus_speed_66 202 : e1000_bus_speed_33; 203 } else { 204 switch (status & E1000_STATUS_PCIX_SPEED) { 205 case E1000_STATUS_PCIX_SPEED_66: 206 bus->speed = e1000_bus_speed_66; 207 break; 208 case E1000_STATUS_PCIX_SPEED_100: 209 bus->speed = e1000_bus_speed_100; 210 break; 211 case E1000_STATUS_PCIX_SPEED_133: 212 bus->speed = e1000_bus_speed_133; 213 break; 214 default: 215 bus->speed = e1000_bus_speed_reserved; 216 break; 217 } 218 } 219 220 /* Bus width */ 221 bus->width = (status & E1000_STATUS_BUS64) 222 ? e1000_bus_width_64 223 : e1000_bus_width_32; 224 225 /* Which PCI(-X) function? */ 226 mac->ops.set_lan_id(hw); 227 228 return ret_val; 229 } 230 231 /** 232 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 233 * @hw: pointer to the HW structure 234 * 235 * Determines and stores the system bus information for a particular 236 * network interface. The following bus information is determined and stored: 237 * bus speed, bus width, type (PCIe), and PCIe function. 238 **/ 239 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 240 { 241 struct e1000_mac_info *mac = &hw->mac; 242 struct e1000_bus_info *bus = &hw->bus; 243 s32 ret_val; 244 u16 pcie_link_status; 245 246 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 247 248 bus->type = e1000_bus_type_pci_express; 249 250 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 251 &pcie_link_status); 252 if (ret_val) { 253 bus->width = e1000_bus_width_unknown; 254 bus->speed = e1000_bus_speed_unknown; 255 } else { 256 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 257 case PCIE_LINK_SPEED_2500: 258 bus->speed = e1000_bus_speed_2500; 259 break; 260 case PCIE_LINK_SPEED_5000: 261 bus->speed = e1000_bus_speed_5000; 262 break; 263 default: 264 bus->speed = e1000_bus_speed_unknown; 265 break; 266 } 267 268 bus->width = (enum e1000_bus_width)((pcie_link_status & 269 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 270 } 271 272 mac->ops.set_lan_id(hw); 273 274 return E1000_SUCCESS; 275 } 276 277 /** 278 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 279 * 280 * @hw: pointer to the HW structure 281 * 282 * Determines the LAN function id by reading memory-mapped registers 283 * and swaps the port value if requested. 284 **/ 285 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 286 { 287 struct e1000_bus_info *bus = &hw->bus; 288 u32 reg; 289 290 /* The status register reports the correct function number 291 * for the device regardless of function swap state. 292 */ 293 reg = E1000_READ_REG(hw, E1000_STATUS); 294 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 295 } 296 297 /** 298 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 299 * @hw: pointer to the HW structure 300 * 301 * Determines the LAN function id by reading PCI config space. 302 **/ 303 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 304 { 305 struct e1000_bus_info *bus = &hw->bus; 306 u16 pci_header_type; 307 u32 status; 308 309 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 310 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 311 status = E1000_READ_REG(hw, E1000_STATUS); 312 bus->func = (status & E1000_STATUS_FUNC_MASK) 313 >> E1000_STATUS_FUNC_SHIFT; 314 } else { 315 bus->func = 0; 316 } 317 } 318 319 /** 320 * e1000_set_lan_id_single_port - Set LAN id for a single port device 321 * @hw: pointer to the HW structure 322 * 323 * Sets the LAN function id to zero for a single port device. 324 **/ 325 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 326 { 327 struct e1000_bus_info *bus = &hw->bus; 328 329 bus->func = 0; 330 } 331 332 /** 333 * e1000_clear_vfta_generic - Clear VLAN filter table 334 * @hw: pointer to the HW structure 335 * 336 * Clears the register array which contains the VLAN filter table by 337 * setting all the values to 0. 338 **/ 339 void e1000_clear_vfta_generic(struct e1000_hw *hw) 340 { 341 u32 offset; 342 343 DEBUGFUNC("e1000_clear_vfta_generic"); 344 345 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 347 E1000_WRITE_FLUSH(hw); 348 } 349 } 350 351 /** 352 * e1000_write_vfta_generic - Write value to VLAN filter table 353 * @hw: pointer to the HW structure 354 * @offset: register offset in VLAN filter table 355 * @value: register value written to VLAN filter table 356 * 357 * Writes value at the given offset in the register array which stores 358 * the VLAN filter table. 359 **/ 360 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 361 { 362 DEBUGFUNC("e1000_write_vfta_generic"); 363 364 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 365 E1000_WRITE_FLUSH(hw); 366 } 367 368 /** 369 * e1000_init_rx_addrs_generic - Initialize receive address's 370 * @hw: pointer to the HW structure 371 * @rar_count: receive address registers 372 * 373 * Setup the receive address registers by setting the base receive address 374 * register to the devices MAC address and clearing all the other receive 375 * address registers to 0. 376 **/ 377 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 378 { 379 u32 i; 380 u8 mac_addr[ETHER_ADDR_LEN] = {0}; 381 382 DEBUGFUNC("e1000_init_rx_addrs_generic"); 383 384 /* Setup the receive address */ 385 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 386 387 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 388 389 /* Zero out the other (rar_entry_count - 1) receive addresses */ 390 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 391 for (i = 1; i < rar_count; i++) 392 hw->mac.ops.rar_set(hw, mac_addr, i); 393 } 394 395 /** 396 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 397 * @hw: pointer to the HW structure 398 * 399 * Checks the nvm for an alternate MAC address. An alternate MAC address 400 * can be setup by pre-boot software and must be treated like a permanent 401 * address and must override the actual permanent MAC address. If an 402 * alternate MAC address is found it is programmed into RAR0, replacing 403 * the permanent address that was installed into RAR0 by the Si on reset. 404 * This function will return SUCCESS unless it encounters an error while 405 * reading the EEPROM. 406 **/ 407 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 408 { 409 u32 i; 410 s32 ret_val; 411 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 412 u8 alt_mac_addr[ETHER_ADDR_LEN]; 413 414 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 415 416 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 417 if (ret_val) 418 return ret_val; 419 420 /* not supported on older hardware or 82573 */ 421 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 422 return E1000_SUCCESS; 423 424 /* Alternate MAC address is handled by the option ROM for 82580 425 * and newer. SW support not required. 426 */ 427 if (hw->mac.type >= e1000_82580) 428 return E1000_SUCCESS; 429 430 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 431 &nvm_alt_mac_addr_offset); 432 if (ret_val) { 433 DEBUGOUT("NVM Read Error\n"); 434 return ret_val; 435 } 436 437 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 438 (nvm_alt_mac_addr_offset == 0x0000)) 439 /* There is no Alternate MAC Address */ 440 return E1000_SUCCESS; 441 442 if (hw->bus.func == E1000_FUNC_1) 443 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 444 if (hw->bus.func == E1000_FUNC_2) 445 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 446 447 if (hw->bus.func == E1000_FUNC_3) 448 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 449 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 450 offset = nvm_alt_mac_addr_offset + (i >> 1); 451 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 452 if (ret_val) { 453 DEBUGOUT("NVM Read Error\n"); 454 return ret_val; 455 } 456 457 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 458 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 459 } 460 461 /* if multicast bit is set, the alternate address will not be used */ 462 if (alt_mac_addr[0] & 0x01) { 463 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 464 return E1000_SUCCESS; 465 } 466 467 /* We have a valid alternate MAC address, and we want to treat it the 468 * same as the normal permanent MAC address stored by the HW into the 469 * RAR. Do this by mapping this address into RAR0. 470 */ 471 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 472 473 return E1000_SUCCESS; 474 } 475 476 /** 477 * e1000_rar_set_generic - Set receive address register 478 * @hw: pointer to the HW structure 479 * @addr: pointer to the receive address 480 * @index: receive address array register 481 * 482 * Sets the receive address array register at index to the address passed 483 * in by addr. 484 **/ 485 int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 486 { 487 u32 rar_low, rar_high; 488 489 DEBUGFUNC("e1000_rar_set_generic"); 490 491 /* HW expects these in little endian so we reverse the byte order 492 * from network order (big endian) to little endian 493 */ 494 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 495 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 496 497 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 498 499 /* If MAC address zero, no need to set the AV bit */ 500 if (rar_low || rar_high) 501 rar_high |= E1000_RAH_AV; 502 503 /* Some bridges will combine consecutive 32-bit writes into 504 * a single burst write, which will malfunction on some parts. 505 * The flushes avoid this. 506 */ 507 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 508 E1000_WRITE_FLUSH(hw); 509 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 510 E1000_WRITE_FLUSH(hw); 511 512 return E1000_SUCCESS; 513 } 514 515 /** 516 * e1000_hash_mc_addr_generic - Generate a multicast hash value 517 * @hw: pointer to the HW structure 518 * @mc_addr: pointer to a multicast address 519 * 520 * Generates a multicast address hash value which is used to determine 521 * the multicast filter table array address and new table value. 522 **/ 523 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 524 { 525 u32 hash_value, hash_mask; 526 u8 bit_shift = 1; 527 528 DEBUGFUNC("e1000_hash_mc_addr_generic"); 529 530 /* Register count multiplied by bits per register */ 531 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 532 533 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 534 * where 0xFF would still fall within the hash mask. 535 */ 536 while (bit_shift < 4 && hash_mask >> bit_shift != 0xFF) 537 bit_shift++; 538 539 /* The portion of the address that is used for the hash table 540 * is determined by the mc_filter_type setting. 541 * The algorithm is such that there is a total of 8 bits of shifting. 542 * The bit_shift for a mc_filter_type of 0 represents the number of 543 * left-shifts where the MSB of mc_addr[5] would still fall within 544 * the hash_mask. Case 0 does this exactly. Since there are a total 545 * of 8 bits of shifting, then mc_addr[4] will shift right the 546 * remaining number of bits. Thus 8 - bit_shift. The rest of the 547 * cases are a variation of this algorithm...essentially raising the 548 * number of bits to shift mc_addr[5] left, while still keeping the 549 * 8-bit shifting total. 550 * 551 * For example, given the following Destination MAC Address and an 552 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 553 * we can see that the bit_shift for case 0 is 4. These are the hash 554 * values resulting from each mc_filter_type... 555 * [0] [1] [2] [3] [4] [5] 556 * 01 AA 00 12 34 56 557 * LSB MSB 558 * 559 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 560 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 561 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 562 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 563 */ 564 switch (hw->mac.mc_filter_type) { 565 default: 566 case 0: 567 break; 568 case 1: 569 bit_shift += 1; 570 break; 571 case 2: 572 bit_shift += 2; 573 break; 574 case 3: 575 bit_shift += 4; 576 break; 577 } 578 579 hash_value = (u32)mc_addr[4]; 580 hash_value >>= 8 - bit_shift; 581 hash_value |= (u32)mc_addr[5] << bit_shift; 582 hash_value &= hash_mask; 583 584 return hash_value; 585 } 586 587 /** 588 * e1000_i21x_check_mta - Verify MTA writes on i210 and i211 589 * @hw: pointer to the HW structure 590 * 591 * The i210 and i211 can occasionally fail to accept MTA writes. Read the 592 * table back and rewrite mismatched entries, with a bounded retry count. 593 **/ 594 static void 595 e1000_i21x_check_mta(struct e1000_hw *hw) 596 { 597 bool failed; 598 int i, retries = 3; 599 600 do { 601 failed = false; 602 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) { 603 if (E1000_READ_REG_ARRAY(hw, E1000_MTA, i) == 604 hw->mac.mta_shadow[i]) 605 continue; 606 failed = true; 607 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 608 hw->mac.mta_shadow[i]); 609 E1000_WRITE_FLUSH(hw); 610 } 611 if (failed && --retries == 0) { 612 DEBUGOUT("Failed to update MTA after retries\n"); 613 break; 614 } 615 } while (failed); 616 } 617 618 /** 619 * e1000_update_mc_addr_list_generic - Update Multicast addresses 620 * @hw: pointer to the HW structure 621 * @mc_addr_list: array of multicast addresses to program 622 * @mc_addr_count: number of multicast addresses to program 623 * 624 * Updates entire Multicast Table Array. 625 * The caller must have a packed mc_addr_list of multicast addresses. 626 **/ 627 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 628 u8 *mc_addr_list, u32 mc_addr_count) 629 { 630 u32 hash_value, hash_bit, hash_reg; 631 int i; 632 633 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 634 635 /* clear mta_shadow */ 636 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 637 638 /* update mta_shadow from mc_addr_list */ 639 for (i = 0; (u32) i < mc_addr_count; i++) { 640 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 641 642 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 643 hash_bit = hash_value & 0x1F; 644 645 hw->mac.mta_shadow[hash_reg] |= 1U << hash_bit; 646 mc_addr_list += (ETHER_ADDR_LEN); 647 } 648 649 /* replace the entire MTA table */ 650 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 651 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 652 E1000_WRITE_FLUSH(hw); 653 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) 654 e1000_i21x_check_mta(hw); 655 } 656 657 /** 658 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 659 * @hw: pointer to the HW structure 660 * 661 * In certain situations, a system BIOS may report that the PCIx maximum 662 * memory read byte count (MMRBC) value is higher than than the actual 663 * value. We check the PCIx command register with the current PCIx status 664 * register. 665 **/ 666 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 667 { 668 u16 cmd_mmrbc; 669 u16 pcix_cmd; 670 u16 pcix_stat_hi_word; 671 u16 stat_mmrbc; 672 673 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 674 675 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 676 if (hw->bus.type != e1000_bus_type_pcix) 677 return; 678 679 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 680 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 681 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 682 PCIX_COMMAND_MMRBC_SHIFT; 683 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 684 PCIX_STATUS_HI_MMRBC_SHIFT; 685 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 686 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 687 if (cmd_mmrbc > stat_mmrbc) { 688 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 689 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 690 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 691 } 692 } 693 694 /** 695 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 696 * @hw: pointer to the HW structure 697 * 698 * Clears the base hardware counters by reading the counter registers. 699 **/ 700 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 701 { 702 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 703 704 E1000_READ_REG(hw, E1000_CRCERRS); 705 E1000_READ_REG(hw, E1000_SYMERRS); 706 E1000_READ_REG(hw, E1000_MPC); 707 E1000_READ_REG(hw, E1000_SCC); 708 E1000_READ_REG(hw, E1000_ECOL); 709 E1000_READ_REG(hw, E1000_MCC); 710 E1000_READ_REG(hw, E1000_LATECOL); 711 E1000_READ_REG(hw, E1000_COLC); 712 E1000_READ_REG(hw, E1000_DC); 713 E1000_READ_REG(hw, E1000_SEC); 714 E1000_READ_REG(hw, E1000_RLEC); 715 E1000_READ_REG(hw, E1000_XONRXC); 716 E1000_READ_REG(hw, E1000_XONTXC); 717 E1000_READ_REG(hw, E1000_XOFFRXC); 718 E1000_READ_REG(hw, E1000_XOFFTXC); 719 E1000_READ_REG(hw, E1000_FCRUC); 720 E1000_READ_REG(hw, E1000_GPRC); 721 E1000_READ_REG(hw, E1000_BPRC); 722 E1000_READ_REG(hw, E1000_MPRC); 723 E1000_READ_REG(hw, E1000_GPTC); 724 E1000_READ_REG(hw, E1000_GORCL); 725 E1000_READ_REG(hw, E1000_GORCH); 726 E1000_READ_REG(hw, E1000_GOTCL); 727 E1000_READ_REG(hw, E1000_GOTCH); 728 E1000_READ_REG(hw, E1000_RNBC); 729 E1000_READ_REG(hw, E1000_RUC); 730 E1000_READ_REG(hw, E1000_RFC); 731 E1000_READ_REG(hw, E1000_ROC); 732 E1000_READ_REG(hw, E1000_RJC); 733 E1000_READ_REG(hw, E1000_TORL); 734 E1000_READ_REG(hw, E1000_TORH); 735 E1000_READ_REG(hw, E1000_TOTL); 736 E1000_READ_REG(hw, E1000_TOTH); 737 E1000_READ_REG(hw, E1000_TPR); 738 E1000_READ_REG(hw, E1000_TPT); 739 E1000_READ_REG(hw, E1000_MPTC); 740 E1000_READ_REG(hw, E1000_BPTC); 741 E1000_READ_REG(hw, E1000_TLPIC); 742 E1000_READ_REG(hw, E1000_RLPIC); 743 } 744 745 /** 746 * e1000_check_for_copper_link_generic - Check for link (Copper) 747 * @hw: pointer to the HW structure 748 * 749 * Checks to see of the link status of the hardware has changed. If a 750 * change in link status has been detected, then we read the PHY registers 751 * to get the current speed/duplex if link exists. 752 **/ 753 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 754 { 755 struct e1000_mac_info *mac = &hw->mac; 756 s32 ret_val; 757 bool link; 758 759 DEBUGFUNC("e1000_check_for_copper_link"); 760 761 /* We only want to go out to the PHY registers to see if Auto-Neg 762 * has completed and/or if our link status has changed. The 763 * get_link_status flag is set upon receiving a Link Status 764 * Change or Rx Sequence Error interrupt. 765 */ 766 if (!mac->get_link_status) 767 return E1000_SUCCESS; 768 769 /* First we want to see if the MII Status Register reports 770 * link. If so, then we want to get the current speed/duplex 771 * of the PHY. 772 */ 773 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 774 if (ret_val) 775 return ret_val; 776 777 if (!link) 778 return E1000_SUCCESS; /* No link detected */ 779 780 mac->get_link_status = false; 781 782 /* Check if there was DownShift, must be checked 783 * immediately after link-up 784 */ 785 e1000_check_downshift_generic(hw); 786 787 /* If we are forcing speed/duplex, then we simply return since 788 * we have already determined whether we have link or not. 789 */ 790 if (!mac->autoneg) 791 return -E1000_ERR_CONFIG; 792 793 /* Auto-Neg is enabled. Auto Speed Detection takes care 794 * of MAC speed/duplex configuration. So we only need to 795 * configure Collision Distance in the MAC. 796 */ 797 mac->ops.config_collision_dist(hw); 798 799 /* Configure Flow Control now that Auto-Neg has completed. 800 * First, we need to restore the desired flow control 801 * settings because we may have had to re-autoneg with a 802 * different link partner. 803 */ 804 ret_val = e1000_config_fc_after_link_up_generic(hw); 805 if (ret_val) 806 DEBUGOUT("Error configuring flow control\n"); 807 808 return ret_val; 809 } 810 811 /** 812 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 813 * @hw: pointer to the HW structure 814 * 815 * Checks for link up on the hardware. If link is not up and we have 816 * a signal, then we need to force link up. 817 **/ 818 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 819 { 820 struct e1000_mac_info *mac = &hw->mac; 821 u32 rxcw; 822 u32 ctrl; 823 u32 status; 824 s32 ret_val; 825 826 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 827 828 ctrl = E1000_READ_REG(hw, E1000_CTRL); 829 status = E1000_READ_REG(hw, E1000_STATUS); 830 rxcw = E1000_READ_REG(hw, E1000_RXCW); 831 832 /* If we don't have link (auto-negotiation failed or link partner 833 * cannot auto-negotiate), the cable is plugged in (we have signal), 834 * and our link partner is not trying to auto-negotiate with us (we 835 * are receiving idles or data), we need to force link up. We also 836 * need to give auto-negotiation time to complete, in case the cable 837 * was just plugged in. The autoneg_failed flag does this. 838 */ 839 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 840 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 841 !(rxcw & E1000_RXCW_C)) { 842 if (!mac->autoneg_failed) { 843 mac->autoneg_failed = true; 844 return E1000_SUCCESS; 845 } 846 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 847 848 /* Disable auto-negotiation in the TXCW register */ 849 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 850 851 /* Force link-up and also force full-duplex. */ 852 ctrl = E1000_READ_REG(hw, E1000_CTRL); 853 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 854 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 855 856 /* Configure Flow Control after forcing link up. */ 857 ret_val = e1000_config_fc_after_link_up_generic(hw); 858 if (ret_val) { 859 DEBUGOUT("Error configuring flow control\n"); 860 return ret_val; 861 } 862 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 863 /* If we are forcing link and we are receiving /C/ ordered 864 * sets, re-enable auto-negotiation in the TXCW register 865 * and disable forced link in the Device Control register 866 * in an attempt to auto-negotiate with our link partner. 867 */ 868 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 869 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 870 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 871 872 mac->serdes_has_link = true; 873 } 874 875 return E1000_SUCCESS; 876 } 877 878 /** 879 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 880 * @hw: pointer to the HW structure 881 * 882 * Checks for link up on the hardware. If link is not up and we have 883 * a signal, then we need to force link up. 884 **/ 885 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 886 { 887 struct e1000_mac_info *mac = &hw->mac; 888 u32 rxcw; 889 u32 ctrl; 890 u32 status; 891 s32 ret_val; 892 893 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 894 895 ctrl = E1000_READ_REG(hw, E1000_CTRL); 896 status = E1000_READ_REG(hw, E1000_STATUS); 897 rxcw = E1000_READ_REG(hw, E1000_RXCW); 898 899 /* If we don't have link (auto-negotiation failed or link partner 900 * cannot auto-negotiate), and our link partner is not trying to 901 * auto-negotiate with us (we are receiving idles or data), 902 * we need to force link up. We also need to give auto-negotiation 903 * time to complete. 904 */ 905 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 906 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 907 if (!mac->autoneg_failed) { 908 mac->autoneg_failed = true; 909 return E1000_SUCCESS; 910 } 911 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 912 913 /* Disable auto-negotiation in the TXCW register */ 914 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 915 916 /* Force link-up and also force full-duplex. */ 917 ctrl = E1000_READ_REG(hw, E1000_CTRL); 918 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 919 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 920 921 /* Configure Flow Control after forcing link up. */ 922 ret_val = e1000_config_fc_after_link_up_generic(hw); 923 if (ret_val) { 924 DEBUGOUT("Error configuring flow control\n"); 925 return ret_val; 926 } 927 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 928 /* If we are forcing link and we are receiving /C/ ordered 929 * sets, re-enable auto-negotiation in the TXCW register 930 * and disable forced link in the Device Control register 931 * in an attempt to auto-negotiate with our link partner. 932 */ 933 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 934 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 935 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 936 937 mac->serdes_has_link = true; 938 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 939 /* If we force link for non-auto-negotiation switch, check 940 * link status based on MAC synchronization for internal 941 * serdes media type. 942 */ 943 /* SYNCH bit and IV bit are sticky. */ 944 usec_delay(10); 945 rxcw = E1000_READ_REG(hw, E1000_RXCW); 946 if (rxcw & E1000_RXCW_SYNCH) { 947 if (!(rxcw & E1000_RXCW_IV)) { 948 mac->serdes_has_link = true; 949 DEBUGOUT("SERDES: Link up - forced.\n"); 950 } 951 } else { 952 mac->serdes_has_link = false; 953 DEBUGOUT("SERDES: Link down - force failed.\n"); 954 } 955 } 956 957 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 958 status = E1000_READ_REG(hw, E1000_STATUS); 959 if (status & E1000_STATUS_LU) { 960 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 961 usec_delay(10); 962 rxcw = E1000_READ_REG(hw, E1000_RXCW); 963 if (rxcw & E1000_RXCW_SYNCH) { 964 if (!(rxcw & E1000_RXCW_IV)) { 965 mac->serdes_has_link = true; 966 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 967 } else { 968 mac->serdes_has_link = false; 969 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 970 } 971 } else { 972 mac->serdes_has_link = false; 973 DEBUGOUT("SERDES: Link down - no sync.\n"); 974 } 975 } else { 976 mac->serdes_has_link = false; 977 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 978 } 979 } 980 981 return E1000_SUCCESS; 982 } 983 984 /** 985 * e1000_set_default_fc_generic - Set flow control default values 986 * @hw: pointer to the HW structure 987 * 988 * Read the EEPROM for the default values for flow control and store the 989 * values. 990 **/ 991 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 992 { 993 s32 ret_val; 994 u16 nvm_data; 995 u16 nvm_offset = 0; 996 997 DEBUGFUNC("e1000_set_default_fc_generic"); 998 999 /* Read and store word 0x0F of the EEPROM. This word contains bits 1000 * that determine the hardware's default PAUSE (flow control) mode, 1001 * a bit that determines whether the HW defaults to enabling or 1002 * disabling auto-negotiation, and the direction of the 1003 * SW defined pins. If there is no SW over-ride of the flow 1004 * control setting, then the variable hw->fc will 1005 * be initialized based on a value in the EEPROM. 1006 */ 1007 if (hw->mac.type == e1000_i350) { 1008 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 1009 ret_val = hw->nvm.ops.read(hw, 1010 NVM_INIT_CONTROL2_REG + 1011 nvm_offset, 1012 1, &nvm_data); 1013 } else { 1014 ret_val = hw->nvm.ops.read(hw, 1015 NVM_INIT_CONTROL2_REG, 1016 1, &nvm_data); 1017 } 1018 1019 1020 if (ret_val) { 1021 DEBUGOUT("NVM Read Error\n"); 1022 return ret_val; 1023 } 1024 1025 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 1026 hw->fc.requested_mode = e1000_fc_none; 1027 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1028 NVM_WORD0F_ASM_DIR) 1029 hw->fc.requested_mode = e1000_fc_tx_pause; 1030 else 1031 hw->fc.requested_mode = e1000_fc_full; 1032 1033 return E1000_SUCCESS; 1034 } 1035 1036 /** 1037 * e1000_setup_link_generic - Setup flow control and link settings 1038 * @hw: pointer to the HW structure 1039 * 1040 * Determines which flow control settings to use, then configures flow 1041 * control. Calls the appropriate media-specific link configuration 1042 * function. Assuming the adapter has a valid link partner, a valid link 1043 * should be established. Assumes the hardware has previously been reset 1044 * and the transmitter and receiver are not enabled. 1045 **/ 1046 s32 e1000_setup_link_generic(struct e1000_hw *hw) 1047 { 1048 s32 ret_val; 1049 1050 DEBUGFUNC("e1000_setup_link_generic"); 1051 1052 /* In the case of the phy reset being blocked, we already have a link. 1053 * We do not need to set it up again. 1054 */ 1055 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1056 return E1000_SUCCESS; 1057 1058 /* If requested flow control is set to default, set flow control 1059 * based on the EEPROM flow control settings. 1060 */ 1061 if (hw->fc.requested_mode == e1000_fc_default) { 1062 ret_val = e1000_set_default_fc_generic(hw); 1063 if (ret_val) 1064 return ret_val; 1065 } 1066 1067 /* Save off the requested flow control mode for use later. Depending 1068 * on the link partner's capabilities, we may or may not use this mode. 1069 */ 1070 hw->fc.current_mode = hw->fc.requested_mode; 1071 1072 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1073 hw->fc.current_mode); 1074 1075 /* Call the necessary media_type subroutine to configure the link. */ 1076 ret_val = hw->mac.ops.setup_physical_interface(hw); 1077 if (ret_val) 1078 return ret_val; 1079 1080 /* Initialize the flow control address, type, and PAUSE timer 1081 * registers to their default values. This is done even if flow 1082 * control is disabled, because it does not hurt anything to 1083 * initialize these registers. 1084 */ 1085 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1086 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1087 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1088 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1089 1090 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1091 1092 return e1000_set_fc_watermarks_generic(hw); 1093 } 1094 1095 /** 1096 * e1000_commit_fc_settings_generic - Configure flow control 1097 * @hw: pointer to the HW structure 1098 * 1099 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1100 * base on the flow control settings in e1000_mac_info. 1101 **/ 1102 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1103 { 1104 struct e1000_mac_info *mac = &hw->mac; 1105 u32 txcw; 1106 1107 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1108 1109 /* Check for a software override of the flow control settings, and 1110 * setup the device accordingly. If auto-negotiation is enabled, then 1111 * software will have to set the "PAUSE" bits to the correct value in 1112 * the Transmit Config Word Register (TXCW) and re-start auto- 1113 * negotiation. However, if auto-negotiation is disabled, then 1114 * software will have to manually configure the two flow control enable 1115 * bits in the CTRL register. 1116 * 1117 * The possible values of the "fc" parameter are: 1118 * 0: Flow control is completely disabled 1119 * 1: Rx flow control is enabled (we can receive pause frames, 1120 * but not send pause frames). 1121 * 2: Tx flow control is enabled (we can send pause frames but we 1122 * do not support receiving pause frames). 1123 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1124 */ 1125 switch (hw->fc.current_mode) { 1126 case e1000_fc_none: 1127 /* Flow control completely disabled by a software over-ride. */ 1128 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1129 break; 1130 case e1000_fc_rx_pause: 1131 /* Rx Flow control is enabled and Tx Flow control is disabled 1132 * by a software over-ride. Since there really isn't a way to 1133 * advertise that we are capable of Rx Pause ONLY, we will 1134 * advertise that we support both symmetric and asymmetric Rx 1135 * PAUSE. Later, we will disable the adapter's ability to send 1136 * PAUSE frames. 1137 */ 1138 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1139 break; 1140 case e1000_fc_tx_pause: 1141 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1142 * by a software over-ride. 1143 */ 1144 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1145 break; 1146 case e1000_fc_full: 1147 /* Flow control (both Rx and Tx) is enabled by a software 1148 * over-ride. 1149 */ 1150 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1151 break; 1152 default: 1153 DEBUGOUT("Flow control param set incorrectly\n"); 1154 return -E1000_ERR_CONFIG; 1155 break; 1156 } 1157 1158 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1159 mac->txcw = txcw; 1160 1161 return E1000_SUCCESS; 1162 } 1163 1164 /** 1165 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1166 * @hw: pointer to the HW structure 1167 * 1168 * Polls for link up by reading the status register, if link fails to come 1169 * up with auto-negotiation, then the link is forced if a signal is detected. 1170 **/ 1171 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1172 { 1173 struct e1000_mac_info *mac = &hw->mac; 1174 u32 i, status; 1175 s32 ret_val; 1176 1177 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1178 1179 /* If we have a signal (the cable is plugged in, or assumed true for 1180 * serdes media) then poll for a "Link-Up" indication in the Device 1181 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1182 * seconds (Auto-negotiation should complete in less than 500 1183 * milliseconds even if the other end is doing it in SW). 1184 */ 1185 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1186 msec_delay(10); 1187 status = E1000_READ_REG(hw, E1000_STATUS); 1188 if (status & E1000_STATUS_LU) 1189 break; 1190 } 1191 if (i == FIBER_LINK_UP_LIMIT) { 1192 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1193 mac->autoneg_failed = true; 1194 /* AutoNeg failed to achieve a link, so we'll call 1195 * mac->check_for_link. This routine will force the 1196 * link up if we detect a signal. This will allow us to 1197 * communicate with non-autonegotiating link partners. 1198 */ 1199 ret_val = mac->ops.check_for_link(hw); 1200 if (ret_val) { 1201 DEBUGOUT("Error while checking for link\n"); 1202 return ret_val; 1203 } 1204 mac->autoneg_failed = false; 1205 } else { 1206 mac->autoneg_failed = false; 1207 DEBUGOUT("Valid Link Found\n"); 1208 } 1209 1210 return E1000_SUCCESS; 1211 } 1212 1213 /** 1214 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1215 * @hw: pointer to the HW structure 1216 * 1217 * Configures collision distance and flow control for fiber and serdes 1218 * links. Upon successful setup, poll for link. 1219 **/ 1220 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1221 { 1222 u32 ctrl; 1223 s32 ret_val; 1224 1225 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1226 1227 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1228 1229 /* Take the link out of reset */ 1230 ctrl &= ~E1000_CTRL_LRST; 1231 1232 hw->mac.ops.config_collision_dist(hw); 1233 1234 ret_val = e1000_commit_fc_settings_generic(hw); 1235 if (ret_val) 1236 return ret_val; 1237 1238 /* Since auto-negotiation is enabled, take the link out of reset (the 1239 * link will be in reset, because we previously reset the chip). This 1240 * will restart auto-negotiation. If auto-negotiation is successful 1241 * then the link-up status bit will be set and the flow control enable 1242 * bits (RFCE and TFCE) will be set according to their negotiated value. 1243 */ 1244 DEBUGOUT("Auto-negotiation enabled\n"); 1245 1246 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1247 E1000_WRITE_FLUSH(hw); 1248 msec_delay(1); 1249 1250 /* For these adapters, the SW definable pin 1 is set when the optics 1251 * detect a signal. If we have a signal, then poll for a "Link-Up" 1252 * indication. 1253 */ 1254 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1255 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1256 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1257 } else { 1258 DEBUGOUT("No signal detected\n"); 1259 } 1260 1261 return ret_val; 1262 } 1263 1264 /** 1265 * e1000_config_collision_dist_generic - Configure collision distance 1266 * @hw: pointer to the HW structure 1267 * 1268 * Configures the collision distance to the default value and is used 1269 * during link setup. 1270 **/ 1271 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1272 { 1273 u32 tctl; 1274 1275 DEBUGFUNC("e1000_config_collision_dist_generic"); 1276 1277 tctl = E1000_READ_REG(hw, E1000_TCTL); 1278 1279 tctl &= ~E1000_TCTL_COLD; 1280 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1281 1282 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1283 E1000_WRITE_FLUSH(hw); 1284 } 1285 1286 /** 1287 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1288 * @hw: pointer to the HW structure 1289 * 1290 * Sets the flow control high/low threshold (watermark) registers. If 1291 * flow control XON frame transmission is enabled, then set XON frame 1292 * transmission as well. 1293 **/ 1294 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1295 { 1296 u32 fcrtl = 0, fcrth = 0; 1297 1298 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1299 1300 /* Set the flow control receive threshold registers. Normally, 1301 * these registers will be set to a default threshold that may be 1302 * adjusted later by the driver's runtime code. However, if the 1303 * ability to transmit pause frames is not enabled, then these 1304 * registers will be set to 0. 1305 */ 1306 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1307 /* We need to set up the Receive Threshold high and low water 1308 * marks as well as (optionally) enabling the transmission of 1309 * XON frames. 1310 */ 1311 fcrtl = hw->fc.low_water; 1312 if (hw->fc.send_xon) 1313 fcrtl |= E1000_FCRTL_XONE; 1314 1315 fcrth = hw->fc.high_water; 1316 } 1317 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1318 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1319 1320 return E1000_SUCCESS; 1321 } 1322 1323 /** 1324 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1325 * @hw: pointer to the HW structure 1326 * 1327 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1328 * device control register to reflect the adapter settings. TFCE and RFCE 1329 * need to be explicitly set by software when a copper PHY is used because 1330 * autonegotiation is managed by the PHY rather than the MAC. Software must 1331 * also configure these bits when link is forced on a fiber connection. 1332 **/ 1333 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1334 { 1335 u32 ctrl; 1336 1337 DEBUGFUNC("e1000_force_mac_fc_generic"); 1338 1339 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1340 1341 /* Because we didn't get link via the internal auto-negotiation 1342 * mechanism (we either forced link or we got link via PHY 1343 * auto-neg), we have to manually enable/disable transmit an 1344 * receive flow control. 1345 * 1346 * The "Case" statement below enables/disable flow control 1347 * according to the "hw->fc.current_mode" parameter. 1348 * 1349 * The possible values of the "fc" parameter are: 1350 * 0: Flow control is completely disabled 1351 * 1: Rx flow control is enabled (we can receive pause 1352 * frames but not send pause frames). 1353 * 2: Tx flow control is enabled (we can send pause frames 1354 * frames but we do not receive pause frames). 1355 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1356 * other: No other values should be possible at this point. 1357 */ 1358 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1359 1360 switch (hw->fc.current_mode) { 1361 case e1000_fc_none: 1362 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1363 break; 1364 case e1000_fc_rx_pause: 1365 ctrl &= (~E1000_CTRL_TFCE); 1366 ctrl |= E1000_CTRL_RFCE; 1367 break; 1368 case e1000_fc_tx_pause: 1369 ctrl &= (~E1000_CTRL_RFCE); 1370 ctrl |= E1000_CTRL_TFCE; 1371 break; 1372 case e1000_fc_full: 1373 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1374 break; 1375 default: 1376 DEBUGOUT("Flow control param set incorrectly\n"); 1377 return -E1000_ERR_CONFIG; 1378 } 1379 1380 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1381 1382 return E1000_SUCCESS; 1383 } 1384 1385 /** 1386 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1387 * @hw: pointer to the HW structure 1388 * 1389 * Checks the status of auto-negotiation after link up to ensure that the 1390 * speed and duplex were not forced. If the link needed to be forced, then 1391 * flow control needs to be forced also. If auto-negotiation is enabled 1392 * and did not fail, then we configure flow control based on our link 1393 * partner. 1394 **/ 1395 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1396 { 1397 struct e1000_mac_info *mac = &hw->mac; 1398 s32 ret_val = E1000_SUCCESS; 1399 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1400 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1401 u16 speed, duplex; 1402 1403 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1404 1405 /* Check for the case where we have fiber media and auto-neg failed 1406 * so we had to force link. In this case, we need to force the 1407 * configuration of the MAC to match the "fc" parameter. 1408 */ 1409 if (mac->autoneg_failed) { 1410 if (hw->phy.media_type == e1000_media_type_fiber || 1411 hw->phy.media_type == e1000_media_type_internal_serdes) 1412 ret_val = e1000_force_mac_fc_generic(hw); 1413 } else { 1414 if (hw->phy.media_type == e1000_media_type_copper) 1415 ret_val = e1000_force_mac_fc_generic(hw); 1416 } 1417 1418 if (ret_val) { 1419 DEBUGOUT("Error forcing flow control settings\n"); 1420 return ret_val; 1421 } 1422 1423 /* Check for the case where we have copper media and auto-neg is 1424 * enabled. In this case, we need to check and see if Auto-Neg 1425 * has completed, and if so, how the PHY and link partner has 1426 * flow control configured. 1427 */ 1428 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1429 /* Read the MII Status Register and check to see if AutoNeg 1430 * has completed. We read this twice because this reg has 1431 * some "sticky" (latched) bits. 1432 */ 1433 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1434 if (ret_val) 1435 return ret_val; 1436 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1437 if (ret_val) 1438 return ret_val; 1439 1440 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1441 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1442 return ret_val; 1443 } 1444 1445 /* The AutoNeg process has completed, so we now need to 1446 * read both the Auto Negotiation Advertisement 1447 * Register (Address 4) and the Auto_Negotiation Base 1448 * Page Ability Register (Address 5) to determine how 1449 * flow control was negotiated. 1450 */ 1451 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1452 &mii_nway_adv_reg); 1453 if (ret_val) 1454 return ret_val; 1455 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1456 &mii_nway_lp_ability_reg); 1457 if (ret_val) 1458 return ret_val; 1459 1460 /* Two bits in the Auto Negotiation Advertisement Register 1461 * (Address 4) and two bits in the Auto Negotiation Base 1462 * Page Ability Register (Address 5) determine flow control 1463 * for both the PHY and the link partner. The following 1464 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1465 * 1999, describes these PAUSE resolution bits and how flow 1466 * control is determined based upon these settings. 1467 * NOTE: DC = Don't Care 1468 * 1469 * LOCAL DEVICE | LINK PARTNER 1470 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1471 *-------|---------|-------|---------|-------------------- 1472 * 0 | 0 | DC | DC | e1000_fc_none 1473 * 0 | 1 | 0 | DC | e1000_fc_none 1474 * 0 | 1 | 1 | 0 | e1000_fc_none 1475 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1476 * 1 | 0 | 0 | DC | e1000_fc_none 1477 * 1 | DC | 1 | DC | e1000_fc_full 1478 * 1 | 1 | 0 | 0 | e1000_fc_none 1479 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1480 * 1481 * Are both PAUSE bits set to 1? If so, this implies 1482 * Symmetric Flow Control is enabled at both ends. The 1483 * ASM_DIR bits are irrelevant per the spec. 1484 * 1485 * For Symmetric Flow Control: 1486 * 1487 * LOCAL DEVICE | LINK PARTNER 1488 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1489 *-------|---------|-------|---------|-------------------- 1490 * 1 | DC | 1 | DC | E1000_fc_full 1491 * 1492 */ 1493 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1494 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1495 /* Now we need to check if the user selected Rx ONLY 1496 * of pause frames. In this case, we had to advertise 1497 * FULL flow control because we could not advertise Rx 1498 * ONLY. Hence, we must now check to see if we need to 1499 * turn OFF the TRANSMISSION of PAUSE frames. 1500 */ 1501 if (hw->fc.requested_mode == e1000_fc_full) { 1502 hw->fc.current_mode = e1000_fc_full; 1503 DEBUGOUT("Flow Control = FULL.\n"); 1504 } else { 1505 hw->fc.current_mode = e1000_fc_rx_pause; 1506 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1507 } 1508 } 1509 /* For receiving PAUSE frames ONLY. 1510 * 1511 * LOCAL DEVICE | LINK PARTNER 1512 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1513 *-------|---------|-------|---------|-------------------- 1514 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1515 */ 1516 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1517 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1518 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1519 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1520 hw->fc.current_mode = e1000_fc_tx_pause; 1521 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1522 } 1523 /* For transmitting PAUSE frames ONLY. 1524 * 1525 * LOCAL DEVICE | LINK PARTNER 1526 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1527 *-------|---------|-------|---------|-------------------- 1528 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1529 */ 1530 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1531 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1532 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1533 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1534 hw->fc.current_mode = e1000_fc_rx_pause; 1535 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1536 } else { 1537 /* Per the IEEE spec, at this point flow control 1538 * should be disabled. 1539 */ 1540 hw->fc.current_mode = e1000_fc_none; 1541 DEBUGOUT("Flow Control = NONE.\n"); 1542 } 1543 1544 /* Now we need to do one last check... If we auto- 1545 * negotiated to HALF DUPLEX, flow control should not be 1546 * enabled per IEEE 802.3 spec. 1547 */ 1548 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1549 if (ret_val) { 1550 DEBUGOUT("Error getting link speed and duplex\n"); 1551 return ret_val; 1552 } 1553 1554 if (duplex == HALF_DUPLEX) 1555 hw->fc.current_mode = e1000_fc_none; 1556 1557 /* Now we call a subroutine to actually force the MAC 1558 * controller to use the correct flow control settings. 1559 */ 1560 ret_val = e1000_force_mac_fc_generic(hw); 1561 if (ret_val) { 1562 DEBUGOUT("Error forcing flow control settings\n"); 1563 return ret_val; 1564 } 1565 } 1566 1567 /* Check for the case where we have SerDes media and auto-neg is 1568 * enabled. In this case, we need to check and see if Auto-Neg 1569 * has completed, and if so, how the PHY and link partner has 1570 * flow control configured. 1571 */ 1572 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1573 mac->autoneg) { 1574 /* Read the PCS_LSTS and check to see if AutoNeg 1575 * has completed. 1576 */ 1577 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1578 1579 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1580 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1581 return ret_val; 1582 } 1583 1584 /* The AutoNeg process has completed, so we now need to 1585 * read both the Auto Negotiation Advertisement 1586 * Register (PCS_ANADV) and the Auto_Negotiation Base 1587 * Page Ability Register (PCS_LPAB) to determine how 1588 * flow control was negotiated. 1589 */ 1590 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1591 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1592 1593 /* Two bits in the Auto Negotiation Advertisement Register 1594 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1595 * Page Ability Register (PCS_LPAB) determine flow control 1596 * for both the PHY and the link partner. The following 1597 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1598 * 1999, describes these PAUSE resolution bits and how flow 1599 * control is determined based upon these settings. 1600 * NOTE: DC = Don't Care 1601 * 1602 * LOCAL DEVICE | LINK PARTNER 1603 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1604 *-------|---------|-------|---------|-------------------- 1605 * 0 | 0 | DC | DC | e1000_fc_none 1606 * 0 | 1 | 0 | DC | e1000_fc_none 1607 * 0 | 1 | 1 | 0 | e1000_fc_none 1608 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1609 * 1 | 0 | 0 | DC | e1000_fc_none 1610 * 1 | DC | 1 | DC | e1000_fc_full 1611 * 1 | 1 | 0 | 0 | e1000_fc_none 1612 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1613 * 1614 * Are both PAUSE bits set to 1? If so, this implies 1615 * Symmetric Flow Control is enabled at both ends. The 1616 * ASM_DIR bits are irrelevant per the spec. 1617 * 1618 * For Symmetric Flow Control: 1619 * 1620 * LOCAL DEVICE | LINK PARTNER 1621 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1622 *-------|---------|-------|---------|-------------------- 1623 * 1 | DC | 1 | DC | e1000_fc_full 1624 * 1625 */ 1626 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1627 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1628 /* Now we need to check if the user selected Rx ONLY 1629 * of pause frames. In this case, we had to advertise 1630 * FULL flow control because we could not advertise Rx 1631 * ONLY. Hence, we must now check to see if we need to 1632 * turn OFF the TRANSMISSION of PAUSE frames. 1633 */ 1634 if (hw->fc.requested_mode == e1000_fc_full) { 1635 hw->fc.current_mode = e1000_fc_full; 1636 DEBUGOUT("Flow Control = FULL.\n"); 1637 } else { 1638 hw->fc.current_mode = e1000_fc_rx_pause; 1639 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1640 } 1641 } 1642 /* For receiving PAUSE frames ONLY. 1643 * 1644 * LOCAL DEVICE | LINK PARTNER 1645 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1646 *-------|---------|-------|---------|-------------------- 1647 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1648 */ 1649 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1650 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1651 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1652 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1653 hw->fc.current_mode = e1000_fc_tx_pause; 1654 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1655 } 1656 /* For transmitting PAUSE frames ONLY. 1657 * 1658 * LOCAL DEVICE | LINK PARTNER 1659 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1660 *-------|---------|-------|---------|-------------------- 1661 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1662 */ 1663 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1664 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1665 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1666 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1667 hw->fc.current_mode = e1000_fc_rx_pause; 1668 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1669 } else { 1670 /* Per the IEEE spec, at this point flow control 1671 * should be disabled. 1672 */ 1673 hw->fc.current_mode = e1000_fc_none; 1674 DEBUGOUT("Flow Control = NONE.\n"); 1675 } 1676 1677 /* Now we call a subroutine to actually force the MAC 1678 * controller to use the correct flow control settings. 1679 */ 1680 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1681 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1682 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1683 1684 ret_val = e1000_force_mac_fc_generic(hw); 1685 if (ret_val) { 1686 DEBUGOUT("Error forcing flow control settings\n"); 1687 return ret_val; 1688 } 1689 } 1690 1691 return E1000_SUCCESS; 1692 } 1693 1694 /** 1695 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1696 * @hw: pointer to the HW structure 1697 * @speed: stores the current speed 1698 * @duplex: stores the current duplex 1699 * 1700 * Read the status register for the current speed/duplex and store the current 1701 * speed and duplex for copper connections. 1702 **/ 1703 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1704 u16 *duplex) 1705 { 1706 u32 status; 1707 1708 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1709 1710 status = E1000_READ_REG(hw, E1000_STATUS); 1711 if (status & E1000_STATUS_SPEED_1000) { 1712 *speed = SPEED_1000; 1713 DEBUGOUT("1000 Mbs, "); 1714 } else if (status & E1000_STATUS_SPEED_100) { 1715 *speed = SPEED_100; 1716 DEBUGOUT("100 Mbs, "); 1717 } else { 1718 *speed = SPEED_10; 1719 DEBUGOUT("10 Mbs, "); 1720 } 1721 1722 if (status & E1000_STATUS_FD) { 1723 *duplex = FULL_DUPLEX; 1724 DEBUGOUT("Full Duplex\n"); 1725 } else { 1726 *duplex = HALF_DUPLEX; 1727 DEBUGOUT("Half Duplex\n"); 1728 } 1729 1730 return E1000_SUCCESS; 1731 } 1732 1733 /** 1734 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1735 * @hw: pointer to the HW structure 1736 * @speed: stores the current speed 1737 * @duplex: stores the current duplex 1738 * 1739 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1740 * for fiber/serdes links. 1741 **/ 1742 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1743 u16 *speed, u16 *duplex) 1744 { 1745 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1746 1747 *speed = SPEED_1000; 1748 *duplex = FULL_DUPLEX; 1749 1750 return E1000_SUCCESS; 1751 } 1752 1753 /** 1754 * e1000_get_auto_rd_done_generic - Check for auto read completion 1755 * @hw: pointer to the HW structure 1756 * 1757 * Check EEPROM for Auto Read done bit. 1758 **/ 1759 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1760 { 1761 s32 i = 0; 1762 1763 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1764 1765 while (i < AUTO_READ_DONE_TIMEOUT) { 1766 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1767 break; 1768 msec_delay(1); 1769 i++; 1770 } 1771 1772 if (i == AUTO_READ_DONE_TIMEOUT) { 1773 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1774 return -E1000_ERR_RESET; 1775 } 1776 1777 return E1000_SUCCESS; 1778 } 1779 1780 /** 1781 * e1000_valid_led_default_generic - Verify a valid default LED config 1782 * @hw: pointer to the HW structure 1783 * @data: pointer to the NVM (EEPROM) 1784 * 1785 * Read the EEPROM for the current default LED configuration. If the 1786 * LED configuration is not valid, set to a valid LED configuration. 1787 **/ 1788 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1789 { 1790 s32 ret_val; 1791 1792 DEBUGFUNC("e1000_valid_led_default_generic"); 1793 1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1795 if (ret_val) { 1796 DEBUGOUT("NVM Read Error\n"); 1797 return ret_val; 1798 } 1799 1800 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1801 *data = ID_LED_DEFAULT; 1802 1803 return E1000_SUCCESS; 1804 } 1805 1806 /** 1807 * e1000_id_led_init_generic - 1808 * @hw: pointer to the HW structure 1809 * 1810 **/ 1811 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1812 { 1813 struct e1000_mac_info *mac = &hw->mac; 1814 s32 ret_val; 1815 const u32 ledctl_mask = 0x000000FF; 1816 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1817 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1818 u16 data, i, temp; 1819 const u16 led_mask = 0x0F; 1820 1821 DEBUGFUNC("e1000_id_led_init_generic"); 1822 1823 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1824 if (ret_val) 1825 return ret_val; 1826 1827 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1828 mac->ledctl_mode1 = mac->ledctl_default; 1829 mac->ledctl_mode2 = mac->ledctl_default; 1830 1831 for (i = 0; i < 4; i++) { 1832 temp = (data >> (i << 2)) & led_mask; 1833 switch (temp) { 1834 case ID_LED_ON1_DEF2: 1835 case ID_LED_ON1_ON2: 1836 case ID_LED_ON1_OFF2: 1837 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1838 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1839 break; 1840 case ID_LED_OFF1_DEF2: 1841 case ID_LED_OFF1_ON2: 1842 case ID_LED_OFF1_OFF2: 1843 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1844 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1845 break; 1846 default: 1847 /* Do nothing */ 1848 break; 1849 } 1850 switch (temp) { 1851 case ID_LED_DEF1_ON2: 1852 case ID_LED_ON1_ON2: 1853 case ID_LED_OFF1_ON2: 1854 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1855 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1856 break; 1857 case ID_LED_DEF1_OFF2: 1858 case ID_LED_ON1_OFF2: 1859 case ID_LED_OFF1_OFF2: 1860 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1861 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1862 break; 1863 default: 1864 /* Do nothing */ 1865 break; 1866 } 1867 } 1868 1869 return E1000_SUCCESS; 1870 } 1871 1872 /** 1873 * e1000_setup_led_generic - Configures SW controllable LED 1874 * @hw: pointer to the HW structure 1875 * 1876 * This prepares the SW controllable LED for use and saves the current state 1877 * of the LED so it can be later restored. 1878 **/ 1879 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1880 { 1881 u32 ledctl; 1882 1883 DEBUGFUNC("e1000_setup_led_generic"); 1884 1885 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1886 return -E1000_ERR_CONFIG; 1887 1888 if (hw->phy.media_type == e1000_media_type_fiber) { 1889 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1890 hw->mac.ledctl_default = ledctl; 1891 /* Turn off LED0 */ 1892 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1893 E1000_LEDCTL_LED0_MODE_MASK); 1894 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1895 E1000_LEDCTL_LED0_MODE_SHIFT); 1896 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1897 } else if (hw->phy.media_type == e1000_media_type_copper) { 1898 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1899 } 1900 1901 return E1000_SUCCESS; 1902 } 1903 1904 /** 1905 * e1000_cleanup_led_generic - Set LED config to default operation 1906 * @hw: pointer to the HW structure 1907 * 1908 * Remove the current LED configuration and set the LED configuration 1909 * to the default value, saved from the EEPROM. 1910 **/ 1911 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1912 { 1913 DEBUGFUNC("e1000_cleanup_led_generic"); 1914 1915 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1916 return E1000_SUCCESS; 1917 } 1918 1919 /** 1920 * e1000_blink_led_generic - Blink LED 1921 * @hw: pointer to the HW structure 1922 * 1923 * Blink the LEDs which are set to be on. 1924 **/ 1925 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1926 { 1927 u32 ledctl_blink = 0; 1928 u32 i; 1929 1930 DEBUGFUNC("e1000_blink_led_generic"); 1931 1932 if (hw->phy.media_type == e1000_media_type_fiber) { 1933 /* always blink LED0 for PCI-E fiber */ 1934 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1935 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1936 } else { 1937 /* Set the blink bit for each LED that's "on" (0x0E) 1938 * (or "off" if inverted) in ledctl_mode2. The blink 1939 * logic in hardware only works when mode is set to "on" 1940 * so it must be changed accordingly when the mode is 1941 * "off" and inverted. 1942 */ 1943 ledctl_blink = hw->mac.ledctl_mode2; 1944 for (i = 0; i < 32; i += 8) { 1945 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1946 E1000_LEDCTL_LED0_MODE_MASK; 1947 u32 led_default = hw->mac.ledctl_default >> i; 1948 1949 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1950 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1951 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1952 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1953 ledctl_blink &= 1954 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1955 ledctl_blink |= (u32)(E1000_LEDCTL_LED0_BLINK | 1956 E1000_LEDCTL_MODE_LED_ON) << i; 1957 } 1958 } 1959 } 1960 1961 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1962 1963 return E1000_SUCCESS; 1964 } 1965 1966 /** 1967 * e1000_led_on_generic - Turn LED on 1968 * @hw: pointer to the HW structure 1969 * 1970 * Turn LED on. 1971 **/ 1972 s32 e1000_led_on_generic(struct e1000_hw *hw) 1973 { 1974 u32 ctrl; 1975 1976 DEBUGFUNC("e1000_led_on_generic"); 1977 1978 switch (hw->phy.media_type) { 1979 case e1000_media_type_fiber: 1980 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1981 ctrl &= ~E1000_CTRL_SWDPIN0; 1982 ctrl |= E1000_CTRL_SWDPIO0; 1983 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1984 break; 1985 case e1000_media_type_copper: 1986 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1987 break; 1988 default: 1989 break; 1990 } 1991 1992 return E1000_SUCCESS; 1993 } 1994 1995 /** 1996 * e1000_led_off_generic - Turn LED off 1997 * @hw: pointer to the HW structure 1998 * 1999 * Turn LED off. 2000 **/ 2001 s32 e1000_led_off_generic(struct e1000_hw *hw) 2002 { 2003 u32 ctrl; 2004 2005 DEBUGFUNC("e1000_led_off_generic"); 2006 2007 switch (hw->phy.media_type) { 2008 case e1000_media_type_fiber: 2009 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2010 ctrl |= E1000_CTRL_SWDPIN0; 2011 ctrl |= E1000_CTRL_SWDPIO0; 2012 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2013 break; 2014 case e1000_media_type_copper: 2015 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2016 break; 2017 default: 2018 break; 2019 } 2020 2021 return E1000_SUCCESS; 2022 } 2023 2024 /** 2025 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2026 * @hw: pointer to the HW structure 2027 * @no_snoop: bitmap of snoop events 2028 * 2029 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2030 **/ 2031 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2032 { 2033 u32 gcr; 2034 2035 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2036 2037 if (hw->bus.type != e1000_bus_type_pci_express) 2038 return; 2039 2040 if (no_snoop) { 2041 gcr = E1000_READ_REG(hw, E1000_GCR); 2042 gcr &= ~(PCIE_NO_SNOOP_ALL); 2043 gcr |= no_snoop; 2044 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2045 } 2046 } 2047 2048 /** 2049 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2050 * @hw: pointer to the HW structure 2051 * 2052 * Returns E1000_SUCCESS if successful, else returns -10 2053 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2054 * the master requests to be disabled. 2055 * 2056 * Disables PCI-Express master access and verifies there are no pending 2057 * requests. 2058 **/ 2059 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2060 { 2061 u32 ctrl; 2062 s32 timeout = MASTER_DISABLE_TIMEOUT; 2063 2064 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2065 2066 if (hw->bus.type != e1000_bus_type_pci_express) 2067 return E1000_SUCCESS; 2068 2069 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2070 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2071 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2072 2073 while (timeout) { 2074 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2075 E1000_STATUS_GIO_MASTER_ENABLE) || 2076 E1000_REMOVED(hw->hw_addr)) 2077 break; 2078 usec_delay(100); 2079 timeout--; 2080 } 2081 2082 if (!timeout) { 2083 DEBUGOUT("Master requests are pending.\n"); 2084 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2085 } 2086 2087 return E1000_SUCCESS; 2088 } 2089 2090 /** 2091 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2092 * @hw: pointer to the HW structure 2093 * 2094 * Reset the Adaptive Interframe Spacing throttle to default values. 2095 **/ 2096 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2097 { 2098 struct e1000_mac_info *mac = &hw->mac; 2099 2100 DEBUGFUNC("e1000_reset_adaptive_generic"); 2101 2102 if (!mac->adaptive_ifs) { 2103 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2104 return; 2105 } 2106 2107 mac->current_ifs_val = 0; 2108 mac->ifs_min_val = IFS_MIN; 2109 mac->ifs_max_val = IFS_MAX; 2110 mac->ifs_step_size = IFS_STEP; 2111 mac->ifs_ratio = IFS_RATIO; 2112 2113 mac->in_ifs_mode = false; 2114 E1000_WRITE_REG(hw, E1000_AIT, 0); 2115 } 2116 2117 /** 2118 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2119 * @hw: pointer to the HW structure 2120 * 2121 * Update the Adaptive Interframe Spacing Throttle value based on the 2122 * time between transmitted packets and time between collisions. 2123 **/ 2124 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2125 { 2126 struct e1000_mac_info *mac = &hw->mac; 2127 2128 DEBUGFUNC("e1000_update_adaptive_generic"); 2129 2130 if (!mac->adaptive_ifs) { 2131 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2132 return; 2133 } 2134 2135 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2136 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2137 mac->in_ifs_mode = true; 2138 if (mac->current_ifs_val < mac->ifs_max_val) { 2139 if (!mac->current_ifs_val) 2140 mac->current_ifs_val = mac->ifs_min_val; 2141 else 2142 mac->current_ifs_val += 2143 mac->ifs_step_size; 2144 E1000_WRITE_REG(hw, E1000_AIT, 2145 mac->current_ifs_val); 2146 } 2147 } 2148 } else { 2149 if (mac->in_ifs_mode && 2150 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2151 mac->current_ifs_val = 0; 2152 mac->in_ifs_mode = false; 2153 E1000_WRITE_REG(hw, E1000_AIT, 0); 2154 } 2155 } 2156 } 2157 2158 /** 2159 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2160 * @hw: pointer to the HW structure 2161 * 2162 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2163 * set, which is forced to MDI mode only. 2164 **/ 2165 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2166 { 2167 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2168 2169 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2170 DEBUGOUT("Invalid MDI setting detected\n"); 2171 hw->phy.mdix = 1; 2172 return -E1000_ERR_CONFIG; 2173 } 2174 2175 return E1000_SUCCESS; 2176 } 2177 2178 /** 2179 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2180 * @hw: pointer to the HW structure 2181 * 2182 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2183 * operation. 2184 **/ 2185 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2186 { 2187 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2188 2189 return E1000_SUCCESS; 2190 } 2191 2192 /** 2193 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2194 * @hw: pointer to the HW structure 2195 * @reg: 32bit register offset such as E1000_SCTL 2196 * @offset: register offset to write to 2197 * @data: data to write at register offset 2198 * 2199 * Writes an address/data control type register. There are several of these 2200 * and they all have the format address << 8 | data and bit 31 is polled for 2201 * completion. 2202 **/ 2203 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2204 u32 offset, u8 data) 2205 { 2206 u32 i, regvalue = 0; 2207 2208 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2209 2210 /* Set up the address and data */ 2211 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2212 E1000_WRITE_REG(hw, reg, regvalue); 2213 2214 /* Poll the ready bit to see if the MDI read completed */ 2215 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2216 usec_delay(5); 2217 regvalue = E1000_READ_REG(hw, reg); 2218 if (regvalue & E1000_GEN_CTL_READY) 2219 break; 2220 } 2221 if (!(regvalue & E1000_GEN_CTL_READY)) { 2222 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2223 return -E1000_ERR_PHY; 2224 } 2225 2226 return E1000_SUCCESS; 2227 } 2228 2229 /** 2230 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 2231 * @hw: pointer to the HW structure 2232 * 2233 * Acquire the HW semaphore to access the PHY or NVM 2234 **/ 2235 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 2236 { 2237 u32 swsm; 2238 s32 timeout = E1000_SWSM_TIMEOUT; 2239 s32 i = 0; 2240 2241 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 2242 2243 /* Get the SW semaphore */ 2244 while (i < timeout) { 2245 swsm = E1000_READ_REG(hw, E1000_SWSM); 2246 if (!(swsm & E1000_SWSM_SMBI)) 2247 break; 2248 2249 usec_delay(50); 2250 i++; 2251 } 2252 2253 if (i == timeout) { 2254 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 2255 return -E1000_ERR_NVM; 2256 } 2257 2258 /* Get the FW semaphore. */ 2259 for (i = 0; i < timeout; i++) { 2260 swsm = E1000_READ_REG(hw, E1000_SWSM); 2261 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 2262 2263 /* Semaphore acquired if bit latched */ 2264 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 2265 break; 2266 2267 usec_delay(50); 2268 } 2269 2270 if (i == timeout) { 2271 /* Release semaphores */ 2272 e1000_put_hw_semaphore(hw); 2273 DEBUGOUT("Driver can't access the NVM\n"); 2274 return -E1000_ERR_NVM; 2275 } 2276 2277 return E1000_SUCCESS; 2278 } 2279 2280 /** 2281 * e1000_put_hw_semaphore - Release hardware semaphore 2282 * @hw: pointer to the HW structure 2283 * 2284 * Release hardware semaphore used to access the PHY or NVM 2285 **/ 2286 void e1000_put_hw_semaphore(struct e1000_hw *hw) 2287 { 2288 u32 swsm; 2289 2290 DEBUGFUNC("e1000_put_hw_semaphore"); 2291 2292 swsm = E1000_READ_REG(hw, E1000_SWSM); 2293 2294 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 2295 2296 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 2297 } 2298 2299 2300 /** 2301 * e1000_acquire_swfw_sync - Acquire SW/FW semaphore 2302 * @hw: pointer to the HW structure 2303 * @mask: specifies which semaphore to acquire 2304 * 2305 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 2306 * will also specify which port we're acquiring the lock for. 2307 **/ 2308 s32 2309 e1000_acquire_swfw_sync(struct e1000_hw *hw, u16 mask) 2310 { 2311 u32 swfw_sync; 2312 u32 swmask = mask; 2313 u32 fwmask = mask << 16; 2314 s32 ret_val = E1000_SUCCESS; 2315 s32 i = 0, timeout = 200; 2316 2317 DEBUGFUNC("e1000_acquire_swfw_sync"); 2318 ASSERT_NO_LOCKS(); 2319 while (i < timeout) { 2320 if (e1000_get_hw_semaphore_generic(hw)) { 2321 ret_val = -E1000_ERR_SWFW_SYNC; 2322 goto out; 2323 } 2324 2325 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 2326 if (!(swfw_sync & (fwmask | swmask))) 2327 break; 2328 2329 /* 2330 * Firmware currently using resource (fwmask) 2331 * or other software thread using resource (swmask) 2332 */ 2333 e1000_put_hw_semaphore(hw); 2334 msec_delay_irq(5); 2335 i++; 2336 } 2337 2338 if (i == timeout) { 2339 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2340 ret_val = -E1000_ERR_SWFW_SYNC; 2341 goto out; 2342 } 2343 2344 swfw_sync |= swmask; 2345 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 2346 2347 e1000_put_hw_semaphore(hw); 2348 2349 out: 2350 return ret_val; 2351 } 2352 2353 /** 2354 * e1000_release_swfw_sync - Release SW/FW semaphore 2355 * @hw: pointer to the HW structure 2356 * @mask: specifies which semaphore to acquire 2357 * 2358 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 2359 * will also specify which port we're releasing the lock for. 2360 **/ 2361 void 2362 e1000_release_swfw_sync(struct e1000_hw *hw, u16 mask) 2363 { 2364 u32 swfw_sync; 2365 2366 DEBUGFUNC("e1000_release_swfw_sync"); 2367 2368 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 2369 ; /* Empty */ 2370 2371 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 2372 swfw_sync &= (u32)~mask; 2373 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 2374 2375 e1000_put_hw_semaphore(hw); 2376 } 2377