xref: /freebsd/sys/dev/e1000/e1000_mac.c (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c)
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4   Copyright (c) 2001-2020, Intel Corporation
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33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #include "e1000_api.h"
37 
38 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
39 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
40 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
41 
42 /**
43  *  e1000_init_mac_ops_generic - Initialize MAC function pointers
44  *  @hw: pointer to the HW structure
45  *
46  *  Setups up the function pointers to no-op functions
47  **/
48 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
49 {
50 	struct e1000_mac_info *mac = &hw->mac;
51 	DEBUGFUNC("e1000_init_mac_ops_generic");
52 
53 	/* General Setup */
54 	mac->ops.init_params = e1000_null_ops_generic;
55 	mac->ops.init_hw = e1000_null_ops_generic;
56 	mac->ops.reset_hw = e1000_null_ops_generic;
57 	mac->ops.setup_physical_interface = e1000_null_ops_generic;
58 	mac->ops.get_bus_info = e1000_null_ops_generic;
59 	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
60 	mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
61 	mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
62 	mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
63 	/* LED */
64 	mac->ops.cleanup_led = e1000_null_ops_generic;
65 	mac->ops.setup_led = e1000_null_ops_generic;
66 	mac->ops.blink_led = e1000_null_ops_generic;
67 	mac->ops.led_on = e1000_null_ops_generic;
68 	mac->ops.led_off = e1000_null_ops_generic;
69 	/* LINK */
70 	mac->ops.setup_link = e1000_null_ops_generic;
71 	mac->ops.get_link_up_info = e1000_null_link_info;
72 	mac->ops.check_for_link = e1000_null_ops_generic;
73 	mac->ops.set_obff_timer = e1000_null_set_obff_timer;
74 	/* Management */
75 	mac->ops.check_mng_mode = e1000_null_mng_mode;
76 	/* VLAN, MC, etc. */
77 	mac->ops.update_mc_addr_list = e1000_null_update_mc;
78 	mac->ops.clear_vfta = e1000_null_mac_generic;
79 	mac->ops.write_vfta = e1000_null_write_vfta;
80 	mac->ops.rar_set = e1000_rar_set_generic;
81 	mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
82 }
83 
84 /**
85  *  e1000_null_ops_generic - No-op function, returns 0
86  *  @hw: pointer to the HW structure
87  **/
88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
89 {
90 	DEBUGFUNC("e1000_null_ops_generic");
91 	return E1000_SUCCESS;
92 }
93 
94 /**
95  *  e1000_null_mac_generic - No-op function, return void
96  *  @hw: pointer to the HW structure
97  **/
98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
99 {
100 	DEBUGFUNC("e1000_null_mac_generic");
101 	return;
102 }
103 
104 /**
105  *  e1000_null_link_info - No-op function, return 0
106  *  @hw: pointer to the HW structure
107  *  @s: dummy variable
108  *  @d: dummy variable
109  **/
110 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
111 			 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
112 {
113 	DEBUGFUNC("e1000_null_link_info");
114 	return E1000_SUCCESS;
115 }
116 
117 /**
118  *  e1000_null_mng_mode - No-op function, return false
119  *  @hw: pointer to the HW structure
120  **/
121 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
122 {
123 	DEBUGFUNC("e1000_null_mng_mode");
124 	return false;
125 }
126 
127 /**
128  *  e1000_null_update_mc - No-op function, return void
129  *  @hw: pointer to the HW structure
130  *  @h: dummy variable
131  *  @a: dummy variable
132  **/
133 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
134 			  u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
135 {
136 	DEBUGFUNC("e1000_null_update_mc");
137 	return;
138 }
139 
140 /**
141  *  e1000_null_write_vfta - No-op function, return void
142  *  @hw: pointer to the HW structure
143  *  @a: dummy variable
144  *  @b: dummy variable
145  **/
146 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
147 			   u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
148 {
149 	DEBUGFUNC("e1000_null_write_vfta");
150 	return;
151 }
152 
153 /**
154  *  e1000_null_rar_set - No-op function, return 0
155  *  @hw: pointer to the HW structure
156  *  @h: dummy variable
157  *  @a: dummy variable
158  **/
159 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
160 			u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
161 {
162 	DEBUGFUNC("e1000_null_rar_set");
163 	return E1000_SUCCESS;
164 }
165 
166 /**
167  *  e1000_null_set_obff_timer - No-op function, return 0
168  *  @hw: pointer to the HW structure
169  **/
170 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
171 			      u32 E1000_UNUSEDARG a)
172 {
173 	DEBUGFUNC("e1000_null_set_obff_timer");
174 	return E1000_SUCCESS;
175 }
176 
177 /**
178  *  e1000_get_bus_info_pci_generic - Get PCI(x) bus information
179  *  @hw: pointer to the HW structure
180  *
181  *  Determines and stores the system bus information for a particular
182  *  network interface.  The following bus information is determined and stored:
183  *  bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
184  **/
185 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
186 {
187 	struct e1000_mac_info *mac = &hw->mac;
188 	struct e1000_bus_info *bus = &hw->bus;
189 	u32 status = E1000_READ_REG(hw, E1000_STATUS);
190 	s32 ret_val = E1000_SUCCESS;
191 
192 	DEBUGFUNC("e1000_get_bus_info_pci_generic");
193 
194 	/* PCI or PCI-X? */
195 	bus->type = (status & E1000_STATUS_PCIX_MODE)
196 			? e1000_bus_type_pcix
197 			: e1000_bus_type_pci;
198 
199 	/* Bus speed */
200 	if (bus->type == e1000_bus_type_pci) {
201 		bus->speed = (status & E1000_STATUS_PCI66)
202 			     ? e1000_bus_speed_66
203 			     : e1000_bus_speed_33;
204 	} else {
205 		switch (status & E1000_STATUS_PCIX_SPEED) {
206 		case E1000_STATUS_PCIX_SPEED_66:
207 			bus->speed = e1000_bus_speed_66;
208 			break;
209 		case E1000_STATUS_PCIX_SPEED_100:
210 			bus->speed = e1000_bus_speed_100;
211 			break;
212 		case E1000_STATUS_PCIX_SPEED_133:
213 			bus->speed = e1000_bus_speed_133;
214 			break;
215 		default:
216 			bus->speed = e1000_bus_speed_reserved;
217 			break;
218 		}
219 	}
220 
221 	/* Bus width */
222 	bus->width = (status & E1000_STATUS_BUS64)
223 		     ? e1000_bus_width_64
224 		     : e1000_bus_width_32;
225 
226 	/* Which PCI(-X) function? */
227 	mac->ops.set_lan_id(hw);
228 
229 	return ret_val;
230 }
231 
232 /**
233  *  e1000_get_bus_info_pcie_generic - Get PCIe bus information
234  *  @hw: pointer to the HW structure
235  *
236  *  Determines and stores the system bus information for a particular
237  *  network interface.  The following bus information is determined and stored:
238  *  bus speed, bus width, type (PCIe), and PCIe function.
239  **/
240 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
241 {
242 	struct e1000_mac_info *mac = &hw->mac;
243 	struct e1000_bus_info *bus = &hw->bus;
244 	s32 ret_val;
245 	u16 pcie_link_status;
246 
247 	DEBUGFUNC("e1000_get_bus_info_pcie_generic");
248 
249 	bus->type = e1000_bus_type_pci_express;
250 
251 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
252 					  &pcie_link_status);
253 	if (ret_val) {
254 		bus->width = e1000_bus_width_unknown;
255 		bus->speed = e1000_bus_speed_unknown;
256 	} else {
257 		switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
258 		case PCIE_LINK_SPEED_2500:
259 			bus->speed = e1000_bus_speed_2500;
260 			break;
261 		case PCIE_LINK_SPEED_5000:
262 			bus->speed = e1000_bus_speed_5000;
263 			break;
264 		default:
265 			bus->speed = e1000_bus_speed_unknown;
266 			break;
267 		}
268 
269 		bus->width = (enum e1000_bus_width)((pcie_link_status &
270 			      PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
271 	}
272 
273 	mac->ops.set_lan_id(hw);
274 
275 	return E1000_SUCCESS;
276 }
277 
278 /**
279  *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
280  *
281  *  @hw: pointer to the HW structure
282  *
283  *  Determines the LAN function id by reading memory-mapped registers
284  *  and swaps the port value if requested.
285  **/
286 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
287 {
288 	struct e1000_bus_info *bus = &hw->bus;
289 	u32 reg;
290 
291 	/* The status register reports the correct function number
292 	 * for the device regardless of function swap state.
293 	 */
294 	reg = E1000_READ_REG(hw, E1000_STATUS);
295 	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
296 }
297 
298 /**
299  *  e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
300  *  @hw: pointer to the HW structure
301  *
302  *  Determines the LAN function id by reading PCI config space.
303  **/
304 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
305 {
306 	struct e1000_bus_info *bus = &hw->bus;
307 	u16 pci_header_type;
308 	u32 status;
309 
310 	e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
311 	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
312 		status = E1000_READ_REG(hw, E1000_STATUS);
313 		bus->func = (status & E1000_STATUS_FUNC_MASK)
314 			    >> E1000_STATUS_FUNC_SHIFT;
315 	} else {
316 		bus->func = 0;
317 	}
318 }
319 
320 /**
321  *  e1000_set_lan_id_single_port - Set LAN id for a single port device
322  *  @hw: pointer to the HW structure
323  *
324  *  Sets the LAN function id to zero for a single port device.
325  **/
326 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
327 {
328 	struct e1000_bus_info *bus = &hw->bus;
329 
330 	bus->func = 0;
331 }
332 
333 /**
334  *  e1000_clear_vfta_generic - Clear VLAN filter table
335  *  @hw: pointer to the HW structure
336  *
337  *  Clears the register array which contains the VLAN filter table by
338  *  setting all the values to 0.
339  **/
340 void e1000_clear_vfta_generic(struct e1000_hw *hw)
341 {
342 	u32 offset;
343 
344 	DEBUGFUNC("e1000_clear_vfta_generic");
345 
346 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
347 		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
348 		E1000_WRITE_FLUSH(hw);
349 	}
350 }
351 
352 /**
353  *  e1000_write_vfta_generic - Write value to VLAN filter table
354  *  @hw: pointer to the HW structure
355  *  @offset: register offset in VLAN filter table
356  *  @value: register value written to VLAN filter table
357  *
358  *  Writes value at the given offset in the register array which stores
359  *  the VLAN filter table.
360  **/
361 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
362 {
363 	DEBUGFUNC("e1000_write_vfta_generic");
364 
365 	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
366 	E1000_WRITE_FLUSH(hw);
367 }
368 
369 /**
370  *  e1000_init_rx_addrs_generic - Initialize receive address's
371  *  @hw: pointer to the HW structure
372  *  @rar_count: receive address registers
373  *
374  *  Setup the receive address registers by setting the base receive address
375  *  register to the devices MAC address and clearing all the other receive
376  *  address registers to 0.
377  **/
378 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
379 {
380 	u32 i;
381 	u8 mac_addr[ETHER_ADDR_LEN] = {0};
382 
383 	DEBUGFUNC("e1000_init_rx_addrs_generic");
384 
385 	/* Setup the receive address */
386 	DEBUGOUT("Programming MAC Address into RAR[0]\n");
387 
388 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
389 
390 	/* Zero out the other (rar_entry_count - 1) receive addresses */
391 	DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
392 	for (i = 1; i < rar_count; i++)
393 		hw->mac.ops.rar_set(hw, mac_addr, i);
394 }
395 
396 /**
397  *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
398  *  @hw: pointer to the HW structure
399  *
400  *  Checks the nvm for an alternate MAC address.  An alternate MAC address
401  *  can be setup by pre-boot software and must be treated like a permanent
402  *  address and must override the actual permanent MAC address. If an
403  *  alternate MAC address is found it is programmed into RAR0, replacing
404  *  the permanent address that was installed into RAR0 by the Si on reset.
405  *  This function will return SUCCESS unless it encounters an error while
406  *  reading the EEPROM.
407  **/
408 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
409 {
410 	u32 i;
411 	s32 ret_val;
412 	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
413 	u8 alt_mac_addr[ETHER_ADDR_LEN];
414 
415 	DEBUGFUNC("e1000_check_alt_mac_addr_generic");
416 
417 	ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
418 	if (ret_val)
419 		return ret_val;
420 
421 	/* not supported on older hardware or 82573 */
422 	if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
423 		return E1000_SUCCESS;
424 
425 	/* Alternate MAC address is handled by the option ROM for 82580
426 	 * and newer. SW support not required.
427 	 */
428 	if (hw->mac.type >= e1000_82580)
429 		return E1000_SUCCESS;
430 
431 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
432 				   &nvm_alt_mac_addr_offset);
433 	if (ret_val) {
434 		DEBUGOUT("NVM Read Error\n");
435 		return ret_val;
436 	}
437 
438 	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
439 	    (nvm_alt_mac_addr_offset == 0x0000))
440 		/* There is no Alternate MAC Address */
441 		return E1000_SUCCESS;
442 
443 	if (hw->bus.func == E1000_FUNC_1)
444 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
445 	if (hw->bus.func == E1000_FUNC_2)
446 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
447 
448 	if (hw->bus.func == E1000_FUNC_3)
449 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
450 	for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
451 		offset = nvm_alt_mac_addr_offset + (i >> 1);
452 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
453 		if (ret_val) {
454 			DEBUGOUT("NVM Read Error\n");
455 			return ret_val;
456 		}
457 
458 		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
459 		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
460 	}
461 
462 	/* if multicast bit is set, the alternate address will not be used */
463 	if (alt_mac_addr[0] & 0x01) {
464 		DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
465 		return E1000_SUCCESS;
466 	}
467 
468 	/* We have a valid alternate MAC address, and we want to treat it the
469 	 * same as the normal permanent MAC address stored by the HW into the
470 	 * RAR. Do this by mapping this address into RAR0.
471 	 */
472 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
473 
474 	return E1000_SUCCESS;
475 }
476 
477 /**
478  *  e1000_rar_set_generic - Set receive address register
479  *  @hw: pointer to the HW structure
480  *  @addr: pointer to the receive address
481  *  @index: receive address array register
482  *
483  *  Sets the receive address array register at index to the address passed
484  *  in by addr.
485  **/
486 int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
487 {
488 	u32 rar_low, rar_high;
489 
490 	DEBUGFUNC("e1000_rar_set_generic");
491 
492 	/* HW expects these in little endian so we reverse the byte order
493 	 * from network order (big endian) to little endian
494 	 */
495 	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
496 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
497 
498 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
499 
500 	/* If MAC address zero, no need to set the AV bit */
501 	if (rar_low || rar_high)
502 		rar_high |= E1000_RAH_AV;
503 
504 	/* Some bridges will combine consecutive 32-bit writes into
505 	 * a single burst write, which will malfunction on some parts.
506 	 * The flushes avoid this.
507 	 */
508 	E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
509 	E1000_WRITE_FLUSH(hw);
510 	E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
511 	E1000_WRITE_FLUSH(hw);
512 
513 	return E1000_SUCCESS;
514 }
515 
516 /**
517  *  e1000_hash_mc_addr_generic - Generate a multicast hash value
518  *  @hw: pointer to the HW structure
519  *  @mc_addr: pointer to a multicast address
520  *
521  *  Generates a multicast address hash value which is used to determine
522  *  the multicast filter table array address and new table value.
523  **/
524 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
525 {
526 	u32 hash_value, hash_mask;
527 	u8 bit_shift = 0;
528 
529 	DEBUGFUNC("e1000_hash_mc_addr_generic");
530 
531 	/* Register count multiplied by bits per register */
532 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
533 
534 	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts
535 	 * where 0xFF would still fall within the hash mask.
536 	 */
537 	while (hash_mask >> bit_shift != 0xFF)
538 		bit_shift++;
539 
540 	/* The portion of the address that is used for the hash table
541 	 * is determined by the mc_filter_type setting.
542 	 * The algorithm is such that there is a total of 8 bits of shifting.
543 	 * The bit_shift for a mc_filter_type of 0 represents the number of
544 	 * left-shifts where the MSB of mc_addr[5] would still fall within
545 	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
546 	 * of 8 bits of shifting, then mc_addr[4] will shift right the
547 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
548 	 * cases are a variation of this algorithm...essentially raising the
549 	 * number of bits to shift mc_addr[5] left, while still keeping the
550 	 * 8-bit shifting total.
551 	 *
552 	 * For example, given the following Destination MAC Address and an
553 	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
554 	 * we can see that the bit_shift for case 0 is 4.  These are the hash
555 	 * values resulting from each mc_filter_type...
556 	 * [0] [1] [2] [3] [4] [5]
557 	 * 01  AA  00  12  34  56
558 	 * LSB		 MSB
559 	 *
560 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
561 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
562 	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
563 	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
564 	 */
565 	switch (hw->mac.mc_filter_type) {
566 	default:
567 	case 0:
568 		break;
569 	case 1:
570 		bit_shift += 1;
571 		break;
572 	case 2:
573 		bit_shift += 2;
574 		break;
575 	case 3:
576 		bit_shift += 4;
577 		break;
578 	}
579 
580 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
581 				  (((u16) mc_addr[5]) << bit_shift)));
582 
583 	return hash_value;
584 }
585 
586 /**
587  *  e1000_update_mc_addr_list_generic - Update Multicast addresses
588  *  @hw: pointer to the HW structure
589  *  @mc_addr_list: array of multicast addresses to program
590  *  @mc_addr_count: number of multicast addresses to program
591  *
592  *  Updates entire Multicast Table Array.
593  *  The caller must have a packed mc_addr_list of multicast addresses.
594  **/
595 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
596 				       u8 *mc_addr_list, u32 mc_addr_count)
597 {
598 	u32 hash_value, hash_bit, hash_reg;
599 	int i;
600 
601 	DEBUGFUNC("e1000_update_mc_addr_list_generic");
602 
603 	/* clear mta_shadow */
604 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
605 
606 	/* update mta_shadow from mc_addr_list */
607 	for (i = 0; (u32) i < mc_addr_count; i++) {
608 		hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
609 
610 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
611 		hash_bit = hash_value & 0x1F;
612 
613 		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
614 		mc_addr_list += (ETHER_ADDR_LEN);
615 	}
616 
617 	/* replace the entire MTA table */
618 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
619 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
620 	E1000_WRITE_FLUSH(hw);
621 }
622 
623 /**
624  *  e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
625  *  @hw: pointer to the HW structure
626  *
627  *  In certain situations, a system BIOS may report that the PCIx maximum
628  *  memory read byte count (MMRBC) value is higher than than the actual
629  *  value. We check the PCIx command register with the current PCIx status
630  *  register.
631  **/
632 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
633 {
634 	u16 cmd_mmrbc;
635 	u16 pcix_cmd;
636 	u16 pcix_stat_hi_word;
637 	u16 stat_mmrbc;
638 
639 	DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
640 
641 	/* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
642 	if (hw->bus.type != e1000_bus_type_pcix)
643 		return;
644 
645 	e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
646 	e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
647 	cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
648 		     PCIX_COMMAND_MMRBC_SHIFT;
649 	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
650 		      PCIX_STATUS_HI_MMRBC_SHIFT;
651 	if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
652 		stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
653 	if (cmd_mmrbc > stat_mmrbc) {
654 		pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
655 		pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
656 		e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
657 	}
658 }
659 
660 /**
661  *  e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
662  *  @hw: pointer to the HW structure
663  *
664  *  Clears the base hardware counters by reading the counter registers.
665  **/
666 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
667 {
668 	DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
669 
670 	E1000_READ_REG(hw, E1000_CRCERRS);
671 	E1000_READ_REG(hw, E1000_SYMERRS);
672 	E1000_READ_REG(hw, E1000_MPC);
673 	E1000_READ_REG(hw, E1000_SCC);
674 	E1000_READ_REG(hw, E1000_ECOL);
675 	E1000_READ_REG(hw, E1000_MCC);
676 	E1000_READ_REG(hw, E1000_LATECOL);
677 	E1000_READ_REG(hw, E1000_COLC);
678 	E1000_READ_REG(hw, E1000_DC);
679 	E1000_READ_REG(hw, E1000_SEC);
680 	E1000_READ_REG(hw, E1000_RLEC);
681 	E1000_READ_REG(hw, E1000_XONRXC);
682 	E1000_READ_REG(hw, E1000_XONTXC);
683 	E1000_READ_REG(hw, E1000_XOFFRXC);
684 	E1000_READ_REG(hw, E1000_XOFFTXC);
685 	E1000_READ_REG(hw, E1000_FCRUC);
686 	E1000_READ_REG(hw, E1000_GPRC);
687 	E1000_READ_REG(hw, E1000_BPRC);
688 	E1000_READ_REG(hw, E1000_MPRC);
689 	E1000_READ_REG(hw, E1000_GPTC);
690 	E1000_READ_REG(hw, E1000_GORCL);
691 	E1000_READ_REG(hw, E1000_GORCH);
692 	E1000_READ_REG(hw, E1000_GOTCL);
693 	E1000_READ_REG(hw, E1000_GOTCH);
694 	E1000_READ_REG(hw, E1000_RNBC);
695 	E1000_READ_REG(hw, E1000_RUC);
696 	E1000_READ_REG(hw, E1000_RFC);
697 	E1000_READ_REG(hw, E1000_ROC);
698 	E1000_READ_REG(hw, E1000_RJC);
699 	E1000_READ_REG(hw, E1000_TORL);
700 	E1000_READ_REG(hw, E1000_TORH);
701 	E1000_READ_REG(hw, E1000_TOTL);
702 	E1000_READ_REG(hw, E1000_TOTH);
703 	E1000_READ_REG(hw, E1000_TPR);
704 	E1000_READ_REG(hw, E1000_TPT);
705 	E1000_READ_REG(hw, E1000_MPTC);
706 	E1000_READ_REG(hw, E1000_BPTC);
707 }
708 
709 /**
710  *  e1000_check_for_copper_link_generic - Check for link (Copper)
711  *  @hw: pointer to the HW structure
712  *
713  *  Checks to see of the link status of the hardware has changed.  If a
714  *  change in link status has been detected, then we read the PHY registers
715  *  to get the current speed/duplex if link exists.
716  **/
717 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
718 {
719 	struct e1000_mac_info *mac = &hw->mac;
720 	s32 ret_val;
721 	bool link;
722 
723 	DEBUGFUNC("e1000_check_for_copper_link");
724 
725 	/* We only want to go out to the PHY registers to see if Auto-Neg
726 	 * has completed and/or if our link status has changed.  The
727 	 * get_link_status flag is set upon receiving a Link Status
728 	 * Change or Rx Sequence Error interrupt.
729 	 */
730 	if (!mac->get_link_status)
731 		return E1000_SUCCESS;
732 
733 	/* First we want to see if the MII Status Register reports
734 	 * link.  If so, then we want to get the current speed/duplex
735 	 * of the PHY.
736 	 */
737 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
738 	if (ret_val)
739 		return ret_val;
740 
741 	if (!link)
742 		return E1000_SUCCESS; /* No link detected */
743 
744 	mac->get_link_status = false;
745 
746 	/* Check if there was DownShift, must be checked
747 	 * immediately after link-up
748 	 */
749 	e1000_check_downshift_generic(hw);
750 
751 	/* If we are forcing speed/duplex, then we simply return since
752 	 * we have already determined whether we have link or not.
753 	 */
754 	if (!mac->autoneg)
755 		return -E1000_ERR_CONFIG;
756 
757 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
758 	 * of MAC speed/duplex configuration.  So we only need to
759 	 * configure Collision Distance in the MAC.
760 	 */
761 	mac->ops.config_collision_dist(hw);
762 
763 	/* Configure Flow Control now that Auto-Neg has completed.
764 	 * First, we need to restore the desired flow control
765 	 * settings because we may have had to re-autoneg with a
766 	 * different link partner.
767 	 */
768 	ret_val = e1000_config_fc_after_link_up_generic(hw);
769 	if (ret_val)
770 		DEBUGOUT("Error configuring flow control\n");
771 
772 	return ret_val;
773 }
774 
775 /**
776  *  e1000_check_for_fiber_link_generic - Check for link (Fiber)
777  *  @hw: pointer to the HW structure
778  *
779  *  Checks for link up on the hardware.  If link is not up and we have
780  *  a signal, then we need to force link up.
781  **/
782 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
783 {
784 	struct e1000_mac_info *mac = &hw->mac;
785 	u32 rxcw;
786 	u32 ctrl;
787 	u32 status;
788 	s32 ret_val;
789 
790 	DEBUGFUNC("e1000_check_for_fiber_link_generic");
791 
792 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
793 	status = E1000_READ_REG(hw, E1000_STATUS);
794 	rxcw = E1000_READ_REG(hw, E1000_RXCW);
795 
796 	/* If we don't have link (auto-negotiation failed or link partner
797 	 * cannot auto-negotiate), the cable is plugged in (we have signal),
798 	 * and our link partner is not trying to auto-negotiate with us (we
799 	 * are receiving idles or data), we need to force link up. We also
800 	 * need to give auto-negotiation time to complete, in case the cable
801 	 * was just plugged in. The autoneg_failed flag does this.
802 	 */
803 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
804 	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
805 	    !(rxcw & E1000_RXCW_C)) {
806 		if (!mac->autoneg_failed) {
807 			mac->autoneg_failed = true;
808 			return E1000_SUCCESS;
809 		}
810 		DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
811 
812 		/* Disable auto-negotiation in the TXCW register */
813 		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
814 
815 		/* Force link-up and also force full-duplex. */
816 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
817 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
818 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
819 
820 		/* Configure Flow Control after forcing link up. */
821 		ret_val = e1000_config_fc_after_link_up_generic(hw);
822 		if (ret_val) {
823 			DEBUGOUT("Error configuring flow control\n");
824 			return ret_val;
825 		}
826 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
827 		/* If we are forcing link and we are receiving /C/ ordered
828 		 * sets, re-enable auto-negotiation in the TXCW register
829 		 * and disable forced link in the Device Control register
830 		 * in an attempt to auto-negotiate with our link partner.
831 		 */
832 		DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
833 		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
834 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
835 
836 		mac->serdes_has_link = true;
837 	}
838 
839 	return E1000_SUCCESS;
840 }
841 
842 /**
843  *  e1000_check_for_serdes_link_generic - Check for link (Serdes)
844  *  @hw: pointer to the HW structure
845  *
846  *  Checks for link up on the hardware.  If link is not up and we have
847  *  a signal, then we need to force link up.
848  **/
849 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
850 {
851 	struct e1000_mac_info *mac = &hw->mac;
852 	u32 rxcw;
853 	u32 ctrl;
854 	u32 status;
855 	s32 ret_val;
856 
857 	DEBUGFUNC("e1000_check_for_serdes_link_generic");
858 
859 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
860 	status = E1000_READ_REG(hw, E1000_STATUS);
861 	rxcw = E1000_READ_REG(hw, E1000_RXCW);
862 
863 	/* If we don't have link (auto-negotiation failed or link partner
864 	 * cannot auto-negotiate), and our link partner is not trying to
865 	 * auto-negotiate with us (we are receiving idles or data),
866 	 * we need to force link up. We also need to give auto-negotiation
867 	 * time to complete.
868 	 */
869 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
870 	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
871 		if (!mac->autoneg_failed) {
872 			mac->autoneg_failed = true;
873 			return E1000_SUCCESS;
874 		}
875 		DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
876 
877 		/* Disable auto-negotiation in the TXCW register */
878 		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
879 
880 		/* Force link-up and also force full-duplex. */
881 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
882 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
883 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
884 
885 		/* Configure Flow Control after forcing link up. */
886 		ret_val = e1000_config_fc_after_link_up_generic(hw);
887 		if (ret_val) {
888 			DEBUGOUT("Error configuring flow control\n");
889 			return ret_val;
890 		}
891 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
892 		/* If we are forcing link and we are receiving /C/ ordered
893 		 * sets, re-enable auto-negotiation in the TXCW register
894 		 * and disable forced link in the Device Control register
895 		 * in an attempt to auto-negotiate with our link partner.
896 		 */
897 		DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
898 		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
899 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
900 
901 		mac->serdes_has_link = true;
902 	} else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
903 		/* If we force link for non-auto-negotiation switch, check
904 		 * link status based on MAC synchronization for internal
905 		 * serdes media type.
906 		 */
907 		/* SYNCH bit and IV bit are sticky. */
908 		usec_delay(10);
909 		rxcw = E1000_READ_REG(hw, E1000_RXCW);
910 		if (rxcw & E1000_RXCW_SYNCH) {
911 			if (!(rxcw & E1000_RXCW_IV)) {
912 				mac->serdes_has_link = true;
913 				DEBUGOUT("SERDES: Link up - forced.\n");
914 			}
915 		} else {
916 			mac->serdes_has_link = false;
917 			DEBUGOUT("SERDES: Link down - force failed.\n");
918 		}
919 	}
920 
921 	if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
922 		status = E1000_READ_REG(hw, E1000_STATUS);
923 		if (status & E1000_STATUS_LU) {
924 			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
925 			usec_delay(10);
926 			rxcw = E1000_READ_REG(hw, E1000_RXCW);
927 			if (rxcw & E1000_RXCW_SYNCH) {
928 				if (!(rxcw & E1000_RXCW_IV)) {
929 					mac->serdes_has_link = true;
930 					DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
931 				} else {
932 					mac->serdes_has_link = false;
933 					DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
934 				}
935 			} else {
936 				mac->serdes_has_link = false;
937 				DEBUGOUT("SERDES: Link down - no sync.\n");
938 			}
939 		} else {
940 			mac->serdes_has_link = false;
941 			DEBUGOUT("SERDES: Link down - autoneg failed\n");
942 		}
943 	}
944 
945 	return E1000_SUCCESS;
946 }
947 
948 /**
949  *  e1000_set_default_fc_generic - Set flow control default values
950  *  @hw: pointer to the HW structure
951  *
952  *  Read the EEPROM for the default values for flow control and store the
953  *  values.
954  **/
955 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
956 {
957 	s32 ret_val;
958 	u16 nvm_data;
959 	u16 nvm_offset = 0;
960 
961 	DEBUGFUNC("e1000_set_default_fc_generic");
962 
963 	/* Read and store word 0x0F of the EEPROM. This word contains bits
964 	 * that determine the hardware's default PAUSE (flow control) mode,
965 	 * a bit that determines whether the HW defaults to enabling or
966 	 * disabling auto-negotiation, and the direction of the
967 	 * SW defined pins. If there is no SW over-ride of the flow
968 	 * control setting, then the variable hw->fc will
969 	 * be initialized based on a value in the EEPROM.
970 	 */
971 	if (hw->mac.type == e1000_i350) {
972 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
973 		ret_val = hw->nvm.ops.read(hw,
974 					   NVM_INIT_CONTROL2_REG +
975 					   nvm_offset,
976 					   1, &nvm_data);
977 	} else {
978 		ret_val = hw->nvm.ops.read(hw,
979 					   NVM_INIT_CONTROL2_REG,
980 					   1, &nvm_data);
981 	}
982 
983 
984 	if (ret_val) {
985 		DEBUGOUT("NVM Read Error\n");
986 		return ret_val;
987 	}
988 
989 	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
990 		hw->fc.requested_mode = e1000_fc_none;
991 	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
992 		 NVM_WORD0F_ASM_DIR)
993 		hw->fc.requested_mode = e1000_fc_tx_pause;
994 	else
995 		hw->fc.requested_mode = e1000_fc_full;
996 
997 	return E1000_SUCCESS;
998 }
999 
1000 /**
1001  *  e1000_setup_link_generic - Setup flow control and link settings
1002  *  @hw: pointer to the HW structure
1003  *
1004  *  Determines which flow control settings to use, then configures flow
1005  *  control.  Calls the appropriate media-specific link configuration
1006  *  function.  Assuming the adapter has a valid link partner, a valid link
1007  *  should be established.  Assumes the hardware has previously been reset
1008  *  and the transmitter and receiver are not enabled.
1009  **/
1010 s32 e1000_setup_link_generic(struct e1000_hw *hw)
1011 {
1012 	s32 ret_val;
1013 
1014 	DEBUGFUNC("e1000_setup_link_generic");
1015 
1016 	/* In the case of the phy reset being blocked, we already have a link.
1017 	 * We do not need to set it up again.
1018 	 */
1019 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1020 		return E1000_SUCCESS;
1021 
1022 	/* If requested flow control is set to default, set flow control
1023 	 * based on the EEPROM flow control settings.
1024 	 */
1025 	if (hw->fc.requested_mode == e1000_fc_default) {
1026 		ret_val = e1000_set_default_fc_generic(hw);
1027 		if (ret_val)
1028 			return ret_val;
1029 	}
1030 
1031 	/* Save off the requested flow control mode for use later.  Depending
1032 	 * on the link partner's capabilities, we may or may not use this mode.
1033 	 */
1034 	hw->fc.current_mode = hw->fc.requested_mode;
1035 
1036 	DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1037 		hw->fc.current_mode);
1038 
1039 	/* Call the necessary media_type subroutine to configure the link. */
1040 	ret_val = hw->mac.ops.setup_physical_interface(hw);
1041 	if (ret_val)
1042 		return ret_val;
1043 
1044 	/* Initialize the flow control address, type, and PAUSE timer
1045 	 * registers to their default values.  This is done even if flow
1046 	 * control is disabled, because it does not hurt anything to
1047 	 * initialize these registers.
1048 	 */
1049 	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1050 	E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1051 	E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1052 	E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1053 
1054 	E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1055 
1056 	return e1000_set_fc_watermarks_generic(hw);
1057 }
1058 
1059 /**
1060  *  e1000_commit_fc_settings_generic - Configure flow control
1061  *  @hw: pointer to the HW structure
1062  *
1063  *  Write the flow control settings to the Transmit Config Word Register (TXCW)
1064  *  base on the flow control settings in e1000_mac_info.
1065  **/
1066 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1067 {
1068 	struct e1000_mac_info *mac = &hw->mac;
1069 	u32 txcw;
1070 
1071 	DEBUGFUNC("e1000_commit_fc_settings_generic");
1072 
1073 	/* Check for a software override of the flow control settings, and
1074 	 * setup the device accordingly.  If auto-negotiation is enabled, then
1075 	 * software will have to set the "PAUSE" bits to the correct value in
1076 	 * the Transmit Config Word Register (TXCW) and re-start auto-
1077 	 * negotiation.  However, if auto-negotiation is disabled, then
1078 	 * software will have to manually configure the two flow control enable
1079 	 * bits in the CTRL register.
1080 	 *
1081 	 * The possible values of the "fc" parameter are:
1082 	 *      0:  Flow control is completely disabled
1083 	 *      1:  Rx flow control is enabled (we can receive pause frames,
1084 	 *          but not send pause frames).
1085 	 *      2:  Tx flow control is enabled (we can send pause frames but we
1086 	 *          do not support receiving pause frames).
1087 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
1088 	 */
1089 	switch (hw->fc.current_mode) {
1090 	case e1000_fc_none:
1091 		/* Flow control completely disabled by a software over-ride. */
1092 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1093 		break;
1094 	case e1000_fc_rx_pause:
1095 		/* Rx Flow control is enabled and Tx Flow control is disabled
1096 		 * by a software over-ride. Since there really isn't a way to
1097 		 * advertise that we are capable of Rx Pause ONLY, we will
1098 		 * advertise that we support both symmetric and asymmetric Rx
1099 		 * PAUSE.  Later, we will disable the adapter's ability to send
1100 		 * PAUSE frames.
1101 		 */
1102 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1103 		break;
1104 	case e1000_fc_tx_pause:
1105 		/* Tx Flow control is enabled, and Rx Flow control is disabled,
1106 		 * by a software over-ride.
1107 		 */
1108 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1109 		break;
1110 	case e1000_fc_full:
1111 		/* Flow control (both Rx and Tx) is enabled by a software
1112 		 * over-ride.
1113 		 */
1114 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1115 		break;
1116 	default:
1117 		DEBUGOUT("Flow control param set incorrectly\n");
1118 		return -E1000_ERR_CONFIG;
1119 		break;
1120 	}
1121 
1122 	E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1123 	mac->txcw = txcw;
1124 
1125 	return E1000_SUCCESS;
1126 }
1127 
1128 /**
1129  *  e1000_poll_fiber_serdes_link_generic - Poll for link up
1130  *  @hw: pointer to the HW structure
1131  *
1132  *  Polls for link up by reading the status register, if link fails to come
1133  *  up with auto-negotiation, then the link is forced if a signal is detected.
1134  **/
1135 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1136 {
1137 	struct e1000_mac_info *mac = &hw->mac;
1138 	u32 i, status;
1139 	s32 ret_val;
1140 
1141 	DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1142 
1143 	/* If we have a signal (the cable is plugged in, or assumed true for
1144 	 * serdes media) then poll for a "Link-Up" indication in the Device
1145 	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
1146 	 * seconds (Auto-negotiation should complete in less than 500
1147 	 * milliseconds even if the other end is doing it in SW).
1148 	 */
1149 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1150 		msec_delay(10);
1151 		status = E1000_READ_REG(hw, E1000_STATUS);
1152 		if (status & E1000_STATUS_LU)
1153 			break;
1154 	}
1155 	if (i == FIBER_LINK_UP_LIMIT) {
1156 		DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1157 		mac->autoneg_failed = true;
1158 		/* AutoNeg failed to achieve a link, so we'll call
1159 		 * mac->check_for_link. This routine will force the
1160 		 * link up if we detect a signal. This will allow us to
1161 		 * communicate with non-autonegotiating link partners.
1162 		 */
1163 		ret_val = mac->ops.check_for_link(hw);
1164 		if (ret_val) {
1165 			DEBUGOUT("Error while checking for link\n");
1166 			return ret_val;
1167 		}
1168 		mac->autoneg_failed = false;
1169 	} else {
1170 		mac->autoneg_failed = false;
1171 		DEBUGOUT("Valid Link Found\n");
1172 	}
1173 
1174 	return E1000_SUCCESS;
1175 }
1176 
1177 /**
1178  *  e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1179  *  @hw: pointer to the HW structure
1180  *
1181  *  Configures collision distance and flow control for fiber and serdes
1182  *  links.  Upon successful setup, poll for link.
1183  **/
1184 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1185 {
1186 	u32 ctrl;
1187 	s32 ret_val;
1188 
1189 	DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1190 
1191 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1192 
1193 	/* Take the link out of reset */
1194 	ctrl &= ~E1000_CTRL_LRST;
1195 
1196 	hw->mac.ops.config_collision_dist(hw);
1197 
1198 	ret_val = e1000_commit_fc_settings_generic(hw);
1199 	if (ret_val)
1200 		return ret_val;
1201 
1202 	/* Since auto-negotiation is enabled, take the link out of reset (the
1203 	 * link will be in reset, because we previously reset the chip). This
1204 	 * will restart auto-negotiation.  If auto-negotiation is successful
1205 	 * then the link-up status bit will be set and the flow control enable
1206 	 * bits (RFCE and TFCE) will be set according to their negotiated value.
1207 	 */
1208 	DEBUGOUT("Auto-negotiation enabled\n");
1209 
1210 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1211 	E1000_WRITE_FLUSH(hw);
1212 	msec_delay(1);
1213 
1214 	/* For these adapters, the SW definable pin 1 is set when the optics
1215 	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
1216 	 * indication.
1217 	 */
1218 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1219 	    (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1220 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1221 	} else {
1222 		DEBUGOUT("No signal detected\n");
1223 	}
1224 
1225 	return ret_val;
1226 }
1227 
1228 /**
1229  *  e1000_config_collision_dist_generic - Configure collision distance
1230  *  @hw: pointer to the HW structure
1231  *
1232  *  Configures the collision distance to the default value and is used
1233  *  during link setup.
1234  **/
1235 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1236 {
1237 	u32 tctl;
1238 
1239 	DEBUGFUNC("e1000_config_collision_dist_generic");
1240 
1241 	tctl = E1000_READ_REG(hw, E1000_TCTL);
1242 
1243 	tctl &= ~E1000_TCTL_COLD;
1244 	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1245 
1246 	E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1247 	E1000_WRITE_FLUSH(hw);
1248 }
1249 
1250 /**
1251  *  e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1252  *  @hw: pointer to the HW structure
1253  *
1254  *  Sets the flow control high/low threshold (watermark) registers.  If
1255  *  flow control XON frame transmission is enabled, then set XON frame
1256  *  transmission as well.
1257  **/
1258 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1259 {
1260 	u32 fcrtl = 0, fcrth = 0;
1261 
1262 	DEBUGFUNC("e1000_set_fc_watermarks_generic");
1263 
1264 	/* Set the flow control receive threshold registers.  Normally,
1265 	 * these registers will be set to a default threshold that may be
1266 	 * adjusted later by the driver's runtime code.  However, if the
1267 	 * ability to transmit pause frames is not enabled, then these
1268 	 * registers will be set to 0.
1269 	 */
1270 	if (hw->fc.current_mode & e1000_fc_tx_pause) {
1271 		/* We need to set up the Receive Threshold high and low water
1272 		 * marks as well as (optionally) enabling the transmission of
1273 		 * XON frames.
1274 		 */
1275 		fcrtl = hw->fc.low_water;
1276 		if (hw->fc.send_xon)
1277 			fcrtl |= E1000_FCRTL_XONE;
1278 
1279 		fcrth = hw->fc.high_water;
1280 	}
1281 	E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1282 	E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1283 
1284 	return E1000_SUCCESS;
1285 }
1286 
1287 /**
1288  *  e1000_force_mac_fc_generic - Force the MAC's flow control settings
1289  *  @hw: pointer to the HW structure
1290  *
1291  *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
1292  *  device control register to reflect the adapter settings.  TFCE and RFCE
1293  *  need to be explicitly set by software when a copper PHY is used because
1294  *  autonegotiation is managed by the PHY rather than the MAC.  Software must
1295  *  also configure these bits when link is forced on a fiber connection.
1296  **/
1297 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1298 {
1299 	u32 ctrl;
1300 
1301 	DEBUGFUNC("e1000_force_mac_fc_generic");
1302 
1303 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
1304 
1305 	/* Because we didn't get link via the internal auto-negotiation
1306 	 * mechanism (we either forced link or we got link via PHY
1307 	 * auto-neg), we have to manually enable/disable transmit an
1308 	 * receive flow control.
1309 	 *
1310 	 * The "Case" statement below enables/disable flow control
1311 	 * according to the "hw->fc.current_mode" parameter.
1312 	 *
1313 	 * The possible values of the "fc" parameter are:
1314 	 *      0:  Flow control is completely disabled
1315 	 *      1:  Rx flow control is enabled (we can receive pause
1316 	 *          frames but not send pause frames).
1317 	 *      2:  Tx flow control is enabled (we can send pause frames
1318 	 *          frames but we do not receive pause frames).
1319 	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
1320 	 *  other:  No other values should be possible at this point.
1321 	 */
1322 	DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1323 
1324 	switch (hw->fc.current_mode) {
1325 	case e1000_fc_none:
1326 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1327 		break;
1328 	case e1000_fc_rx_pause:
1329 		ctrl &= (~E1000_CTRL_TFCE);
1330 		ctrl |= E1000_CTRL_RFCE;
1331 		break;
1332 	case e1000_fc_tx_pause:
1333 		ctrl &= (~E1000_CTRL_RFCE);
1334 		ctrl |= E1000_CTRL_TFCE;
1335 		break;
1336 	case e1000_fc_full:
1337 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1338 		break;
1339 	default:
1340 		DEBUGOUT("Flow control param set incorrectly\n");
1341 		return -E1000_ERR_CONFIG;
1342 	}
1343 
1344 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1345 
1346 	return E1000_SUCCESS;
1347 }
1348 
1349 /**
1350  *  e1000_config_fc_after_link_up_generic - Configures flow control after link
1351  *  @hw: pointer to the HW structure
1352  *
1353  *  Checks the status of auto-negotiation after link up to ensure that the
1354  *  speed and duplex were not forced.  If the link needed to be forced, then
1355  *  flow control needs to be forced also.  If auto-negotiation is enabled
1356  *  and did not fail, then we configure flow control based on our link
1357  *  partner.
1358  **/
1359 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1360 {
1361 	struct e1000_mac_info *mac = &hw->mac;
1362 	s32 ret_val = E1000_SUCCESS;
1363 	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1364 	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1365 	u16 speed, duplex;
1366 
1367 	DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1368 
1369 	/* Check for the case where we have fiber media and auto-neg failed
1370 	 * so we had to force link.  In this case, we need to force the
1371 	 * configuration of the MAC to match the "fc" parameter.
1372 	 */
1373 	if (mac->autoneg_failed) {
1374 		if (hw->phy.media_type == e1000_media_type_fiber ||
1375 		    hw->phy.media_type == e1000_media_type_internal_serdes)
1376 			ret_val = e1000_force_mac_fc_generic(hw);
1377 	} else {
1378 		if (hw->phy.media_type == e1000_media_type_copper)
1379 			ret_val = e1000_force_mac_fc_generic(hw);
1380 	}
1381 
1382 	if (ret_val) {
1383 		DEBUGOUT("Error forcing flow control settings\n");
1384 		return ret_val;
1385 	}
1386 
1387 	/* Check for the case where we have copper media and auto-neg is
1388 	 * enabled.  In this case, we need to check and see if Auto-Neg
1389 	 * has completed, and if so, how the PHY and link partner has
1390 	 * flow control configured.
1391 	 */
1392 	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1393 		/* Read the MII Status Register and check to see if AutoNeg
1394 		 * has completed.  We read this twice because this reg has
1395 		 * some "sticky" (latched) bits.
1396 		 */
1397 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1398 		if (ret_val)
1399 			return ret_val;
1400 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1401 		if (ret_val)
1402 			return ret_val;
1403 
1404 		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1405 			DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1406 			return ret_val;
1407 		}
1408 
1409 		/* The AutoNeg process has completed, so we now need to
1410 		 * read both the Auto Negotiation Advertisement
1411 		 * Register (Address 4) and the Auto_Negotiation Base
1412 		 * Page Ability Register (Address 5) to determine how
1413 		 * flow control was negotiated.
1414 		 */
1415 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1416 					       &mii_nway_adv_reg);
1417 		if (ret_val)
1418 			return ret_val;
1419 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1420 					       &mii_nway_lp_ability_reg);
1421 		if (ret_val)
1422 			return ret_val;
1423 
1424 		/* Two bits in the Auto Negotiation Advertisement Register
1425 		 * (Address 4) and two bits in the Auto Negotiation Base
1426 		 * Page Ability Register (Address 5) determine flow control
1427 		 * for both the PHY and the link partner.  The following
1428 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1429 		 * 1999, describes these PAUSE resolution bits and how flow
1430 		 * control is determined based upon these settings.
1431 		 * NOTE:  DC = Don't Care
1432 		 *
1433 		 *   LOCAL DEVICE  |   LINK PARTNER
1434 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1435 		 *-------|---------|-------|---------|--------------------
1436 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1437 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1438 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1439 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1440 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1441 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1442 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1443 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1444 		 *
1445 		 * Are both PAUSE bits set to 1?  If so, this implies
1446 		 * Symmetric Flow Control is enabled at both ends.  The
1447 		 * ASM_DIR bits are irrelevant per the spec.
1448 		 *
1449 		 * For Symmetric Flow Control:
1450 		 *
1451 		 *   LOCAL DEVICE  |   LINK PARTNER
1452 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1453 		 *-------|---------|-------|---------|--------------------
1454 		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
1455 		 *
1456 		 */
1457 		if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1458 		    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1459 			/* Now we need to check if the user selected Rx ONLY
1460 			 * of pause frames.  In this case, we had to advertise
1461 			 * FULL flow control because we could not advertise Rx
1462 			 * ONLY. Hence, we must now check to see if we need to
1463 			 * turn OFF the TRANSMISSION of PAUSE frames.
1464 			 */
1465 			if (hw->fc.requested_mode == e1000_fc_full) {
1466 				hw->fc.current_mode = e1000_fc_full;
1467 				DEBUGOUT("Flow Control = FULL.\n");
1468 			} else {
1469 				hw->fc.current_mode = e1000_fc_rx_pause;
1470 				DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1471 			}
1472 		}
1473 		/* For receiving PAUSE frames ONLY.
1474 		 *
1475 		 *   LOCAL DEVICE  |   LINK PARTNER
1476 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1477 		 *-------|---------|-------|---------|--------------------
1478 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1479 		 */
1480 		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1481 			  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1482 			  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1483 			  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1484 			hw->fc.current_mode = e1000_fc_tx_pause;
1485 			DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1486 		}
1487 		/* For transmitting PAUSE frames ONLY.
1488 		 *
1489 		 *   LOCAL DEVICE  |   LINK PARTNER
1490 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1491 		 *-------|---------|-------|---------|--------------------
1492 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1493 		 */
1494 		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1495 			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1496 			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1497 			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1498 			hw->fc.current_mode = e1000_fc_rx_pause;
1499 			DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1500 		} else {
1501 			/* Per the IEEE spec, at this point flow control
1502 			 * should be disabled.
1503 			 */
1504 			hw->fc.current_mode = e1000_fc_none;
1505 			DEBUGOUT("Flow Control = NONE.\n");
1506 		}
1507 
1508 		/* Now we need to do one last check...  If we auto-
1509 		 * negotiated to HALF DUPLEX, flow control should not be
1510 		 * enabled per IEEE 802.3 spec.
1511 		 */
1512 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1513 		if (ret_val) {
1514 			DEBUGOUT("Error getting link speed and duplex\n");
1515 			return ret_val;
1516 		}
1517 
1518 		if (duplex == HALF_DUPLEX)
1519 			hw->fc.current_mode = e1000_fc_none;
1520 
1521 		/* Now we call a subroutine to actually force the MAC
1522 		 * controller to use the correct flow control settings.
1523 		 */
1524 		ret_val = e1000_force_mac_fc_generic(hw);
1525 		if (ret_val) {
1526 			DEBUGOUT("Error forcing flow control settings\n");
1527 			return ret_val;
1528 		}
1529 	}
1530 
1531 	/* Check for the case where we have SerDes media and auto-neg is
1532 	 * enabled.  In this case, we need to check and see if Auto-Neg
1533 	 * has completed, and if so, how the PHY and link partner has
1534 	 * flow control configured.
1535 	 */
1536 	if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1537 	    mac->autoneg) {
1538 		/* Read the PCS_LSTS and check to see if AutoNeg
1539 		 * has completed.
1540 		 */
1541 		pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1542 
1543 		if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1544 			DEBUGOUT("PCS Auto Neg has not completed.\n");
1545 			return ret_val;
1546 		}
1547 
1548 		/* The AutoNeg process has completed, so we now need to
1549 		 * read both the Auto Negotiation Advertisement
1550 		 * Register (PCS_ANADV) and the Auto_Negotiation Base
1551 		 * Page Ability Register (PCS_LPAB) to determine how
1552 		 * flow control was negotiated.
1553 		 */
1554 		pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1555 		pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1556 
1557 		/* Two bits in the Auto Negotiation Advertisement Register
1558 		 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1559 		 * Page Ability Register (PCS_LPAB) determine flow control
1560 		 * for both the PHY and the link partner.  The following
1561 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1562 		 * 1999, describes these PAUSE resolution bits and how flow
1563 		 * control is determined based upon these settings.
1564 		 * NOTE:  DC = Don't Care
1565 		 *
1566 		 *   LOCAL DEVICE  |   LINK PARTNER
1567 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1568 		 *-------|---------|-------|---------|--------------------
1569 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1570 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1571 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1572 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1573 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1574 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1575 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1576 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1577 		 *
1578 		 * Are both PAUSE bits set to 1?  If so, this implies
1579 		 * Symmetric Flow Control is enabled at both ends.  The
1580 		 * ASM_DIR bits are irrelevant per the spec.
1581 		 *
1582 		 * For Symmetric Flow Control:
1583 		 *
1584 		 *   LOCAL DEVICE  |   LINK PARTNER
1585 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1586 		 *-------|---------|-------|---------|--------------------
1587 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1588 		 *
1589 		 */
1590 		if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1591 		    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1592 			/* Now we need to check if the user selected Rx ONLY
1593 			 * of pause frames.  In this case, we had to advertise
1594 			 * FULL flow control because we could not advertise Rx
1595 			 * ONLY. Hence, we must now check to see if we need to
1596 			 * turn OFF the TRANSMISSION of PAUSE frames.
1597 			 */
1598 			if (hw->fc.requested_mode == e1000_fc_full) {
1599 				hw->fc.current_mode = e1000_fc_full;
1600 				DEBUGOUT("Flow Control = FULL.\n");
1601 			} else {
1602 				hw->fc.current_mode = e1000_fc_rx_pause;
1603 				DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1604 			}
1605 		}
1606 		/* For receiving PAUSE frames ONLY.
1607 		 *
1608 		 *   LOCAL DEVICE  |   LINK PARTNER
1609 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1610 		 *-------|---------|-------|---------|--------------------
1611 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1612 		 */
1613 		else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1614 			  (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1615 			  (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1616 			  (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1617 			hw->fc.current_mode = e1000_fc_tx_pause;
1618 			DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1619 		}
1620 		/* For transmitting PAUSE frames ONLY.
1621 		 *
1622 		 *   LOCAL DEVICE  |   LINK PARTNER
1623 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1624 		 *-------|---------|-------|---------|--------------------
1625 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1626 		 */
1627 		else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1628 			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1629 			 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1630 			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1631 			hw->fc.current_mode = e1000_fc_rx_pause;
1632 			DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1633 		} else {
1634 			/* Per the IEEE spec, at this point flow control
1635 			 * should be disabled.
1636 			 */
1637 			hw->fc.current_mode = e1000_fc_none;
1638 			DEBUGOUT("Flow Control = NONE.\n");
1639 		}
1640 
1641 		/* Now we call a subroutine to actually force the MAC
1642 		 * controller to use the correct flow control settings.
1643 		 */
1644 		pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1645 		pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1646 		E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1647 
1648 		ret_val = e1000_force_mac_fc_generic(hw);
1649 		if (ret_val) {
1650 			DEBUGOUT("Error forcing flow control settings\n");
1651 			return ret_val;
1652 		}
1653 	}
1654 
1655 	return E1000_SUCCESS;
1656 }
1657 
1658 /**
1659  *  e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1660  *  @hw: pointer to the HW structure
1661  *  @speed: stores the current speed
1662  *  @duplex: stores the current duplex
1663  *
1664  *  Read the status register for the current speed/duplex and store the current
1665  *  speed and duplex for copper connections.
1666  **/
1667 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1668 					      u16 *duplex)
1669 {
1670 	u32 status;
1671 
1672 	DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1673 
1674 	status = E1000_READ_REG(hw, E1000_STATUS);
1675 	if (status & E1000_STATUS_SPEED_1000) {
1676 		*speed = SPEED_1000;
1677 		DEBUGOUT("1000 Mbs, ");
1678 	} else if (status & E1000_STATUS_SPEED_100) {
1679 		*speed = SPEED_100;
1680 		DEBUGOUT("100 Mbs, ");
1681 	} else {
1682 		*speed = SPEED_10;
1683 		DEBUGOUT("10 Mbs, ");
1684 	}
1685 
1686 	if (status & E1000_STATUS_FD) {
1687 		*duplex = FULL_DUPLEX;
1688 		DEBUGOUT("Full Duplex\n");
1689 	} else {
1690 		*duplex = HALF_DUPLEX;
1691 		DEBUGOUT("Half Duplex\n");
1692 	}
1693 
1694 	return E1000_SUCCESS;
1695 }
1696 
1697 /**
1698  *  e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1699  *  @hw: pointer to the HW structure
1700  *  @speed: stores the current speed
1701  *  @duplex: stores the current duplex
1702  *
1703  *  Sets the speed and duplex to gigabit full duplex (the only possible option)
1704  *  for fiber/serdes links.
1705  **/
1706 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1707 						    u16 *speed, u16 *duplex)
1708 {
1709 	DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1710 
1711 	*speed = SPEED_1000;
1712 	*duplex = FULL_DUPLEX;
1713 
1714 	return E1000_SUCCESS;
1715 }
1716 
1717 /**
1718  *  e1000_get_auto_rd_done_generic - Check for auto read completion
1719  *  @hw: pointer to the HW structure
1720  *
1721  *  Check EEPROM for Auto Read done bit.
1722  **/
1723 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1724 {
1725 	s32 i = 0;
1726 
1727 	DEBUGFUNC("e1000_get_auto_rd_done_generic");
1728 
1729 	while (i < AUTO_READ_DONE_TIMEOUT) {
1730 		if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1731 			break;
1732 		msec_delay(1);
1733 		i++;
1734 	}
1735 
1736 	if (i == AUTO_READ_DONE_TIMEOUT) {
1737 		DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1738 		return -E1000_ERR_RESET;
1739 	}
1740 
1741 	return E1000_SUCCESS;
1742 }
1743 
1744 /**
1745  *  e1000_valid_led_default_generic - Verify a valid default LED config
1746  *  @hw: pointer to the HW structure
1747  *  @data: pointer to the NVM (EEPROM)
1748  *
1749  *  Read the EEPROM for the current default LED configuration.  If the
1750  *  LED configuration is not valid, set to a valid LED configuration.
1751  **/
1752 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1753 {
1754 	s32 ret_val;
1755 
1756 	DEBUGFUNC("e1000_valid_led_default_generic");
1757 
1758 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1759 	if (ret_val) {
1760 		DEBUGOUT("NVM Read Error\n");
1761 		return ret_val;
1762 	}
1763 
1764 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1765 		*data = ID_LED_DEFAULT;
1766 
1767 	return E1000_SUCCESS;
1768 }
1769 
1770 /**
1771  *  e1000_id_led_init_generic -
1772  *  @hw: pointer to the HW structure
1773  *
1774  **/
1775 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1776 {
1777 	struct e1000_mac_info *mac = &hw->mac;
1778 	s32 ret_val;
1779 	const u32 ledctl_mask = 0x000000FF;
1780 	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1781 	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1782 	u16 data, i, temp;
1783 	const u16 led_mask = 0x0F;
1784 
1785 	DEBUGFUNC("e1000_id_led_init_generic");
1786 
1787 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1788 	if (ret_val)
1789 		return ret_val;
1790 
1791 	mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1792 	mac->ledctl_mode1 = mac->ledctl_default;
1793 	mac->ledctl_mode2 = mac->ledctl_default;
1794 
1795 	for (i = 0; i < 4; i++) {
1796 		temp = (data >> (i << 2)) & led_mask;
1797 		switch (temp) {
1798 		case ID_LED_ON1_DEF2:
1799 		case ID_LED_ON1_ON2:
1800 		case ID_LED_ON1_OFF2:
1801 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1802 			mac->ledctl_mode1 |= ledctl_on << (i << 3);
1803 			break;
1804 		case ID_LED_OFF1_DEF2:
1805 		case ID_LED_OFF1_ON2:
1806 		case ID_LED_OFF1_OFF2:
1807 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1808 			mac->ledctl_mode1 |= ledctl_off << (i << 3);
1809 			break;
1810 		default:
1811 			/* Do nothing */
1812 			break;
1813 		}
1814 		switch (temp) {
1815 		case ID_LED_DEF1_ON2:
1816 		case ID_LED_ON1_ON2:
1817 		case ID_LED_OFF1_ON2:
1818 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1819 			mac->ledctl_mode2 |= ledctl_on << (i << 3);
1820 			break;
1821 		case ID_LED_DEF1_OFF2:
1822 		case ID_LED_ON1_OFF2:
1823 		case ID_LED_OFF1_OFF2:
1824 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1825 			mac->ledctl_mode2 |= ledctl_off << (i << 3);
1826 			break;
1827 		default:
1828 			/* Do nothing */
1829 			break;
1830 		}
1831 	}
1832 
1833 	return E1000_SUCCESS;
1834 }
1835 
1836 /**
1837  *  e1000_setup_led_generic - Configures SW controllable LED
1838  *  @hw: pointer to the HW structure
1839  *
1840  *  This prepares the SW controllable LED for use and saves the current state
1841  *  of the LED so it can be later restored.
1842  **/
1843 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1844 {
1845 	u32 ledctl;
1846 
1847 	DEBUGFUNC("e1000_setup_led_generic");
1848 
1849 	if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1850 		return -E1000_ERR_CONFIG;
1851 
1852 	if (hw->phy.media_type == e1000_media_type_fiber) {
1853 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1854 		hw->mac.ledctl_default = ledctl;
1855 		/* Turn off LED0 */
1856 		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1857 			    E1000_LEDCTL_LED0_MODE_MASK);
1858 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1859 			   E1000_LEDCTL_LED0_MODE_SHIFT);
1860 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1861 	} else if (hw->phy.media_type == e1000_media_type_copper) {
1862 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1863 	}
1864 
1865 	return E1000_SUCCESS;
1866 }
1867 
1868 /**
1869  *  e1000_cleanup_led_generic - Set LED config to default operation
1870  *  @hw: pointer to the HW structure
1871  *
1872  *  Remove the current LED configuration and set the LED configuration
1873  *  to the default value, saved from the EEPROM.
1874  **/
1875 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1876 {
1877 	DEBUGFUNC("e1000_cleanup_led_generic");
1878 
1879 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1880 	return E1000_SUCCESS;
1881 }
1882 
1883 /**
1884  *  e1000_blink_led_generic - Blink LED
1885  *  @hw: pointer to the HW structure
1886  *
1887  *  Blink the LEDs which are set to be on.
1888  **/
1889 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1890 {
1891 	u32 ledctl_blink = 0;
1892 	u32 i;
1893 
1894 	DEBUGFUNC("e1000_blink_led_generic");
1895 
1896 	if (hw->phy.media_type == e1000_media_type_fiber) {
1897 		/* always blink LED0 for PCI-E fiber */
1898 		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1899 		     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1900 	} else {
1901 		/* Set the blink bit for each LED that's "on" (0x0E)
1902 		 * (or "off" if inverted) in ledctl_mode2.  The blink
1903 		 * logic in hardware only works when mode is set to "on"
1904 		 * so it must be changed accordingly when the mode is
1905 		 * "off" and inverted.
1906 		 */
1907 		ledctl_blink = hw->mac.ledctl_mode2;
1908 		for (i = 0; i < 32; i += 8) {
1909 			u32 mode = (hw->mac.ledctl_mode2 >> i) &
1910 			    E1000_LEDCTL_LED0_MODE_MASK;
1911 			u32 led_default = hw->mac.ledctl_default >> i;
1912 
1913 			if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1914 			     (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1915 			    ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1916 			     (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1917 				ledctl_blink &=
1918 				    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1919 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1920 						 E1000_LEDCTL_MODE_LED_ON) << i;
1921 			}
1922 		}
1923 	}
1924 
1925 	E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1926 
1927 	return E1000_SUCCESS;
1928 }
1929 
1930 /**
1931  *  e1000_led_on_generic - Turn LED on
1932  *  @hw: pointer to the HW structure
1933  *
1934  *  Turn LED on.
1935  **/
1936 s32 e1000_led_on_generic(struct e1000_hw *hw)
1937 {
1938 	u32 ctrl;
1939 
1940 	DEBUGFUNC("e1000_led_on_generic");
1941 
1942 	switch (hw->phy.media_type) {
1943 	case e1000_media_type_fiber:
1944 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
1945 		ctrl &= ~E1000_CTRL_SWDPIN0;
1946 		ctrl |= E1000_CTRL_SWDPIO0;
1947 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1948 		break;
1949 	case e1000_media_type_copper:
1950 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1951 		break;
1952 	default:
1953 		break;
1954 	}
1955 
1956 	return E1000_SUCCESS;
1957 }
1958 
1959 /**
1960  *  e1000_led_off_generic - Turn LED off
1961  *  @hw: pointer to the HW structure
1962  *
1963  *  Turn LED off.
1964  **/
1965 s32 e1000_led_off_generic(struct e1000_hw *hw)
1966 {
1967 	u32 ctrl;
1968 
1969 	DEBUGFUNC("e1000_led_off_generic");
1970 
1971 	switch (hw->phy.media_type) {
1972 	case e1000_media_type_fiber:
1973 		ctrl = E1000_READ_REG(hw, E1000_CTRL);
1974 		ctrl |= E1000_CTRL_SWDPIN0;
1975 		ctrl |= E1000_CTRL_SWDPIO0;
1976 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1977 		break;
1978 	case e1000_media_type_copper:
1979 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1980 		break;
1981 	default:
1982 		break;
1983 	}
1984 
1985 	return E1000_SUCCESS;
1986 }
1987 
1988 /**
1989  *  e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1990  *  @hw: pointer to the HW structure
1991  *  @no_snoop: bitmap of snoop events
1992  *
1993  *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1994  **/
1995 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1996 {
1997 	u32 gcr;
1998 
1999 	DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2000 
2001 	if (hw->bus.type != e1000_bus_type_pci_express)
2002 		return;
2003 
2004 	if (no_snoop) {
2005 		gcr = E1000_READ_REG(hw, E1000_GCR);
2006 		gcr &= ~(PCIE_NO_SNOOP_ALL);
2007 		gcr |= no_snoop;
2008 		E1000_WRITE_REG(hw, E1000_GCR, gcr);
2009 	}
2010 }
2011 
2012 /**
2013  *  e1000_disable_pcie_master_generic - Disables PCI-express master access
2014  *  @hw: pointer to the HW structure
2015  *
2016  *  Returns E1000_SUCCESS if successful, else returns -10
2017  *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2018  *  the master requests to be disabled.
2019  *
2020  *  Disables PCI-Express master access and verifies there are no pending
2021  *  requests.
2022  **/
2023 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2024 {
2025 	u32 ctrl;
2026 	s32 timeout = MASTER_DISABLE_TIMEOUT;
2027 
2028 	DEBUGFUNC("e1000_disable_pcie_master_generic");
2029 
2030 	if (hw->bus.type != e1000_bus_type_pci_express)
2031 		return E1000_SUCCESS;
2032 
2033 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
2034 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2035 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2036 
2037 	while (timeout) {
2038 		if (!(E1000_READ_REG(hw, E1000_STATUS) &
2039 		      E1000_STATUS_GIO_MASTER_ENABLE) ||
2040 				E1000_REMOVED(hw->hw_addr))
2041 			break;
2042 		usec_delay(100);
2043 		timeout--;
2044 	}
2045 
2046 	if (!timeout) {
2047 		DEBUGOUT("Master requests are pending.\n");
2048 		return -E1000_ERR_MASTER_REQUESTS_PENDING;
2049 	}
2050 
2051 	return E1000_SUCCESS;
2052 }
2053 
2054 /**
2055  *  e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2056  *  @hw: pointer to the HW structure
2057  *
2058  *  Reset the Adaptive Interframe Spacing throttle to default values.
2059  **/
2060 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2061 {
2062 	struct e1000_mac_info *mac = &hw->mac;
2063 
2064 	DEBUGFUNC("e1000_reset_adaptive_generic");
2065 
2066 	if (!mac->adaptive_ifs) {
2067 		DEBUGOUT("Not in Adaptive IFS mode!\n");
2068 		return;
2069 	}
2070 
2071 	mac->current_ifs_val = 0;
2072 	mac->ifs_min_val = IFS_MIN;
2073 	mac->ifs_max_val = IFS_MAX;
2074 	mac->ifs_step_size = IFS_STEP;
2075 	mac->ifs_ratio = IFS_RATIO;
2076 
2077 	mac->in_ifs_mode = false;
2078 	E1000_WRITE_REG(hw, E1000_AIT, 0);
2079 }
2080 
2081 /**
2082  *  e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2083  *  @hw: pointer to the HW structure
2084  *
2085  *  Update the Adaptive Interframe Spacing Throttle value based on the
2086  *  time between transmitted packets and time between collisions.
2087  **/
2088 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2089 {
2090 	struct e1000_mac_info *mac = &hw->mac;
2091 
2092 	DEBUGFUNC("e1000_update_adaptive_generic");
2093 
2094 	if (!mac->adaptive_ifs) {
2095 		DEBUGOUT("Not in Adaptive IFS mode!\n");
2096 		return;
2097 	}
2098 
2099 	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2100 		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2101 			mac->in_ifs_mode = true;
2102 			if (mac->current_ifs_val < mac->ifs_max_val) {
2103 				if (!mac->current_ifs_val)
2104 					mac->current_ifs_val = mac->ifs_min_val;
2105 				else
2106 					mac->current_ifs_val +=
2107 						mac->ifs_step_size;
2108 				E1000_WRITE_REG(hw, E1000_AIT,
2109 						mac->current_ifs_val);
2110 			}
2111 		}
2112 	} else {
2113 		if (mac->in_ifs_mode &&
2114 		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2115 			mac->current_ifs_val = 0;
2116 			mac->in_ifs_mode = false;
2117 			E1000_WRITE_REG(hw, E1000_AIT, 0);
2118 		}
2119 	}
2120 }
2121 
2122 /**
2123  *  e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2124  *  @hw: pointer to the HW structure
2125  *
2126  *  Verify that when not using auto-negotiation that MDI/MDIx is correctly
2127  *  set, which is forced to MDI mode only.
2128  **/
2129 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2130 {
2131 	DEBUGFUNC("e1000_validate_mdi_setting_generic");
2132 
2133 	if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2134 		DEBUGOUT("Invalid MDI setting detected\n");
2135 		hw->phy.mdix = 1;
2136 		return -E1000_ERR_CONFIG;
2137 	}
2138 
2139 	return E1000_SUCCESS;
2140 }
2141 
2142 /**
2143  *  e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2144  *  @hw: pointer to the HW structure
2145  *
2146  *  Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2147  *  operation.
2148  **/
2149 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2150 {
2151 	DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2152 
2153 	return E1000_SUCCESS;
2154 }
2155 
2156 /**
2157  *  e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2158  *  @hw: pointer to the HW structure
2159  *  @reg: 32bit register offset such as E1000_SCTL
2160  *  @offset: register offset to write to
2161  *  @data: data to write at register offset
2162  *
2163  *  Writes an address/data control type register.  There are several of these
2164  *  and they all have the format address << 8 | data and bit 31 is polled for
2165  *  completion.
2166  **/
2167 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2168 				      u32 offset, u8 data)
2169 {
2170 	u32 i, regvalue = 0;
2171 
2172 	DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2173 
2174 	/* Set up the address and data */
2175 	regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2176 	E1000_WRITE_REG(hw, reg, regvalue);
2177 
2178 	/* Poll the ready bit to see if the MDI read completed */
2179 	for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2180 		usec_delay(5);
2181 		regvalue = E1000_READ_REG(hw, reg);
2182 		if (regvalue & E1000_GEN_CTL_READY)
2183 			break;
2184 	}
2185 	if (!(regvalue & E1000_GEN_CTL_READY)) {
2186 		DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2187 		return -E1000_ERR_PHY;
2188 	}
2189 
2190 	return E1000_SUCCESS;
2191 }
2192 
2193 /**
2194  *  e1000_get_hw_semaphore - Acquire hardware semaphore
2195  *  @hw: pointer to the HW structure
2196  *
2197  *  Acquire the HW semaphore to access the PHY or NVM
2198  **/
2199 s32 e1000_get_hw_semaphore(struct e1000_hw *hw)
2200 {
2201 	u32 swsm;
2202 	s32 fw_timeout = hw->nvm.word_size + 1;
2203 	s32 sw_timeout = hw->nvm.word_size + 1;
2204 	s32 i = 0;
2205 
2206 	DEBUGFUNC("e1000_get_hw_semaphore");
2207 
2208 	/* _82571 */
2209 	/* If we have timedout 3 times on trying to acquire
2210 	 * the inter-port SMBI semaphore, there is old code
2211 	 * operating on the other port, and it is not
2212 	 * releasing SMBI. Modify the number of times that
2213 	 * we try for the semaphore to interwork with this
2214 	 * older code.
2215 	 */
2216 	if (hw->dev_spec._82571.smb_counter > 2)
2217 		sw_timeout = 1;
2218 
2219 
2220 	/* Get the SW semaphore */
2221 	while (i < sw_timeout) {
2222 		swsm = E1000_READ_REG(hw, E1000_SWSM);
2223 		if (!(swsm & E1000_SWSM_SMBI))
2224 			break;
2225 
2226 		usec_delay(50);
2227 		i++;
2228 	}
2229 
2230 	if (i == sw_timeout) {
2231 		DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
2232 		hw->dev_spec._82571.smb_counter++;
2233 	}
2234 
2235 	/* In rare circumstances, the SW semaphore may already be held
2236 	 * unintentionally. Clear the semaphore once before giving up.
2237 	 */
2238 	if (hw->dev_spec._82575.clear_semaphore_once) {
2239 	 	hw->dev_spec._82575.clear_semaphore_once = false;
2240 		e1000_put_hw_semaphore(hw);
2241 		for (i = 0; i < fw_timeout; i++) {
2242 			swsm = E1000_READ_REG(hw, E1000_SWSM);
2243 	 		if (!(swsm & E1000_SWSM_SMBI))
2244 	 			break;
2245 
2246 	 		usec_delay(50);
2247 	 	}
2248 	 }
2249 
2250 	/* Get the FW semaphore. */
2251 	for (i = 0; i < fw_timeout; i++) {
2252 		swsm = E1000_READ_REG(hw, E1000_SWSM);
2253 		E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
2254 
2255 		/* Semaphore acquired if bit latched */
2256 		if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
2257 			break;
2258 
2259 		usec_delay(50);
2260 	}
2261 
2262 	if (i == fw_timeout) {
2263 		/* Release semaphores */
2264 		e1000_put_hw_semaphore(hw);
2265 		DEBUGOUT("Driver can't access the NVM\n");
2266 		return -E1000_ERR_NVM;
2267 	}
2268 
2269 	return E1000_SUCCESS;
2270 }
2271 
2272 /**
2273  *  e1000_put_hw_semaphore - Release hardware semaphore
2274  *  @hw: pointer to the HW structure
2275  *
2276  *  Release hardware semaphore used to access the PHY or NVM
2277  **/
2278 void e1000_put_hw_semaphore(struct e1000_hw *hw)
2279 {
2280 	u32 swsm;
2281 
2282 	DEBUGFUNC("e1000_put_hw_semaphore");
2283 
2284 	swsm = E1000_READ_REG(hw, E1000_SWSM);
2285 
2286 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
2287 
2288 	E1000_WRITE_REG(hw, E1000_SWSM, swsm);
2289 }
2290 
2291 
2292 /**
2293  *  e1000_acquire_swfw_sync - Acquire SW/FW semaphore
2294  *  @hw: pointer to the HW structure
2295  *  @mask: specifies which semaphore to acquire
2296  *
2297  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
2298  *  will also specify which port we're acquiring the lock for.
2299  **/
2300 s32
2301 e1000_acquire_swfw_sync(struct e1000_hw *hw, u16 mask)
2302 {
2303 	u32 swfw_sync;
2304 	u32 swmask = mask;
2305 	u32 fwmask = mask << 16;
2306 	s32 ret_val = E1000_SUCCESS;
2307 	s32 i = 0, timeout = 200;
2308 
2309 	DEBUGFUNC("e1000_acquire_swfw_sync");
2310 	ASSERT_NO_LOCKS();
2311 	while (i < timeout) {
2312 		if (e1000_get_hw_semaphore(hw)) {
2313 			ret_val = -E1000_ERR_SWFW_SYNC;
2314 			goto out;
2315 		}
2316 
2317 		swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
2318 		if (!(swfw_sync & (fwmask | swmask)))
2319 			break;
2320 
2321 		/*
2322 		 * Firmware currently using resource (fwmask)
2323 		 * or other software thread using resource (swmask)
2324 		 */
2325 		e1000_put_hw_semaphore(hw);
2326 		msec_delay_irq(5);
2327 		i++;
2328 	}
2329 
2330 	if (i == timeout) {
2331 		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2332 		ret_val = -E1000_ERR_SWFW_SYNC;
2333 		goto out;
2334 	}
2335 
2336 	swfw_sync |= swmask;
2337 	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
2338 
2339 	e1000_put_hw_semaphore(hw);
2340 
2341 out:
2342 	return ret_val;
2343 }
2344 
2345 /**
2346  *  e1000_release_swfw_sync - Release SW/FW semaphore
2347  *  @hw: pointer to the HW structure
2348  *  @mask: specifies which semaphore to acquire
2349  *
2350  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
2351  *  will also specify which port we're releasing the lock for.
2352  **/
2353 void
2354 e1000_release_swfw_sync(struct e1000_hw *hw, u16 mask)
2355 {
2356 	u32 swfw_sync;
2357 
2358 	DEBUGFUNC("e1000_release_swfw_sync");
2359 
2360 	while (e1000_get_hw_semaphore(hw) != E1000_SUCCESS)
2361 		; /* Empty */
2362 
2363 	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
2364 	swfw_sync &= (u32)~mask;
2365 	E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
2366 
2367 	e1000_put_hw_semaphore(hw);
2368 }
2369 
2370