1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42 /** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49 { 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 /* VLAN, MC, etc. */ 77 mac->ops.update_mc_addr_list = e1000_null_update_mc; 78 mac->ops.clear_vfta = e1000_null_mac_generic; 79 mac->ops.write_vfta = e1000_null_write_vfta; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82 } 83 84 /** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89 { 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92 } 93 94 /** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99 { 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102 } 103 104 /** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120 { 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123 } 124 125 /** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142 { 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145 } 146 147 /** 148 * e1000_null_rar_set - No-op function, return void 149 * @hw: pointer to the HW structure 150 **/ 151 void e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153 { 154 DEBUGFUNC("e1000_null_rar_set"); 155 return; 156 } 157 158 /** 159 * e1000_null_set_obff_timer - No-op function, return 0 160 * @hw: pointer to the HW structure 161 **/ 162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163 u32 E1000_UNUSEDARG a) 164 { 165 DEBUGFUNC("e1000_null_set_obff_timer"); 166 return E1000_SUCCESS; 167 } 168 169 /** 170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171 * @hw: pointer to the HW structure 172 * 173 * Determines and stores the system bus information for a particular 174 * network interface. The following bus information is determined and stored: 175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176 **/ 177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178 { 179 struct e1000_mac_info *mac = &hw->mac; 180 struct e1000_bus_info *bus = &hw->bus; 181 u32 status = E1000_READ_REG(hw, E1000_STATUS); 182 s32 ret_val = E1000_SUCCESS; 183 184 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185 186 /* PCI or PCI-X? */ 187 bus->type = (status & E1000_STATUS_PCIX_MODE) 188 ? e1000_bus_type_pcix 189 : e1000_bus_type_pci; 190 191 /* Bus speed */ 192 if (bus->type == e1000_bus_type_pci) { 193 bus->speed = (status & E1000_STATUS_PCI66) 194 ? e1000_bus_speed_66 195 : e1000_bus_speed_33; 196 } else { 197 switch (status & E1000_STATUS_PCIX_SPEED) { 198 case E1000_STATUS_PCIX_SPEED_66: 199 bus->speed = e1000_bus_speed_66; 200 break; 201 case E1000_STATUS_PCIX_SPEED_100: 202 bus->speed = e1000_bus_speed_100; 203 break; 204 case E1000_STATUS_PCIX_SPEED_133: 205 bus->speed = e1000_bus_speed_133; 206 break; 207 default: 208 bus->speed = e1000_bus_speed_reserved; 209 break; 210 } 211 } 212 213 /* Bus width */ 214 bus->width = (status & E1000_STATUS_BUS64) 215 ? e1000_bus_width_64 216 : e1000_bus_width_32; 217 218 /* Which PCI(-X) function? */ 219 mac->ops.set_lan_id(hw); 220 221 return ret_val; 222 } 223 224 /** 225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226 * @hw: pointer to the HW structure 227 * 228 * Determines and stores the system bus information for a particular 229 * network interface. The following bus information is determined and stored: 230 * bus speed, bus width, type (PCIe), and PCIe function. 231 **/ 232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233 { 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_bus_info *bus = &hw->bus; 236 s32 ret_val; 237 u16 pcie_link_status; 238 239 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240 241 bus->type = e1000_bus_type_pci_express; 242 243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) { 246 bus->width = e1000_bus_width_unknown; 247 bus->speed = e1000_bus_speed_unknown; 248 } else { 249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250 case PCIE_LINK_SPEED_2500: 251 bus->speed = e1000_bus_speed_2500; 252 break; 253 case PCIE_LINK_SPEED_5000: 254 bus->speed = e1000_bus_speed_5000; 255 break; 256 default: 257 bus->speed = e1000_bus_speed_unknown; 258 break; 259 } 260 261 bus->width = (enum e1000_bus_width)((pcie_link_status & 262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263 } 264 265 mac->ops.set_lan_id(hw); 266 267 return E1000_SUCCESS; 268 } 269 270 /** 271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272 * 273 * @hw: pointer to the HW structure 274 * 275 * Determines the LAN function id by reading memory-mapped registers 276 * and swaps the port value if requested. 277 **/ 278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279 { 280 struct e1000_bus_info *bus = &hw->bus; 281 u32 reg; 282 283 /* The status register reports the correct function number 284 * for the device regardless of function swap state. 285 */ 286 reg = E1000_READ_REG(hw, E1000_STATUS); 287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288 } 289 290 /** 291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292 * @hw: pointer to the HW structure 293 * 294 * Determines the LAN function id by reading PCI config space. 295 **/ 296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297 { 298 struct e1000_bus_info *bus = &hw->bus; 299 u16 pci_header_type; 300 u32 status; 301 302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304 status = E1000_READ_REG(hw, E1000_STATUS); 305 bus->func = (status & E1000_STATUS_FUNC_MASK) 306 >> E1000_STATUS_FUNC_SHIFT; 307 } else { 308 bus->func = 0; 309 } 310 } 311 312 /** 313 * e1000_set_lan_id_single_port - Set LAN id for a single port device 314 * @hw: pointer to the HW structure 315 * 316 * Sets the LAN function id to zero for a single port device. 317 **/ 318 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 319 { 320 struct e1000_bus_info *bus = &hw->bus; 321 322 bus->func = 0; 323 } 324 325 /** 326 * e1000_clear_vfta_generic - Clear VLAN filter table 327 * @hw: pointer to the HW structure 328 * 329 * Clears the register array which contains the VLAN filter table by 330 * setting all the values to 0. 331 **/ 332 void e1000_clear_vfta_generic(struct e1000_hw *hw) 333 { 334 u32 offset; 335 336 DEBUGFUNC("e1000_clear_vfta_generic"); 337 338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342 } 343 344 /** 345 * e1000_write_vfta_generic - Write value to VLAN filter table 346 * @hw: pointer to the HW structure 347 * @offset: register offset in VLAN filter table 348 * @value: register value written to VLAN filter table 349 * 350 * Writes value at the given offset in the register array which stores 351 * the VLAN filter table. 352 **/ 353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354 { 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359 } 360 361 /** 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setup the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 **/ 370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371 { 372 u32 i; 373 u8 mac_addr[ETH_ADDR_LEN] = {0}; 374 375 DEBUGFUNC("e1000_init_rx_addrs_generic"); 376 377 /* Setup the receive address */ 378 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379 380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381 382 /* Zero out the other (rar_entry_count - 1) receive addresses */ 383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384 for (i = 1; i < rar_count; i++) 385 hw->mac.ops.rar_set(hw, mac_addr, i); 386 } 387 388 /** 389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390 * @hw: pointer to the HW structure 391 * 392 * Checks the nvm for an alternate MAC address. An alternate MAC address 393 * can be setup by pre-boot software and must be treated like a permanent 394 * address and must override the actual permanent MAC address. If an 395 * alternate MAC address is found it is programmed into RAR0, replacing 396 * the permanent address that was installed into RAR0 by the Si on reset. 397 * This function will return SUCCESS unless it encounters an error while 398 * reading the EEPROM. 399 **/ 400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401 { 402 u32 i; 403 s32 ret_val; 404 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405 u8 alt_mac_addr[ETH_ADDR_LEN]; 406 407 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408 409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410 if (ret_val) 411 return ret_val; 412 413 /* not supported on older hardware or 82573 */ 414 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 415 return E1000_SUCCESS; 416 417 /* Alternate MAC address is handled by the option ROM for 82580 418 * and newer. SW support not required. 419 */ 420 if (hw->mac.type >= e1000_82580) 421 return E1000_SUCCESS; 422 423 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 424 &nvm_alt_mac_addr_offset); 425 if (ret_val) { 426 DEBUGOUT("NVM Read Error\n"); 427 return ret_val; 428 } 429 430 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 431 (nvm_alt_mac_addr_offset == 0x0000)) 432 /* There is no Alternate MAC Address */ 433 return E1000_SUCCESS; 434 435 if (hw->bus.func == E1000_FUNC_1) 436 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 437 if (hw->bus.func == E1000_FUNC_2) 438 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 439 440 if (hw->bus.func == E1000_FUNC_3) 441 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 442 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 443 offset = nvm_alt_mac_addr_offset + (i >> 1); 444 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 445 if (ret_val) { 446 DEBUGOUT("NVM Read Error\n"); 447 return ret_val; 448 } 449 450 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 451 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 452 } 453 454 /* if multicast bit is set, the alternate address will not be used */ 455 if (alt_mac_addr[0] & 0x01) { 456 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 457 return E1000_SUCCESS; 458 } 459 460 /* We have a valid alternate MAC address, and we want to treat it the 461 * same as the normal permanent MAC address stored by the HW into the 462 * RAR. Do this by mapping this address into RAR0. 463 */ 464 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 465 466 return E1000_SUCCESS; 467 } 468 469 /** 470 * e1000_rar_set_generic - Set receive address register 471 * @hw: pointer to the HW structure 472 * @addr: pointer to the receive address 473 * @index: receive address array register 474 * 475 * Sets the receive address array register at index to the address passed 476 * in by addr. 477 **/ 478 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 479 { 480 u32 rar_low, rar_high; 481 482 DEBUGFUNC("e1000_rar_set_generic"); 483 484 /* HW expects these in little endian so we reverse the byte order 485 * from network order (big endian) to little endian 486 */ 487 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 488 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 489 490 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 491 492 /* If MAC address zero, no need to set the AV bit */ 493 if (rar_low || rar_high) 494 rar_high |= E1000_RAH_AV; 495 496 /* Some bridges will combine consecutive 32-bit writes into 497 * a single burst write, which will malfunction on some parts. 498 * The flushes avoid this. 499 */ 500 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 501 E1000_WRITE_FLUSH(hw); 502 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 503 E1000_WRITE_FLUSH(hw); 504 } 505 506 /** 507 * e1000_hash_mc_addr_generic - Generate a multicast hash value 508 * @hw: pointer to the HW structure 509 * @mc_addr: pointer to a multicast address 510 * 511 * Generates a multicast address hash value which is used to determine 512 * the multicast filter table array address and new table value. 513 **/ 514 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 515 { 516 u32 hash_value, hash_mask; 517 u8 bit_shift = 0; 518 519 DEBUGFUNC("e1000_hash_mc_addr_generic"); 520 521 /* Register count multiplied by bits per register */ 522 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 523 524 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 525 * where 0xFF would still fall within the hash mask. 526 */ 527 while (hash_mask >> bit_shift != 0xFF) 528 bit_shift++; 529 530 /* The portion of the address that is used for the hash table 531 * is determined by the mc_filter_type setting. 532 * The algorithm is such that there is a total of 8 bits of shifting. 533 * The bit_shift for a mc_filter_type of 0 represents the number of 534 * left-shifts where the MSB of mc_addr[5] would still fall within 535 * the hash_mask. Case 0 does this exactly. Since there are a total 536 * of 8 bits of shifting, then mc_addr[4] will shift right the 537 * remaining number of bits. Thus 8 - bit_shift. The rest of the 538 * cases are a variation of this algorithm...essentially raising the 539 * number of bits to shift mc_addr[5] left, while still keeping the 540 * 8-bit shifting total. 541 * 542 * For example, given the following Destination MAC Address and an 543 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 544 * we can see that the bit_shift for case 0 is 4. These are the hash 545 * values resulting from each mc_filter_type... 546 * [0] [1] [2] [3] [4] [5] 547 * 01 AA 00 12 34 56 548 * LSB MSB 549 * 550 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 551 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 552 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 553 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 554 */ 555 switch (hw->mac.mc_filter_type) { 556 default: 557 case 0: 558 break; 559 case 1: 560 bit_shift += 1; 561 break; 562 case 2: 563 bit_shift += 2; 564 break; 565 case 3: 566 bit_shift += 4; 567 break; 568 } 569 570 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 571 (((u16) mc_addr[5]) << bit_shift))); 572 573 return hash_value; 574 } 575 576 /** 577 * e1000_update_mc_addr_list_generic - Update Multicast addresses 578 * @hw: pointer to the HW structure 579 * @mc_addr_list: array of multicast addresses to program 580 * @mc_addr_count: number of multicast addresses to program 581 * 582 * Updates entire Multicast Table Array. 583 * The caller must have a packed mc_addr_list of multicast addresses. 584 **/ 585 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 586 u8 *mc_addr_list, u32 mc_addr_count) 587 { 588 u32 hash_value, hash_bit, hash_reg; 589 int i; 590 591 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 592 593 /* clear mta_shadow */ 594 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 595 596 /* update mta_shadow from mc_addr_list */ 597 for (i = 0; (u32) i < mc_addr_count; i++) { 598 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 599 600 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 601 hash_bit = hash_value & 0x1F; 602 603 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 604 mc_addr_list += (ETH_ADDR_LEN); 605 } 606 607 /* replace the entire MTA table */ 608 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 609 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 610 E1000_WRITE_FLUSH(hw); 611 } 612 613 /** 614 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 615 * @hw: pointer to the HW structure 616 * 617 * In certain situations, a system BIOS may report that the PCIx maximum 618 * memory read byte count (MMRBC) value is higher than than the actual 619 * value. We check the PCIx command register with the current PCIx status 620 * register. 621 **/ 622 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 623 { 624 u16 cmd_mmrbc; 625 u16 pcix_cmd; 626 u16 pcix_stat_hi_word; 627 u16 stat_mmrbc; 628 629 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 630 631 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 632 if (hw->bus.type != e1000_bus_type_pcix) 633 return; 634 635 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 636 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 637 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 638 PCIX_COMMAND_MMRBC_SHIFT; 639 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 640 PCIX_STATUS_HI_MMRBC_SHIFT; 641 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 642 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 643 if (cmd_mmrbc > stat_mmrbc) { 644 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 645 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 646 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 647 } 648 } 649 650 /** 651 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 652 * @hw: pointer to the HW structure 653 * 654 * Clears the base hardware counters by reading the counter registers. 655 **/ 656 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 657 { 658 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 659 660 E1000_READ_REG(hw, E1000_CRCERRS); 661 E1000_READ_REG(hw, E1000_SYMERRS); 662 E1000_READ_REG(hw, E1000_MPC); 663 E1000_READ_REG(hw, E1000_SCC); 664 E1000_READ_REG(hw, E1000_ECOL); 665 E1000_READ_REG(hw, E1000_MCC); 666 E1000_READ_REG(hw, E1000_LATECOL); 667 E1000_READ_REG(hw, E1000_COLC); 668 E1000_READ_REG(hw, E1000_DC); 669 E1000_READ_REG(hw, E1000_SEC); 670 E1000_READ_REG(hw, E1000_RLEC); 671 E1000_READ_REG(hw, E1000_XONRXC); 672 E1000_READ_REG(hw, E1000_XONTXC); 673 E1000_READ_REG(hw, E1000_XOFFRXC); 674 E1000_READ_REG(hw, E1000_XOFFTXC); 675 E1000_READ_REG(hw, E1000_FCRUC); 676 E1000_READ_REG(hw, E1000_GPRC); 677 E1000_READ_REG(hw, E1000_BPRC); 678 E1000_READ_REG(hw, E1000_MPRC); 679 E1000_READ_REG(hw, E1000_GPTC); 680 E1000_READ_REG(hw, E1000_GORCL); 681 E1000_READ_REG(hw, E1000_GORCH); 682 E1000_READ_REG(hw, E1000_GOTCL); 683 E1000_READ_REG(hw, E1000_GOTCH); 684 E1000_READ_REG(hw, E1000_RNBC); 685 E1000_READ_REG(hw, E1000_RUC); 686 E1000_READ_REG(hw, E1000_RFC); 687 E1000_READ_REG(hw, E1000_ROC); 688 E1000_READ_REG(hw, E1000_RJC); 689 E1000_READ_REG(hw, E1000_TORL); 690 E1000_READ_REG(hw, E1000_TORH); 691 E1000_READ_REG(hw, E1000_TOTL); 692 E1000_READ_REG(hw, E1000_TOTH); 693 E1000_READ_REG(hw, E1000_TPR); 694 E1000_READ_REG(hw, E1000_TPT); 695 E1000_READ_REG(hw, E1000_MPTC); 696 E1000_READ_REG(hw, E1000_BPTC); 697 } 698 699 /** 700 * e1000_check_for_copper_link_generic - Check for link (Copper) 701 * @hw: pointer to the HW structure 702 * 703 * Checks to see of the link status of the hardware has changed. If a 704 * change in link status has been detected, then we read the PHY registers 705 * to get the current speed/duplex if link exists. 706 **/ 707 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 708 { 709 struct e1000_mac_info *mac = &hw->mac; 710 s32 ret_val; 711 bool link; 712 713 DEBUGFUNC("e1000_check_for_copper_link"); 714 715 /* We only want to go out to the PHY registers to see if Auto-Neg 716 * has completed and/or if our link status has changed. The 717 * get_link_status flag is set upon receiving a Link Status 718 * Change or Rx Sequence Error interrupt. 719 */ 720 if (!mac->get_link_status) 721 return E1000_SUCCESS; 722 723 /* First we want to see if the MII Status Register reports 724 * link. If so, then we want to get the current speed/duplex 725 * of the PHY. 726 */ 727 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 728 if (ret_val) 729 return ret_val; 730 731 if (!link) 732 return E1000_SUCCESS; /* No link detected */ 733 734 mac->get_link_status = FALSE; 735 736 /* Check if there was DownShift, must be checked 737 * immediately after link-up 738 */ 739 e1000_check_downshift_generic(hw); 740 741 /* If we are forcing speed/duplex, then we simply return since 742 * we have already determined whether we have link or not. 743 */ 744 if (!mac->autoneg) 745 return -E1000_ERR_CONFIG; 746 747 /* Auto-Neg is enabled. Auto Speed Detection takes care 748 * of MAC speed/duplex configuration. So we only need to 749 * configure Collision Distance in the MAC. 750 */ 751 mac->ops.config_collision_dist(hw); 752 753 /* Configure Flow Control now that Auto-Neg has completed. 754 * First, we need to restore the desired flow control 755 * settings because we may have had to re-autoneg with a 756 * different link partner. 757 */ 758 ret_val = e1000_config_fc_after_link_up_generic(hw); 759 if (ret_val) 760 DEBUGOUT("Error configuring flow control\n"); 761 762 return ret_val; 763 } 764 765 /** 766 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 767 * @hw: pointer to the HW structure 768 * 769 * Checks for link up on the hardware. If link is not up and we have 770 * a signal, then we need to force link up. 771 **/ 772 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 773 { 774 struct e1000_mac_info *mac = &hw->mac; 775 u32 rxcw; 776 u32 ctrl; 777 u32 status; 778 s32 ret_val; 779 780 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 781 782 ctrl = E1000_READ_REG(hw, E1000_CTRL); 783 status = E1000_READ_REG(hw, E1000_STATUS); 784 rxcw = E1000_READ_REG(hw, E1000_RXCW); 785 786 /* If we don't have link (auto-negotiation failed or link partner 787 * cannot auto-negotiate), the cable is plugged in (we have signal), 788 * and our link partner is not trying to auto-negotiate with us (we 789 * are receiving idles or data), we need to force link up. We also 790 * need to give auto-negotiation time to complete, in case the cable 791 * was just plugged in. The autoneg_failed flag does this. 792 */ 793 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 794 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 795 !(rxcw & E1000_RXCW_C)) { 796 if (!mac->autoneg_failed) { 797 mac->autoneg_failed = TRUE; 798 return E1000_SUCCESS; 799 } 800 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 801 802 /* Disable auto-negotiation in the TXCW register */ 803 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 804 805 /* Force link-up and also force full-duplex. */ 806 ctrl = E1000_READ_REG(hw, E1000_CTRL); 807 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 808 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 809 810 /* Configure Flow Control after forcing link up. */ 811 ret_val = e1000_config_fc_after_link_up_generic(hw); 812 if (ret_val) { 813 DEBUGOUT("Error configuring flow control\n"); 814 return ret_val; 815 } 816 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 817 /* If we are forcing link and we are receiving /C/ ordered 818 * sets, re-enable auto-negotiation in the TXCW register 819 * and disable forced link in the Device Control register 820 * in an attempt to auto-negotiate with our link partner. 821 */ 822 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 823 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 824 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 825 826 mac->serdes_has_link = TRUE; 827 } 828 829 return E1000_SUCCESS; 830 } 831 832 /** 833 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 834 * @hw: pointer to the HW structure 835 * 836 * Checks for link up on the hardware. If link is not up and we have 837 * a signal, then we need to force link up. 838 **/ 839 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 840 { 841 struct e1000_mac_info *mac = &hw->mac; 842 u32 rxcw; 843 u32 ctrl; 844 u32 status; 845 s32 ret_val; 846 847 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 848 849 ctrl = E1000_READ_REG(hw, E1000_CTRL); 850 status = E1000_READ_REG(hw, E1000_STATUS); 851 rxcw = E1000_READ_REG(hw, E1000_RXCW); 852 853 /* If we don't have link (auto-negotiation failed or link partner 854 * cannot auto-negotiate), and our link partner is not trying to 855 * auto-negotiate with us (we are receiving idles or data), 856 * we need to force link up. We also need to give auto-negotiation 857 * time to complete. 858 */ 859 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 860 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 861 if (!mac->autoneg_failed) { 862 mac->autoneg_failed = TRUE; 863 return E1000_SUCCESS; 864 } 865 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 866 867 /* Disable auto-negotiation in the TXCW register */ 868 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 869 870 /* Force link-up and also force full-duplex. */ 871 ctrl = E1000_READ_REG(hw, E1000_CTRL); 872 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 873 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 874 875 /* Configure Flow Control after forcing link up. */ 876 ret_val = e1000_config_fc_after_link_up_generic(hw); 877 if (ret_val) { 878 DEBUGOUT("Error configuring flow control\n"); 879 return ret_val; 880 } 881 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 882 /* If we are forcing link and we are receiving /C/ ordered 883 * sets, re-enable auto-negotiation in the TXCW register 884 * and disable forced link in the Device Control register 885 * in an attempt to auto-negotiate with our link partner. 886 */ 887 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 888 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 889 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 890 891 mac->serdes_has_link = TRUE; 892 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 893 /* If we force link for non-auto-negotiation switch, check 894 * link status based on MAC synchronization for internal 895 * serdes media type. 896 */ 897 /* SYNCH bit and IV bit are sticky. */ 898 usec_delay(10); 899 rxcw = E1000_READ_REG(hw, E1000_RXCW); 900 if (rxcw & E1000_RXCW_SYNCH) { 901 if (!(rxcw & E1000_RXCW_IV)) { 902 mac->serdes_has_link = TRUE; 903 DEBUGOUT("SERDES: Link up - forced.\n"); 904 } 905 } else { 906 mac->serdes_has_link = FALSE; 907 DEBUGOUT("SERDES: Link down - force failed.\n"); 908 } 909 } 910 911 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 912 status = E1000_READ_REG(hw, E1000_STATUS); 913 if (status & E1000_STATUS_LU) { 914 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 915 usec_delay(10); 916 rxcw = E1000_READ_REG(hw, E1000_RXCW); 917 if (rxcw & E1000_RXCW_SYNCH) { 918 if (!(rxcw & E1000_RXCW_IV)) { 919 mac->serdes_has_link = TRUE; 920 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 921 } else { 922 mac->serdes_has_link = FALSE; 923 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 924 } 925 } else { 926 mac->serdes_has_link = FALSE; 927 DEBUGOUT("SERDES: Link down - no sync.\n"); 928 } 929 } else { 930 mac->serdes_has_link = FALSE; 931 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 932 } 933 } 934 935 return E1000_SUCCESS; 936 } 937 938 /** 939 * e1000_set_default_fc_generic - Set flow control default values 940 * @hw: pointer to the HW structure 941 * 942 * Read the EEPROM for the default values for flow control and store the 943 * values. 944 **/ 945 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 946 { 947 s32 ret_val; 948 u16 nvm_data; 949 u16 nvm_offset = 0; 950 951 DEBUGFUNC("e1000_set_default_fc_generic"); 952 953 /* Read and store word 0x0F of the EEPROM. This word contains bits 954 * that determine the hardware's default PAUSE (flow control) mode, 955 * a bit that determines whether the HW defaults to enabling or 956 * disabling auto-negotiation, and the direction of the 957 * SW defined pins. If there is no SW over-ride of the flow 958 * control setting, then the variable hw->fc will 959 * be initialized based on a value in the EEPROM. 960 */ 961 if (hw->mac.type == e1000_i350) { 962 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 963 ret_val = hw->nvm.ops.read(hw, 964 NVM_INIT_CONTROL2_REG + 965 nvm_offset, 966 1, &nvm_data); 967 } else { 968 ret_val = hw->nvm.ops.read(hw, 969 NVM_INIT_CONTROL2_REG, 970 1, &nvm_data); 971 } 972 973 974 if (ret_val) { 975 DEBUGOUT("NVM Read Error\n"); 976 return ret_val; 977 } 978 979 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 980 hw->fc.requested_mode = e1000_fc_none; 981 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 982 NVM_WORD0F_ASM_DIR) 983 hw->fc.requested_mode = e1000_fc_tx_pause; 984 else 985 hw->fc.requested_mode = e1000_fc_full; 986 987 return E1000_SUCCESS; 988 } 989 990 /** 991 * e1000_setup_link_generic - Setup flow control and link settings 992 * @hw: pointer to the HW structure 993 * 994 * Determines which flow control settings to use, then configures flow 995 * control. Calls the appropriate media-specific link configuration 996 * function. Assuming the adapter has a valid link partner, a valid link 997 * should be established. Assumes the hardware has previously been reset 998 * and the transmitter and receiver are not enabled. 999 **/ 1000 s32 e1000_setup_link_generic(struct e1000_hw *hw) 1001 { 1002 s32 ret_val; 1003 1004 DEBUGFUNC("e1000_setup_link_generic"); 1005 1006 /* In the case of the phy reset being blocked, we already have a link. 1007 * We do not need to set it up again. 1008 */ 1009 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1010 return E1000_SUCCESS; 1011 1012 /* If requested flow control is set to default, set flow control 1013 * based on the EEPROM flow control settings. 1014 */ 1015 if (hw->fc.requested_mode == e1000_fc_default) { 1016 ret_val = e1000_set_default_fc_generic(hw); 1017 if (ret_val) 1018 return ret_val; 1019 } 1020 1021 /* Save off the requested flow control mode for use later. Depending 1022 * on the link partner's capabilities, we may or may not use this mode. 1023 */ 1024 hw->fc.current_mode = hw->fc.requested_mode; 1025 1026 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1027 hw->fc.current_mode); 1028 1029 /* Call the necessary media_type subroutine to configure the link. */ 1030 ret_val = hw->mac.ops.setup_physical_interface(hw); 1031 if (ret_val) 1032 return ret_val; 1033 1034 /* Initialize the flow control address, type, and PAUSE timer 1035 * registers to their default values. This is done even if flow 1036 * control is disabled, because it does not hurt anything to 1037 * initialize these registers. 1038 */ 1039 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1040 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1041 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1042 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1043 1044 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1045 1046 return e1000_set_fc_watermarks_generic(hw); 1047 } 1048 1049 /** 1050 * e1000_commit_fc_settings_generic - Configure flow control 1051 * @hw: pointer to the HW structure 1052 * 1053 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1054 * base on the flow control settings in e1000_mac_info. 1055 **/ 1056 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1057 { 1058 struct e1000_mac_info *mac = &hw->mac; 1059 u32 txcw; 1060 1061 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1062 1063 /* Check for a software override of the flow control settings, and 1064 * setup the device accordingly. If auto-negotiation is enabled, then 1065 * software will have to set the "PAUSE" bits to the correct value in 1066 * the Transmit Config Word Register (TXCW) and re-start auto- 1067 * negotiation. However, if auto-negotiation is disabled, then 1068 * software will have to manually configure the two flow control enable 1069 * bits in the CTRL register. 1070 * 1071 * The possible values of the "fc" parameter are: 1072 * 0: Flow control is completely disabled 1073 * 1: Rx flow control is enabled (we can receive pause frames, 1074 * but not send pause frames). 1075 * 2: Tx flow control is enabled (we can send pause frames but we 1076 * do not support receiving pause frames). 1077 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1078 */ 1079 switch (hw->fc.current_mode) { 1080 case e1000_fc_none: 1081 /* Flow control completely disabled by a software over-ride. */ 1082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1083 break; 1084 case e1000_fc_rx_pause: 1085 /* Rx Flow control is enabled and Tx Flow control is disabled 1086 * by a software over-ride. Since there really isn't a way to 1087 * advertise that we are capable of Rx Pause ONLY, we will 1088 * advertise that we support both symmetric and asymmetric Rx 1089 * PAUSE. Later, we will disable the adapter's ability to send 1090 * PAUSE frames. 1091 */ 1092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1093 break; 1094 case e1000_fc_tx_pause: 1095 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1096 * by a software over-ride. 1097 */ 1098 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1099 break; 1100 case e1000_fc_full: 1101 /* Flow control (both Rx and Tx) is enabled by a software 1102 * over-ride. 1103 */ 1104 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1105 break; 1106 default: 1107 DEBUGOUT("Flow control param set incorrectly\n"); 1108 return -E1000_ERR_CONFIG; 1109 break; 1110 } 1111 1112 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1113 mac->txcw = txcw; 1114 1115 return E1000_SUCCESS; 1116 } 1117 1118 /** 1119 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1120 * @hw: pointer to the HW structure 1121 * 1122 * Polls for link up by reading the status register, if link fails to come 1123 * up with auto-negotiation, then the link is forced if a signal is detected. 1124 **/ 1125 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1126 { 1127 struct e1000_mac_info *mac = &hw->mac; 1128 u32 i, status; 1129 s32 ret_val; 1130 1131 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1132 1133 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1134 * serdes media) then poll for a "Link-Up" indication in the Device 1135 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1136 * seconds (Auto-negotiation should complete in less than 500 1137 * milliseconds even if the other end is doing it in SW). 1138 */ 1139 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1140 msec_delay(10); 1141 status = E1000_READ_REG(hw, E1000_STATUS); 1142 if (status & E1000_STATUS_LU) 1143 break; 1144 } 1145 if (i == FIBER_LINK_UP_LIMIT) { 1146 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1147 mac->autoneg_failed = TRUE; 1148 /* AutoNeg failed to achieve a link, so we'll call 1149 * mac->check_for_link. This routine will force the 1150 * link up if we detect a signal. This will allow us to 1151 * communicate with non-autonegotiating link partners. 1152 */ 1153 ret_val = mac->ops.check_for_link(hw); 1154 if (ret_val) { 1155 DEBUGOUT("Error while checking for link\n"); 1156 return ret_val; 1157 } 1158 mac->autoneg_failed = FALSE; 1159 } else { 1160 mac->autoneg_failed = FALSE; 1161 DEBUGOUT("Valid Link Found\n"); 1162 } 1163 1164 return E1000_SUCCESS; 1165 } 1166 1167 /** 1168 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1169 * @hw: pointer to the HW structure 1170 * 1171 * Configures collision distance and flow control for fiber and serdes 1172 * links. Upon successful setup, poll for link. 1173 **/ 1174 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1175 { 1176 u32 ctrl; 1177 s32 ret_val; 1178 1179 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1180 1181 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1182 1183 /* Take the link out of reset */ 1184 ctrl &= ~E1000_CTRL_LRST; 1185 1186 hw->mac.ops.config_collision_dist(hw); 1187 1188 ret_val = e1000_commit_fc_settings_generic(hw); 1189 if (ret_val) 1190 return ret_val; 1191 1192 /* Since auto-negotiation is enabled, take the link out of reset (the 1193 * link will be in reset, because we previously reset the chip). This 1194 * will restart auto-negotiation. If auto-negotiation is successful 1195 * then the link-up status bit will be set and the flow control enable 1196 * bits (RFCE and TFCE) will be set according to their negotiated value. 1197 */ 1198 DEBUGOUT("Auto-negotiation enabled\n"); 1199 1200 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1201 E1000_WRITE_FLUSH(hw); 1202 msec_delay(1); 1203 1204 /* For these adapters, the SW definable pin 1 is set when the optics 1205 * detect a signal. If we have a signal, then poll for a "Link-Up" 1206 * indication. 1207 */ 1208 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1209 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1210 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1211 } else { 1212 DEBUGOUT("No signal detected\n"); 1213 } 1214 1215 return ret_val; 1216 } 1217 1218 /** 1219 * e1000_config_collision_dist_generic - Configure collision distance 1220 * @hw: pointer to the HW structure 1221 * 1222 * Configures the collision distance to the default value and is used 1223 * during link setup. 1224 **/ 1225 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1226 { 1227 u32 tctl; 1228 1229 DEBUGFUNC("e1000_config_collision_dist_generic"); 1230 1231 tctl = E1000_READ_REG(hw, E1000_TCTL); 1232 1233 tctl &= ~E1000_TCTL_COLD; 1234 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1235 1236 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1237 E1000_WRITE_FLUSH(hw); 1238 } 1239 1240 /** 1241 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1242 * @hw: pointer to the HW structure 1243 * 1244 * Sets the flow control high/low threshold (watermark) registers. If 1245 * flow control XON frame transmission is enabled, then set XON frame 1246 * transmission as well. 1247 **/ 1248 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1249 { 1250 u32 fcrtl = 0, fcrth = 0; 1251 1252 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1253 1254 /* Set the flow control receive threshold registers. Normally, 1255 * these registers will be set to a default threshold that may be 1256 * adjusted later by the driver's runtime code. However, if the 1257 * ability to transmit pause frames is not enabled, then these 1258 * registers will be set to 0. 1259 */ 1260 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1261 /* We need to set up the Receive Threshold high and low water 1262 * marks as well as (optionally) enabling the transmission of 1263 * XON frames. 1264 */ 1265 fcrtl = hw->fc.low_water; 1266 if (hw->fc.send_xon) 1267 fcrtl |= E1000_FCRTL_XONE; 1268 1269 fcrth = hw->fc.high_water; 1270 } 1271 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1272 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1273 1274 return E1000_SUCCESS; 1275 } 1276 1277 /** 1278 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1279 * @hw: pointer to the HW structure 1280 * 1281 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1282 * device control register to reflect the adapter settings. TFCE and RFCE 1283 * need to be explicitly set by software when a copper PHY is used because 1284 * autonegotiation is managed by the PHY rather than the MAC. Software must 1285 * also configure these bits when link is forced on a fiber connection. 1286 **/ 1287 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1288 { 1289 u32 ctrl; 1290 1291 DEBUGFUNC("e1000_force_mac_fc_generic"); 1292 1293 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1294 1295 /* Because we didn't get link via the internal auto-negotiation 1296 * mechanism (we either forced link or we got link via PHY 1297 * auto-neg), we have to manually enable/disable transmit an 1298 * receive flow control. 1299 * 1300 * The "Case" statement below enables/disable flow control 1301 * according to the "hw->fc.current_mode" parameter. 1302 * 1303 * The possible values of the "fc" parameter are: 1304 * 0: Flow control is completely disabled 1305 * 1: Rx flow control is enabled (we can receive pause 1306 * frames but not send pause frames). 1307 * 2: Tx flow control is enabled (we can send pause frames 1308 * frames but we do not receive pause frames). 1309 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1310 * other: No other values should be possible at this point. 1311 */ 1312 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1313 1314 switch (hw->fc.current_mode) { 1315 case e1000_fc_none: 1316 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1317 break; 1318 case e1000_fc_rx_pause: 1319 ctrl &= (~E1000_CTRL_TFCE); 1320 ctrl |= E1000_CTRL_RFCE; 1321 break; 1322 case e1000_fc_tx_pause: 1323 ctrl &= (~E1000_CTRL_RFCE); 1324 ctrl |= E1000_CTRL_TFCE; 1325 break; 1326 case e1000_fc_full: 1327 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1328 break; 1329 default: 1330 DEBUGOUT("Flow control param set incorrectly\n"); 1331 return -E1000_ERR_CONFIG; 1332 } 1333 1334 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1335 1336 return E1000_SUCCESS; 1337 } 1338 1339 /** 1340 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1341 * @hw: pointer to the HW structure 1342 * 1343 * Checks the status of auto-negotiation after link up to ensure that the 1344 * speed and duplex were not forced. If the link needed to be forced, then 1345 * flow control needs to be forced also. If auto-negotiation is enabled 1346 * and did not fail, then we configure flow control based on our link 1347 * partner. 1348 **/ 1349 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1350 { 1351 struct e1000_mac_info *mac = &hw->mac; 1352 s32 ret_val = E1000_SUCCESS; 1353 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1354 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1355 u16 speed, duplex; 1356 1357 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1358 1359 /* Check for the case where we have fiber media and auto-neg failed 1360 * so we had to force link. In this case, we need to force the 1361 * configuration of the MAC to match the "fc" parameter. 1362 */ 1363 if (mac->autoneg_failed) { 1364 if (hw->phy.media_type == e1000_media_type_fiber || 1365 hw->phy.media_type == e1000_media_type_internal_serdes) 1366 ret_val = e1000_force_mac_fc_generic(hw); 1367 } else { 1368 if (hw->phy.media_type == e1000_media_type_copper) 1369 ret_val = e1000_force_mac_fc_generic(hw); 1370 } 1371 1372 if (ret_val) { 1373 DEBUGOUT("Error forcing flow control settings\n"); 1374 return ret_val; 1375 } 1376 1377 /* Check for the case where we have copper media and auto-neg is 1378 * enabled. In this case, we need to check and see if Auto-Neg 1379 * has completed, and if so, how the PHY and link partner has 1380 * flow control configured. 1381 */ 1382 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1383 /* Read the MII Status Register and check to see if AutoNeg 1384 * has completed. We read this twice because this reg has 1385 * some "sticky" (latched) bits. 1386 */ 1387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1388 if (ret_val) 1389 return ret_val; 1390 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1391 if (ret_val) 1392 return ret_val; 1393 1394 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1395 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1396 return ret_val; 1397 } 1398 1399 /* The AutoNeg process has completed, so we now need to 1400 * read both the Auto Negotiation Advertisement 1401 * Register (Address 4) and the Auto_Negotiation Base 1402 * Page Ability Register (Address 5) to determine how 1403 * flow control was negotiated. 1404 */ 1405 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1406 &mii_nway_adv_reg); 1407 if (ret_val) 1408 return ret_val; 1409 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1410 &mii_nway_lp_ability_reg); 1411 if (ret_val) 1412 return ret_val; 1413 1414 /* Two bits in the Auto Negotiation Advertisement Register 1415 * (Address 4) and two bits in the Auto Negotiation Base 1416 * Page Ability Register (Address 5) determine flow control 1417 * for both the PHY and the link partner. The following 1418 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1419 * 1999, describes these PAUSE resolution bits and how flow 1420 * control is determined based upon these settings. 1421 * NOTE: DC = Don't Care 1422 * 1423 * LOCAL DEVICE | LINK PARTNER 1424 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1425 *-------|---------|-------|---------|-------------------- 1426 * 0 | 0 | DC | DC | e1000_fc_none 1427 * 0 | 1 | 0 | DC | e1000_fc_none 1428 * 0 | 1 | 1 | 0 | e1000_fc_none 1429 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1430 * 1 | 0 | 0 | DC | e1000_fc_none 1431 * 1 | DC | 1 | DC | e1000_fc_full 1432 * 1 | 1 | 0 | 0 | e1000_fc_none 1433 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1434 * 1435 * Are both PAUSE bits set to 1? If so, this implies 1436 * Symmetric Flow Control is enabled at both ends. The 1437 * ASM_DIR bits are irrelevant per the spec. 1438 * 1439 * For Symmetric Flow Control: 1440 * 1441 * LOCAL DEVICE | LINK PARTNER 1442 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1443 *-------|---------|-------|---------|-------------------- 1444 * 1 | DC | 1 | DC | E1000_fc_full 1445 * 1446 */ 1447 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1448 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1449 /* Now we need to check if the user selected Rx ONLY 1450 * of pause frames. In this case, we had to advertise 1451 * FULL flow control because we could not advertise Rx 1452 * ONLY. Hence, we must now check to see if we need to 1453 * turn OFF the TRANSMISSION of PAUSE frames. 1454 */ 1455 if (hw->fc.requested_mode == e1000_fc_full) { 1456 hw->fc.current_mode = e1000_fc_full; 1457 DEBUGOUT("Flow Control = FULL.\n"); 1458 } else { 1459 hw->fc.current_mode = e1000_fc_rx_pause; 1460 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1461 } 1462 } 1463 /* For receiving PAUSE frames ONLY. 1464 * 1465 * LOCAL DEVICE | LINK PARTNER 1466 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1467 *-------|---------|-------|---------|-------------------- 1468 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1469 */ 1470 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1471 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1472 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1473 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1474 hw->fc.current_mode = e1000_fc_tx_pause; 1475 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1476 } 1477 /* For transmitting PAUSE frames ONLY. 1478 * 1479 * LOCAL DEVICE | LINK PARTNER 1480 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1481 *-------|---------|-------|---------|-------------------- 1482 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1483 */ 1484 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1485 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1486 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1487 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1488 hw->fc.current_mode = e1000_fc_rx_pause; 1489 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1490 } else { 1491 /* Per the IEEE spec, at this point flow control 1492 * should be disabled. 1493 */ 1494 hw->fc.current_mode = e1000_fc_none; 1495 DEBUGOUT("Flow Control = NONE.\n"); 1496 } 1497 1498 /* Now we need to do one last check... If we auto- 1499 * negotiated to HALF DUPLEX, flow control should not be 1500 * enabled per IEEE 802.3 spec. 1501 */ 1502 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1503 if (ret_val) { 1504 DEBUGOUT("Error getting link speed and duplex\n"); 1505 return ret_val; 1506 } 1507 1508 if (duplex == HALF_DUPLEX) 1509 hw->fc.current_mode = e1000_fc_none; 1510 1511 /* Now we call a subroutine to actually force the MAC 1512 * controller to use the correct flow control settings. 1513 */ 1514 ret_val = e1000_force_mac_fc_generic(hw); 1515 if (ret_val) { 1516 DEBUGOUT("Error forcing flow control settings\n"); 1517 return ret_val; 1518 } 1519 } 1520 1521 /* Check for the case where we have SerDes media and auto-neg is 1522 * enabled. In this case, we need to check and see if Auto-Neg 1523 * has completed, and if so, how the PHY and link partner has 1524 * flow control configured. 1525 */ 1526 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1527 mac->autoneg) { 1528 /* Read the PCS_LSTS and check to see if AutoNeg 1529 * has completed. 1530 */ 1531 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1532 1533 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1534 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1535 return ret_val; 1536 } 1537 1538 /* The AutoNeg process has completed, so we now need to 1539 * read both the Auto Negotiation Advertisement 1540 * Register (PCS_ANADV) and the Auto_Negotiation Base 1541 * Page Ability Register (PCS_LPAB) to determine how 1542 * flow control was negotiated. 1543 */ 1544 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1545 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1546 1547 /* Two bits in the Auto Negotiation Advertisement Register 1548 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1549 * Page Ability Register (PCS_LPAB) determine flow control 1550 * for both the PHY and the link partner. The following 1551 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1552 * 1999, describes these PAUSE resolution bits and how flow 1553 * control is determined based upon these settings. 1554 * NOTE: DC = Don't Care 1555 * 1556 * LOCAL DEVICE | LINK PARTNER 1557 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1558 *-------|---------|-------|---------|-------------------- 1559 * 0 | 0 | DC | DC | e1000_fc_none 1560 * 0 | 1 | 0 | DC | e1000_fc_none 1561 * 0 | 1 | 1 | 0 | e1000_fc_none 1562 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1563 * 1 | 0 | 0 | DC | e1000_fc_none 1564 * 1 | DC | 1 | DC | e1000_fc_full 1565 * 1 | 1 | 0 | 0 | e1000_fc_none 1566 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1567 * 1568 * Are both PAUSE bits set to 1? If so, this implies 1569 * Symmetric Flow Control is enabled at both ends. The 1570 * ASM_DIR bits are irrelevant per the spec. 1571 * 1572 * For Symmetric Flow Control: 1573 * 1574 * LOCAL DEVICE | LINK PARTNER 1575 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1576 *-------|---------|-------|---------|-------------------- 1577 * 1 | DC | 1 | DC | e1000_fc_full 1578 * 1579 */ 1580 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1581 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1582 /* Now we need to check if the user selected Rx ONLY 1583 * of pause frames. In this case, we had to advertise 1584 * FULL flow control because we could not advertise Rx 1585 * ONLY. Hence, we must now check to see if we need to 1586 * turn OFF the TRANSMISSION of PAUSE frames. 1587 */ 1588 if (hw->fc.requested_mode == e1000_fc_full) { 1589 hw->fc.current_mode = e1000_fc_full; 1590 DEBUGOUT("Flow Control = FULL.\n"); 1591 } else { 1592 hw->fc.current_mode = e1000_fc_rx_pause; 1593 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1594 } 1595 } 1596 /* For receiving PAUSE frames ONLY. 1597 * 1598 * LOCAL DEVICE | LINK PARTNER 1599 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1600 *-------|---------|-------|---------|-------------------- 1601 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1602 */ 1603 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1604 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1605 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1606 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1607 hw->fc.current_mode = e1000_fc_tx_pause; 1608 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1609 } 1610 /* For transmitting PAUSE frames ONLY. 1611 * 1612 * LOCAL DEVICE | LINK PARTNER 1613 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1614 *-------|---------|-------|---------|-------------------- 1615 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1616 */ 1617 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1618 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1619 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1620 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1621 hw->fc.current_mode = e1000_fc_rx_pause; 1622 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1623 } else { 1624 /* Per the IEEE spec, at this point flow control 1625 * should be disabled. 1626 */ 1627 hw->fc.current_mode = e1000_fc_none; 1628 DEBUGOUT("Flow Control = NONE.\n"); 1629 } 1630 1631 /* Now we call a subroutine to actually force the MAC 1632 * controller to use the correct flow control settings. 1633 */ 1634 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1635 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1636 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1637 1638 ret_val = e1000_force_mac_fc_generic(hw); 1639 if (ret_val) { 1640 DEBUGOUT("Error forcing flow control settings\n"); 1641 return ret_val; 1642 } 1643 } 1644 1645 return E1000_SUCCESS; 1646 } 1647 1648 /** 1649 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1650 * @hw: pointer to the HW structure 1651 * @speed: stores the current speed 1652 * @duplex: stores the current duplex 1653 * 1654 * Read the status register for the current speed/duplex and store the current 1655 * speed and duplex for copper connections. 1656 **/ 1657 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1658 u16 *duplex) 1659 { 1660 u32 status; 1661 1662 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1663 1664 status = E1000_READ_REG(hw, E1000_STATUS); 1665 if (status & E1000_STATUS_SPEED_1000) { 1666 *speed = SPEED_1000; 1667 DEBUGOUT("1000 Mbs, "); 1668 } else if (status & E1000_STATUS_SPEED_100) { 1669 *speed = SPEED_100; 1670 DEBUGOUT("100 Mbs, "); 1671 } else { 1672 *speed = SPEED_10; 1673 DEBUGOUT("10 Mbs, "); 1674 } 1675 1676 if (status & E1000_STATUS_FD) { 1677 *duplex = FULL_DUPLEX; 1678 DEBUGOUT("Full Duplex\n"); 1679 } else { 1680 *duplex = HALF_DUPLEX; 1681 DEBUGOUT("Half Duplex\n"); 1682 } 1683 1684 return E1000_SUCCESS; 1685 } 1686 1687 /** 1688 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1689 * @hw: pointer to the HW structure 1690 * @speed: stores the current speed 1691 * @duplex: stores the current duplex 1692 * 1693 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1694 * for fiber/serdes links. 1695 **/ 1696 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1697 u16 *speed, u16 *duplex) 1698 { 1699 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1700 1701 *speed = SPEED_1000; 1702 *duplex = FULL_DUPLEX; 1703 1704 return E1000_SUCCESS; 1705 } 1706 1707 /** 1708 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1709 * @hw: pointer to the HW structure 1710 * 1711 * Acquire the HW semaphore to access the PHY or NVM 1712 **/ 1713 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1714 { 1715 u32 swsm; 1716 s32 timeout = hw->nvm.word_size + 1; 1717 s32 i = 0; 1718 1719 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1720 1721 /* Get the SW semaphore */ 1722 while (i < timeout) { 1723 swsm = E1000_READ_REG(hw, E1000_SWSM); 1724 if (!(swsm & E1000_SWSM_SMBI)) 1725 break; 1726 1727 usec_delay(50); 1728 i++; 1729 } 1730 1731 if (i == timeout) { 1732 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1733 return -E1000_ERR_NVM; 1734 } 1735 1736 /* Get the FW semaphore. */ 1737 for (i = 0; i < timeout; i++) { 1738 swsm = E1000_READ_REG(hw, E1000_SWSM); 1739 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1740 1741 /* Semaphore acquired if bit latched */ 1742 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1743 break; 1744 1745 usec_delay(50); 1746 } 1747 1748 if (i == timeout) { 1749 /* Release semaphores */ 1750 e1000_put_hw_semaphore_generic(hw); 1751 DEBUGOUT("Driver can't access the NVM\n"); 1752 return -E1000_ERR_NVM; 1753 } 1754 1755 return E1000_SUCCESS; 1756 } 1757 1758 /** 1759 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1760 * @hw: pointer to the HW structure 1761 * 1762 * Release hardware semaphore used to access the PHY or NVM 1763 **/ 1764 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1765 { 1766 u32 swsm; 1767 1768 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1769 1770 swsm = E1000_READ_REG(hw, E1000_SWSM); 1771 1772 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1773 1774 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1775 } 1776 1777 /** 1778 * e1000_get_auto_rd_done_generic - Check for auto read completion 1779 * @hw: pointer to the HW structure 1780 * 1781 * Check EEPROM for Auto Read done bit. 1782 **/ 1783 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1784 { 1785 s32 i = 0; 1786 1787 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1788 1789 while (i < AUTO_READ_DONE_TIMEOUT) { 1790 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1791 break; 1792 msec_delay(1); 1793 i++; 1794 } 1795 1796 if (i == AUTO_READ_DONE_TIMEOUT) { 1797 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1798 return -E1000_ERR_RESET; 1799 } 1800 1801 return E1000_SUCCESS; 1802 } 1803 1804 /** 1805 * e1000_valid_led_default_generic - Verify a valid default LED config 1806 * @hw: pointer to the HW structure 1807 * @data: pointer to the NVM (EEPROM) 1808 * 1809 * Read the EEPROM for the current default LED configuration. If the 1810 * LED configuration is not valid, set to a valid LED configuration. 1811 **/ 1812 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1813 { 1814 s32 ret_val; 1815 1816 DEBUGFUNC("e1000_valid_led_default_generic"); 1817 1818 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1819 if (ret_val) { 1820 DEBUGOUT("NVM Read Error\n"); 1821 return ret_val; 1822 } 1823 1824 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1825 *data = ID_LED_DEFAULT; 1826 1827 return E1000_SUCCESS; 1828 } 1829 1830 /** 1831 * e1000_id_led_init_generic - 1832 * @hw: pointer to the HW structure 1833 * 1834 **/ 1835 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1836 { 1837 struct e1000_mac_info *mac = &hw->mac; 1838 s32 ret_val; 1839 const u32 ledctl_mask = 0x000000FF; 1840 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1841 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1842 u16 data, i, temp; 1843 const u16 led_mask = 0x0F; 1844 1845 DEBUGFUNC("e1000_id_led_init_generic"); 1846 1847 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1848 if (ret_val) 1849 return ret_val; 1850 1851 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1852 mac->ledctl_mode1 = mac->ledctl_default; 1853 mac->ledctl_mode2 = mac->ledctl_default; 1854 1855 for (i = 0; i < 4; i++) { 1856 temp = (data >> (i << 2)) & led_mask; 1857 switch (temp) { 1858 case ID_LED_ON1_DEF2: 1859 case ID_LED_ON1_ON2: 1860 case ID_LED_ON1_OFF2: 1861 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1862 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1863 break; 1864 case ID_LED_OFF1_DEF2: 1865 case ID_LED_OFF1_ON2: 1866 case ID_LED_OFF1_OFF2: 1867 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1868 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1869 break; 1870 default: 1871 /* Do nothing */ 1872 break; 1873 } 1874 switch (temp) { 1875 case ID_LED_DEF1_ON2: 1876 case ID_LED_ON1_ON2: 1877 case ID_LED_OFF1_ON2: 1878 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1879 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1880 break; 1881 case ID_LED_DEF1_OFF2: 1882 case ID_LED_ON1_OFF2: 1883 case ID_LED_OFF1_OFF2: 1884 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1885 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1886 break; 1887 default: 1888 /* Do nothing */ 1889 break; 1890 } 1891 } 1892 1893 return E1000_SUCCESS; 1894 } 1895 1896 /** 1897 * e1000_setup_led_generic - Configures SW controllable LED 1898 * @hw: pointer to the HW structure 1899 * 1900 * This prepares the SW controllable LED for use and saves the current state 1901 * of the LED so it can be later restored. 1902 **/ 1903 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1904 { 1905 u32 ledctl; 1906 1907 DEBUGFUNC("e1000_setup_led_generic"); 1908 1909 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1910 return -E1000_ERR_CONFIG; 1911 1912 if (hw->phy.media_type == e1000_media_type_fiber) { 1913 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1914 hw->mac.ledctl_default = ledctl; 1915 /* Turn off LED0 */ 1916 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1917 E1000_LEDCTL_LED0_MODE_MASK); 1918 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1919 E1000_LEDCTL_LED0_MODE_SHIFT); 1920 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1921 } else if (hw->phy.media_type == e1000_media_type_copper) { 1922 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1923 } 1924 1925 return E1000_SUCCESS; 1926 } 1927 1928 /** 1929 * e1000_cleanup_led_generic - Set LED config to default operation 1930 * @hw: pointer to the HW structure 1931 * 1932 * Remove the current LED configuration and set the LED configuration 1933 * to the default value, saved from the EEPROM. 1934 **/ 1935 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1936 { 1937 DEBUGFUNC("e1000_cleanup_led_generic"); 1938 1939 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1940 return E1000_SUCCESS; 1941 } 1942 1943 /** 1944 * e1000_blink_led_generic - Blink LED 1945 * @hw: pointer to the HW structure 1946 * 1947 * Blink the LEDs which are set to be on. 1948 **/ 1949 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1950 { 1951 u32 ledctl_blink = 0; 1952 u32 i; 1953 1954 DEBUGFUNC("e1000_blink_led_generic"); 1955 1956 if (hw->phy.media_type == e1000_media_type_fiber) { 1957 /* always blink LED0 for PCI-E fiber */ 1958 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1959 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1960 } else { 1961 /* Set the blink bit for each LED that's "on" (0x0E) 1962 * (or "off" if inverted) in ledctl_mode2. The blink 1963 * logic in hardware only works when mode is set to "on" 1964 * so it must be changed accordingly when the mode is 1965 * "off" and inverted. 1966 */ 1967 ledctl_blink = hw->mac.ledctl_mode2; 1968 for (i = 0; i < 32; i += 8) { 1969 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1970 E1000_LEDCTL_LED0_MODE_MASK; 1971 u32 led_default = hw->mac.ledctl_default >> i; 1972 1973 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1974 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1975 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1976 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1977 ledctl_blink &= 1978 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1979 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1980 E1000_LEDCTL_MODE_LED_ON) << i; 1981 } 1982 } 1983 } 1984 1985 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1986 1987 return E1000_SUCCESS; 1988 } 1989 1990 /** 1991 * e1000_led_on_generic - Turn LED on 1992 * @hw: pointer to the HW structure 1993 * 1994 * Turn LED on. 1995 **/ 1996 s32 e1000_led_on_generic(struct e1000_hw *hw) 1997 { 1998 u32 ctrl; 1999 2000 DEBUGFUNC("e1000_led_on_generic"); 2001 2002 switch (hw->phy.media_type) { 2003 case e1000_media_type_fiber: 2004 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2005 ctrl &= ~E1000_CTRL_SWDPIN0; 2006 ctrl |= E1000_CTRL_SWDPIO0; 2007 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2008 break; 2009 case e1000_media_type_copper: 2010 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2011 break; 2012 default: 2013 break; 2014 } 2015 2016 return E1000_SUCCESS; 2017 } 2018 2019 /** 2020 * e1000_led_off_generic - Turn LED off 2021 * @hw: pointer to the HW structure 2022 * 2023 * Turn LED off. 2024 **/ 2025 s32 e1000_led_off_generic(struct e1000_hw *hw) 2026 { 2027 u32 ctrl; 2028 2029 DEBUGFUNC("e1000_led_off_generic"); 2030 2031 switch (hw->phy.media_type) { 2032 case e1000_media_type_fiber: 2033 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2034 ctrl |= E1000_CTRL_SWDPIN0; 2035 ctrl |= E1000_CTRL_SWDPIO0; 2036 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2037 break; 2038 case e1000_media_type_copper: 2039 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2040 break; 2041 default: 2042 break; 2043 } 2044 2045 return E1000_SUCCESS; 2046 } 2047 2048 /** 2049 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2050 * @hw: pointer to the HW structure 2051 * @no_snoop: bitmap of snoop events 2052 * 2053 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2054 **/ 2055 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2056 { 2057 u32 gcr; 2058 2059 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2060 2061 if (hw->bus.type != e1000_bus_type_pci_express) 2062 return; 2063 2064 if (no_snoop) { 2065 gcr = E1000_READ_REG(hw, E1000_GCR); 2066 gcr &= ~(PCIE_NO_SNOOP_ALL); 2067 gcr |= no_snoop; 2068 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2069 } 2070 } 2071 2072 /** 2073 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2074 * @hw: pointer to the HW structure 2075 * 2076 * Returns E1000_SUCCESS if successful, else returns -10 2077 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2078 * the master requests to be disabled. 2079 * 2080 * Disables PCI-Express master access and verifies there are no pending 2081 * requests. 2082 **/ 2083 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2084 { 2085 u32 ctrl; 2086 s32 timeout = MASTER_DISABLE_TIMEOUT; 2087 2088 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2089 2090 if (hw->bus.type != e1000_bus_type_pci_express) 2091 return E1000_SUCCESS; 2092 2093 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2094 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2095 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2096 2097 while (timeout) { 2098 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2099 E1000_STATUS_GIO_MASTER_ENABLE)) 2100 break; 2101 usec_delay(100); 2102 timeout--; 2103 } 2104 2105 if (!timeout) { 2106 DEBUGOUT("Master requests are pending.\n"); 2107 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2108 } 2109 2110 return E1000_SUCCESS; 2111 } 2112 2113 /** 2114 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2115 * @hw: pointer to the HW structure 2116 * 2117 * Reset the Adaptive Interframe Spacing throttle to default values. 2118 **/ 2119 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2120 { 2121 struct e1000_mac_info *mac = &hw->mac; 2122 2123 DEBUGFUNC("e1000_reset_adaptive_generic"); 2124 2125 if (!mac->adaptive_ifs) { 2126 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2127 return; 2128 } 2129 2130 mac->current_ifs_val = 0; 2131 mac->ifs_min_val = IFS_MIN; 2132 mac->ifs_max_val = IFS_MAX; 2133 mac->ifs_step_size = IFS_STEP; 2134 mac->ifs_ratio = IFS_RATIO; 2135 2136 mac->in_ifs_mode = FALSE; 2137 E1000_WRITE_REG(hw, E1000_AIT, 0); 2138 } 2139 2140 /** 2141 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2142 * @hw: pointer to the HW structure 2143 * 2144 * Update the Adaptive Interframe Spacing Throttle value based on the 2145 * time between transmitted packets and time between collisions. 2146 **/ 2147 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2148 { 2149 struct e1000_mac_info *mac = &hw->mac; 2150 2151 DEBUGFUNC("e1000_update_adaptive_generic"); 2152 2153 if (!mac->adaptive_ifs) { 2154 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2155 return; 2156 } 2157 2158 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2159 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2160 mac->in_ifs_mode = TRUE; 2161 if (mac->current_ifs_val < mac->ifs_max_val) { 2162 if (!mac->current_ifs_val) 2163 mac->current_ifs_val = mac->ifs_min_val; 2164 else 2165 mac->current_ifs_val += 2166 mac->ifs_step_size; 2167 E1000_WRITE_REG(hw, E1000_AIT, 2168 mac->current_ifs_val); 2169 } 2170 } 2171 } else { 2172 if (mac->in_ifs_mode && 2173 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2174 mac->current_ifs_val = 0; 2175 mac->in_ifs_mode = FALSE; 2176 E1000_WRITE_REG(hw, E1000_AIT, 0); 2177 } 2178 } 2179 } 2180 2181 /** 2182 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2183 * @hw: pointer to the HW structure 2184 * 2185 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2186 * set, which is forced to MDI mode only. 2187 **/ 2188 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2189 { 2190 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2191 2192 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2193 DEBUGOUT("Invalid MDI setting detected\n"); 2194 hw->phy.mdix = 1; 2195 return -E1000_ERR_CONFIG; 2196 } 2197 2198 return E1000_SUCCESS; 2199 } 2200 2201 /** 2202 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2203 * @hw: pointer to the HW structure 2204 * 2205 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2206 * operation. 2207 **/ 2208 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2209 { 2210 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2211 2212 return E1000_SUCCESS; 2213 } 2214 2215 /** 2216 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2217 * @hw: pointer to the HW structure 2218 * @reg: 32bit register offset such as E1000_SCTL 2219 * @offset: register offset to write to 2220 * @data: data to write at register offset 2221 * 2222 * Writes an address/data control type register. There are several of these 2223 * and they all have the format address << 8 | data and bit 31 is polled for 2224 * completion. 2225 **/ 2226 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2227 u32 offset, u8 data) 2228 { 2229 u32 i, regvalue = 0; 2230 2231 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2232 2233 /* Set up the address and data */ 2234 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2235 E1000_WRITE_REG(hw, reg, regvalue); 2236 2237 /* Poll the ready bit to see if the MDI read completed */ 2238 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2239 usec_delay(5); 2240 regvalue = E1000_READ_REG(hw, reg); 2241 if (regvalue & E1000_GEN_CTL_READY) 2242 break; 2243 } 2244 if (!(regvalue & E1000_GEN_CTL_READY)) { 2245 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2246 return -E1000_ERR_PHY; 2247 } 2248 2249 return E1000_SUCCESS; 2250 } 2251