1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40 /** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47 { 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.mta_set = e1000_null_mta_set; 82 mac->ops.rar_set = e1000_rar_set_generic; 83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 84 } 85 86 /** 87 * e1000_null_ops_generic - No-op function, returns 0 88 * @hw: pointer to the HW structure 89 **/ 90 s32 e1000_null_ops_generic(struct e1000_hw *hw) 91 { 92 DEBUGFUNC("e1000_null_ops_generic"); 93 return E1000_SUCCESS; 94 } 95 96 /** 97 * e1000_null_mac_generic - No-op function, return void 98 * @hw: pointer to the HW structure 99 **/ 100 void e1000_null_mac_generic(struct e1000_hw *hw) 101 { 102 DEBUGFUNC("e1000_null_mac_generic"); 103 return; 104 } 105 106 /** 107 * e1000_null_link_info - No-op function, return 0 108 * @hw: pointer to the HW structure 109 **/ 110 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 111 { 112 DEBUGFUNC("e1000_null_link_info"); 113 return E1000_SUCCESS; 114 } 115 116 /** 117 * e1000_null_mng_mode - No-op function, return FALSE 118 * @hw: pointer to the HW structure 119 **/ 120 bool e1000_null_mng_mode(struct e1000_hw *hw) 121 { 122 DEBUGFUNC("e1000_null_mng_mode"); 123 return FALSE; 124 } 125 126 /** 127 * e1000_null_update_mc - No-op function, return void 128 * @hw: pointer to the HW structure 129 **/ 130 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 141 { 142 DEBUGFUNC("e1000_null_write_vfta"); 143 return; 144 } 145 146 /** 147 * e1000_null_set_mta - No-op function, return void 148 * @hw: pointer to the HW structure 149 **/ 150 void e1000_null_mta_set(struct e1000_hw *hw, u32 a) 151 { 152 DEBUGFUNC("e1000_null_mta_set"); 153 return; 154 } 155 156 /** 157 * e1000_null_rar_set - No-op function, return void 158 * @hw: pointer to the HW structure 159 **/ 160 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 161 { 162 DEBUGFUNC("e1000_null_rar_set"); 163 return; 164 } 165 166 /** 167 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 168 * @hw: pointer to the HW structure 169 * 170 * Determines and stores the system bus information for a particular 171 * network interface. The following bus information is determined and stored: 172 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 173 **/ 174 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 175 { 176 struct e1000_mac_info *mac = &hw->mac; 177 struct e1000_bus_info *bus = &hw->bus; 178 u32 status = E1000_READ_REG(hw, E1000_STATUS); 179 s32 ret_val = E1000_SUCCESS; 180 181 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 182 183 /* PCI or PCI-X? */ 184 bus->type = (status & E1000_STATUS_PCIX_MODE) 185 ? e1000_bus_type_pcix 186 : e1000_bus_type_pci; 187 188 /* Bus speed */ 189 if (bus->type == e1000_bus_type_pci) { 190 bus->speed = (status & E1000_STATUS_PCI66) 191 ? e1000_bus_speed_66 192 : e1000_bus_speed_33; 193 } else { 194 switch (status & E1000_STATUS_PCIX_SPEED) { 195 case E1000_STATUS_PCIX_SPEED_66: 196 bus->speed = e1000_bus_speed_66; 197 break; 198 case E1000_STATUS_PCIX_SPEED_100: 199 bus->speed = e1000_bus_speed_100; 200 break; 201 case E1000_STATUS_PCIX_SPEED_133: 202 bus->speed = e1000_bus_speed_133; 203 break; 204 default: 205 bus->speed = e1000_bus_speed_reserved; 206 break; 207 } 208 } 209 210 /* Bus width */ 211 bus->width = (status & E1000_STATUS_BUS64) 212 ? e1000_bus_width_64 213 : e1000_bus_width_32; 214 215 /* Which PCI(-X) function? */ 216 mac->ops.set_lan_id(hw); 217 218 return ret_val; 219 } 220 221 /** 222 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 223 * @hw: pointer to the HW structure 224 * 225 * Determines and stores the system bus information for a particular 226 * network interface. The following bus information is determined and stored: 227 * bus speed, bus width, type (PCIe), and PCIe function. 228 **/ 229 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 230 { 231 struct e1000_mac_info *mac = &hw->mac; 232 struct e1000_bus_info *bus = &hw->bus; 233 234 s32 ret_val; 235 u16 pcie_link_status; 236 237 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 238 239 bus->type = e1000_bus_type_pci_express; 240 bus->speed = e1000_bus_speed_2500; 241 242 ret_val = e1000_read_pcie_cap_reg(hw, 243 PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) 246 bus->width = e1000_bus_width_unknown; 247 else 248 bus->width = (enum e1000_bus_width)((pcie_link_status & 249 PCIE_LINK_WIDTH_MASK) >> 250 PCIE_LINK_WIDTH_SHIFT); 251 252 mac->ops.set_lan_id(hw); 253 254 return E1000_SUCCESS; 255 } 256 257 /** 258 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 259 * 260 * @hw: pointer to the HW structure 261 * 262 * Determines the LAN function id by reading memory-mapped registers 263 * and swaps the port value if requested. 264 **/ 265 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 266 { 267 struct e1000_bus_info *bus = &hw->bus; 268 u32 reg; 269 270 /* 271 * The status register reports the correct function number 272 * for the device regardless of function swap state. 273 */ 274 reg = E1000_READ_REG(hw, E1000_STATUS); 275 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 276 } 277 278 /** 279 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 280 * @hw: pointer to the HW structure 281 * 282 * Determines the LAN function id by reading PCI config space. 283 **/ 284 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 285 { 286 struct e1000_bus_info *bus = &hw->bus; 287 u16 pci_header_type; 288 u32 status; 289 290 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 291 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 292 status = E1000_READ_REG(hw, E1000_STATUS); 293 bus->func = (status & E1000_STATUS_FUNC_MASK) 294 >> E1000_STATUS_FUNC_SHIFT; 295 } else { 296 bus->func = 0; 297 } 298 } 299 300 /** 301 * e1000_set_lan_id_single_port - Set LAN id for a single port device 302 * @hw: pointer to the HW structure 303 * 304 * Sets the LAN function id to zero for a single port device. 305 **/ 306 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 307 { 308 struct e1000_bus_info *bus = &hw->bus; 309 310 bus->func = 0; 311 } 312 313 /** 314 * e1000_clear_vfta_generic - Clear VLAN filter table 315 * @hw: pointer to the HW structure 316 * 317 * Clears the register array which contains the VLAN filter table by 318 * setting all the values to 0. 319 **/ 320 void e1000_clear_vfta_generic(struct e1000_hw *hw) 321 { 322 u32 offset; 323 324 DEBUGFUNC("e1000_clear_vfta_generic"); 325 326 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 328 E1000_WRITE_FLUSH(hw); 329 } 330 } 331 332 /** 333 * e1000_write_vfta_generic - Write value to VLAN filter table 334 * @hw: pointer to the HW structure 335 * @offset: register offset in VLAN filter table 336 * @value: register value written to VLAN filter table 337 * 338 * Writes value at the given offset in the register array which stores 339 * the VLAN filter table. 340 **/ 341 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 342 { 343 DEBUGFUNC("e1000_write_vfta_generic"); 344 345 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 346 E1000_WRITE_FLUSH(hw); 347 } 348 349 /** 350 * e1000_init_rx_addrs_generic - Initialize receive address's 351 * @hw: pointer to the HW structure 352 * @rar_count: receive address registers 353 * 354 * Setups the receive address registers by setting the base receive address 355 * register to the devices MAC address and clearing all the other receive 356 * address registers to 0. 357 **/ 358 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 359 { 360 u32 i; 361 u8 mac_addr[ETH_ADDR_LEN] = {0}; 362 363 DEBUGFUNC("e1000_init_rx_addrs_generic"); 364 365 /* Setup the receive address */ 366 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 367 368 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 369 370 /* Zero out the other (rar_entry_count - 1) receive addresses */ 371 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 372 for (i = 1; i < rar_count; i++) 373 hw->mac.ops.rar_set(hw, mac_addr, i); 374 } 375 376 /** 377 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 378 * @hw: pointer to the HW structure 379 * 380 * Checks the nvm for an alternate MAC address. An alternate MAC address 381 * can be setup by pre-boot software and must be treated like a permanent 382 * address and must override the actual permanent MAC address. If an 383 * alternate MAC address is found it is programmed into RAR0, replacing 384 * the permanent address that was installed into RAR0 by the Si on reset. 385 * This function will return SUCCESS unless it encounters an error while 386 * reading the EEPROM. 387 **/ 388 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 389 { 390 u32 i; 391 s32 ret_val = E1000_SUCCESS; 392 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 393 u8 alt_mac_addr[ETH_ADDR_LEN]; 394 395 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 396 397 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 398 &nvm_alt_mac_addr_offset); 399 if (ret_val) { 400 DEBUGOUT("NVM Read Error\n"); 401 goto out; 402 } 403 404 if (nvm_alt_mac_addr_offset == 0xFFFF) { 405 /* There is no Alternate MAC Address */ 406 goto out; 407 } 408 409 if (hw->bus.func == E1000_FUNC_1) 410 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 411 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 412 offset = nvm_alt_mac_addr_offset + (i >> 1); 413 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 414 if (ret_val) { 415 DEBUGOUT("NVM Read Error\n"); 416 goto out; 417 } 418 419 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 420 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 421 } 422 423 /* if multicast bit is set, the alternate address will not be used */ 424 if (alt_mac_addr[0] & 0x01) { 425 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 426 goto out; 427 } 428 429 /* 430 * We have a valid alternate MAC address, and we want to treat it the 431 * same as the normal permanent MAC address stored by the HW into the 432 * RAR. Do this by mapping this address into RAR0. 433 */ 434 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 435 436 out: 437 return ret_val; 438 } 439 440 /** 441 * e1000_rar_set_generic - Set receive address register 442 * @hw: pointer to the HW structure 443 * @addr: pointer to the receive address 444 * @index: receive address array register 445 * 446 * Sets the receive address array register at index to the address passed 447 * in by addr. 448 **/ 449 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 450 { 451 u32 rar_low, rar_high; 452 453 DEBUGFUNC("e1000_rar_set_generic"); 454 455 /* 456 * HW expects these in little endian so we reverse the byte order 457 * from network order (big endian) to little endian 458 */ 459 rar_low = ((u32) addr[0] | 460 ((u32) addr[1] << 8) | 461 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 462 463 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 464 465 /* If MAC address zero, no need to set the AV bit */ 466 if (rar_low || rar_high) 467 rar_high |= E1000_RAH_AV; 468 469 /* 470 * Some bridges will combine consecutive 32-bit writes into 471 * a single burst write, which will malfunction on some parts. 472 * The flushes avoid this. 473 */ 474 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 475 E1000_WRITE_FLUSH(hw); 476 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 477 E1000_WRITE_FLUSH(hw); 478 } 479 480 /** 481 * e1000_mta_set_generic - Set multicast filter table address 482 * @hw: pointer to the HW structure 483 * @hash_value: determines the MTA register and bit to set 484 * 485 * The multicast table address is a register array of 32-bit registers. 486 * The hash_value is used to determine what register the bit is in, the 487 * current value is read, the new bit is OR'd in and the new value is 488 * written back into the register. 489 **/ 490 void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 491 { 492 u32 hash_bit, hash_reg, mta; 493 494 DEBUGFUNC("e1000_mta_set_generic"); 495 /* 496 * The MTA is a register array of 32-bit registers. It is 497 * treated like an array of (32*mta_reg_count) bits. We want to 498 * set bit BitArray[hash_value]. So we figure out what register 499 * the bit is in, read it, OR in the new bit, then write 500 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 501 * mask to bits 31:5 of the hash value which gives us the 502 * register we're modifying. The hash bit within that register 503 * is determined by the lower 5 bits of the hash value. 504 */ 505 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 506 hash_bit = hash_value & 0x1F; 507 508 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 509 510 mta |= (1 << hash_bit); 511 512 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 513 E1000_WRITE_FLUSH(hw); 514 } 515 516 /** 517 * e1000_update_mc_addr_list_generic - Update Multicast addresses 518 * @hw: pointer to the HW structure 519 * @mc_addr_list: array of multicast addresses to program 520 * @mc_addr_count: number of multicast addresses to program 521 * 522 * Updates entire Multicast Table Array. 523 * The caller must have a packed mc_addr_list of multicast addresses. 524 **/ 525 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 526 u8 *mc_addr_list, u32 mc_addr_count) 527 { 528 u32 hash_value, hash_bit, hash_reg; 529 int i; 530 531 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 532 533 /* clear mta_shadow */ 534 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 535 536 /* update mta_shadow from mc_addr_list */ 537 for (i = 0; (u32) i < mc_addr_count; i++) { 538 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 539 540 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 541 hash_bit = hash_value & 0x1F; 542 543 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 544 mc_addr_list += (ETH_ADDR_LEN); 545 } 546 547 /* replace the entire MTA table */ 548 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 549 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 550 E1000_WRITE_FLUSH(hw); 551 } 552 553 /** 554 * e1000_hash_mc_addr_generic - Generate a multicast hash value 555 * @hw: pointer to the HW structure 556 * @mc_addr: pointer to a multicast address 557 * 558 * Generates a multicast address hash value which is used to determine 559 * the multicast filter table array address and new table value. See 560 * e1000_mta_set_generic() 561 **/ 562 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 563 { 564 u32 hash_value, hash_mask; 565 u8 bit_shift = 0; 566 567 DEBUGFUNC("e1000_hash_mc_addr_generic"); 568 569 /* Register count multiplied by bits per register */ 570 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 571 572 /* 573 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 574 * where 0xFF would still fall within the hash mask. 575 */ 576 while (hash_mask >> bit_shift != 0xFF) 577 bit_shift++; 578 579 /* 580 * The portion of the address that is used for the hash table 581 * is determined by the mc_filter_type setting. 582 * The algorithm is such that there is a total of 8 bits of shifting. 583 * The bit_shift for a mc_filter_type of 0 represents the number of 584 * left-shifts where the MSB of mc_addr[5] would still fall within 585 * the hash_mask. Case 0 does this exactly. Since there are a total 586 * of 8 bits of shifting, then mc_addr[4] will shift right the 587 * remaining number of bits. Thus 8 - bit_shift. The rest of the 588 * cases are a variation of this algorithm...essentially raising the 589 * number of bits to shift mc_addr[5] left, while still keeping the 590 * 8-bit shifting total. 591 * 592 * For example, given the following Destination MAC Address and an 593 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 594 * we can see that the bit_shift for case 0 is 4. These are the hash 595 * values resulting from each mc_filter_type... 596 * [0] [1] [2] [3] [4] [5] 597 * 01 AA 00 12 34 56 598 * LSB MSB 599 * 600 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 601 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 602 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 603 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 604 */ 605 switch (hw->mac.mc_filter_type) { 606 default: 607 case 0: 608 break; 609 case 1: 610 bit_shift += 1; 611 break; 612 case 2: 613 bit_shift += 2; 614 break; 615 case 3: 616 bit_shift += 4; 617 break; 618 } 619 620 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 621 (((u16) mc_addr[5]) << bit_shift))); 622 623 return hash_value; 624 } 625 626 /** 627 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 628 * @hw: pointer to the HW structure 629 * 630 * In certain situations, a system BIOS may report that the PCIx maximum 631 * memory read byte count (MMRBC) value is higher than than the actual 632 * value. We check the PCIx command register with the current PCIx status 633 * register. 634 **/ 635 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 636 { 637 u16 cmd_mmrbc; 638 u16 pcix_cmd; 639 u16 pcix_stat_hi_word; 640 u16 stat_mmrbc; 641 642 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 643 644 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 645 if (hw->bus.type != e1000_bus_type_pcix) 646 return; 647 648 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 649 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 650 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 651 PCIX_COMMAND_MMRBC_SHIFT; 652 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 653 PCIX_STATUS_HI_MMRBC_SHIFT; 654 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 655 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 656 if (cmd_mmrbc > stat_mmrbc) { 657 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 658 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 659 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 660 } 661 } 662 663 /** 664 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 665 * @hw: pointer to the HW structure 666 * 667 * Clears the base hardware counters by reading the counter registers. 668 **/ 669 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 670 { 671 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 672 673 E1000_READ_REG(hw, E1000_CRCERRS); 674 E1000_READ_REG(hw, E1000_SYMERRS); 675 E1000_READ_REG(hw, E1000_MPC); 676 E1000_READ_REG(hw, E1000_SCC); 677 E1000_READ_REG(hw, E1000_ECOL); 678 E1000_READ_REG(hw, E1000_MCC); 679 E1000_READ_REG(hw, E1000_LATECOL); 680 E1000_READ_REG(hw, E1000_COLC); 681 E1000_READ_REG(hw, E1000_DC); 682 E1000_READ_REG(hw, E1000_SEC); 683 E1000_READ_REG(hw, E1000_RLEC); 684 E1000_READ_REG(hw, E1000_XONRXC); 685 E1000_READ_REG(hw, E1000_XONTXC); 686 E1000_READ_REG(hw, E1000_XOFFRXC); 687 E1000_READ_REG(hw, E1000_XOFFTXC); 688 E1000_READ_REG(hw, E1000_FCRUC); 689 E1000_READ_REG(hw, E1000_GPRC); 690 E1000_READ_REG(hw, E1000_BPRC); 691 E1000_READ_REG(hw, E1000_MPRC); 692 E1000_READ_REG(hw, E1000_GPTC); 693 E1000_READ_REG(hw, E1000_GORCL); 694 E1000_READ_REG(hw, E1000_GORCH); 695 E1000_READ_REG(hw, E1000_GOTCL); 696 E1000_READ_REG(hw, E1000_GOTCH); 697 E1000_READ_REG(hw, E1000_RNBC); 698 E1000_READ_REG(hw, E1000_RUC); 699 E1000_READ_REG(hw, E1000_RFC); 700 E1000_READ_REG(hw, E1000_ROC); 701 E1000_READ_REG(hw, E1000_RJC); 702 E1000_READ_REG(hw, E1000_TORL); 703 E1000_READ_REG(hw, E1000_TORH); 704 E1000_READ_REG(hw, E1000_TOTL); 705 E1000_READ_REG(hw, E1000_TOTH); 706 E1000_READ_REG(hw, E1000_TPR); 707 E1000_READ_REG(hw, E1000_TPT); 708 E1000_READ_REG(hw, E1000_MPTC); 709 E1000_READ_REG(hw, E1000_BPTC); 710 } 711 712 /** 713 * e1000_check_for_copper_link_generic - Check for link (Copper) 714 * @hw: pointer to the HW structure 715 * 716 * Checks to see of the link status of the hardware has changed. If a 717 * change in link status has been detected, then we read the PHY registers 718 * to get the current speed/duplex if link exists. 719 **/ 720 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 721 { 722 struct e1000_mac_info *mac = &hw->mac; 723 s32 ret_val; 724 bool link; 725 726 DEBUGFUNC("e1000_check_for_copper_link"); 727 728 /* 729 * We only want to go out to the PHY registers to see if Auto-Neg 730 * has completed and/or if our link status has changed. The 731 * get_link_status flag is set upon receiving a Link Status 732 * Change or Rx Sequence Error interrupt. 733 */ 734 if (!mac->get_link_status) { 735 ret_val = E1000_SUCCESS; 736 goto out; 737 } 738 739 /* 740 * First we want to see if the MII Status Register reports 741 * link. If so, then we want to get the current speed/duplex 742 * of the PHY. 743 */ 744 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 745 if (ret_val) 746 goto out; 747 748 if (!link) 749 goto out; /* No link detected */ 750 751 mac->get_link_status = FALSE; 752 753 if (hw->phy.type == e1000_phy_82578) { 754 ret_val = e1000_link_stall_workaround_hv(hw); 755 if (ret_val) 756 goto out; 757 } 758 759 /* 760 * Check if there was DownShift, must be checked 761 * immediately after link-up 762 */ 763 e1000_check_downshift_generic(hw); 764 765 /* 766 * If we are forcing speed/duplex, then we simply return since 767 * we have already determined whether we have link or not. 768 */ 769 if (!mac->autoneg) { 770 ret_val = -E1000_ERR_CONFIG; 771 goto out; 772 } 773 774 /* 775 * Auto-Neg is enabled. Auto Speed Detection takes care 776 * of MAC speed/duplex configuration. So we only need to 777 * configure Collision Distance in the MAC. 778 */ 779 e1000_config_collision_dist_generic(hw); 780 781 /* 782 * Configure Flow Control now that Auto-Neg has completed. 783 * First, we need to restore the desired flow control 784 * settings because we may have had to re-autoneg with a 785 * different link partner. 786 */ 787 ret_val = e1000_config_fc_after_link_up_generic(hw); 788 if (ret_val) 789 DEBUGOUT("Error configuring flow control\n"); 790 791 out: 792 return ret_val; 793 } 794 795 /** 796 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 797 * @hw: pointer to the HW structure 798 * 799 * Checks for link up on the hardware. If link is not up and we have 800 * a signal, then we need to force link up. 801 **/ 802 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 803 { 804 struct e1000_mac_info *mac = &hw->mac; 805 u32 rxcw; 806 u32 ctrl; 807 u32 status; 808 s32 ret_val = E1000_SUCCESS; 809 810 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 811 812 ctrl = E1000_READ_REG(hw, E1000_CTRL); 813 status = E1000_READ_REG(hw, E1000_STATUS); 814 rxcw = E1000_READ_REG(hw, E1000_RXCW); 815 816 /* 817 * If we don't have link (auto-negotiation failed or link partner 818 * cannot auto-negotiate), the cable is plugged in (we have signal), 819 * and our link partner is not trying to auto-negotiate with us (we 820 * are receiving idles or data), we need to force link up. We also 821 * need to give auto-negotiation time to complete, in case the cable 822 * was just plugged in. The autoneg_failed flag does this. 823 */ 824 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 825 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 826 (!(rxcw & E1000_RXCW_C))) { 827 if (mac->autoneg_failed == 0) { 828 mac->autoneg_failed = 1; 829 goto out; 830 } 831 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 832 833 /* Disable auto-negotiation in the TXCW register */ 834 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 835 836 /* Force link-up and also force full-duplex. */ 837 ctrl = E1000_READ_REG(hw, E1000_CTRL); 838 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 839 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 840 841 /* Configure Flow Control after forcing link up. */ 842 ret_val = e1000_config_fc_after_link_up_generic(hw); 843 if (ret_val) { 844 DEBUGOUT("Error configuring flow control\n"); 845 goto out; 846 } 847 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 848 /* 849 * If we are forcing link and we are receiving /C/ ordered 850 * sets, re-enable auto-negotiation in the TXCW register 851 * and disable forced link in the Device Control register 852 * in an attempt to auto-negotiate with our link partner. 853 */ 854 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 855 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 856 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 857 858 mac->serdes_has_link = TRUE; 859 } 860 861 out: 862 return ret_val; 863 } 864 865 /** 866 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 867 * @hw: pointer to the HW structure 868 * 869 * Checks for link up on the hardware. If link is not up and we have 870 * a signal, then we need to force link up. 871 **/ 872 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 873 { 874 struct e1000_mac_info *mac = &hw->mac; 875 u32 rxcw; 876 u32 ctrl; 877 u32 status; 878 s32 ret_val = E1000_SUCCESS; 879 880 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 881 882 ctrl = E1000_READ_REG(hw, E1000_CTRL); 883 status = E1000_READ_REG(hw, E1000_STATUS); 884 rxcw = E1000_READ_REG(hw, E1000_RXCW); 885 886 /* 887 * If we don't have link (auto-negotiation failed or link partner 888 * cannot auto-negotiate), and our link partner is not trying to 889 * auto-negotiate with us (we are receiving idles or data), 890 * we need to force link up. We also need to give auto-negotiation 891 * time to complete. 892 */ 893 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 894 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 895 if (mac->autoneg_failed == 0) { 896 mac->autoneg_failed = 1; 897 goto out; 898 } 899 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 900 901 /* Disable auto-negotiation in the TXCW register */ 902 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 903 904 /* Force link-up and also force full-duplex. */ 905 ctrl = E1000_READ_REG(hw, E1000_CTRL); 906 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 907 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 908 909 /* Configure Flow Control after forcing link up. */ 910 ret_val = e1000_config_fc_after_link_up_generic(hw); 911 if (ret_val) { 912 DEBUGOUT("Error configuring flow control\n"); 913 goto out; 914 } 915 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 916 /* 917 * If we are forcing link and we are receiving /C/ ordered 918 * sets, re-enable auto-negotiation in the TXCW register 919 * and disable forced link in the Device Control register 920 * in an attempt to auto-negotiate with our link partner. 921 */ 922 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 923 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 924 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 925 926 mac->serdes_has_link = TRUE; 927 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 928 /* 929 * If we force link for non-auto-negotiation switch, check 930 * link status based on MAC synchronization for internal 931 * serdes media type. 932 */ 933 /* SYNCH bit and IV bit are sticky. */ 934 usec_delay(10); 935 rxcw = E1000_READ_REG(hw, E1000_RXCW); 936 if (rxcw & E1000_RXCW_SYNCH) { 937 if (!(rxcw & E1000_RXCW_IV)) { 938 mac->serdes_has_link = TRUE; 939 DEBUGOUT("SERDES: Link up - forced.\n"); 940 } 941 } else { 942 mac->serdes_has_link = FALSE; 943 DEBUGOUT("SERDES: Link down - force failed.\n"); 944 } 945 } 946 947 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 948 status = E1000_READ_REG(hw, E1000_STATUS); 949 if (status & E1000_STATUS_LU) { 950 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 951 usec_delay(10); 952 rxcw = E1000_READ_REG(hw, E1000_RXCW); 953 if (rxcw & E1000_RXCW_SYNCH) { 954 if (!(rxcw & E1000_RXCW_IV)) { 955 mac->serdes_has_link = TRUE; 956 DEBUGOUT("SERDES: Link up - autoneg " 957 "completed sucessfully.\n"); 958 } else { 959 mac->serdes_has_link = FALSE; 960 DEBUGOUT("SERDES: Link down - invalid" 961 "codewords detected in autoneg.\n"); 962 } 963 } else { 964 mac->serdes_has_link = FALSE; 965 DEBUGOUT("SERDES: Link down - no sync.\n"); 966 } 967 } else { 968 mac->serdes_has_link = FALSE; 969 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 970 } 971 } 972 973 out: 974 return ret_val; 975 } 976 977 /** 978 * e1000_setup_link_generic - Setup flow control and link settings 979 * @hw: pointer to the HW structure 980 * 981 * Determines which flow control settings to use, then configures flow 982 * control. Calls the appropriate media-specific link configuration 983 * function. Assuming the adapter has a valid link partner, a valid link 984 * should be established. Assumes the hardware has previously been reset 985 * and the transmitter and receiver are not enabled. 986 **/ 987 s32 e1000_setup_link_generic(struct e1000_hw *hw) 988 { 989 s32 ret_val = E1000_SUCCESS; 990 991 DEBUGFUNC("e1000_setup_link_generic"); 992 993 /* 994 * In the case of the phy reset being blocked, we already have a link. 995 * We do not need to set it up again. 996 */ 997 if (hw->phy.ops.check_reset_block) 998 if (hw->phy.ops.check_reset_block(hw)) 999 goto out; 1000 1001 /* 1002 * If requested flow control is set to default, set flow control 1003 * based on the EEPROM flow control settings. 1004 */ 1005 if (hw->fc.requested_mode == e1000_fc_default) { 1006 ret_val = e1000_set_default_fc_generic(hw); 1007 if (ret_val) 1008 goto out; 1009 } 1010 1011 /* 1012 * Save off the requested flow control mode for use later. Depending 1013 * on the link partner's capabilities, we may or may not use this mode. 1014 */ 1015 hw->fc.current_mode = hw->fc.requested_mode; 1016 1017 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1018 hw->fc.current_mode); 1019 1020 /* Call the necessary media_type subroutine to configure the link. */ 1021 ret_val = hw->mac.ops.setup_physical_interface(hw); 1022 if (ret_val) 1023 goto out; 1024 1025 /* 1026 * Initialize the flow control address, type, and PAUSE timer 1027 * registers to their default values. This is done even if flow 1028 * control is disabled, because it does not hurt anything to 1029 * initialize these registers. 1030 */ 1031 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1032 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1033 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1034 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1035 1036 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1037 1038 ret_val = e1000_set_fc_watermarks_generic(hw); 1039 1040 out: 1041 return ret_val; 1042 } 1043 1044 /** 1045 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1046 * @hw: pointer to the HW structure 1047 * 1048 * Configures collision distance and flow control for fiber and serdes 1049 * links. Upon successful setup, poll for link. 1050 **/ 1051 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1052 { 1053 u32 ctrl; 1054 s32 ret_val = E1000_SUCCESS; 1055 1056 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1057 1058 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1059 1060 /* Take the link out of reset */ 1061 ctrl &= ~E1000_CTRL_LRST; 1062 1063 e1000_config_collision_dist_generic(hw); 1064 1065 ret_val = e1000_commit_fc_settings_generic(hw); 1066 if (ret_val) 1067 goto out; 1068 1069 /* 1070 * Since auto-negotiation is enabled, take the link out of reset (the 1071 * link will be in reset, because we previously reset the chip). This 1072 * will restart auto-negotiation. If auto-negotiation is successful 1073 * then the link-up status bit will be set and the flow control enable 1074 * bits (RFCE and TFCE) will be set according to their negotiated value. 1075 */ 1076 DEBUGOUT("Auto-negotiation enabled\n"); 1077 1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1079 E1000_WRITE_FLUSH(hw); 1080 msec_delay(1); 1081 1082 /* 1083 * For these adapters, the SW definable pin 1 is set when the optics 1084 * detect a signal. If we have a signal, then poll for a "Link-Up" 1085 * indication. 1086 */ 1087 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1088 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1089 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1090 } else { 1091 DEBUGOUT("No signal detected\n"); 1092 } 1093 1094 out: 1095 return ret_val; 1096 } 1097 1098 /** 1099 * e1000_config_collision_dist_generic - Configure collision distance 1100 * @hw: pointer to the HW structure 1101 * 1102 * Configures the collision distance to the default value and is used 1103 * during link setup. Currently no func pointer exists and all 1104 * implementations are handled in the generic version of this function. 1105 **/ 1106 void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1107 { 1108 u32 tctl; 1109 1110 DEBUGFUNC("e1000_config_collision_dist_generic"); 1111 1112 tctl = E1000_READ_REG(hw, E1000_TCTL); 1113 1114 tctl &= ~E1000_TCTL_COLD; 1115 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1116 1117 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1118 E1000_WRITE_FLUSH(hw); 1119 } 1120 1121 /** 1122 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1123 * @hw: pointer to the HW structure 1124 * 1125 * Polls for link up by reading the status register, if link fails to come 1126 * up with auto-negotiation, then the link is forced if a signal is detected. 1127 **/ 1128 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1129 { 1130 struct e1000_mac_info *mac = &hw->mac; 1131 u32 i, status; 1132 s32 ret_val = E1000_SUCCESS; 1133 1134 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1135 1136 /* 1137 * If we have a signal (the cable is plugged in, or assumed TRUE for 1138 * serdes media) then poll for a "Link-Up" indication in the Device 1139 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1140 * seconds (Auto-negotiation should complete in less than 500 1141 * milliseconds even if the other end is doing it in SW). 1142 */ 1143 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1144 msec_delay(10); 1145 status = E1000_READ_REG(hw, E1000_STATUS); 1146 if (status & E1000_STATUS_LU) 1147 break; 1148 } 1149 if (i == FIBER_LINK_UP_LIMIT) { 1150 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1151 mac->autoneg_failed = 1; 1152 /* 1153 * AutoNeg failed to achieve a link, so we'll call 1154 * mac->check_for_link. This routine will force the 1155 * link up if we detect a signal. This will allow us to 1156 * communicate with non-autonegotiating link partners. 1157 */ 1158 ret_val = hw->mac.ops.check_for_link(hw); 1159 if (ret_val) { 1160 DEBUGOUT("Error while checking for link\n"); 1161 goto out; 1162 } 1163 mac->autoneg_failed = 0; 1164 } else { 1165 mac->autoneg_failed = 0; 1166 DEBUGOUT("Valid Link Found\n"); 1167 } 1168 1169 out: 1170 return ret_val; 1171 } 1172 1173 /** 1174 * e1000_commit_fc_settings_generic - Configure flow control 1175 * @hw: pointer to the HW structure 1176 * 1177 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1178 * base on the flow control settings in e1000_mac_info. 1179 **/ 1180 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1181 { 1182 struct e1000_mac_info *mac = &hw->mac; 1183 u32 txcw; 1184 s32 ret_val = E1000_SUCCESS; 1185 1186 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1187 1188 /* 1189 * Check for a software override of the flow control settings, and 1190 * setup the device accordingly. If auto-negotiation is enabled, then 1191 * software will have to set the "PAUSE" bits to the correct value in 1192 * the Transmit Config Word Register (TXCW) and re-start auto- 1193 * negotiation. However, if auto-negotiation is disabled, then 1194 * software will have to manually configure the two flow control enable 1195 * bits in the CTRL register. 1196 * 1197 * The possible values of the "fc" parameter are: 1198 * 0: Flow control is completely disabled 1199 * 1: Rx flow control is enabled (we can receive pause frames, 1200 * but not send pause frames). 1201 * 2: Tx flow control is enabled (we can send pause frames but we 1202 * do not support receiving pause frames). 1203 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1204 */ 1205 switch (hw->fc.current_mode) { 1206 case e1000_fc_none: 1207 /* Flow control completely disabled by a software over-ride. */ 1208 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1209 break; 1210 case e1000_fc_rx_pause: 1211 /* 1212 * Rx Flow control is enabled and Tx Flow control is disabled 1213 * by a software over-ride. Since there really isn't a way to 1214 * advertise that we are capable of Rx Pause ONLY, we will 1215 * advertise that we support both symmetric and asymmetric RX 1216 * PAUSE. Later, we will disable the adapter's ability to send 1217 * PAUSE frames. 1218 */ 1219 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1220 break; 1221 case e1000_fc_tx_pause: 1222 /* 1223 * Tx Flow control is enabled, and Rx Flow control is disabled, 1224 * by a software over-ride. 1225 */ 1226 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1227 break; 1228 case e1000_fc_full: 1229 /* 1230 * Flow control (both Rx and Tx) is enabled by a software 1231 * over-ride. 1232 */ 1233 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1234 break; 1235 default: 1236 DEBUGOUT("Flow control param set incorrectly\n"); 1237 ret_val = -E1000_ERR_CONFIG; 1238 goto out; 1239 break; 1240 } 1241 1242 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1243 mac->txcw = txcw; 1244 1245 out: 1246 return ret_val; 1247 } 1248 1249 /** 1250 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1251 * @hw: pointer to the HW structure 1252 * 1253 * Sets the flow control high/low threshold (watermark) registers. If 1254 * flow control XON frame transmission is enabled, then set XON frame 1255 * transmission as well. 1256 **/ 1257 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1258 { 1259 s32 ret_val = E1000_SUCCESS; 1260 u32 fcrtl = 0, fcrth = 0; 1261 1262 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1263 1264 /* 1265 * Set the flow control receive threshold registers. Normally, 1266 * these registers will be set to a default threshold that may be 1267 * adjusted later by the driver's runtime code. However, if the 1268 * ability to transmit pause frames is not enabled, then these 1269 * registers will be set to 0. 1270 */ 1271 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1272 /* 1273 * We need to set up the Receive Threshold high and low water 1274 * marks as well as (optionally) enabling the transmission of 1275 * XON frames. 1276 */ 1277 fcrtl = hw->fc.low_water; 1278 if (hw->fc.send_xon) 1279 fcrtl |= E1000_FCRTL_XONE; 1280 1281 fcrth = hw->fc.high_water; 1282 } 1283 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1284 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1285 1286 return ret_val; 1287 } 1288 1289 /** 1290 * e1000_set_default_fc_generic - Set flow control default values 1291 * @hw: pointer to the HW structure 1292 * 1293 * Read the EEPROM for the default values for flow control and store the 1294 * values. 1295 **/ 1296 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1297 { 1298 s32 ret_val = E1000_SUCCESS; 1299 u16 nvm_data; 1300 1301 DEBUGFUNC("e1000_set_default_fc_generic"); 1302 1303 /* 1304 * Read and store word 0x0F of the EEPROM. This word contains bits 1305 * that determine the hardware's default PAUSE (flow control) mode, 1306 * a bit that determines whether the HW defaults to enabling or 1307 * disabling auto-negotiation, and the direction of the 1308 * SW defined pins. If there is no SW over-ride of the flow 1309 * control setting, then the variable hw->fc will 1310 * be initialized based on a value in the EEPROM. 1311 */ 1312 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1313 1314 if (ret_val) { 1315 DEBUGOUT("NVM Read Error\n"); 1316 goto out; 1317 } 1318 1319 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1320 hw->fc.requested_mode = e1000_fc_none; 1321 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1322 NVM_WORD0F_ASM_DIR) 1323 hw->fc.requested_mode = e1000_fc_tx_pause; 1324 else 1325 hw->fc.requested_mode = e1000_fc_full; 1326 1327 out: 1328 return ret_val; 1329 } 1330 1331 /** 1332 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1333 * @hw: pointer to the HW structure 1334 * 1335 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1336 * device control register to reflect the adapter settings. TFCE and RFCE 1337 * need to be explicitly set by software when a copper PHY is used because 1338 * autonegotiation is managed by the PHY rather than the MAC. Software must 1339 * also configure these bits when link is forced on a fiber connection. 1340 **/ 1341 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1342 { 1343 u32 ctrl; 1344 s32 ret_val = E1000_SUCCESS; 1345 1346 DEBUGFUNC("e1000_force_mac_fc_generic"); 1347 1348 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1349 1350 /* 1351 * Because we didn't get link via the internal auto-negotiation 1352 * mechanism (we either forced link or we got link via PHY 1353 * auto-neg), we have to manually enable/disable transmit an 1354 * receive flow control. 1355 * 1356 * The "Case" statement below enables/disable flow control 1357 * according to the "hw->fc.current_mode" parameter. 1358 * 1359 * The possible values of the "fc" parameter are: 1360 * 0: Flow control is completely disabled 1361 * 1: Rx flow control is enabled (we can receive pause 1362 * frames but not send pause frames). 1363 * 2: Tx flow control is enabled (we can send pause frames 1364 * frames but we do not receive pause frames). 1365 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1366 * other: No other values should be possible at this point. 1367 */ 1368 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1369 1370 switch (hw->fc.current_mode) { 1371 case e1000_fc_none: 1372 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1373 break; 1374 case e1000_fc_rx_pause: 1375 ctrl &= (~E1000_CTRL_TFCE); 1376 ctrl |= E1000_CTRL_RFCE; 1377 break; 1378 case e1000_fc_tx_pause: 1379 ctrl &= (~E1000_CTRL_RFCE); 1380 ctrl |= E1000_CTRL_TFCE; 1381 break; 1382 case e1000_fc_full: 1383 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1384 break; 1385 default: 1386 DEBUGOUT("Flow control param set incorrectly\n"); 1387 ret_val = -E1000_ERR_CONFIG; 1388 goto out; 1389 } 1390 1391 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1392 1393 out: 1394 return ret_val; 1395 } 1396 1397 /** 1398 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1399 * @hw: pointer to the HW structure 1400 * 1401 * Checks the status of auto-negotiation after link up to ensure that the 1402 * speed and duplex were not forced. If the link needed to be forced, then 1403 * flow control needs to be forced also. If auto-negotiation is enabled 1404 * and did not fail, then we configure flow control based on our link 1405 * partner. 1406 **/ 1407 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1408 { 1409 struct e1000_mac_info *mac = &hw->mac; 1410 s32 ret_val = E1000_SUCCESS; 1411 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1412 u16 speed, duplex; 1413 1414 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1415 1416 /* 1417 * Check for the case where we have fiber media and auto-neg failed 1418 * so we had to force link. In this case, we need to force the 1419 * configuration of the MAC to match the "fc" parameter. 1420 */ 1421 if (mac->autoneg_failed) { 1422 if (hw->phy.media_type == e1000_media_type_fiber || 1423 hw->phy.media_type == e1000_media_type_internal_serdes) 1424 ret_val = e1000_force_mac_fc_generic(hw); 1425 } else { 1426 if (hw->phy.media_type == e1000_media_type_copper) 1427 ret_val = e1000_force_mac_fc_generic(hw); 1428 } 1429 1430 if (ret_val) { 1431 DEBUGOUT("Error forcing flow control settings\n"); 1432 goto out; 1433 } 1434 1435 /* 1436 * Check for the case where we have copper media and auto-neg is 1437 * enabled. In this case, we need to check and see if Auto-Neg 1438 * has completed, and if so, how the PHY and link partner has 1439 * flow control configured. 1440 */ 1441 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1442 /* 1443 * Read the MII Status Register and check to see if AutoNeg 1444 * has completed. We read this twice because this reg has 1445 * some "sticky" (latched) bits. 1446 */ 1447 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1448 if (ret_val) 1449 goto out; 1450 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1451 if (ret_val) 1452 goto out; 1453 1454 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1455 DEBUGOUT("Copper PHY and Auto Neg " 1456 "has not completed.\n"); 1457 goto out; 1458 } 1459 1460 /* 1461 * The AutoNeg process has completed, so we now need to 1462 * read both the Auto Negotiation Advertisement 1463 * Register (Address 4) and the Auto_Negotiation Base 1464 * Page Ability Register (Address 5) to determine how 1465 * flow control was negotiated. 1466 */ 1467 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1468 &mii_nway_adv_reg); 1469 if (ret_val) 1470 goto out; 1471 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1472 &mii_nway_lp_ability_reg); 1473 if (ret_val) 1474 goto out; 1475 1476 /* 1477 * Two bits in the Auto Negotiation Advertisement Register 1478 * (Address 4) and two bits in the Auto Negotiation Base 1479 * Page Ability Register (Address 5) determine flow control 1480 * for both the PHY and the link partner. The following 1481 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1482 * 1999, describes these PAUSE resolution bits and how flow 1483 * control is determined based upon these settings. 1484 * NOTE: DC = Don't Care 1485 * 1486 * LOCAL DEVICE | LINK PARTNER 1487 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1488 *-------|---------|-------|---------|-------------------- 1489 * 0 | 0 | DC | DC | e1000_fc_none 1490 * 0 | 1 | 0 | DC | e1000_fc_none 1491 * 0 | 1 | 1 | 0 | e1000_fc_none 1492 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1493 * 1 | 0 | 0 | DC | e1000_fc_none 1494 * 1 | DC | 1 | DC | e1000_fc_full 1495 * 1 | 1 | 0 | 0 | e1000_fc_none 1496 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1497 * 1498 * Are both PAUSE bits set to 1? If so, this implies 1499 * Symmetric Flow Control is enabled at both ends. The 1500 * ASM_DIR bits are irrelevant per the spec. 1501 * 1502 * For Symmetric Flow Control: 1503 * 1504 * LOCAL DEVICE | LINK PARTNER 1505 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1506 *-------|---------|-------|---------|-------------------- 1507 * 1 | DC | 1 | DC | E1000_fc_full 1508 * 1509 */ 1510 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1511 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1512 /* 1513 * Now we need to check if the user selected Rx ONLY 1514 * of pause frames. In this case, we had to advertise 1515 * FULL flow control because we could not advertise RX 1516 * ONLY. Hence, we must now check to see if we need to 1517 * turn OFF the TRANSMISSION of PAUSE frames. 1518 */ 1519 if (hw->fc.requested_mode == e1000_fc_full) { 1520 hw->fc.current_mode = e1000_fc_full; 1521 DEBUGOUT("Flow Control = FULL.\r\n"); 1522 } else { 1523 hw->fc.current_mode = e1000_fc_rx_pause; 1524 DEBUGOUT("Flow Control = " 1525 "RX PAUSE frames only.\r\n"); 1526 } 1527 } 1528 /* 1529 * For receiving PAUSE frames ONLY. 1530 * 1531 * LOCAL DEVICE | LINK PARTNER 1532 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1533 *-------|---------|-------|---------|-------------------- 1534 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1535 */ 1536 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1537 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1538 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1539 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1540 hw->fc.current_mode = e1000_fc_tx_pause; 1541 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1542 } 1543 /* 1544 * For transmitting PAUSE frames ONLY. 1545 * 1546 * LOCAL DEVICE | LINK PARTNER 1547 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1548 *-------|---------|-------|---------|-------------------- 1549 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1550 */ 1551 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1552 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1553 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1554 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1555 hw->fc.current_mode = e1000_fc_rx_pause; 1556 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1557 } else { 1558 /* 1559 * Per the IEEE spec, at this point flow control 1560 * should be disabled. 1561 */ 1562 hw->fc.current_mode = e1000_fc_none; 1563 DEBUGOUT("Flow Control = NONE.\r\n"); 1564 } 1565 1566 /* 1567 * Now we need to do one last check... If we auto- 1568 * negotiated to HALF DUPLEX, flow control should not be 1569 * enabled per IEEE 802.3 spec. 1570 */ 1571 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1572 if (ret_val) { 1573 DEBUGOUT("Error getting link speed and duplex\n"); 1574 goto out; 1575 } 1576 1577 if (duplex == HALF_DUPLEX) 1578 hw->fc.current_mode = e1000_fc_none; 1579 1580 /* 1581 * Now we call a subroutine to actually force the MAC 1582 * controller to use the correct flow control settings. 1583 */ 1584 ret_val = e1000_force_mac_fc_generic(hw); 1585 if (ret_val) { 1586 DEBUGOUT("Error forcing flow control settings\n"); 1587 goto out; 1588 } 1589 } 1590 1591 out: 1592 return ret_val; 1593 } 1594 1595 /** 1596 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1597 * @hw: pointer to the HW structure 1598 * @speed: stores the current speed 1599 * @duplex: stores the current duplex 1600 * 1601 * Read the status register for the current speed/duplex and store the current 1602 * speed and duplex for copper connections. 1603 **/ 1604 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1605 u16 *duplex) 1606 { 1607 u32 status; 1608 1609 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1610 1611 status = E1000_READ_REG(hw, E1000_STATUS); 1612 if (status & E1000_STATUS_SPEED_1000) { 1613 *speed = SPEED_1000; 1614 DEBUGOUT("1000 Mbs, "); 1615 } else if (status & E1000_STATUS_SPEED_100) { 1616 *speed = SPEED_100; 1617 DEBUGOUT("100 Mbs, "); 1618 } else { 1619 *speed = SPEED_10; 1620 DEBUGOUT("10 Mbs, "); 1621 } 1622 1623 if (status & E1000_STATUS_FD) { 1624 *duplex = FULL_DUPLEX; 1625 DEBUGOUT("Full Duplex\n"); 1626 } else { 1627 *duplex = HALF_DUPLEX; 1628 DEBUGOUT("Half Duplex\n"); 1629 } 1630 1631 return E1000_SUCCESS; 1632 } 1633 1634 /** 1635 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1636 * @hw: pointer to the HW structure 1637 * @speed: stores the current speed 1638 * @duplex: stores the current duplex 1639 * 1640 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1641 * for fiber/serdes links. 1642 **/ 1643 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1644 u16 *speed, u16 *duplex) 1645 { 1646 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1647 1648 *speed = SPEED_1000; 1649 *duplex = FULL_DUPLEX; 1650 1651 return E1000_SUCCESS; 1652 } 1653 1654 /** 1655 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1656 * @hw: pointer to the HW structure 1657 * 1658 * Acquire the HW semaphore to access the PHY or NVM 1659 **/ 1660 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1661 { 1662 u32 swsm; 1663 s32 ret_val = E1000_SUCCESS; 1664 s32 timeout = hw->nvm.word_size + 1; 1665 s32 i = 0; 1666 1667 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1668 1669 /* Get the SW semaphore */ 1670 while (i < timeout) { 1671 swsm = E1000_READ_REG(hw, E1000_SWSM); 1672 if (!(swsm & E1000_SWSM_SMBI)) 1673 break; 1674 1675 usec_delay(50); 1676 i++; 1677 } 1678 1679 if (i == timeout) { 1680 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1681 ret_val = -E1000_ERR_NVM; 1682 goto out; 1683 } 1684 1685 /* Get the FW semaphore. */ 1686 for (i = 0; i < timeout; i++) { 1687 swsm = E1000_READ_REG(hw, E1000_SWSM); 1688 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1689 1690 /* Semaphore acquired if bit latched */ 1691 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1692 break; 1693 1694 usec_delay(50); 1695 } 1696 1697 if (i == timeout) { 1698 /* Release semaphores */ 1699 e1000_put_hw_semaphore_generic(hw); 1700 DEBUGOUT("Driver can't access the NVM\n"); 1701 ret_val = -E1000_ERR_NVM; 1702 goto out; 1703 } 1704 1705 out: 1706 return ret_val; 1707 } 1708 1709 /** 1710 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1711 * @hw: pointer to the HW structure 1712 * 1713 * Release hardware semaphore used to access the PHY or NVM 1714 **/ 1715 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1716 { 1717 u32 swsm; 1718 1719 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1720 1721 swsm = E1000_READ_REG(hw, E1000_SWSM); 1722 1723 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1724 1725 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1726 } 1727 1728 /** 1729 * e1000_get_auto_rd_done_generic - Check for auto read completion 1730 * @hw: pointer to the HW structure 1731 * 1732 * Check EEPROM for Auto Read done bit. 1733 **/ 1734 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1735 { 1736 s32 i = 0; 1737 s32 ret_val = E1000_SUCCESS; 1738 1739 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1740 1741 while (i < AUTO_READ_DONE_TIMEOUT) { 1742 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1743 break; 1744 msec_delay(1); 1745 i++; 1746 } 1747 1748 if (i == AUTO_READ_DONE_TIMEOUT) { 1749 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1750 ret_val = -E1000_ERR_RESET; 1751 goto out; 1752 } 1753 1754 out: 1755 return ret_val; 1756 } 1757 1758 /** 1759 * e1000_valid_led_default_generic - Verify a valid default LED config 1760 * @hw: pointer to the HW structure 1761 * @data: pointer to the NVM (EEPROM) 1762 * 1763 * Read the EEPROM for the current default LED configuration. If the 1764 * LED configuration is not valid, set to a valid LED configuration. 1765 **/ 1766 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1767 { 1768 s32 ret_val; 1769 1770 DEBUGFUNC("e1000_valid_led_default_generic"); 1771 1772 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1773 if (ret_val) { 1774 DEBUGOUT("NVM Read Error\n"); 1775 goto out; 1776 } 1777 1778 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1779 *data = ID_LED_DEFAULT; 1780 1781 out: 1782 return ret_val; 1783 } 1784 1785 /** 1786 * e1000_id_led_init_generic - 1787 * @hw: pointer to the HW structure 1788 * 1789 **/ 1790 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1791 { 1792 struct e1000_mac_info *mac = &hw->mac; 1793 s32 ret_val; 1794 const u32 ledctl_mask = 0x000000FF; 1795 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1796 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1797 u16 data, i, temp; 1798 const u16 led_mask = 0x0F; 1799 1800 DEBUGFUNC("e1000_id_led_init_generic"); 1801 1802 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1803 if (ret_val) 1804 goto out; 1805 1806 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1807 mac->ledctl_mode1 = mac->ledctl_default; 1808 mac->ledctl_mode2 = mac->ledctl_default; 1809 1810 for (i = 0; i < 4; i++) { 1811 temp = (data >> (i << 2)) & led_mask; 1812 switch (temp) { 1813 case ID_LED_ON1_DEF2: 1814 case ID_LED_ON1_ON2: 1815 case ID_LED_ON1_OFF2: 1816 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1817 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1818 break; 1819 case ID_LED_OFF1_DEF2: 1820 case ID_LED_OFF1_ON2: 1821 case ID_LED_OFF1_OFF2: 1822 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1823 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1824 break; 1825 default: 1826 /* Do nothing */ 1827 break; 1828 } 1829 switch (temp) { 1830 case ID_LED_DEF1_ON2: 1831 case ID_LED_ON1_ON2: 1832 case ID_LED_OFF1_ON2: 1833 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1834 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1835 break; 1836 case ID_LED_DEF1_OFF2: 1837 case ID_LED_ON1_OFF2: 1838 case ID_LED_OFF1_OFF2: 1839 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1840 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1841 break; 1842 default: 1843 /* Do nothing */ 1844 break; 1845 } 1846 } 1847 1848 out: 1849 return ret_val; 1850 } 1851 1852 /** 1853 * e1000_setup_led_generic - Configures SW controllable LED 1854 * @hw: pointer to the HW structure 1855 * 1856 * This prepares the SW controllable LED for use and saves the current state 1857 * of the LED so it can be later restored. 1858 **/ 1859 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1860 { 1861 u32 ledctl; 1862 s32 ret_val = E1000_SUCCESS; 1863 1864 DEBUGFUNC("e1000_setup_led_generic"); 1865 1866 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1867 ret_val = -E1000_ERR_CONFIG; 1868 goto out; 1869 } 1870 1871 if (hw->phy.media_type == e1000_media_type_fiber) { 1872 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1873 hw->mac.ledctl_default = ledctl; 1874 /* Turn off LED0 */ 1875 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1876 E1000_LEDCTL_LED0_BLINK | 1877 E1000_LEDCTL_LED0_MODE_MASK); 1878 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1879 E1000_LEDCTL_LED0_MODE_SHIFT); 1880 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1881 } else if (hw->phy.media_type == e1000_media_type_copper) { 1882 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1883 } 1884 1885 out: 1886 return ret_val; 1887 } 1888 1889 /** 1890 * e1000_cleanup_led_generic - Set LED config to default operation 1891 * @hw: pointer to the HW structure 1892 * 1893 * Remove the current LED configuration and set the LED configuration 1894 * to the default value, saved from the EEPROM. 1895 **/ 1896 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1897 { 1898 s32 ret_val = E1000_SUCCESS; 1899 1900 DEBUGFUNC("e1000_cleanup_led_generic"); 1901 1902 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1903 ret_val = -E1000_ERR_CONFIG; 1904 goto out; 1905 } 1906 1907 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1908 1909 out: 1910 return ret_val; 1911 } 1912 1913 /** 1914 * e1000_blink_led_generic - Blink LED 1915 * @hw: pointer to the HW structure 1916 * 1917 * Blink the LEDs which are set to be on. 1918 **/ 1919 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1920 { 1921 u32 ledctl_blink = 0; 1922 u32 i; 1923 1924 DEBUGFUNC("e1000_blink_led_generic"); 1925 1926 if (hw->phy.media_type == e1000_media_type_fiber) { 1927 /* always blink LED0 for PCI-E fiber */ 1928 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1929 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1930 } else { 1931 /* 1932 * set the blink bit for each LED that's "on" (0x0E) 1933 * in ledctl_mode2 1934 */ 1935 ledctl_blink = hw->mac.ledctl_mode2; 1936 for (i = 0; i < 4; i++) 1937 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1938 E1000_LEDCTL_MODE_LED_ON) 1939 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1940 (i * 8)); 1941 } 1942 1943 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1944 1945 return E1000_SUCCESS; 1946 } 1947 1948 /** 1949 * e1000_led_on_generic - Turn LED on 1950 * @hw: pointer to the HW structure 1951 * 1952 * Turn LED on. 1953 **/ 1954 s32 e1000_led_on_generic(struct e1000_hw *hw) 1955 { 1956 u32 ctrl; 1957 1958 DEBUGFUNC("e1000_led_on_generic"); 1959 1960 switch (hw->phy.media_type) { 1961 case e1000_media_type_fiber: 1962 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1963 ctrl &= ~E1000_CTRL_SWDPIN0; 1964 ctrl |= E1000_CTRL_SWDPIO0; 1965 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1966 break; 1967 case e1000_media_type_copper: 1968 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1969 break; 1970 default: 1971 break; 1972 } 1973 1974 return E1000_SUCCESS; 1975 } 1976 1977 /** 1978 * e1000_led_off_generic - Turn LED off 1979 * @hw: pointer to the HW structure 1980 * 1981 * Turn LED off. 1982 **/ 1983 s32 e1000_led_off_generic(struct e1000_hw *hw) 1984 { 1985 u32 ctrl; 1986 1987 DEBUGFUNC("e1000_led_off_generic"); 1988 1989 switch (hw->phy.media_type) { 1990 case e1000_media_type_fiber: 1991 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1992 ctrl |= E1000_CTRL_SWDPIN0; 1993 ctrl |= E1000_CTRL_SWDPIO0; 1994 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1995 break; 1996 case e1000_media_type_copper: 1997 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1998 break; 1999 default: 2000 break; 2001 } 2002 2003 return E1000_SUCCESS; 2004 } 2005 2006 /** 2007 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2008 * @hw: pointer to the HW structure 2009 * @no_snoop: bitmap of snoop events 2010 * 2011 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2012 **/ 2013 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2014 { 2015 u32 gcr; 2016 2017 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2018 2019 if (hw->bus.type != e1000_bus_type_pci_express) 2020 goto out; 2021 2022 if (no_snoop) { 2023 gcr = E1000_READ_REG(hw, E1000_GCR); 2024 gcr &= ~(PCIE_NO_SNOOP_ALL); 2025 gcr |= no_snoop; 2026 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2027 } 2028 out: 2029 return; 2030 } 2031 2032 /** 2033 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2034 * @hw: pointer to the HW structure 2035 * 2036 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 2037 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2038 * the master requests to be disabled. 2039 * 2040 * Disables PCI-Express master access and verifies there are no pending 2041 * requests. 2042 **/ 2043 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2044 { 2045 u32 ctrl; 2046 s32 timeout = MASTER_DISABLE_TIMEOUT; 2047 s32 ret_val = E1000_SUCCESS; 2048 2049 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2050 2051 if (hw->bus.type != e1000_bus_type_pci_express) 2052 goto out; 2053 2054 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2055 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2056 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2057 2058 while (timeout) { 2059 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2060 E1000_STATUS_GIO_MASTER_ENABLE)) 2061 break; 2062 usec_delay(100); 2063 timeout--; 2064 } 2065 2066 if (!timeout) { 2067 DEBUGOUT("Master requests are pending.\n"); 2068 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2069 goto out; 2070 } 2071 2072 out: 2073 return ret_val; 2074 } 2075 2076 /** 2077 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2078 * @hw: pointer to the HW structure 2079 * 2080 * Reset the Adaptive Interframe Spacing throttle to default values. 2081 **/ 2082 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2083 { 2084 struct e1000_mac_info *mac = &hw->mac; 2085 2086 DEBUGFUNC("e1000_reset_adaptive_generic"); 2087 2088 if (!mac->adaptive_ifs) { 2089 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2090 goto out; 2091 } 2092 2093 mac->current_ifs_val = 0; 2094 mac->ifs_min_val = IFS_MIN; 2095 mac->ifs_max_val = IFS_MAX; 2096 mac->ifs_step_size = IFS_STEP; 2097 mac->ifs_ratio = IFS_RATIO; 2098 2099 mac->in_ifs_mode = FALSE; 2100 E1000_WRITE_REG(hw, E1000_AIT, 0); 2101 out: 2102 return; 2103 } 2104 2105 /** 2106 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2107 * @hw: pointer to the HW structure 2108 * 2109 * Update the Adaptive Interframe Spacing Throttle value based on the 2110 * time between transmitted packets and time between collisions. 2111 **/ 2112 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2113 { 2114 struct e1000_mac_info *mac = &hw->mac; 2115 2116 DEBUGFUNC("e1000_update_adaptive_generic"); 2117 2118 if (!mac->adaptive_ifs) { 2119 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2120 goto out; 2121 } 2122 2123 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2124 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2125 mac->in_ifs_mode = TRUE; 2126 if (mac->current_ifs_val < mac->ifs_max_val) { 2127 if (!mac->current_ifs_val) 2128 mac->current_ifs_val = mac->ifs_min_val; 2129 else 2130 mac->current_ifs_val += 2131 mac->ifs_step_size; 2132 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2133 } 2134 } 2135 } else { 2136 if (mac->in_ifs_mode && 2137 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2138 mac->current_ifs_val = 0; 2139 mac->in_ifs_mode = FALSE; 2140 E1000_WRITE_REG(hw, E1000_AIT, 0); 2141 } 2142 } 2143 out: 2144 return; 2145 } 2146 2147 /** 2148 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2149 * @hw: pointer to the HW structure 2150 * 2151 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2152 * set, which is forced to MDI mode only. 2153 **/ 2154 s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2155 { 2156 s32 ret_val = E1000_SUCCESS; 2157 2158 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2159 2160 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2161 DEBUGOUT("Invalid MDI setting detected\n"); 2162 hw->phy.mdix = 1; 2163 ret_val = -E1000_ERR_CONFIG; 2164 goto out; 2165 } 2166 2167 out: 2168 return ret_val; 2169 } 2170 2171 /** 2172 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2173 * @hw: pointer to the HW structure 2174 * @reg: 32bit register offset such as E1000_SCTL 2175 * @offset: register offset to write to 2176 * @data: data to write at register offset 2177 * 2178 * Writes an address/data control type register. There are several of these 2179 * and they all have the format address << 8 | data and bit 31 is polled for 2180 * completion. 2181 **/ 2182 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2183 u32 offset, u8 data) 2184 { 2185 u32 i, regvalue = 0; 2186 s32 ret_val = E1000_SUCCESS; 2187 2188 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2189 2190 /* Set up the address and data */ 2191 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2192 E1000_WRITE_REG(hw, reg, regvalue); 2193 2194 /* Poll the ready bit to see if the MDI read completed */ 2195 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2196 usec_delay(5); 2197 regvalue = E1000_READ_REG(hw, reg); 2198 if (regvalue & E1000_GEN_CTL_READY) 2199 break; 2200 } 2201 if (!(regvalue & E1000_GEN_CTL_READY)) { 2202 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2203 ret_val = -E1000_ERR_PHY; 2204 goto out; 2205 } 2206 2207 out: 2208 return ret_val; 2209 } 2210