1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40 /** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47 { 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.rar_set = e1000_rar_set_generic; 82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 83 } 84 85 /** 86 * e1000_null_ops_generic - No-op function, returns 0 87 * @hw: pointer to the HW structure 88 **/ 89 s32 e1000_null_ops_generic(struct e1000_hw *hw) 90 { 91 DEBUGFUNC("e1000_null_ops_generic"); 92 return E1000_SUCCESS; 93 } 94 95 /** 96 * e1000_null_mac_generic - No-op function, return void 97 * @hw: pointer to the HW structure 98 **/ 99 void e1000_null_mac_generic(struct e1000_hw *hw) 100 { 101 DEBUGFUNC("e1000_null_mac_generic"); 102 return; 103 } 104 105 /** 106 * e1000_null_link_info - No-op function, return 0 107 * @hw: pointer to the HW structure 108 **/ 109 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119 bool e1000_null_mng_mode(struct e1000_hw *hw) 120 { 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123 } 124 125 /** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 130 { 131 DEBUGFUNC("e1000_null_update_mc"); 132 return; 133 } 134 135 /** 136 * e1000_null_write_vfta - No-op function, return void 137 * @hw: pointer to the HW structure 138 **/ 139 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 140 { 141 DEBUGFUNC("e1000_null_write_vfta"); 142 return; 143 } 144 145 /** 146 * e1000_null_rar_set - No-op function, return void 147 * @hw: pointer to the HW structure 148 **/ 149 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 150 { 151 DEBUGFUNC("e1000_null_rar_set"); 152 return; 153 } 154 155 /** 156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 157 * @hw: pointer to the HW structure 158 * 159 * Determines and stores the system bus information for a particular 160 * network interface. The following bus information is determined and stored: 161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 162 **/ 163 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 164 { 165 struct e1000_mac_info *mac = &hw->mac; 166 struct e1000_bus_info *bus = &hw->bus; 167 u32 status = E1000_READ_REG(hw, E1000_STATUS); 168 s32 ret_val = E1000_SUCCESS; 169 170 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 171 172 /* PCI or PCI-X? */ 173 bus->type = (status & E1000_STATUS_PCIX_MODE) 174 ? e1000_bus_type_pcix 175 : e1000_bus_type_pci; 176 177 /* Bus speed */ 178 if (bus->type == e1000_bus_type_pci) { 179 bus->speed = (status & E1000_STATUS_PCI66) 180 ? e1000_bus_speed_66 181 : e1000_bus_speed_33; 182 } else { 183 switch (status & E1000_STATUS_PCIX_SPEED) { 184 case E1000_STATUS_PCIX_SPEED_66: 185 bus->speed = e1000_bus_speed_66; 186 break; 187 case E1000_STATUS_PCIX_SPEED_100: 188 bus->speed = e1000_bus_speed_100; 189 break; 190 case E1000_STATUS_PCIX_SPEED_133: 191 bus->speed = e1000_bus_speed_133; 192 break; 193 default: 194 bus->speed = e1000_bus_speed_reserved; 195 break; 196 } 197 } 198 199 /* Bus width */ 200 bus->width = (status & E1000_STATUS_BUS64) 201 ? e1000_bus_width_64 202 : e1000_bus_width_32; 203 204 /* Which PCI(-X) function? */ 205 mac->ops.set_lan_id(hw); 206 207 return ret_val; 208 } 209 210 /** 211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 212 * @hw: pointer to the HW structure 213 * 214 * Determines and stores the system bus information for a particular 215 * network interface. The following bus information is determined and stored: 216 * bus speed, bus width, type (PCIe), and PCIe function. 217 **/ 218 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 219 { 220 struct e1000_mac_info *mac = &hw->mac; 221 struct e1000_bus_info *bus = &hw->bus; 222 s32 ret_val; 223 u16 pcie_link_status; 224 225 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 226 227 bus->type = e1000_bus_type_pci_express; 228 bus->speed = e1000_bus_speed_2500; 229 230 ret_val = e1000_read_pcie_cap_reg(hw, 231 PCIE_LINK_STATUS, 232 &pcie_link_status); 233 if (ret_val) 234 bus->width = e1000_bus_width_unknown; 235 else 236 bus->width = (enum e1000_bus_width)((pcie_link_status & 237 PCIE_LINK_WIDTH_MASK) >> 238 PCIE_LINK_WIDTH_SHIFT); 239 240 mac->ops.set_lan_id(hw); 241 242 return E1000_SUCCESS; 243 } 244 245 /** 246 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 247 * 248 * @hw: pointer to the HW structure 249 * 250 * Determines the LAN function id by reading memory-mapped registers 251 * and swaps the port value if requested. 252 **/ 253 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 254 { 255 struct e1000_bus_info *bus = &hw->bus; 256 u32 reg; 257 258 /* 259 * The status register reports the correct function number 260 * for the device regardless of function swap state. 261 */ 262 reg = E1000_READ_REG(hw, E1000_STATUS); 263 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 264 } 265 266 /** 267 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 268 * @hw: pointer to the HW structure 269 * 270 * Determines the LAN function id by reading PCI config space. 271 **/ 272 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 273 { 274 struct e1000_bus_info *bus = &hw->bus; 275 u16 pci_header_type; 276 u32 status; 277 278 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 279 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 280 status = E1000_READ_REG(hw, E1000_STATUS); 281 bus->func = (status & E1000_STATUS_FUNC_MASK) 282 >> E1000_STATUS_FUNC_SHIFT; 283 } else { 284 bus->func = 0; 285 } 286 } 287 288 /** 289 * e1000_set_lan_id_single_port - Set LAN id for a single port device 290 * @hw: pointer to the HW structure 291 * 292 * Sets the LAN function id to zero for a single port device. 293 **/ 294 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 295 { 296 struct e1000_bus_info *bus = &hw->bus; 297 298 bus->func = 0; 299 } 300 301 /** 302 * e1000_clear_vfta_generic - Clear VLAN filter table 303 * @hw: pointer to the HW structure 304 * 305 * Clears the register array which contains the VLAN filter table by 306 * setting all the values to 0. 307 **/ 308 void e1000_clear_vfta_generic(struct e1000_hw *hw) 309 { 310 u32 offset; 311 312 DEBUGFUNC("e1000_clear_vfta_generic"); 313 314 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 315 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 316 E1000_WRITE_FLUSH(hw); 317 } 318 } 319 320 /** 321 * e1000_write_vfta_generic - Write value to VLAN filter table 322 * @hw: pointer to the HW structure 323 * @offset: register offset in VLAN filter table 324 * @value: register value written to VLAN filter table 325 * 326 * Writes value at the given offset in the register array which stores 327 * the VLAN filter table. 328 **/ 329 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 330 { 331 DEBUGFUNC("e1000_write_vfta_generic"); 332 333 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 334 E1000_WRITE_FLUSH(hw); 335 } 336 337 /** 338 * e1000_init_rx_addrs_generic - Initialize receive address's 339 * @hw: pointer to the HW structure 340 * @rar_count: receive address registers 341 * 342 * Setups the receive address registers by setting the base receive address 343 * register to the devices MAC address and clearing all the other receive 344 * address registers to 0. 345 **/ 346 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 347 { 348 u32 i; 349 u8 mac_addr[ETH_ADDR_LEN] = {0}; 350 351 DEBUGFUNC("e1000_init_rx_addrs_generic"); 352 353 /* Setup the receive address */ 354 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 355 356 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 357 358 /* Zero out the other (rar_entry_count - 1) receive addresses */ 359 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 360 for (i = 1; i < rar_count; i++) 361 hw->mac.ops.rar_set(hw, mac_addr, i); 362 } 363 364 /** 365 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 366 * @hw: pointer to the HW structure 367 * 368 * Checks the nvm for an alternate MAC address. An alternate MAC address 369 * can be setup by pre-boot software and must be treated like a permanent 370 * address and must override the actual permanent MAC address. If an 371 * alternate MAC address is found it is programmed into RAR0, replacing 372 * the permanent address that was installed into RAR0 by the Si on reset. 373 * This function will return SUCCESS unless it encounters an error while 374 * reading the EEPROM. 375 **/ 376 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 377 { 378 u32 i; 379 s32 ret_val = E1000_SUCCESS; 380 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 381 u8 alt_mac_addr[ETH_ADDR_LEN]; 382 383 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 384 385 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 386 &nvm_alt_mac_addr_offset); 387 if (ret_val) { 388 DEBUGOUT("NVM Read Error\n"); 389 goto out; 390 } 391 392 if (nvm_alt_mac_addr_offset == 0xFFFF) { 393 /* There is no Alternate MAC Address */ 394 goto out; 395 } 396 397 if (hw->bus.func == E1000_FUNC_1) 398 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 399 if (hw->bus.func == E1000_FUNC_2) 400 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 401 402 if (hw->bus.func == E1000_FUNC_3) 403 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 404 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 405 offset = nvm_alt_mac_addr_offset + (i >> 1); 406 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 407 if (ret_val) { 408 DEBUGOUT("NVM Read Error\n"); 409 goto out; 410 } 411 412 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 413 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 414 } 415 416 /* if multicast bit is set, the alternate address will not be used */ 417 if (alt_mac_addr[0] & 0x01) { 418 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 419 goto out; 420 } 421 422 /* 423 * We have a valid alternate MAC address, and we want to treat it the 424 * same as the normal permanent MAC address stored by the HW into the 425 * RAR. Do this by mapping this address into RAR0. 426 */ 427 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 428 429 out: 430 return ret_val; 431 } 432 433 /** 434 * e1000_rar_set_generic - Set receive address register 435 * @hw: pointer to the HW structure 436 * @addr: pointer to the receive address 437 * @index: receive address array register 438 * 439 * Sets the receive address array register at index to the address passed 440 * in by addr. 441 **/ 442 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 443 { 444 u32 rar_low, rar_high; 445 446 DEBUGFUNC("e1000_rar_set_generic"); 447 448 /* 449 * HW expects these in little endian so we reverse the byte order 450 * from network order (big endian) to little endian 451 */ 452 rar_low = ((u32) addr[0] | 453 ((u32) addr[1] << 8) | 454 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 455 456 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 457 458 /* If MAC address zero, no need to set the AV bit */ 459 if (rar_low || rar_high) 460 rar_high |= E1000_RAH_AV; 461 462 /* 463 * Some bridges will combine consecutive 32-bit writes into 464 * a single burst write, which will malfunction on some parts. 465 * The flushes avoid this. 466 */ 467 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 468 E1000_WRITE_FLUSH(hw); 469 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 470 E1000_WRITE_FLUSH(hw); 471 } 472 473 /** 474 * e1000_update_mc_addr_list_generic - Update Multicast addresses 475 * @hw: pointer to the HW structure 476 * @mc_addr_list: array of multicast addresses to program 477 * @mc_addr_count: number of multicast addresses to program 478 * 479 * Updates entire Multicast Table Array. 480 * The caller must have a packed mc_addr_list of multicast addresses. 481 **/ 482 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 483 u8 *mc_addr_list, u32 mc_addr_count) 484 { 485 u32 hash_value, hash_bit, hash_reg; 486 int i; 487 488 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 489 490 /* clear mta_shadow */ 491 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 492 493 /* update mta_shadow from mc_addr_list */ 494 for (i = 0; (u32) i < mc_addr_count; i++) { 495 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 496 497 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 498 hash_bit = hash_value & 0x1F; 499 500 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 501 mc_addr_list += (ETH_ADDR_LEN); 502 } 503 504 /* replace the entire MTA table */ 505 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 506 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 507 E1000_WRITE_FLUSH(hw); 508 } 509 510 /** 511 * e1000_hash_mc_addr_generic - Generate a multicast hash value 512 * @hw: pointer to the HW structure 513 * @mc_addr: pointer to a multicast address 514 * 515 * Generates a multicast address hash value which is used to determine 516 * the multicast filter table array address and new table value. 517 **/ 518 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 519 { 520 u32 hash_value, hash_mask; 521 u8 bit_shift = 0; 522 523 DEBUGFUNC("e1000_hash_mc_addr_generic"); 524 525 /* Register count multiplied by bits per register */ 526 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 527 528 /* 529 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 530 * where 0xFF would still fall within the hash mask. 531 */ 532 while (hash_mask >> bit_shift != 0xFF) 533 bit_shift++; 534 535 /* 536 * The portion of the address that is used for the hash table 537 * is determined by the mc_filter_type setting. 538 * The algorithm is such that there is a total of 8 bits of shifting. 539 * The bit_shift for a mc_filter_type of 0 represents the number of 540 * left-shifts where the MSB of mc_addr[5] would still fall within 541 * the hash_mask. Case 0 does this exactly. Since there are a total 542 * of 8 bits of shifting, then mc_addr[4] will shift right the 543 * remaining number of bits. Thus 8 - bit_shift. The rest of the 544 * cases are a variation of this algorithm...essentially raising the 545 * number of bits to shift mc_addr[5] left, while still keeping the 546 * 8-bit shifting total. 547 * 548 * For example, given the following Destination MAC Address and an 549 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 550 * we can see that the bit_shift for case 0 is 4. These are the hash 551 * values resulting from each mc_filter_type... 552 * [0] [1] [2] [3] [4] [5] 553 * 01 AA 00 12 34 56 554 * LSB MSB 555 * 556 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 557 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 558 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 559 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 560 */ 561 switch (hw->mac.mc_filter_type) { 562 default: 563 case 0: 564 break; 565 case 1: 566 bit_shift += 1; 567 break; 568 case 2: 569 bit_shift += 2; 570 break; 571 case 3: 572 bit_shift += 4; 573 break; 574 } 575 576 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 577 (((u16) mc_addr[5]) << bit_shift))); 578 579 return hash_value; 580 } 581 582 /** 583 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 584 * @hw: pointer to the HW structure 585 * 586 * In certain situations, a system BIOS may report that the PCIx maximum 587 * memory read byte count (MMRBC) value is higher than than the actual 588 * value. We check the PCIx command register with the current PCIx status 589 * register. 590 **/ 591 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 592 { 593 u16 cmd_mmrbc; 594 u16 pcix_cmd; 595 u16 pcix_stat_hi_word; 596 u16 stat_mmrbc; 597 598 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 599 600 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 601 if (hw->bus.type != e1000_bus_type_pcix) 602 return; 603 604 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 605 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 606 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 607 PCIX_COMMAND_MMRBC_SHIFT; 608 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 609 PCIX_STATUS_HI_MMRBC_SHIFT; 610 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 611 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 612 if (cmd_mmrbc > stat_mmrbc) { 613 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 614 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 615 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 616 } 617 } 618 619 /** 620 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 621 * @hw: pointer to the HW structure 622 * 623 * Clears the base hardware counters by reading the counter registers. 624 **/ 625 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 626 { 627 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 628 629 E1000_READ_REG(hw, E1000_CRCERRS); 630 E1000_READ_REG(hw, E1000_SYMERRS); 631 E1000_READ_REG(hw, E1000_MPC); 632 E1000_READ_REG(hw, E1000_SCC); 633 E1000_READ_REG(hw, E1000_ECOL); 634 E1000_READ_REG(hw, E1000_MCC); 635 E1000_READ_REG(hw, E1000_LATECOL); 636 E1000_READ_REG(hw, E1000_COLC); 637 E1000_READ_REG(hw, E1000_DC); 638 E1000_READ_REG(hw, E1000_SEC); 639 E1000_READ_REG(hw, E1000_RLEC); 640 E1000_READ_REG(hw, E1000_XONRXC); 641 E1000_READ_REG(hw, E1000_XONTXC); 642 E1000_READ_REG(hw, E1000_XOFFRXC); 643 E1000_READ_REG(hw, E1000_XOFFTXC); 644 E1000_READ_REG(hw, E1000_FCRUC); 645 E1000_READ_REG(hw, E1000_GPRC); 646 E1000_READ_REG(hw, E1000_BPRC); 647 E1000_READ_REG(hw, E1000_MPRC); 648 E1000_READ_REG(hw, E1000_GPTC); 649 E1000_READ_REG(hw, E1000_GORCL); 650 E1000_READ_REG(hw, E1000_GORCH); 651 E1000_READ_REG(hw, E1000_GOTCL); 652 E1000_READ_REG(hw, E1000_GOTCH); 653 E1000_READ_REG(hw, E1000_RNBC); 654 E1000_READ_REG(hw, E1000_RUC); 655 E1000_READ_REG(hw, E1000_RFC); 656 E1000_READ_REG(hw, E1000_ROC); 657 E1000_READ_REG(hw, E1000_RJC); 658 E1000_READ_REG(hw, E1000_TORL); 659 E1000_READ_REG(hw, E1000_TORH); 660 E1000_READ_REG(hw, E1000_TOTL); 661 E1000_READ_REG(hw, E1000_TOTH); 662 E1000_READ_REG(hw, E1000_TPR); 663 E1000_READ_REG(hw, E1000_TPT); 664 E1000_READ_REG(hw, E1000_MPTC); 665 E1000_READ_REG(hw, E1000_BPTC); 666 } 667 668 /** 669 * e1000_check_for_copper_link_generic - Check for link (Copper) 670 * @hw: pointer to the HW structure 671 * 672 * Checks to see of the link status of the hardware has changed. If a 673 * change in link status has been detected, then we read the PHY registers 674 * to get the current speed/duplex if link exists. 675 **/ 676 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 677 { 678 struct e1000_mac_info *mac = &hw->mac; 679 s32 ret_val; 680 bool link; 681 682 DEBUGFUNC("e1000_check_for_copper_link"); 683 684 /* 685 * We only want to go out to the PHY registers to see if Auto-Neg 686 * has completed and/or if our link status has changed. The 687 * get_link_status flag is set upon receiving a Link Status 688 * Change or Rx Sequence Error interrupt. 689 */ 690 if (!mac->get_link_status) { 691 ret_val = E1000_SUCCESS; 692 goto out; 693 } 694 695 /* 696 * First we want to see if the MII Status Register reports 697 * link. If so, then we want to get the current speed/duplex 698 * of the PHY. 699 */ 700 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 701 if (ret_val) 702 goto out; 703 704 if (!link) 705 goto out; /* No link detected */ 706 707 mac->get_link_status = FALSE; 708 709 /* 710 * Check if there was DownShift, must be checked 711 * immediately after link-up 712 */ 713 e1000_check_downshift_generic(hw); 714 715 /* 716 * If we are forcing speed/duplex, then we simply return since 717 * we have already determined whether we have link or not. 718 */ 719 if (!mac->autoneg) { 720 ret_val = -E1000_ERR_CONFIG; 721 goto out; 722 } 723 724 /* 725 * Auto-Neg is enabled. Auto Speed Detection takes care 726 * of MAC speed/duplex configuration. So we only need to 727 * configure Collision Distance in the MAC. 728 */ 729 mac->ops.config_collision_dist(hw); 730 731 /* 732 * Configure Flow Control now that Auto-Neg has completed. 733 * First, we need to restore the desired flow control 734 * settings because we may have had to re-autoneg with a 735 * different link partner. 736 */ 737 ret_val = e1000_config_fc_after_link_up_generic(hw); 738 if (ret_val) 739 DEBUGOUT("Error configuring flow control\n"); 740 741 out: 742 return ret_val; 743 } 744 745 /** 746 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 747 * @hw: pointer to the HW structure 748 * 749 * Checks for link up on the hardware. If link is not up and we have 750 * a signal, then we need to force link up. 751 **/ 752 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 753 { 754 struct e1000_mac_info *mac = &hw->mac; 755 u32 rxcw; 756 u32 ctrl; 757 u32 status; 758 s32 ret_val = E1000_SUCCESS; 759 760 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 761 762 ctrl = E1000_READ_REG(hw, E1000_CTRL); 763 status = E1000_READ_REG(hw, E1000_STATUS); 764 rxcw = E1000_READ_REG(hw, E1000_RXCW); 765 766 /* 767 * If we don't have link (auto-negotiation failed or link partner 768 * cannot auto-negotiate), the cable is plugged in (we have signal), 769 * and our link partner is not trying to auto-negotiate with us (we 770 * are receiving idles or data), we need to force link up. We also 771 * need to give auto-negotiation time to complete, in case the cable 772 * was just plugged in. The autoneg_failed flag does this. 773 */ 774 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 775 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 776 (!(rxcw & E1000_RXCW_C))) { 777 if (mac->autoneg_failed == 0) { 778 mac->autoneg_failed = 1; 779 goto out; 780 } 781 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 782 783 /* Disable auto-negotiation in the TXCW register */ 784 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 785 786 /* Force link-up and also force full-duplex. */ 787 ctrl = E1000_READ_REG(hw, E1000_CTRL); 788 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 789 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 790 791 /* Configure Flow Control after forcing link up. */ 792 ret_val = e1000_config_fc_after_link_up_generic(hw); 793 if (ret_val) { 794 DEBUGOUT("Error configuring flow control\n"); 795 goto out; 796 } 797 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 798 /* 799 * If we are forcing link and we are receiving /C/ ordered 800 * sets, re-enable auto-negotiation in the TXCW register 801 * and disable forced link in the Device Control register 802 * in an attempt to auto-negotiate with our link partner. 803 */ 804 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 805 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 806 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 807 808 mac->serdes_has_link = TRUE; 809 } 810 811 out: 812 return ret_val; 813 } 814 815 /** 816 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 817 * @hw: pointer to the HW structure 818 * 819 * Checks for link up on the hardware. If link is not up and we have 820 * a signal, then we need to force link up. 821 **/ 822 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 823 { 824 struct e1000_mac_info *mac = &hw->mac; 825 u32 rxcw; 826 u32 ctrl; 827 u32 status; 828 s32 ret_val = E1000_SUCCESS; 829 830 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 831 832 ctrl = E1000_READ_REG(hw, E1000_CTRL); 833 status = E1000_READ_REG(hw, E1000_STATUS); 834 rxcw = E1000_READ_REG(hw, E1000_RXCW); 835 836 /* 837 * If we don't have link (auto-negotiation failed or link partner 838 * cannot auto-negotiate), and our link partner is not trying to 839 * auto-negotiate with us (we are receiving idles or data), 840 * we need to force link up. We also need to give auto-negotiation 841 * time to complete. 842 */ 843 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 844 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 845 if (mac->autoneg_failed == 0) { 846 mac->autoneg_failed = 1; 847 goto out; 848 } 849 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 850 851 /* Disable auto-negotiation in the TXCW register */ 852 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 853 854 /* Force link-up and also force full-duplex. */ 855 ctrl = E1000_READ_REG(hw, E1000_CTRL); 856 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 857 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 858 859 /* Configure Flow Control after forcing link up. */ 860 ret_val = e1000_config_fc_after_link_up_generic(hw); 861 if (ret_val) { 862 DEBUGOUT("Error configuring flow control\n"); 863 goto out; 864 } 865 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 866 /* 867 * If we are forcing link and we are receiving /C/ ordered 868 * sets, re-enable auto-negotiation in the TXCW register 869 * and disable forced link in the Device Control register 870 * in an attempt to auto-negotiate with our link partner. 871 */ 872 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 873 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 874 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 875 876 mac->serdes_has_link = TRUE; 877 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 878 /* 879 * If we force link for non-auto-negotiation switch, check 880 * link status based on MAC synchronization for internal 881 * serdes media type. 882 */ 883 /* SYNCH bit and IV bit are sticky. */ 884 usec_delay(10); 885 rxcw = E1000_READ_REG(hw, E1000_RXCW); 886 if (rxcw & E1000_RXCW_SYNCH) { 887 if (!(rxcw & E1000_RXCW_IV)) { 888 mac->serdes_has_link = TRUE; 889 DEBUGOUT("SERDES: Link up - forced.\n"); 890 } 891 } else { 892 mac->serdes_has_link = FALSE; 893 DEBUGOUT("SERDES: Link down - force failed.\n"); 894 } 895 } 896 897 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 898 status = E1000_READ_REG(hw, E1000_STATUS); 899 if (status & E1000_STATUS_LU) { 900 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 901 usec_delay(10); 902 rxcw = E1000_READ_REG(hw, E1000_RXCW); 903 if (rxcw & E1000_RXCW_SYNCH) { 904 if (!(rxcw & E1000_RXCW_IV)) { 905 mac->serdes_has_link = TRUE; 906 DEBUGOUT("SERDES: Link up - autoneg " 907 "completed sucessfully.\n"); 908 } else { 909 mac->serdes_has_link = FALSE; 910 DEBUGOUT("SERDES: Link down - invalid" 911 "codewords detected in autoneg.\n"); 912 } 913 } else { 914 mac->serdes_has_link = FALSE; 915 DEBUGOUT("SERDES: Link down - no sync.\n"); 916 } 917 } else { 918 mac->serdes_has_link = FALSE; 919 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 920 } 921 } 922 923 out: 924 return ret_val; 925 } 926 927 /** 928 * e1000_setup_link_generic - Setup flow control and link settings 929 * @hw: pointer to the HW structure 930 * 931 * Determines which flow control settings to use, then configures flow 932 * control. Calls the appropriate media-specific link configuration 933 * function. Assuming the adapter has a valid link partner, a valid link 934 * should be established. Assumes the hardware has previously been reset 935 * and the transmitter and receiver are not enabled. 936 **/ 937 s32 e1000_setup_link_generic(struct e1000_hw *hw) 938 { 939 s32 ret_val = E1000_SUCCESS; 940 941 DEBUGFUNC("e1000_setup_link_generic"); 942 943 /* 944 * In the case of the phy reset being blocked, we already have a link. 945 * We do not need to set it up again. 946 */ 947 if (e1000_check_reset_block(hw)) 948 goto out; 949 950 /* 951 * If requested flow control is set to default, set flow control 952 * based on the EEPROM flow control settings. 953 */ 954 if (hw->fc.requested_mode == e1000_fc_default) { 955 ret_val = e1000_set_default_fc_generic(hw); 956 if (ret_val) 957 goto out; 958 } 959 960 /* 961 * Save off the requested flow control mode for use later. Depending 962 * on the link partner's capabilities, we may or may not use this mode. 963 */ 964 hw->fc.current_mode = hw->fc.requested_mode; 965 966 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 967 hw->fc.current_mode); 968 969 /* Call the necessary media_type subroutine to configure the link. */ 970 ret_val = hw->mac.ops.setup_physical_interface(hw); 971 if (ret_val) 972 goto out; 973 974 /* 975 * Initialize the flow control address, type, and PAUSE timer 976 * registers to their default values. This is done even if flow 977 * control is disabled, because it does not hurt anything to 978 * initialize these registers. 979 */ 980 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 981 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 982 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 983 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 984 985 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 986 987 ret_val = e1000_set_fc_watermarks_generic(hw); 988 989 out: 990 return ret_val; 991 } 992 993 /** 994 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 995 * @hw: pointer to the HW structure 996 * 997 * Configures collision distance and flow control for fiber and serdes 998 * links. Upon successful setup, poll for link. 999 **/ 1000 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1001 { 1002 struct e1000_mac_info *mac = &hw->mac; 1003 u32 ctrl; 1004 s32 ret_val = E1000_SUCCESS; 1005 1006 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1007 1008 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1009 1010 /* Take the link out of reset */ 1011 ctrl &= ~E1000_CTRL_LRST; 1012 1013 mac->ops.config_collision_dist(hw); 1014 1015 ret_val = e1000_commit_fc_settings_generic(hw); 1016 if (ret_val) 1017 goto out; 1018 1019 /* 1020 * Since auto-negotiation is enabled, take the link out of reset (the 1021 * link will be in reset, because we previously reset the chip). This 1022 * will restart auto-negotiation. If auto-negotiation is successful 1023 * then the link-up status bit will be set and the flow control enable 1024 * bits (RFCE and TFCE) will be set according to their negotiated value. 1025 */ 1026 DEBUGOUT("Auto-negotiation enabled\n"); 1027 1028 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1029 E1000_WRITE_FLUSH(hw); 1030 msec_delay(1); 1031 1032 /* 1033 * For these adapters, the SW definable pin 1 is set when the optics 1034 * detect a signal. If we have a signal, then poll for a "Link-Up" 1035 * indication. 1036 */ 1037 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1038 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1039 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1040 } else { 1041 DEBUGOUT("No signal detected\n"); 1042 } 1043 1044 out: 1045 return ret_val; 1046 } 1047 1048 /** 1049 * e1000_config_collision_dist_generic - Configure collision distance 1050 * @hw: pointer to the HW structure 1051 * 1052 * Configures the collision distance to the default value and is used 1053 * during link setup. 1054 **/ 1055 void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1056 { 1057 u32 tctl; 1058 1059 DEBUGFUNC("e1000_config_collision_dist_generic"); 1060 1061 tctl = E1000_READ_REG(hw, E1000_TCTL); 1062 1063 tctl &= ~E1000_TCTL_COLD; 1064 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1065 1066 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1067 E1000_WRITE_FLUSH(hw); 1068 } 1069 1070 /** 1071 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1072 * @hw: pointer to the HW structure 1073 * 1074 * Polls for link up by reading the status register, if link fails to come 1075 * up with auto-negotiation, then the link is forced if a signal is detected. 1076 **/ 1077 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1078 { 1079 struct e1000_mac_info *mac = &hw->mac; 1080 u32 i, status; 1081 s32 ret_val = E1000_SUCCESS; 1082 1083 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1084 1085 /* 1086 * If we have a signal (the cable is plugged in, or assumed TRUE for 1087 * serdes media) then poll for a "Link-Up" indication in the Device 1088 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1089 * seconds (Auto-negotiation should complete in less than 500 1090 * milliseconds even if the other end is doing it in SW). 1091 */ 1092 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1093 msec_delay(10); 1094 status = E1000_READ_REG(hw, E1000_STATUS); 1095 if (status & E1000_STATUS_LU) 1096 break; 1097 } 1098 if (i == FIBER_LINK_UP_LIMIT) { 1099 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1100 mac->autoneg_failed = 1; 1101 /* 1102 * AutoNeg failed to achieve a link, so we'll call 1103 * mac->check_for_link. This routine will force the 1104 * link up if we detect a signal. This will allow us to 1105 * communicate with non-autonegotiating link partners. 1106 */ 1107 ret_val = mac->ops.check_for_link(hw); 1108 if (ret_val) { 1109 DEBUGOUT("Error while checking for link\n"); 1110 goto out; 1111 } 1112 mac->autoneg_failed = 0; 1113 } else { 1114 mac->autoneg_failed = 0; 1115 DEBUGOUT("Valid Link Found\n"); 1116 } 1117 1118 out: 1119 return ret_val; 1120 } 1121 1122 /** 1123 * e1000_commit_fc_settings_generic - Configure flow control 1124 * @hw: pointer to the HW structure 1125 * 1126 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1127 * base on the flow control settings in e1000_mac_info. 1128 **/ 1129 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1130 { 1131 struct e1000_mac_info *mac = &hw->mac; 1132 u32 txcw; 1133 s32 ret_val = E1000_SUCCESS; 1134 1135 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1136 1137 /* 1138 * Check for a software override of the flow control settings, and 1139 * setup the device accordingly. If auto-negotiation is enabled, then 1140 * software will have to set the "PAUSE" bits to the correct value in 1141 * the Transmit Config Word Register (TXCW) and re-start auto- 1142 * negotiation. However, if auto-negotiation is disabled, then 1143 * software will have to manually configure the two flow control enable 1144 * bits in the CTRL register. 1145 * 1146 * The possible values of the "fc" parameter are: 1147 * 0: Flow control is completely disabled 1148 * 1: Rx flow control is enabled (we can receive pause frames, 1149 * but not send pause frames). 1150 * 2: Tx flow control is enabled (we can send pause frames but we 1151 * do not support receiving pause frames). 1152 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1153 */ 1154 switch (hw->fc.current_mode) { 1155 case e1000_fc_none: 1156 /* Flow control completely disabled by a software over-ride. */ 1157 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1158 break; 1159 case e1000_fc_rx_pause: 1160 /* 1161 * Rx Flow control is enabled and Tx Flow control is disabled 1162 * by a software over-ride. Since there really isn't a way to 1163 * advertise that we are capable of Rx Pause ONLY, we will 1164 * advertise that we support both symmetric and asymmetric Rx 1165 * PAUSE. Later, we will disable the adapter's ability to send 1166 * PAUSE frames. 1167 */ 1168 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1169 break; 1170 case e1000_fc_tx_pause: 1171 /* 1172 * Tx Flow control is enabled, and Rx Flow control is disabled, 1173 * by a software over-ride. 1174 */ 1175 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1176 break; 1177 case e1000_fc_full: 1178 /* 1179 * Flow control (both Rx and Tx) is enabled by a software 1180 * over-ride. 1181 */ 1182 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1183 break; 1184 default: 1185 DEBUGOUT("Flow control param set incorrectly\n"); 1186 ret_val = -E1000_ERR_CONFIG; 1187 goto out; 1188 break; 1189 } 1190 1191 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1192 mac->txcw = txcw; 1193 1194 out: 1195 return ret_val; 1196 } 1197 1198 /** 1199 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1200 * @hw: pointer to the HW structure 1201 * 1202 * Sets the flow control high/low threshold (watermark) registers. If 1203 * flow control XON frame transmission is enabled, then set XON frame 1204 * transmission as well. 1205 **/ 1206 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1207 { 1208 u32 fcrtl = 0, fcrth = 0; 1209 1210 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1211 1212 /* 1213 * Set the flow control receive threshold registers. Normally, 1214 * these registers will be set to a default threshold that may be 1215 * adjusted later by the driver's runtime code. However, if the 1216 * ability to transmit pause frames is not enabled, then these 1217 * registers will be set to 0. 1218 */ 1219 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1220 /* 1221 * We need to set up the Receive Threshold high and low water 1222 * marks as well as (optionally) enabling the transmission of 1223 * XON frames. 1224 */ 1225 fcrtl = hw->fc.low_water; 1226 if (hw->fc.send_xon) 1227 fcrtl |= E1000_FCRTL_XONE; 1228 1229 fcrth = hw->fc.high_water; 1230 } 1231 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1232 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1233 1234 return E1000_SUCCESS; 1235 } 1236 1237 /** 1238 * e1000_set_default_fc_generic - Set flow control default values 1239 * @hw: pointer to the HW structure 1240 * 1241 * Read the EEPROM for the default values for flow control and store the 1242 * values. 1243 **/ 1244 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1245 { 1246 s32 ret_val = E1000_SUCCESS; 1247 u16 nvm_data; 1248 1249 DEBUGFUNC("e1000_set_default_fc_generic"); 1250 1251 /* 1252 * Read and store word 0x0F of the EEPROM. This word contains bits 1253 * that determine the hardware's default PAUSE (flow control) mode, 1254 * a bit that determines whether the HW defaults to enabling or 1255 * disabling auto-negotiation, and the direction of the 1256 * SW defined pins. If there is no SW over-ride of the flow 1257 * control setting, then the variable hw->fc will 1258 * be initialized based on a value in the EEPROM. 1259 */ 1260 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1261 1262 if (ret_val) { 1263 DEBUGOUT("NVM Read Error\n"); 1264 goto out; 1265 } 1266 1267 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1268 hw->fc.requested_mode = e1000_fc_none; 1269 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1270 NVM_WORD0F_ASM_DIR) 1271 hw->fc.requested_mode = e1000_fc_tx_pause; 1272 else 1273 hw->fc.requested_mode = e1000_fc_full; 1274 1275 out: 1276 return ret_val; 1277 } 1278 1279 /** 1280 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1281 * @hw: pointer to the HW structure 1282 * 1283 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1284 * device control register to reflect the adapter settings. TFCE and RFCE 1285 * need to be explicitly set by software when a copper PHY is used because 1286 * autonegotiation is managed by the PHY rather than the MAC. Software must 1287 * also configure these bits when link is forced on a fiber connection. 1288 **/ 1289 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1290 { 1291 u32 ctrl; 1292 s32 ret_val = E1000_SUCCESS; 1293 1294 DEBUGFUNC("e1000_force_mac_fc_generic"); 1295 1296 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1297 1298 /* 1299 * Because we didn't get link via the internal auto-negotiation 1300 * mechanism (we either forced link or we got link via PHY 1301 * auto-neg), we have to manually enable/disable transmit an 1302 * receive flow control. 1303 * 1304 * The "Case" statement below enables/disable flow control 1305 * according to the "hw->fc.current_mode" parameter. 1306 * 1307 * The possible values of the "fc" parameter are: 1308 * 0: Flow control is completely disabled 1309 * 1: Rx flow control is enabled (we can receive pause 1310 * frames but not send pause frames). 1311 * 2: Tx flow control is enabled (we can send pause frames 1312 * frames but we do not receive pause frames). 1313 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1314 * other: No other values should be possible at this point. 1315 */ 1316 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1317 1318 switch (hw->fc.current_mode) { 1319 case e1000_fc_none: 1320 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1321 break; 1322 case e1000_fc_rx_pause: 1323 ctrl &= (~E1000_CTRL_TFCE); 1324 ctrl |= E1000_CTRL_RFCE; 1325 break; 1326 case e1000_fc_tx_pause: 1327 ctrl &= (~E1000_CTRL_RFCE); 1328 ctrl |= E1000_CTRL_TFCE; 1329 break; 1330 case e1000_fc_full: 1331 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1332 break; 1333 default: 1334 DEBUGOUT("Flow control param set incorrectly\n"); 1335 ret_val = -E1000_ERR_CONFIG; 1336 goto out; 1337 } 1338 1339 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1340 1341 out: 1342 return ret_val; 1343 } 1344 1345 /** 1346 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1347 * @hw: pointer to the HW structure 1348 * 1349 * Checks the status of auto-negotiation after link up to ensure that the 1350 * speed and duplex were not forced. If the link needed to be forced, then 1351 * flow control needs to be forced also. If auto-negotiation is enabled 1352 * and did not fail, then we configure flow control based on our link 1353 * partner. 1354 **/ 1355 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1356 { 1357 struct e1000_mac_info *mac = &hw->mac; 1358 s32 ret_val = E1000_SUCCESS; 1359 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1360 u16 speed, duplex; 1361 1362 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1363 1364 /* 1365 * Check for the case where we have fiber media and auto-neg failed 1366 * so we had to force link. In this case, we need to force the 1367 * configuration of the MAC to match the "fc" parameter. 1368 */ 1369 if (mac->autoneg_failed) { 1370 if (hw->phy.media_type == e1000_media_type_fiber || 1371 hw->phy.media_type == e1000_media_type_internal_serdes) 1372 ret_val = e1000_force_mac_fc_generic(hw); 1373 } else { 1374 if (hw->phy.media_type == e1000_media_type_copper) 1375 ret_val = e1000_force_mac_fc_generic(hw); 1376 } 1377 1378 if (ret_val) { 1379 DEBUGOUT("Error forcing flow control settings\n"); 1380 goto out; 1381 } 1382 1383 /* 1384 * Check for the case where we have copper media and auto-neg is 1385 * enabled. In this case, we need to check and see if Auto-Neg 1386 * has completed, and if so, how the PHY and link partner has 1387 * flow control configured. 1388 */ 1389 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1390 /* 1391 * Read the MII Status Register and check to see if AutoNeg 1392 * has completed. We read this twice because this reg has 1393 * some "sticky" (latched) bits. 1394 */ 1395 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1396 if (ret_val) 1397 goto out; 1398 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1399 if (ret_val) 1400 goto out; 1401 1402 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1403 DEBUGOUT("Copper PHY and Auto Neg " 1404 "has not completed.\n"); 1405 goto out; 1406 } 1407 1408 /* 1409 * The AutoNeg process has completed, so we now need to 1410 * read both the Auto Negotiation Advertisement 1411 * Register (Address 4) and the Auto_Negotiation Base 1412 * Page Ability Register (Address 5) to determine how 1413 * flow control was negotiated. 1414 */ 1415 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1416 &mii_nway_adv_reg); 1417 if (ret_val) 1418 goto out; 1419 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1420 &mii_nway_lp_ability_reg); 1421 if (ret_val) 1422 goto out; 1423 1424 /* 1425 * Two bits in the Auto Negotiation Advertisement Register 1426 * (Address 4) and two bits in the Auto Negotiation Base 1427 * Page Ability Register (Address 5) determine flow control 1428 * for both the PHY and the link partner. The following 1429 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1430 * 1999, describes these PAUSE resolution bits and how flow 1431 * control is determined based upon these settings. 1432 * NOTE: DC = Don't Care 1433 * 1434 * LOCAL DEVICE | LINK PARTNER 1435 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1436 *-------|---------|-------|---------|-------------------- 1437 * 0 | 0 | DC | DC | e1000_fc_none 1438 * 0 | 1 | 0 | DC | e1000_fc_none 1439 * 0 | 1 | 1 | 0 | e1000_fc_none 1440 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1441 * 1 | 0 | 0 | DC | e1000_fc_none 1442 * 1 | DC | 1 | DC | e1000_fc_full 1443 * 1 | 1 | 0 | 0 | e1000_fc_none 1444 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1445 * 1446 * Are both PAUSE bits set to 1? If so, this implies 1447 * Symmetric Flow Control is enabled at both ends. The 1448 * ASM_DIR bits are irrelevant per the spec. 1449 * 1450 * For Symmetric Flow Control: 1451 * 1452 * LOCAL DEVICE | LINK PARTNER 1453 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1454 *-------|---------|-------|---------|-------------------- 1455 * 1 | DC | 1 | DC | E1000_fc_full 1456 * 1457 */ 1458 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1459 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1460 /* 1461 * Now we need to check if the user selected Rx ONLY 1462 * of pause frames. In this case, we had to advertise 1463 * FULL flow control because we could not advertise Rx 1464 * ONLY. Hence, we must now check to see if we need to 1465 * turn OFF the TRANSMISSION of PAUSE frames. 1466 */ 1467 if (hw->fc.requested_mode == e1000_fc_full) { 1468 hw->fc.current_mode = e1000_fc_full; 1469 DEBUGOUT("Flow Control = FULL.\r\n"); 1470 } else { 1471 hw->fc.current_mode = e1000_fc_rx_pause; 1472 DEBUGOUT("Flow Control = " 1473 "Rx PAUSE frames only.\r\n"); 1474 } 1475 } 1476 /* 1477 * For receiving PAUSE frames ONLY. 1478 * 1479 * LOCAL DEVICE | LINK PARTNER 1480 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1481 *-------|---------|-------|---------|-------------------- 1482 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1483 */ 1484 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1485 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1486 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1487 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1488 hw->fc.current_mode = e1000_fc_tx_pause; 1489 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); 1490 } 1491 /* 1492 * For transmitting PAUSE frames ONLY. 1493 * 1494 * LOCAL DEVICE | LINK PARTNER 1495 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1496 *-------|---------|-------|---------|-------------------- 1497 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1498 */ 1499 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1500 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1501 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1502 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1503 hw->fc.current_mode = e1000_fc_rx_pause; 1504 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); 1505 } else { 1506 /* 1507 * Per the IEEE spec, at this point flow control 1508 * should be disabled. 1509 */ 1510 hw->fc.current_mode = e1000_fc_none; 1511 DEBUGOUT("Flow Control = NONE.\r\n"); 1512 } 1513 1514 /* 1515 * Now we need to do one last check... If we auto- 1516 * negotiated to HALF DUPLEX, flow control should not be 1517 * enabled per IEEE 802.3 spec. 1518 */ 1519 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1520 if (ret_val) { 1521 DEBUGOUT("Error getting link speed and duplex\n"); 1522 goto out; 1523 } 1524 1525 if (duplex == HALF_DUPLEX) 1526 hw->fc.current_mode = e1000_fc_none; 1527 1528 /* 1529 * Now we call a subroutine to actually force the MAC 1530 * controller to use the correct flow control settings. 1531 */ 1532 ret_val = e1000_force_mac_fc_generic(hw); 1533 if (ret_val) { 1534 DEBUGOUT("Error forcing flow control settings\n"); 1535 goto out; 1536 } 1537 } 1538 1539 out: 1540 return ret_val; 1541 } 1542 1543 /** 1544 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1545 * @hw: pointer to the HW structure 1546 * @speed: stores the current speed 1547 * @duplex: stores the current duplex 1548 * 1549 * Read the status register for the current speed/duplex and store the current 1550 * speed and duplex for copper connections. 1551 **/ 1552 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1553 u16 *duplex) 1554 { 1555 u32 status; 1556 1557 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1558 1559 status = E1000_READ_REG(hw, E1000_STATUS); 1560 if (status & E1000_STATUS_SPEED_1000) { 1561 *speed = SPEED_1000; 1562 DEBUGOUT("1000 Mbs, "); 1563 } else if (status & E1000_STATUS_SPEED_100) { 1564 *speed = SPEED_100; 1565 DEBUGOUT("100 Mbs, "); 1566 } else { 1567 *speed = SPEED_10; 1568 DEBUGOUT("10 Mbs, "); 1569 } 1570 1571 if (status & E1000_STATUS_FD) { 1572 *duplex = FULL_DUPLEX; 1573 DEBUGOUT("Full Duplex\n"); 1574 } else { 1575 *duplex = HALF_DUPLEX; 1576 DEBUGOUT("Half Duplex\n"); 1577 } 1578 1579 return E1000_SUCCESS; 1580 } 1581 1582 /** 1583 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1584 * @hw: pointer to the HW structure 1585 * @speed: stores the current speed 1586 * @duplex: stores the current duplex 1587 * 1588 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1589 * for fiber/serdes links. 1590 **/ 1591 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1592 u16 *speed, u16 *duplex) 1593 { 1594 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1595 1596 *speed = SPEED_1000; 1597 *duplex = FULL_DUPLEX; 1598 1599 return E1000_SUCCESS; 1600 } 1601 1602 /** 1603 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1604 * @hw: pointer to the HW structure 1605 * 1606 * Acquire the HW semaphore to access the PHY or NVM 1607 **/ 1608 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1609 { 1610 u32 swsm; 1611 s32 ret_val = E1000_SUCCESS; 1612 s32 timeout = hw->nvm.word_size + 1; 1613 s32 i = 0; 1614 1615 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1616 1617 /* Get the SW semaphore */ 1618 while (i < timeout) { 1619 swsm = E1000_READ_REG(hw, E1000_SWSM); 1620 if (!(swsm & E1000_SWSM_SMBI)) 1621 break; 1622 1623 usec_delay(50); 1624 i++; 1625 } 1626 1627 if (i == timeout) { 1628 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1629 ret_val = -E1000_ERR_NVM; 1630 goto out; 1631 } 1632 1633 /* Get the FW semaphore. */ 1634 for (i = 0; i < timeout; i++) { 1635 swsm = E1000_READ_REG(hw, E1000_SWSM); 1636 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1637 1638 /* Semaphore acquired if bit latched */ 1639 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1640 break; 1641 1642 usec_delay(50); 1643 } 1644 1645 if (i == timeout) { 1646 /* Release semaphores */ 1647 e1000_put_hw_semaphore_generic(hw); 1648 DEBUGOUT("Driver can't access the NVM\n"); 1649 ret_val = -E1000_ERR_NVM; 1650 goto out; 1651 } 1652 1653 out: 1654 return ret_val; 1655 } 1656 1657 /** 1658 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1659 * @hw: pointer to the HW structure 1660 * 1661 * Release hardware semaphore used to access the PHY or NVM 1662 **/ 1663 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1664 { 1665 u32 swsm; 1666 1667 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1668 1669 swsm = E1000_READ_REG(hw, E1000_SWSM); 1670 1671 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1672 1673 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1674 } 1675 1676 /** 1677 * e1000_get_auto_rd_done_generic - Check for auto read completion 1678 * @hw: pointer to the HW structure 1679 * 1680 * Check EEPROM for Auto Read done bit. 1681 **/ 1682 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1683 { 1684 s32 i = 0; 1685 s32 ret_val = E1000_SUCCESS; 1686 1687 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1688 1689 while (i < AUTO_READ_DONE_TIMEOUT) { 1690 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1691 break; 1692 msec_delay(1); 1693 i++; 1694 } 1695 1696 if (i == AUTO_READ_DONE_TIMEOUT) { 1697 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1698 ret_val = -E1000_ERR_RESET; 1699 goto out; 1700 } 1701 1702 out: 1703 return ret_val; 1704 } 1705 1706 /** 1707 * e1000_valid_led_default_generic - Verify a valid default LED config 1708 * @hw: pointer to the HW structure 1709 * @data: pointer to the NVM (EEPROM) 1710 * 1711 * Read the EEPROM for the current default LED configuration. If the 1712 * LED configuration is not valid, set to a valid LED configuration. 1713 **/ 1714 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1715 { 1716 s32 ret_val; 1717 1718 DEBUGFUNC("e1000_valid_led_default_generic"); 1719 1720 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1721 if (ret_val) { 1722 DEBUGOUT("NVM Read Error\n"); 1723 goto out; 1724 } 1725 1726 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1727 *data = ID_LED_DEFAULT; 1728 1729 out: 1730 return ret_val; 1731 } 1732 1733 /** 1734 * e1000_id_led_init_generic - 1735 * @hw: pointer to the HW structure 1736 * 1737 **/ 1738 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1739 { 1740 struct e1000_mac_info *mac = &hw->mac; 1741 s32 ret_val; 1742 const u32 ledctl_mask = 0x000000FF; 1743 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1744 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1745 u16 data, i, temp; 1746 const u16 led_mask = 0x0F; 1747 1748 DEBUGFUNC("e1000_id_led_init_generic"); 1749 1750 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1751 if (ret_val) 1752 goto out; 1753 1754 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1755 mac->ledctl_mode1 = mac->ledctl_default; 1756 mac->ledctl_mode2 = mac->ledctl_default; 1757 1758 for (i = 0; i < 4; i++) { 1759 temp = (data >> (i << 2)) & led_mask; 1760 switch (temp) { 1761 case ID_LED_ON1_DEF2: 1762 case ID_LED_ON1_ON2: 1763 case ID_LED_ON1_OFF2: 1764 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1765 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1766 break; 1767 case ID_LED_OFF1_DEF2: 1768 case ID_LED_OFF1_ON2: 1769 case ID_LED_OFF1_OFF2: 1770 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1771 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1772 break; 1773 default: 1774 /* Do nothing */ 1775 break; 1776 } 1777 switch (temp) { 1778 case ID_LED_DEF1_ON2: 1779 case ID_LED_ON1_ON2: 1780 case ID_LED_OFF1_ON2: 1781 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1782 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1783 break; 1784 case ID_LED_DEF1_OFF2: 1785 case ID_LED_ON1_OFF2: 1786 case ID_LED_OFF1_OFF2: 1787 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1788 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1789 break; 1790 default: 1791 /* Do nothing */ 1792 break; 1793 } 1794 } 1795 1796 out: 1797 return ret_val; 1798 } 1799 1800 /** 1801 * e1000_setup_led_generic - Configures SW controllable LED 1802 * @hw: pointer to the HW structure 1803 * 1804 * This prepares the SW controllable LED for use and saves the current state 1805 * of the LED so it can be later restored. 1806 **/ 1807 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1808 { 1809 u32 ledctl; 1810 s32 ret_val = E1000_SUCCESS; 1811 1812 DEBUGFUNC("e1000_setup_led_generic"); 1813 1814 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1815 ret_val = -E1000_ERR_CONFIG; 1816 goto out; 1817 } 1818 1819 if (hw->phy.media_type == e1000_media_type_fiber) { 1820 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1821 hw->mac.ledctl_default = ledctl; 1822 /* Turn off LED0 */ 1823 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1824 E1000_LEDCTL_LED0_BLINK | 1825 E1000_LEDCTL_LED0_MODE_MASK); 1826 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1827 E1000_LEDCTL_LED0_MODE_SHIFT); 1828 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1829 } else if (hw->phy.media_type == e1000_media_type_copper) { 1830 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1831 } 1832 1833 out: 1834 return ret_val; 1835 } 1836 1837 /** 1838 * e1000_cleanup_led_generic - Set LED config to default operation 1839 * @hw: pointer to the HW structure 1840 * 1841 * Remove the current LED configuration and set the LED configuration 1842 * to the default value, saved from the EEPROM. 1843 **/ 1844 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1845 { 1846 DEBUGFUNC("e1000_cleanup_led_generic"); 1847 1848 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1849 return E1000_SUCCESS; 1850 } 1851 1852 /** 1853 * e1000_blink_led_generic - Blink LED 1854 * @hw: pointer to the HW structure 1855 * 1856 * Blink the LEDs which are set to be on. 1857 **/ 1858 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1859 { 1860 u32 ledctl_blink = 0; 1861 u32 i; 1862 1863 DEBUGFUNC("e1000_blink_led_generic"); 1864 1865 if (hw->phy.media_type == e1000_media_type_fiber) { 1866 /* always blink LED0 for PCI-E fiber */ 1867 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1868 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1869 } else { 1870 /* 1871 * set the blink bit for each LED that's "on" (0x0E) 1872 * in ledctl_mode2 1873 */ 1874 ledctl_blink = hw->mac.ledctl_mode2; 1875 for (i = 0; i < 4; i++) 1876 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1877 E1000_LEDCTL_MODE_LED_ON) 1878 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1879 (i * 8)); 1880 } 1881 1882 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1883 1884 return E1000_SUCCESS; 1885 } 1886 1887 /** 1888 * e1000_led_on_generic - Turn LED on 1889 * @hw: pointer to the HW structure 1890 * 1891 * Turn LED on. 1892 **/ 1893 s32 e1000_led_on_generic(struct e1000_hw *hw) 1894 { 1895 u32 ctrl; 1896 1897 DEBUGFUNC("e1000_led_on_generic"); 1898 1899 switch (hw->phy.media_type) { 1900 case e1000_media_type_fiber: 1901 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1902 ctrl &= ~E1000_CTRL_SWDPIN0; 1903 ctrl |= E1000_CTRL_SWDPIO0; 1904 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1905 break; 1906 case e1000_media_type_copper: 1907 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1908 break; 1909 default: 1910 break; 1911 } 1912 1913 return E1000_SUCCESS; 1914 } 1915 1916 /** 1917 * e1000_led_off_generic - Turn LED off 1918 * @hw: pointer to the HW structure 1919 * 1920 * Turn LED off. 1921 **/ 1922 s32 e1000_led_off_generic(struct e1000_hw *hw) 1923 { 1924 u32 ctrl; 1925 1926 DEBUGFUNC("e1000_led_off_generic"); 1927 1928 switch (hw->phy.media_type) { 1929 case e1000_media_type_fiber: 1930 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1931 ctrl |= E1000_CTRL_SWDPIN0; 1932 ctrl |= E1000_CTRL_SWDPIO0; 1933 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1934 break; 1935 case e1000_media_type_copper: 1936 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1937 break; 1938 default: 1939 break; 1940 } 1941 1942 return E1000_SUCCESS; 1943 } 1944 1945 /** 1946 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1947 * @hw: pointer to the HW structure 1948 * @no_snoop: bitmap of snoop events 1949 * 1950 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1951 **/ 1952 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1953 { 1954 u32 gcr; 1955 1956 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1957 1958 if (hw->bus.type != e1000_bus_type_pci_express) 1959 goto out; 1960 1961 if (no_snoop) { 1962 gcr = E1000_READ_REG(hw, E1000_GCR); 1963 gcr &= ~(PCIE_NO_SNOOP_ALL); 1964 gcr |= no_snoop; 1965 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1966 } 1967 out: 1968 return; 1969 } 1970 1971 /** 1972 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1973 * @hw: pointer to the HW structure 1974 * 1975 * Returns E1000_SUCCESS if successful, else returns -10 1976 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1977 * the master requests to be disabled. 1978 * 1979 * Disables PCI-Express master access and verifies there are no pending 1980 * requests. 1981 **/ 1982 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1983 { 1984 u32 ctrl; 1985 s32 timeout = MASTER_DISABLE_TIMEOUT; 1986 s32 ret_val = E1000_SUCCESS; 1987 1988 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1989 1990 if (hw->bus.type != e1000_bus_type_pci_express) 1991 goto out; 1992 1993 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1994 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1995 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1996 1997 while (timeout) { 1998 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1999 E1000_STATUS_GIO_MASTER_ENABLE)) 2000 break; 2001 usec_delay(100); 2002 timeout--; 2003 } 2004 2005 if (!timeout) { 2006 DEBUGOUT("Master requests are pending.\n"); 2007 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2008 } 2009 2010 out: 2011 return ret_val; 2012 } 2013 2014 /** 2015 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2016 * @hw: pointer to the HW structure 2017 * 2018 * Reset the Adaptive Interframe Spacing throttle to default values. 2019 **/ 2020 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2021 { 2022 struct e1000_mac_info *mac = &hw->mac; 2023 2024 DEBUGFUNC("e1000_reset_adaptive_generic"); 2025 2026 if (!mac->adaptive_ifs) { 2027 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2028 goto out; 2029 } 2030 2031 mac->current_ifs_val = 0; 2032 mac->ifs_min_val = IFS_MIN; 2033 mac->ifs_max_val = IFS_MAX; 2034 mac->ifs_step_size = IFS_STEP; 2035 mac->ifs_ratio = IFS_RATIO; 2036 2037 mac->in_ifs_mode = FALSE; 2038 E1000_WRITE_REG(hw, E1000_AIT, 0); 2039 out: 2040 return; 2041 } 2042 2043 /** 2044 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2045 * @hw: pointer to the HW structure 2046 * 2047 * Update the Adaptive Interframe Spacing Throttle value based on the 2048 * time between transmitted packets and time between collisions. 2049 **/ 2050 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2051 { 2052 struct e1000_mac_info *mac = &hw->mac; 2053 2054 DEBUGFUNC("e1000_update_adaptive_generic"); 2055 2056 if (!mac->adaptive_ifs) { 2057 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2058 goto out; 2059 } 2060 2061 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2062 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2063 mac->in_ifs_mode = TRUE; 2064 if (mac->current_ifs_val < mac->ifs_max_val) { 2065 if (!mac->current_ifs_val) 2066 mac->current_ifs_val = mac->ifs_min_val; 2067 else 2068 mac->current_ifs_val += 2069 mac->ifs_step_size; 2070 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2071 } 2072 } 2073 } else { 2074 if (mac->in_ifs_mode && 2075 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2076 mac->current_ifs_val = 0; 2077 mac->in_ifs_mode = FALSE; 2078 E1000_WRITE_REG(hw, E1000_AIT, 0); 2079 } 2080 } 2081 out: 2082 return; 2083 } 2084 2085 /** 2086 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2087 * @hw: pointer to the HW structure 2088 * 2089 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2090 * set, which is forced to MDI mode only. 2091 **/ 2092 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2093 { 2094 s32 ret_val = E1000_SUCCESS; 2095 2096 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2097 2098 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2099 DEBUGOUT("Invalid MDI setting detected\n"); 2100 hw->phy.mdix = 1; 2101 ret_val = -E1000_ERR_CONFIG; 2102 goto out; 2103 } 2104 2105 out: 2106 return ret_val; 2107 } 2108 2109 /** 2110 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2111 * @hw: pointer to the HW structure 2112 * @reg: 32bit register offset such as E1000_SCTL 2113 * @offset: register offset to write to 2114 * @data: data to write at register offset 2115 * 2116 * Writes an address/data control type register. There are several of these 2117 * and they all have the format address << 8 | data and bit 31 is polled for 2118 * completion. 2119 **/ 2120 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2121 u32 offset, u8 data) 2122 { 2123 u32 i, regvalue = 0; 2124 s32 ret_val = E1000_SUCCESS; 2125 2126 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2127 2128 /* Set up the address and data */ 2129 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2130 E1000_WRITE_REG(hw, reg, regvalue); 2131 2132 /* Poll the ready bit to see if the MDI read completed */ 2133 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2134 usec_delay(5); 2135 regvalue = E1000_READ_REG(hw, reg); 2136 if (regvalue & E1000_GEN_CTL_READY) 2137 break; 2138 } 2139 if (!(regvalue & E1000_GEN_CTL_READY)) { 2140 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2141 ret_val = -E1000_ERR_PHY; 2142 goto out; 2143 } 2144 2145 out: 2146 return ret_val; 2147 } 2148