1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* e1000_ich8lan 36 * e1000_ich9lan 37 */ 38 39 #include "e1000_api.h" 40 41 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 42 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 43 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 44 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 45 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 46 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 47 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); 48 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 49 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw); 50 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 51 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 52 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 53 bool active); 54 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 55 bool active); 56 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 57 u16 words, u16 *data); 58 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 59 u16 words, u16 *data); 60 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 61 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 62 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 63 u16 *data); 64 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 65 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 66 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 67 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 68 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 69 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 70 u16 *speed, u16 *duplex); 71 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 72 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 73 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 74 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 75 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 76 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 77 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 78 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 79 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 80 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 81 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 82 u32 offset, u8* data); 83 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 84 u8 size, u16* data); 85 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 86 u32 offset, u16 *data); 87 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 88 u32 offset, u8 byte); 89 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 90 u32 offset, u8 data); 91 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 92 u8 size, u16 data); 93 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 94 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 95 96 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 97 /* Offset 04h HSFSTS */ 98 union ich8_hws_flash_status { 99 struct ich8_hsfsts { 100 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 101 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 102 u16 dael :1; /* bit 2 Direct Access error Log */ 103 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 104 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 105 u16 reserved1 :2; /* bit 13:6 Reserved */ 106 u16 reserved2 :6; /* bit 13:6 Reserved */ 107 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 108 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 109 } hsf_status; 110 u16 regval; 111 }; 112 113 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 114 /* Offset 06h FLCTL */ 115 union ich8_hws_flash_ctrl { 116 struct ich8_hsflctl { 117 u16 flcgo :1; /* 0 Flash Cycle Go */ 118 u16 flcycle :2; /* 2:1 Flash Cycle */ 119 u16 reserved :5; /* 7:3 Reserved */ 120 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 121 u16 flockdn :6; /* 15:10 Reserved */ 122 } hsf_ctrl; 123 u16 regval; 124 }; 125 126 /* ICH Flash Region Access Permissions */ 127 union ich8_hws_flash_regacc { 128 struct ich8_flracc { 129 u32 grra :8; /* 0:7 GbE region Read Access */ 130 u32 grwa :8; /* 8:15 GbE region Write Access */ 131 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 132 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 133 } hsf_flregacc; 134 u16 regval; 135 }; 136 137 struct e1000_shadow_ram { 138 u16 value; 139 bool modified; 140 }; 141 142 struct e1000_dev_spec_ich8lan { 143 bool kmrn_lock_loss_workaround_enabled; 144 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 145 }; 146 147 /** 148 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 149 * @hw: pointer to the HW structure 150 * 151 * Initialize family-specific PHY parameters and function pointers. 152 **/ 153 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 154 { 155 struct e1000_phy_info *phy = &hw->phy; 156 s32 ret_val = E1000_SUCCESS; 157 u16 i = 0; 158 159 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 160 161 phy->addr = 1; 162 phy->reset_delay_us = 100; 163 164 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 165 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 166 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 167 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan; 168 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 169 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 170 phy->ops.get_info = e1000_get_phy_info_ich8lan; 171 phy->ops.read_reg = e1000_read_phy_reg_igp; 172 phy->ops.release = e1000_release_swflag_ich8lan; 173 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 174 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 175 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 176 phy->ops.write_reg = e1000_write_phy_reg_igp; 177 phy->ops.power_up = e1000_power_up_phy_copper; 178 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 179 180 /* 181 * We may need to do this twice - once for IGP and if that fails, 182 * we'll set BM func pointers and try again 183 */ 184 ret_val = e1000_determine_phy_address(hw); 185 if (ret_val) { 186 phy->ops.write_reg = e1000_write_phy_reg_bm; 187 phy->ops.read_reg = e1000_read_phy_reg_bm; 188 ret_val = e1000_determine_phy_address(hw); 189 if (ret_val) { 190 DEBUGOUT("Cannot determine PHY address. Erroring out\n"); 191 goto out; 192 } 193 } 194 195 phy->id = 0; 196 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 197 (i++ < 100)) { 198 msec_delay(1); 199 ret_val = e1000_get_phy_id(hw); 200 if (ret_val) 201 goto out; 202 } 203 204 /* Verify phy id */ 205 switch (phy->id) { 206 case IGP03E1000_E_PHY_ID: 207 phy->type = e1000_phy_igp_3; 208 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 209 break; 210 case IFE_E_PHY_ID: 211 case IFE_PLUS_E_PHY_ID: 212 case IFE_C_E_PHY_ID: 213 phy->type = e1000_phy_ife; 214 phy->autoneg_mask = E1000_ALL_NOT_GIG; 215 break; 216 case BME1000_E_PHY_ID: 217 phy->type = e1000_phy_bm; 218 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 219 phy->ops.read_reg = e1000_read_phy_reg_bm; 220 phy->ops.write_reg = e1000_write_phy_reg_bm; 221 phy->ops.commit = e1000_phy_sw_reset_generic; 222 break; 223 default: 224 ret_val = -E1000_ERR_PHY; 225 goto out; 226 } 227 228 out: 229 return ret_val; 230 } 231 232 /** 233 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 234 * @hw: pointer to the HW structure 235 * 236 * Initialize family-specific NVM parameters and function 237 * pointers. 238 **/ 239 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 240 { 241 struct e1000_nvm_info *nvm = &hw->nvm; 242 struct e1000_dev_spec_ich8lan *dev_spec; 243 u32 gfpreg, sector_base_addr, sector_end_addr; 244 s32 ret_val = E1000_SUCCESS; 245 u16 i; 246 247 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 248 249 /* Can't read flash registers if the register set isn't mapped. */ 250 if (!hw->flash_address) { 251 DEBUGOUT("ERROR: Flash registers not mapped\n"); 252 ret_val = -E1000_ERR_CONFIG; 253 goto out; 254 } 255 256 nvm->type = e1000_nvm_flash_sw; 257 258 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 259 260 /* 261 * sector_X_addr is a "sector"-aligned address (4096 bytes) 262 * Add 1 to sector_end_addr since this sector is included in 263 * the overall size. 264 */ 265 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 266 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 267 268 /* flash_base_addr is byte-aligned */ 269 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 270 271 /* 272 * find total size of the NVM, then cut in half since the total 273 * size represents two separate NVM banks. 274 */ 275 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 276 << FLASH_SECTOR_ADDR_SHIFT; 277 nvm->flash_bank_size /= 2; 278 /* Adjust to word count */ 279 nvm->flash_bank_size /= sizeof(u16); 280 281 nvm->word_size = E1000_SHADOW_RAM_WORDS; 282 283 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 284 285 if (!dev_spec) { 286 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 287 ret_val = -E1000_ERR_CONFIG; 288 goto out; 289 } 290 291 /* Clear shadow ram */ 292 for (i = 0; i < nvm->word_size; i++) { 293 dev_spec->shadow_ram[i].modified = FALSE; 294 dev_spec->shadow_ram[i].value = 0xFFFF; 295 } 296 297 /* Function Pointers */ 298 nvm->ops.acquire = e1000_acquire_swflag_ich8lan; 299 nvm->ops.read = e1000_read_nvm_ich8lan; 300 nvm->ops.release = e1000_release_swflag_ich8lan; 301 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 302 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 303 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 304 nvm->ops.write = e1000_write_nvm_ich8lan; 305 306 out: 307 return ret_val; 308 } 309 310 /** 311 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 312 * @hw: pointer to the HW structure 313 * 314 * Initialize family-specific MAC parameters and function 315 * pointers. 316 **/ 317 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 318 { 319 struct e1000_mac_info *mac = &hw->mac; 320 s32 ret_val = E1000_SUCCESS; 321 322 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 323 324 /* Set media type function pointer */ 325 hw->phy.media_type = e1000_media_type_copper; 326 327 /* Set mta register count */ 328 mac->mta_reg_count = 32; 329 /* Set rar entry count */ 330 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 331 if (mac->type == e1000_ich8lan) 332 mac->rar_entry_count--; 333 /* Set if part includes ASF firmware */ 334 mac->asf_firmware_present = TRUE; 335 /* Set if manageability features are enabled. */ 336 mac->arc_subsystem_valid = TRUE; 337 338 /* Function pointers */ 339 340 /* bus type/speed/width */ 341 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 342 /* reset */ 343 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 344 /* hw initialization */ 345 mac->ops.init_hw = e1000_init_hw_ich8lan; 346 /* link setup */ 347 mac->ops.setup_link = e1000_setup_link_ich8lan; 348 /* physical interface setup */ 349 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 350 /* check for link */ 351 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 352 /* check management mode */ 353 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 354 /* link info */ 355 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 356 /* multicast address update */ 357 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 358 /* setting MTA */ 359 mac->ops.mta_set = e1000_mta_set_generic; 360 /* blink LED */ 361 mac->ops.blink_led = e1000_blink_led_generic; 362 /* setup LED */ 363 mac->ops.setup_led = e1000_setup_led_generic; 364 /* cleanup LED */ 365 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 366 /* turn on/off LED */ 367 mac->ops.led_on = e1000_led_on_ich8lan; 368 mac->ops.led_off = e1000_led_off_ich8lan; 369 /* remove device */ 370 mac->ops.remove_device = e1000_remove_device_generic; 371 /* clear hardware counters */ 372 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 373 374 hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan); 375 376 /* Device-specific structure allocation */ 377 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 378 if (ret_val) 379 goto out; 380 381 /* Enable PCS Lock-loss workaround for ICH8 */ 382 if (mac->type == e1000_ich8lan) 383 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 384 385 386 out: 387 return ret_val; 388 } 389 390 /** 391 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 392 * @hw: pointer to the HW structure 393 * 394 * Initialize family-specific function pointers for PHY, MAC, and NVM. 395 **/ 396 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 397 { 398 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 399 400 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 401 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 402 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 403 } 404 405 /** 406 * e1000_acquire_swflag_ich8lan - Acquire software control flag 407 * @hw: pointer to the HW structure 408 * 409 * Acquires the software control flag for performing NVM and PHY 410 * operations. This is a function pointer entry point only called by 411 * read/write routines for the PHY and NVM parts. 412 **/ 413 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 414 { 415 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 416 s32 ret_val = E1000_SUCCESS; 417 418 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 419 420 while (timeout) { 421 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 422 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 423 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 424 425 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 426 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 427 break; 428 msec_delay_irq(1); 429 timeout--; 430 } 431 432 if (!timeout) { 433 DEBUGOUT("FW or HW has locked the resource for too long.\n"); 434 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 435 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 436 ret_val = -E1000_ERR_CONFIG; 437 goto out; 438 } 439 440 out: 441 return ret_val; 442 } 443 444 /** 445 * e1000_release_swflag_ich8lan - Release software control flag 446 * @hw: pointer to the HW structure 447 * 448 * Releases the software control flag for performing NVM and PHY operations. 449 * This is a function pointer entry point only called by read/write 450 * routines for the PHY and NVM parts. 451 **/ 452 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 453 { 454 u32 extcnf_ctrl; 455 456 DEBUGFUNC("e1000_release_swflag_ich8lan"); 457 458 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 459 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 460 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 461 462 return; 463 } 464 465 /** 466 * e1000_check_mng_mode_ich8lan - Checks management mode 467 * @hw: pointer to the HW structure 468 * 469 * This checks if the adapter has manageability enabled. 470 * This is a function pointer entry point only called by read/write 471 * routines for the PHY and NVM parts. 472 **/ 473 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 474 { 475 u32 fwsm; 476 477 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 478 479 fwsm = E1000_READ_REG(hw, E1000_FWSM); 480 481 return ((fwsm & E1000_FWSM_MODE_MASK) == 482 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 483 } 484 485 /** 486 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 487 * @hw: pointer to the HW structure 488 * 489 * Checks if firmware is blocking the reset of the PHY. 490 * This is a function pointer entry point only called by 491 * reset routines. 492 **/ 493 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 494 { 495 u32 fwsm; 496 497 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 498 499 fwsm = E1000_READ_REG(hw, E1000_FWSM); 500 501 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 502 : E1000_BLK_PHY_RESET; 503 } 504 505 /** 506 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex 507 * @hw: pointer to the HW structure 508 * 509 * Forces the speed and duplex settings of the PHY. 510 * This is a function pointer entry point only called by 511 * PHY setup routines. 512 **/ 513 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) 514 { 515 struct e1000_phy_info *phy = &hw->phy; 516 s32 ret_val; 517 u16 data; 518 bool link; 519 520 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan"); 521 522 if (phy->type != e1000_phy_ife) { 523 ret_val = e1000_phy_force_speed_duplex_igp(hw); 524 goto out; 525 } 526 527 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 528 if (ret_val) 529 goto out; 530 531 e1000_phy_force_speed_duplex_setup(hw, &data); 532 533 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 534 if (ret_val) 535 goto out; 536 537 /* Disable MDI-X support for 10/100 */ 538 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 539 if (ret_val) 540 goto out; 541 542 data &= ~IFE_PMC_AUTO_MDIX; 543 data &= ~IFE_PMC_FORCE_MDIX; 544 545 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 546 if (ret_val) 547 goto out; 548 549 DEBUGOUT1("IFE PMC: %X\n", data); 550 551 usec_delay(1); 552 553 if (phy->autoneg_wait_to_complete) { 554 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 555 556 ret_val = e1000_phy_has_link_generic(hw, 557 PHY_FORCE_LIMIT, 558 100000, 559 &link); 560 if (ret_val) 561 goto out; 562 563 if (!link) { 564 DEBUGOUT("Link taking longer than expected.\n"); 565 } 566 567 /* Try once more */ 568 ret_val = e1000_phy_has_link_generic(hw, 569 PHY_FORCE_LIMIT, 570 100000, 571 &link); 572 if (ret_val) 573 goto out; 574 } 575 576 out: 577 return ret_val; 578 } 579 580 /** 581 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 582 * @hw: pointer to the HW structure 583 * 584 * Resets the PHY 585 * This is a function pointer entry point called by drivers 586 * or other shared routines. 587 **/ 588 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 589 { 590 struct e1000_phy_info *phy = &hw->phy; 591 struct e1000_nvm_info *nvm = &hw->nvm; 592 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 593 s32 ret_val; 594 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; 595 u16 word_addr, reg_data, reg_addr, phy_page = 0; 596 597 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 598 599 ret_val = e1000_phy_hw_reset_generic(hw); 600 if (ret_val) 601 goto out; 602 603 /* 604 * Initialize the PHY from the NVM on ICH platforms. This 605 * is needed due to an issue where the NVM configuration is 606 * not properly autoloaded after power transitions. 607 * Therefore, after each PHY reset, we will load the 608 * configuration data out of the NVM manually. 609 */ 610 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 611 /* Check if SW needs configure the PHY */ 612 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 613 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 614 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 615 else 616 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 617 618 data = E1000_READ_REG(hw, E1000_FEXTNVM); 619 if (!(data & sw_cfg_mask)) 620 goto out; 621 622 /* Wait for basic configuration completes before proceeding*/ 623 do { 624 data = E1000_READ_REG(hw, E1000_STATUS); 625 data &= E1000_STATUS_LAN_INIT_DONE; 626 usec_delay(100); 627 } while ((!data) && --loop); 628 629 /* 630 * If basic configuration is incomplete before the above loop 631 * count reaches 0, loading the configuration from NVM will 632 * leave the PHY in a bad state possibly resulting in no link. 633 */ 634 if (loop == 0) { 635 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 636 } 637 638 /* Clear the Init Done bit for the next init event */ 639 data = E1000_READ_REG(hw, E1000_STATUS); 640 data &= ~E1000_STATUS_LAN_INIT_DONE; 641 E1000_WRITE_REG(hw, E1000_STATUS, data); 642 643 /* 644 * Make sure HW does not configure LCD from PHY 645 * extended configuration before SW configuration 646 */ 647 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 648 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 649 goto out; 650 651 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 652 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 653 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 654 if (!cnf_size) 655 goto out; 656 657 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 658 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 659 660 /* 661 * Configure LCD from extended configuration 662 * region. 663 */ 664 665 /* cnf_base_addr is in DWORD */ 666 word_addr = (u16)(cnf_base_addr << 1); 667 668 for (i = 0; i < cnf_size; i++) { 669 ret_val = nvm->ops.read(hw, 670 (word_addr + i * 2), 671 1, 672 ®_data); 673 if (ret_val) 674 goto out; 675 676 ret_val = nvm->ops.read(hw, 677 (word_addr + i * 2 + 1), 678 1, 679 ®_addr); 680 if (ret_val) 681 goto out; 682 683 /* Save off the PHY page for future writes. */ 684 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 685 phy_page = reg_data; 686 continue; 687 } 688 689 reg_addr |= phy_page; 690 691 ret_val = phy->ops.write_reg(hw, 692 (u32)reg_addr, 693 reg_data); 694 if (ret_val) 695 goto out; 696 } 697 } 698 699 out: 700 return ret_val; 701 } 702 703 /** 704 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 705 * @hw: pointer to the HW structure 706 * 707 * Wrapper for calling the get_phy_info routines for the appropriate phy type. 708 * This is a function pointer entry point called by drivers 709 * or other shared routines. 710 **/ 711 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 712 { 713 s32 ret_val = -E1000_ERR_PHY_TYPE; 714 715 DEBUGFUNC("e1000_get_phy_info_ich8lan"); 716 717 switch (hw->phy.type) { 718 case e1000_phy_ife: 719 ret_val = e1000_get_phy_info_ife_ich8lan(hw); 720 break; 721 case e1000_phy_igp_3: 722 case e1000_phy_bm: 723 ret_val = e1000_get_phy_info_igp(hw); 724 break; 725 default: 726 break; 727 } 728 729 return ret_val; 730 } 731 732 /** 733 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 734 * @hw: pointer to the HW structure 735 * 736 * Populates "phy" structure with various feature states. 737 * This function is only called by other family-specific 738 * routines. 739 **/ 740 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 741 { 742 struct e1000_phy_info *phy = &hw->phy; 743 s32 ret_val; 744 u16 data; 745 bool link; 746 747 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 748 749 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 750 if (ret_val) 751 goto out; 752 753 if (!link) { 754 DEBUGOUT("Phy info is only valid if link is up\n"); 755 ret_val = -E1000_ERR_CONFIG; 756 goto out; 757 } 758 759 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 760 if (ret_val) 761 goto out; 762 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 763 ? FALSE : TRUE; 764 765 if (phy->polarity_correction) { 766 ret_val = e1000_check_polarity_ife_ich8lan(hw); 767 if (ret_val) 768 goto out; 769 } else { 770 /* Polarity is forced */ 771 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 772 ? e1000_rev_polarity_reversed 773 : e1000_rev_polarity_normal; 774 } 775 776 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 777 if (ret_val) 778 goto out; 779 780 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 781 782 /* The following parameters are undefined for 10/100 operation. */ 783 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 784 phy->local_rx = e1000_1000t_rx_status_undefined; 785 phy->remote_rx = e1000_1000t_rx_status_undefined; 786 787 out: 788 return ret_val; 789 } 790 791 /** 792 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY 793 * @hw: pointer to the HW structure 794 * 795 * Polarity is determined on the polarity reversal feature being enabled. 796 * This function is only called by other family-specific 797 * routines. 798 **/ 799 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) 800 { 801 struct e1000_phy_info *phy = &hw->phy; 802 s32 ret_val; 803 u16 phy_data, offset, mask; 804 805 DEBUGFUNC("e1000_check_polarity_ife_ich8lan"); 806 807 /* 808 * Polarity is determined based on the reversal feature 809 * being enabled. 810 */ 811 if (phy->polarity_correction) { 812 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 813 mask = IFE_PESC_POLARITY_REVERSED; 814 } else { 815 offset = IFE_PHY_SPECIAL_CONTROL; 816 mask = IFE_PSC_FORCE_POLARITY; 817 } 818 819 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 820 821 if (!ret_val) 822 phy->cable_polarity = (phy_data & mask) 823 ? e1000_rev_polarity_reversed 824 : e1000_rev_polarity_normal; 825 826 return ret_val; 827 } 828 829 /** 830 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 831 * @hw: pointer to the HW structure 832 * @active: TRUE to enable LPLU, FALSE to disable 833 * 834 * Sets the LPLU D0 state according to the active flag. When 835 * activating LPLU this function also disables smart speed 836 * and vice versa. LPLU will not be activated unless the 837 * device autonegotiation advertisement meets standards of 838 * either 10 or 10/100 or 10/100/1000 at all duplexes. 839 * This is a function pointer entry point only called by 840 * PHY setup routines. 841 **/ 842 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 843 bool active) 844 { 845 struct e1000_phy_info *phy = &hw->phy; 846 u32 phy_ctrl; 847 s32 ret_val = E1000_SUCCESS; 848 u16 data; 849 850 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 851 852 if (phy->type == e1000_phy_ife) 853 goto out; 854 855 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 856 857 if (active) { 858 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 859 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 860 861 /* 862 * Call gig speed drop workaround on LPLU before accessing 863 * any PHY registers 864 */ 865 if ((hw->mac.type == e1000_ich8lan) && 866 (hw->phy.type == e1000_phy_igp_3)) 867 e1000_gig_downshift_workaround_ich8lan(hw); 868 869 /* When LPLU is enabled, we should disable SmartSpeed */ 870 ret_val = phy->ops.read_reg(hw, 871 IGP01E1000_PHY_PORT_CONFIG, 872 &data); 873 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 874 ret_val = phy->ops.write_reg(hw, 875 IGP01E1000_PHY_PORT_CONFIG, 876 data); 877 if (ret_val) 878 goto out; 879 } else { 880 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 881 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 882 883 /* 884 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 885 * during Dx states where the power conservation is most 886 * important. During driver activity we should enable 887 * SmartSpeed, so performance is maintained. 888 */ 889 if (phy->smart_speed == e1000_smart_speed_on) { 890 ret_val = phy->ops.read_reg(hw, 891 IGP01E1000_PHY_PORT_CONFIG, 892 &data); 893 if (ret_val) 894 goto out; 895 896 data |= IGP01E1000_PSCFR_SMART_SPEED; 897 ret_val = phy->ops.write_reg(hw, 898 IGP01E1000_PHY_PORT_CONFIG, 899 data); 900 if (ret_val) 901 goto out; 902 } else if (phy->smart_speed == e1000_smart_speed_off) { 903 ret_val = phy->ops.read_reg(hw, 904 IGP01E1000_PHY_PORT_CONFIG, 905 &data); 906 if (ret_val) 907 goto out; 908 909 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 910 ret_val = phy->ops.write_reg(hw, 911 IGP01E1000_PHY_PORT_CONFIG, 912 data); 913 if (ret_val) 914 goto out; 915 } 916 } 917 918 out: 919 return ret_val; 920 } 921 922 /** 923 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 924 * @hw: pointer to the HW structure 925 * @active: TRUE to enable LPLU, FALSE to disable 926 * 927 * Sets the LPLU D3 state according to the active flag. When 928 * activating LPLU this function also disables smart speed 929 * and vice versa. LPLU will not be activated unless the 930 * device autonegotiation advertisement meets standards of 931 * either 10 or 10/100 or 10/100/1000 at all duplexes. 932 * This is a function pointer entry point only called by 933 * PHY setup routines. 934 **/ 935 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 936 bool active) 937 { 938 struct e1000_phy_info *phy = &hw->phy; 939 u32 phy_ctrl; 940 s32 ret_val = E1000_SUCCESS; 941 u16 data; 942 943 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 944 945 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 946 947 if (!active) { 948 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 949 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 950 /* 951 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 952 * during Dx states where the power conservation is most 953 * important. During driver activity we should enable 954 * SmartSpeed, so performance is maintained. 955 */ 956 if (phy->smart_speed == e1000_smart_speed_on) { 957 ret_val = phy->ops.read_reg(hw, 958 IGP01E1000_PHY_PORT_CONFIG, 959 &data); 960 if (ret_val) 961 goto out; 962 963 data |= IGP01E1000_PSCFR_SMART_SPEED; 964 ret_val = phy->ops.write_reg(hw, 965 IGP01E1000_PHY_PORT_CONFIG, 966 data); 967 if (ret_val) 968 goto out; 969 } else if (phy->smart_speed == e1000_smart_speed_off) { 970 ret_val = phy->ops.read_reg(hw, 971 IGP01E1000_PHY_PORT_CONFIG, 972 &data); 973 if (ret_val) 974 goto out; 975 976 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 977 ret_val = phy->ops.write_reg(hw, 978 IGP01E1000_PHY_PORT_CONFIG, 979 data); 980 if (ret_val) 981 goto out; 982 } 983 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 984 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 985 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 986 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 987 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 988 989 /* 990 * Call gig speed drop workaround on LPLU before accessing 991 * any PHY registers 992 */ 993 if ((hw->mac.type == e1000_ich8lan) && 994 (hw->phy.type == e1000_phy_igp_3)) 995 e1000_gig_downshift_workaround_ich8lan(hw); 996 997 /* When LPLU is enabled, we should disable SmartSpeed */ 998 ret_val = phy->ops.read_reg(hw, 999 IGP01E1000_PHY_PORT_CONFIG, 1000 &data); 1001 if (ret_val) 1002 goto out; 1003 1004 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1005 ret_val = phy->ops.write_reg(hw, 1006 IGP01E1000_PHY_PORT_CONFIG, 1007 data); 1008 } 1009 1010 out: 1011 return ret_val; 1012 } 1013 1014 /** 1015 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1016 * @hw: pointer to the HW structure 1017 * @bank: pointer to the variable that returns the active bank 1018 * 1019 * Reads signature byte from the NVM using the flash access registers. 1020 **/ 1021 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1022 { 1023 s32 ret_val = E1000_SUCCESS; 1024 struct e1000_nvm_info *nvm = &hw->nvm; 1025 /* flash bank size is in words */ 1026 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1027 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1028 u8 bank_high_byte = 0; 1029 1030 if (hw->mac.type != e1000_ich10lan) { 1031 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL) 1032 *bank = 1; 1033 else 1034 *bank = 0; 1035 } else if (hw->dev_spec != NULL) { 1036 /* 1037 * Make sure the signature for bank 0 is valid, 1038 * if not check for bank1 1039 */ 1040 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte); 1041 if ((bank_high_byte & 0xC0) == 0x80) { 1042 *bank = 0; 1043 } else { 1044 /* 1045 * find if segment 1 is valid by verifying 1046 * bit 15:14 = 10b in word 0x13 1047 */ 1048 e1000_read_flash_byte_ich8lan(hw, 1049 act_offset + bank1_offset, 1050 &bank_high_byte); 1051 1052 /* bank1 has a valid signature equivalent to SEC1V */ 1053 if ((bank_high_byte & 0xC0) == 0x80) { 1054 *bank = 1; 1055 } else { 1056 DEBUGOUT("ERROR: EEPROM not present\n"); 1057 ret_val = -E1000_ERR_NVM; 1058 } 1059 } 1060 } else { 1061 DEBUGOUT("DEV SPEC is NULL\n"); 1062 ret_val = -E1000_ERR_NVM; 1063 } 1064 1065 return ret_val; 1066 } 1067 1068 /** 1069 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1070 * @hw: pointer to the HW structure 1071 * @offset: The offset (in bytes) of the word(s) to read. 1072 * @words: Size of data to read in words 1073 * @data: Pointer to the word(s) to read at offset. 1074 * 1075 * Reads a word(s) from the NVM using the flash access registers. 1076 **/ 1077 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1078 u16 *data) 1079 { 1080 struct e1000_nvm_info *nvm = &hw->nvm; 1081 struct e1000_dev_spec_ich8lan *dev_spec; 1082 u32 act_offset; 1083 s32 ret_val = E1000_SUCCESS; 1084 u32 bank = 0; 1085 u16 i, word; 1086 1087 DEBUGFUNC("e1000_read_nvm_ich8lan"); 1088 1089 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1090 1091 if (!dev_spec) { 1092 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1093 ret_val = -E1000_ERR_CONFIG; 1094 goto out; 1095 } 1096 1097 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1098 (words == 0)) { 1099 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1100 ret_val = -E1000_ERR_NVM; 1101 goto out; 1102 } 1103 1104 ret_val = nvm->ops.acquire(hw); 1105 if (ret_val) 1106 goto out; 1107 1108 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1109 if (ret_val != E1000_SUCCESS) 1110 goto out; 1111 1112 act_offset = (bank) ? nvm->flash_bank_size : 0; 1113 act_offset += offset; 1114 1115 for (i = 0; i < words; i++) { 1116 if ((dev_spec->shadow_ram) && 1117 (dev_spec->shadow_ram[offset+i].modified)) { 1118 data[i] = dev_spec->shadow_ram[offset+i].value; 1119 } else { 1120 ret_val = e1000_read_flash_word_ich8lan(hw, 1121 act_offset + i, 1122 &word); 1123 if (ret_val) 1124 break; 1125 data[i] = word; 1126 } 1127 } 1128 1129 nvm->ops.release(hw); 1130 1131 out: 1132 return ret_val; 1133 } 1134 1135 /** 1136 * e1000_flash_cycle_init_ich8lan - Initialize flash 1137 * @hw: pointer to the HW structure 1138 * 1139 * This function does initial flash setup so that a new read/write/erase cycle 1140 * can be started. 1141 **/ 1142 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1143 { 1144 union ich8_hws_flash_status hsfsts; 1145 s32 ret_val = -E1000_ERR_NVM; 1146 s32 i = 0; 1147 1148 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1149 1150 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1151 1152 /* Check if the flash descriptor is valid */ 1153 if (hsfsts.hsf_status.fldesvalid == 0) { 1154 DEBUGOUT("Flash descriptor invalid. " 1155 "SW Sequencing must be used."); 1156 goto out; 1157 } 1158 1159 /* Clear FCERR and DAEL in hw status by writing 1 */ 1160 hsfsts.hsf_status.flcerr = 1; 1161 hsfsts.hsf_status.dael = 1; 1162 1163 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1164 1165 /* 1166 * Either we should have a hardware SPI cycle in progress 1167 * bit to check against, in order to start a new cycle or 1168 * FDONE bit should be changed in the hardware so that it 1169 * is 1 after hardware reset, which can then be used as an 1170 * indication whether a cycle is in progress or has been 1171 * completed. 1172 */ 1173 1174 if (hsfsts.hsf_status.flcinprog == 0) { 1175 /* 1176 * There is no cycle running at present, 1177 * so we can start a cycle. 1178 * Begin by setting Flash Cycle Done. 1179 */ 1180 hsfsts.hsf_status.flcdone = 1; 1181 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1182 ret_val = E1000_SUCCESS; 1183 } else { 1184 /* 1185 * Otherwise poll for sometime so the current 1186 * cycle has a chance to end before giving up. 1187 */ 1188 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1189 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1190 ICH_FLASH_HSFSTS); 1191 if (hsfsts.hsf_status.flcinprog == 0) { 1192 ret_val = E1000_SUCCESS; 1193 break; 1194 } 1195 usec_delay(1); 1196 } 1197 if (ret_val == E1000_SUCCESS) { 1198 /* 1199 * Successful in waiting for previous cycle to timeout, 1200 * now set the Flash Cycle Done. 1201 */ 1202 hsfsts.hsf_status.flcdone = 1; 1203 E1000_WRITE_FLASH_REG16(hw, 1204 ICH_FLASH_HSFSTS, 1205 hsfsts.regval); 1206 } else { 1207 DEBUGOUT("Flash controller busy, cannot get access"); 1208 } 1209 } 1210 1211 out: 1212 return ret_val; 1213 } 1214 1215 /** 1216 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1217 * @hw: pointer to the HW structure 1218 * @timeout: maximum time to wait for completion 1219 * 1220 * This function starts a flash cycle and waits for its completion. 1221 **/ 1222 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1223 { 1224 union ich8_hws_flash_ctrl hsflctl; 1225 union ich8_hws_flash_status hsfsts; 1226 s32 ret_val = -E1000_ERR_NVM; 1227 u32 i = 0; 1228 1229 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1230 1231 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1232 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1233 hsflctl.hsf_ctrl.flcgo = 1; 1234 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1235 1236 /* wait till FDONE bit is set to 1 */ 1237 do { 1238 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1239 if (hsfsts.hsf_status.flcdone == 1) 1240 break; 1241 usec_delay(1); 1242 } while (i++ < timeout); 1243 1244 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1245 ret_val = E1000_SUCCESS; 1246 1247 return ret_val; 1248 } 1249 1250 /** 1251 * e1000_read_flash_word_ich8lan - Read word from flash 1252 * @hw: pointer to the HW structure 1253 * @offset: offset to data location 1254 * @data: pointer to the location for storing the data 1255 * 1256 * Reads the flash word at offset into data. Offset is converted 1257 * to bytes before read. 1258 **/ 1259 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1260 u16 *data) 1261 { 1262 s32 ret_val; 1263 1264 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1265 1266 if (!data) { 1267 ret_val = -E1000_ERR_NVM; 1268 goto out; 1269 } 1270 1271 /* Must convert offset into bytes. */ 1272 offset <<= 1; 1273 1274 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1275 1276 out: 1277 return ret_val; 1278 } 1279 1280 /** 1281 * e1000_read_flash_byte_ich8lan - Read byte from flash 1282 * @hw: pointer to the HW structure 1283 * @offset: The offset of the byte to read. 1284 * @data: Pointer to a byte to store the value read. 1285 * 1286 * Reads a single byte from the NVM using the flash access registers. 1287 **/ 1288 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1289 u8* data) 1290 { 1291 s32 ret_val = E1000_SUCCESS; 1292 u16 word = 0; 1293 1294 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1295 if (ret_val) 1296 goto out; 1297 1298 *data = (u8)word; 1299 1300 out: 1301 return ret_val; 1302 } 1303 1304 /** 1305 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1306 * @hw: pointer to the HW structure 1307 * @offset: The offset (in bytes) of the byte or word to read. 1308 * @size: Size of data to read, 1=byte 2=word 1309 * @data: Pointer to the word to store the value read. 1310 * 1311 * Reads a byte or word from the NVM using the flash access registers. 1312 **/ 1313 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1314 u8 size, u16* data) 1315 { 1316 union ich8_hws_flash_status hsfsts; 1317 union ich8_hws_flash_ctrl hsflctl; 1318 u32 flash_linear_addr; 1319 u32 flash_data = 0; 1320 s32 ret_val = -E1000_ERR_NVM; 1321 u8 count = 0; 1322 1323 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1324 1325 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1326 goto out; 1327 1328 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1329 hw->nvm.flash_base_addr; 1330 1331 do { 1332 usec_delay(1); 1333 /* Steps */ 1334 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1335 if (ret_val != E1000_SUCCESS) 1336 break; 1337 1338 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1339 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1340 hsflctl.hsf_ctrl.fldbcount = size - 1; 1341 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1342 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1343 1344 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1345 1346 ret_val = e1000_flash_cycle_ich8lan(hw, 1347 ICH_FLASH_READ_COMMAND_TIMEOUT); 1348 1349 /* 1350 * Check if FCERR is set to 1, if set to 1, clear it 1351 * and try the whole sequence a few more times, else 1352 * read in (shift in) the Flash Data0, the order is 1353 * least significant byte first msb to lsb 1354 */ 1355 if (ret_val == E1000_SUCCESS) { 1356 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1357 if (size == 1) { 1358 *data = (u8)(flash_data & 0x000000FF); 1359 } else if (size == 2) { 1360 *data = (u16)(flash_data & 0x0000FFFF); 1361 } 1362 break; 1363 } else { 1364 /* 1365 * If we've gotten here, then things are probably 1366 * completely hosed, but if the error condition is 1367 * detected, it won't hurt to give it another try... 1368 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1369 */ 1370 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1371 ICH_FLASH_HSFSTS); 1372 if (hsfsts.hsf_status.flcerr == 1) { 1373 /* Repeat for some time before giving up. */ 1374 continue; 1375 } else if (hsfsts.hsf_status.flcdone == 0) { 1376 DEBUGOUT("Timeout error - flash cycle " 1377 "did not complete."); 1378 break; 1379 } 1380 } 1381 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1382 1383 out: 1384 return ret_val; 1385 } 1386 1387 /** 1388 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1389 * @hw: pointer to the HW structure 1390 * @offset: The offset (in bytes) of the word(s) to write. 1391 * @words: Size of data to write in words 1392 * @data: Pointer to the word(s) to write at offset. 1393 * 1394 * Writes a byte or word to the NVM using the flash access registers. 1395 **/ 1396 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1397 u16 *data) 1398 { 1399 struct e1000_nvm_info *nvm = &hw->nvm; 1400 struct e1000_dev_spec_ich8lan *dev_spec; 1401 s32 ret_val = E1000_SUCCESS; 1402 u16 i; 1403 1404 DEBUGFUNC("e1000_write_nvm_ich8lan"); 1405 1406 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1407 1408 if (!dev_spec) { 1409 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1410 ret_val = -E1000_ERR_CONFIG; 1411 goto out; 1412 } 1413 1414 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1415 (words == 0)) { 1416 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1417 ret_val = -E1000_ERR_NVM; 1418 goto out; 1419 } 1420 1421 ret_val = nvm->ops.acquire(hw); 1422 if (ret_val) 1423 goto out; 1424 1425 for (i = 0; i < words; i++) { 1426 dev_spec->shadow_ram[offset+i].modified = TRUE; 1427 dev_spec->shadow_ram[offset+i].value = data[i]; 1428 } 1429 1430 nvm->ops.release(hw); 1431 1432 out: 1433 return ret_val; 1434 } 1435 1436 /** 1437 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1438 * @hw: pointer to the HW structure 1439 * 1440 * The NVM checksum is updated by calling the generic update_nvm_checksum, 1441 * which writes the checksum to the shadow ram. The changes in the shadow 1442 * ram are then committed to the EEPROM by processing each bank at a time 1443 * checking for the modified bit and writing only the pending changes. 1444 * After a successful commit, the shadow ram is cleared and is ready for 1445 * future writes. 1446 **/ 1447 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1448 { 1449 struct e1000_nvm_info *nvm = &hw->nvm; 1450 struct e1000_dev_spec_ich8lan *dev_spec; 1451 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1452 s32 ret_val; 1453 u16 data; 1454 1455 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1456 1457 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 1458 1459 ret_val = e1000_update_nvm_checksum_generic(hw); 1460 if (ret_val) 1461 goto out; 1462 1463 if (nvm->type != e1000_nvm_flash_sw) 1464 goto out; 1465 1466 ret_val = nvm->ops.acquire(hw); 1467 if (ret_val) 1468 goto out; 1469 1470 /* 1471 * We're writing to the opposite bank so if we're on bank 1, 1472 * write to bank 0 etc. We also need to erase the segment that 1473 * is going to be written 1474 */ 1475 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1476 if (ret_val != E1000_SUCCESS) 1477 goto out; 1478 1479 if (bank == 0) { 1480 new_bank_offset = nvm->flash_bank_size; 1481 old_bank_offset = 0; 1482 e1000_erase_flash_bank_ich8lan(hw, 1); 1483 } else { 1484 old_bank_offset = nvm->flash_bank_size; 1485 new_bank_offset = 0; 1486 e1000_erase_flash_bank_ich8lan(hw, 0); 1487 } 1488 1489 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1490 /* 1491 * Determine whether to write the value stored 1492 * in the other NVM bank or a modified value stored 1493 * in the shadow RAM 1494 */ 1495 if (dev_spec->shadow_ram[i].modified) { 1496 data = dev_spec->shadow_ram[i].value; 1497 } else { 1498 e1000_read_flash_word_ich8lan(hw, 1499 i + old_bank_offset, 1500 &data); 1501 } 1502 1503 /* 1504 * If the word is 0x13, then make sure the signature bits 1505 * (15:14) are 11b until the commit has completed. 1506 * This will allow us to write 10b which indicates the 1507 * signature is valid. We want to do this after the write 1508 * has completed so that we don't mark the segment valid 1509 * while the write is still in progress 1510 */ 1511 if (i == E1000_ICH_NVM_SIG_WORD) 1512 data |= E1000_ICH_NVM_SIG_MASK; 1513 1514 /* Convert offset to bytes. */ 1515 act_offset = (i + new_bank_offset) << 1; 1516 1517 usec_delay(100); 1518 /* Write the bytes to the new bank. */ 1519 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1520 act_offset, 1521 (u8)data); 1522 if (ret_val) 1523 break; 1524 1525 usec_delay(100); 1526 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1527 act_offset + 1, 1528 (u8)(data >> 8)); 1529 if (ret_val) 1530 break; 1531 } 1532 1533 /* 1534 * Don't bother writing the segment valid bits if sector 1535 * programming failed. 1536 */ 1537 if (ret_val) { 1538 DEBUGOUT("Flash commit failed.\n"); 1539 nvm->ops.release(hw); 1540 goto out; 1541 } 1542 1543 /* 1544 * Finally validate the new segment by setting bit 15:14 1545 * to 10b in word 0x13 , this can be done without an 1546 * erase as well since these bits are 11 to start with 1547 * and we need to change bit 14 to 0b 1548 */ 1549 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1550 e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1551 data &= 0xBFFF; 1552 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1553 act_offset * 2 + 1, 1554 (u8)(data >> 8)); 1555 if (ret_val) { 1556 nvm->ops.release(hw); 1557 goto out; 1558 } 1559 1560 /* 1561 * And invalidate the previously valid segment by setting 1562 * its signature word (0x13) high_byte to 0b. This can be 1563 * done without an erase because flash erase sets all bits 1564 * to 1's. We can write 1's to 0's without an erase 1565 */ 1566 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1567 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1568 if (ret_val) { 1569 nvm->ops.release(hw); 1570 goto out; 1571 } 1572 1573 /* Great! Everything worked, we can now clear the cached entries. */ 1574 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1575 dev_spec->shadow_ram[i].modified = FALSE; 1576 dev_spec->shadow_ram[i].value = 0xFFFF; 1577 } 1578 1579 nvm->ops.release(hw); 1580 1581 /* 1582 * Reload the EEPROM, or else modifications will not appear 1583 * until after the next adapter reset. 1584 */ 1585 nvm->ops.reload(hw); 1586 msec_delay(10); 1587 1588 out: 1589 return ret_val; 1590 } 1591 1592 /** 1593 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1594 * @hw: pointer to the HW structure 1595 * 1596 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1597 * If the bit is 0, that the EEPROM had been modified, but the checksum was 1598 * not calculated, in which case we need to calculate the checksum and set 1599 * bit 6. 1600 **/ 1601 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1602 { 1603 s32 ret_val = E1000_SUCCESS; 1604 u16 data; 1605 1606 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1607 1608 /* 1609 * Read 0x19 and check bit 6. If this bit is 0, the checksum 1610 * needs to be fixed. This bit is an indication that the NVM 1611 * was prepared by OEM software and did not calculate the 1612 * checksum...a likely scenario. 1613 */ 1614 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 1615 if (ret_val) 1616 goto out; 1617 1618 if ((data & 0x40) == 0) { 1619 data |= 0x40; 1620 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 1621 if (ret_val) 1622 goto out; 1623 ret_val = hw->nvm.ops.update(hw); 1624 if (ret_val) 1625 goto out; 1626 } 1627 1628 ret_val = e1000_validate_nvm_checksum_generic(hw); 1629 1630 out: 1631 return ret_val; 1632 } 1633 1634 /** 1635 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1636 * @hw: pointer to the HW structure 1637 * @offset: The offset (in bytes) of the byte/word to read. 1638 * @size: Size of data to read, 1=byte 2=word 1639 * @data: The byte(s) to write to the NVM. 1640 * 1641 * Writes one/two bytes to the NVM using the flash access registers. 1642 **/ 1643 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1644 u8 size, u16 data) 1645 { 1646 union ich8_hws_flash_status hsfsts; 1647 union ich8_hws_flash_ctrl hsflctl; 1648 u32 flash_linear_addr; 1649 u32 flash_data = 0; 1650 s32 ret_val = -E1000_ERR_NVM; 1651 u8 count = 0; 1652 1653 DEBUGFUNC("e1000_write_ich8_data"); 1654 1655 if (size < 1 || size > 2 || data > size * 0xff || 1656 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1657 goto out; 1658 1659 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1660 hw->nvm.flash_base_addr; 1661 1662 do { 1663 usec_delay(1); 1664 /* Steps */ 1665 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1666 if (ret_val != E1000_SUCCESS) 1667 break; 1668 1669 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1670 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1671 hsflctl.hsf_ctrl.fldbcount = size -1; 1672 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1673 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1674 1675 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1676 1677 if (size == 1) 1678 flash_data = (u32)data & 0x00FF; 1679 else 1680 flash_data = (u32)data; 1681 1682 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1683 1684 /* 1685 * check if FCERR is set to 1 , if set to 1, clear it 1686 * and try the whole sequence a few more times else done 1687 */ 1688 ret_val = e1000_flash_cycle_ich8lan(hw, 1689 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1690 if (ret_val == E1000_SUCCESS) { 1691 break; 1692 } else { 1693 /* 1694 * If we're here, then things are most likely 1695 * completely hosed, but if the error condition 1696 * is detected, it won't hurt to give it another 1697 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1698 */ 1699 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1700 ICH_FLASH_HSFSTS); 1701 if (hsfsts.hsf_status.flcerr == 1) { 1702 /* Repeat for some time before giving up. */ 1703 continue; 1704 } else if (hsfsts.hsf_status.flcdone == 0) { 1705 DEBUGOUT("Timeout error - flash cycle " 1706 "did not complete."); 1707 break; 1708 } 1709 } 1710 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1711 1712 out: 1713 return ret_val; 1714 } 1715 1716 /** 1717 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1718 * @hw: pointer to the HW structure 1719 * @offset: The index of the byte to read. 1720 * @data: The byte to write to the NVM. 1721 * 1722 * Writes a single byte to the NVM using the flash access registers. 1723 **/ 1724 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1725 u8 data) 1726 { 1727 u16 word = (u16)data; 1728 1729 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1730 1731 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1732 } 1733 1734 /** 1735 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1736 * @hw: pointer to the HW structure 1737 * @offset: The offset of the byte to write. 1738 * @byte: The byte to write to the NVM. 1739 * 1740 * Writes a single byte to the NVM using the flash access registers. 1741 * Goes through a retry algorithm before giving up. 1742 **/ 1743 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1744 u32 offset, u8 byte) 1745 { 1746 s32 ret_val; 1747 u16 program_retries; 1748 1749 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1750 1751 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1752 if (ret_val == E1000_SUCCESS) 1753 goto out; 1754 1755 for (program_retries = 0; program_retries < 100; program_retries++) { 1756 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1757 usec_delay(100); 1758 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1759 if (ret_val == E1000_SUCCESS) 1760 break; 1761 } 1762 if (program_retries == 100) { 1763 ret_val = -E1000_ERR_NVM; 1764 goto out; 1765 } 1766 1767 out: 1768 return ret_val; 1769 } 1770 1771 /** 1772 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1773 * @hw: pointer to the HW structure 1774 * @bank: 0 for first bank, 1 for second bank, etc. 1775 * 1776 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1777 * bank N is 4096 * N + flash_reg_addr. 1778 **/ 1779 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1780 { 1781 struct e1000_nvm_info *nvm = &hw->nvm; 1782 union ich8_hws_flash_status hsfsts; 1783 union ich8_hws_flash_ctrl hsflctl; 1784 u32 flash_linear_addr; 1785 /* bank size is in 16bit words - adjust to bytes */ 1786 u32 flash_bank_size = nvm->flash_bank_size * 2; 1787 s32 ret_val = E1000_SUCCESS; 1788 s32 count = 0; 1789 s32 j, iteration, sector_size; 1790 1791 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1792 1793 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1794 1795 /* 1796 * Determine HW Sector size: Read BERASE bits of hw flash status 1797 * register 1798 * 00: The Hw sector is 256 bytes, hence we need to erase 16 1799 * consecutive sectors. The start index for the nth Hw sector 1800 * can be calculated as = bank * 4096 + n * 256 1801 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1802 * The start index for the nth Hw sector can be calculated 1803 * as = bank * 4096 1804 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1805 * (ich9 only, otherwise error condition) 1806 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1807 */ 1808 switch (hsfsts.hsf_status.berasesz) { 1809 case 0: 1810 /* Hw sector size 256 */ 1811 sector_size = ICH_FLASH_SEG_SIZE_256; 1812 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1813 break; 1814 case 1: 1815 sector_size = ICH_FLASH_SEG_SIZE_4K; 1816 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 1817 break; 1818 case 2: 1819 if (hw->mac.type == e1000_ich9lan) { 1820 sector_size = ICH_FLASH_SEG_SIZE_8K; 1821 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1822 } else { 1823 ret_val = -E1000_ERR_NVM; 1824 goto out; 1825 } 1826 break; 1827 case 3: 1828 sector_size = ICH_FLASH_SEG_SIZE_64K; 1829 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 1830 break; 1831 default: 1832 ret_val = -E1000_ERR_NVM; 1833 goto out; 1834 } 1835 1836 /* Start with the base address, then add the sector offset. */ 1837 flash_linear_addr = hw->nvm.flash_base_addr; 1838 flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1839 1840 for (j = 0; j < iteration ; j++) { 1841 do { 1842 /* Steps */ 1843 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1844 if (ret_val) 1845 goto out; 1846 1847 /* 1848 * Write a value 11 (block Erase) in Flash 1849 * Cycle field in hw flash control 1850 */ 1851 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1852 ICH_FLASH_HSFCTL); 1853 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1854 E1000_WRITE_FLASH_REG16(hw, 1855 ICH_FLASH_HSFCTL, 1856 hsflctl.regval); 1857 1858 /* 1859 * Write the last 24 bits of an index within the 1860 * block into Flash Linear address field in Flash 1861 * Address. 1862 */ 1863 flash_linear_addr += (j * sector_size); 1864 E1000_WRITE_FLASH_REG(hw, 1865 ICH_FLASH_FADDR, 1866 flash_linear_addr); 1867 1868 ret_val = e1000_flash_cycle_ich8lan(hw, 1869 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 1870 if (ret_val == E1000_SUCCESS) { 1871 break; 1872 } else { 1873 /* 1874 * Check if FCERR is set to 1. If 1, 1875 * clear it and try the whole sequence 1876 * a few more times else Done 1877 */ 1878 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1879 ICH_FLASH_HSFSTS); 1880 if (hsfsts.hsf_status.flcerr == 1) { 1881 /* 1882 * repeat for some time before 1883 * giving up 1884 */ 1885 continue; 1886 } else if (hsfsts.hsf_status.flcdone == 0) 1887 goto out; 1888 } 1889 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 1890 } 1891 1892 out: 1893 return ret_val; 1894 } 1895 1896 /** 1897 * e1000_valid_led_default_ich8lan - Set the default LED settings 1898 * @hw: pointer to the HW structure 1899 * @data: Pointer to the LED settings 1900 * 1901 * Reads the LED default settings from the NVM to data. If the NVM LED 1902 * settings is all 0's or F's, set the LED default to a valid LED default 1903 * setting. 1904 **/ 1905 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 1906 { 1907 s32 ret_val; 1908 1909 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 1910 1911 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1912 if (ret_val) { 1913 DEBUGOUT("NVM Read Error\n"); 1914 goto out; 1915 } 1916 1917 if (*data == ID_LED_RESERVED_0000 || 1918 *data == ID_LED_RESERVED_FFFF) 1919 *data = ID_LED_DEFAULT_ICH8LAN; 1920 1921 out: 1922 return ret_val; 1923 } 1924 1925 /** 1926 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 1927 * @hw: pointer to the HW structure 1928 * 1929 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 1930 * register, so the the bus width is hard coded. 1931 **/ 1932 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 1933 { 1934 struct e1000_bus_info *bus = &hw->bus; 1935 s32 ret_val; 1936 1937 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 1938 1939 ret_val = e1000_get_bus_info_pcie_generic(hw); 1940 1941 /* 1942 * ICH devices are "PCI Express"-ish. They have 1943 * a configuration space, but do not contain 1944 * PCI Express Capability registers, so bus width 1945 * must be hardcoded. 1946 */ 1947 if (bus->width == e1000_bus_width_unknown) 1948 bus->width = e1000_bus_width_pcie_x1; 1949 1950 return ret_val; 1951 } 1952 1953 /** 1954 * e1000_reset_hw_ich8lan - Reset the hardware 1955 * @hw: pointer to the HW structure 1956 * 1957 * Does a full reset of the hardware which includes a reset of the PHY and 1958 * MAC. 1959 **/ 1960 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 1961 { 1962 u32 ctrl, icr, kab; 1963 s32 ret_val; 1964 1965 DEBUGFUNC("e1000_reset_hw_ich8lan"); 1966 1967 /* 1968 * Prevent the PCI-E bus from sticking if there is no TLP connection 1969 * on the last TLP read/write transaction when MAC is reset. 1970 */ 1971 ret_val = e1000_disable_pcie_master_generic(hw); 1972 if (ret_val) { 1973 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1974 } 1975 1976 DEBUGOUT("Masking off all interrupts\n"); 1977 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1978 1979 /* 1980 * Disable the Transmit and Receive units. Then delay to allow 1981 * any pending transactions to complete before we hit the MAC 1982 * with the global reset. 1983 */ 1984 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1985 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1986 E1000_WRITE_FLUSH(hw); 1987 1988 msec_delay(10); 1989 1990 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1991 if (hw->mac.type == e1000_ich8lan) { 1992 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1993 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 1994 /* Set Packet Buffer Size to 16k. */ 1995 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 1996 } 1997 1998 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1999 2000 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 2001 /* 2002 * PHY HW reset requires MAC CORE reset at the same 2003 * time to make sure the interface between MAC and the 2004 * external PHY is reset. 2005 */ 2006 ctrl |= E1000_CTRL_PHY_RST; 2007 } 2008 ret_val = e1000_acquire_swflag_ich8lan(hw); 2009 DEBUGOUT("Issuing a global reset to ich8lan"); 2010 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2011 msec_delay(20); 2012 2013 ret_val = e1000_get_auto_rd_done_generic(hw); 2014 if (ret_val) { 2015 /* 2016 * When auto config read does not complete, do not 2017 * return with an error. This can happen in situations 2018 * where there is no eeprom and prevents getting link. 2019 */ 2020 DEBUGOUT("Auto Read Done did not complete\n"); 2021 } 2022 2023 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2024 icr = E1000_READ_REG(hw, E1000_ICR); 2025 2026 kab = E1000_READ_REG(hw, E1000_KABGTXD); 2027 kab |= E1000_KABGTXD_BGSQLBIAS; 2028 E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2029 2030 return ret_val; 2031 } 2032 2033 /** 2034 * e1000_init_hw_ich8lan - Initialize the hardware 2035 * @hw: pointer to the HW structure 2036 * 2037 * Prepares the hardware for transmit and receive by doing the following: 2038 * - initialize hardware bits 2039 * - initialize LED identification 2040 * - setup receive address registers 2041 * - setup flow control 2042 * - setup transmit descriptors 2043 * - clear statistics 2044 **/ 2045 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2046 { 2047 struct e1000_mac_info *mac = &hw->mac; 2048 u32 ctrl_ext, txdctl, snoop; 2049 s32 ret_val; 2050 u16 i; 2051 2052 DEBUGFUNC("e1000_init_hw_ich8lan"); 2053 2054 e1000_initialize_hw_bits_ich8lan(hw); 2055 2056 /* Initialize identification LED */ 2057 ret_val = e1000_id_led_init_generic(hw); 2058 if (ret_val) { 2059 DEBUGOUT("Error initializing identification LED\n"); 2060 /* This is not fatal and we should not stop init due to this */ 2061 } 2062 2063 /* Setup the receive address. */ 2064 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2065 2066 /* Zero out the Multicast HASH table */ 2067 DEBUGOUT("Zeroing the MTA\n"); 2068 for (i = 0; i < mac->mta_reg_count; i++) 2069 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2070 2071 /* Setup link and flow control */ 2072 ret_val = mac->ops.setup_link(hw); 2073 2074 /* Set the transmit descriptor write-back policy for both queues */ 2075 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2076 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2077 E1000_TXDCTL_FULL_TX_DESC_WB; 2078 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2079 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2080 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2081 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2082 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2083 E1000_TXDCTL_FULL_TX_DESC_WB; 2084 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2085 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2086 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2087 2088 /* 2089 * ICH8 has opposite polarity of no_snoop bits. 2090 * By default, we should use snoop behavior. 2091 */ 2092 if (mac->type == e1000_ich8lan) 2093 snoop = PCIE_ICH8_SNOOP_ALL; 2094 else 2095 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2096 e1000_set_pcie_no_snoop_generic(hw, snoop); 2097 2098 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2099 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2100 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2101 2102 /* 2103 * Clear all of the statistics registers (clear on read). It is 2104 * important that we do this after we have tried to establish link 2105 * because the symbol error count will increment wildly if there 2106 * is no link. 2107 */ 2108 e1000_clear_hw_cntrs_ich8lan(hw); 2109 2110 return ret_val; 2111 } 2112 /** 2113 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2114 * @hw: pointer to the HW structure 2115 * 2116 * Sets/Clears required hardware bits necessary for correctly setting up the 2117 * hardware for transmit and receive. 2118 **/ 2119 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2120 { 2121 u32 reg; 2122 2123 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2124 2125 if (hw->mac.disable_hw_init_bits) 2126 goto out; 2127 2128 /* Extended Device Control */ 2129 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2130 reg |= (1 << 22); 2131 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2132 2133 /* Transmit Descriptor Control 0 */ 2134 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2135 reg |= (1 << 22); 2136 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2137 2138 /* Transmit Descriptor Control 1 */ 2139 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2140 reg |= (1 << 22); 2141 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2142 2143 /* Transmit Arbitration Control 0 */ 2144 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2145 if (hw->mac.type == e1000_ich8lan) 2146 reg |= (1 << 28) | (1 << 29); 2147 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2148 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2149 2150 /* Transmit Arbitration Control 1 */ 2151 reg = E1000_READ_REG(hw, E1000_TARC(1)); 2152 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2153 reg &= ~(1 << 28); 2154 else 2155 reg |= (1 << 28); 2156 reg |= (1 << 24) | (1 << 26) | (1 << 30); 2157 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2158 2159 /* Device Status */ 2160 if (hw->mac.type == e1000_ich8lan) { 2161 reg = E1000_READ_REG(hw, E1000_STATUS); 2162 reg &= ~(1 << 31); 2163 E1000_WRITE_REG(hw, E1000_STATUS, reg); 2164 } 2165 2166 out: 2167 return; 2168 } 2169 2170 /** 2171 * e1000_setup_link_ich8lan - Setup flow control and link settings 2172 * @hw: pointer to the HW structure 2173 * 2174 * Determines which flow control settings to use, then configures flow 2175 * control. Calls the appropriate media-specific link configuration 2176 * function. Assuming the adapter has a valid link partner, a valid link 2177 * should be established. Assumes the hardware has previously been reset 2178 * and the transmitter and receiver are not enabled. 2179 **/ 2180 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2181 { 2182 s32 ret_val = E1000_SUCCESS; 2183 2184 DEBUGFUNC("e1000_setup_link_ich8lan"); 2185 2186 if (hw->phy.ops.check_reset_block(hw)) 2187 goto out; 2188 2189 /* 2190 * ICH parts do not have a word in the NVM to determine 2191 * the default flow control setting, so we explicitly 2192 * set it to full. 2193 */ 2194 if (hw->fc.type == e1000_fc_default) 2195 hw->fc.type = e1000_fc_full; 2196 2197 hw->fc.original_type = hw->fc.type; 2198 2199 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 2200 2201 /* Continue to configure the copper link. */ 2202 ret_val = hw->mac.ops.setup_physical_interface(hw); 2203 if (ret_val) 2204 goto out; 2205 2206 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2207 2208 ret_val = e1000_set_fc_watermarks_generic(hw); 2209 2210 out: 2211 return ret_val; 2212 } 2213 2214 /** 2215 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2216 * @hw: pointer to the HW structure 2217 * 2218 * Configures the kumeran interface to the PHY to wait the appropriate time 2219 * when polling the PHY, then call the generic setup_copper_link to finish 2220 * configuring the copper link. 2221 **/ 2222 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2223 { 2224 u32 ctrl; 2225 s32 ret_val; 2226 u16 reg_data; 2227 2228 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2229 2230 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2231 ctrl |= E1000_CTRL_SLU; 2232 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2233 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2234 2235 /* 2236 * Set the mac to wait the maximum time between each iteration 2237 * and increase the max iterations when polling the phy; 2238 * this fixes erroneous timeouts at 10Mbps. 2239 */ 2240 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4), 2241 0xFFFF); 2242 if (ret_val) 2243 goto out; 2244 ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 2245 ®_data); 2246 if (ret_val) 2247 goto out; 2248 reg_data |= 0x3F; 2249 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 2250 reg_data); 2251 if (ret_val) 2252 goto out; 2253 2254 if (hw->phy.type == e1000_phy_igp_3) { 2255 ret_val = e1000_copper_link_setup_igp(hw); 2256 if (ret_val) 2257 goto out; 2258 } else if (hw->phy.type == e1000_phy_bm) { 2259 ret_val = e1000_copper_link_setup_m88(hw); 2260 if (ret_val) 2261 goto out; 2262 } 2263 2264 if (hw->phy.type == e1000_phy_ife) { 2265 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2266 ®_data); 2267 if (ret_val) 2268 goto out; 2269 2270 reg_data &= ~IFE_PMC_AUTO_MDIX; 2271 2272 switch (hw->phy.mdix) { 2273 case 1: 2274 reg_data &= ~IFE_PMC_FORCE_MDIX; 2275 break; 2276 case 2: 2277 reg_data |= IFE_PMC_FORCE_MDIX; 2278 break; 2279 case 0: 2280 default: 2281 reg_data |= IFE_PMC_AUTO_MDIX; 2282 break; 2283 } 2284 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2285 reg_data); 2286 if (ret_val) 2287 goto out; 2288 } 2289 ret_val = e1000_setup_copper_link_generic(hw); 2290 2291 out: 2292 return ret_val; 2293 } 2294 2295 /** 2296 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2297 * @hw: pointer to the HW structure 2298 * @speed: pointer to store current link speed 2299 * @duplex: pointer to store the current link duplex 2300 * 2301 * Calls the generic get_speed_and_duplex to retrieve the current link 2302 * information and then calls the Kumeran lock loss workaround for links at 2303 * gigabit speeds. 2304 **/ 2305 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2306 u16 *duplex) 2307 { 2308 s32 ret_val; 2309 2310 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2311 2312 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2313 if (ret_val) 2314 goto out; 2315 2316 if ((hw->mac.type == e1000_ich8lan) && 2317 (hw->phy.type == e1000_phy_igp_3) && 2318 (*speed == SPEED_1000)) { 2319 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2320 } 2321 2322 out: 2323 return ret_val; 2324 } 2325 2326 /** 2327 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2328 * @hw: pointer to the HW structure 2329 * 2330 * Work-around for 82566 Kumeran PCS lock loss: 2331 * On link status change (i.e. PCI reset, speed change) and link is up and 2332 * speed is gigabit- 2333 * 0) if workaround is optionally disabled do nothing 2334 * 1) wait 1ms for Kumeran link to come up 2335 * 2) check Kumeran Diagnostic register PCS lock loss bit 2336 * 3) if not set the link is locked (all is good), otherwise... 2337 * 4) reset the PHY 2338 * 5) repeat up to 10 times 2339 * Note: this is only called for IGP3 copper when speed is 1gb. 2340 **/ 2341 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2342 { 2343 struct e1000_dev_spec_ich8lan *dev_spec; 2344 u32 phy_ctrl; 2345 s32 ret_val = E1000_SUCCESS; 2346 u16 i, data; 2347 bool link; 2348 2349 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2350 2351 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2352 2353 if (!dev_spec) { 2354 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2355 ret_val = -E1000_ERR_CONFIG; 2356 goto out; 2357 } 2358 2359 if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2360 goto out; 2361 2362 /* 2363 * Make sure link is up before proceeding. If not just return. 2364 * Attempting this while link is negotiating fouled up link 2365 * stability 2366 */ 2367 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2368 if (!link) { 2369 ret_val = E1000_SUCCESS; 2370 goto out; 2371 } 2372 2373 for (i = 0; i < 10; i++) { 2374 /* read once to clear */ 2375 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2376 if (ret_val) 2377 goto out; 2378 /* and again to get new status */ 2379 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2380 if (ret_val) 2381 goto out; 2382 2383 /* check for PCS lock */ 2384 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2385 ret_val = E1000_SUCCESS; 2386 goto out; 2387 } 2388 2389 /* Issue PHY reset */ 2390 hw->phy.ops.reset(hw); 2391 msec_delay_irq(5); 2392 } 2393 /* Disable GigE link negotiation */ 2394 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2395 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2396 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2397 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2398 2399 /* 2400 * Call gig speed drop workaround on Gig disable before accessing 2401 * any PHY registers 2402 */ 2403 e1000_gig_downshift_workaround_ich8lan(hw); 2404 2405 /* unable to acquire PCS lock */ 2406 ret_val = -E1000_ERR_PHY; 2407 2408 out: 2409 return ret_val; 2410 } 2411 2412 /** 2413 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2414 * @hw: pointer to the HW structure 2415 * @state: boolean value used to set the current Kumeran workaround state 2416 * 2417 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2418 * /disabled - FALSE). 2419 **/ 2420 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2421 bool state) 2422 { 2423 struct e1000_dev_spec_ich8lan *dev_spec; 2424 2425 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2426 2427 if (hw->mac.type != e1000_ich8lan) { 2428 DEBUGOUT("Workaround applies to ICH8 only.\n"); 2429 goto out; 2430 } 2431 2432 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec; 2433 2434 if (!dev_spec) { 2435 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 2436 goto out; 2437 } 2438 2439 dev_spec->kmrn_lock_loss_workaround_enabled = state; 2440 2441 out: 2442 return; 2443 } 2444 2445 /** 2446 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2447 * @hw: pointer to the HW structure 2448 * 2449 * Workaround for 82566 power-down on D3 entry: 2450 * 1) disable gigabit link 2451 * 2) write VR power-down enable 2452 * 3) read it back 2453 * Continue if successful, else issue LCD reset and repeat 2454 **/ 2455 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2456 { 2457 u32 reg; 2458 u16 data; 2459 u8 retry = 0; 2460 2461 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2462 2463 if (hw->phy.type != e1000_phy_igp_3) 2464 goto out; 2465 2466 /* Try the workaround twice (if needed) */ 2467 do { 2468 /* Disable link */ 2469 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2470 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2471 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2472 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2473 2474 /* 2475 * Call gig speed drop workaround on Gig disable before 2476 * accessing any PHY registers 2477 */ 2478 if (hw->mac.type == e1000_ich8lan) 2479 e1000_gig_downshift_workaround_ich8lan(hw); 2480 2481 /* Write VR power-down enable */ 2482 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2483 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2484 hw->phy.ops.write_reg(hw, 2485 IGP3_VR_CTRL, 2486 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2487 2488 /* Read it back and test */ 2489 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2490 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2491 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2492 break; 2493 2494 /* Issue PHY reset and repeat at most one more time */ 2495 reg = E1000_READ_REG(hw, E1000_CTRL); 2496 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2497 retry++; 2498 } while (retry); 2499 2500 out: 2501 return; 2502 } 2503 2504 /** 2505 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2506 * @hw: pointer to the HW structure 2507 * 2508 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2509 * LPLU, Gig disable, MDIC PHY reset): 2510 * 1) Set Kumeran Near-end loopback 2511 * 2) Clear Kumeran Near-end loopback 2512 * Should only be called for ICH8[m] devices with IGP_3 Phy. 2513 **/ 2514 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2515 { 2516 s32 ret_val = E1000_SUCCESS; 2517 u16 reg_data; 2518 2519 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2520 2521 if ((hw->mac.type != e1000_ich8lan) || 2522 (hw->phy.type != e1000_phy_igp_3)) 2523 goto out; 2524 2525 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2526 ®_data); 2527 if (ret_val) 2528 goto out; 2529 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2530 ret_val = e1000_write_kmrn_reg_generic(hw, 2531 E1000_KMRNCTRLSTA_DIAG_OFFSET, 2532 reg_data); 2533 if (ret_val) 2534 goto out; 2535 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2536 ret_val = e1000_write_kmrn_reg_generic(hw, 2537 E1000_KMRNCTRLSTA_DIAG_OFFSET, 2538 reg_data); 2539 out: 2540 return; 2541 } 2542 2543 /** 2544 * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2545 * @hw: pointer to the HW structure 2546 * 2547 * During S0 to Sx transition, it is possible the link remains at gig 2548 * instead of negotiating to a lower speed. Before going to Sx, set 2549 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2550 * to a lower speed. 2551 * 2552 * Should only be called for ICH9 and ICH10 devices. 2553 **/ 2554 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2555 { 2556 u32 phy_ctrl; 2557 2558 if ((hw->mac.type == e1000_ich10lan) || 2559 (hw->mac.type == e1000_ich9lan)) { 2560 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2561 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2562 E1000_PHY_CTRL_GBE_DISABLE; 2563 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2564 } 2565 2566 return; 2567 } 2568 2569 /** 2570 * e1000_cleanup_led_ich8lan - Restore the default LED operation 2571 * @hw: pointer to the HW structure 2572 * 2573 * Return the LED back to the default configuration. 2574 **/ 2575 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2576 { 2577 s32 ret_val = E1000_SUCCESS; 2578 2579 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2580 2581 if (hw->phy.type == e1000_phy_ife) 2582 ret_val = hw->phy.ops.write_reg(hw, 2583 IFE_PHY_SPECIAL_CONTROL_LED, 2584 0); 2585 else 2586 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2587 2588 return ret_val; 2589 } 2590 2591 /** 2592 * e1000_led_on_ich8lan - Turn LEDs on 2593 * @hw: pointer to the HW structure 2594 * 2595 * Turn on the LEDs. 2596 **/ 2597 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2598 { 2599 s32 ret_val = E1000_SUCCESS; 2600 2601 DEBUGFUNC("e1000_led_on_ich8lan"); 2602 2603 if (hw->phy.type == e1000_phy_ife) 2604 ret_val = hw->phy.ops.write_reg(hw, 2605 IFE_PHY_SPECIAL_CONTROL_LED, 2606 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2607 else 2608 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2609 2610 return ret_val; 2611 } 2612 2613 /** 2614 * e1000_led_off_ich8lan - Turn LEDs off 2615 * @hw: pointer to the HW structure 2616 * 2617 * Turn off the LEDs. 2618 **/ 2619 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2620 { 2621 s32 ret_val = E1000_SUCCESS; 2622 2623 DEBUGFUNC("e1000_led_off_ich8lan"); 2624 2625 if (hw->phy.type == e1000_phy_ife) 2626 ret_val = hw->phy.ops.write_reg(hw, 2627 IFE_PHY_SPECIAL_CONTROL_LED, 2628 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2629 else 2630 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2631 2632 return ret_val; 2633 } 2634 2635 /** 2636 * e1000_get_cfg_done_ich8lan - Read config done bit 2637 * @hw: pointer to the HW structure 2638 * 2639 * Read the management control register for the config done bit for 2640 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2641 * to read the config done bit, so an error is *ONLY* logged and returns 2642 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2643 * would not be able to be reset or change link. 2644 **/ 2645 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2646 { 2647 s32 ret_val = E1000_SUCCESS; 2648 u32 bank = 0; 2649 2650 e1000_get_cfg_done_generic(hw); 2651 2652 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2653 if (hw->mac.type != e1000_ich10lan) { 2654 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 2655 (hw->phy.type == e1000_phy_igp_3)) { 2656 e1000_phy_init_script_igp3(hw); 2657 } 2658 } else { 2659 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 2660 /* Maybe we should do a basic Boazman config */ 2661 DEBUGOUT("EEPROM not present\n"); 2662 ret_val = -E1000_ERR_CONFIG; 2663 } 2664 } 2665 2666 return ret_val; 2667 } 2668 2669 /** 2670 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 2671 * @hw: pointer to the HW structure 2672 * 2673 * In the case of a PHY power down to save power, or to turn off link during a 2674 * driver unload, or wake on lan is not enabled, remove the link. 2675 **/ 2676 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 2677 { 2678 struct e1000_phy_info *phy = &hw->phy; 2679 struct e1000_mac_info *mac = &hw->mac; 2680 2681 /* If the management interface is not enabled, then power down */ 2682 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 2683 e1000_power_down_phy_copper(hw); 2684 2685 return; 2686 } 2687 2688 /** 2689 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 2690 * @hw: pointer to the HW structure 2691 * 2692 * Clears hardware counters specific to the silicon family and calls 2693 * clear_hw_cntrs_generic to clear all general purpose counters. 2694 **/ 2695 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2696 { 2697 volatile u32 temp; 2698 2699 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 2700 2701 e1000_clear_hw_cntrs_base_generic(hw); 2702 2703 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 2704 temp = E1000_READ_REG(hw, E1000_RXERRC); 2705 temp = E1000_READ_REG(hw, E1000_TNCRS); 2706 temp = E1000_READ_REG(hw, E1000_CEXTERR); 2707 temp = E1000_READ_REG(hw, E1000_TSCTC); 2708 temp = E1000_READ_REG(hw, E1000_TSCTFC); 2709 2710 temp = E1000_READ_REG(hw, E1000_MGTPRC); 2711 temp = E1000_READ_REG(hw, E1000_MGTPDC); 2712 temp = E1000_READ_REG(hw, E1000_MGTPTC); 2713 2714 temp = E1000_READ_REG(hw, E1000_IAC); 2715 temp = E1000_READ_REG(hw, E1000_ICRXOC); 2716 } 2717 2718