xref: /freebsd/sys/dev/e1000/e1000_ich8lan.c (revision 6fe4c0a063f7010db199e2f50ca00e5830a100fd)
18cfa0ad2SJack F Vogel /******************************************************************************
27282444bSPedro F. Giffuni   SPDX-License-Identifier: BSD-3-Clause
38cfa0ad2SJack F Vogel 
47c669ab6SSean Bruno   Copyright (c) 2001-2015, Intel Corporation
58cfa0ad2SJack F Vogel   All rights reserved.
68cfa0ad2SJack F Vogel 
78cfa0ad2SJack F Vogel   Redistribution and use in source and binary forms, with or without
88cfa0ad2SJack F Vogel   modification, are permitted provided that the following conditions are met:
98cfa0ad2SJack F Vogel 
108cfa0ad2SJack F Vogel    1. Redistributions of source code must retain the above copyright notice,
118cfa0ad2SJack F Vogel       this list of conditions and the following disclaimer.
128cfa0ad2SJack F Vogel 
138cfa0ad2SJack F Vogel    2. Redistributions in binary form must reproduce the above copyright
148cfa0ad2SJack F Vogel       notice, this list of conditions and the following disclaimer in the
158cfa0ad2SJack F Vogel       documentation and/or other materials provided with the distribution.
168cfa0ad2SJack F Vogel 
178cfa0ad2SJack F Vogel    3. Neither the name of the Intel Corporation nor the names of its
188cfa0ad2SJack F Vogel       contributors may be used to endorse or promote products derived from
198cfa0ad2SJack F Vogel       this software without specific prior written permission.
208cfa0ad2SJack F Vogel 
218cfa0ad2SJack F Vogel   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
228cfa0ad2SJack F Vogel   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
238cfa0ad2SJack F Vogel   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
248cfa0ad2SJack F Vogel   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
258cfa0ad2SJack F Vogel   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
268cfa0ad2SJack F Vogel   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
278cfa0ad2SJack F Vogel   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
288cfa0ad2SJack F Vogel   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
298cfa0ad2SJack F Vogel   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
308cfa0ad2SJack F Vogel   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
318cfa0ad2SJack F Vogel   POSSIBILITY OF SUCH DAMAGE.
328cfa0ad2SJack F Vogel 
338cfa0ad2SJack F Vogel ******************************************************************************/
348cfa0ad2SJack F Vogel /*$FreeBSD$*/
358cfa0ad2SJack F Vogel 
366ab6bfe3SJack F Vogel /* 82562G 10/100 Network Connection
37daf9197cSJack F Vogel  * 82562G-2 10/100 Network Connection
38daf9197cSJack F Vogel  * 82562GT 10/100 Network Connection
39daf9197cSJack F Vogel  * 82562GT-2 10/100 Network Connection
40daf9197cSJack F Vogel  * 82562V 10/100 Network Connection
41daf9197cSJack F Vogel  * 82562V-2 10/100 Network Connection
42daf9197cSJack F Vogel  * 82566DC-2 Gigabit Network Connection
43daf9197cSJack F Vogel  * 82566DC Gigabit Network Connection
44daf9197cSJack F Vogel  * 82566DM-2 Gigabit Network Connection
45daf9197cSJack F Vogel  * 82566DM Gigabit Network Connection
46daf9197cSJack F Vogel  * 82566MC Gigabit Network Connection
47daf9197cSJack F Vogel  * 82566MM Gigabit Network Connection
48daf9197cSJack F Vogel  * 82567LM Gigabit Network Connection
49daf9197cSJack F Vogel  * 82567LF Gigabit Network Connection
50daf9197cSJack F Vogel  * 82567V Gigabit Network Connection
51daf9197cSJack F Vogel  * 82567LM-2 Gigabit Network Connection
52daf9197cSJack F Vogel  * 82567LF-2 Gigabit Network Connection
53daf9197cSJack F Vogel  * 82567V-2 Gigabit Network Connection
54daf9197cSJack F Vogel  * 82567LF-3 Gigabit Network Connection
55daf9197cSJack F Vogel  * 82567LM-3 Gigabit Network Connection
56daf9197cSJack F Vogel  * 82567LM-4 Gigabit Network Connection
579d81738fSJack F Vogel  * 82577LM Gigabit Network Connection
589d81738fSJack F Vogel  * 82577LC Gigabit Network Connection
599d81738fSJack F Vogel  * 82578DM Gigabit Network Connection
609d81738fSJack F Vogel  * 82578DC Gigabit Network Connection
617d9119bdSJack F Vogel  * 82579LM Gigabit Network Connection
627d9119bdSJack F Vogel  * 82579V Gigabit Network Connection
637609433eSJack F Vogel  * Ethernet Connection I217-LM
647609433eSJack F Vogel  * Ethernet Connection I217-V
657609433eSJack F Vogel  * Ethernet Connection I218-V
667609433eSJack F Vogel  * Ethernet Connection I218-LM
678cc64f1eSJack F Vogel  * Ethernet Connection (2) I218-LM
688cc64f1eSJack F Vogel  * Ethernet Connection (2) I218-V
698cc64f1eSJack F Vogel  * Ethernet Connection (3) I218-LM
708cc64f1eSJack F Vogel  * Ethernet Connection (3) I218-V
718cfa0ad2SJack F Vogel  */
728cfa0ad2SJack F Vogel 
738cfa0ad2SJack F Vogel #include "e1000_api.h"
748cfa0ad2SJack F Vogel 
758cfa0ad2SJack F Vogel static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
768cfa0ad2SJack F Vogel static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
774edd8523SJack F Vogel static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
784edd8523SJack F Vogel static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
798cfa0ad2SJack F Vogel static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
807d9119bdSJack F Vogel static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
818cc64f1eSJack F Vogel static int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
828cc64f1eSJack F Vogel static int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
837609433eSJack F Vogel static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
84730d3130SJack F Vogel static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
85730d3130SJack F Vogel 					      u8 *mc_addr_list,
86730d3130SJack F Vogel 					      u32 mc_addr_count);
878cfa0ad2SJack F Vogel static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
888cfa0ad2SJack F Vogel static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
894edd8523SJack F Vogel static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
908cfa0ad2SJack F Vogel static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
918cfa0ad2SJack F Vogel 					    bool active);
928cfa0ad2SJack F Vogel static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
938cfa0ad2SJack F Vogel 					    bool active);
948cfa0ad2SJack F Vogel static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
958cfa0ad2SJack F Vogel 				   u16 words, u16 *data);
96c80429ceSEric Joyner static s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97c80429ceSEric Joyner 			       u16 *data);
988cfa0ad2SJack F Vogel static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
998cfa0ad2SJack F Vogel 				    u16 words, u16 *data);
1008cfa0ad2SJack F Vogel static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
1018cfa0ad2SJack F Vogel static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
102c80429ceSEric Joyner static s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
1038cfa0ad2SJack F Vogel static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
1048cfa0ad2SJack F Vogel 					    u16 *data);
1059d81738fSJack F Vogel static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
1068cfa0ad2SJack F Vogel static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
1078cfa0ad2SJack F Vogel static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
1088cfa0ad2SJack F Vogel static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
1098cfa0ad2SJack F Vogel static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
1108cfa0ad2SJack F Vogel static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
1116ab6bfe3SJack F Vogel static s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
1128cfa0ad2SJack F Vogel static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
1138cfa0ad2SJack F Vogel 					   u16 *speed, u16 *duplex);
1148cfa0ad2SJack F Vogel static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
1158cfa0ad2SJack F Vogel static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
1168cfa0ad2SJack F Vogel static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
1174edd8523SJack F Vogel static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
1189d81738fSJack F Vogel static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
1199d81738fSJack F Vogel static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
1209d81738fSJack F Vogel static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
1219d81738fSJack F Vogel static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
1228cfa0ad2SJack F Vogel static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
1238cfa0ad2SJack F Vogel static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
1248cfa0ad2SJack F Vogel static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
1258cfa0ad2SJack F Vogel static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
1268cfa0ad2SJack F Vogel static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
1278cfa0ad2SJack F Vogel 					  u32 offset, u8 *data);
1288cfa0ad2SJack F Vogel static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1298cfa0ad2SJack F Vogel 					  u8 size, u16 *data);
130c80429ceSEric Joyner static s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131c80429ceSEric Joyner 					    u32 *data);
132c80429ceSEric Joyner static s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133c80429ceSEric Joyner 					   u32 offset, u32 *data);
134c80429ceSEric Joyner static s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135c80429ceSEric Joyner 					     u32 offset, u32 data);
136c80429ceSEric Joyner static s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137c80429ceSEric Joyner 						  u32 offset, u32 dword);
1388cfa0ad2SJack F Vogel static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
1398cfa0ad2SJack F Vogel 					  u32 offset, u16 *data);
1408cfa0ad2SJack F Vogel static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1418cfa0ad2SJack F Vogel 						 u32 offset, u8 byte);
1428cfa0ad2SJack F Vogel static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
1438cfa0ad2SJack F Vogel static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
1444edd8523SJack F Vogel static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
145a69ed8dfSJack F Vogel static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
1467d9119bdSJack F Vogel static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
1477d9119bdSJack F Vogel static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
148e373323fSSean Bruno static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
1498cfa0ad2SJack F Vogel 
1508cfa0ad2SJack F Vogel /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
1518cfa0ad2SJack F Vogel /* Offset 04h HSFSTS */
1528cfa0ad2SJack F Vogel union ich8_hws_flash_status {
1538cfa0ad2SJack F Vogel 	struct ich8_hsfsts {
1548cfa0ad2SJack F Vogel 		u16 flcdone:1; /* bit 0 Flash Cycle Done */
1558cfa0ad2SJack F Vogel 		u16 flcerr:1; /* bit 1 Flash Cycle Error */
1568cfa0ad2SJack F Vogel 		u16 dael:1; /* bit 2 Direct Access error Log */
1578cfa0ad2SJack F Vogel 		u16 berasesz:2; /* bit 4:3 Sector Erase Size */
1588cfa0ad2SJack F Vogel 		u16 flcinprog:1; /* bit 5 flash cycle in Progress */
1598cfa0ad2SJack F Vogel 		u16 reserved1:2; /* bit 13:6 Reserved */
1608cfa0ad2SJack F Vogel 		u16 reserved2:6; /* bit 13:6 Reserved */
1618cfa0ad2SJack F Vogel 		u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
1628cfa0ad2SJack F Vogel 		u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
1638cfa0ad2SJack F Vogel 	} hsf_status;
1648cfa0ad2SJack F Vogel 	u16 regval;
1658cfa0ad2SJack F Vogel };
1668cfa0ad2SJack F Vogel 
1678cfa0ad2SJack F Vogel /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
1688cfa0ad2SJack F Vogel /* Offset 06h FLCTL */
1698cfa0ad2SJack F Vogel union ich8_hws_flash_ctrl {
1708cfa0ad2SJack F Vogel 	struct ich8_hsflctl {
1718cfa0ad2SJack F Vogel 		u16 flcgo:1;   /* 0 Flash Cycle Go */
1728cfa0ad2SJack F Vogel 		u16 flcycle:2;   /* 2:1 Flash Cycle */
1738cfa0ad2SJack F Vogel 		u16 reserved:5;   /* 7:3 Reserved  */
1748cfa0ad2SJack F Vogel 		u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
1758cfa0ad2SJack F Vogel 		u16 flockdn:6;   /* 15:10 Reserved */
1768cfa0ad2SJack F Vogel 	} hsf_ctrl;
1778cfa0ad2SJack F Vogel 	u16 regval;
1788cfa0ad2SJack F Vogel };
1798cfa0ad2SJack F Vogel 
1808cfa0ad2SJack F Vogel /* ICH Flash Region Access Permissions */
1818cfa0ad2SJack F Vogel union ich8_hws_flash_regacc {
1828cfa0ad2SJack F Vogel 	struct ich8_flracc {
1838cfa0ad2SJack F Vogel 		u32 grra:8; /* 0:7 GbE region Read Access */
1848cfa0ad2SJack F Vogel 		u32 grwa:8; /* 8:15 GbE region Write Access */
1858cfa0ad2SJack F Vogel 		u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
1868cfa0ad2SJack F Vogel 		u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
1878cfa0ad2SJack F Vogel 	} hsf_flregacc;
1888cfa0ad2SJack F Vogel 	u16 regval;
1898cfa0ad2SJack F Vogel };
1908cfa0ad2SJack F Vogel 
1916ab6bfe3SJack F Vogel /**
1926ab6bfe3SJack F Vogel  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
1936ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
1946ab6bfe3SJack F Vogel  *
1956ab6bfe3SJack F Vogel  *  Test access to the PHY registers by reading the PHY ID registers.  If
1966ab6bfe3SJack F Vogel  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
1976ab6bfe3SJack F Vogel  *  otherwise assume the read PHY ID is correct if it is valid.
1986ab6bfe3SJack F Vogel  *
1996ab6bfe3SJack F Vogel  *  Assumes the sw/fw/hw semaphore is already acquired.
2006ab6bfe3SJack F Vogel  **/
2016ab6bfe3SJack F Vogel static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
2024dab5c37SJack F Vogel {
2036ab6bfe3SJack F Vogel 	u16 phy_reg = 0;
2046ab6bfe3SJack F Vogel 	u32 phy_id = 0;
2057609433eSJack F Vogel 	s32 ret_val = 0;
2066ab6bfe3SJack F Vogel 	u16 retry_count;
2077609433eSJack F Vogel 	u32 mac_reg = 0;
2084dab5c37SJack F Vogel 
2096ab6bfe3SJack F Vogel 	for (retry_count = 0; retry_count < 2; retry_count++) {
2106ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
2116ab6bfe3SJack F Vogel 		if (ret_val || (phy_reg == 0xFFFF))
2126ab6bfe3SJack F Vogel 			continue;
2136ab6bfe3SJack F Vogel 		phy_id = (u32)(phy_reg << 16);
2144dab5c37SJack F Vogel 
2156ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
2166ab6bfe3SJack F Vogel 		if (ret_val || (phy_reg == 0xFFFF)) {
2176ab6bfe3SJack F Vogel 			phy_id = 0;
2186ab6bfe3SJack F Vogel 			continue;
2196ab6bfe3SJack F Vogel 		}
2206ab6bfe3SJack F Vogel 		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
2216ab6bfe3SJack F Vogel 		break;
2226ab6bfe3SJack F Vogel 	}
2236ab6bfe3SJack F Vogel 
2246ab6bfe3SJack F Vogel 	if (hw->phy.id) {
2256ab6bfe3SJack F Vogel 		if  (hw->phy.id == phy_id)
2267609433eSJack F Vogel 			goto out;
2276ab6bfe3SJack F Vogel 	} else if (phy_id) {
2286ab6bfe3SJack F Vogel 		hw->phy.id = phy_id;
2296ab6bfe3SJack F Vogel 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
2307609433eSJack F Vogel 		goto out;
2316ab6bfe3SJack F Vogel 	}
2326ab6bfe3SJack F Vogel 
2336ab6bfe3SJack F Vogel 	/* In case the PHY needs to be in mdio slow mode,
2346ab6bfe3SJack F Vogel 	 * set slow mode and try to get the PHY id again.
2356ab6bfe3SJack F Vogel 	 */
2367609433eSJack F Vogel 	if (hw->mac.type < e1000_pch_lpt) {
2376ab6bfe3SJack F Vogel 		hw->phy.ops.release(hw);
2386ab6bfe3SJack F Vogel 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
2396ab6bfe3SJack F Vogel 		if (!ret_val)
2406ab6bfe3SJack F Vogel 			ret_val = e1000_get_phy_id(hw);
2416ab6bfe3SJack F Vogel 		hw->phy.ops.acquire(hw);
2427609433eSJack F Vogel 	}
2436ab6bfe3SJack F Vogel 
2447609433eSJack F Vogel 	if (ret_val)
2457609433eSJack F Vogel 		return FALSE;
2467609433eSJack F Vogel out:
247295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_lpt) {
248c80429ceSEric Joyner 		/* Only unforce SMBus if ME is not active */
249c80429ceSEric Joyner 		if (!(E1000_READ_REG(hw, E1000_FWSM) &
250c80429ceSEric Joyner 		    E1000_ICH_FWSM_FW_VALID)) {
2517609433eSJack F Vogel 			/* Unforce SMBus mode in PHY */
2527609433eSJack F Vogel 			hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
2537609433eSJack F Vogel 			phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
2547609433eSJack F Vogel 			hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
2557609433eSJack F Vogel 
2567609433eSJack F Vogel 			/* Unforce SMBus mode in MAC */
2577609433eSJack F Vogel 			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2587609433eSJack F Vogel 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
2597609433eSJack F Vogel 			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
2607609433eSJack F Vogel 		}
261c80429ceSEric Joyner 	}
2627609433eSJack F Vogel 
2637609433eSJack F Vogel 	return TRUE;
2647609433eSJack F Vogel }
2657609433eSJack F Vogel 
2667609433eSJack F Vogel /**
2677609433eSJack F Vogel  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
2687609433eSJack F Vogel  *  @hw: pointer to the HW structure
2697609433eSJack F Vogel  *
2707609433eSJack F Vogel  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
2717609433eSJack F Vogel  *  used to reset the PHY to a quiescent state when necessary.
2727609433eSJack F Vogel  **/
2738cc64f1eSJack F Vogel static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
2747609433eSJack F Vogel {
2757609433eSJack F Vogel 	u32 mac_reg;
2767609433eSJack F Vogel 
2777609433eSJack F Vogel 	DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
2787609433eSJack F Vogel 
2797609433eSJack F Vogel 	/* Set Phy Config Counter to 50msec */
2807609433eSJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
2817609433eSJack F Vogel 	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
2827609433eSJack F Vogel 	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
2837609433eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
2847609433eSJack F Vogel 
2857609433eSJack F Vogel 	/* Toggle LANPHYPC Value bit */
2867609433eSJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_CTRL);
2877609433eSJack F Vogel 	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
2887609433eSJack F Vogel 	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
2897609433eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
2907609433eSJack F Vogel 	E1000_WRITE_FLUSH(hw);
291e760e292SSean Bruno 	msec_delay(1);
2927609433eSJack F Vogel 	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
2937609433eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
2947609433eSJack F Vogel 	E1000_WRITE_FLUSH(hw);
2957609433eSJack F Vogel 
2967609433eSJack F Vogel 	if (hw->mac.type < e1000_pch_lpt) {
2977609433eSJack F Vogel 		msec_delay(50);
2987609433eSJack F Vogel 	} else {
2997609433eSJack F Vogel 		u16 count = 20;
3007609433eSJack F Vogel 
3017609433eSJack F Vogel 		do {
3027609433eSJack F Vogel 			msec_delay(5);
3037609433eSJack F Vogel 		} while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
3047609433eSJack F Vogel 			   E1000_CTRL_EXT_LPCD) && count--);
3057609433eSJack F Vogel 
3067609433eSJack F Vogel 		msec_delay(30);
3077609433eSJack F Vogel 	}
3086ab6bfe3SJack F Vogel }
3096ab6bfe3SJack F Vogel 
3106ab6bfe3SJack F Vogel /**
3116ab6bfe3SJack F Vogel  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
3126ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
3136ab6bfe3SJack F Vogel  *
3146ab6bfe3SJack F Vogel  *  Workarounds/flow necessary for PHY initialization during driver load
3156ab6bfe3SJack F Vogel  *  and resume paths.
3166ab6bfe3SJack F Vogel  **/
3176ab6bfe3SJack F Vogel static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
3186ab6bfe3SJack F Vogel {
3196ab6bfe3SJack F Vogel 	u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
3206ab6bfe3SJack F Vogel 	s32 ret_val;
3216ab6bfe3SJack F Vogel 
3226ab6bfe3SJack F Vogel 	DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
3236ab6bfe3SJack F Vogel 
3246ab6bfe3SJack F Vogel 	/* Gate automatic PHY configuration by hardware on managed and
3256ab6bfe3SJack F Vogel 	 * non-managed 82579 and newer adapters.
3266ab6bfe3SJack F Vogel 	 */
3276ab6bfe3SJack F Vogel 	e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3286ab6bfe3SJack F Vogel 
3298cc64f1eSJack F Vogel 	/* It is not possible to be certain of the current state of ULP
3308cc64f1eSJack F Vogel 	 * so forcibly disable it.
3318cc64f1eSJack F Vogel 	 */
3328cc64f1eSJack F Vogel 	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
3338cc64f1eSJack F Vogel 	e1000_disable_ulp_lpt_lp(hw, TRUE);
3348cc64f1eSJack F Vogel 
3356ab6bfe3SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
3366ab6bfe3SJack F Vogel 	if (ret_val) {
3376ab6bfe3SJack F Vogel 		DEBUGOUT("Failed to initialize PHY flow\n");
3386ab6bfe3SJack F Vogel 		goto out;
3396ab6bfe3SJack F Vogel 	}
3406ab6bfe3SJack F Vogel 
3416ab6bfe3SJack F Vogel 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
3426ab6bfe3SJack F Vogel 	 * inaccessible and resetting the PHY is not blocked, toggle the
3436ab6bfe3SJack F Vogel 	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
3446ab6bfe3SJack F Vogel 	 */
3456ab6bfe3SJack F Vogel 	switch (hw->mac.type) {
3466ab6bfe3SJack F Vogel 	case e1000_pch_lpt:
347c80429ceSEric Joyner 	case e1000_pch_spt:
348*6fe4c0a0SSean Bruno 	case e1000_pch_cnp:
3496ab6bfe3SJack F Vogel 		if (e1000_phy_is_accessible_pchlan(hw))
3506ab6bfe3SJack F Vogel 			break;
3516ab6bfe3SJack F Vogel 
3526ab6bfe3SJack F Vogel 		/* Before toggling LANPHYPC, see if PHY is accessible by
3536ab6bfe3SJack F Vogel 		 * forcing MAC to SMBus mode first.
3546ab6bfe3SJack F Vogel 		 */
3556ab6bfe3SJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3566ab6bfe3SJack F Vogel 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
3576ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
3586ab6bfe3SJack F Vogel 
3597609433eSJack F Vogel 		/* Wait 50 milliseconds for MAC to finish any retries
3607609433eSJack F Vogel 		 * that it might be trying to perform from previous
3617609433eSJack F Vogel 		 * attempts to acknowledge any phy read requests.
3627609433eSJack F Vogel 		 */
3637609433eSJack F Vogel 		 msec_delay(50);
3647609433eSJack F Vogel 
3656ab6bfe3SJack F Vogel 		/* fall-through */
3666ab6bfe3SJack F Vogel 	case e1000_pch2lan:
3677609433eSJack F Vogel 		if (e1000_phy_is_accessible_pchlan(hw))
3686ab6bfe3SJack F Vogel 			break;
3696ab6bfe3SJack F Vogel 
3706ab6bfe3SJack F Vogel 		/* fall-through */
3716ab6bfe3SJack F Vogel 	case e1000_pchlan:
3726ab6bfe3SJack F Vogel 		if ((hw->mac.type == e1000_pchlan) &&
3736ab6bfe3SJack F Vogel 		    (fwsm & E1000_ICH_FWSM_FW_VALID))
3746ab6bfe3SJack F Vogel 			break;
3756ab6bfe3SJack F Vogel 
3766ab6bfe3SJack F Vogel 		if (hw->phy.ops.check_reset_block(hw)) {
3776ab6bfe3SJack F Vogel 			DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
3787609433eSJack F Vogel 			ret_val = -E1000_ERR_PHY;
3796ab6bfe3SJack F Vogel 			break;
3806ab6bfe3SJack F Vogel 		}
3816ab6bfe3SJack F Vogel 
3827609433eSJack F Vogel 		/* Toggle LANPHYPC Value bit */
3837609433eSJack F Vogel 		e1000_toggle_lanphypc_pch_lpt(hw);
3847609433eSJack F Vogel 		if (hw->mac.type >= e1000_pch_lpt) {
3857609433eSJack F Vogel 			if (e1000_phy_is_accessible_pchlan(hw))
3867609433eSJack F Vogel 				break;
3876ab6bfe3SJack F Vogel 
3886ab6bfe3SJack F Vogel 			/* Toggling LANPHYPC brings the PHY out of SMBus mode
3897609433eSJack F Vogel 			 * so ensure that the MAC is also out of SMBus mode
3906ab6bfe3SJack F Vogel 			 */
3916ab6bfe3SJack F Vogel 			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3926ab6bfe3SJack F Vogel 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
3936ab6bfe3SJack F Vogel 			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
3946ab6bfe3SJack F Vogel 
3957609433eSJack F Vogel 			if (e1000_phy_is_accessible_pchlan(hw))
3967609433eSJack F Vogel 				break;
3977609433eSJack F Vogel 
3987609433eSJack F Vogel 			ret_val = -E1000_ERR_PHY;
3996ab6bfe3SJack F Vogel 		}
4006ab6bfe3SJack F Vogel 		break;
4016ab6bfe3SJack F Vogel 	default:
4026ab6bfe3SJack F Vogel 		break;
4036ab6bfe3SJack F Vogel 	}
4046ab6bfe3SJack F Vogel 
4056ab6bfe3SJack F Vogel 	hw->phy.ops.release(hw);
4067609433eSJack F Vogel 	if (!ret_val) {
4077609433eSJack F Vogel 
4087609433eSJack F Vogel 		/* Check to see if able to reset PHY.  Print error if not */
4097609433eSJack F Vogel 		if (hw->phy.ops.check_reset_block(hw)) {
4107609433eSJack F Vogel 			ERROR_REPORT("Reset blocked by ME\n");
4117609433eSJack F Vogel 			goto out;
4127609433eSJack F Vogel 		}
4136ab6bfe3SJack F Vogel 
4146ab6bfe3SJack F Vogel 		/* Reset the PHY before any access to it.  Doing so, ensures
4156ab6bfe3SJack F Vogel 		 * that the PHY is in a known good state before we read/write
4166ab6bfe3SJack F Vogel 		 * PHY registers.  The generic reset is sufficient here,
4176ab6bfe3SJack F Vogel 		 * because we haven't determined the PHY type yet.
4186ab6bfe3SJack F Vogel 		 */
4196ab6bfe3SJack F Vogel 		ret_val = e1000_phy_hw_reset_generic(hw);
4207609433eSJack F Vogel 		if (ret_val)
4217609433eSJack F Vogel 			goto out;
4227609433eSJack F Vogel 
4237609433eSJack F Vogel 		/* On a successful reset, possibly need to wait for the PHY
4247609433eSJack F Vogel 		 * to quiesce to an accessible state before returning control
4257609433eSJack F Vogel 		 * to the calling function.  If the PHY does not quiesce, then
4267609433eSJack F Vogel 		 * return E1000E_BLK_PHY_RESET, as this is the condition that
4277609433eSJack F Vogel 		 *  the PHY is in.
4287609433eSJack F Vogel 		 */
4297609433eSJack F Vogel 		ret_val = hw->phy.ops.check_reset_block(hw);
4307609433eSJack F Vogel 		if (ret_val)
4317609433eSJack F Vogel 			ERROR_REPORT("ME blocked access to PHY after reset\n");
4327609433eSJack F Vogel 	}
4336ab6bfe3SJack F Vogel 
4346ab6bfe3SJack F Vogel out:
4356ab6bfe3SJack F Vogel 	/* Ungate automatic PHY configuration on non-managed 82579 */
4366ab6bfe3SJack F Vogel 	if ((hw->mac.type == e1000_pch2lan) &&
4376ab6bfe3SJack F Vogel 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
4386ab6bfe3SJack F Vogel 		msec_delay(10);
4396ab6bfe3SJack F Vogel 		e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
4406ab6bfe3SJack F Vogel 	}
4416ab6bfe3SJack F Vogel 
4426ab6bfe3SJack F Vogel 	return ret_val;
4434dab5c37SJack F Vogel }
4444dab5c37SJack F Vogel 
4458cfa0ad2SJack F Vogel /**
4469d81738fSJack F Vogel  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
4479d81738fSJack F Vogel  *  @hw: pointer to the HW structure
4489d81738fSJack F Vogel  *
4499d81738fSJack F Vogel  *  Initialize family-specific PHY parameters and function pointers.
4509d81738fSJack F Vogel  **/
4519d81738fSJack F Vogel static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
4529d81738fSJack F Vogel {
4539d81738fSJack F Vogel 	struct e1000_phy_info *phy = &hw->phy;
4546ab6bfe3SJack F Vogel 	s32 ret_val;
4559d81738fSJack F Vogel 
4569d81738fSJack F Vogel 	DEBUGFUNC("e1000_init_phy_params_pchlan");
4579d81738fSJack F Vogel 
4589d81738fSJack F Vogel 	phy->addr		= 1;
4599d81738fSJack F Vogel 	phy->reset_delay_us	= 100;
4609d81738fSJack F Vogel 
4619d81738fSJack F Vogel 	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
4629d81738fSJack F Vogel 	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
4639d81738fSJack F Vogel 	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
4644dab5c37SJack F Vogel 	phy->ops.set_page	= e1000_set_page_igp;
4659d81738fSJack F Vogel 	phy->ops.read_reg	= e1000_read_phy_reg_hv;
4664edd8523SJack F Vogel 	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
4674dab5c37SJack F Vogel 	phy->ops.read_reg_page	= e1000_read_phy_reg_page_hv;
4689d81738fSJack F Vogel 	phy->ops.release	= e1000_release_swflag_ich8lan;
4699d81738fSJack F Vogel 	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
4704edd8523SJack F Vogel 	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
4714edd8523SJack F Vogel 	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
4729d81738fSJack F Vogel 	phy->ops.write_reg	= e1000_write_phy_reg_hv;
4734edd8523SJack F Vogel 	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
4744dab5c37SJack F Vogel 	phy->ops.write_reg_page	= e1000_write_phy_reg_page_hv;
4759d81738fSJack F Vogel 	phy->ops.power_up	= e1000_power_up_phy_copper;
4769d81738fSJack F Vogel 	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
4779d81738fSJack F Vogel 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
4789d81738fSJack F Vogel 
4799d81738fSJack F Vogel 	phy->id = e1000_phy_unknown;
4806ab6bfe3SJack F Vogel 
4816ab6bfe3SJack F Vogel 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
4826ab6bfe3SJack F Vogel 	if (ret_val)
4836ab6bfe3SJack F Vogel 		return ret_val;
4846ab6bfe3SJack F Vogel 
4856ab6bfe3SJack F Vogel 	if (phy->id == e1000_phy_unknown)
4867d9119bdSJack F Vogel 		switch (hw->mac.type) {
4877d9119bdSJack F Vogel 		default:
488a69ed8dfSJack F Vogel 			ret_val = e1000_get_phy_id(hw);
489a69ed8dfSJack F Vogel 			if (ret_val)
4906ab6bfe3SJack F Vogel 				return ret_val;
4917d9119bdSJack F Vogel 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
4927d9119bdSJack F Vogel 				break;
4937d9119bdSJack F Vogel 			/* fall-through */
4947d9119bdSJack F Vogel 		case e1000_pch2lan:
4956ab6bfe3SJack F Vogel 		case e1000_pch_lpt:
496c80429ceSEric Joyner 		case e1000_pch_spt:
497*6fe4c0a0SSean Bruno 		case e1000_pch_cnp:
4986ab6bfe3SJack F Vogel 			/* In case the PHY needs to be in mdio slow mode,
499a69ed8dfSJack F Vogel 			 * set slow mode and try to get the PHY id again.
500a69ed8dfSJack F Vogel 			 */
501a69ed8dfSJack F Vogel 			ret_val = e1000_set_mdio_slow_mode_hv(hw);
502a69ed8dfSJack F Vogel 			if (ret_val)
5036ab6bfe3SJack F Vogel 				return ret_val;
504a69ed8dfSJack F Vogel 			ret_val = e1000_get_phy_id(hw);
505a69ed8dfSJack F Vogel 			if (ret_val)
5066ab6bfe3SJack F Vogel 				return ret_val;
5077d9119bdSJack F Vogel 			break;
508a69ed8dfSJack F Vogel 		}
5099d81738fSJack F Vogel 	phy->type = e1000_get_phy_type_from_id(phy->id);
5109d81738fSJack F Vogel 
5114edd8523SJack F Vogel 	switch (phy->type) {
5124edd8523SJack F Vogel 	case e1000_phy_82577:
5137d9119bdSJack F Vogel 	case e1000_phy_82579:
5146ab6bfe3SJack F Vogel 	case e1000_phy_i217:
5159d81738fSJack F Vogel 		phy->ops.check_polarity = e1000_check_polarity_82577;
5169d81738fSJack F Vogel 		phy->ops.force_speed_duplex =
5179d81738fSJack F Vogel 			e1000_phy_force_speed_duplex_82577;
5189d81738fSJack F Vogel 		phy->ops.get_cable_length = e1000_get_cable_length_82577;
5199d81738fSJack F Vogel 		phy->ops.get_info = e1000_get_phy_info_82577;
5209d81738fSJack F Vogel 		phy->ops.commit = e1000_phy_sw_reset_generic;
5218ec87fc5SJack F Vogel 		break;
5224edd8523SJack F Vogel 	case e1000_phy_82578:
5234edd8523SJack F Vogel 		phy->ops.check_polarity = e1000_check_polarity_m88;
5244edd8523SJack F Vogel 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
5254edd8523SJack F Vogel 		phy->ops.get_cable_length = e1000_get_cable_length_m88;
5264edd8523SJack F Vogel 		phy->ops.get_info = e1000_get_phy_info_m88;
5274edd8523SJack F Vogel 		break;
5284edd8523SJack F Vogel 	default:
5294edd8523SJack F Vogel 		ret_val = -E1000_ERR_PHY;
5304edd8523SJack F Vogel 		break;
5319d81738fSJack F Vogel 	}
5329d81738fSJack F Vogel 
5339d81738fSJack F Vogel 	return ret_val;
5349d81738fSJack F Vogel }
5359d81738fSJack F Vogel 
5369d81738fSJack F Vogel /**
5378cfa0ad2SJack F Vogel  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
5388cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
5398cfa0ad2SJack F Vogel  *
5408cfa0ad2SJack F Vogel  *  Initialize family-specific PHY parameters and function pointers.
5418cfa0ad2SJack F Vogel  **/
5428cfa0ad2SJack F Vogel static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
5438cfa0ad2SJack F Vogel {
5448cfa0ad2SJack F Vogel 	struct e1000_phy_info *phy = &hw->phy;
5456ab6bfe3SJack F Vogel 	s32 ret_val;
5468cfa0ad2SJack F Vogel 	u16 i = 0;
5478cfa0ad2SJack F Vogel 
5488cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_init_phy_params_ich8lan");
5498cfa0ad2SJack F Vogel 
5508cfa0ad2SJack F Vogel 	phy->addr		= 1;
5518cfa0ad2SJack F Vogel 	phy->reset_delay_us	= 100;
5528cfa0ad2SJack F Vogel 
5538cfa0ad2SJack F Vogel 	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
5548cfa0ad2SJack F Vogel 	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
5558cfa0ad2SJack F Vogel 	phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
5568cfa0ad2SJack F Vogel 	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
5578cfa0ad2SJack F Vogel 	phy->ops.read_reg	= e1000_read_phy_reg_igp;
5588cfa0ad2SJack F Vogel 	phy->ops.release	= e1000_release_swflag_ich8lan;
5598cfa0ad2SJack F Vogel 	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
5608cfa0ad2SJack F Vogel 	phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
5618cfa0ad2SJack F Vogel 	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
5628cfa0ad2SJack F Vogel 	phy->ops.write_reg	= e1000_write_phy_reg_igp;
5638cfa0ad2SJack F Vogel 	phy->ops.power_up	= e1000_power_up_phy_copper;
5648cfa0ad2SJack F Vogel 	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
5658cfa0ad2SJack F Vogel 
5666ab6bfe3SJack F Vogel 	/* We may need to do this twice - once for IGP and if that fails,
5678cfa0ad2SJack F Vogel 	 * we'll set BM func pointers and try again
5688cfa0ad2SJack F Vogel 	 */
5698cfa0ad2SJack F Vogel 	ret_val = e1000_determine_phy_address(hw);
5708cfa0ad2SJack F Vogel 	if (ret_val) {
5718cfa0ad2SJack F Vogel 		phy->ops.write_reg = e1000_write_phy_reg_bm;
5728cfa0ad2SJack F Vogel 		phy->ops.read_reg  = e1000_read_phy_reg_bm;
5738cfa0ad2SJack F Vogel 		ret_val = e1000_determine_phy_address(hw);
5748cfa0ad2SJack F Vogel 		if (ret_val) {
575d035aa2dSJack F Vogel 			DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
5766ab6bfe3SJack F Vogel 			return ret_val;
5778cfa0ad2SJack F Vogel 		}
5788cfa0ad2SJack F Vogel 	}
5798cfa0ad2SJack F Vogel 
5808cfa0ad2SJack F Vogel 	phy->id = 0;
5818cfa0ad2SJack F Vogel 	while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
5828cfa0ad2SJack F Vogel 	       (i++ < 100)) {
5838cfa0ad2SJack F Vogel 		msec_delay(1);
5848cfa0ad2SJack F Vogel 		ret_val = e1000_get_phy_id(hw);
5858cfa0ad2SJack F Vogel 		if (ret_val)
5866ab6bfe3SJack F Vogel 			return ret_val;
5878cfa0ad2SJack F Vogel 	}
5888cfa0ad2SJack F Vogel 
5898cfa0ad2SJack F Vogel 	/* Verify phy id */
5908cfa0ad2SJack F Vogel 	switch (phy->id) {
5918cfa0ad2SJack F Vogel 	case IGP03E1000_E_PHY_ID:
5928cfa0ad2SJack F Vogel 		phy->type = e1000_phy_igp_3;
5938cfa0ad2SJack F Vogel 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
5944edd8523SJack F Vogel 		phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
5954edd8523SJack F Vogel 		phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
5964edd8523SJack F Vogel 		phy->ops.get_info = e1000_get_phy_info_igp;
5974edd8523SJack F Vogel 		phy->ops.check_polarity = e1000_check_polarity_igp;
5984edd8523SJack F Vogel 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
5998cfa0ad2SJack F Vogel 		break;
6008cfa0ad2SJack F Vogel 	case IFE_E_PHY_ID:
6018cfa0ad2SJack F Vogel 	case IFE_PLUS_E_PHY_ID:
6028cfa0ad2SJack F Vogel 	case IFE_C_E_PHY_ID:
6038cfa0ad2SJack F Vogel 		phy->type = e1000_phy_ife;
6048cfa0ad2SJack F Vogel 		phy->autoneg_mask = E1000_ALL_NOT_GIG;
6054edd8523SJack F Vogel 		phy->ops.get_info = e1000_get_phy_info_ife;
6064edd8523SJack F Vogel 		phy->ops.check_polarity = e1000_check_polarity_ife;
6074edd8523SJack F Vogel 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
6088cfa0ad2SJack F Vogel 		break;
6098cfa0ad2SJack F Vogel 	case BME1000_E_PHY_ID:
6108cfa0ad2SJack F Vogel 		phy->type = e1000_phy_bm;
6118cfa0ad2SJack F Vogel 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
6128cfa0ad2SJack F Vogel 		phy->ops.read_reg = e1000_read_phy_reg_bm;
6138cfa0ad2SJack F Vogel 		phy->ops.write_reg = e1000_write_phy_reg_bm;
6148cfa0ad2SJack F Vogel 		phy->ops.commit = e1000_phy_sw_reset_generic;
6154edd8523SJack F Vogel 		phy->ops.get_info = e1000_get_phy_info_m88;
6164edd8523SJack F Vogel 		phy->ops.check_polarity = e1000_check_polarity_m88;
6174edd8523SJack F Vogel 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
6188cfa0ad2SJack F Vogel 		break;
6198cfa0ad2SJack F Vogel 	default:
6206ab6bfe3SJack F Vogel 		return -E1000_ERR_PHY;
6216ab6bfe3SJack F Vogel 		break;
6228cfa0ad2SJack F Vogel 	}
6238cfa0ad2SJack F Vogel 
6246ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
6258cfa0ad2SJack F Vogel }
6268cfa0ad2SJack F Vogel 
6278cfa0ad2SJack F Vogel /**
6288cfa0ad2SJack F Vogel  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
6298cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
6308cfa0ad2SJack F Vogel  *
6318cfa0ad2SJack F Vogel  *  Initialize family-specific NVM parameters and function
6328cfa0ad2SJack F Vogel  *  pointers.
6338cfa0ad2SJack F Vogel  **/
6348cfa0ad2SJack F Vogel static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
6358cfa0ad2SJack F Vogel {
6368cfa0ad2SJack F Vogel 	struct e1000_nvm_info *nvm = &hw->nvm;
637daf9197cSJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
6388cfa0ad2SJack F Vogel 	u32 gfpreg, sector_base_addr, sector_end_addr;
6398cfa0ad2SJack F Vogel 	u16 i;
640c80429ceSEric Joyner 	u32 nvm_size;
6418cfa0ad2SJack F Vogel 
6428cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_init_nvm_params_ich8lan");
6438cfa0ad2SJack F Vogel 
6448cc64f1eSJack F Vogel 	nvm->type = e1000_nvm_flash_sw;
645c80429ceSEric Joyner 
646295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt) {
647c80429ceSEric Joyner 		/* in SPT, gfpreg doesn't exist. NVM size is taken from the
648c80429ceSEric Joyner 		 * STRAP register. This is because in SPT the GbE Flash region
649c80429ceSEric Joyner 		 * is no longer accessed through the flash registers. Instead,
650c80429ceSEric Joyner 		 * the mechanism has changed, and the Flash region access
651c80429ceSEric Joyner 		 * registers are now implemented in GbE memory space.
652c80429ceSEric Joyner 		 */
653c80429ceSEric Joyner 		nvm->flash_base_addr = 0;
654c80429ceSEric Joyner 		nvm_size =
655c80429ceSEric Joyner 		    (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
656c80429ceSEric Joyner 		    * NVM_SIZE_MULTIPLIER;
657c80429ceSEric Joyner 		nvm->flash_bank_size = nvm_size / 2;
658c80429ceSEric Joyner 		/* Adjust to word count */
659c80429ceSEric Joyner 		nvm->flash_bank_size /= sizeof(u16);
660c80429ceSEric Joyner 		/* Set the base address for flash register access */
661c80429ceSEric Joyner 		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
662c80429ceSEric Joyner 	} else {
663c80429ceSEric Joyner 		/* Can't read flash registers if register set isn't mapped. */
6648cfa0ad2SJack F Vogel 		if (!hw->flash_address) {
6658cfa0ad2SJack F Vogel 			DEBUGOUT("ERROR: Flash registers not mapped\n");
6666ab6bfe3SJack F Vogel 			return -E1000_ERR_CONFIG;
6678cfa0ad2SJack F Vogel 		}
6688cfa0ad2SJack F Vogel 
6698cfa0ad2SJack F Vogel 		gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
6708cfa0ad2SJack F Vogel 
6716ab6bfe3SJack F Vogel 		/* sector_X_addr is a "sector"-aligned address (4096 bytes)
6728cfa0ad2SJack F Vogel 		 * Add 1 to sector_end_addr since this sector is included in
6738cfa0ad2SJack F Vogel 		 * the overall size.
6748cfa0ad2SJack F Vogel 		 */
6758cfa0ad2SJack F Vogel 		sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
6768cfa0ad2SJack F Vogel 		sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
6778cfa0ad2SJack F Vogel 
6788cfa0ad2SJack F Vogel 		/* flash_base_addr is byte-aligned */
679c80429ceSEric Joyner 		nvm->flash_base_addr = sector_base_addr
680c80429ceSEric Joyner 				       << FLASH_SECTOR_ADDR_SHIFT;
6818cfa0ad2SJack F Vogel 
6826ab6bfe3SJack F Vogel 		/* find total size of the NVM, then cut in half since the total
6838cfa0ad2SJack F Vogel 		 * size represents two separate NVM banks.
6848cfa0ad2SJack F Vogel 		 */
6857609433eSJack F Vogel 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
6867609433eSJack F Vogel 					<< FLASH_SECTOR_ADDR_SHIFT);
6878cfa0ad2SJack F Vogel 		nvm->flash_bank_size /= 2;
6888cfa0ad2SJack F Vogel 		/* Adjust to word count */
6898cfa0ad2SJack F Vogel 		nvm->flash_bank_size /= sizeof(u16);
690c80429ceSEric Joyner 	}
6918cfa0ad2SJack F Vogel 
6928cfa0ad2SJack F Vogel 	nvm->word_size = E1000_SHADOW_RAM_WORDS;
6938cfa0ad2SJack F Vogel 
6948cfa0ad2SJack F Vogel 	/* Clear shadow ram */
6958cfa0ad2SJack F Vogel 	for (i = 0; i < nvm->word_size; i++) {
6968cfa0ad2SJack F Vogel 		dev_spec->shadow_ram[i].modified = FALSE;
6978cfa0ad2SJack F Vogel 		dev_spec->shadow_ram[i].value    = 0xFFFF;
6988cfa0ad2SJack F Vogel 	}
6998cfa0ad2SJack F Vogel 
700ab2e3f79SStephen Hurd 	E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
701ab2e3f79SStephen Hurd 	E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
702ab2e3f79SStephen Hurd 
7038cfa0ad2SJack F Vogel 	/* Function Pointers */
7044edd8523SJack F Vogel 	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
7054edd8523SJack F Vogel 	nvm->ops.release	= e1000_release_nvm_ich8lan;
706295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt) {
707c80429ceSEric Joyner 		nvm->ops.read	= e1000_read_nvm_spt;
708c80429ceSEric Joyner 		nvm->ops.update	= e1000_update_nvm_checksum_spt;
709c80429ceSEric Joyner 	} else {
7108cfa0ad2SJack F Vogel 		nvm->ops.read	= e1000_read_nvm_ich8lan;
7118cfa0ad2SJack F Vogel 		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;
712c80429ceSEric Joyner 	}
7138cfa0ad2SJack F Vogel 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
7148cfa0ad2SJack F Vogel 	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
7158cfa0ad2SJack F Vogel 	nvm->ops.write		= e1000_write_nvm_ich8lan;
7168cfa0ad2SJack F Vogel 
7176ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
7188cfa0ad2SJack F Vogel }
7198cfa0ad2SJack F Vogel 
7208cfa0ad2SJack F Vogel /**
7218cfa0ad2SJack F Vogel  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
7228cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
7238cfa0ad2SJack F Vogel  *
7248cfa0ad2SJack F Vogel  *  Initialize family-specific MAC parameters and function
7258cfa0ad2SJack F Vogel  *  pointers.
7268cfa0ad2SJack F Vogel  **/
7278cfa0ad2SJack F Vogel static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
7288cfa0ad2SJack F Vogel {
7298cfa0ad2SJack F Vogel 	struct e1000_mac_info *mac = &hw->mac;
7308cfa0ad2SJack F Vogel 
7318cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_init_mac_params_ich8lan");
7328cfa0ad2SJack F Vogel 
7338cfa0ad2SJack F Vogel 	/* Set media type function pointer */
7348cfa0ad2SJack F Vogel 	hw->phy.media_type = e1000_media_type_copper;
7358cfa0ad2SJack F Vogel 
7368cfa0ad2SJack F Vogel 	/* Set mta register count */
7378cfa0ad2SJack F Vogel 	mac->mta_reg_count = 32;
7388cfa0ad2SJack F Vogel 	/* Set rar entry count */
7398cfa0ad2SJack F Vogel 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
7408cfa0ad2SJack F Vogel 	if (mac->type == e1000_ich8lan)
7418cfa0ad2SJack F Vogel 		mac->rar_entry_count--;
7428cfa0ad2SJack F Vogel 	/* Set if part includes ASF firmware */
7438cfa0ad2SJack F Vogel 	mac->asf_firmware_present = TRUE;
7448ec87fc5SJack F Vogel 	/* FWSM register */
7458ec87fc5SJack F Vogel 	mac->has_fwsm = TRUE;
7468ec87fc5SJack F Vogel 	/* ARC subsystem not supported */
7478ec87fc5SJack F Vogel 	mac->arc_subsystem_valid = FALSE;
7484edd8523SJack F Vogel 	/* Adaptive IFS supported */
7494edd8523SJack F Vogel 	mac->adaptive_ifs = TRUE;
7508cfa0ad2SJack F Vogel 
7518cfa0ad2SJack F Vogel 	/* Function pointers */
7528cfa0ad2SJack F Vogel 
7538cfa0ad2SJack F Vogel 	/* bus type/speed/width */
7548cfa0ad2SJack F Vogel 	mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
755daf9197cSJack F Vogel 	/* function id */
756daf9197cSJack F Vogel 	mac->ops.set_lan_id = e1000_set_lan_id_single_port;
7578cfa0ad2SJack F Vogel 	/* reset */
7588cfa0ad2SJack F Vogel 	mac->ops.reset_hw = e1000_reset_hw_ich8lan;
7598cfa0ad2SJack F Vogel 	/* hw initialization */
7608cfa0ad2SJack F Vogel 	mac->ops.init_hw = e1000_init_hw_ich8lan;
7618cfa0ad2SJack F Vogel 	/* link setup */
7628cfa0ad2SJack F Vogel 	mac->ops.setup_link = e1000_setup_link_ich8lan;
7638cfa0ad2SJack F Vogel 	/* physical interface setup */
7648cfa0ad2SJack F Vogel 	mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
7658cfa0ad2SJack F Vogel 	/* check for link */
7664edd8523SJack F Vogel 	mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
7678cfa0ad2SJack F Vogel 	/* link info */
7688cfa0ad2SJack F Vogel 	mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
7698cfa0ad2SJack F Vogel 	/* multicast address update */
7708cfa0ad2SJack F Vogel 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
771d035aa2dSJack F Vogel 	/* clear hardware counters */
772d035aa2dSJack F Vogel 	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
773d035aa2dSJack F Vogel 
7746ab6bfe3SJack F Vogel 	/* LED and other operations */
775d035aa2dSJack F Vogel 	switch (mac->type) {
776d035aa2dSJack F Vogel 	case e1000_ich8lan:
777d035aa2dSJack F Vogel 	case e1000_ich9lan:
778d035aa2dSJack F Vogel 	case e1000_ich10lan:
7797d9119bdSJack F Vogel 		/* check management mode */
7807d9119bdSJack F Vogel 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
781d035aa2dSJack F Vogel 		/* ID LED init */
782d035aa2dSJack F Vogel 		mac->ops.id_led_init = e1000_id_led_init_generic;
7838cfa0ad2SJack F Vogel 		/* blink LED */
7848cfa0ad2SJack F Vogel 		mac->ops.blink_led = e1000_blink_led_generic;
7858cfa0ad2SJack F Vogel 		/* setup LED */
7868cfa0ad2SJack F Vogel 		mac->ops.setup_led = e1000_setup_led_generic;
7878cfa0ad2SJack F Vogel 		/* cleanup LED */
7888cfa0ad2SJack F Vogel 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
7898cfa0ad2SJack F Vogel 		/* turn on/off LED */
7908cfa0ad2SJack F Vogel 		mac->ops.led_on = e1000_led_on_ich8lan;
7918cfa0ad2SJack F Vogel 		mac->ops.led_off = e1000_led_off_ich8lan;
792d035aa2dSJack F Vogel 		break;
7937d9119bdSJack F Vogel 	case e1000_pch2lan:
7947d9119bdSJack F Vogel 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
7957d9119bdSJack F Vogel 		mac->ops.rar_set = e1000_rar_set_pch2lan;
7966ab6bfe3SJack F Vogel 		/* fall-through */
7976ab6bfe3SJack F Vogel 	case e1000_pch_lpt:
798c80429ceSEric Joyner 	case e1000_pch_spt:
799*6fe4c0a0SSean Bruno 	case e1000_pch_cnp:
800730d3130SJack F Vogel 		/* multicast address update for pch2 */
801730d3130SJack F Vogel 		mac->ops.update_mc_addr_list =
802730d3130SJack F Vogel 			e1000_update_mc_addr_list_pch2lan;
803c80429ceSEric Joyner 		/* fall-through */
8049d81738fSJack F Vogel 	case e1000_pchlan:
8057d9119bdSJack F Vogel 		/* check management mode */
8067d9119bdSJack F Vogel 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
8079d81738fSJack F Vogel 		/* ID LED init */
8089d81738fSJack F Vogel 		mac->ops.id_led_init = e1000_id_led_init_pchlan;
8099d81738fSJack F Vogel 		/* setup LED */
8109d81738fSJack F Vogel 		mac->ops.setup_led = e1000_setup_led_pchlan;
8119d81738fSJack F Vogel 		/* cleanup LED */
8129d81738fSJack F Vogel 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
8139d81738fSJack F Vogel 		/* turn on/off LED */
8149d81738fSJack F Vogel 		mac->ops.led_on = e1000_led_on_pchlan;
8159d81738fSJack F Vogel 		mac->ops.led_off = e1000_led_off_pchlan;
8169d81738fSJack F Vogel 		break;
817d035aa2dSJack F Vogel 	default:
818d035aa2dSJack F Vogel 		break;
819d035aa2dSJack F Vogel 	}
8208cfa0ad2SJack F Vogel 
821295df609SEric Joyner 	if (mac->type >= e1000_pch_lpt) {
8226ab6bfe3SJack F Vogel 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
8236ab6bfe3SJack F Vogel 		mac->ops.rar_set = e1000_rar_set_pch_lpt;
8246ab6bfe3SJack F Vogel 		mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
825e373323fSSean Bruno 		mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
8264dab5c37SJack F Vogel 	}
8274dab5c37SJack F Vogel 
8288cfa0ad2SJack F Vogel 	/* Enable PCS Lock-loss workaround for ICH8 */
8298cfa0ad2SJack F Vogel 	if (mac->type == e1000_ich8lan)
8308cfa0ad2SJack F Vogel 		e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
8318cfa0ad2SJack F Vogel 
832daf9197cSJack F Vogel 	return E1000_SUCCESS;
8338cfa0ad2SJack F Vogel }
8348cfa0ad2SJack F Vogel 
8358cfa0ad2SJack F Vogel /**
8366ab6bfe3SJack F Vogel  *  __e1000_access_emi_reg_locked - Read/write EMI register
8376ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
8386ab6bfe3SJack F Vogel  *  @addr: EMI address to program
8396ab6bfe3SJack F Vogel  *  @data: pointer to value to read/write from/to the EMI address
8406ab6bfe3SJack F Vogel  *  @read: boolean flag to indicate read or write
8416ab6bfe3SJack F Vogel  *
8426ab6bfe3SJack F Vogel  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
8436ab6bfe3SJack F Vogel  **/
8446ab6bfe3SJack F Vogel static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
8456ab6bfe3SJack F Vogel 					 u16 *data, bool read)
8466ab6bfe3SJack F Vogel {
8476ab6bfe3SJack F Vogel 	s32 ret_val;
8486ab6bfe3SJack F Vogel 
8496ab6bfe3SJack F Vogel 	DEBUGFUNC("__e1000_access_emi_reg_locked");
8506ab6bfe3SJack F Vogel 
8516ab6bfe3SJack F Vogel 	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
8526ab6bfe3SJack F Vogel 	if (ret_val)
8536ab6bfe3SJack F Vogel 		return ret_val;
8546ab6bfe3SJack F Vogel 
8556ab6bfe3SJack F Vogel 	if (read)
8566ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
8576ab6bfe3SJack F Vogel 						      data);
8586ab6bfe3SJack F Vogel 	else
8596ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
8606ab6bfe3SJack F Vogel 						       *data);
8616ab6bfe3SJack F Vogel 
8626ab6bfe3SJack F Vogel 	return ret_val;
8636ab6bfe3SJack F Vogel }
8646ab6bfe3SJack F Vogel 
8656ab6bfe3SJack F Vogel /**
8666ab6bfe3SJack F Vogel  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
8676ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
8686ab6bfe3SJack F Vogel  *  @addr: EMI address to program
8696ab6bfe3SJack F Vogel  *  @data: value to be read from the EMI address
8706ab6bfe3SJack F Vogel  *
8716ab6bfe3SJack F Vogel  *  Assumes the SW/FW/HW Semaphore is already acquired.
8726ab6bfe3SJack F Vogel  **/
8736ab6bfe3SJack F Vogel s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
8746ab6bfe3SJack F Vogel {
8756ab6bfe3SJack F Vogel 	DEBUGFUNC("e1000_read_emi_reg_locked");
8766ab6bfe3SJack F Vogel 
8776ab6bfe3SJack F Vogel 	return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
8786ab6bfe3SJack F Vogel }
8796ab6bfe3SJack F Vogel 
8806ab6bfe3SJack F Vogel /**
8816ab6bfe3SJack F Vogel  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
8826ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
8836ab6bfe3SJack F Vogel  *  @addr: EMI address to program
8846ab6bfe3SJack F Vogel  *  @data: value to be written to the EMI address
8856ab6bfe3SJack F Vogel  *
8866ab6bfe3SJack F Vogel  *  Assumes the SW/FW/HW Semaphore is already acquired.
8876ab6bfe3SJack F Vogel  **/
8887609433eSJack F Vogel s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
8896ab6bfe3SJack F Vogel {
8906ab6bfe3SJack F Vogel 	DEBUGFUNC("e1000_read_emi_reg_locked");
8916ab6bfe3SJack F Vogel 
8926ab6bfe3SJack F Vogel 	return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
8936ab6bfe3SJack F Vogel }
8946ab6bfe3SJack F Vogel 
8956ab6bfe3SJack F Vogel /**
8967d9119bdSJack F Vogel  *  e1000_set_eee_pchlan - Enable/disable EEE support
8977d9119bdSJack F Vogel  *  @hw: pointer to the HW structure
8987d9119bdSJack F Vogel  *
8996ab6bfe3SJack F Vogel  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
9006ab6bfe3SJack F Vogel  *  the link and the EEE capabilities of the link partner.  The LPI Control
9016ab6bfe3SJack F Vogel  *  register bits will remain set only if/when link is up.
9027609433eSJack F Vogel  *
9037609433eSJack F Vogel  *  EEE LPI must not be asserted earlier than one second after link is up.
9047609433eSJack F Vogel  *  On 82579, EEE LPI should not be enabled until such time otherwise there
9057609433eSJack F Vogel  *  can be link issues with some switches.  Other devices can have EEE LPI
9067609433eSJack F Vogel  *  enabled immediately upon link up since they have a timer in hardware which
9077609433eSJack F Vogel  *  prevents LPI from being asserted too early.
9087d9119bdSJack F Vogel  **/
9097609433eSJack F Vogel s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
9107d9119bdSJack F Vogel {
9114dab5c37SJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
9126ab6bfe3SJack F Vogel 	s32 ret_val;
9137609433eSJack F Vogel 	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
9147d9119bdSJack F Vogel 
9157d9119bdSJack F Vogel 	DEBUGFUNC("e1000_set_eee_pchlan");
9167d9119bdSJack F Vogel 
9177609433eSJack F Vogel 	switch (hw->phy.type) {
9187609433eSJack F Vogel 	case e1000_phy_82579:
9197609433eSJack F Vogel 		lpa = I82579_EEE_LP_ABILITY;
9207609433eSJack F Vogel 		pcs_status = I82579_EEE_PCS_STATUS;
9217609433eSJack F Vogel 		adv_addr = I82579_EEE_ADVERTISEMENT;
9227609433eSJack F Vogel 		break;
9237609433eSJack F Vogel 	case e1000_phy_i217:
9247609433eSJack F Vogel 		lpa = I217_EEE_LP_ABILITY;
9257609433eSJack F Vogel 		pcs_status = I217_EEE_PCS_STATUS;
9267609433eSJack F Vogel 		adv_addr = I217_EEE_ADVERTISEMENT;
9277609433eSJack F Vogel 		break;
9287609433eSJack F Vogel 	default:
9296ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
9307609433eSJack F Vogel 	}
9317d9119bdSJack F Vogel 
9326ab6bfe3SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
9337d9119bdSJack F Vogel 	if (ret_val)
9347d9119bdSJack F Vogel 		return ret_val;
9356ab6bfe3SJack F Vogel 
9366ab6bfe3SJack F Vogel 	ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
9376ab6bfe3SJack F Vogel 	if (ret_val)
9386ab6bfe3SJack F Vogel 		goto release;
9396ab6bfe3SJack F Vogel 
9406ab6bfe3SJack F Vogel 	/* Clear bits that enable EEE in various speeds */
9416ab6bfe3SJack F Vogel 	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
9426ab6bfe3SJack F Vogel 
9436ab6bfe3SJack F Vogel 	/* Enable EEE if not disabled by user */
9446ab6bfe3SJack F Vogel 	if (!dev_spec->eee_disable) {
9456ab6bfe3SJack F Vogel 		/* Save off link partner's EEE ability */
9466ab6bfe3SJack F Vogel 		ret_val = e1000_read_emi_reg_locked(hw, lpa,
9476ab6bfe3SJack F Vogel 						    &dev_spec->eee_lp_ability);
9486ab6bfe3SJack F Vogel 		if (ret_val)
9496ab6bfe3SJack F Vogel 			goto release;
9506ab6bfe3SJack F Vogel 
9517609433eSJack F Vogel 		/* Read EEE advertisement */
9527609433eSJack F Vogel 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
9537609433eSJack F Vogel 		if (ret_val)
9547609433eSJack F Vogel 			goto release;
9557609433eSJack F Vogel 
9566ab6bfe3SJack F Vogel 		/* Enable EEE only for speeds in which the link partner is
9577609433eSJack F Vogel 		 * EEE capable and for which we advertise EEE.
9586ab6bfe3SJack F Vogel 		 */
9597609433eSJack F Vogel 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
9606ab6bfe3SJack F Vogel 			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
9616ab6bfe3SJack F Vogel 
9627609433eSJack F Vogel 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
9636ab6bfe3SJack F Vogel 			hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
9646ab6bfe3SJack F Vogel 			if (data & NWAY_LPAR_100TX_FD_CAPS)
9656ab6bfe3SJack F Vogel 				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
9666ab6bfe3SJack F Vogel 			else
9676ab6bfe3SJack F Vogel 				/* EEE is not supported in 100Half, so ignore
9686ab6bfe3SJack F Vogel 				 * partner's EEE in 100 ability if full-duplex
9696ab6bfe3SJack F Vogel 				 * is not advertised.
9706ab6bfe3SJack F Vogel 				 */
9716ab6bfe3SJack F Vogel 				dev_spec->eee_lp_ability &=
9726ab6bfe3SJack F Vogel 				    ~I82579_EEE_100_SUPPORTED;
9736ab6bfe3SJack F Vogel 		}
9747609433eSJack F Vogel 	}
9756ab6bfe3SJack F Vogel 
9768cc64f1eSJack F Vogel 	if (hw->phy.type == e1000_phy_82579) {
9778cc64f1eSJack F Vogel 		ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
9788cc64f1eSJack F Vogel 						    &data);
9798cc64f1eSJack F Vogel 		if (ret_val)
9808cc64f1eSJack F Vogel 			goto release;
9818cc64f1eSJack F Vogel 
9828cc64f1eSJack F Vogel 		data &= ~I82579_LPI_100_PLL_SHUT;
9838cc64f1eSJack F Vogel 		ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
9848cc64f1eSJack F Vogel 						     data);
9858cc64f1eSJack F Vogel 	}
9868cc64f1eSJack F Vogel 
9876ab6bfe3SJack F Vogel 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
9886ab6bfe3SJack F Vogel 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
9896ab6bfe3SJack F Vogel 	if (ret_val)
9906ab6bfe3SJack F Vogel 		goto release;
9916ab6bfe3SJack F Vogel 
9926ab6bfe3SJack F Vogel 	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
9936ab6bfe3SJack F Vogel release:
9946ab6bfe3SJack F Vogel 	hw->phy.ops.release(hw);
9956ab6bfe3SJack F Vogel 
9966ab6bfe3SJack F Vogel 	return ret_val;
9976ab6bfe3SJack F Vogel }
9986ab6bfe3SJack F Vogel 
9996ab6bfe3SJack F Vogel /**
10006ab6bfe3SJack F Vogel  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
10016ab6bfe3SJack F Vogel  *  @hw:   pointer to the HW structure
10026ab6bfe3SJack F Vogel  *  @link: link up bool flag
10036ab6bfe3SJack F Vogel  *
10046ab6bfe3SJack F Vogel  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
10056ab6bfe3SJack F Vogel  *  preventing further DMA write requests.  Workaround the issue by disabling
10066ab6bfe3SJack F Vogel  *  the de-assertion of the clock request when in 1Gpbs mode.
10077609433eSJack F Vogel  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
10087609433eSJack F Vogel  *  speeds in order to avoid Tx hangs.
10096ab6bfe3SJack F Vogel  **/
10106ab6bfe3SJack F Vogel static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
10116ab6bfe3SJack F Vogel {
10126ab6bfe3SJack F Vogel 	u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
10137609433eSJack F Vogel 	u32 status = E1000_READ_REG(hw, E1000_STATUS);
10146ab6bfe3SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
10157609433eSJack F Vogel 	u16 reg;
10166ab6bfe3SJack F Vogel 
10177609433eSJack F Vogel 	if (link && (status & E1000_STATUS_SPEED_1000)) {
10186ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
10196ab6bfe3SJack F Vogel 		if (ret_val)
10206ab6bfe3SJack F Vogel 			return ret_val;
10216ab6bfe3SJack F Vogel 
10226ab6bfe3SJack F Vogel 		ret_val =
10236ab6bfe3SJack F Vogel 		    e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
10247609433eSJack F Vogel 					       &reg);
10256ab6bfe3SJack F Vogel 		if (ret_val)
10266ab6bfe3SJack F Vogel 			goto release;
10276ab6bfe3SJack F Vogel 
10286ab6bfe3SJack F Vogel 		ret_val =
10296ab6bfe3SJack F Vogel 		    e1000_write_kmrn_reg_locked(hw,
10306ab6bfe3SJack F Vogel 						E1000_KMRNCTRLSTA_K1_CONFIG,
10317609433eSJack F Vogel 						reg &
10326ab6bfe3SJack F Vogel 						~E1000_KMRNCTRLSTA_K1_ENABLE);
10336ab6bfe3SJack F Vogel 		if (ret_val)
10346ab6bfe3SJack F Vogel 			goto release;
10356ab6bfe3SJack F Vogel 
10366ab6bfe3SJack F Vogel 		usec_delay(10);
10376ab6bfe3SJack F Vogel 
10386ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_FEXTNVM6,
10396ab6bfe3SJack F Vogel 				fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
10406ab6bfe3SJack F Vogel 
10416ab6bfe3SJack F Vogel 		ret_val =
10426ab6bfe3SJack F Vogel 		    e1000_write_kmrn_reg_locked(hw,
10436ab6bfe3SJack F Vogel 						E1000_KMRNCTRLSTA_K1_CONFIG,
10447609433eSJack F Vogel 						reg);
10456ab6bfe3SJack F Vogel release:
10466ab6bfe3SJack F Vogel 		hw->phy.ops.release(hw);
10476ab6bfe3SJack F Vogel 	} else {
10486ab6bfe3SJack F Vogel 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
10497609433eSJack F Vogel 		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
10507609433eSJack F Vogel 
1051c80429ceSEric Joyner 		if ((hw->phy.revision > 5) || !link ||
1052c80429ceSEric Joyner 		    ((status & E1000_STATUS_SPEED_100) &&
10537609433eSJack F Vogel 		     (status & E1000_STATUS_FD)))
10547609433eSJack F Vogel 			goto update_fextnvm6;
10557609433eSJack F Vogel 
10567609433eSJack F Vogel 		ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
10577609433eSJack F Vogel 		if (ret_val)
10587609433eSJack F Vogel 			return ret_val;
10597609433eSJack F Vogel 
10607609433eSJack F Vogel 		/* Clear link status transmit timeout */
10617609433eSJack F Vogel 		reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
10627609433eSJack F Vogel 
10637609433eSJack F Vogel 		if (status & E1000_STATUS_SPEED_100) {
10647609433eSJack F Vogel 			/* Set inband Tx timeout to 5x10us for 100Half */
10657609433eSJack F Vogel 			reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
10667609433eSJack F Vogel 
10677609433eSJack F Vogel 			/* Do not extend the K1 entry latency for 100Half */
10687609433eSJack F Vogel 			fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
10697609433eSJack F Vogel 		} else {
10707609433eSJack F Vogel 			/* Set inband Tx timeout to 50x10us for 10Full/Half */
10717609433eSJack F Vogel 			reg |= 50 <<
10727609433eSJack F Vogel 			       I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
10737609433eSJack F Vogel 
10747609433eSJack F Vogel 			/* Extend the K1 entry latency for 10 Mbps */
10757609433eSJack F Vogel 			fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
10767609433eSJack F Vogel 		}
10777609433eSJack F Vogel 
10787609433eSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
10797609433eSJack F Vogel 		if (ret_val)
10807609433eSJack F Vogel 			return ret_val;
10817609433eSJack F Vogel 
10827609433eSJack F Vogel update_fextnvm6:
10837609433eSJack F Vogel 		E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
10846ab6bfe3SJack F Vogel 	}
10856ab6bfe3SJack F Vogel 
10866ab6bfe3SJack F Vogel 	return ret_val;
10876ab6bfe3SJack F Vogel }
10886ab6bfe3SJack F Vogel 
1089e373323fSSean Bruno static u64 e1000_ltr2ns(u16 ltr)
1090e373323fSSean Bruno {
1091e373323fSSean Bruno 	u32 value, scale;
1092e373323fSSean Bruno 
1093e373323fSSean Bruno 	/* Determine the latency in nsec based on the LTR value & scale */
1094e373323fSSean Bruno 	value = ltr & E1000_LTRV_VALUE_MASK;
1095e373323fSSean Bruno 	scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1096e373323fSSean Bruno 
1097e373323fSSean Bruno 	return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1098e373323fSSean Bruno }
1099e373323fSSean Bruno 
1100e373323fSSean Bruno /**
1101e373323fSSean Bruno  *  e1000_platform_pm_pch_lpt - Set platform power management values
1102e373323fSSean Bruno  *  @hw: pointer to the HW structure
1103e373323fSSean Bruno  *  @link: bool indicating link status
1104e373323fSSean Bruno  *
1105e373323fSSean Bruno  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1106e373323fSSean Bruno  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1107e373323fSSean Bruno  *  when link is up (which must not exceed the maximum latency supported
1108e373323fSSean Bruno  *  by the platform), otherwise specify there is no LTR requirement.
1109e373323fSSean Bruno  *  Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1110e373323fSSean Bruno  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1111e373323fSSean Bruno  *  Capability register set, on this device LTR is set by writing the
1112e373323fSSean Bruno  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1113e373323fSSean Bruno  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1114e373323fSSean Bruno  *  message to the PMC.
1115e373323fSSean Bruno  *
1116e373323fSSean Bruno  *  Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1117e373323fSSean Bruno  *  high-water mark.
1118e373323fSSean Bruno  **/
1119e373323fSSean Bruno static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1120e373323fSSean Bruno {
1121e373323fSSean Bruno 	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1122e373323fSSean Bruno 		  link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1123e373323fSSean Bruno 	u16 lat_enc = 0;	/* latency encoded */
1124e373323fSSean Bruno 	s32 obff_hwm = 0;
1125e373323fSSean Bruno 
1126e373323fSSean Bruno 	DEBUGFUNC("e1000_platform_pm_pch_lpt");
1127e373323fSSean Bruno 
1128e373323fSSean Bruno 	if (link) {
1129e373323fSSean Bruno 		u16 speed, duplex, scale = 0;
1130e373323fSSean Bruno 		u16 max_snoop, max_nosnoop;
1131e373323fSSean Bruno 		u16 max_ltr_enc;	/* max LTR latency encoded */
1132e373323fSSean Bruno 		s64 lat_ns;
1133e373323fSSean Bruno 		s64 value;
1134e373323fSSean Bruno 		u32 rxa;
1135e373323fSSean Bruno 
1136e373323fSSean Bruno 		if (!hw->mac.max_frame_size) {
1137e373323fSSean Bruno 			DEBUGOUT("max_frame_size not set.\n");
1138e373323fSSean Bruno 			return -E1000_ERR_CONFIG;
1139e373323fSSean Bruno 		}
1140e373323fSSean Bruno 
1141e373323fSSean Bruno 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1142e373323fSSean Bruno 		if (!speed) {
1143e373323fSSean Bruno 			DEBUGOUT("Speed not set.\n");
1144e373323fSSean Bruno 			return -E1000_ERR_CONFIG;
1145e373323fSSean Bruno 		}
1146e373323fSSean Bruno 
1147e373323fSSean Bruno 		/* Rx Packet Buffer Allocation size (KB) */
1148e373323fSSean Bruno 		rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1149e373323fSSean Bruno 
1150e373323fSSean Bruno 		/* Determine the maximum latency tolerated by the device.
1151e373323fSSean Bruno 		 *
1152e373323fSSean Bruno 		 * Per the PCIe spec, the tolerated latencies are encoded as
1153e373323fSSean Bruno 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1154e373323fSSean Bruno 		 * a 10-bit value (0-1023) to provide a range from 1 ns to
1155e373323fSSean Bruno 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1156e373323fSSean Bruno 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1157e373323fSSean Bruno 		 */
1158e373323fSSean Bruno 		lat_ns = ((s64)rxa * 1024 -
1159e373323fSSean Bruno 			  (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1160e373323fSSean Bruno 		if (lat_ns < 0)
1161e373323fSSean Bruno 			lat_ns = 0;
1162e373323fSSean Bruno 		else
1163e373323fSSean Bruno 			lat_ns /= speed;
1164e373323fSSean Bruno 		value = lat_ns;
1165e373323fSSean Bruno 
1166e373323fSSean Bruno 		while (value > E1000_LTRV_VALUE_MASK) {
1167e373323fSSean Bruno 			scale++;
1168e373323fSSean Bruno 			value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1169e373323fSSean Bruno 		}
1170e373323fSSean Bruno 		if (scale > E1000_LTRV_SCALE_MAX) {
1171e373323fSSean Bruno 			DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1172e373323fSSean Bruno 			return -E1000_ERR_CONFIG;
1173e373323fSSean Bruno 		}
1174e373323fSSean Bruno 		lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1175e373323fSSean Bruno 
1176e373323fSSean Bruno 		/* Determine the maximum latency tolerated by the platform */
1177e373323fSSean Bruno 		e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1178e373323fSSean Bruno 		e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1179e373323fSSean Bruno 		max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1180e373323fSSean Bruno 
1181e373323fSSean Bruno 		if (lat_enc > max_ltr_enc) {
1182e373323fSSean Bruno 			lat_enc = max_ltr_enc;
1183e373323fSSean Bruno 			lat_ns = e1000_ltr2ns(max_ltr_enc);
1184e373323fSSean Bruno 		}
1185e373323fSSean Bruno 
1186e373323fSSean Bruno 		if (lat_ns) {
1187e373323fSSean Bruno 			lat_ns *= speed * 1000;
1188e373323fSSean Bruno 			lat_ns /= 8;
1189e373323fSSean Bruno 			lat_ns /= 1000000000;
1190e373323fSSean Bruno 			obff_hwm = (s32)(rxa - lat_ns);
1191e373323fSSean Bruno 		}
1192e373323fSSean Bruno 		if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1193e373323fSSean Bruno 			DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1194e373323fSSean Bruno 			return -E1000_ERR_CONFIG;
1195e373323fSSean Bruno 		}
1196e373323fSSean Bruno 	}
1197e373323fSSean Bruno 
1198e373323fSSean Bruno 	/* Set Snoop and No-Snoop latencies the same */
1199e373323fSSean Bruno 	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1200e373323fSSean Bruno 	E1000_WRITE_REG(hw, E1000_LTRV, reg);
1201e373323fSSean Bruno 
1202e373323fSSean Bruno 	/* Set OBFF high water mark */
1203e373323fSSean Bruno 	reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1204e373323fSSean Bruno 	reg |= obff_hwm;
1205e373323fSSean Bruno 	E1000_WRITE_REG(hw, E1000_SVT, reg);
1206e373323fSSean Bruno 
1207e373323fSSean Bruno 	/* Enable OBFF */
1208e373323fSSean Bruno 	reg = E1000_READ_REG(hw, E1000_SVCR);
1209e373323fSSean Bruno 	reg |= E1000_SVCR_OFF_EN;
1210e373323fSSean Bruno 	/* Always unblock interrupts to the CPU even when the system is
1211e373323fSSean Bruno 	 * in OBFF mode. This ensures that small round-robin traffic
1212e373323fSSean Bruno 	 * (like ping) does not get dropped or experience long latency.
1213e373323fSSean Bruno 	 */
1214e373323fSSean Bruno 	reg |= E1000_SVCR_OFF_MASKINT;
1215e373323fSSean Bruno 	E1000_WRITE_REG(hw, E1000_SVCR, reg);
1216e373323fSSean Bruno 
1217e373323fSSean Bruno 	return E1000_SUCCESS;
1218e373323fSSean Bruno }
1219e373323fSSean Bruno 
1220e373323fSSean Bruno /**
1221e373323fSSean Bruno  *  e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1222e373323fSSean Bruno  *  @hw: pointer to the HW structure
1223e373323fSSean Bruno  *  @itr: interrupt throttling rate
1224e373323fSSean Bruno  *
1225e373323fSSean Bruno  *  Configure OBFF with the updated interrupt rate.
1226e373323fSSean Bruno  **/
1227e373323fSSean Bruno static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1228e373323fSSean Bruno {
1229e373323fSSean Bruno 	u32 svcr;
1230e373323fSSean Bruno 	s32 timer;
1231e373323fSSean Bruno 
1232e373323fSSean Bruno 	DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1233e373323fSSean Bruno 
1234e373323fSSean Bruno 	/* Convert ITR value into microseconds for OBFF timer */
1235e373323fSSean Bruno 	timer = itr & E1000_ITR_MASK;
1236e373323fSSean Bruno 	timer = (timer * E1000_ITR_MULT) / 1000;
1237e373323fSSean Bruno 
1238e373323fSSean Bruno 	if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1239e373323fSSean Bruno 		DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1240e373323fSSean Bruno 		return -E1000_ERR_CONFIG;
1241e373323fSSean Bruno 	}
1242e373323fSSean Bruno 
1243e373323fSSean Bruno 	svcr = E1000_READ_REG(hw, E1000_SVCR);
1244e373323fSSean Bruno 	svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1245e373323fSSean Bruno 	svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1246e373323fSSean Bruno 	E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1247e373323fSSean Bruno 
1248e373323fSSean Bruno 	return E1000_SUCCESS;
1249e373323fSSean Bruno }
1250e373323fSSean Bruno 
12517d9119bdSJack F Vogel /**
12528cc64f1eSJack F Vogel  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
12538cc64f1eSJack F Vogel  *  @hw: pointer to the HW structure
12548cc64f1eSJack F Vogel  *  @to_sx: boolean indicating a system power state transition to Sx
12558cc64f1eSJack F Vogel  *
12568cc64f1eSJack F Vogel  *  When link is down, configure ULP mode to significantly reduce the power
12578cc64f1eSJack F Vogel  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
12588cc64f1eSJack F Vogel  *  ME firmware to start the ULP configuration.  If not on an ME enabled
12598cc64f1eSJack F Vogel  *  system, configure the ULP mode by software.
12608cc64f1eSJack F Vogel  */
12618cc64f1eSJack F Vogel s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
12628cc64f1eSJack F Vogel {
12638cc64f1eSJack F Vogel 	u32 mac_reg;
12648cc64f1eSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
12658cc64f1eSJack F Vogel 	u16 phy_reg;
1266c80429ceSEric Joyner 	u16 oem_reg = 0;
12678cc64f1eSJack F Vogel 
12688cc64f1eSJack F Vogel 	if ((hw->mac.type < e1000_pch_lpt) ||
12698cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
12708cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
12718cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
12728cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
12738cc64f1eSJack F Vogel 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
12748cc64f1eSJack F Vogel 		return 0;
12758cc64f1eSJack F Vogel 
12768cc64f1eSJack F Vogel 	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
12778cc64f1eSJack F Vogel 		/* Request ME configure ULP mode in the PHY */
12788cc64f1eSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_H2ME);
12798cc64f1eSJack F Vogel 		mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
12808cc64f1eSJack F Vogel 		E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
12818cc64f1eSJack F Vogel 
12828cc64f1eSJack F Vogel 		goto out;
12838cc64f1eSJack F Vogel 	}
12848cc64f1eSJack F Vogel 
12858cc64f1eSJack F Vogel 	if (!to_sx) {
12868cc64f1eSJack F Vogel 		int i = 0;
12878cc64f1eSJack F Vogel 
12888cc64f1eSJack F Vogel 		/* Poll up to 5 seconds for Cable Disconnected indication */
12898cc64f1eSJack F Vogel 		while (!(E1000_READ_REG(hw, E1000_FEXT) &
12908cc64f1eSJack F Vogel 			 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
12918cc64f1eSJack F Vogel 			/* Bail if link is re-acquired */
12928cc64f1eSJack F Vogel 			if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
12938cc64f1eSJack F Vogel 				return -E1000_ERR_PHY;
12948cc64f1eSJack F Vogel 
12958cc64f1eSJack F Vogel 			if (i++ == 100)
12968cc64f1eSJack F Vogel 				break;
12978cc64f1eSJack F Vogel 
12988cc64f1eSJack F Vogel 			msec_delay(50);
12998cc64f1eSJack F Vogel 		}
13008cc64f1eSJack F Vogel 		DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
13018cc64f1eSJack F Vogel 			 (E1000_READ_REG(hw, E1000_FEXT) &
13028cc64f1eSJack F Vogel 			  E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
13038cc64f1eSJack F Vogel 			 i * 50);
13048cc64f1eSJack F Vogel 	}
13058cc64f1eSJack F Vogel 
13068cc64f1eSJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
13078cc64f1eSJack F Vogel 	if (ret_val)
13088cc64f1eSJack F Vogel 		goto out;
13098cc64f1eSJack F Vogel 
13108cc64f1eSJack F Vogel 	/* Force SMBus mode in PHY */
13118cc64f1eSJack F Vogel 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
13128cc64f1eSJack F Vogel 	if (ret_val)
13138cc64f1eSJack F Vogel 		goto release;
13148cc64f1eSJack F Vogel 	phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
13158cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
13168cc64f1eSJack F Vogel 
13178cc64f1eSJack F Vogel 	/* Force SMBus mode in MAC */
13188cc64f1eSJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
13198cc64f1eSJack F Vogel 	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
13208cc64f1eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
13218cc64f1eSJack F Vogel 
1322c80429ceSEric Joyner 	/* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1323c80429ceSEric Joyner 	 * LPLU and disable Gig speed when entering ULP
1324c80429ceSEric Joyner 	 */
1325c80429ceSEric Joyner 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1326c80429ceSEric Joyner 		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1327c80429ceSEric Joyner 						       &oem_reg);
1328c80429ceSEric Joyner 		if (ret_val)
1329c80429ceSEric Joyner 			goto release;
1330c80429ceSEric Joyner 
1331c80429ceSEric Joyner 		phy_reg = oem_reg;
1332c80429ceSEric Joyner 		phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1333c80429ceSEric Joyner 
1334c80429ceSEric Joyner 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1335c80429ceSEric Joyner 							phy_reg);
1336c80429ceSEric Joyner 
1337c80429ceSEric Joyner 		if (ret_val)
1338c80429ceSEric Joyner 			goto release;
1339c80429ceSEric Joyner 	}
1340c80429ceSEric Joyner 
13418cc64f1eSJack F Vogel 	/* Set Inband ULP Exit, Reset to SMBus mode and
13428cc64f1eSJack F Vogel 	 * Disable SMBus Release on PERST# in PHY
13438cc64f1eSJack F Vogel 	 */
13448cc64f1eSJack F Vogel 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
13458cc64f1eSJack F Vogel 	if (ret_val)
13468cc64f1eSJack F Vogel 		goto release;
13478cc64f1eSJack F Vogel 	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
13488cc64f1eSJack F Vogel 		    I218_ULP_CONFIG1_DISABLE_SMB_PERST);
13498cc64f1eSJack F Vogel 	if (to_sx) {
13508cc64f1eSJack F Vogel 		if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
13518cc64f1eSJack F Vogel 			phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1352c80429ceSEric Joyner 		else
1353c80429ceSEric Joyner 			phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
13548cc64f1eSJack F Vogel 
13558cc64f1eSJack F Vogel 		phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1356c80429ceSEric Joyner 		phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
13578cc64f1eSJack F Vogel 	} else {
13588cc64f1eSJack F Vogel 		phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1359c80429ceSEric Joyner 		phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1360c80429ceSEric Joyner 		phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
13618cc64f1eSJack F Vogel 	}
13628cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
13638cc64f1eSJack F Vogel 
13648cc64f1eSJack F Vogel 	/* Set Disable SMBus Release on PERST# in MAC */
13658cc64f1eSJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
13668cc64f1eSJack F Vogel 	mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
13678cc64f1eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
13688cc64f1eSJack F Vogel 
13698cc64f1eSJack F Vogel 	/* Commit ULP changes in PHY by starting auto ULP configuration */
13708cc64f1eSJack F Vogel 	phy_reg |= I218_ULP_CONFIG1_START;
13718cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1372c80429ceSEric Joyner 
1373c80429ceSEric Joyner 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1374c80429ceSEric Joyner 	    to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1375c80429ceSEric Joyner 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1376c80429ceSEric Joyner 							oem_reg);
1377c80429ceSEric Joyner 		if (ret_val)
1378c80429ceSEric Joyner 			goto release;
1379c80429ceSEric Joyner 	}
1380c80429ceSEric Joyner 
13818cc64f1eSJack F Vogel release:
13828cc64f1eSJack F Vogel 	hw->phy.ops.release(hw);
13838cc64f1eSJack F Vogel out:
13848cc64f1eSJack F Vogel 	if (ret_val)
13858cc64f1eSJack F Vogel 		DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
13868cc64f1eSJack F Vogel 	else
13878cc64f1eSJack F Vogel 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
13888cc64f1eSJack F Vogel 
13898cc64f1eSJack F Vogel 	return ret_val;
13908cc64f1eSJack F Vogel }
13918cc64f1eSJack F Vogel 
13928cc64f1eSJack F Vogel /**
13938cc64f1eSJack F Vogel  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
13948cc64f1eSJack F Vogel  *  @hw: pointer to the HW structure
13958cc64f1eSJack F Vogel  *  @force: boolean indicating whether or not to force disabling ULP
13968cc64f1eSJack F Vogel  *
13978cc64f1eSJack F Vogel  *  Un-configure ULP mode when link is up, the system is transitioned from
13988cc64f1eSJack F Vogel  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
13998cc64f1eSJack F Vogel  *  system, poll for an indication from ME that ULP has been un-configured.
14008cc64f1eSJack F Vogel  *  If not on an ME enabled system, un-configure the ULP mode by software.
14018cc64f1eSJack F Vogel  *
14028cc64f1eSJack F Vogel  *  During nominal operation, this function is called when link is acquired
14038cc64f1eSJack F Vogel  *  to disable ULP mode (force=FALSE); otherwise, for example when unloading
14048cc64f1eSJack F Vogel  *  the driver or during Sx->S0 transitions, this is called with force=TRUE
14058cc64f1eSJack F Vogel  *  to forcibly disable ULP.
14068cc64f1eSJack F Vogel  */
14078cc64f1eSJack F Vogel s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
14088cc64f1eSJack F Vogel {
14098cc64f1eSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
14108cc64f1eSJack F Vogel 	u32 mac_reg;
14118cc64f1eSJack F Vogel 	u16 phy_reg;
14128cc64f1eSJack F Vogel 	int i = 0;
14138cc64f1eSJack F Vogel 
14148cc64f1eSJack F Vogel 	if ((hw->mac.type < e1000_pch_lpt) ||
14158cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
14168cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
14178cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
14188cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
14198cc64f1eSJack F Vogel 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
14208cc64f1eSJack F Vogel 		return 0;
14218cc64f1eSJack F Vogel 
14228cc64f1eSJack F Vogel 	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
14238cc64f1eSJack F Vogel 		if (force) {
14248cc64f1eSJack F Vogel 			/* Request ME un-configure ULP mode in the PHY */
14258cc64f1eSJack F Vogel 			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
14268cc64f1eSJack F Vogel 			mac_reg &= ~E1000_H2ME_ULP;
14278cc64f1eSJack F Vogel 			mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
14288cc64f1eSJack F Vogel 			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
14298cc64f1eSJack F Vogel 		}
14308cc64f1eSJack F Vogel 
1431c80429ceSEric Joyner 		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
14328cc64f1eSJack F Vogel 		while (E1000_READ_REG(hw, E1000_FWSM) &
14338cc64f1eSJack F Vogel 		       E1000_FWSM_ULP_CFG_DONE) {
1434c80429ceSEric Joyner 			if (i++ == 30) {
14358cc64f1eSJack F Vogel 				ret_val = -E1000_ERR_PHY;
14368cc64f1eSJack F Vogel 				goto out;
14378cc64f1eSJack F Vogel 			}
14388cc64f1eSJack F Vogel 
14398cc64f1eSJack F Vogel 			msec_delay(10);
14408cc64f1eSJack F Vogel 		}
14418cc64f1eSJack F Vogel 		DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
14428cc64f1eSJack F Vogel 
14438cc64f1eSJack F Vogel 		if (force) {
14448cc64f1eSJack F Vogel 			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
14458cc64f1eSJack F Vogel 			mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
14468cc64f1eSJack F Vogel 			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
14478cc64f1eSJack F Vogel 		} else {
14488cc64f1eSJack F Vogel 			/* Clear H2ME.ULP after ME ULP configuration */
14498cc64f1eSJack F Vogel 			mac_reg = E1000_READ_REG(hw, E1000_H2ME);
14508cc64f1eSJack F Vogel 			mac_reg &= ~E1000_H2ME_ULP;
14518cc64f1eSJack F Vogel 			E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
14528cc64f1eSJack F Vogel 		}
14538cc64f1eSJack F Vogel 
14548cc64f1eSJack F Vogel 		goto out;
14558cc64f1eSJack F Vogel 	}
14568cc64f1eSJack F Vogel 
14578cc64f1eSJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
14588cc64f1eSJack F Vogel 	if (ret_val)
14598cc64f1eSJack F Vogel 		goto out;
14608cc64f1eSJack F Vogel 
14618cc64f1eSJack F Vogel 	if (force)
14628cc64f1eSJack F Vogel 		/* Toggle LANPHYPC Value bit */
14638cc64f1eSJack F Vogel 		e1000_toggle_lanphypc_pch_lpt(hw);
14648cc64f1eSJack F Vogel 
14658cc64f1eSJack F Vogel 	/* Unforce SMBus mode in PHY */
14668cc64f1eSJack F Vogel 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
14678cc64f1eSJack F Vogel 	if (ret_val) {
14688cc64f1eSJack F Vogel 		/* The MAC might be in PCIe mode, so temporarily force to
14698cc64f1eSJack F Vogel 		 * SMBus mode in order to access the PHY.
14708cc64f1eSJack F Vogel 		 */
14718cc64f1eSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
14728cc64f1eSJack F Vogel 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
14738cc64f1eSJack F Vogel 		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
14748cc64f1eSJack F Vogel 
14758cc64f1eSJack F Vogel 		msec_delay(50);
14768cc64f1eSJack F Vogel 
14778cc64f1eSJack F Vogel 		ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
14788cc64f1eSJack F Vogel 						       &phy_reg);
14798cc64f1eSJack F Vogel 		if (ret_val)
14808cc64f1eSJack F Vogel 			goto release;
14818cc64f1eSJack F Vogel 	}
14828cc64f1eSJack F Vogel 	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
14838cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
14848cc64f1eSJack F Vogel 
14858cc64f1eSJack F Vogel 	/* Unforce SMBus mode in MAC */
14868cc64f1eSJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
14878cc64f1eSJack F Vogel 	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
14888cc64f1eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
14898cc64f1eSJack F Vogel 
14908cc64f1eSJack F Vogel 	/* When ULP mode was previously entered, K1 was disabled by the
14918cc64f1eSJack F Vogel 	 * hardware.  Re-Enable K1 in the PHY when exiting ULP.
14928cc64f1eSJack F Vogel 	 */
14938cc64f1eSJack F Vogel 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
14948cc64f1eSJack F Vogel 	if (ret_val)
14958cc64f1eSJack F Vogel 		goto release;
14968cc64f1eSJack F Vogel 	phy_reg |= HV_PM_CTRL_K1_ENABLE;
14978cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
14988cc64f1eSJack F Vogel 
14998cc64f1eSJack F Vogel 	/* Clear ULP enabled configuration */
15008cc64f1eSJack F Vogel 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
15018cc64f1eSJack F Vogel 	if (ret_val)
15028cc64f1eSJack F Vogel 		goto release;
15038cc64f1eSJack F Vogel 	phy_reg &= ~(I218_ULP_CONFIG1_IND |
15048cc64f1eSJack F Vogel 		     I218_ULP_CONFIG1_STICKY_ULP |
15058cc64f1eSJack F Vogel 		     I218_ULP_CONFIG1_RESET_TO_SMBUS |
15068cc64f1eSJack F Vogel 		     I218_ULP_CONFIG1_WOL_HOST |
15078cc64f1eSJack F Vogel 		     I218_ULP_CONFIG1_INBAND_EXIT |
1508c80429ceSEric Joyner 		     I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1509c80429ceSEric Joyner 		     I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
15108cc64f1eSJack F Vogel 		     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
15118cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
15128cc64f1eSJack F Vogel 
15138cc64f1eSJack F Vogel 	/* Commit ULP changes by starting auto ULP configuration */
15148cc64f1eSJack F Vogel 	phy_reg |= I218_ULP_CONFIG1_START;
15158cc64f1eSJack F Vogel 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
15168cc64f1eSJack F Vogel 
15178cc64f1eSJack F Vogel 	/* Clear Disable SMBus Release on PERST# in MAC */
15188cc64f1eSJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
15198cc64f1eSJack F Vogel 	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
15208cc64f1eSJack F Vogel 	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
15218cc64f1eSJack F Vogel 
15228cc64f1eSJack F Vogel release:
15238cc64f1eSJack F Vogel 	hw->phy.ops.release(hw);
15248cc64f1eSJack F Vogel 	if (force) {
15258cc64f1eSJack F Vogel 		hw->phy.ops.reset(hw);
15268cc64f1eSJack F Vogel 		msec_delay(50);
15278cc64f1eSJack F Vogel 	}
15288cc64f1eSJack F Vogel out:
15298cc64f1eSJack F Vogel 	if (ret_val)
15308cc64f1eSJack F Vogel 		DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
15318cc64f1eSJack F Vogel 	else
15328cc64f1eSJack F Vogel 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
15338cc64f1eSJack F Vogel 
15348cc64f1eSJack F Vogel 	return ret_val;
15358cc64f1eSJack F Vogel }
15368cc64f1eSJack F Vogel 
15378cc64f1eSJack F Vogel /**
15384edd8523SJack F Vogel  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
15394edd8523SJack F Vogel  *  @hw: pointer to the HW structure
15404edd8523SJack F Vogel  *
15414edd8523SJack F Vogel  *  Checks to see of the link status of the hardware has changed.  If a
15424edd8523SJack F Vogel  *  change in link status has been detected, then we read the PHY registers
15434edd8523SJack F Vogel  *  to get the current speed/duplex if link exists.
15444edd8523SJack F Vogel  **/
15454edd8523SJack F Vogel static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
15464edd8523SJack F Vogel {
15474edd8523SJack F Vogel 	struct e1000_mac_info *mac = &hw->mac;
1548c80429ceSEric Joyner 	s32 ret_val, tipg_reg = 0;
1549c80429ceSEric Joyner 	u16 emi_addr, emi_val = 0;
15504edd8523SJack F Vogel 	bool link;
15514dab5c37SJack F Vogel 	u16 phy_reg;
15524edd8523SJack F Vogel 
15534edd8523SJack F Vogel 	DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
15544edd8523SJack F Vogel 
15556ab6bfe3SJack F Vogel 	/* We only want to go out to the PHY registers to see if Auto-Neg
15564edd8523SJack F Vogel 	 * has completed and/or if our link status has changed.  The
15574edd8523SJack F Vogel 	 * get_link_status flag is set upon receiving a Link Status
15584edd8523SJack F Vogel 	 * Change or Rx Sequence Error interrupt.
15594edd8523SJack F Vogel 	 */
15606ab6bfe3SJack F Vogel 	if (!mac->get_link_status)
15616ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
15624edd8523SJack F Vogel 
15636ab6bfe3SJack F Vogel 	/* First we want to see if the MII Status Register reports
15644edd8523SJack F Vogel 	 * link.  If so, then we want to get the current speed/duplex
15654edd8523SJack F Vogel 	 * of the PHY.
15664edd8523SJack F Vogel 	 */
15674edd8523SJack F Vogel 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
15684edd8523SJack F Vogel 	if (ret_val)
15696ab6bfe3SJack F Vogel 		return ret_val;
15704edd8523SJack F Vogel 
15714edd8523SJack F Vogel 	if (hw->mac.type == e1000_pchlan) {
15724edd8523SJack F Vogel 		ret_val = e1000_k1_gig_workaround_hv(hw, link);
15734edd8523SJack F Vogel 		if (ret_val)
15746ab6bfe3SJack F Vogel 			return ret_val;
15754edd8523SJack F Vogel 	}
15764edd8523SJack F Vogel 
15778cc64f1eSJack F Vogel 	/* When connected at 10Mbps half-duplex, some parts are excessively
15786ab6bfe3SJack F Vogel 	 * aggressive resulting in many collisions. To avoid this, increase
15796ab6bfe3SJack F Vogel 	 * the IPG and reduce Rx latency in the PHY.
15806ab6bfe3SJack F Vogel 	 */
1581295df609SEric Joyner 	if ((hw->mac.type >= e1000_pch2lan) && link) {
1582c80429ceSEric Joyner 		u16 speed, duplex;
15838cc64f1eSJack F Vogel 
1584c80429ceSEric Joyner 		e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1585c80429ceSEric Joyner 		tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1586c80429ceSEric Joyner 		tipg_reg &= ~E1000_TIPG_IPGT_MASK;
15876ab6bfe3SJack F Vogel 
1588c80429ceSEric Joyner 		if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1589c80429ceSEric Joyner 			tipg_reg |= 0xFF;
15906ab6bfe3SJack F Vogel 			/* Reduce Rx latency in analog PHY */
1591c80429ceSEric Joyner 			emi_val = 0;
1592295df609SEric Joyner 		} else if (hw->mac.type >= e1000_pch_spt &&
1593c80429ceSEric Joyner 			   duplex == FULL_DUPLEX && speed != SPEED_1000) {
1594c80429ceSEric Joyner 			tipg_reg |= 0xC;
1595c80429ceSEric Joyner 			emi_val = 1;
1596c80429ceSEric Joyner 		} else {
1597c80429ceSEric Joyner 			/* Roll back the default values */
1598c80429ceSEric Joyner 			tipg_reg |= 0x08;
1599c80429ceSEric Joyner 			emi_val = 1;
1600c80429ceSEric Joyner 		}
1601c80429ceSEric Joyner 
1602c80429ceSEric Joyner 		E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1603c80429ceSEric Joyner 
16046ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
16056ab6bfe3SJack F Vogel 		if (ret_val)
16066ab6bfe3SJack F Vogel 			return ret_val;
16076ab6bfe3SJack F Vogel 
16088cc64f1eSJack F Vogel 		if (hw->mac.type == e1000_pch2lan)
16098cc64f1eSJack F Vogel 			emi_addr = I82579_RX_CONFIG;
16108cc64f1eSJack F Vogel 		else
16118cc64f1eSJack F Vogel 			emi_addr = I217_RX_CONFIG;
1612c80429ceSEric Joyner 		ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
16136ab6bfe3SJack F Vogel 
1614295df609SEric Joyner 
1615295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_lpt) {
1616c80429ceSEric Joyner 			u16 phy_reg;
1617c80429ceSEric Joyner 
1618c80429ceSEric Joyner 			hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1619c80429ceSEric Joyner 						    &phy_reg);
1620c80429ceSEric Joyner 			phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1621c80429ceSEric Joyner 			if (speed == SPEED_100 || speed == SPEED_10)
1622c80429ceSEric Joyner 				phy_reg |= 0x3E8;
1623c80429ceSEric Joyner 			else
1624c80429ceSEric Joyner 				phy_reg |= 0xFA;
1625c80429ceSEric Joyner 			hw->phy.ops.write_reg_locked(hw,
1626c80429ceSEric Joyner 						     I217_PLL_CLOCK_GATE_REG,
1627c80429ceSEric Joyner 						     phy_reg);
1628e760e292SSean Bruno 
1629e760e292SSean Bruno 			if (speed == SPEED_1000) {
1630e760e292SSean Bruno 				hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1631e760e292SSean Bruno 							    &phy_reg);
1632e760e292SSean Bruno 
1633e760e292SSean Bruno 				phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1634e760e292SSean Bruno 
1635e760e292SSean Bruno 				hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1636e760e292SSean Bruno 							     phy_reg);
1637e760e292SSean Bruno 				}
1638c80429ceSEric Joyner 		 }
16396ab6bfe3SJack F Vogel 		hw->phy.ops.release(hw);
16406ab6bfe3SJack F Vogel 
16416ab6bfe3SJack F Vogel 		if (ret_val)
16426ab6bfe3SJack F Vogel 			return ret_val;
1643c80429ceSEric Joyner 
1644295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_spt) {
1645c80429ceSEric Joyner 			u16 data;
1646c80429ceSEric Joyner 			u16 ptr_gap;
1647c80429ceSEric Joyner 
1648c80429ceSEric Joyner 			if (speed == SPEED_1000) {
1649c80429ceSEric Joyner 				ret_val = hw->phy.ops.acquire(hw);
1650c80429ceSEric Joyner 				if (ret_val)
1651c80429ceSEric Joyner 					return ret_val;
1652c80429ceSEric Joyner 
1653c80429ceSEric Joyner 				ret_val = hw->phy.ops.read_reg_locked(hw,
1654c80429ceSEric Joyner 							      PHY_REG(776, 20),
1655c80429ceSEric Joyner 							      &data);
1656c80429ceSEric Joyner 				if (ret_val) {
1657c80429ceSEric Joyner 					hw->phy.ops.release(hw);
1658c80429ceSEric Joyner 					return ret_val;
16596ab6bfe3SJack F Vogel 				}
1660c80429ceSEric Joyner 
1661c80429ceSEric Joyner 				ptr_gap = (data & (0x3FF << 2)) >> 2;
1662c80429ceSEric Joyner 				if (ptr_gap < 0x18) {
1663c80429ceSEric Joyner 					data &= ~(0x3FF << 2);
1664c80429ceSEric Joyner 					data |= (0x18 << 2);
1665c80429ceSEric Joyner 					ret_val =
1666c80429ceSEric Joyner 						hw->phy.ops.write_reg_locked(hw,
1667c80429ceSEric Joyner 							PHY_REG(776, 20), data);
1668c80429ceSEric Joyner 				}
1669c80429ceSEric Joyner 				hw->phy.ops.release(hw);
1670c80429ceSEric Joyner 				if (ret_val)
1671c80429ceSEric Joyner 					return ret_val;
1672c80429ceSEric Joyner 			} else {
1673c80429ceSEric Joyner 				ret_val = hw->phy.ops.acquire(hw);
1674c80429ceSEric Joyner 				if (ret_val)
1675c80429ceSEric Joyner 					return ret_val;
1676c80429ceSEric Joyner 
1677c80429ceSEric Joyner 				ret_val = hw->phy.ops.write_reg_locked(hw,
1678c80429ceSEric Joyner 							     PHY_REG(776, 20),
1679c80429ceSEric Joyner 							     0xC023);
1680c80429ceSEric Joyner 				hw->phy.ops.release(hw);
1681c80429ceSEric Joyner 				if (ret_val)
1682c80429ceSEric Joyner 					return ret_val;
1683c80429ceSEric Joyner 
1684c80429ceSEric Joyner 			}
1685c80429ceSEric Joyner 		}
1686c80429ceSEric Joyner 	}
1687c80429ceSEric Joyner 
1688c80429ceSEric Joyner 	/* I217 Packet Loss issue:
1689c80429ceSEric Joyner 	 * ensure that FEXTNVM4 Beacon Duration is set correctly
1690c80429ceSEric Joyner 	 * on power up.
1691c80429ceSEric Joyner 	 * Set the Beacon Duration for I217 to 8 usec
1692c80429ceSEric Joyner 	 */
1693295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_lpt) {
1694c80429ceSEric Joyner 		u32 mac_reg;
1695c80429ceSEric Joyner 
1696c80429ceSEric Joyner 		mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1697c80429ceSEric Joyner 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1698c80429ceSEric Joyner 		mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1699c80429ceSEric Joyner 		E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
17006ab6bfe3SJack F Vogel 	}
17016ab6bfe3SJack F Vogel 
17026ab6bfe3SJack F Vogel 	/* Work-around I218 hang issue */
17036ab6bfe3SJack F Vogel 	if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
17048cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
17058cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
17068cc64f1eSJack F Vogel 	    (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
17076ab6bfe3SJack F Vogel 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);
17086ab6bfe3SJack F Vogel 		if (ret_val)
17096ab6bfe3SJack F Vogel 			return ret_val;
17106ab6bfe3SJack F Vogel 	}
1711295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_lpt) {
1712e373323fSSean Bruno 		/* Set platform power management values for
1713e373323fSSean Bruno 		 * Latency Tolerance Reporting (LTR)
1714e373323fSSean Bruno 		 * Optimized Buffer Flush/Fill (OBFF)
1715e373323fSSean Bruno 		 */
1716e373323fSSean Bruno 		ret_val = e1000_platform_pm_pch_lpt(hw, link);
1717e373323fSSean Bruno 		if (ret_val)
1718e373323fSSean Bruno 			return ret_val;
1719e373323fSSean Bruno 	}
1720e373323fSSean Bruno 
17216ab6bfe3SJack F Vogel 	/* Clear link partner's EEE ability */
17226ab6bfe3SJack F Vogel 	hw->dev_spec.ich8lan.eee_lp_ability = 0;
17236ab6bfe3SJack F Vogel 
1724295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_lpt) {
1725c80429ceSEric Joyner 		u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1726c80429ceSEric Joyner 
1727295df609SEric Joyner 		if (hw->mac.type == e1000_pch_spt) {
1728295df609SEric Joyner 			/* FEXTNVM6 K1-off workaround - for SPT only */
1729295df609SEric Joyner 			u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1730295df609SEric Joyner 
1731295df609SEric Joyner 			if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1732c80429ceSEric Joyner 				fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1733c80429ceSEric Joyner 			else
1734c80429ceSEric Joyner 				fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1735295df609SEric Joyner 		}
1736295df609SEric Joyner 
1737295df609SEric Joyner 		if (hw->dev_spec.ich8lan.disable_k1_off == TRUE)
1738295df609SEric Joyner 			fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1739c80429ceSEric Joyner 
1740c80429ceSEric Joyner 		E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1741c80429ceSEric Joyner 	}
1742c80429ceSEric Joyner 
17434edd8523SJack F Vogel 	if (!link)
17446ab6bfe3SJack F Vogel 		return E1000_SUCCESS; /* No link detected */
17454edd8523SJack F Vogel 
17464edd8523SJack F Vogel 	mac->get_link_status = FALSE;
17474edd8523SJack F Vogel 
17484dab5c37SJack F Vogel 	switch (hw->mac.type) {
17494dab5c37SJack F Vogel 	case e1000_pch2lan:
17504dab5c37SJack F Vogel 		ret_val = e1000_k1_workaround_lv(hw);
17514dab5c37SJack F Vogel 		if (ret_val)
17526ab6bfe3SJack F Vogel 			return ret_val;
17534dab5c37SJack F Vogel 		/* fall-thru */
17544dab5c37SJack F Vogel 	case e1000_pchlan:
17554edd8523SJack F Vogel 		if (hw->phy.type == e1000_phy_82578) {
17564edd8523SJack F Vogel 			ret_val = e1000_link_stall_workaround_hv(hw);
17574edd8523SJack F Vogel 			if (ret_val)
17586ab6bfe3SJack F Vogel 				return ret_val;
17594edd8523SJack F Vogel 		}
17604edd8523SJack F Vogel 
17616ab6bfe3SJack F Vogel 		/* Workaround for PCHx parts in half-duplex:
17624dab5c37SJack F Vogel 		 * Set the number of preambles removed from the packet
17634dab5c37SJack F Vogel 		 * when it is passed from the PHY to the MAC to prevent
17644dab5c37SJack F Vogel 		 * the MAC from misinterpreting the packet type.
17654dab5c37SJack F Vogel 		 */
17664dab5c37SJack F Vogel 		hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
17674dab5c37SJack F Vogel 		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
17684dab5c37SJack F Vogel 
17694dab5c37SJack F Vogel 		if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
17704dab5c37SJack F Vogel 		    E1000_STATUS_FD)
17714dab5c37SJack F Vogel 			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
17724dab5c37SJack F Vogel 
17734dab5c37SJack F Vogel 		hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
17744dab5c37SJack F Vogel 		break;
17754dab5c37SJack F Vogel 	default:
17764dab5c37SJack F Vogel 		break;
17777d9119bdSJack F Vogel 	}
17787d9119bdSJack F Vogel 
17796ab6bfe3SJack F Vogel 	/* Check if there was DownShift, must be checked
17804edd8523SJack F Vogel 	 * immediately after link-up
17814edd8523SJack F Vogel 	 */
17824edd8523SJack F Vogel 	e1000_check_downshift_generic(hw);
17834edd8523SJack F Vogel 
17847d9119bdSJack F Vogel 	/* Enable/Disable EEE after link up */
17857609433eSJack F Vogel 	if (hw->phy.type > e1000_phy_82579) {
17867d9119bdSJack F Vogel 		ret_val = e1000_set_eee_pchlan(hw);
17877d9119bdSJack F Vogel 		if (ret_val)
17886ab6bfe3SJack F Vogel 			return ret_val;
17897609433eSJack F Vogel 	}
17907d9119bdSJack F Vogel 
17916ab6bfe3SJack F Vogel 	/* If we are forcing speed/duplex, then we simply return since
17924edd8523SJack F Vogel 	 * we have already determined whether we have link or not.
17934edd8523SJack F Vogel 	 */
17946ab6bfe3SJack F Vogel 	if (!mac->autoneg)
17956ab6bfe3SJack F Vogel 		return -E1000_ERR_CONFIG;
17964edd8523SJack F Vogel 
17976ab6bfe3SJack F Vogel 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
17984edd8523SJack F Vogel 	 * of MAC speed/duplex configuration.  So we only need to
17994edd8523SJack F Vogel 	 * configure Collision Distance in the MAC.
18004edd8523SJack F Vogel 	 */
18016ab6bfe3SJack F Vogel 	mac->ops.config_collision_dist(hw);
18024edd8523SJack F Vogel 
18036ab6bfe3SJack F Vogel 	/* Configure Flow Control now that Auto-Neg has completed.
18044edd8523SJack F Vogel 	 * First, we need to restore the desired flow control
18054edd8523SJack F Vogel 	 * settings because we may have had to re-autoneg with a
18064edd8523SJack F Vogel 	 * different link partner.
18074edd8523SJack F Vogel 	 */
18084edd8523SJack F Vogel 	ret_val = e1000_config_fc_after_link_up_generic(hw);
18094edd8523SJack F Vogel 	if (ret_val)
18104edd8523SJack F Vogel 		DEBUGOUT("Error configuring flow control\n");
18114edd8523SJack F Vogel 
18124edd8523SJack F Vogel 	return ret_val;
18134edd8523SJack F Vogel }
18144edd8523SJack F Vogel 
18154edd8523SJack F Vogel /**
18168cfa0ad2SJack F Vogel  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
18178cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
18188cfa0ad2SJack F Vogel  *
18198cfa0ad2SJack F Vogel  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
18208cfa0ad2SJack F Vogel  **/
18218cfa0ad2SJack F Vogel void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
18228cfa0ad2SJack F Vogel {
18238cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_init_function_pointers_ich8lan");
18248cfa0ad2SJack F Vogel 
18258cfa0ad2SJack F Vogel 	hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
18268cfa0ad2SJack F Vogel 	hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
18279d81738fSJack F Vogel 	switch (hw->mac.type) {
18289d81738fSJack F Vogel 	case e1000_ich8lan:
18299d81738fSJack F Vogel 	case e1000_ich9lan:
18309d81738fSJack F Vogel 	case e1000_ich10lan:
18318cfa0ad2SJack F Vogel 		hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
18329d81738fSJack F Vogel 		break;
18339d81738fSJack F Vogel 	case e1000_pchlan:
18347d9119bdSJack F Vogel 	case e1000_pch2lan:
18356ab6bfe3SJack F Vogel 	case e1000_pch_lpt:
1836c80429ceSEric Joyner 	case e1000_pch_spt:
1837*6fe4c0a0SSean Bruno 	case e1000_pch_cnp:
18389d81738fSJack F Vogel 		hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
18399d81738fSJack F Vogel 		break;
18409d81738fSJack F Vogel 	default:
18419d81738fSJack F Vogel 		break;
18429d81738fSJack F Vogel 	}
18438cfa0ad2SJack F Vogel }
18448cfa0ad2SJack F Vogel 
18458cfa0ad2SJack F Vogel /**
18464edd8523SJack F Vogel  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
18474edd8523SJack F Vogel  *  @hw: pointer to the HW structure
18484edd8523SJack F Vogel  *
18494edd8523SJack F Vogel  *  Acquires the mutex for performing NVM operations.
18504edd8523SJack F Vogel  **/
18514edd8523SJack F Vogel static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
18524edd8523SJack F Vogel {
18534edd8523SJack F Vogel 	DEBUGFUNC("e1000_acquire_nvm_ich8lan");
18544edd8523SJack F Vogel 
1855ab2e3f79SStephen Hurd 	E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
18564edd8523SJack F Vogel 
18574edd8523SJack F Vogel 	return E1000_SUCCESS;
18584edd8523SJack F Vogel }
18594edd8523SJack F Vogel 
18604edd8523SJack F Vogel /**
18614edd8523SJack F Vogel  *  e1000_release_nvm_ich8lan - Release NVM mutex
18624edd8523SJack F Vogel  *  @hw: pointer to the HW structure
18634edd8523SJack F Vogel  *
18644edd8523SJack F Vogel  *  Releases the mutex used while performing NVM operations.
18654edd8523SJack F Vogel  **/
18664edd8523SJack F Vogel static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
18674edd8523SJack F Vogel {
18684edd8523SJack F Vogel 	DEBUGFUNC("e1000_release_nvm_ich8lan");
18694edd8523SJack F Vogel 
1870ab2e3f79SStephen Hurd 	E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1871ab2e3f79SStephen Hurd 
1872ab2e3f79SStephen Hurd 	return;
18734edd8523SJack F Vogel }
18744edd8523SJack F Vogel 
18754edd8523SJack F Vogel /**
18768cfa0ad2SJack F Vogel  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
18778cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
18788cfa0ad2SJack F Vogel  *
18794edd8523SJack F Vogel  *  Acquires the software control flag for performing PHY and select
18804edd8523SJack F Vogel  *  MAC CSR accesses.
18818cfa0ad2SJack F Vogel  **/
18828cfa0ad2SJack F Vogel static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
18838cfa0ad2SJack F Vogel {
18848cfa0ad2SJack F Vogel 	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
18858cfa0ad2SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
18868cfa0ad2SJack F Vogel 
18878cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_acquire_swflag_ich8lan");
18888cfa0ad2SJack F Vogel 
1889ab2e3f79SStephen Hurd 	E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
18904edd8523SJack F Vogel 
18918cfa0ad2SJack F Vogel 	while (timeout) {
18928cfa0ad2SJack F Vogel 		extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
18934edd8523SJack F Vogel 		if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
18948cfa0ad2SJack F Vogel 			break;
18954edd8523SJack F Vogel 
18968cfa0ad2SJack F Vogel 		msec_delay_irq(1);
18978cfa0ad2SJack F Vogel 		timeout--;
18988cfa0ad2SJack F Vogel 	}
18998cfa0ad2SJack F Vogel 
19008cfa0ad2SJack F Vogel 	if (!timeout) {
19014dab5c37SJack F Vogel 		DEBUGOUT("SW has already locked the resource.\n");
19024edd8523SJack F Vogel 		ret_val = -E1000_ERR_CONFIG;
19034edd8523SJack F Vogel 		goto out;
19044edd8523SJack F Vogel 	}
19054edd8523SJack F Vogel 
19064edd8523SJack F Vogel 	timeout = SW_FLAG_TIMEOUT;
19074edd8523SJack F Vogel 
19084edd8523SJack F Vogel 	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
19094edd8523SJack F Vogel 	E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
19104edd8523SJack F Vogel 
19114edd8523SJack F Vogel 	while (timeout) {
19124edd8523SJack F Vogel 		extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
19134edd8523SJack F Vogel 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
19144edd8523SJack F Vogel 			break;
19154edd8523SJack F Vogel 
19164edd8523SJack F Vogel 		msec_delay_irq(1);
19174edd8523SJack F Vogel 		timeout--;
19184edd8523SJack F Vogel 	}
19194edd8523SJack F Vogel 
19204edd8523SJack F Vogel 	if (!timeout) {
19214dab5c37SJack F Vogel 		DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
19224dab5c37SJack F Vogel 			  E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
19238cfa0ad2SJack F Vogel 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
19248cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
19258cfa0ad2SJack F Vogel 		ret_val = -E1000_ERR_CONFIG;
19268cfa0ad2SJack F Vogel 		goto out;
19278cfa0ad2SJack F Vogel 	}
19288cfa0ad2SJack F Vogel 
19298cfa0ad2SJack F Vogel out:
1930ab2e3f79SStephen Hurd 	if (ret_val)
1931ab2e3f79SStephen Hurd 		E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1932ab2e3f79SStephen Hurd 
19338cfa0ad2SJack F Vogel 	return ret_val;
19348cfa0ad2SJack F Vogel }
19358cfa0ad2SJack F Vogel 
19368cfa0ad2SJack F Vogel /**
19378cfa0ad2SJack F Vogel  *  e1000_release_swflag_ich8lan - Release software control flag
19388cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
19398cfa0ad2SJack F Vogel  *
19404edd8523SJack F Vogel  *  Releases the software control flag for performing PHY and select
19414edd8523SJack F Vogel  *  MAC CSR accesses.
19428cfa0ad2SJack F Vogel  **/
19438cfa0ad2SJack F Vogel static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
19448cfa0ad2SJack F Vogel {
19458cfa0ad2SJack F Vogel 	u32 extcnf_ctrl;
19468cfa0ad2SJack F Vogel 
19478cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_release_swflag_ich8lan");
19488cfa0ad2SJack F Vogel 
19498cfa0ad2SJack F Vogel 	extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1950730d3130SJack F Vogel 
1951730d3130SJack F Vogel 	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
19528cfa0ad2SJack F Vogel 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
19538cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1954730d3130SJack F Vogel 	} else {
1955730d3130SJack F Vogel 		DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1956730d3130SJack F Vogel 	}
1957ab2e3f79SStephen Hurd 
1958ab2e3f79SStephen Hurd 	E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1959ab2e3f79SStephen Hurd 
1960ab2e3f79SStephen Hurd 	return;
19618cfa0ad2SJack F Vogel }
19628cfa0ad2SJack F Vogel 
19638cfa0ad2SJack F Vogel /**
19648cfa0ad2SJack F Vogel  *  e1000_check_mng_mode_ich8lan - Checks management mode
19658cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
19668cfa0ad2SJack F Vogel  *
19677d9119bdSJack F Vogel  *  This checks if the adapter has any manageability enabled.
19688cfa0ad2SJack F Vogel  *  This is a function pointer entry point only called by read/write
19698cfa0ad2SJack F Vogel  *  routines for the PHY and NVM parts.
19708cfa0ad2SJack F Vogel  **/
19718cfa0ad2SJack F Vogel static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
19728cfa0ad2SJack F Vogel {
19738cfa0ad2SJack F Vogel 	u32 fwsm;
19748cfa0ad2SJack F Vogel 
19758cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_check_mng_mode_ich8lan");
19768cfa0ad2SJack F Vogel 
19778cfa0ad2SJack F Vogel 	fwsm = E1000_READ_REG(hw, E1000_FWSM);
19788cfa0ad2SJack F Vogel 
19798cc64f1eSJack F Vogel 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
19807d9119bdSJack F Vogel 	       ((fwsm & E1000_FWSM_MODE_MASK) ==
19818cc64f1eSJack F Vogel 		(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
19827d9119bdSJack F Vogel }
19837d9119bdSJack F Vogel 
19847d9119bdSJack F Vogel /**
19857d9119bdSJack F Vogel  *  e1000_check_mng_mode_pchlan - Checks management mode
19867d9119bdSJack F Vogel  *  @hw: pointer to the HW structure
19877d9119bdSJack F Vogel  *
19887d9119bdSJack F Vogel  *  This checks if the adapter has iAMT enabled.
19897d9119bdSJack F Vogel  *  This is a function pointer entry point only called by read/write
19907d9119bdSJack F Vogel  *  routines for the PHY and NVM parts.
19917d9119bdSJack F Vogel  **/
19927d9119bdSJack F Vogel static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
19937d9119bdSJack F Vogel {
19947d9119bdSJack F Vogel 	u32 fwsm;
19957d9119bdSJack F Vogel 
19967d9119bdSJack F Vogel 	DEBUGFUNC("e1000_check_mng_mode_pchlan");
19977d9119bdSJack F Vogel 
19987d9119bdSJack F Vogel 	fwsm = E1000_READ_REG(hw, E1000_FWSM);
19997d9119bdSJack F Vogel 
20007d9119bdSJack F Vogel 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
20017d9119bdSJack F Vogel 	       (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
20027d9119bdSJack F Vogel }
20037d9119bdSJack F Vogel 
20047d9119bdSJack F Vogel /**
20057d9119bdSJack F Vogel  *  e1000_rar_set_pch2lan - Set receive address register
20067d9119bdSJack F Vogel  *  @hw: pointer to the HW structure
20077d9119bdSJack F Vogel  *  @addr: pointer to the receive address
20087d9119bdSJack F Vogel  *  @index: receive address array register
20097d9119bdSJack F Vogel  *
20107d9119bdSJack F Vogel  *  Sets the receive address array register at index to the address passed
20117d9119bdSJack F Vogel  *  in by addr.  For 82579, RAR[0] is the base address register that is to
20127d9119bdSJack F Vogel  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
20137d9119bdSJack F Vogel  *  Use SHRA[0-3] in place of those reserved for ME.
20147d9119bdSJack F Vogel  **/
20158cc64f1eSJack F Vogel static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
20167d9119bdSJack F Vogel {
20177d9119bdSJack F Vogel 	u32 rar_low, rar_high;
20187d9119bdSJack F Vogel 
20197d9119bdSJack F Vogel 	DEBUGFUNC("e1000_rar_set_pch2lan");
20207d9119bdSJack F Vogel 
20216ab6bfe3SJack F Vogel 	/* HW expects these in little endian so we reverse the byte order
20227d9119bdSJack F Vogel 	 * from network order (big endian) to little endian
20237d9119bdSJack F Vogel 	 */
20247d9119bdSJack F Vogel 	rar_low = ((u32) addr[0] |
20257d9119bdSJack F Vogel 		   ((u32) addr[1] << 8) |
20267d9119bdSJack F Vogel 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
20277d9119bdSJack F Vogel 
20287d9119bdSJack F Vogel 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
20297d9119bdSJack F Vogel 
20307d9119bdSJack F Vogel 	/* If MAC address zero, no need to set the AV bit */
20317d9119bdSJack F Vogel 	if (rar_low || rar_high)
20327d9119bdSJack F Vogel 		rar_high |= E1000_RAH_AV;
20337d9119bdSJack F Vogel 
20347d9119bdSJack F Vogel 	if (index == 0) {
20357d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
20367d9119bdSJack F Vogel 		E1000_WRITE_FLUSH(hw);
20377d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
20387d9119bdSJack F Vogel 		E1000_WRITE_FLUSH(hw);
20398cc64f1eSJack F Vogel 		return E1000_SUCCESS;
20407d9119bdSJack F Vogel 	}
20417d9119bdSJack F Vogel 
20427609433eSJack F Vogel 	/* RAR[1-6] are owned by manageability.  Skip those and program the
20437609433eSJack F Vogel 	 * next address into the SHRA register array.
20447609433eSJack F Vogel 	 */
20458cc64f1eSJack F Vogel 	if (index < (u32) (hw->mac.rar_entry_count)) {
20466ab6bfe3SJack F Vogel 		s32 ret_val;
20476ab6bfe3SJack F Vogel 
20486ab6bfe3SJack F Vogel 		ret_val = e1000_acquire_swflag_ich8lan(hw);
20496ab6bfe3SJack F Vogel 		if (ret_val)
20506ab6bfe3SJack F Vogel 			goto out;
20516ab6bfe3SJack F Vogel 
20527d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
20537d9119bdSJack F Vogel 		E1000_WRITE_FLUSH(hw);
20547d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
20557d9119bdSJack F Vogel 		E1000_WRITE_FLUSH(hw);
20567d9119bdSJack F Vogel 
20576ab6bfe3SJack F Vogel 		e1000_release_swflag_ich8lan(hw);
20586ab6bfe3SJack F Vogel 
20597d9119bdSJack F Vogel 		/* verify the register updates */
20607d9119bdSJack F Vogel 		if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
20617d9119bdSJack F Vogel 		    (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
20628cc64f1eSJack F Vogel 			return E1000_SUCCESS;
20637d9119bdSJack F Vogel 
20647d9119bdSJack F Vogel 		DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
20657d9119bdSJack F Vogel 			 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
20667d9119bdSJack F Vogel 	}
20677d9119bdSJack F Vogel 
20686ab6bfe3SJack F Vogel out:
20696ab6bfe3SJack F Vogel 	DEBUGOUT1("Failed to write receive address at index %d\n", index);
20708cc64f1eSJack F Vogel 	return -E1000_ERR_CONFIG;
20716ab6bfe3SJack F Vogel }
20726ab6bfe3SJack F Vogel 
20736ab6bfe3SJack F Vogel /**
20746ab6bfe3SJack F Vogel  *  e1000_rar_set_pch_lpt - Set receive address registers
20756ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
20766ab6bfe3SJack F Vogel  *  @addr: pointer to the receive address
20776ab6bfe3SJack F Vogel  *  @index: receive address array register
20786ab6bfe3SJack F Vogel  *
20796ab6bfe3SJack F Vogel  *  Sets the receive address register array at index to the address passed
20806ab6bfe3SJack F Vogel  *  in by addr. For LPT, RAR[0] is the base address register that is to
20816ab6bfe3SJack F Vogel  *  contain the MAC address. SHRA[0-10] are the shared receive address
20826ab6bfe3SJack F Vogel  *  registers that are shared between the Host and manageability engine (ME).
20836ab6bfe3SJack F Vogel  **/
20848cc64f1eSJack F Vogel static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
20856ab6bfe3SJack F Vogel {
20866ab6bfe3SJack F Vogel 	u32 rar_low, rar_high;
20876ab6bfe3SJack F Vogel 	u32 wlock_mac;
20886ab6bfe3SJack F Vogel 
20896ab6bfe3SJack F Vogel 	DEBUGFUNC("e1000_rar_set_pch_lpt");
20906ab6bfe3SJack F Vogel 
20916ab6bfe3SJack F Vogel 	/* HW expects these in little endian so we reverse the byte order
20926ab6bfe3SJack F Vogel 	 * from network order (big endian) to little endian
20936ab6bfe3SJack F Vogel 	 */
20946ab6bfe3SJack F Vogel 	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
20956ab6bfe3SJack F Vogel 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
20966ab6bfe3SJack F Vogel 
20976ab6bfe3SJack F Vogel 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
20986ab6bfe3SJack F Vogel 
20996ab6bfe3SJack F Vogel 	/* If MAC address zero, no need to set the AV bit */
21006ab6bfe3SJack F Vogel 	if (rar_low || rar_high)
21016ab6bfe3SJack F Vogel 		rar_high |= E1000_RAH_AV;
21026ab6bfe3SJack F Vogel 
21036ab6bfe3SJack F Vogel 	if (index == 0) {
21046ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
21056ab6bfe3SJack F Vogel 		E1000_WRITE_FLUSH(hw);
21066ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
21076ab6bfe3SJack F Vogel 		E1000_WRITE_FLUSH(hw);
21088cc64f1eSJack F Vogel 		return E1000_SUCCESS;
21096ab6bfe3SJack F Vogel 	}
21106ab6bfe3SJack F Vogel 
21116ab6bfe3SJack F Vogel 	/* The manageability engine (ME) can lock certain SHRAR registers that
21126ab6bfe3SJack F Vogel 	 * it is using - those registers are unavailable for use.
21136ab6bfe3SJack F Vogel 	 */
21146ab6bfe3SJack F Vogel 	if (index < hw->mac.rar_entry_count) {
21156ab6bfe3SJack F Vogel 		wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
21166ab6bfe3SJack F Vogel 			    E1000_FWSM_WLOCK_MAC_MASK;
21176ab6bfe3SJack F Vogel 		wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
21186ab6bfe3SJack F Vogel 
21196ab6bfe3SJack F Vogel 		/* Check if all SHRAR registers are locked */
21206ab6bfe3SJack F Vogel 		if (wlock_mac == 1)
21216ab6bfe3SJack F Vogel 			goto out;
21226ab6bfe3SJack F Vogel 
21236ab6bfe3SJack F Vogel 		if ((wlock_mac == 0) || (index <= wlock_mac)) {
21246ab6bfe3SJack F Vogel 			s32 ret_val;
21256ab6bfe3SJack F Vogel 
21266ab6bfe3SJack F Vogel 			ret_val = e1000_acquire_swflag_ich8lan(hw);
21276ab6bfe3SJack F Vogel 
21286ab6bfe3SJack F Vogel 			if (ret_val)
21296ab6bfe3SJack F Vogel 				goto out;
21306ab6bfe3SJack F Vogel 
21316ab6bfe3SJack F Vogel 			E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
21326ab6bfe3SJack F Vogel 					rar_low);
21336ab6bfe3SJack F Vogel 			E1000_WRITE_FLUSH(hw);
21346ab6bfe3SJack F Vogel 			E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
21356ab6bfe3SJack F Vogel 					rar_high);
21366ab6bfe3SJack F Vogel 			E1000_WRITE_FLUSH(hw);
21376ab6bfe3SJack F Vogel 
21386ab6bfe3SJack F Vogel 			e1000_release_swflag_ich8lan(hw);
21396ab6bfe3SJack F Vogel 
21406ab6bfe3SJack F Vogel 			/* verify the register updates */
21416ab6bfe3SJack F Vogel 			if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
21426ab6bfe3SJack F Vogel 			    (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
21438cc64f1eSJack F Vogel 				return E1000_SUCCESS;
21446ab6bfe3SJack F Vogel 		}
21456ab6bfe3SJack F Vogel 	}
21466ab6bfe3SJack F Vogel 
21476ab6bfe3SJack F Vogel out:
21487d9119bdSJack F Vogel 	DEBUGOUT1("Failed to write receive address at index %d\n", index);
21498cc64f1eSJack F Vogel 	return -E1000_ERR_CONFIG;
21508cfa0ad2SJack F Vogel }
21518cfa0ad2SJack F Vogel 
21528cfa0ad2SJack F Vogel /**
2153730d3130SJack F Vogel  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2154730d3130SJack F Vogel  *  @hw: pointer to the HW structure
2155730d3130SJack F Vogel  *  @mc_addr_list: array of multicast addresses to program
2156730d3130SJack F Vogel  *  @mc_addr_count: number of multicast addresses to program
2157730d3130SJack F Vogel  *
2158730d3130SJack F Vogel  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2159730d3130SJack F Vogel  *  The caller must have a packed mc_addr_list of multicast addresses.
2160730d3130SJack F Vogel  **/
2161730d3130SJack F Vogel static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2162730d3130SJack F Vogel 					      u8 *mc_addr_list,
2163730d3130SJack F Vogel 					      u32 mc_addr_count)
2164730d3130SJack F Vogel {
21654dab5c37SJack F Vogel 	u16 phy_reg = 0;
2166730d3130SJack F Vogel 	int i;
21674dab5c37SJack F Vogel 	s32 ret_val;
2168730d3130SJack F Vogel 
2169730d3130SJack F Vogel 	DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2170730d3130SJack F Vogel 
2171730d3130SJack F Vogel 	e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2172730d3130SJack F Vogel 
21734dab5c37SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
21744dab5c37SJack F Vogel 	if (ret_val)
21754dab5c37SJack F Vogel 		return;
21764dab5c37SJack F Vogel 
21774dab5c37SJack F Vogel 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
21784dab5c37SJack F Vogel 	if (ret_val)
21794dab5c37SJack F Vogel 		goto release;
21804dab5c37SJack F Vogel 
2181730d3130SJack F Vogel 	for (i = 0; i < hw->mac.mta_reg_count; i++) {
21824dab5c37SJack F Vogel 		hw->phy.ops.write_reg_page(hw, BM_MTA(i),
21834dab5c37SJack F Vogel 					   (u16)(hw->mac.mta_shadow[i] &
21844dab5c37SJack F Vogel 						 0xFFFF));
21854dab5c37SJack F Vogel 		hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2186730d3130SJack F Vogel 					   (u16)((hw->mac.mta_shadow[i] >> 16) &
2187730d3130SJack F Vogel 						 0xFFFF));
2188730d3130SJack F Vogel 	}
21894dab5c37SJack F Vogel 
21904dab5c37SJack F Vogel 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
21914dab5c37SJack F Vogel 
21924dab5c37SJack F Vogel release:
21934dab5c37SJack F Vogel 	hw->phy.ops.release(hw);
2194730d3130SJack F Vogel }
2195730d3130SJack F Vogel 
2196730d3130SJack F Vogel /**
21978cfa0ad2SJack F Vogel  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
21988cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
21998cfa0ad2SJack F Vogel  *
22008cfa0ad2SJack F Vogel  *  Checks if firmware is blocking the reset of the PHY.
22018cfa0ad2SJack F Vogel  *  This is a function pointer entry point only called by
22028cfa0ad2SJack F Vogel  *  reset routines.
22038cfa0ad2SJack F Vogel  **/
22048cfa0ad2SJack F Vogel static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
22058cfa0ad2SJack F Vogel {
22068cfa0ad2SJack F Vogel 	u32 fwsm;
22077609433eSJack F Vogel 	bool blocked = FALSE;
22087609433eSJack F Vogel 	int i = 0;
22098cfa0ad2SJack F Vogel 
22108cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_check_reset_block_ich8lan");
22118cfa0ad2SJack F Vogel 
22127609433eSJack F Vogel 	do {
22138cfa0ad2SJack F Vogel 		fwsm = E1000_READ_REG(hw, E1000_FWSM);
22147609433eSJack F Vogel 		if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
22157609433eSJack F Vogel 			blocked = TRUE;
22167609433eSJack F Vogel 			msec_delay(10);
22177609433eSJack F Vogel 			continue;
22187609433eSJack F Vogel 		}
22197609433eSJack F Vogel 		blocked = FALSE;
2220c80429ceSEric Joyner 	} while (blocked && (i++ < 30));
22217609433eSJack F Vogel 	return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
22228cfa0ad2SJack F Vogel }
22238cfa0ad2SJack F Vogel 
22248cfa0ad2SJack F Vogel /**
22257d9119bdSJack F Vogel  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
22267d9119bdSJack F Vogel  *  @hw: pointer to the HW structure
22277d9119bdSJack F Vogel  *
22287d9119bdSJack F Vogel  *  Assumes semaphore already acquired.
22297d9119bdSJack F Vogel  *
22307d9119bdSJack F Vogel  **/
22317d9119bdSJack F Vogel static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
22327d9119bdSJack F Vogel {
22337d9119bdSJack F Vogel 	u16 phy_data;
22347d9119bdSJack F Vogel 	u32 strap = E1000_READ_REG(hw, E1000_STRAP);
22356ab6bfe3SJack F Vogel 	u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
22366ab6bfe3SJack F Vogel 		E1000_STRAP_SMT_FREQ_SHIFT;
22376ab6bfe3SJack F Vogel 	s32 ret_val;
22387d9119bdSJack F Vogel 
22397d9119bdSJack F Vogel 	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
22407d9119bdSJack F Vogel 
22417d9119bdSJack F Vogel 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
22427d9119bdSJack F Vogel 	if (ret_val)
22436ab6bfe3SJack F Vogel 		return ret_val;
22447d9119bdSJack F Vogel 
22457d9119bdSJack F Vogel 	phy_data &= ~HV_SMB_ADDR_MASK;
22467d9119bdSJack F Vogel 	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
22477d9119bdSJack F Vogel 	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
22487d9119bdSJack F Vogel 
22496ab6bfe3SJack F Vogel 	if (hw->phy.type == e1000_phy_i217) {
22506ab6bfe3SJack F Vogel 		/* Restore SMBus frequency */
22516ab6bfe3SJack F Vogel 		if (freq--) {
22526ab6bfe3SJack F Vogel 			phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
22536ab6bfe3SJack F Vogel 			phy_data |= (freq & (1 << 0)) <<
22546ab6bfe3SJack F Vogel 				HV_SMB_ADDR_FREQ_LOW_SHIFT;
22556ab6bfe3SJack F Vogel 			phy_data |= (freq & (1 << 1)) <<
22566ab6bfe3SJack F Vogel 				(HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
22576ab6bfe3SJack F Vogel 		} else {
22586ab6bfe3SJack F Vogel 			DEBUGOUT("Unsupported SMB frequency in PHY\n");
22596ab6bfe3SJack F Vogel 		}
22606ab6bfe3SJack F Vogel 	}
22616ab6bfe3SJack F Vogel 
22626ab6bfe3SJack F Vogel 	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
22637d9119bdSJack F Vogel }
22647d9119bdSJack F Vogel 
22657d9119bdSJack F Vogel /**
22664edd8523SJack F Vogel  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
22674edd8523SJack F Vogel  *  @hw:   pointer to the HW structure
22684edd8523SJack F Vogel  *
22694edd8523SJack F Vogel  *  SW should configure the LCD from the NVM extended configuration region
22704edd8523SJack F Vogel  *  as a workaround for certain parts.
22714edd8523SJack F Vogel  **/
22724edd8523SJack F Vogel static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
22734edd8523SJack F Vogel {
22744edd8523SJack F Vogel 	struct e1000_phy_info *phy = &hw->phy;
22754edd8523SJack F Vogel 	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2276a69ed8dfSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
22774edd8523SJack F Vogel 	u16 word_addr, reg_data, reg_addr, phy_page = 0;
22784edd8523SJack F Vogel 
22797d9119bdSJack F Vogel 	DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
22804edd8523SJack F Vogel 
22816ab6bfe3SJack F Vogel 	/* Initialize the PHY from the NVM on ICH platforms.  This
22824edd8523SJack F Vogel 	 * is needed due to an issue where the NVM configuration is
22834edd8523SJack F Vogel 	 * not properly autoloaded after power transitions.
22844edd8523SJack F Vogel 	 * Therefore, after each PHY reset, we will load the
22854edd8523SJack F Vogel 	 * configuration data out of the NVM manually.
22864edd8523SJack F Vogel 	 */
22877d9119bdSJack F Vogel 	switch (hw->mac.type) {
22887d9119bdSJack F Vogel 	case e1000_ich8lan:
22897d9119bdSJack F Vogel 		if (phy->type != e1000_phy_igp_3)
22907d9119bdSJack F Vogel 			return ret_val;
22917d9119bdSJack F Vogel 
22927d9119bdSJack F Vogel 		if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
22937d9119bdSJack F Vogel 		    (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
22944edd8523SJack F Vogel 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
22957d9119bdSJack F Vogel 			break;
22967d9119bdSJack F Vogel 		}
22977d9119bdSJack F Vogel 		/* Fall-thru */
22987d9119bdSJack F Vogel 	case e1000_pchlan:
22997d9119bdSJack F Vogel 	case e1000_pch2lan:
23006ab6bfe3SJack F Vogel 	case e1000_pch_lpt:
2301c80429ceSEric Joyner 	case e1000_pch_spt:
2302*6fe4c0a0SSean Bruno 	case e1000_pch_cnp:
23037d9119bdSJack F Vogel 		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
23047d9119bdSJack F Vogel 		break;
23057d9119bdSJack F Vogel 	default:
23067d9119bdSJack F Vogel 		return ret_val;
23077d9119bdSJack F Vogel 	}
23087d9119bdSJack F Vogel 
23097d9119bdSJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
23107d9119bdSJack F Vogel 	if (ret_val)
23117d9119bdSJack F Vogel 		return ret_val;
23124edd8523SJack F Vogel 
23134edd8523SJack F Vogel 	data = E1000_READ_REG(hw, E1000_FEXTNVM);
23144edd8523SJack F Vogel 	if (!(data & sw_cfg_mask))
23156ab6bfe3SJack F Vogel 		goto release;
23164edd8523SJack F Vogel 
23176ab6bfe3SJack F Vogel 	/* Make sure HW does not configure LCD from PHY
23184edd8523SJack F Vogel 	 * extended configuration before SW configuration
23194edd8523SJack F Vogel 	 */
23204edd8523SJack F Vogel 	data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
23216ab6bfe3SJack F Vogel 	if ((hw->mac.type < e1000_pch2lan) &&
23226ab6bfe3SJack F Vogel 	    (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
23236ab6bfe3SJack F Vogel 			goto release;
23244edd8523SJack F Vogel 
23254edd8523SJack F Vogel 	cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
23264edd8523SJack F Vogel 	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
23274edd8523SJack F Vogel 	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
23284edd8523SJack F Vogel 	if (!cnf_size)
23296ab6bfe3SJack F Vogel 		goto release;
23304edd8523SJack F Vogel 
23314edd8523SJack F Vogel 	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
23324edd8523SJack F Vogel 	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
23334edd8523SJack F Vogel 
23346ab6bfe3SJack F Vogel 	if (((hw->mac.type == e1000_pchlan) &&
23356ab6bfe3SJack F Vogel 	     !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
23366ab6bfe3SJack F Vogel 	    (hw->mac.type > e1000_pchlan)) {
23376ab6bfe3SJack F Vogel 		/* HW configures the SMBus address and LEDs when the
23384edd8523SJack F Vogel 		 * OEM and LCD Write Enable bits are set in the NVM.
23394edd8523SJack F Vogel 		 * When both NVM bits are cleared, SW will configure
23404edd8523SJack F Vogel 		 * them instead.
23414edd8523SJack F Vogel 		 */
23427d9119bdSJack F Vogel 		ret_val = e1000_write_smbus_addr(hw);
23434edd8523SJack F Vogel 		if (ret_val)
23446ab6bfe3SJack F Vogel 			goto release;
23454edd8523SJack F Vogel 
23464edd8523SJack F Vogel 		data = E1000_READ_REG(hw, E1000_LEDCTL);
2347a69ed8dfSJack F Vogel 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
23484edd8523SJack F Vogel 							(u16)data);
23494edd8523SJack F Vogel 		if (ret_val)
23506ab6bfe3SJack F Vogel 			goto release;
23514edd8523SJack F Vogel 	}
23524edd8523SJack F Vogel 
23534edd8523SJack F Vogel 	/* Configure LCD from extended configuration region. */
23544edd8523SJack F Vogel 
23554edd8523SJack F Vogel 	/* cnf_base_addr is in DWORD */
23564edd8523SJack F Vogel 	word_addr = (u16)(cnf_base_addr << 1);
23574edd8523SJack F Vogel 
23584edd8523SJack F Vogel 	for (i = 0; i < cnf_size; i++) {
23594edd8523SJack F Vogel 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
23604edd8523SJack F Vogel 					   &reg_data);
23614edd8523SJack F Vogel 		if (ret_val)
23626ab6bfe3SJack F Vogel 			goto release;
23634edd8523SJack F Vogel 
23644edd8523SJack F Vogel 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
23654edd8523SJack F Vogel 					   1, &reg_addr);
23664edd8523SJack F Vogel 		if (ret_val)
23676ab6bfe3SJack F Vogel 			goto release;
23684edd8523SJack F Vogel 
23694edd8523SJack F Vogel 		/* Save off the PHY page for future writes. */
23704edd8523SJack F Vogel 		if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
23714edd8523SJack F Vogel 			phy_page = reg_data;
23724edd8523SJack F Vogel 			continue;
23734edd8523SJack F Vogel 		}
23744edd8523SJack F Vogel 
23754edd8523SJack F Vogel 		reg_addr &= PHY_REG_MASK;
23764edd8523SJack F Vogel 		reg_addr |= phy_page;
23774edd8523SJack F Vogel 
23784edd8523SJack F Vogel 		ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
23794edd8523SJack F Vogel 						    reg_data);
23804edd8523SJack F Vogel 		if (ret_val)
23816ab6bfe3SJack F Vogel 			goto release;
23824edd8523SJack F Vogel 	}
23834edd8523SJack F Vogel 
23846ab6bfe3SJack F Vogel release:
23854edd8523SJack F Vogel 	hw->phy.ops.release(hw);
23864edd8523SJack F Vogel 	return ret_val;
23874edd8523SJack F Vogel }
23884edd8523SJack F Vogel 
23894edd8523SJack F Vogel /**
23904edd8523SJack F Vogel  *  e1000_k1_gig_workaround_hv - K1 Si workaround
23914edd8523SJack F Vogel  *  @hw:   pointer to the HW structure
23924edd8523SJack F Vogel  *  @link: link up bool flag
23934edd8523SJack F Vogel  *
23944edd8523SJack F Vogel  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
23954edd8523SJack F Vogel  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
23964edd8523SJack F Vogel  *  If link is down, the function will restore the default K1 setting located
23974edd8523SJack F Vogel  *  in the NVM.
23984edd8523SJack F Vogel  **/
23994edd8523SJack F Vogel static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
24004edd8523SJack F Vogel {
24014edd8523SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
24024edd8523SJack F Vogel 	u16 status_reg = 0;
24034edd8523SJack F Vogel 	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
24044edd8523SJack F Vogel 
24054edd8523SJack F Vogel 	DEBUGFUNC("e1000_k1_gig_workaround_hv");
24064edd8523SJack F Vogel 
24074edd8523SJack F Vogel 	if (hw->mac.type != e1000_pchlan)
24086ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
24094edd8523SJack F Vogel 
24104edd8523SJack F Vogel 	/* Wrap the whole flow with the sw flag */
24114edd8523SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
24124edd8523SJack F Vogel 	if (ret_val)
24136ab6bfe3SJack F Vogel 		return ret_val;
24144edd8523SJack F Vogel 
24154edd8523SJack F Vogel 	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
24164edd8523SJack F Vogel 	if (link) {
24174edd8523SJack F Vogel 		if (hw->phy.type == e1000_phy_82578) {
24184edd8523SJack F Vogel 			ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
24194edd8523SJack F Vogel 							      &status_reg);
24204edd8523SJack F Vogel 			if (ret_val)
24214edd8523SJack F Vogel 				goto release;
24224edd8523SJack F Vogel 
24237609433eSJack F Vogel 			status_reg &= (BM_CS_STATUS_LINK_UP |
24244edd8523SJack F Vogel 				       BM_CS_STATUS_RESOLVED |
24257609433eSJack F Vogel 				       BM_CS_STATUS_SPEED_MASK);
24264edd8523SJack F Vogel 
24274edd8523SJack F Vogel 			if (status_reg == (BM_CS_STATUS_LINK_UP |
24284edd8523SJack F Vogel 					   BM_CS_STATUS_RESOLVED |
24294edd8523SJack F Vogel 					   BM_CS_STATUS_SPEED_1000))
24304edd8523SJack F Vogel 				k1_enable = FALSE;
24314edd8523SJack F Vogel 		}
24324edd8523SJack F Vogel 
24334edd8523SJack F Vogel 		if (hw->phy.type == e1000_phy_82577) {
24344edd8523SJack F Vogel 			ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
24354edd8523SJack F Vogel 							      &status_reg);
24364edd8523SJack F Vogel 			if (ret_val)
24374edd8523SJack F Vogel 				goto release;
24384edd8523SJack F Vogel 
24397609433eSJack F Vogel 			status_reg &= (HV_M_STATUS_LINK_UP |
24404edd8523SJack F Vogel 				       HV_M_STATUS_AUTONEG_COMPLETE |
24417609433eSJack F Vogel 				       HV_M_STATUS_SPEED_MASK);
24424edd8523SJack F Vogel 
24434edd8523SJack F Vogel 			if (status_reg == (HV_M_STATUS_LINK_UP |
24444edd8523SJack F Vogel 					   HV_M_STATUS_AUTONEG_COMPLETE |
24454edd8523SJack F Vogel 					   HV_M_STATUS_SPEED_1000))
24464edd8523SJack F Vogel 				k1_enable = FALSE;
24474edd8523SJack F Vogel 		}
24484edd8523SJack F Vogel 
24494edd8523SJack F Vogel 		/* Link stall fix for link up */
24504edd8523SJack F Vogel 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
24514edd8523SJack F Vogel 						       0x0100);
24524edd8523SJack F Vogel 		if (ret_val)
24534edd8523SJack F Vogel 			goto release;
24544edd8523SJack F Vogel 
24554edd8523SJack F Vogel 	} else {
24564edd8523SJack F Vogel 		/* Link stall fix for link down */
24574edd8523SJack F Vogel 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
24584edd8523SJack F Vogel 						       0x4100);
24594edd8523SJack F Vogel 		if (ret_val)
24604edd8523SJack F Vogel 			goto release;
24614edd8523SJack F Vogel 	}
24624edd8523SJack F Vogel 
24634edd8523SJack F Vogel 	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
24644edd8523SJack F Vogel 
24654edd8523SJack F Vogel release:
24664edd8523SJack F Vogel 	hw->phy.ops.release(hw);
24676ab6bfe3SJack F Vogel 
24684edd8523SJack F Vogel 	return ret_val;
24694edd8523SJack F Vogel }
24704edd8523SJack F Vogel 
24714edd8523SJack F Vogel /**
24724edd8523SJack F Vogel  *  e1000_configure_k1_ich8lan - Configure K1 power state
24734edd8523SJack F Vogel  *  @hw: pointer to the HW structure
24744edd8523SJack F Vogel  *  @enable: K1 state to configure
24754edd8523SJack F Vogel  *
24764edd8523SJack F Vogel  *  Configure the K1 power state based on the provided parameter.
24774edd8523SJack F Vogel  *  Assumes semaphore already acquired.
24784edd8523SJack F Vogel  *
24794edd8523SJack F Vogel  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
24804edd8523SJack F Vogel  **/
24814edd8523SJack F Vogel s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
24824edd8523SJack F Vogel {
24836ab6bfe3SJack F Vogel 	s32 ret_val;
24844edd8523SJack F Vogel 	u32 ctrl_reg = 0;
24854edd8523SJack F Vogel 	u32 ctrl_ext = 0;
24864edd8523SJack F Vogel 	u32 reg = 0;
24874edd8523SJack F Vogel 	u16 kmrn_reg = 0;
24884edd8523SJack F Vogel 
24897d9119bdSJack F Vogel 	DEBUGFUNC("e1000_configure_k1_ich8lan");
24907d9119bdSJack F Vogel 
24914dab5c37SJack F Vogel 	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
24924edd8523SJack F Vogel 					     &kmrn_reg);
24934edd8523SJack F Vogel 	if (ret_val)
24946ab6bfe3SJack F Vogel 		return ret_val;
24954edd8523SJack F Vogel 
24964edd8523SJack F Vogel 	if (k1_enable)
24974edd8523SJack F Vogel 		kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
24984edd8523SJack F Vogel 	else
24994edd8523SJack F Vogel 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
25004edd8523SJack F Vogel 
25014dab5c37SJack F Vogel 	ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
25024edd8523SJack F Vogel 					      kmrn_reg);
25034edd8523SJack F Vogel 	if (ret_val)
25046ab6bfe3SJack F Vogel 		return ret_val;
25054edd8523SJack F Vogel 
25064edd8523SJack F Vogel 	usec_delay(20);
25074edd8523SJack F Vogel 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
25084edd8523SJack F Vogel 	ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
25094edd8523SJack F Vogel 
25104edd8523SJack F Vogel 	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
25114edd8523SJack F Vogel 	reg |= E1000_CTRL_FRCSPD;
25124edd8523SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, reg);
25134edd8523SJack F Vogel 
25144edd8523SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
25154dab5c37SJack F Vogel 	E1000_WRITE_FLUSH(hw);
25164edd8523SJack F Vogel 	usec_delay(20);
25174edd8523SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
25184edd8523SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
25194dab5c37SJack F Vogel 	E1000_WRITE_FLUSH(hw);
25204edd8523SJack F Vogel 	usec_delay(20);
25214edd8523SJack F Vogel 
25226ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
25234edd8523SJack F Vogel }
25244edd8523SJack F Vogel 
25254edd8523SJack F Vogel /**
25264edd8523SJack F Vogel  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
25274edd8523SJack F Vogel  *  @hw:       pointer to the HW structure
25284edd8523SJack F Vogel  *  @d0_state: boolean if entering d0 or d3 device state
25294edd8523SJack F Vogel  *
25304edd8523SJack F Vogel  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
25314edd8523SJack F Vogel  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
25324edd8523SJack F Vogel  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
25334edd8523SJack F Vogel  **/
25344dab5c37SJack F Vogel static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
25354edd8523SJack F Vogel {
25364edd8523SJack F Vogel 	s32 ret_val = 0;
25374edd8523SJack F Vogel 	u32 mac_reg;
25384edd8523SJack F Vogel 	u16 oem_reg;
25394edd8523SJack F Vogel 
25407d9119bdSJack F Vogel 	DEBUGFUNC("e1000_oem_bits_config_ich8lan");
25417d9119bdSJack F Vogel 
25426ab6bfe3SJack F Vogel 	if (hw->mac.type < e1000_pchlan)
25434edd8523SJack F Vogel 		return ret_val;
25444edd8523SJack F Vogel 
25454edd8523SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
25464edd8523SJack F Vogel 	if (ret_val)
25474edd8523SJack F Vogel 		return ret_val;
25484edd8523SJack F Vogel 
25496ab6bfe3SJack F Vogel 	if (hw->mac.type == e1000_pchlan) {
25504edd8523SJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
25514edd8523SJack F Vogel 		if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
25526ab6bfe3SJack F Vogel 			goto release;
25537d9119bdSJack F Vogel 	}
25544edd8523SJack F Vogel 
25554edd8523SJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
25564edd8523SJack F Vogel 	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
25576ab6bfe3SJack F Vogel 		goto release;
25584edd8523SJack F Vogel 
25594edd8523SJack F Vogel 	mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
25604edd8523SJack F Vogel 
25614edd8523SJack F Vogel 	ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
25624edd8523SJack F Vogel 	if (ret_val)
25636ab6bfe3SJack F Vogel 		goto release;
25644edd8523SJack F Vogel 
25654edd8523SJack F Vogel 	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
25664edd8523SJack F Vogel 
25674edd8523SJack F Vogel 	if (d0_state) {
25684edd8523SJack F Vogel 		if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
25694edd8523SJack F Vogel 			oem_reg |= HV_OEM_BITS_GBE_DIS;
25704edd8523SJack F Vogel 
25714edd8523SJack F Vogel 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
25724edd8523SJack F Vogel 			oem_reg |= HV_OEM_BITS_LPLU;
25734dab5c37SJack F Vogel 	} else {
25744dab5c37SJack F Vogel 		if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
25754dab5c37SJack F Vogel 		    E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
25764dab5c37SJack F Vogel 			oem_reg |= HV_OEM_BITS_GBE_DIS;
25774dab5c37SJack F Vogel 
25784dab5c37SJack F Vogel 		if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
25794dab5c37SJack F Vogel 		    E1000_PHY_CTRL_NOND0A_LPLU))
25804dab5c37SJack F Vogel 			oem_reg |= HV_OEM_BITS_LPLU;
25814dab5c37SJack F Vogel 	}
25824dab5c37SJack F Vogel 
25836ab6bfe3SJack F Vogel 	/* Set Restart auto-neg to activate the bits */
25846ab6bfe3SJack F Vogel 	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
25856ab6bfe3SJack F Vogel 	    !hw->phy.ops.check_reset_block(hw))
25866ab6bfe3SJack F Vogel 		oem_reg |= HV_OEM_BITS_RESTART_AN;
25876ab6bfe3SJack F Vogel 
25884edd8523SJack F Vogel 	ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
25894edd8523SJack F Vogel 
25906ab6bfe3SJack F Vogel release:
25914edd8523SJack F Vogel 	hw->phy.ops.release(hw);
25924edd8523SJack F Vogel 
25934edd8523SJack F Vogel 	return ret_val;
25944edd8523SJack F Vogel }
25954edd8523SJack F Vogel 
25964edd8523SJack F Vogel 
25974edd8523SJack F Vogel /**
2598a69ed8dfSJack F Vogel  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2599a69ed8dfSJack F Vogel  *  @hw:   pointer to the HW structure
2600a69ed8dfSJack F Vogel  **/
2601a69ed8dfSJack F Vogel static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2602a69ed8dfSJack F Vogel {
2603a69ed8dfSJack F Vogel 	s32 ret_val;
2604a69ed8dfSJack F Vogel 	u16 data;
2605a69ed8dfSJack F Vogel 
26067d9119bdSJack F Vogel 	DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
26077d9119bdSJack F Vogel 
2608a69ed8dfSJack F Vogel 	ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2609a69ed8dfSJack F Vogel 	if (ret_val)
2610a69ed8dfSJack F Vogel 		return ret_val;
2611a69ed8dfSJack F Vogel 
2612a69ed8dfSJack F Vogel 	data |= HV_KMRN_MDIO_SLOW;
2613a69ed8dfSJack F Vogel 
2614a69ed8dfSJack F Vogel 	ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2615a69ed8dfSJack F Vogel 
2616a69ed8dfSJack F Vogel 	return ret_val;
2617a69ed8dfSJack F Vogel }
2618a69ed8dfSJack F Vogel 
2619a69ed8dfSJack F Vogel /**
26209d81738fSJack F Vogel  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
26219d81738fSJack F Vogel  *  done after every PHY reset.
26229d81738fSJack F Vogel  **/
26239d81738fSJack F Vogel static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
26249d81738fSJack F Vogel {
26259d81738fSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
2626a69ed8dfSJack F Vogel 	u16 phy_data;
26279d81738fSJack F Vogel 
26287d9119bdSJack F Vogel 	DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
26297d9119bdSJack F Vogel 
26309d81738fSJack F Vogel 	if (hw->mac.type != e1000_pchlan)
26316ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
26329d81738fSJack F Vogel 
2633a69ed8dfSJack F Vogel 	/* Set MDIO slow mode before any other MDIO access */
2634a69ed8dfSJack F Vogel 	if (hw->phy.type == e1000_phy_82577) {
2635a69ed8dfSJack F Vogel 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
2636a69ed8dfSJack F Vogel 		if (ret_val)
26376ab6bfe3SJack F Vogel 			return ret_val;
2638a69ed8dfSJack F Vogel 	}
2639a69ed8dfSJack F Vogel 
26409d81738fSJack F Vogel 	if (((hw->phy.type == e1000_phy_82577) &&
26419d81738fSJack F Vogel 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
26429d81738fSJack F Vogel 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
26439d81738fSJack F Vogel 		/* Disable generation of early preamble */
26449d81738fSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
26459d81738fSJack F Vogel 		if (ret_val)
26466ab6bfe3SJack F Vogel 			return ret_val;
26479d81738fSJack F Vogel 
26489d81738fSJack F Vogel 		/* Preamble tuning for SSC */
26494dab5c37SJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
26504dab5c37SJack F Vogel 						0xA204);
26519d81738fSJack F Vogel 		if (ret_val)
26526ab6bfe3SJack F Vogel 			return ret_val;
26539d81738fSJack F Vogel 	}
26549d81738fSJack F Vogel 
26559d81738fSJack F Vogel 	if (hw->phy.type == e1000_phy_82578) {
26566ab6bfe3SJack F Vogel 		/* Return registers to default by doing a soft reset then
26579d81738fSJack F Vogel 		 * writing 0x3140 to the control register.
26589d81738fSJack F Vogel 		 */
26599d81738fSJack F Vogel 		if (hw->phy.revision < 2) {
26609d81738fSJack F Vogel 			e1000_phy_sw_reset_generic(hw);
26619d81738fSJack F Vogel 			ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
26629d81738fSJack F Vogel 							0x3140);
2663*6fe4c0a0SSean Bruno 			if (ret_val)
2664*6fe4c0a0SSean Bruno 				return ret_val;
26659d81738fSJack F Vogel 		}
26669d81738fSJack F Vogel 	}
26679d81738fSJack F Vogel 
26689d81738fSJack F Vogel 	/* Select page 0 */
26699d81738fSJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
26709d81738fSJack F Vogel 	if (ret_val)
26716ab6bfe3SJack F Vogel 		return ret_val;
26724edd8523SJack F Vogel 
26739d81738fSJack F Vogel 	hw->phy.addr = 1;
26744edd8523SJack F Vogel 	ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2675a69ed8dfSJack F Vogel 	hw->phy.ops.release(hw);
26764edd8523SJack F Vogel 	if (ret_val)
26776ab6bfe3SJack F Vogel 		return ret_val;
26789d81738fSJack F Vogel 
26796ab6bfe3SJack F Vogel 	/* Configure the K1 Si workaround during phy reset assuming there is
26804edd8523SJack F Vogel 	 * link so that it disables K1 if link is in 1Gbps.
26814edd8523SJack F Vogel 	 */
26824edd8523SJack F Vogel 	ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2683a69ed8dfSJack F Vogel 	if (ret_val)
26846ab6bfe3SJack F Vogel 		return ret_val;
26854edd8523SJack F Vogel 
2686a69ed8dfSJack F Vogel 	/* Workaround for link disconnects on a busy hub in half duplex */
2687a69ed8dfSJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
2688a69ed8dfSJack F Vogel 	if (ret_val)
26896ab6bfe3SJack F Vogel 		return ret_val;
26904dab5c37SJack F Vogel 	ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2691a69ed8dfSJack F Vogel 	if (ret_val)
2692a69ed8dfSJack F Vogel 		goto release;
26934dab5c37SJack F Vogel 	ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2694a69ed8dfSJack F Vogel 					       phy_data & 0x00FF);
26956ab6bfe3SJack F Vogel 	if (ret_val)
26966ab6bfe3SJack F Vogel 		goto release;
26976ab6bfe3SJack F Vogel 
26986ab6bfe3SJack F Vogel 	/* set MSE higher to enable link to stay up when noise is high */
26996ab6bfe3SJack F Vogel 	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2700a69ed8dfSJack F Vogel release:
2701a69ed8dfSJack F Vogel 	hw->phy.ops.release(hw);
27026ab6bfe3SJack F Vogel 
27039d81738fSJack F Vogel 	return ret_val;
27049d81738fSJack F Vogel }
27059d81738fSJack F Vogel 
27069d81738fSJack F Vogel /**
27077d9119bdSJack F Vogel  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
27087d9119bdSJack F Vogel  *  @hw:   pointer to the HW structure
27097d9119bdSJack F Vogel  **/
27107d9119bdSJack F Vogel void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
27117d9119bdSJack F Vogel {
27127d9119bdSJack F Vogel 	u32 mac_reg;
27134dab5c37SJack F Vogel 	u16 i, phy_reg = 0;
27144dab5c37SJack F Vogel 	s32 ret_val;
27157d9119bdSJack F Vogel 
27167d9119bdSJack F Vogel 	DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
27177d9119bdSJack F Vogel 
27184dab5c37SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
27194dab5c37SJack F Vogel 	if (ret_val)
27204dab5c37SJack F Vogel 		return;
27214dab5c37SJack F Vogel 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
27224dab5c37SJack F Vogel 	if (ret_val)
27234dab5c37SJack F Vogel 		goto release;
27244dab5c37SJack F Vogel 
27257609433eSJack F Vogel 	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
27267609433eSJack F Vogel 	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
27277d9119bdSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
27284dab5c37SJack F Vogel 		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
27294dab5c37SJack F Vogel 					   (u16)(mac_reg & 0xFFFF));
27304dab5c37SJack F Vogel 		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
27314dab5c37SJack F Vogel 					   (u16)((mac_reg >> 16) & 0xFFFF));
27324dab5c37SJack F Vogel 
27337d9119bdSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
27344dab5c37SJack F Vogel 		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
27354dab5c37SJack F Vogel 					   (u16)(mac_reg & 0xFFFF));
27364dab5c37SJack F Vogel 		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
27374dab5c37SJack F Vogel 					   (u16)((mac_reg & E1000_RAH_AV)
27384dab5c37SJack F Vogel 						 >> 16));
27397d9119bdSJack F Vogel 	}
27404dab5c37SJack F Vogel 
27414dab5c37SJack F Vogel 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
27424dab5c37SJack F Vogel 
27434dab5c37SJack F Vogel release:
27444dab5c37SJack F Vogel 	hw->phy.ops.release(hw);
27457d9119bdSJack F Vogel }
27467d9119bdSJack F Vogel 
27477d9119bdSJack F Vogel static u32 e1000_calc_rx_da_crc(u8 mac[])
27487d9119bdSJack F Vogel {
27497d9119bdSJack F Vogel 	u32 poly = 0xEDB88320;	/* Polynomial for 802.3 CRC calculation */
27507d9119bdSJack F Vogel 	u32 i, j, mask, crc;
27517d9119bdSJack F Vogel 
27527d9119bdSJack F Vogel 	DEBUGFUNC("e1000_calc_rx_da_crc");
27537d9119bdSJack F Vogel 
27547d9119bdSJack F Vogel 	crc = 0xffffffff;
27557d9119bdSJack F Vogel 	for (i = 0; i < 6; i++) {
27567d9119bdSJack F Vogel 		crc = crc ^ mac[i];
27577d9119bdSJack F Vogel 		for (j = 8; j > 0; j--) {
27587d9119bdSJack F Vogel 			mask = (crc & 1) * (-1);
27597d9119bdSJack F Vogel 			crc = (crc >> 1) ^ (poly & mask);
27607d9119bdSJack F Vogel 		}
27617d9119bdSJack F Vogel 	}
27627d9119bdSJack F Vogel 	return ~crc;
27637d9119bdSJack F Vogel }
27647d9119bdSJack F Vogel 
27657d9119bdSJack F Vogel /**
27667d9119bdSJack F Vogel  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
27677d9119bdSJack F Vogel  *  with 82579 PHY
27687d9119bdSJack F Vogel  *  @hw: pointer to the HW structure
27697d9119bdSJack F Vogel  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
27707d9119bdSJack F Vogel  **/
27717d9119bdSJack F Vogel s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
27727d9119bdSJack F Vogel {
27737d9119bdSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
27747d9119bdSJack F Vogel 	u16 phy_reg, data;
27757d9119bdSJack F Vogel 	u32 mac_reg;
27767d9119bdSJack F Vogel 	u16 i;
27777d9119bdSJack F Vogel 
27787d9119bdSJack F Vogel 	DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
27797d9119bdSJack F Vogel 
27806ab6bfe3SJack F Vogel 	if (hw->mac.type < e1000_pch2lan)
27816ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
27827d9119bdSJack F Vogel 
27837d9119bdSJack F Vogel 	/* disable Rx path while enabling/disabling workaround */
27847d9119bdSJack F Vogel 	hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
27854dab5c37SJack F Vogel 	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
27864dab5c37SJack F Vogel 					phy_reg | (1 << 14));
27877d9119bdSJack F Vogel 	if (ret_val)
27886ab6bfe3SJack F Vogel 		return ret_val;
27897d9119bdSJack F Vogel 
27907d9119bdSJack F Vogel 	if (enable) {
27917609433eSJack F Vogel 		/* Write Rx addresses (rar_entry_count for RAL/H, and
27927d9119bdSJack F Vogel 		 * SHRAL/H) and initial CRC values to the MAC
27937d9119bdSJack F Vogel 		 */
27947609433eSJack F Vogel 		for (i = 0; i < hw->mac.rar_entry_count; i++) {
27957d9119bdSJack F Vogel 			u8 mac_addr[ETH_ADDR_LEN] = {0};
27967d9119bdSJack F Vogel 			u32 addr_high, addr_low;
27977d9119bdSJack F Vogel 
27987d9119bdSJack F Vogel 			addr_high = E1000_READ_REG(hw, E1000_RAH(i));
27997d9119bdSJack F Vogel 			if (!(addr_high & E1000_RAH_AV))
28007d9119bdSJack F Vogel 				continue;
28017d9119bdSJack F Vogel 			addr_low = E1000_READ_REG(hw, E1000_RAL(i));
28027d9119bdSJack F Vogel 			mac_addr[0] = (addr_low & 0xFF);
28037d9119bdSJack F Vogel 			mac_addr[1] = ((addr_low >> 8) & 0xFF);
28047d9119bdSJack F Vogel 			mac_addr[2] = ((addr_low >> 16) & 0xFF);
28057d9119bdSJack F Vogel 			mac_addr[3] = ((addr_low >> 24) & 0xFF);
28067d9119bdSJack F Vogel 			mac_addr[4] = (addr_high & 0xFF);
28077d9119bdSJack F Vogel 			mac_addr[5] = ((addr_high >> 8) & 0xFF);
28087d9119bdSJack F Vogel 
28097d9119bdSJack F Vogel 			E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
28107d9119bdSJack F Vogel 					e1000_calc_rx_da_crc(mac_addr));
28117d9119bdSJack F Vogel 		}
28127d9119bdSJack F Vogel 
28137d9119bdSJack F Vogel 		/* Write Rx addresses to the PHY */
28147d9119bdSJack F Vogel 		e1000_copy_rx_addrs_to_phy_ich8lan(hw);
28157d9119bdSJack F Vogel 
28167d9119bdSJack F Vogel 		/* Enable jumbo frame workaround in the MAC */
28177d9119bdSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
28187d9119bdSJack F Vogel 		mac_reg &= ~(1 << 14);
28197d9119bdSJack F Vogel 		mac_reg |= (7 << 15);
28207d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
28217d9119bdSJack F Vogel 
28227d9119bdSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_RCTL);
28237d9119bdSJack F Vogel 		mac_reg |= E1000_RCTL_SECRC;
28247d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
28257d9119bdSJack F Vogel 
28267d9119bdSJack F Vogel 		ret_val = e1000_read_kmrn_reg_generic(hw,
28277d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
28287d9119bdSJack F Vogel 						&data);
28297d9119bdSJack F Vogel 		if (ret_val)
28306ab6bfe3SJack F Vogel 			return ret_val;
28317d9119bdSJack F Vogel 		ret_val = e1000_write_kmrn_reg_generic(hw,
28327d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
28337d9119bdSJack F Vogel 						data | (1 << 0));
28347d9119bdSJack F Vogel 		if (ret_val)
28356ab6bfe3SJack F Vogel 			return ret_val;
28367d9119bdSJack F Vogel 		ret_val = e1000_read_kmrn_reg_generic(hw,
28377d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_HD_CTRL,
28387d9119bdSJack F Vogel 						&data);
28397d9119bdSJack F Vogel 		if (ret_val)
28406ab6bfe3SJack F Vogel 			return ret_val;
28417d9119bdSJack F Vogel 		data &= ~(0xF << 8);
28427d9119bdSJack F Vogel 		data |= (0xB << 8);
28437d9119bdSJack F Vogel 		ret_val = e1000_write_kmrn_reg_generic(hw,
28447d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_HD_CTRL,
28457d9119bdSJack F Vogel 						data);
28467d9119bdSJack F Vogel 		if (ret_val)
28476ab6bfe3SJack F Vogel 			return ret_val;
28487d9119bdSJack F Vogel 
28497d9119bdSJack F Vogel 		/* Enable jumbo frame workaround in the PHY */
28507d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
28517d9119bdSJack F Vogel 		data &= ~(0x7F << 5);
28527d9119bdSJack F Vogel 		data |= (0x37 << 5);
28537d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
28547d9119bdSJack F Vogel 		if (ret_val)
28556ab6bfe3SJack F Vogel 			return ret_val;
28567d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
28577d9119bdSJack F Vogel 		data &= ~(1 << 13);
28587d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
28597d9119bdSJack F Vogel 		if (ret_val)
28606ab6bfe3SJack F Vogel 			return ret_val;
28617d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
28627d9119bdSJack F Vogel 		data &= ~(0x3FF << 2);
28638cc64f1eSJack F Vogel 		data |= (E1000_TX_PTR_GAP << 2);
28647d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
28657d9119bdSJack F Vogel 		if (ret_val)
28666ab6bfe3SJack F Vogel 			return ret_val;
28674dab5c37SJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
28687d9119bdSJack F Vogel 		if (ret_val)
28696ab6bfe3SJack F Vogel 			return ret_val;
28707d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
28714dab5c37SJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
28724dab5c37SJack F Vogel 						(1 << 10));
28737d9119bdSJack F Vogel 		if (ret_val)
28746ab6bfe3SJack F Vogel 			return ret_val;
28757d9119bdSJack F Vogel 	} else {
28767d9119bdSJack F Vogel 		/* Write MAC register values back to h/w defaults */
28777d9119bdSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
28787d9119bdSJack F Vogel 		mac_reg &= ~(0xF << 14);
28797d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
28807d9119bdSJack F Vogel 
28817d9119bdSJack F Vogel 		mac_reg = E1000_READ_REG(hw, E1000_RCTL);
28827d9119bdSJack F Vogel 		mac_reg &= ~E1000_RCTL_SECRC;
28837d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
28847d9119bdSJack F Vogel 
28857d9119bdSJack F Vogel 		ret_val = e1000_read_kmrn_reg_generic(hw,
28867d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
28877d9119bdSJack F Vogel 						&data);
28887d9119bdSJack F Vogel 		if (ret_val)
28896ab6bfe3SJack F Vogel 			return ret_val;
28907d9119bdSJack F Vogel 		ret_val = e1000_write_kmrn_reg_generic(hw,
28917d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
28927d9119bdSJack F Vogel 						data & ~(1 << 0));
28937d9119bdSJack F Vogel 		if (ret_val)
28946ab6bfe3SJack F Vogel 			return ret_val;
28957d9119bdSJack F Vogel 		ret_val = e1000_read_kmrn_reg_generic(hw,
28967d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_HD_CTRL,
28977d9119bdSJack F Vogel 						&data);
28987d9119bdSJack F Vogel 		if (ret_val)
28996ab6bfe3SJack F Vogel 			return ret_val;
29007d9119bdSJack F Vogel 		data &= ~(0xF << 8);
29017d9119bdSJack F Vogel 		data |= (0xB << 8);
29027d9119bdSJack F Vogel 		ret_val = e1000_write_kmrn_reg_generic(hw,
29037d9119bdSJack F Vogel 						E1000_KMRNCTRLSTA_HD_CTRL,
29047d9119bdSJack F Vogel 						data);
29057d9119bdSJack F Vogel 		if (ret_val)
29066ab6bfe3SJack F Vogel 			return ret_val;
29077d9119bdSJack F Vogel 
29087d9119bdSJack F Vogel 		/* Write PHY register values back to h/w defaults */
29097d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
29107d9119bdSJack F Vogel 		data &= ~(0x7F << 5);
29117d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
29127d9119bdSJack F Vogel 		if (ret_val)
29136ab6bfe3SJack F Vogel 			return ret_val;
29147d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
29157d9119bdSJack F Vogel 		data |= (1 << 13);
29167d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
29177d9119bdSJack F Vogel 		if (ret_val)
29186ab6bfe3SJack F Vogel 			return ret_val;
29197d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
29207d9119bdSJack F Vogel 		data &= ~(0x3FF << 2);
29217d9119bdSJack F Vogel 		data |= (0x8 << 2);
29227d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
29237d9119bdSJack F Vogel 		if (ret_val)
29246ab6bfe3SJack F Vogel 			return ret_val;
29257d9119bdSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
29267d9119bdSJack F Vogel 		if (ret_val)
29276ab6bfe3SJack F Vogel 			return ret_val;
29287d9119bdSJack F Vogel 		hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
29294dab5c37SJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
29304dab5c37SJack F Vogel 						~(1 << 10));
29317d9119bdSJack F Vogel 		if (ret_val)
29326ab6bfe3SJack F Vogel 			return ret_val;
29337d9119bdSJack F Vogel 	}
29347d9119bdSJack F Vogel 
29357d9119bdSJack F Vogel 	/* re-enable Rx path after enabling/disabling workaround */
29366ab6bfe3SJack F Vogel 	return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
29374dab5c37SJack F Vogel 				     ~(1 << 14));
29387d9119bdSJack F Vogel }
29397d9119bdSJack F Vogel 
29407d9119bdSJack F Vogel /**
29417d9119bdSJack F Vogel  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
29427d9119bdSJack F Vogel  *  done after every PHY reset.
29437d9119bdSJack F Vogel  **/
29447d9119bdSJack F Vogel static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
29457d9119bdSJack F Vogel {
29467d9119bdSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
29477d9119bdSJack F Vogel 
29487d9119bdSJack F Vogel 	DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
29497d9119bdSJack F Vogel 
29507d9119bdSJack F Vogel 	if (hw->mac.type != e1000_pch2lan)
29516ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
29527d9119bdSJack F Vogel 
29537d9119bdSJack F Vogel 	/* Set MDIO slow mode before any other MDIO access */
29547d9119bdSJack F Vogel 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
29556ab6bfe3SJack F Vogel 	if (ret_val)
29566ab6bfe3SJack F Vogel 		return ret_val;
29577d9119bdSJack F Vogel 
29584dab5c37SJack F Vogel 	ret_val = hw->phy.ops.acquire(hw);
29594dab5c37SJack F Vogel 	if (ret_val)
29606ab6bfe3SJack F Vogel 		return ret_val;
29614dab5c37SJack F Vogel 	/* set MSE higher to enable link to stay up when noise is high */
29626ab6bfe3SJack F Vogel 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
29634dab5c37SJack F Vogel 	if (ret_val)
29644dab5c37SJack F Vogel 		goto release;
29654dab5c37SJack F Vogel 	/* drop link after 5 times MSE threshold was reached */
29666ab6bfe3SJack F Vogel 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
29674dab5c37SJack F Vogel release:
29684dab5c37SJack F Vogel 	hw->phy.ops.release(hw);
29694dab5c37SJack F Vogel 
29707d9119bdSJack F Vogel 	return ret_val;
29717d9119bdSJack F Vogel }
29727d9119bdSJack F Vogel 
29737d9119bdSJack F Vogel /**
29747d9119bdSJack F Vogel  *  e1000_k1_gig_workaround_lv - K1 Si workaround
29757d9119bdSJack F Vogel  *  @hw:   pointer to the HW structure
29767d9119bdSJack F Vogel  *
29778cc64f1eSJack F Vogel  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
29788cc64f1eSJack F Vogel  *  Disable K1 for 1000 and 100 speeds
29797d9119bdSJack F Vogel  **/
29807d9119bdSJack F Vogel static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
29817d9119bdSJack F Vogel {
29827d9119bdSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
29837d9119bdSJack F Vogel 	u16 status_reg = 0;
29847d9119bdSJack F Vogel 
29857d9119bdSJack F Vogel 	DEBUGFUNC("e1000_k1_workaround_lv");
29867d9119bdSJack F Vogel 
29877d9119bdSJack F Vogel 	if (hw->mac.type != e1000_pch2lan)
29886ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
29897d9119bdSJack F Vogel 
29908cc64f1eSJack F Vogel 	/* Set K1 beacon duration based on 10Mbs speed */
29917d9119bdSJack F Vogel 	ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
29927d9119bdSJack F Vogel 	if (ret_val)
29936ab6bfe3SJack F Vogel 		return ret_val;
29947d9119bdSJack F Vogel 
29957d9119bdSJack F Vogel 	if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
29967d9119bdSJack F Vogel 	    == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
29978cc64f1eSJack F Vogel 		if (status_reg &
29988cc64f1eSJack F Vogel 		    (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
29996ab6bfe3SJack F Vogel 			u16 pm_phy_reg;
30006ab6bfe3SJack F Vogel 
30018cc64f1eSJack F Vogel 			/* LV 1G/100 Packet drop issue wa  */
30026ab6bfe3SJack F Vogel 			ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
30036ab6bfe3SJack F Vogel 						       &pm_phy_reg);
30046ab6bfe3SJack F Vogel 			if (ret_val)
30056ab6bfe3SJack F Vogel 				return ret_val;
30068cc64f1eSJack F Vogel 			pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
30076ab6bfe3SJack F Vogel 			ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
30086ab6bfe3SJack F Vogel 							pm_phy_reg);
30096ab6bfe3SJack F Vogel 			if (ret_val)
30106ab6bfe3SJack F Vogel 				return ret_val;
30114dab5c37SJack F Vogel 		} else {
30128cc64f1eSJack F Vogel 			u32 mac_reg;
30138cc64f1eSJack F Vogel 			mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
30148cc64f1eSJack F Vogel 			mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
30154dab5c37SJack F Vogel 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
30167d9119bdSJack F Vogel 			E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
30178cc64f1eSJack F Vogel 		}
30187d9119bdSJack F Vogel 	}
30197d9119bdSJack F Vogel 
30207d9119bdSJack F Vogel 	return ret_val;
30217d9119bdSJack F Vogel }
30227d9119bdSJack F Vogel 
30237d9119bdSJack F Vogel /**
30247d9119bdSJack F Vogel  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
30257d9119bdSJack F Vogel  *  @hw:   pointer to the HW structure
3026730d3130SJack F Vogel  *  @gate: boolean set to TRUE to gate, FALSE to ungate
30277d9119bdSJack F Vogel  *
30287d9119bdSJack F Vogel  *  Gate/ungate the automatic PHY configuration via hardware; perform
30297d9119bdSJack F Vogel  *  the configuration via software instead.
30307d9119bdSJack F Vogel  **/
30317d9119bdSJack F Vogel static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
30327d9119bdSJack F Vogel {
30337d9119bdSJack F Vogel 	u32 extcnf_ctrl;
30347d9119bdSJack F Vogel 
30357d9119bdSJack F Vogel 	DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
30367d9119bdSJack F Vogel 
30376ab6bfe3SJack F Vogel 	if (hw->mac.type < e1000_pch2lan)
30387d9119bdSJack F Vogel 		return;
30397d9119bdSJack F Vogel 
30407d9119bdSJack F Vogel 	extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
30417d9119bdSJack F Vogel 
30427d9119bdSJack F Vogel 	if (gate)
30437d9119bdSJack F Vogel 		extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
30447d9119bdSJack F Vogel 	else
30457d9119bdSJack F Vogel 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
30467d9119bdSJack F Vogel 
30477d9119bdSJack F Vogel 	E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
30487d9119bdSJack F Vogel }
30497d9119bdSJack F Vogel 
30507d9119bdSJack F Vogel /**
30519d81738fSJack F Vogel  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
30528cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
30538cfa0ad2SJack F Vogel  *
30549d81738fSJack F Vogel  *  Check the appropriate indication the MAC has finished configuring the
30559d81738fSJack F Vogel  *  PHY after a software reset.
30568cfa0ad2SJack F Vogel  **/
30579d81738fSJack F Vogel static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
30588cfa0ad2SJack F Vogel {
30599d81738fSJack F Vogel 	u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
30608cfa0ad2SJack F Vogel 
30619d81738fSJack F Vogel 	DEBUGFUNC("e1000_lan_init_done_ich8lan");
30628cfa0ad2SJack F Vogel 
30639d81738fSJack F Vogel 	/* Wait for basic configuration completes before proceeding */
30649d81738fSJack F Vogel 	do {
30659d81738fSJack F Vogel 		data = E1000_READ_REG(hw, E1000_STATUS);
30669d81738fSJack F Vogel 		data &= E1000_STATUS_LAN_INIT_DONE;
30679d81738fSJack F Vogel 		usec_delay(100);
30689d81738fSJack F Vogel 	} while ((!data) && --loop);
30698cfa0ad2SJack F Vogel 
30706ab6bfe3SJack F Vogel 	/* If basic configuration is incomplete before the above loop
30719d81738fSJack F Vogel 	 * count reaches 0, loading the configuration from NVM will
30729d81738fSJack F Vogel 	 * leave the PHY in a bad state possibly resulting in no link.
30739d81738fSJack F Vogel 	 */
30749d81738fSJack F Vogel 	if (loop == 0)
30759d81738fSJack F Vogel 		DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
30768cfa0ad2SJack F Vogel 
30779d81738fSJack F Vogel 	/* Clear the Init Done bit for the next init event */
30789d81738fSJack F Vogel 	data = E1000_READ_REG(hw, E1000_STATUS);
30799d81738fSJack F Vogel 	data &= ~E1000_STATUS_LAN_INIT_DONE;
30809d81738fSJack F Vogel 	E1000_WRITE_REG(hw, E1000_STATUS, data);
30818cfa0ad2SJack F Vogel }
30828cfa0ad2SJack F Vogel 
30838cfa0ad2SJack F Vogel /**
30847d9119bdSJack F Vogel  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
30857d9119bdSJack F Vogel  *  @hw: pointer to the HW structure
30867d9119bdSJack F Vogel  **/
30877d9119bdSJack F Vogel static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
30887d9119bdSJack F Vogel {
30897d9119bdSJack F Vogel 	s32 ret_val = E1000_SUCCESS;
30907d9119bdSJack F Vogel 	u16 reg;
30917d9119bdSJack F Vogel 
30927d9119bdSJack F Vogel 	DEBUGFUNC("e1000_post_phy_reset_ich8lan");
30937d9119bdSJack F Vogel 
30947d9119bdSJack F Vogel 	if (hw->phy.ops.check_reset_block(hw))
30956ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
30967d9119bdSJack F Vogel 
30977d9119bdSJack F Vogel 	/* Allow time for h/w to get to quiescent state after reset */
30987d9119bdSJack F Vogel 	msec_delay(10);
30997d9119bdSJack F Vogel 
31007d9119bdSJack F Vogel 	/* Perform any necessary post-reset workarounds */
31017d9119bdSJack F Vogel 	switch (hw->mac.type) {
31027d9119bdSJack F Vogel 	case e1000_pchlan:
31037d9119bdSJack F Vogel 		ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
31047d9119bdSJack F Vogel 		if (ret_val)
31056ab6bfe3SJack F Vogel 			return ret_val;
31067d9119bdSJack F Vogel 		break;
31077d9119bdSJack F Vogel 	case e1000_pch2lan:
31087d9119bdSJack F Vogel 		ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
31097d9119bdSJack F Vogel 		if (ret_val)
31106ab6bfe3SJack F Vogel 			return ret_val;
31117d9119bdSJack F Vogel 		break;
31127d9119bdSJack F Vogel 	default:
31137d9119bdSJack F Vogel 		break;
31147d9119bdSJack F Vogel 	}
31157d9119bdSJack F Vogel 
31164dab5c37SJack F Vogel 	/* Clear the host wakeup bit after lcd reset */
31174dab5c37SJack F Vogel 	if (hw->mac.type >= e1000_pchlan) {
31184dab5c37SJack F Vogel 		hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
31194dab5c37SJack F Vogel 		reg &= ~BM_WUC_HOST_WU_BIT;
31204dab5c37SJack F Vogel 		hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
31217d9119bdSJack F Vogel 	}
31227d9119bdSJack F Vogel 
31237d9119bdSJack F Vogel 	/* Configure the LCD with the extended configuration region in NVM */
31247d9119bdSJack F Vogel 	ret_val = e1000_sw_lcd_config_ich8lan(hw);
31257d9119bdSJack F Vogel 	if (ret_val)
31266ab6bfe3SJack F Vogel 		return ret_val;
31277d9119bdSJack F Vogel 
31287d9119bdSJack F Vogel 	/* Configure the LCD with the OEM bits in NVM */
31297d9119bdSJack F Vogel 	ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
31307d9119bdSJack F Vogel 
3131730d3130SJack F Vogel 	if (hw->mac.type == e1000_pch2lan) {
31327d9119bdSJack F Vogel 		/* Ungate automatic PHY configuration on non-managed 82579 */
3133730d3130SJack F Vogel 		if (!(E1000_READ_REG(hw, E1000_FWSM) &
3134730d3130SJack F Vogel 		    E1000_ICH_FWSM_FW_VALID)) {
31357d9119bdSJack F Vogel 			msec_delay(10);
31367d9119bdSJack F Vogel 			e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
31377d9119bdSJack F Vogel 		}
31387d9119bdSJack F Vogel 
3139730d3130SJack F Vogel 		/* Set EEE LPI Update Timer to 200usec */
3140730d3130SJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
3141730d3130SJack F Vogel 		if (ret_val)
31426ab6bfe3SJack F Vogel 			return ret_val;
31436ab6bfe3SJack F Vogel 		ret_val = e1000_write_emi_reg_locked(hw,
31446ab6bfe3SJack F Vogel 						     I82579_LPI_UPDATE_TIMER,
3145730d3130SJack F Vogel 						     0x1387);
3146730d3130SJack F Vogel 		hw->phy.ops.release(hw);
3147730d3130SJack F Vogel 	}
3148730d3130SJack F Vogel 
31497d9119bdSJack F Vogel 	return ret_val;
31507d9119bdSJack F Vogel }
31517d9119bdSJack F Vogel 
31527d9119bdSJack F Vogel /**
31538cfa0ad2SJack F Vogel  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
31548cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
31558cfa0ad2SJack F Vogel  *
31568cfa0ad2SJack F Vogel  *  Resets the PHY
31578cfa0ad2SJack F Vogel  *  This is a function pointer entry point called by drivers
31588cfa0ad2SJack F Vogel  *  or other shared routines.
31598cfa0ad2SJack F Vogel  **/
31608cfa0ad2SJack F Vogel static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
31618cfa0ad2SJack F Vogel {
31624edd8523SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
31638cfa0ad2SJack F Vogel 
31648cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
31658cfa0ad2SJack F Vogel 
31667d9119bdSJack F Vogel 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
31677d9119bdSJack F Vogel 	if ((hw->mac.type == e1000_pch2lan) &&
31687d9119bdSJack F Vogel 	    !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
31697d9119bdSJack F Vogel 		e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
31707d9119bdSJack F Vogel 
31718cfa0ad2SJack F Vogel 	ret_val = e1000_phy_hw_reset_generic(hw);
31728cfa0ad2SJack F Vogel 	if (ret_val)
31738cfa0ad2SJack F Vogel 		return ret_val;
31746ab6bfe3SJack F Vogel 
31756ab6bfe3SJack F Vogel 	return e1000_post_phy_reset_ich8lan(hw);
31768cfa0ad2SJack F Vogel }
31778cfa0ad2SJack F Vogel 
31788cfa0ad2SJack F Vogel /**
31794edd8523SJack F Vogel  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
31808cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
31814edd8523SJack F Vogel  *  @active: TRUE to enable LPLU, FALSE to disable
31828cfa0ad2SJack F Vogel  *
31834edd8523SJack F Vogel  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
31844edd8523SJack F Vogel  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
31854edd8523SJack F Vogel  *  the phy speed. This function will manually set the LPLU bit and restart
31864edd8523SJack F Vogel  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
31874edd8523SJack F Vogel  *  since it configures the same bit.
31888cfa0ad2SJack F Vogel  **/
31894edd8523SJack F Vogel static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
31908cfa0ad2SJack F Vogel {
31916ab6bfe3SJack F Vogel 	s32 ret_val;
31924edd8523SJack F Vogel 	u16 oem_reg;
31938cfa0ad2SJack F Vogel 
31944edd8523SJack F Vogel 	DEBUGFUNC("e1000_set_lplu_state_pchlan");
31954edd8523SJack F Vogel 	ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
31968cfa0ad2SJack F Vogel 	if (ret_val)
31976ab6bfe3SJack F Vogel 		return ret_val;
31988cfa0ad2SJack F Vogel 
31994edd8523SJack F Vogel 	if (active)
32004edd8523SJack F Vogel 		oem_reg |= HV_OEM_BITS_LPLU;
32014edd8523SJack F Vogel 	else
32024edd8523SJack F Vogel 		oem_reg &= ~HV_OEM_BITS_LPLU;
32038cfa0ad2SJack F Vogel 
32044dab5c37SJack F Vogel 	if (!hw->phy.ops.check_reset_block(hw))
32054edd8523SJack F Vogel 		oem_reg |= HV_OEM_BITS_RESTART_AN;
32064dab5c37SJack F Vogel 
32076ab6bfe3SJack F Vogel 	return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
32088cfa0ad2SJack F Vogel }
32098cfa0ad2SJack F Vogel 
32108cfa0ad2SJack F Vogel /**
32118cfa0ad2SJack F Vogel  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
32128cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
32138cfa0ad2SJack F Vogel  *  @active: TRUE to enable LPLU, FALSE to disable
32148cfa0ad2SJack F Vogel  *
32158cfa0ad2SJack F Vogel  *  Sets the LPLU D0 state according to the active flag.  When
32168cfa0ad2SJack F Vogel  *  activating LPLU this function also disables smart speed
32178cfa0ad2SJack F Vogel  *  and vice versa.  LPLU will not be activated unless the
32188cfa0ad2SJack F Vogel  *  device autonegotiation advertisement meets standards of
32198cfa0ad2SJack F Vogel  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
32208cfa0ad2SJack F Vogel  *  This is a function pointer entry point only called by
32218cfa0ad2SJack F Vogel  *  PHY setup routines.
32228cfa0ad2SJack F Vogel  **/
3223daf9197cSJack F Vogel static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
32248cfa0ad2SJack F Vogel {
32258cfa0ad2SJack F Vogel 	struct e1000_phy_info *phy = &hw->phy;
32268cfa0ad2SJack F Vogel 	u32 phy_ctrl;
32278cfa0ad2SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
32288cfa0ad2SJack F Vogel 	u16 data;
32298cfa0ad2SJack F Vogel 
32308cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
32318cfa0ad2SJack F Vogel 
32328cfa0ad2SJack F Vogel 	if (phy->type == e1000_phy_ife)
32336ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
32348cfa0ad2SJack F Vogel 
32358cfa0ad2SJack F Vogel 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
32368cfa0ad2SJack F Vogel 
32378cfa0ad2SJack F Vogel 	if (active) {
32388cfa0ad2SJack F Vogel 		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
32398cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
32408cfa0ad2SJack F Vogel 
32419d81738fSJack F Vogel 		if (phy->type != e1000_phy_igp_3)
32426ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
32439d81738fSJack F Vogel 
32446ab6bfe3SJack F Vogel 		/* Call gig speed drop workaround on LPLU before accessing
32458cfa0ad2SJack F Vogel 		 * any PHY registers
32468cfa0ad2SJack F Vogel 		 */
32479d81738fSJack F Vogel 		if (hw->mac.type == e1000_ich8lan)
32488cfa0ad2SJack F Vogel 			e1000_gig_downshift_workaround_ich8lan(hw);
32498cfa0ad2SJack F Vogel 
32508cfa0ad2SJack F Vogel 		/* When LPLU is enabled, we should disable SmartSpeed */
32518cfa0ad2SJack F Vogel 		ret_val = phy->ops.read_reg(hw,
32528cfa0ad2SJack F Vogel 					    IGP01E1000_PHY_PORT_CONFIG,
32538cfa0ad2SJack F Vogel 					    &data);
32546ab6bfe3SJack F Vogel 		if (ret_val)
32556ab6bfe3SJack F Vogel 			return ret_val;
32568cfa0ad2SJack F Vogel 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
32578cfa0ad2SJack F Vogel 		ret_val = phy->ops.write_reg(hw,
32588cfa0ad2SJack F Vogel 					     IGP01E1000_PHY_PORT_CONFIG,
32598cfa0ad2SJack F Vogel 					     data);
32608cfa0ad2SJack F Vogel 		if (ret_val)
32616ab6bfe3SJack F Vogel 			return ret_val;
32628cfa0ad2SJack F Vogel 	} else {
32638cfa0ad2SJack F Vogel 		phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
32648cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
32658cfa0ad2SJack F Vogel 
32669d81738fSJack F Vogel 		if (phy->type != e1000_phy_igp_3)
32676ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
32689d81738fSJack F Vogel 
32696ab6bfe3SJack F Vogel 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
32708cfa0ad2SJack F Vogel 		 * during Dx states where the power conservation is most
32718cfa0ad2SJack F Vogel 		 * important.  During driver activity we should enable
32728cfa0ad2SJack F Vogel 		 * SmartSpeed, so performance is maintained.
32738cfa0ad2SJack F Vogel 		 */
32748cfa0ad2SJack F Vogel 		if (phy->smart_speed == e1000_smart_speed_on) {
32758cfa0ad2SJack F Vogel 			ret_val = phy->ops.read_reg(hw,
32768cfa0ad2SJack F Vogel 						    IGP01E1000_PHY_PORT_CONFIG,
32778cfa0ad2SJack F Vogel 						    &data);
32788cfa0ad2SJack F Vogel 			if (ret_val)
32796ab6bfe3SJack F Vogel 				return ret_val;
32808cfa0ad2SJack F Vogel 
32818cfa0ad2SJack F Vogel 			data |= IGP01E1000_PSCFR_SMART_SPEED;
32828cfa0ad2SJack F Vogel 			ret_val = phy->ops.write_reg(hw,
32838cfa0ad2SJack F Vogel 						     IGP01E1000_PHY_PORT_CONFIG,
32848cfa0ad2SJack F Vogel 						     data);
32858cfa0ad2SJack F Vogel 			if (ret_val)
32866ab6bfe3SJack F Vogel 				return ret_val;
32878cfa0ad2SJack F Vogel 		} else if (phy->smart_speed == e1000_smart_speed_off) {
32888cfa0ad2SJack F Vogel 			ret_val = phy->ops.read_reg(hw,
32898cfa0ad2SJack F Vogel 						    IGP01E1000_PHY_PORT_CONFIG,
32908cfa0ad2SJack F Vogel 						    &data);
32918cfa0ad2SJack F Vogel 			if (ret_val)
32926ab6bfe3SJack F Vogel 				return ret_val;
32938cfa0ad2SJack F Vogel 
32948cfa0ad2SJack F Vogel 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
32958cfa0ad2SJack F Vogel 			ret_val = phy->ops.write_reg(hw,
32968cfa0ad2SJack F Vogel 						     IGP01E1000_PHY_PORT_CONFIG,
32978cfa0ad2SJack F Vogel 						     data);
32988cfa0ad2SJack F Vogel 			if (ret_val)
32996ab6bfe3SJack F Vogel 				return ret_val;
33008cfa0ad2SJack F Vogel 		}
33018cfa0ad2SJack F Vogel 	}
33028cfa0ad2SJack F Vogel 
33036ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
33048cfa0ad2SJack F Vogel }
33058cfa0ad2SJack F Vogel 
33068cfa0ad2SJack F Vogel /**
33078cfa0ad2SJack F Vogel  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
33088cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
33098cfa0ad2SJack F Vogel  *  @active: TRUE to enable LPLU, FALSE to disable
33108cfa0ad2SJack F Vogel  *
33118cfa0ad2SJack F Vogel  *  Sets the LPLU D3 state according to the active flag.  When
33128cfa0ad2SJack F Vogel  *  activating LPLU this function also disables smart speed
33138cfa0ad2SJack F Vogel  *  and vice versa.  LPLU will not be activated unless the
33148cfa0ad2SJack F Vogel  *  device autonegotiation advertisement meets standards of
33158cfa0ad2SJack F Vogel  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
33168cfa0ad2SJack F Vogel  *  This is a function pointer entry point only called by
33178cfa0ad2SJack F Vogel  *  PHY setup routines.
33188cfa0ad2SJack F Vogel  **/
3319daf9197cSJack F Vogel static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
33208cfa0ad2SJack F Vogel {
33218cfa0ad2SJack F Vogel 	struct e1000_phy_info *phy = &hw->phy;
33228cfa0ad2SJack F Vogel 	u32 phy_ctrl;
33238cfa0ad2SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
33248cfa0ad2SJack F Vogel 	u16 data;
33258cfa0ad2SJack F Vogel 
33268cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
33278cfa0ad2SJack F Vogel 
33288cfa0ad2SJack F Vogel 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
33298cfa0ad2SJack F Vogel 
33308cfa0ad2SJack F Vogel 	if (!active) {
33318cfa0ad2SJack F Vogel 		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
33328cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
33339d81738fSJack F Vogel 
33349d81738fSJack F Vogel 		if (phy->type != e1000_phy_igp_3)
33356ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
33369d81738fSJack F Vogel 
33376ab6bfe3SJack F Vogel 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
33388cfa0ad2SJack F Vogel 		 * during Dx states where the power conservation is most
33398cfa0ad2SJack F Vogel 		 * important.  During driver activity we should enable
33408cfa0ad2SJack F Vogel 		 * SmartSpeed, so performance is maintained.
33418cfa0ad2SJack F Vogel 		 */
33428cfa0ad2SJack F Vogel 		if (phy->smart_speed == e1000_smart_speed_on) {
33438cfa0ad2SJack F Vogel 			ret_val = phy->ops.read_reg(hw,
33448cfa0ad2SJack F Vogel 						    IGP01E1000_PHY_PORT_CONFIG,
33458cfa0ad2SJack F Vogel 						    &data);
33468cfa0ad2SJack F Vogel 			if (ret_val)
33476ab6bfe3SJack F Vogel 				return ret_val;
33488cfa0ad2SJack F Vogel 
33498cfa0ad2SJack F Vogel 			data |= IGP01E1000_PSCFR_SMART_SPEED;
33508cfa0ad2SJack F Vogel 			ret_val = phy->ops.write_reg(hw,
33518cfa0ad2SJack F Vogel 						     IGP01E1000_PHY_PORT_CONFIG,
33528cfa0ad2SJack F Vogel 						     data);
33538cfa0ad2SJack F Vogel 			if (ret_val)
33546ab6bfe3SJack F Vogel 				return ret_val;
33558cfa0ad2SJack F Vogel 		} else if (phy->smart_speed == e1000_smart_speed_off) {
33568cfa0ad2SJack F Vogel 			ret_val = phy->ops.read_reg(hw,
33578cfa0ad2SJack F Vogel 						    IGP01E1000_PHY_PORT_CONFIG,
33588cfa0ad2SJack F Vogel 						    &data);
33598cfa0ad2SJack F Vogel 			if (ret_val)
33606ab6bfe3SJack F Vogel 				return ret_val;
33618cfa0ad2SJack F Vogel 
33628cfa0ad2SJack F Vogel 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
33638cfa0ad2SJack F Vogel 			ret_val = phy->ops.write_reg(hw,
33648cfa0ad2SJack F Vogel 						     IGP01E1000_PHY_PORT_CONFIG,
33658cfa0ad2SJack F Vogel 						     data);
33668cfa0ad2SJack F Vogel 			if (ret_val)
33676ab6bfe3SJack F Vogel 				return ret_val;
33688cfa0ad2SJack F Vogel 		}
33698cfa0ad2SJack F Vogel 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
33708cfa0ad2SJack F Vogel 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
33718cfa0ad2SJack F Vogel 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
33728cfa0ad2SJack F Vogel 		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
33738cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
33748cfa0ad2SJack F Vogel 
33759d81738fSJack F Vogel 		if (phy->type != e1000_phy_igp_3)
33766ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
33779d81738fSJack F Vogel 
33786ab6bfe3SJack F Vogel 		/* Call gig speed drop workaround on LPLU before accessing
33798cfa0ad2SJack F Vogel 		 * any PHY registers
33808cfa0ad2SJack F Vogel 		 */
33819d81738fSJack F Vogel 		if (hw->mac.type == e1000_ich8lan)
33828cfa0ad2SJack F Vogel 			e1000_gig_downshift_workaround_ich8lan(hw);
33838cfa0ad2SJack F Vogel 
33848cfa0ad2SJack F Vogel 		/* When LPLU is enabled, we should disable SmartSpeed */
33858cfa0ad2SJack F Vogel 		ret_val = phy->ops.read_reg(hw,
33868cfa0ad2SJack F Vogel 					    IGP01E1000_PHY_PORT_CONFIG,
33878cfa0ad2SJack F Vogel 					    &data);
33888cfa0ad2SJack F Vogel 		if (ret_val)
33896ab6bfe3SJack F Vogel 			return ret_val;
33908cfa0ad2SJack F Vogel 
33918cfa0ad2SJack F Vogel 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
33928cfa0ad2SJack F Vogel 		ret_val = phy->ops.write_reg(hw,
33938cfa0ad2SJack F Vogel 					     IGP01E1000_PHY_PORT_CONFIG,
33948cfa0ad2SJack F Vogel 					     data);
33958cfa0ad2SJack F Vogel 	}
33968cfa0ad2SJack F Vogel 
33978cfa0ad2SJack F Vogel 	return ret_val;
33988cfa0ad2SJack F Vogel }
33998cfa0ad2SJack F Vogel 
34008cfa0ad2SJack F Vogel /**
34018cfa0ad2SJack F Vogel  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
34028cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
34038cfa0ad2SJack F Vogel  *  @bank:  pointer to the variable that returns the active bank
34048cfa0ad2SJack F Vogel  *
34058cfa0ad2SJack F Vogel  *  Reads signature byte from the NVM using the flash access registers.
3406d035aa2dSJack F Vogel  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
34078cfa0ad2SJack F Vogel  **/
34088cfa0ad2SJack F Vogel static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
34098cfa0ad2SJack F Vogel {
3410d035aa2dSJack F Vogel 	u32 eecd;
34118cfa0ad2SJack F Vogel 	struct e1000_nvm_info *nvm = &hw->nvm;
34128cfa0ad2SJack F Vogel 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
34138cfa0ad2SJack F Vogel 	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3414c80429ceSEric Joyner 	u32 nvm_dword = 0;
3415d035aa2dSJack F Vogel 	u8 sig_byte = 0;
34166ab6bfe3SJack F Vogel 	s32 ret_val;
34178cfa0ad2SJack F Vogel 
34187d9119bdSJack F Vogel 	DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
34197d9119bdSJack F Vogel 
3420d035aa2dSJack F Vogel 	switch (hw->mac.type) {
3421c80429ceSEric Joyner 	case e1000_pch_spt:
3422*6fe4c0a0SSean Bruno 	case e1000_pch_cnp:
3423c80429ceSEric Joyner 		bank1_offset = nvm->flash_bank_size;
3424c80429ceSEric Joyner 		act_offset = E1000_ICH_NVM_SIG_WORD;
3425c80429ceSEric Joyner 
3426c80429ceSEric Joyner 		/* set bank to 0 in case flash read fails */
3427c80429ceSEric Joyner 		*bank = 0;
3428c80429ceSEric Joyner 
3429c80429ceSEric Joyner 		/* Check bank 0 */
3430c80429ceSEric Joyner 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3431c80429ceSEric Joyner 							 &nvm_dword);
3432c80429ceSEric Joyner 		if (ret_val)
3433c80429ceSEric Joyner 			return ret_val;
3434c80429ceSEric Joyner 		sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3435c80429ceSEric Joyner 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3436c80429ceSEric Joyner 		    E1000_ICH_NVM_SIG_VALUE) {
3437c80429ceSEric Joyner 			*bank = 0;
3438c80429ceSEric Joyner 			return E1000_SUCCESS;
3439c80429ceSEric Joyner 		}
3440c80429ceSEric Joyner 
3441c80429ceSEric Joyner 		/* Check bank 1 */
3442c80429ceSEric Joyner 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3443c80429ceSEric Joyner 							 bank1_offset,
3444c80429ceSEric Joyner 							 &nvm_dword);
3445c80429ceSEric Joyner 		if (ret_val)
3446c80429ceSEric Joyner 			return ret_val;
3447c80429ceSEric Joyner 		sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3448c80429ceSEric Joyner 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3449c80429ceSEric Joyner 		    E1000_ICH_NVM_SIG_VALUE) {
3450c80429ceSEric Joyner 			*bank = 1;
3451c80429ceSEric Joyner 			return E1000_SUCCESS;
3452c80429ceSEric Joyner 		}
3453c80429ceSEric Joyner 
3454c80429ceSEric Joyner 		DEBUGOUT("ERROR: No valid NVM bank present\n");
3455c80429ceSEric Joyner 		return -E1000_ERR_NVM;
3456d035aa2dSJack F Vogel 	case e1000_ich8lan:
3457d035aa2dSJack F Vogel 	case e1000_ich9lan:
3458d035aa2dSJack F Vogel 		eecd = E1000_READ_REG(hw, E1000_EECD);
3459d035aa2dSJack F Vogel 		if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3460d035aa2dSJack F Vogel 		    E1000_EECD_SEC1VAL_VALID_MASK) {
3461d035aa2dSJack F Vogel 			if (eecd & E1000_EECD_SEC1VAL)
34628cfa0ad2SJack F Vogel 				*bank = 1;
34638cfa0ad2SJack F Vogel 			else
34648cfa0ad2SJack F Vogel 				*bank = 0;
3465d035aa2dSJack F Vogel 
34666ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
3467d035aa2dSJack F Vogel 		}
34684dab5c37SJack F Vogel 		DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3469d035aa2dSJack F Vogel 		/* fall-thru */
3470d035aa2dSJack F Vogel 	default:
3471d035aa2dSJack F Vogel 		/* set bank to 0 in case flash read fails */
34728cfa0ad2SJack F Vogel 		*bank = 0;
34738cfa0ad2SJack F Vogel 
3474d035aa2dSJack F Vogel 		/* Check bank 0 */
3475d035aa2dSJack F Vogel 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3476d035aa2dSJack F Vogel 							&sig_byte);
3477d035aa2dSJack F Vogel 		if (ret_val)
34786ab6bfe3SJack F Vogel 			return ret_val;
3479d035aa2dSJack F Vogel 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3480d035aa2dSJack F Vogel 		    E1000_ICH_NVM_SIG_VALUE) {
3481d035aa2dSJack F Vogel 			*bank = 0;
34826ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
3483d035aa2dSJack F Vogel 		}
3484d035aa2dSJack F Vogel 
3485d035aa2dSJack F Vogel 		/* Check bank 1 */
3486d035aa2dSJack F Vogel 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3487d035aa2dSJack F Vogel 							bank1_offset,
3488d035aa2dSJack F Vogel 							&sig_byte);
3489d035aa2dSJack F Vogel 		if (ret_val)
34906ab6bfe3SJack F Vogel 			return ret_val;
3491d035aa2dSJack F Vogel 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3492d035aa2dSJack F Vogel 		    E1000_ICH_NVM_SIG_VALUE) {
34938cfa0ad2SJack F Vogel 			*bank = 1;
34946ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
34958cfa0ad2SJack F Vogel 		}
34968cfa0ad2SJack F Vogel 
3497d035aa2dSJack F Vogel 		DEBUGOUT("ERROR: No valid NVM bank present\n");
34986ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
3499d035aa2dSJack F Vogel 	}
35008cfa0ad2SJack F Vogel }
35018cfa0ad2SJack F Vogel 
35028cfa0ad2SJack F Vogel /**
3503c80429ceSEric Joyner  *  e1000_read_nvm_spt - NVM access for SPT
3504c80429ceSEric Joyner  *  @hw: pointer to the HW structure
3505c80429ceSEric Joyner  *  @offset: The offset (in bytes) of the word(s) to read.
3506c80429ceSEric Joyner  *  @words: Size of data to read in words.
3507c80429ceSEric Joyner  *  @data: pointer to the word(s) to read at offset.
3508c80429ceSEric Joyner  *
3509c80429ceSEric Joyner  *  Reads a word(s) from the NVM
3510c80429ceSEric Joyner  **/
3511c80429ceSEric Joyner static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3512c80429ceSEric Joyner 			      u16 *data)
3513c80429ceSEric Joyner {
3514c80429ceSEric Joyner 	struct e1000_nvm_info *nvm = &hw->nvm;
3515c80429ceSEric Joyner 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3516c80429ceSEric Joyner 	u32 act_offset;
3517c80429ceSEric Joyner 	s32 ret_val = E1000_SUCCESS;
3518c80429ceSEric Joyner 	u32 bank = 0;
3519c80429ceSEric Joyner 	u32 dword = 0;
3520c80429ceSEric Joyner 	u16 offset_to_read;
3521c80429ceSEric Joyner 	u16 i;
3522c80429ceSEric Joyner 
3523c80429ceSEric Joyner 	DEBUGFUNC("e1000_read_nvm_spt");
3524c80429ceSEric Joyner 
3525c80429ceSEric Joyner 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3526c80429ceSEric Joyner 	    (words == 0)) {
3527c80429ceSEric Joyner 		DEBUGOUT("nvm parameter(s) out of bounds\n");
3528c80429ceSEric Joyner 		ret_val = -E1000_ERR_NVM;
3529c80429ceSEric Joyner 		goto out;
3530c80429ceSEric Joyner 	}
3531c80429ceSEric Joyner 
3532c80429ceSEric Joyner 	nvm->ops.acquire(hw);
3533c80429ceSEric Joyner 
3534c80429ceSEric Joyner 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3535c80429ceSEric Joyner 	if (ret_val != E1000_SUCCESS) {
3536c80429ceSEric Joyner 		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3537c80429ceSEric Joyner 		bank = 0;
3538c80429ceSEric Joyner 	}
3539c80429ceSEric Joyner 
3540c80429ceSEric Joyner 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3541c80429ceSEric Joyner 	act_offset += offset;
3542c80429ceSEric Joyner 
3543c80429ceSEric Joyner 	ret_val = E1000_SUCCESS;
3544c80429ceSEric Joyner 
3545c80429ceSEric Joyner 	for (i = 0; i < words; i += 2) {
3546c80429ceSEric Joyner 		if (words - i == 1) {
3547c80429ceSEric Joyner 			if (dev_spec->shadow_ram[offset+i].modified) {
3548c80429ceSEric Joyner 				data[i] = dev_spec->shadow_ram[offset+i].value;
3549c80429ceSEric Joyner 			} else {
3550c80429ceSEric Joyner 				offset_to_read = act_offset + i -
3551c80429ceSEric Joyner 						 ((act_offset + i) % 2);
3552c80429ceSEric Joyner 				ret_val =
3553c80429ceSEric Joyner 				   e1000_read_flash_dword_ich8lan(hw,
3554c80429ceSEric Joyner 								 offset_to_read,
3555c80429ceSEric Joyner 								 &dword);
3556c80429ceSEric Joyner 				if (ret_val)
3557c80429ceSEric Joyner 					break;
3558c80429ceSEric Joyner 				if ((act_offset + i) % 2 == 0)
3559c80429ceSEric Joyner 					data[i] = (u16)(dword & 0xFFFF);
3560c80429ceSEric Joyner 				else
3561c80429ceSEric Joyner 					data[i] = (u16)((dword >> 16) & 0xFFFF);
3562c80429ceSEric Joyner 			}
3563c80429ceSEric Joyner 		} else {
3564c80429ceSEric Joyner 			offset_to_read = act_offset + i;
3565c80429ceSEric Joyner 			if (!(dev_spec->shadow_ram[offset+i].modified) ||
3566c80429ceSEric Joyner 			    !(dev_spec->shadow_ram[offset+i+1].modified)) {
3567c80429ceSEric Joyner 				ret_val =
3568c80429ceSEric Joyner 				   e1000_read_flash_dword_ich8lan(hw,
3569c80429ceSEric Joyner 								 offset_to_read,
3570c80429ceSEric Joyner 								 &dword);
3571c80429ceSEric Joyner 				if (ret_val)
3572c80429ceSEric Joyner 					break;
3573c80429ceSEric Joyner 			}
3574c80429ceSEric Joyner 			if (dev_spec->shadow_ram[offset+i].modified)
3575c80429ceSEric Joyner 				data[i] = dev_spec->shadow_ram[offset+i].value;
3576c80429ceSEric Joyner 			else
3577c80429ceSEric Joyner 				data[i] = (u16) (dword & 0xFFFF);
3578c80429ceSEric Joyner 			if (dev_spec->shadow_ram[offset+i].modified)
3579c80429ceSEric Joyner 				data[i+1] =
3580c80429ceSEric Joyner 				   dev_spec->shadow_ram[offset+i+1].value;
3581c80429ceSEric Joyner 			else
3582c80429ceSEric Joyner 				data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3583c80429ceSEric Joyner 		}
3584c80429ceSEric Joyner 	}
3585c80429ceSEric Joyner 
3586c80429ceSEric Joyner 	nvm->ops.release(hw);
3587c80429ceSEric Joyner 
3588c80429ceSEric Joyner out:
3589c80429ceSEric Joyner 	if (ret_val)
3590c80429ceSEric Joyner 		DEBUGOUT1("NVM read error: %d\n", ret_val);
3591c80429ceSEric Joyner 
3592c80429ceSEric Joyner 	return ret_val;
3593c80429ceSEric Joyner }
3594c80429ceSEric Joyner 
3595c80429ceSEric Joyner /**
35968cfa0ad2SJack F Vogel  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
35978cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
35988cfa0ad2SJack F Vogel  *  @offset: The offset (in bytes) of the word(s) to read.
35998cfa0ad2SJack F Vogel  *  @words: Size of data to read in words
36008cfa0ad2SJack F Vogel  *  @data: Pointer to the word(s) to read at offset.
36018cfa0ad2SJack F Vogel  *
36028cfa0ad2SJack F Vogel  *  Reads a word(s) from the NVM using the flash access registers.
36038cfa0ad2SJack F Vogel  **/
36048cfa0ad2SJack F Vogel static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
36058cfa0ad2SJack F Vogel 				  u16 *data)
36068cfa0ad2SJack F Vogel {
36078cfa0ad2SJack F Vogel 	struct e1000_nvm_info *nvm = &hw->nvm;
3608daf9197cSJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
36098cfa0ad2SJack F Vogel 	u32 act_offset;
36108cfa0ad2SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
36118cfa0ad2SJack F Vogel 	u32 bank = 0;
36128cfa0ad2SJack F Vogel 	u16 i, word;
36138cfa0ad2SJack F Vogel 
36148cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_read_nvm_ich8lan");
36158cfa0ad2SJack F Vogel 
36168cfa0ad2SJack F Vogel 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
36178cfa0ad2SJack F Vogel 	    (words == 0)) {
36188cfa0ad2SJack F Vogel 		DEBUGOUT("nvm parameter(s) out of bounds\n");
36198cfa0ad2SJack F Vogel 		ret_val = -E1000_ERR_NVM;
36208cfa0ad2SJack F Vogel 		goto out;
36218cfa0ad2SJack F Vogel 	}
36228cfa0ad2SJack F Vogel 
36234edd8523SJack F Vogel 	nvm->ops.acquire(hw);
36248cfa0ad2SJack F Vogel 
36258cfa0ad2SJack F Vogel 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
36264edd8523SJack F Vogel 	if (ret_val != E1000_SUCCESS) {
36274edd8523SJack F Vogel 		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
36284edd8523SJack F Vogel 		bank = 0;
36294edd8523SJack F Vogel 	}
36308cfa0ad2SJack F Vogel 
36318cfa0ad2SJack F Vogel 	act_offset = (bank) ? nvm->flash_bank_size : 0;
36328cfa0ad2SJack F Vogel 	act_offset += offset;
36338cfa0ad2SJack F Vogel 
36344edd8523SJack F Vogel 	ret_val = E1000_SUCCESS;
36358cfa0ad2SJack F Vogel 	for (i = 0; i < words; i++) {
36364dab5c37SJack F Vogel 		if (dev_spec->shadow_ram[offset+i].modified) {
36378cfa0ad2SJack F Vogel 			data[i] = dev_spec->shadow_ram[offset+i].value;
36388cfa0ad2SJack F Vogel 		} else {
36398cfa0ad2SJack F Vogel 			ret_val = e1000_read_flash_word_ich8lan(hw,
36408cfa0ad2SJack F Vogel 								act_offset + i,
36418cfa0ad2SJack F Vogel 								&word);
36428cfa0ad2SJack F Vogel 			if (ret_val)
36438cfa0ad2SJack F Vogel 				break;
36448cfa0ad2SJack F Vogel 			data[i] = word;
36458cfa0ad2SJack F Vogel 		}
36468cfa0ad2SJack F Vogel 	}
36478cfa0ad2SJack F Vogel 
36488cfa0ad2SJack F Vogel 	nvm->ops.release(hw);
36498cfa0ad2SJack F Vogel 
36508cfa0ad2SJack F Vogel out:
3651d035aa2dSJack F Vogel 	if (ret_val)
3652d035aa2dSJack F Vogel 		DEBUGOUT1("NVM read error: %d\n", ret_val);
3653d035aa2dSJack F Vogel 
36548cfa0ad2SJack F Vogel 	return ret_val;
36558cfa0ad2SJack F Vogel }
36568cfa0ad2SJack F Vogel 
36578cfa0ad2SJack F Vogel /**
36588cfa0ad2SJack F Vogel  *  e1000_flash_cycle_init_ich8lan - Initialize flash
36598cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
36608cfa0ad2SJack F Vogel  *
36618cfa0ad2SJack F Vogel  *  This function does initial flash setup so that a new read/write/erase cycle
36628cfa0ad2SJack F Vogel  *  can be started.
36638cfa0ad2SJack F Vogel  **/
36648cfa0ad2SJack F Vogel static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
36658cfa0ad2SJack F Vogel {
36668cfa0ad2SJack F Vogel 	union ich8_hws_flash_status hsfsts;
36678cfa0ad2SJack F Vogel 	s32 ret_val = -E1000_ERR_NVM;
36688cfa0ad2SJack F Vogel 
36698cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
36708cfa0ad2SJack F Vogel 
36718cfa0ad2SJack F Vogel 	hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
36728cfa0ad2SJack F Vogel 
36738cfa0ad2SJack F Vogel 	/* Check if the flash descriptor is valid */
36746ab6bfe3SJack F Vogel 	if (!hsfsts.hsf_status.fldesvalid) {
36754dab5c37SJack F Vogel 		DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
36766ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
36778cfa0ad2SJack F Vogel 	}
36788cfa0ad2SJack F Vogel 
36798cfa0ad2SJack F Vogel 	/* Clear FCERR and DAEL in hw status by writing 1 */
36808cfa0ad2SJack F Vogel 	hsfsts.hsf_status.flcerr = 1;
36818cfa0ad2SJack F Vogel 	hsfsts.hsf_status.dael = 1;
3682295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt)
3683c80429ceSEric Joyner 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3684c80429ceSEric Joyner 				      hsfsts.regval & 0xFFFF);
3685c80429ceSEric Joyner 	else
36868cfa0ad2SJack F Vogel 		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
36878cfa0ad2SJack F Vogel 
36886ab6bfe3SJack F Vogel 	/* Either we should have a hardware SPI cycle in progress
36898cfa0ad2SJack F Vogel 	 * bit to check against, in order to start a new cycle or
36908cfa0ad2SJack F Vogel 	 * FDONE bit should be changed in the hardware so that it
36918cfa0ad2SJack F Vogel 	 * is 1 after hardware reset, which can then be used as an
36928cfa0ad2SJack F Vogel 	 * indication whether a cycle is in progress or has been
36938cfa0ad2SJack F Vogel 	 * completed.
36948cfa0ad2SJack F Vogel 	 */
36958cfa0ad2SJack F Vogel 
36966ab6bfe3SJack F Vogel 	if (!hsfsts.hsf_status.flcinprog) {
36976ab6bfe3SJack F Vogel 		/* There is no cycle running at present,
36988cfa0ad2SJack F Vogel 		 * so we can start a cycle.
36998cfa0ad2SJack F Vogel 		 * Begin by setting Flash Cycle Done.
37008cfa0ad2SJack F Vogel 		 */
37018cfa0ad2SJack F Vogel 		hsfsts.hsf_status.flcdone = 1;
3702295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_spt)
3703c80429ceSEric Joyner 			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3704c80429ceSEric Joyner 					      hsfsts.regval & 0xFFFF);
3705c80429ceSEric Joyner 		else
3706c80429ceSEric Joyner 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3707c80429ceSEric Joyner 						hsfsts.regval);
37088cfa0ad2SJack F Vogel 		ret_val = E1000_SUCCESS;
37098cfa0ad2SJack F Vogel 	} else {
3710730d3130SJack F Vogel 		s32 i;
3711730d3130SJack F Vogel 
37126ab6bfe3SJack F Vogel 		/* Otherwise poll for sometime so the current
37138cfa0ad2SJack F Vogel 		 * cycle has a chance to end before giving up.
37148cfa0ad2SJack F Vogel 		 */
37158cfa0ad2SJack F Vogel 		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
37168cfa0ad2SJack F Vogel 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
37178cfa0ad2SJack F Vogel 							      ICH_FLASH_HSFSTS);
37186ab6bfe3SJack F Vogel 			if (!hsfsts.hsf_status.flcinprog) {
37198cfa0ad2SJack F Vogel 				ret_val = E1000_SUCCESS;
37208cfa0ad2SJack F Vogel 				break;
37218cfa0ad2SJack F Vogel 			}
37228cfa0ad2SJack F Vogel 			usec_delay(1);
37238cfa0ad2SJack F Vogel 		}
37248cfa0ad2SJack F Vogel 		if (ret_val == E1000_SUCCESS) {
37256ab6bfe3SJack F Vogel 			/* Successful in waiting for previous cycle to timeout,
37268cfa0ad2SJack F Vogel 			 * now set the Flash Cycle Done.
37278cfa0ad2SJack F Vogel 			 */
37288cfa0ad2SJack F Vogel 			hsfsts.hsf_status.flcdone = 1;
3729295df609SEric Joyner 			if (hw->mac.type >= e1000_pch_spt)
3730c80429ceSEric Joyner 				E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3731c80429ceSEric Joyner 						      hsfsts.regval & 0xFFFF);
3732c80429ceSEric Joyner 			else
3733daf9197cSJack F Vogel 				E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
37348cfa0ad2SJack F Vogel 							hsfsts.regval);
37358cfa0ad2SJack F Vogel 		} else {
37364dab5c37SJack F Vogel 			DEBUGOUT("Flash controller busy, cannot get access\n");
37378cfa0ad2SJack F Vogel 		}
37388cfa0ad2SJack F Vogel 	}
37398cfa0ad2SJack F Vogel 
37408cfa0ad2SJack F Vogel 	return ret_val;
37418cfa0ad2SJack F Vogel }
37428cfa0ad2SJack F Vogel 
37438cfa0ad2SJack F Vogel /**
37448cfa0ad2SJack F Vogel  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
37458cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
37468cfa0ad2SJack F Vogel  *  @timeout: maximum time to wait for completion
37478cfa0ad2SJack F Vogel  *
37488cfa0ad2SJack F Vogel  *  This function starts a flash cycle and waits for its completion.
37498cfa0ad2SJack F Vogel  **/
37508cfa0ad2SJack F Vogel static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
37518cfa0ad2SJack F Vogel {
37528cfa0ad2SJack F Vogel 	union ich8_hws_flash_ctrl hsflctl;
37538cfa0ad2SJack F Vogel 	union ich8_hws_flash_status hsfsts;
37548cfa0ad2SJack F Vogel 	u32 i = 0;
37558cfa0ad2SJack F Vogel 
37568cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_flash_cycle_ich8lan");
37578cfa0ad2SJack F Vogel 
37588cfa0ad2SJack F Vogel 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3759295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt)
3760c80429ceSEric Joyner 		hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3761c80429ceSEric Joyner 	else
37628cfa0ad2SJack F Vogel 		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
37638cfa0ad2SJack F Vogel 	hsflctl.hsf_ctrl.flcgo = 1;
37648cc64f1eSJack F Vogel 
3765295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt)
3766c80429ceSEric Joyner 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3767c80429ceSEric Joyner 				      hsflctl.regval << 16);
3768c80429ceSEric Joyner 	else
37698cfa0ad2SJack F Vogel 		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
37708cfa0ad2SJack F Vogel 
37718cfa0ad2SJack F Vogel 	/* wait till FDONE bit is set to 1 */
37728cfa0ad2SJack F Vogel 	do {
37738cfa0ad2SJack F Vogel 		hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
37746ab6bfe3SJack F Vogel 		if (hsfsts.hsf_status.flcdone)
37758cfa0ad2SJack F Vogel 			break;
37768cfa0ad2SJack F Vogel 		usec_delay(1);
37778cfa0ad2SJack F Vogel 	} while (i++ < timeout);
37788cfa0ad2SJack F Vogel 
37796ab6bfe3SJack F Vogel 	if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
37806ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
37818cfa0ad2SJack F Vogel 
37826ab6bfe3SJack F Vogel 	return -E1000_ERR_NVM;
37838cfa0ad2SJack F Vogel }
37848cfa0ad2SJack F Vogel 
37858cfa0ad2SJack F Vogel /**
3786c80429ceSEric Joyner  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3787c80429ceSEric Joyner  *  @hw: pointer to the HW structure
3788c80429ceSEric Joyner  *  @offset: offset to data location
3789c80429ceSEric Joyner  *  @data: pointer to the location for storing the data
3790c80429ceSEric Joyner  *
3791c80429ceSEric Joyner  *  Reads the flash dword at offset into data.  Offset is converted
3792c80429ceSEric Joyner  *  to bytes before read.
3793c80429ceSEric Joyner  **/
3794c80429ceSEric Joyner static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3795c80429ceSEric Joyner 					  u32 *data)
3796c80429ceSEric Joyner {
3797c80429ceSEric Joyner 	DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3798c80429ceSEric Joyner 
3799c80429ceSEric Joyner 	if (!data)
3800c80429ceSEric Joyner 		return -E1000_ERR_NVM;
3801c80429ceSEric Joyner 
3802c80429ceSEric Joyner 	/* Must convert word offset into bytes. */
3803c80429ceSEric Joyner 	offset <<= 1;
3804c80429ceSEric Joyner 
3805c80429ceSEric Joyner 	return e1000_read_flash_data32_ich8lan(hw, offset, data);
3806c80429ceSEric Joyner }
3807c80429ceSEric Joyner 
3808c80429ceSEric Joyner /**
38098cfa0ad2SJack F Vogel  *  e1000_read_flash_word_ich8lan - Read word from flash
38108cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
38118cfa0ad2SJack F Vogel  *  @offset: offset to data location
38128cfa0ad2SJack F Vogel  *  @data: pointer to the location for storing the data
38138cfa0ad2SJack F Vogel  *
38148cfa0ad2SJack F Vogel  *  Reads the flash word at offset into data.  Offset is converted
38158cfa0ad2SJack F Vogel  *  to bytes before read.
38168cfa0ad2SJack F Vogel  **/
38178cfa0ad2SJack F Vogel static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
38188cfa0ad2SJack F Vogel 					 u16 *data)
38198cfa0ad2SJack F Vogel {
38208cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_read_flash_word_ich8lan");
38218cfa0ad2SJack F Vogel 
38226ab6bfe3SJack F Vogel 	if (!data)
38236ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
38248cfa0ad2SJack F Vogel 
38258cfa0ad2SJack F Vogel 	/* Must convert offset into bytes. */
38268cfa0ad2SJack F Vogel 	offset <<= 1;
38278cfa0ad2SJack F Vogel 
38286ab6bfe3SJack F Vogel 	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
38298cfa0ad2SJack F Vogel }
38308cfa0ad2SJack F Vogel 
38318cfa0ad2SJack F Vogel /**
38328cfa0ad2SJack F Vogel  *  e1000_read_flash_byte_ich8lan - Read byte from flash
38338cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
38348cfa0ad2SJack F Vogel  *  @offset: The offset of the byte to read.
38358cfa0ad2SJack F Vogel  *  @data: Pointer to a byte to store the value read.
38368cfa0ad2SJack F Vogel  *
38378cfa0ad2SJack F Vogel  *  Reads a single byte from the NVM using the flash access registers.
38388cfa0ad2SJack F Vogel  **/
38398cfa0ad2SJack F Vogel static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
38408cfa0ad2SJack F Vogel 					 u8 *data)
38418cfa0ad2SJack F Vogel {
38426ab6bfe3SJack F Vogel 	s32 ret_val;
38438cfa0ad2SJack F Vogel 	u16 word = 0;
38448cfa0ad2SJack F Vogel 
3845c80429ceSEric Joyner 	/* In SPT, only 32 bits access is supported,
3846c80429ceSEric Joyner 	 * so this function should not be called.
3847c80429ceSEric Joyner 	 */
3848295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt)
3849c80429ceSEric Joyner 		return -E1000_ERR_NVM;
3850c80429ceSEric Joyner 	else
38518cfa0ad2SJack F Vogel 		ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
38528cc64f1eSJack F Vogel 
38538cfa0ad2SJack F Vogel 	if (ret_val)
38546ab6bfe3SJack F Vogel 		return ret_val;
38558cfa0ad2SJack F Vogel 
38568cfa0ad2SJack F Vogel 	*data = (u8)word;
38578cfa0ad2SJack F Vogel 
38586ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
38598cfa0ad2SJack F Vogel }
38608cfa0ad2SJack F Vogel 
38618cfa0ad2SJack F Vogel /**
38628cfa0ad2SJack F Vogel  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
38638cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
38648cfa0ad2SJack F Vogel  *  @offset: The offset (in bytes) of the byte or word to read.
38658cfa0ad2SJack F Vogel  *  @size: Size of data to read, 1=byte 2=word
38668cfa0ad2SJack F Vogel  *  @data: Pointer to the word to store the value read.
38678cfa0ad2SJack F Vogel  *
38688cfa0ad2SJack F Vogel  *  Reads a byte or word from the NVM using the flash access registers.
38698cfa0ad2SJack F Vogel  **/
38708cfa0ad2SJack F Vogel static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
38718cfa0ad2SJack F Vogel 					 u8 size, u16 *data)
38728cfa0ad2SJack F Vogel {
38738cfa0ad2SJack F Vogel 	union ich8_hws_flash_status hsfsts;
38748cfa0ad2SJack F Vogel 	union ich8_hws_flash_ctrl hsflctl;
38758cfa0ad2SJack F Vogel 	u32 flash_linear_addr;
38768cfa0ad2SJack F Vogel 	u32 flash_data = 0;
38778cfa0ad2SJack F Vogel 	s32 ret_val = -E1000_ERR_NVM;
38788cfa0ad2SJack F Vogel 	u8 count = 0;
38798cfa0ad2SJack F Vogel 
38808cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_read_flash_data_ich8lan");
38818cfa0ad2SJack F Vogel 
38828cfa0ad2SJack F Vogel 	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
38836ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
38847609433eSJack F Vogel 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
38857609433eSJack F Vogel 			     hw->nvm.flash_base_addr);
38868cfa0ad2SJack F Vogel 
38878cfa0ad2SJack F Vogel 	do {
38888cfa0ad2SJack F Vogel 		usec_delay(1);
38898cfa0ad2SJack F Vogel 		/* Steps */
38908cfa0ad2SJack F Vogel 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
38918cfa0ad2SJack F Vogel 		if (ret_val != E1000_SUCCESS)
38928cfa0ad2SJack F Vogel 			break;
38938cfa0ad2SJack F Vogel 		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
38948cc64f1eSJack F Vogel 
38958cfa0ad2SJack F Vogel 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
38968cfa0ad2SJack F Vogel 		hsflctl.hsf_ctrl.fldbcount = size - 1;
38978cfa0ad2SJack F Vogel 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
38988cfa0ad2SJack F Vogel 		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
38998cfa0ad2SJack F Vogel 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
39008cfa0ad2SJack F Vogel 
39018cc64f1eSJack F Vogel 		ret_val = e1000_flash_cycle_ich8lan(hw,
39028cfa0ad2SJack F Vogel 						ICH_FLASH_READ_COMMAND_TIMEOUT);
39038cfa0ad2SJack F Vogel 
39046ab6bfe3SJack F Vogel 		/* Check if FCERR is set to 1, if set to 1, clear it
39058cfa0ad2SJack F Vogel 		 * and try the whole sequence a few more times, else
39068cfa0ad2SJack F Vogel 		 * read in (shift in) the Flash Data0, the order is
39078cfa0ad2SJack F Vogel 		 * least significant byte first msb to lsb
39088cfa0ad2SJack F Vogel 		 */
39098cfa0ad2SJack F Vogel 		if (ret_val == E1000_SUCCESS) {
39108cfa0ad2SJack F Vogel 			flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3911daf9197cSJack F Vogel 			if (size == 1)
39128cfa0ad2SJack F Vogel 				*data = (u8)(flash_data & 0x000000FF);
3913daf9197cSJack F Vogel 			else if (size == 2)
39148cfa0ad2SJack F Vogel 				*data = (u16)(flash_data & 0x0000FFFF);
39158cfa0ad2SJack F Vogel 			break;
39168cfa0ad2SJack F Vogel 		} else {
39176ab6bfe3SJack F Vogel 			/* If we've gotten here, then things are probably
39188cfa0ad2SJack F Vogel 			 * completely hosed, but if the error condition is
39198cfa0ad2SJack F Vogel 			 * detected, it won't hurt to give it another try...
39208cfa0ad2SJack F Vogel 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
39218cfa0ad2SJack F Vogel 			 */
39228cfa0ad2SJack F Vogel 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
39238cfa0ad2SJack F Vogel 							      ICH_FLASH_HSFSTS);
39246ab6bfe3SJack F Vogel 			if (hsfsts.hsf_status.flcerr) {
39258cfa0ad2SJack F Vogel 				/* Repeat for some time before giving up. */
39268cfa0ad2SJack F Vogel 				continue;
39276ab6bfe3SJack F Vogel 			} else if (!hsfsts.hsf_status.flcdone) {
39284dab5c37SJack F Vogel 				DEBUGOUT("Timeout error - flash cycle did not complete.\n");
39298cfa0ad2SJack F Vogel 				break;
39308cfa0ad2SJack F Vogel 			}
39318cfa0ad2SJack F Vogel 		}
39328cfa0ad2SJack F Vogel 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
39338cfa0ad2SJack F Vogel 
39348cfa0ad2SJack F Vogel 	return ret_val;
39358cfa0ad2SJack F Vogel }
39368cfa0ad2SJack F Vogel 
3937c80429ceSEric Joyner /**
3938c80429ceSEric Joyner  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3939c80429ceSEric Joyner  *  @hw: pointer to the HW structure
3940c80429ceSEric Joyner  *  @offset: The offset (in bytes) of the dword to read.
3941c80429ceSEric Joyner  *  @data: Pointer to the dword to store the value read.
3942c80429ceSEric Joyner  *
3943c80429ceSEric Joyner  *  Reads a byte or word from the NVM using the flash access registers.
3944c80429ceSEric Joyner  **/
3945c80429ceSEric Joyner static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3946c80429ceSEric Joyner 					   u32 *data)
3947c80429ceSEric Joyner {
3948c80429ceSEric Joyner 	union ich8_hws_flash_status hsfsts;
3949c80429ceSEric Joyner 	union ich8_hws_flash_ctrl hsflctl;
3950c80429ceSEric Joyner 	u32 flash_linear_addr;
3951c80429ceSEric Joyner 	s32 ret_val = -E1000_ERR_NVM;
3952c80429ceSEric Joyner 	u8 count = 0;
3953c80429ceSEric Joyner 
3954c80429ceSEric Joyner 	DEBUGFUNC("e1000_read_flash_data_ich8lan");
3955c80429ceSEric Joyner 
3956c80429ceSEric Joyner 		if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3957295df609SEric Joyner 		    hw->mac.type < e1000_pch_spt)
3958c80429ceSEric Joyner 			return -E1000_ERR_NVM;
3959c80429ceSEric Joyner 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3960c80429ceSEric Joyner 			     hw->nvm.flash_base_addr);
3961c80429ceSEric Joyner 
3962c80429ceSEric Joyner 	do {
3963c80429ceSEric Joyner 		usec_delay(1);
3964c80429ceSEric Joyner 		/* Steps */
3965c80429ceSEric Joyner 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
3966c80429ceSEric Joyner 		if (ret_val != E1000_SUCCESS)
3967c80429ceSEric Joyner 			break;
3968c80429ceSEric Joyner 		/* In SPT, This register is in Lan memory space, not flash.
3969c80429ceSEric Joyner 		 * Therefore, only 32 bit access is supported
3970c80429ceSEric Joyner 		 */
3971c80429ceSEric Joyner 		hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3972c80429ceSEric Joyner 
3973c80429ceSEric Joyner 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3974c80429ceSEric Joyner 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3975c80429ceSEric Joyner 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3976c80429ceSEric Joyner 		/* In SPT, This register is in Lan memory space, not flash.
3977c80429ceSEric Joyner 		 * Therefore, only 32 bit access is supported
3978c80429ceSEric Joyner 		 */
3979c80429ceSEric Joyner 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3980c80429ceSEric Joyner 				      (u32)hsflctl.regval << 16);
3981c80429ceSEric Joyner 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3982c80429ceSEric Joyner 
3983c80429ceSEric Joyner 		ret_val = e1000_flash_cycle_ich8lan(hw,
3984c80429ceSEric Joyner 						ICH_FLASH_READ_COMMAND_TIMEOUT);
3985c80429ceSEric Joyner 
3986c80429ceSEric Joyner 		/* Check if FCERR is set to 1, if set to 1, clear it
3987c80429ceSEric Joyner 		 * and try the whole sequence a few more times, else
3988c80429ceSEric Joyner 		 * read in (shift in) the Flash Data0, the order is
3989c80429ceSEric Joyner 		 * least significant byte first msb to lsb
3990c80429ceSEric Joyner 		 */
3991c80429ceSEric Joyner 		if (ret_val == E1000_SUCCESS) {
3992c80429ceSEric Joyner 			*data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3993c80429ceSEric Joyner 			break;
3994c80429ceSEric Joyner 		} else {
3995c80429ceSEric Joyner 			/* If we've gotten here, then things are probably
3996c80429ceSEric Joyner 			 * completely hosed, but if the error condition is
3997c80429ceSEric Joyner 			 * detected, it won't hurt to give it another try...
3998c80429ceSEric Joyner 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3999c80429ceSEric Joyner 			 */
4000c80429ceSEric Joyner 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4001c80429ceSEric Joyner 							      ICH_FLASH_HSFSTS);
4002c80429ceSEric Joyner 			if (hsfsts.hsf_status.flcerr) {
4003c80429ceSEric Joyner 				/* Repeat for some time before giving up. */
4004c80429ceSEric Joyner 				continue;
4005c80429ceSEric Joyner 			} else if (!hsfsts.hsf_status.flcdone) {
4006c80429ceSEric Joyner 				DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4007c80429ceSEric Joyner 				break;
4008c80429ceSEric Joyner 			}
4009c80429ceSEric Joyner 		}
4010c80429ceSEric Joyner 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4011c80429ceSEric Joyner 
4012c80429ceSEric Joyner 	return ret_val;
4013c80429ceSEric Joyner }
40148cc64f1eSJack F Vogel 
40158cfa0ad2SJack F Vogel /**
40168cfa0ad2SJack F Vogel  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
40178cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
40188cfa0ad2SJack F Vogel  *  @offset: The offset (in bytes) of the word(s) to write.
40198cfa0ad2SJack F Vogel  *  @words: Size of data to write in words
40208cfa0ad2SJack F Vogel  *  @data: Pointer to the word(s) to write at offset.
40218cfa0ad2SJack F Vogel  *
40228cfa0ad2SJack F Vogel  *  Writes a byte or word to the NVM using the flash access registers.
40238cfa0ad2SJack F Vogel  **/
40248cfa0ad2SJack F Vogel static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
40258cfa0ad2SJack F Vogel 				   u16 *data)
40268cfa0ad2SJack F Vogel {
40278cfa0ad2SJack F Vogel 	struct e1000_nvm_info *nvm = &hw->nvm;
4028daf9197cSJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
40298cfa0ad2SJack F Vogel 	u16 i;
40308cfa0ad2SJack F Vogel 
40318cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_write_nvm_ich8lan");
40328cfa0ad2SJack F Vogel 
40338cfa0ad2SJack F Vogel 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
40348cfa0ad2SJack F Vogel 	    (words == 0)) {
40358cfa0ad2SJack F Vogel 		DEBUGOUT("nvm parameter(s) out of bounds\n");
40366ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
40378cfa0ad2SJack F Vogel 	}
40388cfa0ad2SJack F Vogel 
40394edd8523SJack F Vogel 	nvm->ops.acquire(hw);
40408cfa0ad2SJack F Vogel 
40418cfa0ad2SJack F Vogel 	for (i = 0; i < words; i++) {
40428cfa0ad2SJack F Vogel 		dev_spec->shadow_ram[offset+i].modified = TRUE;
40438cfa0ad2SJack F Vogel 		dev_spec->shadow_ram[offset+i].value = data[i];
40448cfa0ad2SJack F Vogel 	}
40458cfa0ad2SJack F Vogel 
40468cfa0ad2SJack F Vogel 	nvm->ops.release(hw);
40478cfa0ad2SJack F Vogel 
40486ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
40498cfa0ad2SJack F Vogel }
40508cfa0ad2SJack F Vogel 
40518cfa0ad2SJack F Vogel /**
4052c80429ceSEric Joyner  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
4053c80429ceSEric Joyner  *  @hw: pointer to the HW structure
4054c80429ceSEric Joyner  *
4055c80429ceSEric Joyner  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4056c80429ceSEric Joyner  *  which writes the checksum to the shadow ram.  The changes in the shadow
4057c80429ceSEric Joyner  *  ram are then committed to the EEPROM by processing each bank at a time
4058c80429ceSEric Joyner  *  checking for the modified bit and writing only the pending changes.
4059c80429ceSEric Joyner  *  After a successful commit, the shadow ram is cleared and is ready for
4060c80429ceSEric Joyner  *  future writes.
4061c80429ceSEric Joyner  **/
4062c80429ceSEric Joyner static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4063c80429ceSEric Joyner {
4064c80429ceSEric Joyner 	struct e1000_nvm_info *nvm = &hw->nvm;
4065c80429ceSEric Joyner 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4066c80429ceSEric Joyner 	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4067c80429ceSEric Joyner 	s32 ret_val;
4068c80429ceSEric Joyner 	u32 dword = 0;
4069c80429ceSEric Joyner 
4070c80429ceSEric Joyner 	DEBUGFUNC("e1000_update_nvm_checksum_spt");
4071c80429ceSEric Joyner 
4072c80429ceSEric Joyner 	ret_val = e1000_update_nvm_checksum_generic(hw);
4073c80429ceSEric Joyner 	if (ret_val)
4074c80429ceSEric Joyner 		goto out;
4075c80429ceSEric Joyner 
4076c80429ceSEric Joyner 	if (nvm->type != e1000_nvm_flash_sw)
4077c80429ceSEric Joyner 		goto out;
4078c80429ceSEric Joyner 
4079c80429ceSEric Joyner 	nvm->ops.acquire(hw);
4080c80429ceSEric Joyner 
4081c80429ceSEric Joyner 	/* We're writing to the opposite bank so if we're on bank 1,
4082c80429ceSEric Joyner 	 * write to bank 0 etc.  We also need to erase the segment that
4083c80429ceSEric Joyner 	 * is going to be written
4084c80429ceSEric Joyner 	 */
4085c80429ceSEric Joyner 	ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4086c80429ceSEric Joyner 	if (ret_val != E1000_SUCCESS) {
4087c80429ceSEric Joyner 		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4088c80429ceSEric Joyner 		bank = 0;
4089c80429ceSEric Joyner 	}
4090c80429ceSEric Joyner 
4091c80429ceSEric Joyner 	if (bank == 0) {
4092c80429ceSEric Joyner 		new_bank_offset = nvm->flash_bank_size;
4093c80429ceSEric Joyner 		old_bank_offset = 0;
4094c80429ceSEric Joyner 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4095c80429ceSEric Joyner 		if (ret_val)
4096c80429ceSEric Joyner 			goto release;
4097c80429ceSEric Joyner 	} else {
4098c80429ceSEric Joyner 		old_bank_offset = nvm->flash_bank_size;
4099c80429ceSEric Joyner 		new_bank_offset = 0;
4100c80429ceSEric Joyner 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4101c80429ceSEric Joyner 		if (ret_val)
4102c80429ceSEric Joyner 			goto release;
4103c80429ceSEric Joyner 	}
4104c80429ceSEric Joyner 	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4105c80429ceSEric Joyner 		/* Determine whether to write the value stored
4106c80429ceSEric Joyner 		 * in the other NVM bank or a modified value stored
4107c80429ceSEric Joyner 		 * in the shadow RAM
4108c80429ceSEric Joyner 		 */
4109c80429ceSEric Joyner 		ret_val = e1000_read_flash_dword_ich8lan(hw,
4110c80429ceSEric Joyner 							 i + old_bank_offset,
4111c80429ceSEric Joyner 							 &dword);
4112c80429ceSEric Joyner 
4113c80429ceSEric Joyner 		if (dev_spec->shadow_ram[i].modified) {
4114c80429ceSEric Joyner 			dword &= 0xffff0000;
4115c80429ceSEric Joyner 			dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4116c80429ceSEric Joyner 		}
4117c80429ceSEric Joyner 		if (dev_spec->shadow_ram[i + 1].modified) {
4118c80429ceSEric Joyner 			dword &= 0x0000ffff;
4119c80429ceSEric Joyner 			dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4120c80429ceSEric Joyner 				  << 16);
4121c80429ceSEric Joyner 		}
4122c80429ceSEric Joyner 		if (ret_val)
4123c80429ceSEric Joyner 			break;
4124c80429ceSEric Joyner 
4125c80429ceSEric Joyner 		/* If the word is 0x13, then make sure the signature bits
4126c80429ceSEric Joyner 		 * (15:14) are 11b until the commit has completed.
4127c80429ceSEric Joyner 		 * This will allow us to write 10b which indicates the
4128c80429ceSEric Joyner 		 * signature is valid.  We want to do this after the write
4129c80429ceSEric Joyner 		 * has completed so that we don't mark the segment valid
4130c80429ceSEric Joyner 		 * while the write is still in progress
4131c80429ceSEric Joyner 		 */
4132c80429ceSEric Joyner 		if (i == E1000_ICH_NVM_SIG_WORD - 1)
4133c80429ceSEric Joyner 			dword |= E1000_ICH_NVM_SIG_MASK << 16;
4134c80429ceSEric Joyner 
4135c80429ceSEric Joyner 		/* Convert offset to bytes. */
4136c80429ceSEric Joyner 		act_offset = (i + new_bank_offset) << 1;
4137c80429ceSEric Joyner 
4138c80429ceSEric Joyner 		usec_delay(100);
4139c80429ceSEric Joyner 
4140c80429ceSEric Joyner 		/* Write the data to the new bank. Offset in words*/
4141c80429ceSEric Joyner 		act_offset = i + new_bank_offset;
4142c80429ceSEric Joyner 		ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4143c80429ceSEric Joyner 								dword);
4144c80429ceSEric Joyner 		if (ret_val)
4145c80429ceSEric Joyner 			break;
4146c80429ceSEric Joyner 	 }
4147c80429ceSEric Joyner 
4148c80429ceSEric Joyner 	/* Don't bother writing the segment valid bits if sector
4149c80429ceSEric Joyner 	 * programming failed.
4150c80429ceSEric Joyner 	 */
4151c80429ceSEric Joyner 	if (ret_val) {
4152c80429ceSEric Joyner 		DEBUGOUT("Flash commit failed.\n");
4153c80429ceSEric Joyner 		goto release;
4154c80429ceSEric Joyner 	}
4155c80429ceSEric Joyner 
4156c80429ceSEric Joyner 	/* Finally validate the new segment by setting bit 15:14
4157c80429ceSEric Joyner 	 * to 10b in word 0x13 , this can be done without an
4158c80429ceSEric Joyner 	 * erase as well since these bits are 11 to start with
4159c80429ceSEric Joyner 	 * and we need to change bit 14 to 0b
4160c80429ceSEric Joyner 	 */
4161c80429ceSEric Joyner 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4162c80429ceSEric Joyner 
4163c80429ceSEric Joyner 	/*offset in words but we read dword*/
4164c80429ceSEric Joyner 	--act_offset;
4165c80429ceSEric Joyner 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4166c80429ceSEric Joyner 
4167c80429ceSEric Joyner 	if (ret_val)
4168c80429ceSEric Joyner 		goto release;
4169c80429ceSEric Joyner 
4170c80429ceSEric Joyner 	dword &= 0xBFFFFFFF;
4171c80429ceSEric Joyner 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4172c80429ceSEric Joyner 
4173c80429ceSEric Joyner 	if (ret_val)
4174c80429ceSEric Joyner 		goto release;
4175c80429ceSEric Joyner 
4176c80429ceSEric Joyner 	/* And invalidate the previously valid segment by setting
4177c80429ceSEric Joyner 	 * its signature word (0x13) high_byte to 0b. This can be
4178c80429ceSEric Joyner 	 * done without an erase because flash erase sets all bits
4179c80429ceSEric Joyner 	 * to 1's. We can write 1's to 0's without an erase
4180c80429ceSEric Joyner 	 */
4181c80429ceSEric Joyner 	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4182c80429ceSEric Joyner 
4183c80429ceSEric Joyner 	/* offset in words but we read dword*/
4184c80429ceSEric Joyner 	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4185c80429ceSEric Joyner 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4186c80429ceSEric Joyner 
4187c80429ceSEric Joyner 	if (ret_val)
4188c80429ceSEric Joyner 		goto release;
4189c80429ceSEric Joyner 
4190c80429ceSEric Joyner 	dword &= 0x00FFFFFF;
4191c80429ceSEric Joyner 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4192c80429ceSEric Joyner 
4193c80429ceSEric Joyner 	if (ret_val)
4194c80429ceSEric Joyner 		goto release;
4195c80429ceSEric Joyner 
4196c80429ceSEric Joyner 	/* Great!  Everything worked, we can now clear the cached entries. */
4197c80429ceSEric Joyner 	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4198c80429ceSEric Joyner 		dev_spec->shadow_ram[i].modified = FALSE;
4199c80429ceSEric Joyner 		dev_spec->shadow_ram[i].value = 0xFFFF;
4200c80429ceSEric Joyner 	}
4201c80429ceSEric Joyner 
4202c80429ceSEric Joyner release:
4203c80429ceSEric Joyner 	nvm->ops.release(hw);
4204c80429ceSEric Joyner 
4205c80429ceSEric Joyner 	/* Reload the EEPROM, or else modifications will not appear
4206c80429ceSEric Joyner 	 * until after the next adapter reset.
4207c80429ceSEric Joyner 	 */
4208c80429ceSEric Joyner 	if (!ret_val) {
4209c80429ceSEric Joyner 		nvm->ops.reload(hw);
4210c80429ceSEric Joyner 		msec_delay(10);
4211c80429ceSEric Joyner 	}
4212c80429ceSEric Joyner 
4213c80429ceSEric Joyner out:
4214c80429ceSEric Joyner 	if (ret_val)
4215c80429ceSEric Joyner 		DEBUGOUT1("NVM update error: %d\n", ret_val);
4216c80429ceSEric Joyner 
4217c80429ceSEric Joyner 	return ret_val;
4218c80429ceSEric Joyner }
4219c80429ceSEric Joyner 
4220c80429ceSEric Joyner /**
42218cfa0ad2SJack F Vogel  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
42228cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
42238cfa0ad2SJack F Vogel  *
42248cfa0ad2SJack F Vogel  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
42258cfa0ad2SJack F Vogel  *  which writes the checksum to the shadow ram.  The changes in the shadow
42268cfa0ad2SJack F Vogel  *  ram are then committed to the EEPROM by processing each bank at a time
42278cfa0ad2SJack F Vogel  *  checking for the modified bit and writing only the pending changes.
42288cfa0ad2SJack F Vogel  *  After a successful commit, the shadow ram is cleared and is ready for
42298cfa0ad2SJack F Vogel  *  future writes.
42308cfa0ad2SJack F Vogel  **/
42318cfa0ad2SJack F Vogel static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
42328cfa0ad2SJack F Vogel {
42338cfa0ad2SJack F Vogel 	struct e1000_nvm_info *nvm = &hw->nvm;
4234daf9197cSJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
42358cfa0ad2SJack F Vogel 	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
42368cfa0ad2SJack F Vogel 	s32 ret_val;
42378cc64f1eSJack F Vogel 	u16 data = 0;
42388cfa0ad2SJack F Vogel 
42398cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
42408cfa0ad2SJack F Vogel 
42418cfa0ad2SJack F Vogel 	ret_val = e1000_update_nvm_checksum_generic(hw);
42428cfa0ad2SJack F Vogel 	if (ret_val)
42438cfa0ad2SJack F Vogel 		goto out;
42448cfa0ad2SJack F Vogel 
42458cfa0ad2SJack F Vogel 	if (nvm->type != e1000_nvm_flash_sw)
42468cfa0ad2SJack F Vogel 		goto out;
42478cfa0ad2SJack F Vogel 
42484edd8523SJack F Vogel 	nvm->ops.acquire(hw);
42498cfa0ad2SJack F Vogel 
42506ab6bfe3SJack F Vogel 	/* We're writing to the opposite bank so if we're on bank 1,
42518cfa0ad2SJack F Vogel 	 * write to bank 0 etc.  We also need to erase the segment that
42528cfa0ad2SJack F Vogel 	 * is going to be written
42538cfa0ad2SJack F Vogel 	 */
42548cfa0ad2SJack F Vogel 	ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4255d035aa2dSJack F Vogel 	if (ret_val != E1000_SUCCESS) {
42564edd8523SJack F Vogel 		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
42574edd8523SJack F Vogel 		bank = 0;
4258d035aa2dSJack F Vogel 	}
42598cfa0ad2SJack F Vogel 
42608cfa0ad2SJack F Vogel 	if (bank == 0) {
42618cfa0ad2SJack F Vogel 		new_bank_offset = nvm->flash_bank_size;
42628cfa0ad2SJack F Vogel 		old_bank_offset = 0;
4263d035aa2dSJack F Vogel 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4264a69ed8dfSJack F Vogel 		if (ret_val)
4265a69ed8dfSJack F Vogel 			goto release;
42668cfa0ad2SJack F Vogel 	} else {
42678cfa0ad2SJack F Vogel 		old_bank_offset = nvm->flash_bank_size;
42688cfa0ad2SJack F Vogel 		new_bank_offset = 0;
4269d035aa2dSJack F Vogel 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4270a69ed8dfSJack F Vogel 		if (ret_val)
4271a69ed8dfSJack F Vogel 			goto release;
42728cfa0ad2SJack F Vogel 	}
42738cfa0ad2SJack F Vogel 	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
42748cfa0ad2SJack F Vogel 		if (dev_spec->shadow_ram[i].modified) {
42758cfa0ad2SJack F Vogel 			data = dev_spec->shadow_ram[i].value;
42768cfa0ad2SJack F Vogel 		} else {
4277d035aa2dSJack F Vogel 			ret_val = e1000_read_flash_word_ich8lan(hw, i +
4278d035aa2dSJack F Vogel 								old_bank_offset,
42798cfa0ad2SJack F Vogel 								&data);
4280d035aa2dSJack F Vogel 			if (ret_val)
4281d035aa2dSJack F Vogel 				break;
42828cfa0ad2SJack F Vogel 		}
42836ab6bfe3SJack F Vogel 		/* If the word is 0x13, then make sure the signature bits
42848cfa0ad2SJack F Vogel 		 * (15:14) are 11b until the commit has completed.
42858cfa0ad2SJack F Vogel 		 * This will allow us to write 10b which indicates the
42868cfa0ad2SJack F Vogel 		 * signature is valid.  We want to do this after the write
42878cfa0ad2SJack F Vogel 		 * has completed so that we don't mark the segment valid
42888cfa0ad2SJack F Vogel 		 * while the write is still in progress
42898cfa0ad2SJack F Vogel 		 */
42908cfa0ad2SJack F Vogel 		if (i == E1000_ICH_NVM_SIG_WORD)
42918cfa0ad2SJack F Vogel 			data |= E1000_ICH_NVM_SIG_MASK;
42928cfa0ad2SJack F Vogel 
42938cfa0ad2SJack F Vogel 		/* Convert offset to bytes. */
42948cfa0ad2SJack F Vogel 		act_offset = (i + new_bank_offset) << 1;
42958cfa0ad2SJack F Vogel 
42968cfa0ad2SJack F Vogel 		usec_delay(100);
42978cc64f1eSJack F Vogel 
42988cfa0ad2SJack F Vogel 		/* Write the bytes to the new bank. */
42998cfa0ad2SJack F Vogel 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
43008cfa0ad2SJack F Vogel 							       act_offset,
43018cfa0ad2SJack F Vogel 							       (u8)data);
43028cfa0ad2SJack F Vogel 		if (ret_val)
43038cfa0ad2SJack F Vogel 			break;
43048cfa0ad2SJack F Vogel 
43058cfa0ad2SJack F Vogel 		usec_delay(100);
43068cfa0ad2SJack F Vogel 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
43078cfa0ad2SJack F Vogel 							  act_offset + 1,
43088cfa0ad2SJack F Vogel 							  (u8)(data >> 8));
43098cfa0ad2SJack F Vogel 		if (ret_val)
43108cfa0ad2SJack F Vogel 			break;
43118cfa0ad2SJack F Vogel 	 }
43128cfa0ad2SJack F Vogel 
43136ab6bfe3SJack F Vogel 	/* Don't bother writing the segment valid bits if sector
43148cfa0ad2SJack F Vogel 	 * programming failed.
43158cfa0ad2SJack F Vogel 	 */
43168cfa0ad2SJack F Vogel 	if (ret_val) {
43178cfa0ad2SJack F Vogel 		DEBUGOUT("Flash commit failed.\n");
4318a69ed8dfSJack F Vogel 		goto release;
43198cfa0ad2SJack F Vogel 	}
43208cfa0ad2SJack F Vogel 
43216ab6bfe3SJack F Vogel 	/* Finally validate the new segment by setting bit 15:14
43228cfa0ad2SJack F Vogel 	 * to 10b in word 0x13 , this can be done without an
43238cfa0ad2SJack F Vogel 	 * erase as well since these bits are 11 to start with
43248cfa0ad2SJack F Vogel 	 * and we need to change bit 14 to 0b
43258cfa0ad2SJack F Vogel 	 */
43268cfa0ad2SJack F Vogel 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4327d035aa2dSJack F Vogel 	ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4328a69ed8dfSJack F Vogel 	if (ret_val)
4329a69ed8dfSJack F Vogel 		goto release;
43304edd8523SJack F Vogel 
43318cfa0ad2SJack F Vogel 	data &= 0xBFFF;
43328cc64f1eSJack F Vogel 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
43338cfa0ad2SJack F Vogel 						       (u8)(data >> 8));
4334a69ed8dfSJack F Vogel 	if (ret_val)
4335a69ed8dfSJack F Vogel 		goto release;
43368cfa0ad2SJack F Vogel 
43376ab6bfe3SJack F Vogel 	/* And invalidate the previously valid segment by setting
43388cfa0ad2SJack F Vogel 	 * its signature word (0x13) high_byte to 0b. This can be
43398cfa0ad2SJack F Vogel 	 * done without an erase because flash erase sets all bits
43408cfa0ad2SJack F Vogel 	 * to 1's. We can write 1's to 0's without an erase
43418cfa0ad2SJack F Vogel 	 */
43428cfa0ad2SJack F Vogel 	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
43438cc64f1eSJack F Vogel 
43448cfa0ad2SJack F Vogel 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
43458cc64f1eSJack F Vogel 
4346a69ed8dfSJack F Vogel 	if (ret_val)
4347a69ed8dfSJack F Vogel 		goto release;
43488cfa0ad2SJack F Vogel 
43498cfa0ad2SJack F Vogel 	/* Great!  Everything worked, we can now clear the cached entries. */
43508cfa0ad2SJack F Vogel 	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
43518cfa0ad2SJack F Vogel 		dev_spec->shadow_ram[i].modified = FALSE;
43528cfa0ad2SJack F Vogel 		dev_spec->shadow_ram[i].value = 0xFFFF;
43538cfa0ad2SJack F Vogel 	}
43548cfa0ad2SJack F Vogel 
4355a69ed8dfSJack F Vogel release:
43568cfa0ad2SJack F Vogel 	nvm->ops.release(hw);
43578cfa0ad2SJack F Vogel 
43586ab6bfe3SJack F Vogel 	/* Reload the EEPROM, or else modifications will not appear
43598cfa0ad2SJack F Vogel 	 * until after the next adapter reset.
43608cfa0ad2SJack F Vogel 	 */
4361a69ed8dfSJack F Vogel 	if (!ret_val) {
43628cfa0ad2SJack F Vogel 		nvm->ops.reload(hw);
43638cfa0ad2SJack F Vogel 		msec_delay(10);
4364a69ed8dfSJack F Vogel 	}
43658cfa0ad2SJack F Vogel 
43668cfa0ad2SJack F Vogel out:
4367d035aa2dSJack F Vogel 	if (ret_val)
4368d035aa2dSJack F Vogel 		DEBUGOUT1("NVM update error: %d\n", ret_val);
4369d035aa2dSJack F Vogel 
43708cfa0ad2SJack F Vogel 	return ret_val;
43718cfa0ad2SJack F Vogel }
43728cfa0ad2SJack F Vogel 
43738cfa0ad2SJack F Vogel /**
43748cfa0ad2SJack F Vogel  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
43758cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
43768cfa0ad2SJack F Vogel  *
43778cfa0ad2SJack F Vogel  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4378daf9197cSJack F Vogel  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4379daf9197cSJack F Vogel  *  calculated, in which case we need to calculate the checksum and set bit 6.
43808cfa0ad2SJack F Vogel  **/
43818cfa0ad2SJack F Vogel static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
43828cfa0ad2SJack F Vogel {
43836ab6bfe3SJack F Vogel 	s32 ret_val;
43848cfa0ad2SJack F Vogel 	u16 data;
43856ab6bfe3SJack F Vogel 	u16 word;
43866ab6bfe3SJack F Vogel 	u16 valid_csum_mask;
43878cfa0ad2SJack F Vogel 
43888cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
43898cfa0ad2SJack F Vogel 
43906ab6bfe3SJack F Vogel 	/* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
43916ab6bfe3SJack F Vogel 	 * the checksum needs to be fixed.  This bit is an indication that
43926ab6bfe3SJack F Vogel 	 * the NVM was prepared by OEM software and did not calculate
43936ab6bfe3SJack F Vogel 	 * the checksum...a likely scenario.
43948cfa0ad2SJack F Vogel 	 */
43956ab6bfe3SJack F Vogel 	switch (hw->mac.type) {
43966ab6bfe3SJack F Vogel 	case e1000_pch_lpt:
4397c80429ceSEric Joyner 	case e1000_pch_spt:
4398*6fe4c0a0SSean Bruno 	case e1000_pch_cnp:
43996ab6bfe3SJack F Vogel 		word = NVM_COMPAT;
44006ab6bfe3SJack F Vogel 		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
44016ab6bfe3SJack F Vogel 		break;
44026ab6bfe3SJack F Vogel 	default:
44036ab6bfe3SJack F Vogel 		word = NVM_FUTURE_INIT_WORD1;
44046ab6bfe3SJack F Vogel 		valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
44056ab6bfe3SJack F Vogel 		break;
44068cfa0ad2SJack F Vogel 	}
44078cfa0ad2SJack F Vogel 
44086ab6bfe3SJack F Vogel 	ret_val = hw->nvm.ops.read(hw, word, 1, &data);
44096ab6bfe3SJack F Vogel 	if (ret_val)
44108cfa0ad2SJack F Vogel 		return ret_val;
44116ab6bfe3SJack F Vogel 
44126ab6bfe3SJack F Vogel 	if (!(data & valid_csum_mask)) {
44136ab6bfe3SJack F Vogel 		data |= valid_csum_mask;
44146ab6bfe3SJack F Vogel 		ret_val = hw->nvm.ops.write(hw, word, 1, &data);
44156ab6bfe3SJack F Vogel 		if (ret_val)
44166ab6bfe3SJack F Vogel 			return ret_val;
44176ab6bfe3SJack F Vogel 		ret_val = hw->nvm.ops.update(hw);
44186ab6bfe3SJack F Vogel 		if (ret_val)
44196ab6bfe3SJack F Vogel 			return ret_val;
44206ab6bfe3SJack F Vogel 	}
44216ab6bfe3SJack F Vogel 
44226ab6bfe3SJack F Vogel 	return e1000_validate_nvm_checksum_generic(hw);
44238cfa0ad2SJack F Vogel }
44248cfa0ad2SJack F Vogel 
44258cfa0ad2SJack F Vogel /**
44268cfa0ad2SJack F Vogel  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
44278cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
44288cfa0ad2SJack F Vogel  *  @offset: The offset (in bytes) of the byte/word to read.
44298cfa0ad2SJack F Vogel  *  @size: Size of data to read, 1=byte 2=word
44308cfa0ad2SJack F Vogel  *  @data: The byte(s) to write to the NVM.
44318cfa0ad2SJack F Vogel  *
44328cfa0ad2SJack F Vogel  *  Writes one/two bytes to the NVM using the flash access registers.
44338cfa0ad2SJack F Vogel  **/
44348cfa0ad2SJack F Vogel static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
44358cfa0ad2SJack F Vogel 					  u8 size, u16 data)
44368cfa0ad2SJack F Vogel {
44378cfa0ad2SJack F Vogel 	union ich8_hws_flash_status hsfsts;
44388cfa0ad2SJack F Vogel 	union ich8_hws_flash_ctrl hsflctl;
44398cfa0ad2SJack F Vogel 	u32 flash_linear_addr;
44408cfa0ad2SJack F Vogel 	u32 flash_data = 0;
44416ab6bfe3SJack F Vogel 	s32 ret_val;
44428cfa0ad2SJack F Vogel 	u8 count = 0;
44438cfa0ad2SJack F Vogel 
44448cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_write_ich8_data");
44458cfa0ad2SJack F Vogel 
4446295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt) {
4447c80429ceSEric Joyner 		if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4448c80429ceSEric Joyner 			return -E1000_ERR_NVM;
4449c80429ceSEric Joyner 	} else {
44508cc64f1eSJack F Vogel 		if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
44516ab6bfe3SJack F Vogel 			return -E1000_ERR_NVM;
4452c80429ceSEric Joyner 	}
44538cfa0ad2SJack F Vogel 
44547609433eSJack F Vogel 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
44557609433eSJack F Vogel 			     hw->nvm.flash_base_addr);
44568cfa0ad2SJack F Vogel 
44578cfa0ad2SJack F Vogel 	do {
44588cfa0ad2SJack F Vogel 		usec_delay(1);
44598cfa0ad2SJack F Vogel 		/* Steps */
44608cfa0ad2SJack F Vogel 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
44618cfa0ad2SJack F Vogel 		if (ret_val != E1000_SUCCESS)
44628cfa0ad2SJack F Vogel 			break;
4463c80429ceSEric Joyner 		/* In SPT, This register is in Lan memory space, not
4464c80429ceSEric Joyner 		 * flash.  Therefore, only 32 bit access is supported
4465c80429ceSEric Joyner 		 */
4466295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_spt)
4467c80429ceSEric Joyner 			hsflctl.regval =
4468c80429ceSEric Joyner 			    E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4469c80429ceSEric Joyner 		else
4470c80429ceSEric Joyner 			hsflctl.regval =
4471c80429ceSEric Joyner 			    E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
44728cc64f1eSJack F Vogel 
44738cfa0ad2SJack F Vogel 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
44748cfa0ad2SJack F Vogel 		hsflctl.hsf_ctrl.fldbcount = size - 1;
44758cfa0ad2SJack F Vogel 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4476c80429ceSEric Joyner 		/* In SPT, This register is in Lan memory space,
4477c80429ceSEric Joyner 		 * not flash.  Therefore, only 32 bit access is
4478c80429ceSEric Joyner 		 * supported
4479c80429ceSEric Joyner 		 */
4480295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_spt)
4481c80429ceSEric Joyner 			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4482c80429ceSEric Joyner 					      hsflctl.regval << 16);
4483c80429ceSEric Joyner 		else
4484c80429ceSEric Joyner 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4485c80429ceSEric Joyner 						hsflctl.regval);
44868cfa0ad2SJack F Vogel 
44878cfa0ad2SJack F Vogel 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
44888cfa0ad2SJack F Vogel 
44898cfa0ad2SJack F Vogel 		if (size == 1)
44908cfa0ad2SJack F Vogel 			flash_data = (u32)data & 0x00FF;
44918cfa0ad2SJack F Vogel 		else
44928cfa0ad2SJack F Vogel 			flash_data = (u32)data;
44938cfa0ad2SJack F Vogel 
44948cfa0ad2SJack F Vogel 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
44958cfa0ad2SJack F Vogel 
44966ab6bfe3SJack F Vogel 		/* check if FCERR is set to 1 , if set to 1, clear it
44978cfa0ad2SJack F Vogel 		 * and try the whole sequence a few more times else done
44988cfa0ad2SJack F Vogel 		 */
44997609433eSJack F Vogel 		ret_val =
45007609433eSJack F Vogel 		    e1000_flash_cycle_ich8lan(hw,
45018cfa0ad2SJack F Vogel 					      ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4502daf9197cSJack F Vogel 		if (ret_val == E1000_SUCCESS)
45038cfa0ad2SJack F Vogel 			break;
4504daf9197cSJack F Vogel 
45056ab6bfe3SJack F Vogel 		/* If we're here, then things are most likely
45068cfa0ad2SJack F Vogel 		 * completely hosed, but if the error condition
45078cfa0ad2SJack F Vogel 		 * is detected, it won't hurt to give it another
45088cfa0ad2SJack F Vogel 		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
45098cfa0ad2SJack F Vogel 		 */
4510daf9197cSJack F Vogel 		hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
45116ab6bfe3SJack F Vogel 		if (hsfsts.hsf_status.flcerr)
45128cfa0ad2SJack F Vogel 			/* Repeat for some time before giving up. */
45138cfa0ad2SJack F Vogel 			continue;
45146ab6bfe3SJack F Vogel 		if (!hsfsts.hsf_status.flcdone) {
45154dab5c37SJack F Vogel 			DEBUGOUT("Timeout error - flash cycle did not complete.\n");
45168cfa0ad2SJack F Vogel 			break;
45178cfa0ad2SJack F Vogel 		}
45188cfa0ad2SJack F Vogel 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
45198cfa0ad2SJack F Vogel 
45208cfa0ad2SJack F Vogel 	return ret_val;
45218cfa0ad2SJack F Vogel }
45228cfa0ad2SJack F Vogel 
4523c80429ceSEric Joyner /**
4524c80429ceSEric Joyner *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4525c80429ceSEric Joyner *  @hw: pointer to the HW structure
4526c80429ceSEric Joyner *  @offset: The offset (in bytes) of the dwords to read.
4527c80429ceSEric Joyner *  @data: The 4 bytes to write to the NVM.
4528c80429ceSEric Joyner *
4529c80429ceSEric Joyner *  Writes one/two/four bytes to the NVM using the flash access registers.
4530c80429ceSEric Joyner **/
4531c80429ceSEric Joyner static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4532c80429ceSEric Joyner 					    u32 data)
4533c80429ceSEric Joyner {
4534c80429ceSEric Joyner 	union ich8_hws_flash_status hsfsts;
4535c80429ceSEric Joyner 	union ich8_hws_flash_ctrl hsflctl;
4536c80429ceSEric Joyner 	u32 flash_linear_addr;
4537c80429ceSEric Joyner 	s32 ret_val;
4538c80429ceSEric Joyner 	u8 count = 0;
4539c80429ceSEric Joyner 
4540c80429ceSEric Joyner 	DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4541c80429ceSEric Joyner 
4542295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_spt) {
4543c80429ceSEric Joyner 		if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4544c80429ceSEric Joyner 			return -E1000_ERR_NVM;
4545c80429ceSEric Joyner 	}
4546c80429ceSEric Joyner 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4547c80429ceSEric Joyner 			     hw->nvm.flash_base_addr);
4548c80429ceSEric Joyner 	do {
4549c80429ceSEric Joyner 		usec_delay(1);
4550c80429ceSEric Joyner 		/* Steps */
4551c80429ceSEric Joyner 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
4552c80429ceSEric Joyner 		if (ret_val != E1000_SUCCESS)
4553c80429ceSEric Joyner 			break;
4554c80429ceSEric Joyner 
4555c80429ceSEric Joyner 		/* In SPT, This register is in Lan memory space, not
4556c80429ceSEric Joyner 		 * flash.  Therefore, only 32 bit access is supported
4557c80429ceSEric Joyner 		 */
4558295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_spt)
4559c80429ceSEric Joyner 			hsflctl.regval = E1000_READ_FLASH_REG(hw,
4560c80429ceSEric Joyner 							      ICH_FLASH_HSFSTS)
4561c80429ceSEric Joyner 					 >> 16;
4562c80429ceSEric Joyner 		else
4563c80429ceSEric Joyner 			hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4564c80429ceSEric Joyner 							      ICH_FLASH_HSFCTL);
4565c80429ceSEric Joyner 
4566c80429ceSEric Joyner 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4567c80429ceSEric Joyner 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4568c80429ceSEric Joyner 
4569c80429ceSEric Joyner 		/* In SPT, This register is in Lan memory space,
4570c80429ceSEric Joyner 		 * not flash.  Therefore, only 32 bit access is
4571c80429ceSEric Joyner 		 * supported
4572c80429ceSEric Joyner 		 */
4573295df609SEric Joyner 		if (hw->mac.type >= e1000_pch_spt)
4574c80429ceSEric Joyner 			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4575c80429ceSEric Joyner 					      hsflctl.regval << 16);
4576c80429ceSEric Joyner 		else
4577c80429ceSEric Joyner 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4578c80429ceSEric Joyner 						hsflctl.regval);
4579c80429ceSEric Joyner 
4580c80429ceSEric Joyner 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4581c80429ceSEric Joyner 
4582c80429ceSEric Joyner 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4583c80429ceSEric Joyner 
4584c80429ceSEric Joyner 		/* check if FCERR is set to 1 , if set to 1, clear it
4585c80429ceSEric Joyner 		 * and try the whole sequence a few more times else done
4586c80429ceSEric Joyner 		 */
4587c80429ceSEric Joyner 		ret_val = e1000_flash_cycle_ich8lan(hw,
4588c80429ceSEric Joyner 					       ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4589c80429ceSEric Joyner 
4590c80429ceSEric Joyner 		if (ret_val == E1000_SUCCESS)
4591c80429ceSEric Joyner 			break;
4592c80429ceSEric Joyner 
4593c80429ceSEric Joyner 		/* If we're here, then things are most likely
4594c80429ceSEric Joyner 		 * completely hosed, but if the error condition
4595c80429ceSEric Joyner 		 * is detected, it won't hurt to give it another
4596c80429ceSEric Joyner 		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4597c80429ceSEric Joyner 		 */
4598c80429ceSEric Joyner 		hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4599c80429ceSEric Joyner 
4600c80429ceSEric Joyner 		if (hsfsts.hsf_status.flcerr)
4601c80429ceSEric Joyner 			/* Repeat for some time before giving up. */
4602c80429ceSEric Joyner 			continue;
4603c80429ceSEric Joyner 		if (!hsfsts.hsf_status.flcdone) {
4604c80429ceSEric Joyner 			DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4605c80429ceSEric Joyner 			break;
4606c80429ceSEric Joyner 		}
4607c80429ceSEric Joyner 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4608c80429ceSEric Joyner 
4609c80429ceSEric Joyner 	return ret_val;
4610c80429ceSEric Joyner }
46118cc64f1eSJack F Vogel 
46128cfa0ad2SJack F Vogel /**
46138cfa0ad2SJack F Vogel  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
46148cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
46158cfa0ad2SJack F Vogel  *  @offset: The index of the byte to read.
46168cfa0ad2SJack F Vogel  *  @data: The byte to write to the NVM.
46178cfa0ad2SJack F Vogel  *
46188cfa0ad2SJack F Vogel  *  Writes a single byte to the NVM using the flash access registers.
46198cfa0ad2SJack F Vogel  **/
46208cfa0ad2SJack F Vogel static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
46218cfa0ad2SJack F Vogel 					  u8 data)
46228cfa0ad2SJack F Vogel {
46238cfa0ad2SJack F Vogel 	u16 word = (u16)data;
46248cfa0ad2SJack F Vogel 
46258cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_write_flash_byte_ich8lan");
46268cfa0ad2SJack F Vogel 
46278cfa0ad2SJack F Vogel 	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
46288cfa0ad2SJack F Vogel }
46298cfa0ad2SJack F Vogel 
4630c80429ceSEric Joyner /**
4631c80429ceSEric Joyner *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4632c80429ceSEric Joyner *  @hw: pointer to the HW structure
4633c80429ceSEric Joyner *  @offset: The offset of the word to write.
4634c80429ceSEric Joyner *  @dword: The dword to write to the NVM.
4635c80429ceSEric Joyner *
4636c80429ceSEric Joyner *  Writes a single dword to the NVM using the flash access registers.
4637c80429ceSEric Joyner *  Goes through a retry algorithm before giving up.
4638c80429ceSEric Joyner **/
4639c80429ceSEric Joyner static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4640c80429ceSEric Joyner 						 u32 offset, u32 dword)
4641c80429ceSEric Joyner {
4642c80429ceSEric Joyner 	s32 ret_val;
4643c80429ceSEric Joyner 	u16 program_retries;
46448cc64f1eSJack F Vogel 
4645c80429ceSEric Joyner 	DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4646c80429ceSEric Joyner 
4647c80429ceSEric Joyner 	/* Must convert word offset into bytes. */
4648c80429ceSEric Joyner 	offset <<= 1;
4649c80429ceSEric Joyner 
4650c80429ceSEric Joyner 	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4651c80429ceSEric Joyner 
4652c80429ceSEric Joyner 	if (!ret_val)
4653c80429ceSEric Joyner 		return ret_val;
4654c80429ceSEric Joyner 	for (program_retries = 0; program_retries < 100; program_retries++) {
4655c80429ceSEric Joyner 		DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4656c80429ceSEric Joyner 		usec_delay(100);
4657c80429ceSEric Joyner 		ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4658c80429ceSEric Joyner 		if (ret_val == E1000_SUCCESS)
4659c80429ceSEric Joyner 			break;
4660c80429ceSEric Joyner 	}
4661c80429ceSEric Joyner 	if (program_retries == 100)
4662c80429ceSEric Joyner 		return -E1000_ERR_NVM;
4663c80429ceSEric Joyner 
4664c80429ceSEric Joyner 	return E1000_SUCCESS;
4665c80429ceSEric Joyner }
46668cc64f1eSJack F Vogel 
46678cfa0ad2SJack F Vogel /**
46688cfa0ad2SJack F Vogel  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
46698cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
46708cfa0ad2SJack F Vogel  *  @offset: The offset of the byte to write.
46718cfa0ad2SJack F Vogel  *  @byte: The byte to write to the NVM.
46728cfa0ad2SJack F Vogel  *
46738cfa0ad2SJack F Vogel  *  Writes a single byte to the NVM using the flash access registers.
46748cfa0ad2SJack F Vogel  *  Goes through a retry algorithm before giving up.
46758cfa0ad2SJack F Vogel  **/
46768cfa0ad2SJack F Vogel static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
46778cfa0ad2SJack F Vogel 						u32 offset, u8 byte)
46788cfa0ad2SJack F Vogel {
46798cfa0ad2SJack F Vogel 	s32 ret_val;
46808cfa0ad2SJack F Vogel 	u16 program_retries;
46818cfa0ad2SJack F Vogel 
46828cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
46838cfa0ad2SJack F Vogel 
46848cfa0ad2SJack F Vogel 	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
46856ab6bfe3SJack F Vogel 	if (!ret_val)
46866ab6bfe3SJack F Vogel 		return ret_val;
46878cfa0ad2SJack F Vogel 
46888cfa0ad2SJack F Vogel 	for (program_retries = 0; program_retries < 100; program_retries++) {
46898cfa0ad2SJack F Vogel 		DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
46908cfa0ad2SJack F Vogel 		usec_delay(100);
46918cfa0ad2SJack F Vogel 		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
46928cfa0ad2SJack F Vogel 		if (ret_val == E1000_SUCCESS)
46938cfa0ad2SJack F Vogel 			break;
46948cfa0ad2SJack F Vogel 	}
46956ab6bfe3SJack F Vogel 	if (program_retries == 100)
46966ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
46978cfa0ad2SJack F Vogel 
46986ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
46998cfa0ad2SJack F Vogel }
47008cfa0ad2SJack F Vogel 
47018cfa0ad2SJack F Vogel /**
47028cfa0ad2SJack F Vogel  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
47038cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
47048cfa0ad2SJack F Vogel  *  @bank: 0 for first bank, 1 for second bank, etc.
47058cfa0ad2SJack F Vogel  *
47068cfa0ad2SJack F Vogel  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
47078cfa0ad2SJack F Vogel  *  bank N is 4096 * N + flash_reg_addr.
47088cfa0ad2SJack F Vogel  **/
47098cfa0ad2SJack F Vogel static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
47108cfa0ad2SJack F Vogel {
47118cfa0ad2SJack F Vogel 	struct e1000_nvm_info *nvm = &hw->nvm;
47128cfa0ad2SJack F Vogel 	union ich8_hws_flash_status hsfsts;
47138cfa0ad2SJack F Vogel 	union ich8_hws_flash_ctrl hsflctl;
47148cfa0ad2SJack F Vogel 	u32 flash_linear_addr;
47158cfa0ad2SJack F Vogel 	/* bank size is in 16bit words - adjust to bytes */
47168cfa0ad2SJack F Vogel 	u32 flash_bank_size = nvm->flash_bank_size * 2;
47176ab6bfe3SJack F Vogel 	s32 ret_val;
47188cfa0ad2SJack F Vogel 	s32 count = 0;
47198cfa0ad2SJack F Vogel 	s32 j, iteration, sector_size;
47208cfa0ad2SJack F Vogel 
47218cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
47228cfa0ad2SJack F Vogel 
47238cfa0ad2SJack F Vogel 	hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
47248cfa0ad2SJack F Vogel 
47256ab6bfe3SJack F Vogel 	/* Determine HW Sector size: Read BERASE bits of hw flash status
47268cfa0ad2SJack F Vogel 	 * register
47278cfa0ad2SJack F Vogel 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16
47288cfa0ad2SJack F Vogel 	 *     consecutive sectors.  The start index for the nth Hw sector
47298cfa0ad2SJack F Vogel 	 *     can be calculated as = bank * 4096 + n * 256
47308cfa0ad2SJack F Vogel 	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
47318cfa0ad2SJack F Vogel 	 *     The start index for the nth Hw sector can be calculated
47328cfa0ad2SJack F Vogel 	 *     as = bank * 4096
47338cfa0ad2SJack F Vogel 	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
47348cfa0ad2SJack F Vogel 	 *     (ich9 only, otherwise error condition)
47358cfa0ad2SJack F Vogel 	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
47368cfa0ad2SJack F Vogel 	 */
47378cfa0ad2SJack F Vogel 	switch (hsfsts.hsf_status.berasesz) {
47388cfa0ad2SJack F Vogel 	case 0:
47398cfa0ad2SJack F Vogel 		/* Hw sector size 256 */
47408cfa0ad2SJack F Vogel 		sector_size = ICH_FLASH_SEG_SIZE_256;
47418cfa0ad2SJack F Vogel 		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
47428cfa0ad2SJack F Vogel 		break;
47438cfa0ad2SJack F Vogel 	case 1:
47448cfa0ad2SJack F Vogel 		sector_size = ICH_FLASH_SEG_SIZE_4K;
47459d81738fSJack F Vogel 		iteration = 1;
47468cfa0ad2SJack F Vogel 		break;
47478cfa0ad2SJack F Vogel 	case 2:
47488cfa0ad2SJack F Vogel 		sector_size = ICH_FLASH_SEG_SIZE_8K;
47498bd0025fSJack F Vogel 		iteration = 1;
47508cfa0ad2SJack F Vogel 		break;
47518cfa0ad2SJack F Vogel 	case 3:
47528cfa0ad2SJack F Vogel 		sector_size = ICH_FLASH_SEG_SIZE_64K;
47539d81738fSJack F Vogel 		iteration = 1;
47548cfa0ad2SJack F Vogel 		break;
47558cfa0ad2SJack F Vogel 	default:
47566ab6bfe3SJack F Vogel 		return -E1000_ERR_NVM;
47578cfa0ad2SJack F Vogel 	}
47588cfa0ad2SJack F Vogel 
47598cfa0ad2SJack F Vogel 	/* Start with the base address, then add the sector offset. */
47608cfa0ad2SJack F Vogel 	flash_linear_addr = hw->nvm.flash_base_addr;
47614edd8523SJack F Vogel 	flash_linear_addr += (bank) ? flash_bank_size : 0;
47628cfa0ad2SJack F Vogel 
47638cfa0ad2SJack F Vogel 	for (j = 0; j < iteration; j++) {
47648cfa0ad2SJack F Vogel 		do {
47657609433eSJack F Vogel 			u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
47667609433eSJack F Vogel 
47678cfa0ad2SJack F Vogel 			/* Steps */
47688cfa0ad2SJack F Vogel 			ret_val = e1000_flash_cycle_init_ich8lan(hw);
47698cfa0ad2SJack F Vogel 			if (ret_val)
47706ab6bfe3SJack F Vogel 				return ret_val;
47718cfa0ad2SJack F Vogel 
47726ab6bfe3SJack F Vogel 			/* Write a value 11 (block Erase) in Flash
47738cfa0ad2SJack F Vogel 			 * Cycle field in hw flash control
47748cfa0ad2SJack F Vogel 			 */
4775295df609SEric Joyner 			if (hw->mac.type >= e1000_pch_spt)
47768cc64f1eSJack F Vogel 				hsflctl.regval =
4777c80429ceSEric Joyner 				    E1000_READ_FLASH_REG(hw,
4778c80429ceSEric Joyner 							 ICH_FLASH_HSFSTS)>>16;
4779c80429ceSEric Joyner 			else
4780c80429ceSEric Joyner 				hsflctl.regval =
4781c80429ceSEric Joyner 				    E1000_READ_FLASH_REG16(hw,
4782c80429ceSEric Joyner 							   ICH_FLASH_HSFCTL);
47838cc64f1eSJack F Vogel 
47848cfa0ad2SJack F Vogel 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4785295df609SEric Joyner 			if (hw->mac.type >= e1000_pch_spt)
4786c80429ceSEric Joyner 				E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4787c80429ceSEric Joyner 						      hsflctl.regval << 16);
4788c80429ceSEric Joyner 			else
4789daf9197cSJack F Vogel 				E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
47908cfa0ad2SJack F Vogel 							hsflctl.regval);
47918cfa0ad2SJack F Vogel 
47926ab6bfe3SJack F Vogel 			/* Write the last 24 bits of an index within the
47938cfa0ad2SJack F Vogel 			 * block into Flash Linear address field in Flash
47948cfa0ad2SJack F Vogel 			 * Address.
47958cfa0ad2SJack F Vogel 			 */
47968cfa0ad2SJack F Vogel 			flash_linear_addr += (j * sector_size);
4797daf9197cSJack F Vogel 			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
47988cfa0ad2SJack F Vogel 					      flash_linear_addr);
47998cfa0ad2SJack F Vogel 
48007609433eSJack F Vogel 			ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4801daf9197cSJack F Vogel 			if (ret_val == E1000_SUCCESS)
48028cfa0ad2SJack F Vogel 				break;
4803daf9197cSJack F Vogel 
48046ab6bfe3SJack F Vogel 			/* Check if FCERR is set to 1.  If 1,
48058cfa0ad2SJack F Vogel 			 * clear it and try the whole sequence
48068cfa0ad2SJack F Vogel 			 * a few more times else Done
48078cfa0ad2SJack F Vogel 			 */
48088cfa0ad2SJack F Vogel 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
48098cfa0ad2SJack F Vogel 						      ICH_FLASH_HSFSTS);
48106ab6bfe3SJack F Vogel 			if (hsfsts.hsf_status.flcerr)
4811daf9197cSJack F Vogel 				/* repeat for some time before giving up */
48128cfa0ad2SJack F Vogel 				continue;
48136ab6bfe3SJack F Vogel 			else if (!hsfsts.hsf_status.flcdone)
48146ab6bfe3SJack F Vogel 				return ret_val;
48158cfa0ad2SJack F Vogel 		} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
48168cfa0ad2SJack F Vogel 	}
48178cfa0ad2SJack F Vogel 
48186ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
48198cfa0ad2SJack F Vogel }
48208cfa0ad2SJack F Vogel 
48218cfa0ad2SJack F Vogel /**
48228cfa0ad2SJack F Vogel  *  e1000_valid_led_default_ich8lan - Set the default LED settings
48238cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
48248cfa0ad2SJack F Vogel  *  @data: Pointer to the LED settings
48258cfa0ad2SJack F Vogel  *
48268cfa0ad2SJack F Vogel  *  Reads the LED default settings from the NVM to data.  If the NVM LED
48278cfa0ad2SJack F Vogel  *  settings is all 0's or F's, set the LED default to a valid LED default
48288cfa0ad2SJack F Vogel  *  setting.
48298cfa0ad2SJack F Vogel  **/
48308cfa0ad2SJack F Vogel static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
48318cfa0ad2SJack F Vogel {
48328cfa0ad2SJack F Vogel 	s32 ret_val;
48338cfa0ad2SJack F Vogel 
48348cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_valid_led_default_ich8lan");
48358cfa0ad2SJack F Vogel 
48368cfa0ad2SJack F Vogel 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
48378cfa0ad2SJack F Vogel 	if (ret_val) {
48388cfa0ad2SJack F Vogel 		DEBUGOUT("NVM Read Error\n");
48396ab6bfe3SJack F Vogel 		return ret_val;
48408cfa0ad2SJack F Vogel 	}
48418cfa0ad2SJack F Vogel 
48424dab5c37SJack F Vogel 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
48438cfa0ad2SJack F Vogel 		*data = ID_LED_DEFAULT_ICH8LAN;
48448cfa0ad2SJack F Vogel 
48456ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
48468cfa0ad2SJack F Vogel }
48478cfa0ad2SJack F Vogel 
48488cfa0ad2SJack F Vogel /**
48499d81738fSJack F Vogel  *  e1000_id_led_init_pchlan - store LED configurations
48509d81738fSJack F Vogel  *  @hw: pointer to the HW structure
48519d81738fSJack F Vogel  *
48529d81738fSJack F Vogel  *  PCH does not control LEDs via the LEDCTL register, rather it uses
48539d81738fSJack F Vogel  *  the PHY LED configuration register.
48549d81738fSJack F Vogel  *
48559d81738fSJack F Vogel  *  PCH also does not have an "always on" or "always off" mode which
48569d81738fSJack F Vogel  *  complicates the ID feature.  Instead of using the "on" mode to indicate
48579d81738fSJack F Vogel  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
48589d81738fSJack F Vogel  *  use "link_up" mode.  The LEDs will still ID on request if there is no
48599d81738fSJack F Vogel  *  link based on logic in e1000_led_[on|off]_pchlan().
48609d81738fSJack F Vogel  **/
48619d81738fSJack F Vogel static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
48629d81738fSJack F Vogel {
48639d81738fSJack F Vogel 	struct e1000_mac_info *mac = &hw->mac;
48649d81738fSJack F Vogel 	s32 ret_val;
48659d81738fSJack F Vogel 	const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
48669d81738fSJack F Vogel 	const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
48679d81738fSJack F Vogel 	u16 data, i, temp, shift;
48689d81738fSJack F Vogel 
48699d81738fSJack F Vogel 	DEBUGFUNC("e1000_id_led_init_pchlan");
48709d81738fSJack F Vogel 
48719d81738fSJack F Vogel 	/* Get default ID LED modes */
48729d81738fSJack F Vogel 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
48739d81738fSJack F Vogel 	if (ret_val)
48746ab6bfe3SJack F Vogel 		return ret_val;
48759d81738fSJack F Vogel 
48769d81738fSJack F Vogel 	mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
48779d81738fSJack F Vogel 	mac->ledctl_mode1 = mac->ledctl_default;
48789d81738fSJack F Vogel 	mac->ledctl_mode2 = mac->ledctl_default;
48799d81738fSJack F Vogel 
48809d81738fSJack F Vogel 	for (i = 0; i < 4; i++) {
48819d81738fSJack F Vogel 		temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
48829d81738fSJack F Vogel 		shift = (i * 5);
48839d81738fSJack F Vogel 		switch (temp) {
48849d81738fSJack F Vogel 		case ID_LED_ON1_DEF2:
48859d81738fSJack F Vogel 		case ID_LED_ON1_ON2:
48869d81738fSJack F Vogel 		case ID_LED_ON1_OFF2:
48879d81738fSJack F Vogel 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
48889d81738fSJack F Vogel 			mac->ledctl_mode1 |= (ledctl_on << shift);
48899d81738fSJack F Vogel 			break;
48909d81738fSJack F Vogel 		case ID_LED_OFF1_DEF2:
48919d81738fSJack F Vogel 		case ID_LED_OFF1_ON2:
48929d81738fSJack F Vogel 		case ID_LED_OFF1_OFF2:
48939d81738fSJack F Vogel 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
48949d81738fSJack F Vogel 			mac->ledctl_mode1 |= (ledctl_off << shift);
48959d81738fSJack F Vogel 			break;
48969d81738fSJack F Vogel 		default:
48979d81738fSJack F Vogel 			/* Do nothing */
48989d81738fSJack F Vogel 			break;
48999d81738fSJack F Vogel 		}
49009d81738fSJack F Vogel 		switch (temp) {
49019d81738fSJack F Vogel 		case ID_LED_DEF1_ON2:
49029d81738fSJack F Vogel 		case ID_LED_ON1_ON2:
49039d81738fSJack F Vogel 		case ID_LED_OFF1_ON2:
49049d81738fSJack F Vogel 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
49059d81738fSJack F Vogel 			mac->ledctl_mode2 |= (ledctl_on << shift);
49069d81738fSJack F Vogel 			break;
49079d81738fSJack F Vogel 		case ID_LED_DEF1_OFF2:
49089d81738fSJack F Vogel 		case ID_LED_ON1_OFF2:
49099d81738fSJack F Vogel 		case ID_LED_OFF1_OFF2:
49109d81738fSJack F Vogel 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
49119d81738fSJack F Vogel 			mac->ledctl_mode2 |= (ledctl_off << shift);
49129d81738fSJack F Vogel 			break;
49139d81738fSJack F Vogel 		default:
49149d81738fSJack F Vogel 			/* Do nothing */
49159d81738fSJack F Vogel 			break;
49169d81738fSJack F Vogel 		}
49179d81738fSJack F Vogel 	}
49189d81738fSJack F Vogel 
49196ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
49209d81738fSJack F Vogel }
49219d81738fSJack F Vogel 
49229d81738fSJack F Vogel /**
49238cfa0ad2SJack F Vogel  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
49248cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
49258cfa0ad2SJack F Vogel  *
49268cfa0ad2SJack F Vogel  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4927cef367e6SEitan Adler  *  register, so the bus width is hard coded.
49288cfa0ad2SJack F Vogel  **/
49298cfa0ad2SJack F Vogel static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
49308cfa0ad2SJack F Vogel {
49318cfa0ad2SJack F Vogel 	struct e1000_bus_info *bus = &hw->bus;
49328cfa0ad2SJack F Vogel 	s32 ret_val;
49338cfa0ad2SJack F Vogel 
49348cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_get_bus_info_ich8lan");
49358cfa0ad2SJack F Vogel 
49368cfa0ad2SJack F Vogel 	ret_val = e1000_get_bus_info_pcie_generic(hw);
49378cfa0ad2SJack F Vogel 
49386ab6bfe3SJack F Vogel 	/* ICH devices are "PCI Express"-ish.  They have
49398cfa0ad2SJack F Vogel 	 * a configuration space, but do not contain
49408cfa0ad2SJack F Vogel 	 * PCI Express Capability registers, so bus width
49418cfa0ad2SJack F Vogel 	 * must be hardcoded.
49428cfa0ad2SJack F Vogel 	 */
49438cfa0ad2SJack F Vogel 	if (bus->width == e1000_bus_width_unknown)
49448cfa0ad2SJack F Vogel 		bus->width = e1000_bus_width_pcie_x1;
49458cfa0ad2SJack F Vogel 
49468cfa0ad2SJack F Vogel 	return ret_val;
49478cfa0ad2SJack F Vogel }
49488cfa0ad2SJack F Vogel 
49498cfa0ad2SJack F Vogel /**
49508cfa0ad2SJack F Vogel  *  e1000_reset_hw_ich8lan - Reset the hardware
49518cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
49528cfa0ad2SJack F Vogel  *
49538cfa0ad2SJack F Vogel  *  Does a full reset of the hardware which includes a reset of the PHY and
49548cfa0ad2SJack F Vogel  *  MAC.
49558cfa0ad2SJack F Vogel  **/
49568cfa0ad2SJack F Vogel static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
49578cfa0ad2SJack F Vogel {
49584edd8523SJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
49596ab6bfe3SJack F Vogel 	u16 kum_cfg;
49606ab6bfe3SJack F Vogel 	u32 ctrl, reg;
49618cfa0ad2SJack F Vogel 	s32 ret_val;
49628cfa0ad2SJack F Vogel 
49638cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_reset_hw_ich8lan");
49648cfa0ad2SJack F Vogel 
49656ab6bfe3SJack F Vogel 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
49668cfa0ad2SJack F Vogel 	 * on the last TLP read/write transaction when MAC is reset.
49678cfa0ad2SJack F Vogel 	 */
49688cfa0ad2SJack F Vogel 	ret_val = e1000_disable_pcie_master_generic(hw);
4969daf9197cSJack F Vogel 	if (ret_val)
49708cfa0ad2SJack F Vogel 		DEBUGOUT("PCI-E Master disable polling has failed.\n");
49718cfa0ad2SJack F Vogel 
49728cfa0ad2SJack F Vogel 	DEBUGOUT("Masking off all interrupts\n");
49738cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
49748cfa0ad2SJack F Vogel 
49756ab6bfe3SJack F Vogel 	/* Disable the Transmit and Receive units.  Then delay to allow
49768cfa0ad2SJack F Vogel 	 * any pending transactions to complete before we hit the MAC
49778cfa0ad2SJack F Vogel 	 * with the global reset.
49788cfa0ad2SJack F Vogel 	 */
49798cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_RCTL, 0);
49808cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
49818cfa0ad2SJack F Vogel 	E1000_WRITE_FLUSH(hw);
49828cfa0ad2SJack F Vogel 
49838cfa0ad2SJack F Vogel 	msec_delay(10);
49848cfa0ad2SJack F Vogel 
49858cfa0ad2SJack F Vogel 	/* Workaround for ICH8 bit corruption issue in FIFO memory */
49868cfa0ad2SJack F Vogel 	if (hw->mac.type == e1000_ich8lan) {
49878cfa0ad2SJack F Vogel 		/* Set Tx and Rx buffer allocation to 8k apiece. */
49888cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
49898cfa0ad2SJack F Vogel 		/* Set Packet Buffer Size to 16k. */
49908cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
49918cfa0ad2SJack F Vogel 	}
49928cfa0ad2SJack F Vogel 
49934edd8523SJack F Vogel 	if (hw->mac.type == e1000_pchlan) {
49944edd8523SJack F Vogel 		/* Save the NVM K1 bit setting*/
49956ab6bfe3SJack F Vogel 		ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
49964edd8523SJack F Vogel 		if (ret_val)
49974edd8523SJack F Vogel 			return ret_val;
49984edd8523SJack F Vogel 
49996ab6bfe3SJack F Vogel 		if (kum_cfg & E1000_NVM_K1_ENABLE)
50004edd8523SJack F Vogel 			dev_spec->nvm_k1_enabled = TRUE;
50014edd8523SJack F Vogel 		else
50024edd8523SJack F Vogel 			dev_spec->nvm_k1_enabled = FALSE;
50034edd8523SJack F Vogel 	}
50044edd8523SJack F Vogel 
50058cfa0ad2SJack F Vogel 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
50068cfa0ad2SJack F Vogel 
50077d9119bdSJack F Vogel 	if (!hw->phy.ops.check_reset_block(hw)) {
50086ab6bfe3SJack F Vogel 		/* Full-chip reset requires MAC and PHY reset at the same
50098cfa0ad2SJack F Vogel 		 * time to make sure the interface between MAC and the
50108cfa0ad2SJack F Vogel 		 * external PHY is reset.
50118cfa0ad2SJack F Vogel 		 */
50128cfa0ad2SJack F Vogel 		ctrl |= E1000_CTRL_PHY_RST;
50137d9119bdSJack F Vogel 
50146ab6bfe3SJack F Vogel 		/* Gate automatic PHY configuration by hardware on
50157d9119bdSJack F Vogel 		 * non-managed 82579
50167d9119bdSJack F Vogel 		 */
50177d9119bdSJack F Vogel 		if ((hw->mac.type == e1000_pch2lan) &&
50187d9119bdSJack F Vogel 		    !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
50197d9119bdSJack F Vogel 			e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
50208cfa0ad2SJack F Vogel 	}
50218cfa0ad2SJack F Vogel 	ret_val = e1000_acquire_swflag_ich8lan(hw);
5022daf9197cSJack F Vogel 	DEBUGOUT("Issuing a global reset to ich8lan\n");
50238cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
50244dab5c37SJack F Vogel 	/* cannot issue a flush here because it hangs the hardware */
50258cfa0ad2SJack F Vogel 	msec_delay(20);
50268cfa0ad2SJack F Vogel 
50276ab6bfe3SJack F Vogel 	/* Set Phy Config Counter to 50msec */
50286ab6bfe3SJack F Vogel 	if (hw->mac.type == e1000_pch2lan) {
50296ab6bfe3SJack F Vogel 		reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
50306ab6bfe3SJack F Vogel 		reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
50316ab6bfe3SJack F Vogel 		reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
50326ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
50336ab6bfe3SJack F Vogel 	}
50346ab6bfe3SJack F Vogel 
5035ab2e3f79SStephen Hurd 	if (!ret_val)
5036ab2e3f79SStephen Hurd 		E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
50379d81738fSJack F Vogel 
50387d9119bdSJack F Vogel 	if (ctrl & E1000_CTRL_PHY_RST) {
50399d81738fSJack F Vogel 		ret_val = hw->phy.ops.get_cfg_done(hw);
50404edd8523SJack F Vogel 		if (ret_val)
50416ab6bfe3SJack F Vogel 			return ret_val;
50424edd8523SJack F Vogel 
50437d9119bdSJack F Vogel 		ret_val = e1000_post_phy_reset_ich8lan(hw);
50444edd8523SJack F Vogel 		if (ret_val)
50456ab6bfe3SJack F Vogel 			return ret_val;
50467d9119bdSJack F Vogel 	}
50477d9119bdSJack F Vogel 
50486ab6bfe3SJack F Vogel 	/* For PCH, this write will make sure that any noise
50494edd8523SJack F Vogel 	 * will be detected as a CRC error and be dropped rather than show up
50504edd8523SJack F Vogel 	 * as a bad packet to the DMA engine.
50514edd8523SJack F Vogel 	 */
50524edd8523SJack F Vogel 	if (hw->mac.type == e1000_pchlan)
50534edd8523SJack F Vogel 		E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
50548cfa0ad2SJack F Vogel 
50558cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5056730d3130SJack F Vogel 	E1000_READ_REG(hw, E1000_ICR);
50578cfa0ad2SJack F Vogel 
50586ab6bfe3SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_KABGTXD);
50596ab6bfe3SJack F Vogel 	reg |= E1000_KABGTXD_BGSQLBIAS;
50606ab6bfe3SJack F Vogel 	E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
50618cfa0ad2SJack F Vogel 
50626ab6bfe3SJack F Vogel 	return E1000_SUCCESS;
50638cfa0ad2SJack F Vogel }
50648cfa0ad2SJack F Vogel 
50658cfa0ad2SJack F Vogel /**
50668cfa0ad2SJack F Vogel  *  e1000_init_hw_ich8lan - Initialize the hardware
50678cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
50688cfa0ad2SJack F Vogel  *
50698cfa0ad2SJack F Vogel  *  Prepares the hardware for transmit and receive by doing the following:
50708cfa0ad2SJack F Vogel  *   - initialize hardware bits
50718cfa0ad2SJack F Vogel  *   - initialize LED identification
50728cfa0ad2SJack F Vogel  *   - setup receive address registers
50738cfa0ad2SJack F Vogel  *   - setup flow control
50748cfa0ad2SJack F Vogel  *   - setup transmit descriptors
50758cfa0ad2SJack F Vogel  *   - clear statistics
50768cfa0ad2SJack F Vogel  **/
50778cfa0ad2SJack F Vogel static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
50788cfa0ad2SJack F Vogel {
50798cfa0ad2SJack F Vogel 	struct e1000_mac_info *mac = &hw->mac;
50808cfa0ad2SJack F Vogel 	u32 ctrl_ext, txdctl, snoop;
50818cfa0ad2SJack F Vogel 	s32 ret_val;
50828cfa0ad2SJack F Vogel 	u16 i;
50838cfa0ad2SJack F Vogel 
50848cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_init_hw_ich8lan");
50858cfa0ad2SJack F Vogel 
50868cfa0ad2SJack F Vogel 	e1000_initialize_hw_bits_ich8lan(hw);
50878cfa0ad2SJack F Vogel 
50888cfa0ad2SJack F Vogel 	/* Initialize identification LED */
5089d035aa2dSJack F Vogel 	ret_val = mac->ops.id_led_init(hw);
50906ab6bfe3SJack F Vogel 	/* An error is not fatal and we should not stop init due to this */
5091d035aa2dSJack F Vogel 	if (ret_val)
5092d035aa2dSJack F Vogel 		DEBUGOUT("Error initializing identification LED\n");
50938cfa0ad2SJack F Vogel 
50948cfa0ad2SJack F Vogel 	/* Setup the receive address. */
50958cfa0ad2SJack F Vogel 	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
50968cfa0ad2SJack F Vogel 
50978cfa0ad2SJack F Vogel 	/* Zero out the Multicast HASH table */
50988cfa0ad2SJack F Vogel 	DEBUGOUT("Zeroing the MTA\n");
50998cfa0ad2SJack F Vogel 	for (i = 0; i < mac->mta_reg_count; i++)
51008cfa0ad2SJack F Vogel 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
51018cfa0ad2SJack F Vogel 
51026ab6bfe3SJack F Vogel 	/* The 82578 Rx buffer will stall if wakeup is enabled in host and
51034dab5c37SJack F Vogel 	 * the ME.  Disable wakeup by clearing the host wakeup bit.
51049d81738fSJack F Vogel 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
51059d81738fSJack F Vogel 	 */
51069d81738fSJack F Vogel 	if (hw->phy.type == e1000_phy_82578) {
51074dab5c37SJack F Vogel 		hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
51084dab5c37SJack F Vogel 		i &= ~BM_WUC_HOST_WU_BIT;
51094dab5c37SJack F Vogel 		hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
51109d81738fSJack F Vogel 		ret_val = e1000_phy_hw_reset_ich8lan(hw);
51119d81738fSJack F Vogel 		if (ret_val)
51129d81738fSJack F Vogel 			return ret_val;
51139d81738fSJack F Vogel 	}
51149d81738fSJack F Vogel 
51158cfa0ad2SJack F Vogel 	/* Setup link and flow control */
51168cfa0ad2SJack F Vogel 	ret_val = mac->ops.setup_link(hw);
51178cfa0ad2SJack F Vogel 
51188cfa0ad2SJack F Vogel 	/* Set the transmit descriptor write-back policy for both queues */
51198cfa0ad2SJack F Vogel 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
51207609433eSJack F Vogel 	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
51217609433eSJack F Vogel 		  E1000_TXDCTL_FULL_TX_DESC_WB);
51227609433eSJack F Vogel 	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
51237609433eSJack F Vogel 		  E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
51248cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
51258cfa0ad2SJack F Vogel 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
51267609433eSJack F Vogel 	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
51277609433eSJack F Vogel 		  E1000_TXDCTL_FULL_TX_DESC_WB);
51287609433eSJack F Vogel 	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
51297609433eSJack F Vogel 		  E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
51308cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
51318cfa0ad2SJack F Vogel 
51326ab6bfe3SJack F Vogel 	/* ICH8 has opposite polarity of no_snoop bits.
51338cfa0ad2SJack F Vogel 	 * By default, we should use snoop behavior.
51348cfa0ad2SJack F Vogel 	 */
51358cfa0ad2SJack F Vogel 	if (mac->type == e1000_ich8lan)
51368cfa0ad2SJack F Vogel 		snoop = PCIE_ICH8_SNOOP_ALL;
51378cfa0ad2SJack F Vogel 	else
51388cfa0ad2SJack F Vogel 		snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
51398cfa0ad2SJack F Vogel 	e1000_set_pcie_no_snoop_generic(hw, snoop);
51408cfa0ad2SJack F Vogel 
51418cfa0ad2SJack F Vogel 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
51428cfa0ad2SJack F Vogel 	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
51438cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
51448cfa0ad2SJack F Vogel 
51456ab6bfe3SJack F Vogel 	/* Clear all of the statistics registers (clear on read).  It is
51468cfa0ad2SJack F Vogel 	 * important that we do this after we have tried to establish link
51478cfa0ad2SJack F Vogel 	 * because the symbol error count will increment wildly if there
51488cfa0ad2SJack F Vogel 	 * is no link.
51498cfa0ad2SJack F Vogel 	 */
51508cfa0ad2SJack F Vogel 	e1000_clear_hw_cntrs_ich8lan(hw);
51518cfa0ad2SJack F Vogel 
51528cfa0ad2SJack F Vogel 	return ret_val;
51538cfa0ad2SJack F Vogel }
51546ab6bfe3SJack F Vogel 
51558cfa0ad2SJack F Vogel /**
51568cfa0ad2SJack F Vogel  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
51578cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
51588cfa0ad2SJack F Vogel  *
51598cfa0ad2SJack F Vogel  *  Sets/Clears required hardware bits necessary for correctly setting up the
51608cfa0ad2SJack F Vogel  *  hardware for transmit and receive.
51618cfa0ad2SJack F Vogel  **/
51628cfa0ad2SJack F Vogel static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
51638cfa0ad2SJack F Vogel {
51648cfa0ad2SJack F Vogel 	u32 reg;
51658cfa0ad2SJack F Vogel 
51668cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
51678cfa0ad2SJack F Vogel 
51688cfa0ad2SJack F Vogel 	/* Extended Device Control */
51698cfa0ad2SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
51708cfa0ad2SJack F Vogel 	reg |= (1 << 22);
51719d81738fSJack F Vogel 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
51729d81738fSJack F Vogel 	if (hw->mac.type >= e1000_pchlan)
51739d81738fSJack F Vogel 		reg |= E1000_CTRL_EXT_PHYPDEN;
51748cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
51758cfa0ad2SJack F Vogel 
51768cfa0ad2SJack F Vogel 	/* Transmit Descriptor Control 0 */
51778cfa0ad2SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
51788cfa0ad2SJack F Vogel 	reg |= (1 << 22);
51798cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
51808cfa0ad2SJack F Vogel 
51818cfa0ad2SJack F Vogel 	/* Transmit Descriptor Control 1 */
51828cfa0ad2SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
51838cfa0ad2SJack F Vogel 	reg |= (1 << 22);
51848cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
51858cfa0ad2SJack F Vogel 
51868cfa0ad2SJack F Vogel 	/* Transmit Arbitration Control 0 */
51878cfa0ad2SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_TARC(0));
51888cfa0ad2SJack F Vogel 	if (hw->mac.type == e1000_ich8lan)
51898cfa0ad2SJack F Vogel 		reg |= (1 << 28) | (1 << 29);
51908cfa0ad2SJack F Vogel 	reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
51918cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TARC(0), reg);
51928cfa0ad2SJack F Vogel 
51938cfa0ad2SJack F Vogel 	/* Transmit Arbitration Control 1 */
51948cfa0ad2SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_TARC(1));
51958cfa0ad2SJack F Vogel 	if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
51968cfa0ad2SJack F Vogel 		reg &= ~(1 << 28);
51978cfa0ad2SJack F Vogel 	else
51988cfa0ad2SJack F Vogel 		reg |= (1 << 28);
51998cfa0ad2SJack F Vogel 	reg |= (1 << 24) | (1 << 26) | (1 << 30);
52008cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_TARC(1), reg);
52018cfa0ad2SJack F Vogel 
52028cfa0ad2SJack F Vogel 	/* Device Status */
52038cfa0ad2SJack F Vogel 	if (hw->mac.type == e1000_ich8lan) {
52048cfa0ad2SJack F Vogel 		reg = E1000_READ_REG(hw, E1000_STATUS);
52058cc64f1eSJack F Vogel 		reg &= ~(1 << 31);
52068cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_STATUS, reg);
52078cfa0ad2SJack F Vogel 	}
52088cfa0ad2SJack F Vogel 
52096ab6bfe3SJack F Vogel 	/* work-around descriptor data corruption issue during nfs v2 udp
52108ec87fc5SJack F Vogel 	 * traffic, just disable the nfs filtering capability
52118ec87fc5SJack F Vogel 	 */
52128ec87fc5SJack F Vogel 	reg = E1000_READ_REG(hw, E1000_RFCTL);
52138ec87fc5SJack F Vogel 	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
52147609433eSJack F Vogel 
52156ab6bfe3SJack F Vogel 	/* Disable IPv6 extension header parsing because some malformed
52166ab6bfe3SJack F Vogel 	 * IPv6 headers can hang the Rx.
52176ab6bfe3SJack F Vogel 	 */
52186ab6bfe3SJack F Vogel 	if (hw->mac.type == e1000_ich8lan)
52196ab6bfe3SJack F Vogel 		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
52208ec87fc5SJack F Vogel 	E1000_WRITE_REG(hw, E1000_RFCTL, reg);
52218ec87fc5SJack F Vogel 
52226ab6bfe3SJack F Vogel 	/* Enable ECC on Lynxpoint */
5223295df609SEric Joyner 	if (hw->mac.type >= e1000_pch_lpt) {
52246ab6bfe3SJack F Vogel 		reg = E1000_READ_REG(hw, E1000_PBECCSTS);
52256ab6bfe3SJack F Vogel 		reg |= E1000_PBECCSTS_ECC_ENABLE;
52266ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
52276ab6bfe3SJack F Vogel 
52286ab6bfe3SJack F Vogel 		reg = E1000_READ_REG(hw, E1000_CTRL);
52296ab6bfe3SJack F Vogel 		reg |= E1000_CTRL_MEHE;
52306ab6bfe3SJack F Vogel 		E1000_WRITE_REG(hw, E1000_CTRL, reg);
52316ab6bfe3SJack F Vogel 	}
52326ab6bfe3SJack F Vogel 
52338cfa0ad2SJack F Vogel 	return;
52348cfa0ad2SJack F Vogel }
52358cfa0ad2SJack F Vogel 
52368cfa0ad2SJack F Vogel /**
52378cfa0ad2SJack F Vogel  *  e1000_setup_link_ich8lan - Setup flow control and link settings
52388cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
52398cfa0ad2SJack F Vogel  *
52408cfa0ad2SJack F Vogel  *  Determines which flow control settings to use, then configures flow
52418cfa0ad2SJack F Vogel  *  control.  Calls the appropriate media-specific link configuration
52428cfa0ad2SJack F Vogel  *  function.  Assuming the adapter has a valid link partner, a valid link
52438cfa0ad2SJack F Vogel  *  should be established.  Assumes the hardware has previously been reset
52448cfa0ad2SJack F Vogel  *  and the transmitter and receiver are not enabled.
52458cfa0ad2SJack F Vogel  **/
52468cfa0ad2SJack F Vogel static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
52478cfa0ad2SJack F Vogel {
52486ab6bfe3SJack F Vogel 	s32 ret_val;
52498cfa0ad2SJack F Vogel 
52508cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_setup_link_ich8lan");
52518cfa0ad2SJack F Vogel 
52528cfa0ad2SJack F Vogel 	if (hw->phy.ops.check_reset_block(hw))
52536ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
52548cfa0ad2SJack F Vogel 
52556ab6bfe3SJack F Vogel 	/* ICH parts do not have a word in the NVM to determine
52568cfa0ad2SJack F Vogel 	 * the default flow control setting, so we explicitly
52578cfa0ad2SJack F Vogel 	 * set it to full.
52588cfa0ad2SJack F Vogel 	 */
5259daf9197cSJack F Vogel 	if (hw->fc.requested_mode == e1000_fc_default)
5260daf9197cSJack F Vogel 		hw->fc.requested_mode = e1000_fc_full;
52618cfa0ad2SJack F Vogel 
52626ab6bfe3SJack F Vogel 	/* Save off the requested flow control mode for use later.  Depending
5263daf9197cSJack F Vogel 	 * on the link partner's capabilities, we may or may not use this mode.
5264daf9197cSJack F Vogel 	 */
5265daf9197cSJack F Vogel 	hw->fc.current_mode = hw->fc.requested_mode;
52668cfa0ad2SJack F Vogel 
5267daf9197cSJack F Vogel 	DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5268daf9197cSJack F Vogel 		hw->fc.current_mode);
52698cfa0ad2SJack F Vogel 
52708cfa0ad2SJack F Vogel 	/* Continue to configure the copper link. */
52718cfa0ad2SJack F Vogel 	ret_val = hw->mac.ops.setup_physical_interface(hw);
52728cfa0ad2SJack F Vogel 	if (ret_val)
52736ab6bfe3SJack F Vogel 		return ret_val;
52748cfa0ad2SJack F Vogel 
52758cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
52769d81738fSJack F Vogel 	if ((hw->phy.type == e1000_phy_82578) ||
52777d9119bdSJack F Vogel 	    (hw->phy.type == e1000_phy_82579) ||
52786ab6bfe3SJack F Vogel 	    (hw->phy.type == e1000_phy_i217) ||
52799d81738fSJack F Vogel 	    (hw->phy.type == e1000_phy_82577)) {
52807d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
52817d9119bdSJack F Vogel 
52829d81738fSJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw,
52839d81738fSJack F Vogel 					     PHY_REG(BM_PORT_CTRL_PAGE, 27),
52849d81738fSJack F Vogel 					     hw->fc.pause_time);
52859d81738fSJack F Vogel 		if (ret_val)
52866ab6bfe3SJack F Vogel 			return ret_val;
52879d81738fSJack F Vogel 	}
52888cfa0ad2SJack F Vogel 
52896ab6bfe3SJack F Vogel 	return e1000_set_fc_watermarks_generic(hw);
52908cfa0ad2SJack F Vogel }
52918cfa0ad2SJack F Vogel 
52928cfa0ad2SJack F Vogel /**
52938cfa0ad2SJack F Vogel  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
52948cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
52958cfa0ad2SJack F Vogel  *
52968cfa0ad2SJack F Vogel  *  Configures the kumeran interface to the PHY to wait the appropriate time
52978cfa0ad2SJack F Vogel  *  when polling the PHY, then call the generic setup_copper_link to finish
52988cfa0ad2SJack F Vogel  *  configuring the copper link.
52998cfa0ad2SJack F Vogel  **/
53008cfa0ad2SJack F Vogel static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
53018cfa0ad2SJack F Vogel {
53028cfa0ad2SJack F Vogel 	u32 ctrl;
53038cfa0ad2SJack F Vogel 	s32 ret_val;
53048cfa0ad2SJack F Vogel 	u16 reg_data;
53058cfa0ad2SJack F Vogel 
53068cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_setup_copper_link_ich8lan");
53078cfa0ad2SJack F Vogel 
53088cfa0ad2SJack F Vogel 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
53098cfa0ad2SJack F Vogel 	ctrl |= E1000_CTRL_SLU;
53108cfa0ad2SJack F Vogel 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
53118cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
53128cfa0ad2SJack F Vogel 
53136ab6bfe3SJack F Vogel 	/* Set the mac to wait the maximum time between each iteration
53148cfa0ad2SJack F Vogel 	 * and increase the max iterations when polling the phy;
53158cfa0ad2SJack F Vogel 	 * this fixes erroneous timeouts at 10Mbps.
53168cfa0ad2SJack F Vogel 	 */
53174edd8523SJack F Vogel 	ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
53188cfa0ad2SJack F Vogel 					       0xFFFF);
53198cfa0ad2SJack F Vogel 	if (ret_val)
53206ab6bfe3SJack F Vogel 		return ret_val;
53219d81738fSJack F Vogel 	ret_val = e1000_read_kmrn_reg_generic(hw,
53229d81738fSJack F Vogel 					      E1000_KMRNCTRLSTA_INBAND_PARAM,
53238cfa0ad2SJack F Vogel 					      &reg_data);
53248cfa0ad2SJack F Vogel 	if (ret_val)
53256ab6bfe3SJack F Vogel 		return ret_val;
53268cfa0ad2SJack F Vogel 	reg_data |= 0x3F;
53279d81738fSJack F Vogel 	ret_val = e1000_write_kmrn_reg_generic(hw,
53289d81738fSJack F Vogel 					       E1000_KMRNCTRLSTA_INBAND_PARAM,
53298cfa0ad2SJack F Vogel 					       reg_data);
53308cfa0ad2SJack F Vogel 	if (ret_val)
53316ab6bfe3SJack F Vogel 		return ret_val;
53328cfa0ad2SJack F Vogel 
5333d035aa2dSJack F Vogel 	switch (hw->phy.type) {
5334d035aa2dSJack F Vogel 	case e1000_phy_igp_3:
53358cfa0ad2SJack F Vogel 		ret_val = e1000_copper_link_setup_igp(hw);
53368cfa0ad2SJack F Vogel 		if (ret_val)
53376ab6bfe3SJack F Vogel 			return ret_val;
5338d035aa2dSJack F Vogel 		break;
5339d035aa2dSJack F Vogel 	case e1000_phy_bm:
53409d81738fSJack F Vogel 	case e1000_phy_82578:
53418cfa0ad2SJack F Vogel 		ret_val = e1000_copper_link_setup_m88(hw);
53428cfa0ad2SJack F Vogel 		if (ret_val)
53436ab6bfe3SJack F Vogel 			return ret_val;
5344d035aa2dSJack F Vogel 		break;
53459d81738fSJack F Vogel 	case e1000_phy_82577:
53467d9119bdSJack F Vogel 	case e1000_phy_82579:
53479d81738fSJack F Vogel 		ret_val = e1000_copper_link_setup_82577(hw);
53489d81738fSJack F Vogel 		if (ret_val)
53496ab6bfe3SJack F Vogel 			return ret_val;
53509d81738fSJack F Vogel 		break;
5351d035aa2dSJack F Vogel 	case e1000_phy_ife:
53528cfa0ad2SJack F Vogel 		ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
53538cfa0ad2SJack F Vogel 					       &reg_data);
53548cfa0ad2SJack F Vogel 		if (ret_val)
53556ab6bfe3SJack F Vogel 			return ret_val;
53568cfa0ad2SJack F Vogel 
53578cfa0ad2SJack F Vogel 		reg_data &= ~IFE_PMC_AUTO_MDIX;
53588cfa0ad2SJack F Vogel 
53598cfa0ad2SJack F Vogel 		switch (hw->phy.mdix) {
53608cfa0ad2SJack F Vogel 		case 1:
53618cfa0ad2SJack F Vogel 			reg_data &= ~IFE_PMC_FORCE_MDIX;
53628cfa0ad2SJack F Vogel 			break;
53638cfa0ad2SJack F Vogel 		case 2:
53648cfa0ad2SJack F Vogel 			reg_data |= IFE_PMC_FORCE_MDIX;
53658cfa0ad2SJack F Vogel 			break;
53668cfa0ad2SJack F Vogel 		case 0:
53678cfa0ad2SJack F Vogel 		default:
53688cfa0ad2SJack F Vogel 			reg_data |= IFE_PMC_AUTO_MDIX;
53698cfa0ad2SJack F Vogel 			break;
53708cfa0ad2SJack F Vogel 		}
53718cfa0ad2SJack F Vogel 		ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
53728cfa0ad2SJack F Vogel 						reg_data);
53738cfa0ad2SJack F Vogel 		if (ret_val)
53746ab6bfe3SJack F Vogel 			return ret_val;
5375d035aa2dSJack F Vogel 		break;
5376d035aa2dSJack F Vogel 	default:
5377d035aa2dSJack F Vogel 		break;
53788cfa0ad2SJack F Vogel 	}
53798cfa0ad2SJack F Vogel 
53806ab6bfe3SJack F Vogel 	return e1000_setup_copper_link_generic(hw);
53816ab6bfe3SJack F Vogel }
53826ab6bfe3SJack F Vogel 
53836ab6bfe3SJack F Vogel /**
53846ab6bfe3SJack F Vogel  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
53856ab6bfe3SJack F Vogel  *  @hw: pointer to the HW structure
53866ab6bfe3SJack F Vogel  *
53876ab6bfe3SJack F Vogel  *  Calls the PHY specific link setup function and then calls the
53886ab6bfe3SJack F Vogel  *  generic setup_copper_link to finish configuring the link for
53896ab6bfe3SJack F Vogel  *  Lynxpoint PCH devices
53906ab6bfe3SJack F Vogel  **/
53916ab6bfe3SJack F Vogel static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
53926ab6bfe3SJack F Vogel {
53936ab6bfe3SJack F Vogel 	u32 ctrl;
53946ab6bfe3SJack F Vogel 	s32 ret_val;
53956ab6bfe3SJack F Vogel 
53966ab6bfe3SJack F Vogel 	DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
53976ab6bfe3SJack F Vogel 
53986ab6bfe3SJack F Vogel 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
53996ab6bfe3SJack F Vogel 	ctrl |= E1000_CTRL_SLU;
54006ab6bfe3SJack F Vogel 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
54016ab6bfe3SJack F Vogel 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
54026ab6bfe3SJack F Vogel 
54036ab6bfe3SJack F Vogel 	ret_val = e1000_copper_link_setup_82577(hw);
54046ab6bfe3SJack F Vogel 	if (ret_val)
54058cfa0ad2SJack F Vogel 		return ret_val;
54066ab6bfe3SJack F Vogel 
54076ab6bfe3SJack F Vogel 	return e1000_setup_copper_link_generic(hw);
54088cfa0ad2SJack F Vogel }
54098cfa0ad2SJack F Vogel 
54108cfa0ad2SJack F Vogel /**
54118cfa0ad2SJack F Vogel  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
54128cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
54138cfa0ad2SJack F Vogel  *  @speed: pointer to store current link speed
54148cfa0ad2SJack F Vogel  *  @duplex: pointer to store the current link duplex
54158cfa0ad2SJack F Vogel  *
54168cfa0ad2SJack F Vogel  *  Calls the generic get_speed_and_duplex to retrieve the current link
54178cfa0ad2SJack F Vogel  *  information and then calls the Kumeran lock loss workaround for links at
54188cfa0ad2SJack F Vogel  *  gigabit speeds.
54198cfa0ad2SJack F Vogel  **/
54208cfa0ad2SJack F Vogel static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
54218cfa0ad2SJack F Vogel 					  u16 *duplex)
54228cfa0ad2SJack F Vogel {
54238cfa0ad2SJack F Vogel 	s32 ret_val;
54248cfa0ad2SJack F Vogel 
54258cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_get_link_up_info_ich8lan");
54268cfa0ad2SJack F Vogel 
54278cfa0ad2SJack F Vogel 	ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
54288cfa0ad2SJack F Vogel 	if (ret_val)
54296ab6bfe3SJack F Vogel 		return ret_val;
54308cfa0ad2SJack F Vogel 
54318cfa0ad2SJack F Vogel 	if ((hw->mac.type == e1000_ich8lan) &&
54328cfa0ad2SJack F Vogel 	    (hw->phy.type == e1000_phy_igp_3) &&
54338cfa0ad2SJack F Vogel 	    (*speed == SPEED_1000)) {
54348cfa0ad2SJack F Vogel 		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
54358cfa0ad2SJack F Vogel 	}
54368cfa0ad2SJack F Vogel 
54378cfa0ad2SJack F Vogel 	return ret_val;
54388cfa0ad2SJack F Vogel }
54398cfa0ad2SJack F Vogel 
54408cfa0ad2SJack F Vogel /**
54418cfa0ad2SJack F Vogel  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
54428cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
54438cfa0ad2SJack F Vogel  *
54448cfa0ad2SJack F Vogel  *  Work-around for 82566 Kumeran PCS lock loss:
54458cfa0ad2SJack F Vogel  *  On link status change (i.e. PCI reset, speed change) and link is up and
54468cfa0ad2SJack F Vogel  *  speed is gigabit-
54478cfa0ad2SJack F Vogel  *    0) if workaround is optionally disabled do nothing
54488cfa0ad2SJack F Vogel  *    1) wait 1ms for Kumeran link to come up
54498cfa0ad2SJack F Vogel  *    2) check Kumeran Diagnostic register PCS lock loss bit
54508cfa0ad2SJack F Vogel  *    3) if not set the link is locked (all is good), otherwise...
54518cfa0ad2SJack F Vogel  *    4) reset the PHY
54528cfa0ad2SJack F Vogel  *    5) repeat up to 10 times
54538cfa0ad2SJack F Vogel  *  Note: this is only called for IGP3 copper when speed is 1gb.
54548cfa0ad2SJack F Vogel  **/
54558cfa0ad2SJack F Vogel static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
54568cfa0ad2SJack F Vogel {
5457daf9197cSJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
54588cfa0ad2SJack F Vogel 	u32 phy_ctrl;
54596ab6bfe3SJack F Vogel 	s32 ret_val;
54608cfa0ad2SJack F Vogel 	u16 i, data;
54618cfa0ad2SJack F Vogel 	bool link;
54628cfa0ad2SJack F Vogel 
54638cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
54648cfa0ad2SJack F Vogel 
5465730d3130SJack F Vogel 	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
54666ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
54678cfa0ad2SJack F Vogel 
54686ab6bfe3SJack F Vogel 	/* Make sure link is up before proceeding.  If not just return.
54698cfa0ad2SJack F Vogel 	 * Attempting this while link is negotiating fouled up link
54708cfa0ad2SJack F Vogel 	 * stability
54718cfa0ad2SJack F Vogel 	 */
54728cfa0ad2SJack F Vogel 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
54736ab6bfe3SJack F Vogel 	if (!link)
54746ab6bfe3SJack F Vogel 		return E1000_SUCCESS;
54758cfa0ad2SJack F Vogel 
54768cfa0ad2SJack F Vogel 	for (i = 0; i < 10; i++) {
54778cfa0ad2SJack F Vogel 		/* read once to clear */
54788cfa0ad2SJack F Vogel 		ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
54798cfa0ad2SJack F Vogel 		if (ret_val)
54806ab6bfe3SJack F Vogel 			return ret_val;
54818cfa0ad2SJack F Vogel 		/* and again to get new status */
54828cfa0ad2SJack F Vogel 		ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
54838cfa0ad2SJack F Vogel 		if (ret_val)
54846ab6bfe3SJack F Vogel 			return ret_val;
54858cfa0ad2SJack F Vogel 
54868cfa0ad2SJack F Vogel 		/* check for PCS lock */
54876ab6bfe3SJack F Vogel 		if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
54886ab6bfe3SJack F Vogel 			return E1000_SUCCESS;
54898cfa0ad2SJack F Vogel 
54908cfa0ad2SJack F Vogel 		/* Issue PHY reset */
54918cfa0ad2SJack F Vogel 		hw->phy.ops.reset(hw);
54928cfa0ad2SJack F Vogel 		msec_delay_irq(5);
54938cfa0ad2SJack F Vogel 	}
54948cfa0ad2SJack F Vogel 	/* Disable GigE link negotiation */
54958cfa0ad2SJack F Vogel 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
54968cfa0ad2SJack F Vogel 	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
54978cfa0ad2SJack F Vogel 		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
54988cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
54998cfa0ad2SJack F Vogel 
55006ab6bfe3SJack F Vogel 	/* Call gig speed drop workaround on Gig disable before accessing
55018cfa0ad2SJack F Vogel 	 * any PHY registers
55028cfa0ad2SJack F Vogel 	 */
55038cfa0ad2SJack F Vogel 	e1000_gig_downshift_workaround_ich8lan(hw);
55048cfa0ad2SJack F Vogel 
55058cfa0ad2SJack F Vogel 	/* unable to acquire PCS lock */
55066ab6bfe3SJack F Vogel 	return -E1000_ERR_PHY;
55078cfa0ad2SJack F Vogel }
55088cfa0ad2SJack F Vogel 
55098cfa0ad2SJack F Vogel /**
55108cfa0ad2SJack F Vogel  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
55118cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
55128cfa0ad2SJack F Vogel  *  @state: boolean value used to set the current Kumeran workaround state
55138cfa0ad2SJack F Vogel  *
55148cfa0ad2SJack F Vogel  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
55158cfa0ad2SJack F Vogel  *  /disabled - FALSE).
55168cfa0ad2SJack F Vogel  **/
55178cfa0ad2SJack F Vogel void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
55188cfa0ad2SJack F Vogel 						 bool state)
55198cfa0ad2SJack F Vogel {
5520daf9197cSJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
55218cfa0ad2SJack F Vogel 
55228cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
55238cfa0ad2SJack F Vogel 
55248cfa0ad2SJack F Vogel 	if (hw->mac.type != e1000_ich8lan) {
55258cfa0ad2SJack F Vogel 		DEBUGOUT("Workaround applies to ICH8 only.\n");
5526daf9197cSJack F Vogel 		return;
55278cfa0ad2SJack F Vogel 	}
55288cfa0ad2SJack F Vogel 
55298cfa0ad2SJack F Vogel 	dev_spec->kmrn_lock_loss_workaround_enabled = state;
55308cfa0ad2SJack F Vogel 
55318cfa0ad2SJack F Vogel 	return;
55328cfa0ad2SJack F Vogel }
55338cfa0ad2SJack F Vogel 
55348cfa0ad2SJack F Vogel /**
55358cfa0ad2SJack F Vogel  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
55368cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
55378cfa0ad2SJack F Vogel  *
55388cfa0ad2SJack F Vogel  *  Workaround for 82566 power-down on D3 entry:
55398cfa0ad2SJack F Vogel  *    1) disable gigabit link
55408cfa0ad2SJack F Vogel  *    2) write VR power-down enable
55418cfa0ad2SJack F Vogel  *    3) read it back
55428cfa0ad2SJack F Vogel  *  Continue if successful, else issue LCD reset and repeat
55438cfa0ad2SJack F Vogel  **/
55448cfa0ad2SJack F Vogel void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
55458cfa0ad2SJack F Vogel {
55468cfa0ad2SJack F Vogel 	u32 reg;
55478cfa0ad2SJack F Vogel 	u16 data;
55488cfa0ad2SJack F Vogel 	u8  retry = 0;
55498cfa0ad2SJack F Vogel 
55508cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
55518cfa0ad2SJack F Vogel 
55528cfa0ad2SJack F Vogel 	if (hw->phy.type != e1000_phy_igp_3)
55536ab6bfe3SJack F Vogel 		return;
55548cfa0ad2SJack F Vogel 
55558cfa0ad2SJack F Vogel 	/* Try the workaround twice (if needed) */
55568cfa0ad2SJack F Vogel 	do {
55578cfa0ad2SJack F Vogel 		/* Disable link */
55588cfa0ad2SJack F Vogel 		reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
55598cfa0ad2SJack F Vogel 		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
55608cfa0ad2SJack F Vogel 			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
55618cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
55628cfa0ad2SJack F Vogel 
55636ab6bfe3SJack F Vogel 		/* Call gig speed drop workaround on Gig disable before
55648cfa0ad2SJack F Vogel 		 * accessing any PHY registers
55658cfa0ad2SJack F Vogel 		 */
55668cfa0ad2SJack F Vogel 		if (hw->mac.type == e1000_ich8lan)
55678cfa0ad2SJack F Vogel 			e1000_gig_downshift_workaround_ich8lan(hw);
55688cfa0ad2SJack F Vogel 
55698cfa0ad2SJack F Vogel 		/* Write VR power-down enable */
55708cfa0ad2SJack F Vogel 		hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
55718cfa0ad2SJack F Vogel 		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5572daf9197cSJack F Vogel 		hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
55738cfa0ad2SJack F Vogel 				      data | IGP3_VR_CTRL_MODE_SHUTDOWN);
55748cfa0ad2SJack F Vogel 
55758cfa0ad2SJack F Vogel 		/* Read it back and test */
55768cfa0ad2SJack F Vogel 		hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
55778cfa0ad2SJack F Vogel 		data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
55788cfa0ad2SJack F Vogel 		if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
55798cfa0ad2SJack F Vogel 			break;
55808cfa0ad2SJack F Vogel 
55818cfa0ad2SJack F Vogel 		/* Issue PHY reset and repeat at most one more time */
55828cfa0ad2SJack F Vogel 		reg = E1000_READ_REG(hw, E1000_CTRL);
55838cfa0ad2SJack F Vogel 		E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
55848cfa0ad2SJack F Vogel 		retry++;
55858cfa0ad2SJack F Vogel 	} while (retry);
55868cfa0ad2SJack F Vogel }
55878cfa0ad2SJack F Vogel 
55888cfa0ad2SJack F Vogel /**
55898cfa0ad2SJack F Vogel  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
55908cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
55918cfa0ad2SJack F Vogel  *
55928cfa0ad2SJack F Vogel  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
55938cfa0ad2SJack F Vogel  *  LPLU, Gig disable, MDIC PHY reset):
55948cfa0ad2SJack F Vogel  *    1) Set Kumeran Near-end loopback
55958cfa0ad2SJack F Vogel  *    2) Clear Kumeran Near-end loopback
55964dab5c37SJack F Vogel  *  Should only be called for ICH8[m] devices with any 1G Phy.
55978cfa0ad2SJack F Vogel  **/
55988cfa0ad2SJack F Vogel void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
55998cfa0ad2SJack F Vogel {
56006ab6bfe3SJack F Vogel 	s32 ret_val;
56018cfa0ad2SJack F Vogel 	u16 reg_data;
56028cfa0ad2SJack F Vogel 
56038cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
56048cfa0ad2SJack F Vogel 
56058cfa0ad2SJack F Vogel 	if ((hw->mac.type != e1000_ich8lan) ||
56064dab5c37SJack F Vogel 	    (hw->phy.type == e1000_phy_ife))
56076ab6bfe3SJack F Vogel 		return;
56088cfa0ad2SJack F Vogel 
56098cfa0ad2SJack F Vogel 	ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
56108cfa0ad2SJack F Vogel 					      &reg_data);
56118cfa0ad2SJack F Vogel 	if (ret_val)
56126ab6bfe3SJack F Vogel 		return;
56138cfa0ad2SJack F Vogel 	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
56148cfa0ad2SJack F Vogel 	ret_val = e1000_write_kmrn_reg_generic(hw,
56158cfa0ad2SJack F Vogel 					       E1000_KMRNCTRLSTA_DIAG_OFFSET,
56168cfa0ad2SJack F Vogel 					       reg_data);
56178cfa0ad2SJack F Vogel 	if (ret_val)
56188cfa0ad2SJack F Vogel 		return;
56196ab6bfe3SJack F Vogel 	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
56206ab6bfe3SJack F Vogel 	e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
56216ab6bfe3SJack F Vogel 				     reg_data);
56228cfa0ad2SJack F Vogel }
56238cfa0ad2SJack F Vogel 
56248cfa0ad2SJack F Vogel /**
56254dab5c37SJack F Vogel  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
56268cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
56278cfa0ad2SJack F Vogel  *
56288cfa0ad2SJack F Vogel  *  During S0 to Sx transition, it is possible the link remains at gig
56298cfa0ad2SJack F Vogel  *  instead of negotiating to a lower speed.  Before going to Sx, set
56304dab5c37SJack F Vogel  *  'Gig Disable' to force link speed negotiation to a lower speed based on
56314dab5c37SJack F Vogel  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
56324dab5c37SJack F Vogel  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
56334dab5c37SJack F Vogel  *  needs to be written.
56346ab6bfe3SJack F Vogel  *  Parts that support (and are linked to a partner which support) EEE in
56356ab6bfe3SJack F Vogel  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
56366ab6bfe3SJack F Vogel  *  than 10Mbps w/o EEE.
56378cfa0ad2SJack F Vogel  **/
56384dab5c37SJack F Vogel void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
56398cfa0ad2SJack F Vogel {
56406ab6bfe3SJack F Vogel 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
56418cfa0ad2SJack F Vogel 	u32 phy_ctrl;
56427d9119bdSJack F Vogel 	s32 ret_val;
56438cfa0ad2SJack F Vogel 
56444dab5c37SJack F Vogel 	DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
56457d9119bdSJack F Vogel 
56468cfa0ad2SJack F Vogel 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
56474dab5c37SJack F Vogel 	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
56486ab6bfe3SJack F Vogel 
56496ab6bfe3SJack F Vogel 	if (hw->phy.type == e1000_phy_i217) {
56506ab6bfe3SJack F Vogel 		u16 phy_reg, device_id = hw->device_id;
56516ab6bfe3SJack F Vogel 
56526ab6bfe3SJack F Vogel 		if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
56538cc64f1eSJack F Vogel 		    (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
56548cc64f1eSJack F Vogel 		    (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5655c80429ceSEric Joyner 		    (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5656295df609SEric Joyner 		    (hw->mac.type >= e1000_pch_spt)) {
56576ab6bfe3SJack F Vogel 			u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
56586ab6bfe3SJack F Vogel 
56596ab6bfe3SJack F Vogel 			E1000_WRITE_REG(hw, E1000_FEXTNVM6,
56606ab6bfe3SJack F Vogel 					fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
56616ab6bfe3SJack F Vogel 		}
56626ab6bfe3SJack F Vogel 
56636ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
56646ab6bfe3SJack F Vogel 		if (ret_val)
56656ab6bfe3SJack F Vogel 			goto out;
56666ab6bfe3SJack F Vogel 
56676ab6bfe3SJack F Vogel 		if (!dev_spec->eee_disable) {
56686ab6bfe3SJack F Vogel 			u16 eee_advert;
56696ab6bfe3SJack F Vogel 
56706ab6bfe3SJack F Vogel 			ret_val =
56716ab6bfe3SJack F Vogel 			    e1000_read_emi_reg_locked(hw,
56726ab6bfe3SJack F Vogel 						      I217_EEE_ADVERTISEMENT,
56736ab6bfe3SJack F Vogel 						      &eee_advert);
56746ab6bfe3SJack F Vogel 			if (ret_val)
56756ab6bfe3SJack F Vogel 				goto release;
56766ab6bfe3SJack F Vogel 
56776ab6bfe3SJack F Vogel 			/* Disable LPLU if both link partners support 100BaseT
56786ab6bfe3SJack F Vogel 			 * EEE and 100Full is advertised on both ends of the
56797609433eSJack F Vogel 			 * link, and enable Auto Enable LPI since there will
56807609433eSJack F Vogel 			 * be no driver to enable LPI while in Sx.
56816ab6bfe3SJack F Vogel 			 */
56826ab6bfe3SJack F Vogel 			if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
56836ab6bfe3SJack F Vogel 			    (dev_spec->eee_lp_ability &
56846ab6bfe3SJack F Vogel 			     I82579_EEE_100_SUPPORTED) &&
56857609433eSJack F Vogel 			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
56866ab6bfe3SJack F Vogel 				phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
56876ab6bfe3SJack F Vogel 					      E1000_PHY_CTRL_NOND0A_LPLU);
56887609433eSJack F Vogel 
56897609433eSJack F Vogel 				/* Set Auto Enable LPI after link up */
56907609433eSJack F Vogel 				hw->phy.ops.read_reg_locked(hw,
56917609433eSJack F Vogel 							    I217_LPI_GPIO_CTRL,
56927609433eSJack F Vogel 							    &phy_reg);
56937609433eSJack F Vogel 				phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
56947609433eSJack F Vogel 				hw->phy.ops.write_reg_locked(hw,
56957609433eSJack F Vogel 							     I217_LPI_GPIO_CTRL,
56967609433eSJack F Vogel 							     phy_reg);
56977609433eSJack F Vogel 			}
56986ab6bfe3SJack F Vogel 		}
56996ab6bfe3SJack F Vogel 
57006ab6bfe3SJack F Vogel 		/* For i217 Intel Rapid Start Technology support,
57016ab6bfe3SJack F Vogel 		 * when the system is going into Sx and no manageability engine
57026ab6bfe3SJack F Vogel 		 * is present, the driver must configure proxy to reset only on
57036ab6bfe3SJack F Vogel 		 * power good.  LPI (Low Power Idle) state must also reset only
57046ab6bfe3SJack F Vogel 		 * on power good, as well as the MTA (Multicast table array).
57056ab6bfe3SJack F Vogel 		 * The SMBus release must also be disabled on LCD reset.
57066ab6bfe3SJack F Vogel 		 */
57076ab6bfe3SJack F Vogel 		if (!(E1000_READ_REG(hw, E1000_FWSM) &
57086ab6bfe3SJack F Vogel 		      E1000_ICH_FWSM_FW_VALID)) {
57096ab6bfe3SJack F Vogel 			/* Enable proxy to reset only on power good. */
57106ab6bfe3SJack F Vogel 			hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
57116ab6bfe3SJack F Vogel 						    &phy_reg);
57126ab6bfe3SJack F Vogel 			phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
57136ab6bfe3SJack F Vogel 			hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
57146ab6bfe3SJack F Vogel 						     phy_reg);
57156ab6bfe3SJack F Vogel 
57166ab6bfe3SJack F Vogel 			/* Set bit enable LPI (EEE) to reset only on
57176ab6bfe3SJack F Vogel 			 * power good.
57186ab6bfe3SJack F Vogel 			*/
57196ab6bfe3SJack F Vogel 			hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
57206ab6bfe3SJack F Vogel 			phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
57216ab6bfe3SJack F Vogel 			hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
57226ab6bfe3SJack F Vogel 
57236ab6bfe3SJack F Vogel 			/* Disable the SMB release on LCD reset. */
57246ab6bfe3SJack F Vogel 			hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
57256ab6bfe3SJack F Vogel 			phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
57266ab6bfe3SJack F Vogel 			hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
57276ab6bfe3SJack F Vogel 		}
57286ab6bfe3SJack F Vogel 
57296ab6bfe3SJack F Vogel 		/* Enable MTA to reset for Intel Rapid Start Technology
57306ab6bfe3SJack F Vogel 		 * Support
57316ab6bfe3SJack F Vogel 		 */
57326ab6bfe3SJack F Vogel 		hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
57336ab6bfe3SJack F Vogel 		phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
57346ab6bfe3SJack F Vogel 		hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
57356ab6bfe3SJack F Vogel 
57366ab6bfe3SJack F Vogel release:
57376ab6bfe3SJack F Vogel 		hw->phy.ops.release(hw);
57386ab6bfe3SJack F Vogel 	}
57396ab6bfe3SJack F Vogel out:
57408cfa0ad2SJack F Vogel 	E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
57416ab6bfe3SJack F Vogel 
57424dab5c37SJack F Vogel 	if (hw->mac.type == e1000_ich8lan)
57434dab5c37SJack F Vogel 		e1000_gig_downshift_workaround_ich8lan(hw);
57449d81738fSJack F Vogel 
57457d9119bdSJack F Vogel 	if (hw->mac.type >= e1000_pchlan) {
57467d9119bdSJack F Vogel 		e1000_oem_bits_config_ich8lan(hw, FALSE);
57476ab6bfe3SJack F Vogel 
57486ab6bfe3SJack F Vogel 		/* Reset PHY to activate OEM bits on 82577/8 */
57496ab6bfe3SJack F Vogel 		if (hw->mac.type == e1000_pchlan)
57506ab6bfe3SJack F Vogel 			e1000_phy_hw_reset_generic(hw);
57516ab6bfe3SJack F Vogel 
57527d9119bdSJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
57537d9119bdSJack F Vogel 		if (ret_val)
57547d9119bdSJack F Vogel 			return;
57557d9119bdSJack F Vogel 		e1000_write_smbus_addr(hw);
57567d9119bdSJack F Vogel 		hw->phy.ops.release(hw);
57578cfa0ad2SJack F Vogel 	}
57588cfa0ad2SJack F Vogel 
57598cfa0ad2SJack F Vogel 	return;
57608cfa0ad2SJack F Vogel }
57618cfa0ad2SJack F Vogel 
57628cfa0ad2SJack F Vogel /**
57634dab5c37SJack F Vogel  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
57644dab5c37SJack F Vogel  *  @hw: pointer to the HW structure
57654dab5c37SJack F Vogel  *
57664dab5c37SJack F Vogel  *  During Sx to S0 transitions on non-managed devices or managed devices
57674dab5c37SJack F Vogel  *  on which PHY resets are not blocked, if the PHY registers cannot be
57684dab5c37SJack F Vogel  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
57694dab5c37SJack F Vogel  *  the PHY.
57706ab6bfe3SJack F Vogel  *  On i217, setup Intel Rapid Start Technology.
57714dab5c37SJack F Vogel  **/
5772c80429ceSEric Joyner u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
57734dab5c37SJack F Vogel {
57744dab5c37SJack F Vogel 	s32 ret_val;
57754dab5c37SJack F Vogel 
57764dab5c37SJack F Vogel 	DEBUGFUNC("e1000_resume_workarounds_pchlan");
57776ab6bfe3SJack F Vogel 	if (hw->mac.type < e1000_pch2lan)
5778c80429ceSEric Joyner 		return E1000_SUCCESS;
57794dab5c37SJack F Vogel 
57806ab6bfe3SJack F Vogel 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
57814dab5c37SJack F Vogel 	if (ret_val) {
57826ab6bfe3SJack F Vogel 		DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5783c80429ceSEric Joyner 		return ret_val;
57844dab5c37SJack F Vogel 	}
57854dab5c37SJack F Vogel 
57866ab6bfe3SJack F Vogel 	/* For i217 Intel Rapid Start Technology support when the system
57876ab6bfe3SJack F Vogel 	 * is transitioning from Sx and no manageability engine is present
57886ab6bfe3SJack F Vogel 	 * configure SMBus to restore on reset, disable proxy, and enable
57896ab6bfe3SJack F Vogel 	 * the reset on MTA (Multicast table array).
57906ab6bfe3SJack F Vogel 	 */
57916ab6bfe3SJack F Vogel 	if (hw->phy.type == e1000_phy_i217) {
57926ab6bfe3SJack F Vogel 		u16 phy_reg;
57934dab5c37SJack F Vogel 
57946ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
57956ab6bfe3SJack F Vogel 		if (ret_val) {
57966ab6bfe3SJack F Vogel 			DEBUGOUT("Failed to setup iRST\n");
5797c80429ceSEric Joyner 			return ret_val;
57986ab6bfe3SJack F Vogel 		}
57994dab5c37SJack F Vogel 
58007609433eSJack F Vogel 		/* Clear Auto Enable LPI after link up */
58017609433eSJack F Vogel 		hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
58027609433eSJack F Vogel 		phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
58037609433eSJack F Vogel 		hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
58047609433eSJack F Vogel 
58056ab6bfe3SJack F Vogel 		if (!(E1000_READ_REG(hw, E1000_FWSM) &
58066ab6bfe3SJack F Vogel 		    E1000_ICH_FWSM_FW_VALID)) {
58076ab6bfe3SJack F Vogel 			/* Restore clear on SMB if no manageability engine
58086ab6bfe3SJack F Vogel 			 * is present
58096ab6bfe3SJack F Vogel 			 */
58106ab6bfe3SJack F Vogel 			ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
58116ab6bfe3SJack F Vogel 							      &phy_reg);
58126ab6bfe3SJack F Vogel 			if (ret_val)
58136ab6bfe3SJack F Vogel 				goto release;
58146ab6bfe3SJack F Vogel 			phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
58156ab6bfe3SJack F Vogel 			hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
58166ab6bfe3SJack F Vogel 
58176ab6bfe3SJack F Vogel 			/* Disable Proxy */
58186ab6bfe3SJack F Vogel 			hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
58196ab6bfe3SJack F Vogel 		}
58206ab6bfe3SJack F Vogel 		/* Enable reset on MTA */
58216ab6bfe3SJack F Vogel 		ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
58226ab6bfe3SJack F Vogel 						      &phy_reg);
58236ab6bfe3SJack F Vogel 		if (ret_val)
58246ab6bfe3SJack F Vogel 			goto release;
58256ab6bfe3SJack F Vogel 		phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
58266ab6bfe3SJack F Vogel 		hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
58274dab5c37SJack F Vogel release:
58286ab6bfe3SJack F Vogel 		if (ret_val)
58296ab6bfe3SJack F Vogel 			DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
58304dab5c37SJack F Vogel 		hw->phy.ops.release(hw);
5831c80429ceSEric Joyner 		return ret_val;
58326ab6bfe3SJack F Vogel 	}
5833c80429ceSEric Joyner 	return E1000_SUCCESS;
58344dab5c37SJack F Vogel }
58354dab5c37SJack F Vogel 
58364dab5c37SJack F Vogel /**
58378cfa0ad2SJack F Vogel  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
58388cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
58398cfa0ad2SJack F Vogel  *
58408cfa0ad2SJack F Vogel  *  Return the LED back to the default configuration.
58418cfa0ad2SJack F Vogel  **/
58428cfa0ad2SJack F Vogel static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
58438cfa0ad2SJack F Vogel {
58448cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_cleanup_led_ich8lan");
58458cfa0ad2SJack F Vogel 
58468cfa0ad2SJack F Vogel 	if (hw->phy.type == e1000_phy_ife)
5847a69ed8dfSJack F Vogel 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
58488cfa0ad2SJack F Vogel 					     0);
58498cfa0ad2SJack F Vogel 
5850a69ed8dfSJack F Vogel 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5851a69ed8dfSJack F Vogel 	return E1000_SUCCESS;
58528cfa0ad2SJack F Vogel }
58538cfa0ad2SJack F Vogel 
58548cfa0ad2SJack F Vogel /**
58558cfa0ad2SJack F Vogel  *  e1000_led_on_ich8lan - Turn LEDs on
58568cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
58578cfa0ad2SJack F Vogel  *
58588cfa0ad2SJack F Vogel  *  Turn on the LEDs.
58598cfa0ad2SJack F Vogel  **/
58608cfa0ad2SJack F Vogel static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
58618cfa0ad2SJack F Vogel {
58628cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_led_on_ich8lan");
58638cfa0ad2SJack F Vogel 
58648cfa0ad2SJack F Vogel 	if (hw->phy.type == e1000_phy_ife)
5865a69ed8dfSJack F Vogel 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
58668cfa0ad2SJack F Vogel 				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
58678cfa0ad2SJack F Vogel 
5868a69ed8dfSJack F Vogel 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5869a69ed8dfSJack F Vogel 	return E1000_SUCCESS;
58708cfa0ad2SJack F Vogel }
58718cfa0ad2SJack F Vogel 
58728cfa0ad2SJack F Vogel /**
58738cfa0ad2SJack F Vogel  *  e1000_led_off_ich8lan - Turn LEDs off
58748cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
58758cfa0ad2SJack F Vogel  *
58768cfa0ad2SJack F Vogel  *  Turn off the LEDs.
58778cfa0ad2SJack F Vogel  **/
58788cfa0ad2SJack F Vogel static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
58798cfa0ad2SJack F Vogel {
58808cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_led_off_ich8lan");
58818cfa0ad2SJack F Vogel 
58828cfa0ad2SJack F Vogel 	if (hw->phy.type == e1000_phy_ife)
5883a69ed8dfSJack F Vogel 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
58848cfa0ad2SJack F Vogel 			       (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
58858cfa0ad2SJack F Vogel 
5886a69ed8dfSJack F Vogel 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5887a69ed8dfSJack F Vogel 	return E1000_SUCCESS;
58888cfa0ad2SJack F Vogel }
58898cfa0ad2SJack F Vogel 
58908cfa0ad2SJack F Vogel /**
58919d81738fSJack F Vogel  *  e1000_setup_led_pchlan - Configures SW controllable LED
58929d81738fSJack F Vogel  *  @hw: pointer to the HW structure
58939d81738fSJack F Vogel  *
58949d81738fSJack F Vogel  *  This prepares the SW controllable LED for use.
58959d81738fSJack F Vogel  **/
58969d81738fSJack F Vogel static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
58979d81738fSJack F Vogel {
58989d81738fSJack F Vogel 	DEBUGFUNC("e1000_setup_led_pchlan");
58999d81738fSJack F Vogel 
59009d81738fSJack F Vogel 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
59019d81738fSJack F Vogel 				     (u16)hw->mac.ledctl_mode1);
59029d81738fSJack F Vogel }
59039d81738fSJack F Vogel 
59049d81738fSJack F Vogel /**
59059d81738fSJack F Vogel  *  e1000_cleanup_led_pchlan - Restore the default LED operation
59069d81738fSJack F Vogel  *  @hw: pointer to the HW structure
59079d81738fSJack F Vogel  *
59089d81738fSJack F Vogel  *  Return the LED back to the default configuration.
59099d81738fSJack F Vogel  **/
59109d81738fSJack F Vogel static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
59119d81738fSJack F Vogel {
59129d81738fSJack F Vogel 	DEBUGFUNC("e1000_cleanup_led_pchlan");
59139d81738fSJack F Vogel 
59149d81738fSJack F Vogel 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
59159d81738fSJack F Vogel 				     (u16)hw->mac.ledctl_default);
59169d81738fSJack F Vogel }
59179d81738fSJack F Vogel 
59189d81738fSJack F Vogel /**
59199d81738fSJack F Vogel  *  e1000_led_on_pchlan - Turn LEDs on
59209d81738fSJack F Vogel  *  @hw: pointer to the HW structure
59219d81738fSJack F Vogel  *
59229d81738fSJack F Vogel  *  Turn on the LEDs.
59239d81738fSJack F Vogel  **/
59249d81738fSJack F Vogel static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
59259d81738fSJack F Vogel {
59269d81738fSJack F Vogel 	u16 data = (u16)hw->mac.ledctl_mode2;
59279d81738fSJack F Vogel 	u32 i, led;
59289d81738fSJack F Vogel 
59299d81738fSJack F Vogel 	DEBUGFUNC("e1000_led_on_pchlan");
59309d81738fSJack F Vogel 
59316ab6bfe3SJack F Vogel 	/* If no link, then turn LED on by setting the invert bit
59329d81738fSJack F Vogel 	 * for each LED that's mode is "link_up" in ledctl_mode2.
59339d81738fSJack F Vogel 	 */
59349d81738fSJack F Vogel 	if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
59359d81738fSJack F Vogel 		for (i = 0; i < 3; i++) {
59369d81738fSJack F Vogel 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
59379d81738fSJack F Vogel 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
59389d81738fSJack F Vogel 			    E1000_LEDCTL_MODE_LINK_UP)
59399d81738fSJack F Vogel 				continue;
59409d81738fSJack F Vogel 			if (led & E1000_PHY_LED0_IVRT)
59419d81738fSJack F Vogel 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
59429d81738fSJack F Vogel 			else
59439d81738fSJack F Vogel 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
59449d81738fSJack F Vogel 		}
59459d81738fSJack F Vogel 	}
59469d81738fSJack F Vogel 
59479d81738fSJack F Vogel 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
59489d81738fSJack F Vogel }
59499d81738fSJack F Vogel 
59509d81738fSJack F Vogel /**
59519d81738fSJack F Vogel  *  e1000_led_off_pchlan - Turn LEDs off
59529d81738fSJack F Vogel  *  @hw: pointer to the HW structure
59539d81738fSJack F Vogel  *
59549d81738fSJack F Vogel  *  Turn off the LEDs.
59559d81738fSJack F Vogel  **/
59569d81738fSJack F Vogel static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
59579d81738fSJack F Vogel {
59589d81738fSJack F Vogel 	u16 data = (u16)hw->mac.ledctl_mode1;
59599d81738fSJack F Vogel 	u32 i, led;
59609d81738fSJack F Vogel 
59619d81738fSJack F Vogel 	DEBUGFUNC("e1000_led_off_pchlan");
59629d81738fSJack F Vogel 
59636ab6bfe3SJack F Vogel 	/* If no link, then turn LED off by clearing the invert bit
59649d81738fSJack F Vogel 	 * for each LED that's mode is "link_up" in ledctl_mode1.
59659d81738fSJack F Vogel 	 */
59669d81738fSJack F Vogel 	if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
59679d81738fSJack F Vogel 		for (i = 0; i < 3; i++) {
59689d81738fSJack F Vogel 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
59699d81738fSJack F Vogel 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
59709d81738fSJack F Vogel 			    E1000_LEDCTL_MODE_LINK_UP)
59719d81738fSJack F Vogel 				continue;
59729d81738fSJack F Vogel 			if (led & E1000_PHY_LED0_IVRT)
59739d81738fSJack F Vogel 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
59749d81738fSJack F Vogel 			else
59759d81738fSJack F Vogel 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
59769d81738fSJack F Vogel 		}
59779d81738fSJack F Vogel 	}
59789d81738fSJack F Vogel 
59799d81738fSJack F Vogel 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
59809d81738fSJack F Vogel }
59819d81738fSJack F Vogel 
59829d81738fSJack F Vogel /**
59837d9119bdSJack F Vogel  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
59848cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
59858cfa0ad2SJack F Vogel  *
59867d9119bdSJack F Vogel  *  Read appropriate register for the config done bit for completion status
59877d9119bdSJack F Vogel  *  and configure the PHY through s/w for EEPROM-less parts.
59887d9119bdSJack F Vogel  *
59897d9119bdSJack F Vogel  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
59907d9119bdSJack F Vogel  *  config done bit, so only an error is logged and continues.  If we were
59917d9119bdSJack F Vogel  *  to return with error, EEPROM-less silicon would not be able to be reset
59927d9119bdSJack F Vogel  *  or change link.
59938cfa0ad2SJack F Vogel  **/
59948cfa0ad2SJack F Vogel static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
59958cfa0ad2SJack F Vogel {
59968cfa0ad2SJack F Vogel 	s32 ret_val = E1000_SUCCESS;
59978cfa0ad2SJack F Vogel 	u32 bank = 0;
59987d9119bdSJack F Vogel 	u32 status;
59998cfa0ad2SJack F Vogel 
60007d9119bdSJack F Vogel 	DEBUGFUNC("e1000_get_cfg_done_ich8lan");
60019d81738fSJack F Vogel 
60028cfa0ad2SJack F Vogel 	e1000_get_cfg_done_generic(hw);
60038cfa0ad2SJack F Vogel 
60047d9119bdSJack F Vogel 	/* Wait for indication from h/w that it has completed basic config */
60057d9119bdSJack F Vogel 	if (hw->mac.type >= e1000_ich10lan) {
60067d9119bdSJack F Vogel 		e1000_lan_init_done_ich8lan(hw);
60077d9119bdSJack F Vogel 	} else {
60087d9119bdSJack F Vogel 		ret_val = e1000_get_auto_rd_done_generic(hw);
60097d9119bdSJack F Vogel 		if (ret_val) {
60106ab6bfe3SJack F Vogel 			/* When auto config read does not complete, do not
60117d9119bdSJack F Vogel 			 * return with an error. This can happen in situations
60127d9119bdSJack F Vogel 			 * where there is no eeprom and prevents getting link.
60137d9119bdSJack F Vogel 			 */
60147d9119bdSJack F Vogel 			DEBUGOUT("Auto Read Done did not complete\n");
60157d9119bdSJack F Vogel 			ret_val = E1000_SUCCESS;
60167d9119bdSJack F Vogel 		}
60177d9119bdSJack F Vogel 	}
60187d9119bdSJack F Vogel 
60197d9119bdSJack F Vogel 	/* Clear PHY Reset Asserted bit */
60207d9119bdSJack F Vogel 	status = E1000_READ_REG(hw, E1000_STATUS);
60217d9119bdSJack F Vogel 	if (status & E1000_STATUS_PHYRA)
60227d9119bdSJack F Vogel 		E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
60237d9119bdSJack F Vogel 	else
60247d9119bdSJack F Vogel 		DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
60257d9119bdSJack F Vogel 
60268cfa0ad2SJack F Vogel 	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
60274edd8523SJack F Vogel 	if (hw->mac.type <= e1000_ich9lan) {
60286ab6bfe3SJack F Vogel 		if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
60298cfa0ad2SJack F Vogel 		    (hw->phy.type == e1000_phy_igp_3)) {
60308cfa0ad2SJack F Vogel 			e1000_phy_init_script_igp3(hw);
60318cfa0ad2SJack F Vogel 		}
60328cfa0ad2SJack F Vogel 	} else {
60338cfa0ad2SJack F Vogel 		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6034daf9197cSJack F Vogel 			/* Maybe we should do a basic PHY config */
60358cfa0ad2SJack F Vogel 			DEBUGOUT("EEPROM not present\n");
60368cfa0ad2SJack F Vogel 			ret_val = -E1000_ERR_CONFIG;
60378cfa0ad2SJack F Vogel 		}
60388cfa0ad2SJack F Vogel 	}
60398cfa0ad2SJack F Vogel 
60408cfa0ad2SJack F Vogel 	return ret_val;
60418cfa0ad2SJack F Vogel }
60428cfa0ad2SJack F Vogel 
60438cfa0ad2SJack F Vogel /**
60448cfa0ad2SJack F Vogel  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
60458cfa0ad2SJack F Vogel  * @hw: pointer to the HW structure
60468cfa0ad2SJack F Vogel  *
60478cfa0ad2SJack F Vogel  * In the case of a PHY power down to save power, or to turn off link during a
60488cfa0ad2SJack F Vogel  * driver unload, or wake on lan is not enabled, remove the link.
60498cfa0ad2SJack F Vogel  **/
60508cfa0ad2SJack F Vogel static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
60518cfa0ad2SJack F Vogel {
60528cfa0ad2SJack F Vogel 	/* If the management interface is not enabled, then power down */
6053daf9197cSJack F Vogel 	if (!(hw->mac.ops.check_mng_mode(hw) ||
6054daf9197cSJack F Vogel 	      hw->phy.ops.check_reset_block(hw)))
60558cfa0ad2SJack F Vogel 		e1000_power_down_phy_copper(hw);
60568cfa0ad2SJack F Vogel 
60578cfa0ad2SJack F Vogel 	return;
60588cfa0ad2SJack F Vogel }
60598cfa0ad2SJack F Vogel 
60608cfa0ad2SJack F Vogel /**
60618cfa0ad2SJack F Vogel  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
60628cfa0ad2SJack F Vogel  *  @hw: pointer to the HW structure
60638cfa0ad2SJack F Vogel  *
60648cfa0ad2SJack F Vogel  *  Clears hardware counters specific to the silicon family and calls
60658cfa0ad2SJack F Vogel  *  clear_hw_cntrs_generic to clear all general purpose counters.
60668cfa0ad2SJack F Vogel  **/
60678cfa0ad2SJack F Vogel static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
60688cfa0ad2SJack F Vogel {
60699d81738fSJack F Vogel 	u16 phy_data;
60704dab5c37SJack F Vogel 	s32 ret_val;
60719d81738fSJack F Vogel 
60728cfa0ad2SJack F Vogel 	DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
60738cfa0ad2SJack F Vogel 
60748cfa0ad2SJack F Vogel 	e1000_clear_hw_cntrs_base_generic(hw);
60758cfa0ad2SJack F Vogel 
6076daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_ALGNERRC);
6077daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_RXERRC);
6078daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_TNCRS);
6079daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_CEXTERR);
6080daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_TSCTC);
6081daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_TSCTFC);
60828cfa0ad2SJack F Vogel 
6083daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_MGTPRC);
6084daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_MGTPDC);
6085daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_MGTPTC);
60868cfa0ad2SJack F Vogel 
6087daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_IAC);
6088daf9197cSJack F Vogel 	E1000_READ_REG(hw, E1000_ICRXOC);
60899d81738fSJack F Vogel 
60909d81738fSJack F Vogel 	/* Clear PHY statistics registers */
60919d81738fSJack F Vogel 	if ((hw->phy.type == e1000_phy_82578) ||
60927d9119bdSJack F Vogel 	    (hw->phy.type == e1000_phy_82579) ||
60936ab6bfe3SJack F Vogel 	    (hw->phy.type == e1000_phy_i217) ||
60949d81738fSJack F Vogel 	    (hw->phy.type == e1000_phy_82577)) {
60954dab5c37SJack F Vogel 		ret_val = hw->phy.ops.acquire(hw);
60964dab5c37SJack F Vogel 		if (ret_val)
60974dab5c37SJack F Vogel 			return;
60984dab5c37SJack F Vogel 		ret_val = hw->phy.ops.set_page(hw,
60994dab5c37SJack F Vogel 					       HV_STATS_PAGE << IGP_PAGE_SHIFT);
61004dab5c37SJack F Vogel 		if (ret_val)
61014dab5c37SJack F Vogel 			goto release;
61024dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
61034dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
61044dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
61054dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
61064dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
61074dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
61084dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
61094dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
61104dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
61114dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
61124dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
61134dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
61144dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
61154dab5c37SJack F Vogel 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
61164dab5c37SJack F Vogel release:
61174dab5c37SJack F Vogel 		hw->phy.ops.release(hw);
61189d81738fSJack F Vogel 	}
61198cfa0ad2SJack F Vogel }
61208cfa0ad2SJack F Vogel 
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