1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2015, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #ifndef _E1000_I210_H_ 37 #define _E1000_I210_H_ 38 39 bool e1000_get_flash_presence_i210(struct e1000_hw *hw); 40 s32 e1000_update_flash_i210(struct e1000_hw *hw); 41 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw); 42 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw); 43 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, 44 u16 words, u16 *data); 45 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, 46 u16 words, u16 *data); 47 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, 48 u16 *data); 49 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, 50 u16 data); 51 s32 e1000_init_hw_i210(struct e1000_hw *hw); 52 53 #define E1000_STM_OPCODE 0xDB00 54 #define E1000_EEPROM_FLASH_SIZE_WORD 0x11 55 56 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \ 57 (u8)((invm_dword) & 0x7) 58 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \ 59 (u8)(((invm_dword) & 0x0000FE00) >> 9) 60 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \ 61 (u16)(((invm_dword) & 0xFFFF0000) >> 16) 62 63 enum E1000_INVM_STRUCTURE_TYPE { 64 E1000_INVM_UNINITIALIZED_STRUCTURE = 0x00, 65 E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 0x01, 66 E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 0x02, 67 E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 0x03, 68 E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 0x04, 69 E1000_INVM_INVALIDATED_STRUCTURE = 0x0F, 70 }; 71 72 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 73 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 74 #define E1000_INVM_ULT_BYTES_SIZE 8 75 #define E1000_INVM_RECORD_SIZE_IN_BYTES 4 76 #define E1000_INVM_VER_FIELD_ONE 0x1FF8 77 #define E1000_INVM_VER_FIELD_TWO 0x7FE000 78 #define E1000_INVM_IMGTYPE_FIELD 0x1F800000 79 80 #define E1000_INVM_MAJOR_MASK 0x3F0 81 #define E1000_INVM_MINOR_MASK 0xF 82 #define E1000_INVM_MAJOR_SHIFT 4 83 84 #define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \ 85 (ID_LED_DEF1_DEF2 << 4) | \ 86 (ID_LED_OFF1_OFF2)) 87 #define ID_LED_DEFAULT_I210_SERDES ((ID_LED_DEF1_DEF2 << 8) | \ 88 (ID_LED_DEF1_DEF2 << 4) | \ 89 (ID_LED_OFF1_ON2)) 90 91 /* NVM offset defaults for I211 devices */ 92 #define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243 93 #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1 94 #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 95 #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C 96 97 /* PLL Defines */ 98 #define E1000_PCI_PMCSR 0x44 99 #define E1000_PCI_PMCSR_D3 0x03 100 #define E1000_MAX_PLL_TRIES 5 101 #define E1000_PHY_PLL_UNCONF 0xFF 102 #define E1000_PHY_PLL_FREQ_PAGE 0xFC0000 103 #define E1000_PHY_PLL_FREQ_REG 0x000E 104 #define E1000_INVM_DEFAULT_AL 0x202F 105 #define E1000_INVM_AUTOLOAD 0x0A 106 #define E1000_INVM_PLL_WO_VAL 0x0010 107 108 #endif 109